PSoC® Creator™ Component Datasheet
Sequencing Successive Approximation ADC
(ADC_SAR_Seq)
2.0
Features
Supports PSoC 5LP devices
Selectable resolution (8, 10 or 12 bit) and sample rate
(up to 1 Msps)
Scans up to 64 single ended or 32 differential channels
automatically, or just a single input
Note Only GPIOs can be connected to the channel inputs. The
actual maximum number of input channels depends on the
number of routable analog GPIOs available on a specific PSoC
part and package.
General Description
The Sequencing SAR ADC component enables makes it possible for you to configure and then
use the different operational modes of the SAR ADC on PSoC 5LP. You also have schematic
level and firmware level support for seamless use of the Sequencing SAR ADC in PSoC Creator
designs and projects. You are able to configure multiple analog channels that are automatically
scanned with the results placed in individual SRAM locations.
When to Use the ADC_SAR_Seq
The Sequencing SAR ADC is commonly used in high sample rate systems where multiple
channels must be sampled without CPU intervention until all channels are sampled.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-96232 Rev. *C
Revised December 16, 2015
Sequencing Successive Approximation ADC (ADC_SAR_Seq)
PSoC® Creator™ Component Datasheet
Input/Output Connections
This section describes the input and output connections for the ADC_SAR_Seq. An asterisk (*)
in the list of I/Os indicates that the I/O may be hidden on the symbol under the conditions listed
in the description of that I/O.
Differential Inputs
Single-ended inputs
Differential inputs – 1 channel
(sdone is visible)
+Input – Analog
This input is the positive analog signal input to the ADC_SAR_Seq. The conversion result is a
function of the +Input signal minus the voltage reference. The voltage reference is either the
Input signal or VSSA.
–Input – Analog *
When shown, this optional input is the negative analog signal (or reference) input to the
ADC_SAR_Seq. The conversion result is a function of +Input minus –Input. You see this pin
when you set the Input Range parameter to one of the differential modes.
vdac_ref – Input *
The VDAC reference (vdac_ref) is an optional pin. To see it, select Vssa to VDAC*2 (Single
Ended) or 0.0 +/- VDAC (Differential) input range; otherwise, this I/O is hidden.
Note You can only connect this pin to a VDAC component output. Do not connect it to any other
signal.
soc – Input *
The start of conversion (soc) is an optional pin. You see it if you select the Hardware trigger
sample mode. A rising edge on this input starts an ADC conversion. The first soc rising edge
should be generated at least 10 us after the component is started to guarantee reference and
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PSoC® Creator™ Component Datasheet
Sequencing Successive Approximation ADC (ADC_SAR_Seq)
pump voltage stability. You can connect the output of a PWM component to this input. It can also
be connected to any GPIO pin or a UDB. This signal should be synchronized to the
ADC_SAR_Seq clock and must be at least one ADC_SAR_Seq clock cycle wide.
This input is hidden if you set the Sample Mode parameter to Free-running or Software
trigger.
aclk – Input *
You see this optional pin if you set the Clock Source parameter to External; otherwise, the pin
is hidden. This clock determines the conversion rate as a function of the conversion method and
resolution.
eoc – Output
A rising edge on the end of conversion (eoc) output means that one conversion cycle is
complete. At this moment, conversion results for all channels are ready to be read from the
SRAM. An internal interrupt is also connected to this signal, or you may connect your own
interrupt.
sdone – Output *
A rising edge on this output means that sampling is complete. This is a direct connection from
EOS output of the ADC SAR component. This signal is only visible when the component is
configured for one channel operation.
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PSoC® Creator™ Component Datasheet
Component Parameters
Drag an ADC_SAR_Seq component onto your design and double-click it to open the Configure
dialog.
The ADC_SAR_Seq has the following parameters. The option shown in bold is the default.
Timing
Resolution (bits)
Sets the resolution of the ADC_SAR_Seq.
Resolution
Description
12
Sets resolution to 12 bits
10
Sets resolution to 10 bits
8
Sets resolution to 8 bits
Sample Rate (SPS)
This parameter shows the sample rate in samples per second (SPS) for all channels. It is
automatically calculated based on the clock frequency and number of channels. Channel Sample
Rate is shown near the Channels numeric up-down control.
The actual sample rate may differ based on the available clock speed and divider range. It is
shown on the right side from selected sample rate.
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Sequencing Successive Approximation ADC (ADC_SAR_Seq)
The actual sample rate also depends on a sample mode and availability of the data bus for DMA
transfer. Refer to the Functional Description section for details on how to calculate the number of
clocks required for sampling.
Clock Frequency (kHz)
This text box is read-only by default (always grayed out) that displays the required clock rate for
the selected operating conditions: resolution and conversion rate. It is updated when either or
both of these conditions change. It can be changed if Clock Source is set to Internal. Clock
frequency can be anywhere between 1 MHz and 18 MHz. The duty cycle should be 50 percent.
Make the minimum pulse width greater than 25.5 ns. PSoC Creator generates an error during
the build process if the clock does not fall within these limits. In there is an error, change the
Master Clock in the Design-Wide Resources Clock Editor.
Sample mode
This parameter determines how the ADC operates.
SampleMode
Description
Free Running
ADC_SAR_Seq runs continuously. Use the ADC_SAR_Seq_StartConvert() function to
start and the ADC_SAR_Seq_StopConvert() function to stop continuous conversions.
Software trigger
Calling of the ADC_SAR_Seq_StartConvert() starts a single cycle of conversion for all
channels
Hardware trigger
A rising-edge pulse on the SOC pin starts a single cycle of conversion for all channels
Input
Input Range
This parameter configures the ADC for a given input range. The analog signals connected to the
PSoC must be between VSSA and VDDA regardless of the input range settings.
InputRange
0.0 to 2.048V (Single Ended)
0 to Vref*2
Description
When using the internal reference (1.024 V), the usable input range is 0.0 to
2.048 V. The ADC is configured to operate in a single-ended input mode with
–Input connected internally to Vrefhi_out. If you are using an external reference
voltage, the usable input range is 0.0 to Vref*2.
Vssa to Vdda (Single Ended)
This mode uses the VDDA/2 reference; the usable input range covers the full
analog supply voltage. The ADC is put in a single-ended input mode with –Input
connected internally to Vrefhi_out. If you are using an external reference
voltage, the usable input range is 0.0 to Vref*2.
Vssa to VDAC*2 (Single Ended)
This mode uses the VDAC reference, which should be connected to the
vdac_ref pin. The usable input range is Vssa to VDAC*2 volts. The ADC is
configured to operate in a single-ended input mode with –Input connected
internally to Vrefhi_out.
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Sequencing Successive Approximation ADC (ADC_SAR_Seq)
InputRange
0.0 ± 1.024V (Differential)
–Input ± Vref
PSoC® Creator™ Component Datasheet
Description
This mode is configured for differential inputs. When using the internal
reference (1.024 V), the input range is –Input ± 1.024 V.
For example, if –Input is connected to 2.048 V, the usable input range is 2.048
± 1.024 V or 1.024 to 3.072 V. For systems in which both single-ended and
differential signals are scanned, connect –Input to Vssa when scanning a
single-ended input.
You can use an external reference to provide a wider operating range. You can
calculate the usable input range with the same equation, –Input ± Vref.
0.0 ± Vdda (Differential)
–Input ± Vdda
0.0 ± Vdda/2 (Differential)
–Input ± Vdda/2
0.0 ± VDAC (Differential)
–Input ± VDAC
This mode is configured for differential inputs and is ratiometric with the supply
voltage. The input range is –Input ± Vdda. For systems in which both singleended and differential signals are scanned, connect –Input to Vssa when
scanning a single-ended input. If you are using an external reference voltage,
the usable input range is –Input ± Vref.
This mode is configured for differential inputs and is ratiometric to the supply
voltage. The input range is –Input ± Vdda/2. For systems in which both singleended and differential signals are scanned, connect –Input to Vssa when
scanning a single-ended input. If you are using an external reference voltage,
the usable input range is –Input ± Vref.
This mode is configured for differential inputs and uses the VDAC reference,
which should be connected to the vdac_ref pin. The input range is
–Input ±VDAC. For systems in which both single-ended and differential signals
are scanned, connect –Input to Vssa when scanning a single-ended input.
Reference
This parameter selects the switches for reference configuration for the ADC_SAR.
ADC_Reference
Allowed Clock
Frequency (MHz)
Internal Vref
1 ~ 1.6 MHz
Description
Uses the internal reference. This clock frequency range is valid with all
input ranges except “0.0 ± Vdda”.
Uses the Internal Vref, bypassed option for higher clock frequency.
1
1 ~ 9 MHz
Uses the internal reference. This clock frequency range is valid with “0.0 ±
Vdda” input range.
Internal Vref,
bypassed
1 ~ 18 MHz
Uses the internal reference. You must place a bypass capacitor on pin
P0[2] [1] for SAR1 or on pin P0[4] [1] for SAR0. This mode is not applicable
with “0.0 ± Vdda” input range.
External Vref
1 ~ 18 MHz
Uses an external reference on pin P0[2] for SAR1 or on pin P0[4] for
SAR0.
The use of an external bypass capacitor is recommended if the internal noise caused by digital switching
exceeds an application's analog performance requirements. To use this option, configure either port pin P0[2] or
P0[4] as an analog HI-Z pin and connect an external capacitor with a value between 0.01 µF and 10 µF.
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PSoC® Creator™ Component Datasheet
Sequencing Successive Approximation ADC (ADC_SAR_Seq)
Note The same internal reference is used for ADC_SAR and for ADC_DelSig components. If
both types of the ADC need to work with an internal reference simultaneously, use the Internal
Vref, bypassed option for the best performance.
Voltage Reference
The voltage reference is used for the ADC count to voltage conversion functions that is
discussed in the Application Programming Interface section. This parameter is read-only when
using the internal reference. When using an external reference, change this value to match the
external reference voltage.
When selecting input range Vssa to Vdda, -Input +/- Vdda, or -Input +/- Vdda/2, the
value is derived from the VDDA setting in System tab of the Design Wide Resources
(DWR).
When selecting the input range Vssa to VDAC*2 or –Input +/- VDAC, type the VDAC
supply voltage value.
Note The input range and reference voltage is limited by the VDDA voltage.
Clock Source
This parameter allows you to select either a clock that is internal to the ADC_SAR_Seq module
or an external clock.
ADC_Clock
Description
Internal
Use the internal clock of the ADC_SAR_Seq
External
Use an external clock. The clock source can be analog, digital, or generated by
another component.
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PSoC® Creator™ Component Datasheet
Application Programming Interface
Application Programming Interface (API) routines allow you to configure the component using
software. This table lists and describes the interface to each function. The following sections
discuss each function in more detail.
By default, PSoC Creator assigns the instance name “ ADC_SAR_Seq_1” to the first instance of
a component in a given design. You can rename the instance to any unique value that follows
the syntactic rules for identifiers. The instance name becomes the prefix of every global function
name, variable, and constant symbol. For readability, the instance name used in the following
table is “ADC_SAR_Seq”.
Functions
Function
Description
ADC_SAR_Seq_Start()
Powers up the ADC_SAR_Seq and resets all states
ADC_SAR_Seq_Stop()
Stops ADC_SAR_Seq conversions and reduces the power to the minimum
ADC_SAR_Seq_SetResolution()
Sets the resolution of the ADC_SAR_Seq
ADC_SAR_Seq_StartConvert()
Starts conversions
ADC_SAR_Seq_StopConvert()
Stops conversions
ADC_SAR_Seq_IRQ_Enable()
An internal IRQ is connected to the eoc. This API enables the internal ISR
ADC_SAR_Seq_IRQ_Disable()
An internal IRQ is connected to the eoc. This API disables the internal ISR
ADC_SAR_Seq_IsEndConversion()
Returns a nonzero value if conversion is complete
ADC_SAR_Seq_GetAdcResult()
Returns a signed 16-bit conversion result available in the ADC SAR Data
Register not the result buffer
ADC_SAR_Seq_GetResult16()
Returns a signed16-bit conversion result for specified channel
ADC_SAR_Seq_SetOffset()
Sets the offset of the ADC_SAR_Seq
ADC_SAR_Seq_SetScaledGain()
Sets the ADC_SAR_Seq gain in counts per 10 volts
ADC_SAR_Seq _CountsTo_Volts()
Converts ADC_SAR_Seq counts to floating-point volts
ADC_SAR_Seq_CountsTo_mVolts() Converts ADC_SAR_Seq counts to millivolts
ADC_SAR_Seq_CountsTo_uVolts()
Converts ADC_SAR_Seq counts to microvolts
ADC_SAR_Seq_Sleep()
Stops ADC_SAR_Seq operation and saves the user configuration
ADC_SAR_Seq_Wakeup()
Restores and enables the user configuration
ADC_SAR_Seq_Init()
Initializes the default configuration provided with the customizer
ADC_SAR_Seq_Enable()
Enables the clock and power for the ADC_SAR_Seq
ADC_SAR_Seq_SaveConfig()
Saves the current user configuration
ADC_SAR_Seq_RestoreConfig()
Restores the user configuration
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PSoC® Creator™ Component Datasheet
Sequencing Successive Approximation ADC (ADC_SAR_Seq)
void ADC_SAR_Seq_Start(void)
Description:
This is the preferred method to begin component operation. ADC_SAR_Seq_Start() sets the
initVar variable, calls the ADC_SAR_Seq _Init() function, and then calls the
ADC_SAR_Seq_Enable() function. It is not recommended to call this API a second time
without stopping the component first.
Parameters:
None
Return Value:
None
Side Effects:
If the initVar variable is already set, this function only calls the ADC_SAR_Seq_Enable()
function.
void ADC_SAR_Seq_Stop(void)
Description:
Stops ADC_SAR_Seq conversions and reduces the power to the minimum.
Note This API does not power down the ADC, but reduces power to a minimum level. This
device has a defect that causes connections to several analog resources to be unreliable
when the device is not powered. The unreliability manifests itself in silent failures (for
example, unpredictable bad results from analog components) when the component using
that resource is stopped.
Parameters:
None
Return Value:
None
Side Effects:
None
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PSoC® Creator™ Component Datasheet
Sequencing Successive Approximation ADC (ADC_SAR_Seq)
void ADC_SAR_Seq_SetResolution(uint8 resolution)
Description:
Sets the resolution for the GetResult16() and GetAdcResult() APIs.
Parameters:
uint8 resolution: Resolution setting
Parameters Name
Value
Description
ADC_SAR_Seq_ADC_BITS_12
12
Sets resolution to 12 bits.
ADC_SAR_Seq_ADC_BITS_10
10
Sets resolution to 10 bits.
ADC_SAR_Seq_ADC_BITS_8
8
Sets resolution to 8 bits.
Return Value:
None
Side Effects:
You cannot change the ADC resolution during a conversion cycle. The recommended best
practice is to stop conversions with ADC_SAR_SeqStopConvert(), change the resolution,
then restart the conversions with ADC_SAR_Seq_StartConvert().
If you decide not to stop conversions before calling this API, use
ADC_SAR_Seq_IsEndConversion() to wait until conversion is complete before changing the
resolution.
If you call ADC_SAR_Seq_SetResolution() during a conversion, the resolution does not
change until the current conversion is complete. Data will not be available in the new
resolution for another 6 + “New Resolution(in bits)” clock cycles. You may need add a delay
of this number of clock cycles after ADC_SAR_Seq_SetResolution() is called before data is
valid again.
Affects ADC_SAR_Seq_CountsTo_Volts(), ADC_SAR_Seq_CountsTo_mVolts(), and
ADC_SAR_Seq_CountsTo_uVolts() by calculating the correct conversion between
ADC_SAR_Seq counts and the applied input voltage. Calculation depends on resolution,
input range, and voltage reference.
void ADC_SAR_Seq_StartConvert(void)
Description:
This forces the ADC to initiate a conversion. In free-running mode, the ADC_SAR_Seq runs
continuously. In software trigger mode, the function also acts as a software version of the
SOC and every conversion must be triggered by ADC_SAR_Seq_StartConvert(). In
Hardware trigger mode this function is unavailable.
Parameters:
None
Return Value:
None
Side Effects:
Calling ADC_SAR_Seq_StartConvert() disables the external SOC pin.
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PSoC® Creator™ Component Datasheet
Sequencing Successive Approximation ADC (ADC_SAR_Seq)
void ADC_SAR_Seq_StopConvert(void)
Description:
This forces the ADC_SAR_Seq to stop conversions. If a conversion is currently executing,
that conversion completes, but no further conversions happen. This only applies to freerunning mode.
Parameters:
None
Return Value:
None
Side Effects:
In free-running and software trigger mode, this function sets a software version of the SOC
to low level and switches the SOC source to hardware SOC input (Hardware trigger).
void ADC_SAR_Seq_IRQ_Enable(void)
Description:
This enables interrupts to occur at the end of a conversion. Global interrupts must also be
enabled for the ADC interrupts to occur. To enable global interrupts, call the enable global
interrupt macro “CyGlobalIntEnable;” in your main.c file before enabling any interrupts.
Parameters:
None
Return Value:
None
Side Effects:
Enables interrupts to occur. Reading the result clears the interrupt.
void ADC_SAR_Seq_IRQ_Disable(void)
Description:
Disables interrupts at the end of a conversion.
Parameters:
None
Return Value:
None
Side Effects:
None
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PSoC® Creator™ Component Datasheet
Sequencing Successive Approximation ADC (ADC_SAR_Seq)
uint32 ADC_SAR_Seq_IsEndConversion(uint8 retMode)
Description:
Immediately returns the status of the conversion or does not return (blocking) until the
conversion completes, depending on the retMode parameter.
Parameters:
uint8 retMode: Check conversion return mode. This table describes the available options.
Options
ADC_SAR_Seq_RETURN_STATUS
Description
Immediately returns the status. If the value
returned is zero, the conversion is
incomplete, and this function should be
retried until a nonzero result is returned.
ADC_SAR_Seq_WAIT_FOR_RESULT Does not return a result until the
ADC_SAR_Seq conversion is complete.
Return Value:
uint32: If a nonzero value is returned, the last conversion is complete. If the returned value is
zero, the ADC_SAR_Seq is still calculating the last result.
Side Effects:
This function reads the end of conversion status, which is cleared on read.
int16 ADC_SAR_Seq_GetAdcResult(void)
Description:
Gets the data available in the SAR DATA register, not the results buffer.
Parameters:
None
Return Value:
int16: The last ADC conversion result.
Side Effects:
Converts the ADC counts to the 2’s complement form.
int16 ADC_SAR_Seq_GetResult16(uint16 chan)
Description:
Returns the conversion result for channel “chan”.
Parameters:
uint16 chan: The ADC channel in which to return the result. The first channel is 0 and the
last channel is the total number of channels – 1.
Return Value:
int16: Returns converted data as a signed 16-bit integer
Side Effects:
Converts the ADC counts to the 2’s complement form.
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PSoC® Creator™ Component Datasheet
Sequencing Successive Approximation ADC (ADC_SAR_Seq)
void ADC_SAR_Seq_SetOffset(int32 offset)
Description:
Sets the ADC_SAR_Seq offset, which is used by ADC_SAR_Seq_CountsTo_Volts(),
ADC_SAR_Seq_CountsTo_mVolts(), and ADC_SAR_Seq_CountsTo_uVolts(), to
subtract the offset from the given reading before calculating the voltage conversion.
Parameters:
int32 offset: This value is measured when the inputs are shorted or connected to the
same input voltage.
Return Value:
None
Side Effects:
Affects ADC_SAR_Seq_CountsTo_Volts(), ADC_SAR_Seq_CountsTo_mVolts(), and
ADC_SAR_Seq_CountsTo_uVolts() by subtracting the given offset.
void ADC_SAR_Seq_SetScaledGain(int32 adcGain)
Description:
Sets the ADC_SAR_Seq gain in counts per 10 volts for the voltage conversion functions
that follow. This value is set by default by the reference and input range settings. It should
only be used to further calibrate the ADC_SAR_Seq with a known input or if the
ADC_SAR_Seq is using an external reference. To calibrate the gain, supply close to
reference voltage to ADC inputs and measure it by multimeter. Calculate the gain coefficient
using following formula.
adcGain
counts 10
Vmeasured
Where the counts is returned from ADC_SAR_Seq_GetResult16() value, Vmeasued –
measured by multimeter voltage in volts.
Parameters:
int32 adcGain: ADC_SAR_Seq gain in counts per 10 volts
Return Value:
None
Side Effects:
Affects ADC_SAR_Seq_CountsTo_Volts(), ADC_SAR_Seq_CountsTo_mVolts(),
ADC_SAR_Seq_CountsTo_uVolts() by supplying the correct conversion between ADC
counts and the applied input voltage.
float32 ADC_SAR_Seq_CountsTo_Volts(int16 adcCounts)
Description:
Converts the ADC_SAR_Seq output to volts as a floating-point number. For example, if the
ADC_SAR_Seq measured 0.534 volts, the return value would be 0.534. The calculation of
voltage depends on the value of the voltage reference. When the Vref is based on Vdda, the
value used for Vdda is set for the project in the System tab of the Design Wide Resources
(DWR).
Parameters:
int16 adcCounts: Result from the ADC_SAR_Seq conversion
Return Value:
float32: Result in volts
Side Effects:
None
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PSoC® Creator™ Component Datasheet
int32 ADC_SAR_Seq_CountsTo_mVolts(int16 adcCounts)
Description:
Converts the ADC_SAR_Seq output to millivolts as a 32-bit integer. For example, if the
ADC_SAR_Seq measured 0.534 volts, the return value would be 534. The calculation of
voltage depends on the value of the voltage reference. When the Vref is based on Vdda, the
value used for Vdda is set for the project in the System tab of the Design Wide Resources
(DWR).
Parameters:
Int32 adcCounts: Result from the ADC_SAR_Seq conversion
Return Value:
int32: Result in mV
Side Effects:
None
int32 ADC_SAR_Seq_CountsTo_uVolts(int16 adcCounts)
Description:
Converts the ADC_SAR_Seq output to microvolts as a 32-bit integer. For example, if the
ADC_SAR_Seq measured 0.534 volts, the return value would be 534000. The calculation of
voltage depends on the value of the voltage reference. When the Vref is based on Vdda, the
value used for Vdda is set for the project in the System tab of the Design Wide Resources
(DWR).
Parameters:
int16 adcCounts: Result from the ADC conversion
Return Value:
int32: Result in µV
Side Effects:
None
void ADC_SAR_Seq_Sleep(void)
Description:
This is the preferred routine to prepare the component for sleep. The
ADC_SAR_Seq_Sleep() routine saves the current component state. Then it calls the
ADC_SAR_Seq_Stop() function and calls ADC_SAR_Seq_SaveConfig() to save the
hardware configuration.
Call the ADC_SAR_Seq_Sleep() function before calling the CyPmSleep() or the
CyPmHibernate() function. See the PSoC Creator System Reference Guide for more
information about power-management functions.
Parameters:
None
Return Value:
None
Side Effects:
None
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PSoC® Creator™ Component Datasheet
Sequencing Successive Approximation ADC (ADC_SAR_Seq)
void ADC_SAR_Seq_Wakeup(void)
Description:
This is the preferred routine to restore the component to the state when
ADC_SAR_Seq_Sleep() was called. The ADC_SAR_Seq_Wakeup() function calls the
ADC_SAR_Seq_RestoreConfig() function to restore the configuration. If the component was
enabled before the ADC_SAR_Seq_Sleep() function was called, the
ADC_SAR_Seq_Wakeup() function also re-enables the component.
Parameters:
None
Return Value:
None
Side Effects:
Calling the ADC_SAR_Seq_Wakeup() function without first calling the ADC_Sleep() or
ADC_SAR_Seq_SaveConfig() function can produce unexpected behavior.
void ADC_SAR_Seq_Init(void)
Description:
Initializes or restores the component according to the customizer Configure dialog
settings. It is not necessary to call ADC_SAR_Seq_Init() because the
ADC_SAR_Seq_Start() routine calls this function and is the preferred method to
begin component operation.
Parameters:
None
Return Value: None
Side Effects:
All registers will be set to values according to the customizer Configure dialog.
void ADC_SAR_Seq_Enable(void)
Description:
Activates the hardware and begins component operation. It is not necessary to call
ADC_SAR_Seq_Enable() because the ADC_SAR_Seq_Start() routine calls this function,
which is the preferred method to begin component operation. It is not recommended to call
this API a second time without stopping the component first.
Parameters:
None
Return Value: None
Side Effects:
None
Document Number: 001-96232 Rev. *C
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PSoC® Creator™ Component Datasheet
void ADC_SAR_Seq_SaveConfig(void)
Description:
This function saves the component configuration and nonretention registers. It also saves
the current component parameter values, as defined in the Configure dialog or as modified
by the appropriate APIs. This function is called by the ADC_SAR_Seq_Sleep() function.
Parameters:
None
Return Value:
None
Side Effects:
All ADC_SAR_Seq configuration registers are retained. This function does not have an
implementation and is meant for future use. It is shown here so that the APIs are consistent
across components.
void ADC_SAR_Seq_RestoreConfig(void)
Description:
This function restores the component configuration and nonretention registers. It also
restores the component parameter values to what they were before calling the
ADC_SAR_Seq_Sleep() function.
Parameters:
None
Return Value:
None
Side Effects:
Calling this function without first calling the ADC_SAR_Seq_Sleep() or
ADC_SAR_Seq_SaveConfig() function can produce unexpected behavior. This function
does not have an implementation and is meant for future use. It is provided here so that the
APIs are consistent across components.
Global Variables
Variable
ADC_SAR_Seq_initVar
Description
This variable indicates whether the ADC has been initialized. The variable is
initialized to 0 and set to 1 the first time ADC_SAR_Seq _Start() is called. This
allows the component to restart without reinitialization after the first call to the
ADC_SAR_Seq _Start() routine.
If reinitialization of the component is required, then the ADC_SAR_Seq _Init()
function can be called before the ADC_SAR_Seq _Start() or ADC_SAR_Seq
_Enable() functions.
ADC_SAR_Seq_finalArray
This array contains valid conversion results for all channels each time after EOC
pulse has been generated and EOC status is set.
Note When using the values from this array directly (not using
ADC_SAR_Seq_GetResult16() API function), the fact should be taken into account,
that channels are scanned in a reverse order, so the conversion result for the last
channel will be placed at ADC_SAR_finalArray[0].
Do not use this array directly in any of Differential modes because the
ADC_SAR_offset is not taken into account. Use ADC_SAR_Seq_GetResult16(),
where it is handled. If used directly, you must manually handle the ADC_SAR_offset.
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PSoC® Creator™ Component Datasheet
Sequencing Successive Approximation ADC (ADC_SAR_Seq)
Macro Callbacks
Macro callbacks allow users to execute code from the API files that are automatically generated
by PSoC Creator. Refer to the PSoC Creator Help and Component Author Guide for the more
details.
In order to add code to the macro callback present in the component’s generated source files,
perform the following:
Define a macro to signal the presence of a callback (in cyapicallbacks.h). This will
“uncomment” the function call from the component’s source code.
Write the function declaration (in cyapicallbacks.h). This will make this function visible by
all the project files.
Write the function implementation (in any user file).
Callback Function [2]
Associated Macro
ADC_SAR_Seq_ISR_InterruptCall ADC_SAR_Seq_ISR_INTERR
back
UPT_CALLBACK
Description
Used in the ADC_SAR_Seq_ISR() interrupt
handler to perform additional applicationspecific actions.
MISRA Compliance
This section describes the MISRA-C:2004 compliance and deviations for the component. There
are two types of deviations:
project deviations – deviations that are applicable for all PSoC Creator components
specific deviations – deviations that are applicable only for this component
This section provides information on component-specific deviations. Project deviations are
described in the MISRA Compliance section of the System Reference Guide along with
information on the MISRA compliance verification environment.
The ADC_SAR_Seq component does not have any specific deviations.
This component has the following embedded components: ADC_SAR, DMA, interrupt, clock,
Hardware AMUX. Refer to the corresponding component datasheets for information on their
MISRA compliance and specific deviations.
2
The callback function name is formed by component function name optionally appended by short explanation
and “Callback” suffix.
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Sequencing Successive Approximation ADC (ADC_SAR_Seq)
PSoC® Creator™ Component Datasheet
API Memory Usage
The component memory usage varies significantly depending on the compiler, device, number of
APIs used and component configuration. This table gives the memory usage for all APIs
available in the default component configuration.
The measurements were done with the associated compiler configured in release mode with
optimization set for size. For a specific design, analyze the map file generated by the compiler to
determine the memory usage.
PSoC 5LP (GCC)
Configuration
Flash Bytes
SRAM Bytes
1486
32
Default
Interrupt Service Routine
The ADC_SAR_Seq contains a blank interrupt service routine in the file ADC_SAR_Seq_INT.c
file, where “ADC_SAR_Seq” is the instance name. You can place custom code in the designated
areas to perform whatever function is required at the end of a conversion. A copy of the blank
interrupt service routine is shown below. Place custom code between the “/* `#START
MAIN_SEQ_ADC_ISR` */” and “/* `#END` */” comments. This ensures that the code will
be preserved when a project is regenerated.
CY_ISR( ADC_SAR_Seq_ISR )
{
#ifdef ADC_SAR_Seq_ISR_INTERRUPT_CALLBACK
ADC_SAR_Seq_ISR_InterruptCallback();
#endif /* ADC_SAR_Seq_ISR_INTERRUPT_CALLBACK */
/************************************************************************
* Custom Code
* - add user ISR code between the following #START and #END tags
*************************************************************************/
/* `#START MAIN_SEQ_ADC_ISR` */
/* `#END`
*/
}
A second designated area is available to place variable definitions and constant definitions.
/* `#START SEQ_ADC_SYS_VAR `
/* `#END`
*/
*/
Note You may use an alternative Interrupt service routine, located in your main.c file. In this case
use the following template:
Implement interrupt service routine in main.c:
CY_ISR( ADC_SAR_Seq_ISR_LOC )
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PSoC® Creator™ Component Datasheet
Sequencing Successive Approximation ADC (ADC_SAR_Seq)
{
/* Place your code here */
}
Enable ADC interrupt and set interrupt handler to local routine:
ADC_SAR_Seq_IRQ_StartEx(ADC_SAR_Seq_ISR_LOC);
Refer to Macro Callbacks section for details how to use callback from ISR.
Refer to the Interrupt component datasheet for more information.
Functional Description
This block diagram shows how input analog signals from the hardware AMUX are sampled and
converted by the ADC SAR component. The first DMA channel moves the results one at a time
from the SAR ADC to the temporary RAM buffer. When a complete set of data for all channels is
collected in the temporary RAM buffer, the contents of the temporary RAM buffer are transferred
to the results (SRAM) buffer in one transfer. Using a temporary buffer allows all data to be
collected so that the results buffer are updated once per scan, so that you have the necessary
time to do one scan sequence to move the last results.
Converting one sample in free running sample mode takes 12+6 clock cycles, or 12+4 clock
cycles if Reference is Internal Vref (not bypassed), where 12 is a resolution in bits
(RESOLUTIONbits), 6 (or 4) is a sample width and auto-zeroing (SAMPLEwidth).
The conversion time of the each sample is more than four cycles when hardware trigger sample
mode is used (SOChw). One cycle more for whole sampling is used for the soc edge detect logic
by sequencer (SOCedge).
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PSoC® Creator™ Component Datasheet
Sequencing Successive Approximation ADC (ADC_SAR_Seq)
The total number of clock required for sampling a selected number of channels could be
calculated by the following formula:
SAR_Seqclk=SOCedge+(RESOLUTIONbits+SAMPLEwidth + SOChw) * Channels + DMAbus_clk
The DMA operates at the same frequency as the CPU, which is the bus clock frequency. If the
ideal conditions are met, the number of bus clock cycles required for a data transfer from the
SAR to the RAM is equal to N+7 and from the RAM to the RAM is equal to 2N+6 where N is a
number of bursts. When the latest conversion is complete the DMA transfers last result from the
SAR to the RAM buffer and whole results from temporary RAM buffer to the results RAM buffer:
DMAbus_clk= 1+7 + 2*Channels+6
Refer to AN84810 for details on how to calculate the exact number of bus clock cycles required
for a DMA transaction under non-ideal conditions.
Refer to the ADC_SAR component datasheet for more information.
Registers
Status Register
ADC_SAR_SEQ_STATUS_REG
Bits
7
6
5
4
Value
3
2
1
0
Unused
EOC
EOC – End of Conversion. This register is set when one cycle of conversion for all
channels is complete.
Resources
The ADC_SAR_Seq uses SAR ADC component, which in turn is placed on a fixed-block SAR in
the silicon.
Resource Type
Configuration
Default
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Datapath
Cells
Macrocells
Status
Cells
Control/
Counter7
Cells
DMA
Channels
Interrupts
-
43
3
2
2
1
Document Number: 001-96232 Rev. *C
PSoC® Creator™ Component Datasheet
Sequencing Successive Approximation ADC (ADC_SAR_Seq)
DC and AC Electrical Characteristics
These values indicate expected performance and are based on initial characterization data.
Unless otherwise specified, operating conditions are:
Fclk = 1-18 MHz
Note The desired sample rate is guaranteed only if bus clock frequency value is at least
twice as large as the component clock frequency.
Input range = ±VREF
Bypass capacitor of 10 µF
See the appropriate section of the ADC SAR component datasheet for more details.
Component Errata
This section lists known problems with the component.
Cypress
ID
213738
Component
Version
2.0
Problem
Workaround
If the ADC_SAR_Seq component is
configured in “Hardware trigger” sample
mode, it can be halted if the first “soc”
signal rising edge appears during _Start()
function execution.
If you are facing this problem, the first soc
rising edge should be provided after the
_Start() function execution.
For example, if you are using a clock
component (named “Clock_soc”)
connected to the soc input of the
ADC_SAR_Seq component, apply the
following workaround:
1. Open Clock tab in the DesignWide Resources (cydwr) file.
2. Remove "Start on Reset" for
Clock_soc.
3. In the main.c file, add
Clock_soc_Start() API after
ADC_SAR_Seq_Start().
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Sequencing Successive Approximation ADC (ADC_SAR_Seq)
PSoC® Creator™ Component Datasheet
Component Changes
This section lists the major changes in the component from the previous version.
Version
2.0.c
Description of Changes
Datasheet update.
Reason for Changes / Impact
Updated the Functional Description section with
details on how to calculate the number of clocks
required for sampling.
Added Interrupt Service Routine section.
2.0.b
Datasheet update.
Added Macro Callbacks section.
2.0.a
Updated ADC_SAR_Seq_Start() and
ADC_SAR_Seq_Enable() descriptions.
Added a note that these APIs should not be called a
second time without first stopping the component.
Added Component Errata section.
Document a potential issue and workaround if the
component configured in “Hardware trigger” sample
mode.
2.0
The maximum sampling rate when operating with 1 Msps rate is not guaranteed by the silicon when
VDDA reference was reduced from 1 Msps to
used without a bypass capacitor. Refer to the VRef
500 Ksps.
Select parameter for more information.
Changed the conversion time from 18 to 16
cycles for Internal Vref Reference.
Limited configurations which violate DC/AC
Specifications.
Limited usage of the XTAL clock source. Higher
than 15 MHz XTAL must be divided by 2 or
greater.
Updated version of the embedded ADC_SAR
component to version 3.0.
Out of date component may contain defects or
incompatibilities.
Corrected channels scanning sequence
Incorrect results of last scanned channels
Corrected synchronization for high frequency
clock
Warning of static timing analyze for high frequency
clock
Edited datasheet to remove Component Errata
section.
This section does not apply to this version of the
component.
Datasheet edits
Updated Features section to show inputs restriction.
Updated MISRA Compliance section to remove
MISRA deviations.
Updated parameters description for
ADC_SAR_Seq_GetResult16 API.
Updated Resources section.
Updated API Memory Usage section.
Updated Functional Description section.
Updated Reference section.
1.10.a
Edited datasheet to add Component Errata
section.
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Document that the component was changed, but
there is no impact to designs.
Document Number: 001-96232 Rev. *C
PSoC® Creator™ Component Datasheet
Version
1.10
Sequencing Successive Approximation ADC (ADC_SAR_Seq)
Description of Changes
Updated the gain calibration to have better
resolution.
Added new ADC_SAR_Seq_SetScaledGain()
API which sets the gain coefficient with more
than 12-bit resolution.
1.0
Reason for Changes / Impact
New API added according to changes in the ADC
SAR component (gain coefficient
(ADC_countsPerVolt) had 10-bits resolution in Vssa
to Vdda input range.) This issue affected
ADC_SAR_Seq_CountsTo_Volts(), ADC_SAR_Seq
_CountsTo_mVolts(), and ADC_SAR_Seq
_CountsTo_uVolts() API.
First component release
© Cypress Semiconductor Corporation, 2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control, or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for
use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in lifesupport systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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referenced herein are property of the respective corporations.
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specified above is prohibited without the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein.
Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in lifesupport systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application
implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-96232 Rev. *C
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