PHILIPS P87CL881H/000

INTEGRATED CIRCUITS
DATA SHEET
P87CL881H
Low-voltage microcontroller with
63-kbyte OTP program memory
and 2-kbyte RAM
Product specification
File under Integrated Circuits, IC17
1999 Apr 16
Philips Semiconductors
Product specification
Low-voltage microcontroller with 63-kbyte
OTP program memory and 2-kbyte RAM
CONTENTS
1
FEATURES
2
GENERAL DESCRIPTION
3
ORDERING INFORMATION
4
BLOCK DIAGRAM
5
PINNING INFORMATION
5.1
5.2
Pinning
Pin description
6
FUNCTIONAL DESCRIPTION
6.1
6.2
6.3
6.4
6.5
6.6
Special Function Registers
I/O facilities
Internal data memory
OTP programming
Oscillator circuitry
Non-conformance
7
LIMITING VALUES
8
DC CHARACTERISTICS
9
AC CHARACTERISTICS
9.1
AC testing
10
PACKAGE OUTLINE
11
SOLDERING
11.1
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
11.2
11.3
11.4
11.5
12
DEFINITIONS
13
LIFE SUPPORT APPLICATIONS
14
PURCHASE OF PHILIPS I2C COMPONENTS
1999 Apr 16
2
P87CL881H
Philips Semiconductors
Product specification
Low-voltage microcontroller with 63-kbyte
OTP program memory and 2-kbyte RAM
1
P87CL881H
FEATURES
• Full static 80C51 CPU; enhanced 8-bit architecture with:
– Minimum 6 cycles per instruction (twice as fast as a
standard 80C51 core)
– Non-page oriented instructions
• Wake-up from Power-down mode via LVD or external
interrupts at Port 1
– Direct addressing
– Four 8-byte RAM register banks
• Two 16-bit timer/event counters
– Stack depth limited only by available internal RAM
(maximum 256 bytes)
• Additional 16-bit timer/event counters, with capture,
compare and PWM function
– Multiply, divide, subtract and compare instructions.
• Very low current consumption
• Watchdog Timer
• Single supply voltage of 2.7 to 3.6 V
• Full duplex enhanced UART with double buffering
• Frequency: 1 to 10 MHz
• I2C-bus interface for serial transfer on two lines,
maximum operating frequency 400 kHz.
• Operating temperature: −25 to +70 °C
• 44-pin LQFP package
• Four 8-bit ports (32 I/O lines)
2
• 63-kbyte One-Time Programmable (OTP) program
memory; programmable in parallel mode or in-system
via I2C-bus interface.
The P87CL881 is an 8-bit microcontroller especially suited
for pager applications.
The P87CL881 is manufactured in an advanced CMOS
technology and is based on single chip technology.
• 256-byte internal RAM
• 1792-byte internal AUX-RAM
The device is optimized for low power consumption and
has two software selectable features for power reduction:
Idle and Power-down modes. In addition, all derivative
blocks switch off their clock if they are inactive.
• External address range: 64 kbytes of ROM and
64 kbytes of RAM
• Amplitude Controlled Oscillator (ACO) suitable for use
with a quartz crystal or ceramic resonator
The instruction set of the P87CL881 is based on that of
the 80C51. The P87CL881 also functions as an arithmetic
processor having facilities for both binary and BCD
arithmetic plus bit-handling capabilities. The instruction set
consists of over 100 instructions: 49 one-byte,
46 two-byte, and 16 three-byte.
• Improved Power-on/Power-off reset circuitry (POR)
• Low Voltage Detection (LVD) with 11 software
programmable levels
• 8 interrupts on Port 1, edge or level sensitive triggering
selectable via software power-saving use for keyboard
control
This data sheet details the specific properties of the
P87CL881; for details of the P87CL881 core and the
derivative functions see the “TELX family” data sheet and
“8051-Based 8-bit Microcontrollers; Data Handbook IC20”.
• Twenty source, twenty vector interrupt structure with two
priority levels
3
GENERAL DESCRIPTION
ORDERING INFORMATION
TYPE
NUMBER(1)
PACKAGE
PRODUCT TYPE
P87CL881H/000
Blank OTP
P87CL881H/xxx
Factory-programmed OTP
NAME
DESCRIPTION
VERSION
LQFP44
plastic low profile quad flat package;
44 leads; body 10 × 10 × 1.4 mm
SOT389-1
Note
1. Please refer to the Order Entry Form (OEF) for this device for the full type number to use when ordering. This type
number will also specify the required program and options.
1999 Apr 16
3
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PROGRAM
MEMORY
ROM
VSS VSSP VPP(5)
DATA
MEMORY
RAM
DATA
MEMORY
AUX-RAM
P87CL881H
80C51
core
excluding
ROM/RAM
ACO
8-bit
internal bus
PSEN
ALE
WR (4)
RD (4)
LVD
4
AD0 to AD7 (1)
SERIAL
UART
PORT
PARALLEL
I/O PORTS
A8 to A15 (3)
16-BIT
TIMER/EVENT
COUNTER WITH
CAPTURE/
COMPARE/
(T2)
EEPROM
I2C-BUS
INTERFACE
WATCHDOG
TIMER
(T3)
Low-voltage microcontroller with 63-kbyte
OTP program memory and 2-kbyte RAM
CPU
BLOCK DIAGRAM
TWO 16-BIT
TIMER/
EVENT
COUNTERS
(T0, T1)
EA
XTAL1
XTAL2
CLK (2)
INT1 (4)
T1 (4) INT0 (4) INT2 to INT8 (2) VDD VDDP
7
Philips Semiconductors
4
1999 Apr 16
T0 (4)
POR
MGL617
P0
P3
TXD (4)
T2 (2)
RST
EW
PORENABLE
T2COMP (2)
Fig.1 Block diagram.
Product specification
Alternative function of Port 0.
Alternative function of Port 1.
Alternative function of Port 2.
Alternative function of Port 3.
Alternative function of pin 6.
P2
SDA (2) SCL (2)
P87CL881H
(1)
(2)
(3)
(4)
(5)
P1
T2EX (2)
handbook, full pagewidth
RXD (4)
Philips Semiconductors
Product specification
Low-voltage microcontroller with 63-kbyte
OTP program memory and 2-kbyte RAM
34 P0.3/AD3
P1.5/INT7
1
33 P0.4/AD4
P1.6/INT8/SCL
2
32 P0.5/AD5
P1.7/INT9/SDA
3
31 P0.6/AD6
RST
4
30 P0.7/AD7
P3.0/RXD/data
5
29 EA
PORENABLE/VPP
6
P3.1/TXD/clock
7
27 ALE
P3.2/INT0
8
26 PSEN
P3.3/INT1
9
25 P2.7/A15
P3.4/T0 10
24 P2.6/A14
P3.5/T1 11
23 P2.5/A13
5
P2.4/A12 22
P2.3/A11 21
P2.2/A10 20
28 EW
P2.1/A9 19
P2.0/A8 18
VSS 17
VSSP 16
XTAL1 15
P3.7/RD 13
P3.6/WR 12
P87CL881H
Fig.2 Pin configuration.
1999 Apr 16
35 P0.2/AD2
36 P0.1/AD1
37 P0.0/AD0
38 VDDP
39 VDD
40 P1.0/INT2/T2
43 P1.3/INT5
44 P1.4/INT6/CLK
handbook, full pagewidth
41 P1.1/INT3/T2EX
Pinning
42 P1.2/INT4/T2COMP
5.1
PINNING INFORMATION
XTAL2 14
5
P87CL881H
MGL616
Philips Semiconductors
Product specification
Low-voltage microcontroller with 63-kbyte
OTP program memory and 2-kbyte RAM
5.2
P87CL881H
Pin description
Table 1
LQFP package
SYMBOL
PIN
DESCRIPTION
VDD
39
Power supply for core.
VDDP
38
Power supply for I/O ring.
VSS
17
Ground for core.
VSSP
16
Ground for I/O ring.
RST
4
RESET. A LOW level on this pin for two machine cycles while the oscillator is running,
resets the device. The RST pin is also an output which can be used to reset other ICs.
PORENABLE/VPP
6
PORENABLE. If set to a logic 1, the internal Power-on reset circuit is enabled. If external
reset circuitry is used, it is recommended to keep PORENABLE LOW in order to achieve
the lowest power consumption. This pin is also used for the OTP programming voltage
VPP.
EW
28
Enable Watchdog Timer.
XTAL2
14
Crystal output. Output of the amplitude controlled oscillator. If an external oscillator
clock is used this pin not used.
XTAL1
15
Crystal input. Input to the amplitude controlled oscillator. Also the input for an externally
generated clock source.
PSEN
26
Program Store Enable. Read strobe to external program memory. When executing
code out of external program memory, PSEN is activated twice each machine cycle.
However, during each access to external data memory two PSEN activations are
skipped. During Power-down mode the PSEN pin stays HIGH.
ALE
27
Address Latch Enable. Latches the low byte of the address during accesses to external
memory. It is activated every six oscillator periods and may be used for external timing or
clocking purposes. For improved EMC behaviour, the toggle of the ALE pin can be
disabled by setting the RFI bit in the PCON register by software. This bit is cleared on
reset and can be set and cleared by software. When set, the ALE pin will be pulled-down
internally, switching an external address latch to a quiet state. The MOVX instruction will
still toggle ALE if external memory is accessed. ALE will retain its normal HIGH state
during Idle mode and a LOW state during the Power-down mode while in the EMC mode.
Additionally, during internal access (EA = 1) ALE will toggle normally when the address
exceeds the internal program memory size. During external access (EA = 0) ALE will
always toggle normally, whether the RFI bit is set or not.
EA
29
External Access. When EA is held HIGH, the CPU executes out of the internal program
memory (unless the program counter exceeds the highest address for internal program
memory). When EA is held LOW, the CPU executes out of external program memory
regardless of the value of the program counter. The state of the EA pin is internally
latched at reset.
1999 Apr 16
6
Philips Semiconductors
Product specification
Low-voltage microcontroller with 63-kbyte
OTP program memory and 2-kbyte RAM
SYMBOL
P87CL881H
PIN
DESCRIPTION
P0.0/AD0
37
P0.1/AD1
36
P0.2/AD2
35
Port 0. 8-bit bidirectional I/O port with alternative functions. Every port pin can be used
as open-drain, standard port, high-impedance input or push-pull output, according to
Section 6.2. AD7 to AD0 provide the multiplexed low-order address and data bus during
accesses to external memory.
P0.3/AD3
34
P0.4/AD4
33
P0.5/AD5
32
P0.6/AD6
31
P0.7/AD7
30
P1.0/INT2/T2
40
P1.1/INT3/T2EX
41
P1.2/INT4/
T2COMP
42
P1.3/INT5
43
P1.4/INT6/CLK
44
P1.5/INT7
1
P1.6/INT8/SCL
2
P1.7/INT9/SDA
3
P2.0/A8
18
P2.1/A9
19
P2.2/A10
20
P2.3/A11
21
P2.4/A12
22
P2.5/A13
23
P2.6/A14
24
P2.7/A15
25
P3.0/RXD/data
5
P3.1/TXD/clock
7
P3.2/INT0
8
P3.3/INT1
9
P3.4/T0
10
P3.5/T1
11
P3.6/WR
12
P3.7/RD
13
1999 Apr 16
Port 1. 8-bit bidirectional I/O port with alternative functions. Every port pin except P1.6
and P1.7 (I2C-bus pins) can be used as open-drain, standard port, high-impedance input
or push-pull output, according to Section 6.2. Port 1 also serves the alternative functions
INT2 to INT9 interrupts, Timer 2 external input and Timer 2 compare output, external
clock output CLK and I2C-bus clock and I2C-bus data in/outputs.
Port 2. 8-bit bidirectional I/O port with alternative functions. Every port pin can be used
as open-drain, standard port, high-impedance input or push-pull output, according to
Section 6.2. Port 2 emits the high order address byte during accesses to external
memory that use 16-bit addresses (MOVX @ DPTR). In this application it uses the
strong internal pull-ups when emitting logic 1's. During accesses to external memory that
use 8-bit addresses (MOVX @ Ri), Port 2 emits the contents of the P2 Special Function
Register.
Port 3. 8-bit bidirectional I/O port with alternative functions. Every port pin can be used
as open-drain, standard port, high-impedance input or push-pull output, according to
Section 6.2. RXD/data is the serial port receiver data input (asynchronous) or data I/O
(synchronous). TXD/clock is the serial port transmitter data output (asynchronous) or
clock output (synchronous). INT0 and INT1 are external interrupt lines. T0 and T1 are
external inputs for Timers 0 and 1 respectively. WR is the external memory write strobe
and RD is the external memory read strobe.
7
Philips Semiconductors
Product specification
Low-voltage microcontroller with 63-kbyte
OTP program memory and 2-kbyte RAM
6
P87CL881H
FUNCTIONAL DESCRIPTION
For the functional and block descriptions of the P87CL881, refer to the “TELX family” data sheet.
6.1
Special Function Registers
Table 2
Special Function Registers memory map and reset values; note 1
REGISTER NAME
REGISTER MNEMONIC
SFR ADDRESS
RESET VALUE(2)
80C51 core
Accumulator
ACC
E0H
0000 0000
B Register
B
F0H
0000 0000
Data Pointer Low byte
DPL
82H
0000 0000
Data Pointer High byte
DPH
83H
0000 0000
Program Counter High byte
PCH
no SFR
0000 0000
Program Counter Low byte
PCL
no SFR
0000 0000
Power Control Register
PCON
87H
0000 0000
Prescaler Register
PRESC
F3H
0000 0000
Program Status Word
PSW
D0H
0000 0000
Stack Pointer
SP
81H
0000 0111
XRAM Page Register
XRAMP
FAH
XXXX X000
Timer/Counter Control Register
TCON
88H
0000 0000
Timer/Counter 0 High byte
TH0
8CH
0000 0000
Timer/Counter 1 High byte
TH1
8DH
0000 0000
Timer/Counter 0 Low byte
TL0
8AH
0000 0000
Timer/Counter 1 Low byte
TL1
8BH
0000 0000
Timer/Counter Mode Control Register
TMOD
89H
0000 0000
Alternative Port Function Control Register
ALTP
A3H
0000 0000
Port P0 output data Register
P0
80H
1111 1111
Port P0 Configuration A Register
P0CFGA
8EH
1111 1111
Port P0 Configuration B Register
P0CFGB
8FH
0000 0000
Port P1 output data Register
P1
90H
0111 1111
Port P1 Configuration A Register
P1CFGA
9EH
0000 1000
Port P1 Configuration B Register
P1CFGB
9FH
0111 1111
Port P2 output data Register
P2
A0H
1111 1111
Port P2 Configuration A Register
P2CFGA
AEH
1111 1111
Port P2 Configuration B Register
P2CFGB
AFH
0000 0000
Port P3 output data Register
P3
B0H
1111 1111
Port P3 Configuration A Register
P3CFGA
BEH
1111 1110
Port P3 Configuration B Register
P3CFGB
BFH
1111 1111
Timers 0 and 1
Ports
1999 Apr 16
8
Philips Semiconductors
Product specification
Low-voltage microcontroller with 63-kbyte
OTP program memory and 2-kbyte RAM
REGISTER NAME
REGISTER MNEMONIC
P87CL881H
SFR ADDRESS
RESET VALUE(2)
Timer 2
Timer 2 Compare High byte
COMP2H
ABH
0000 0000
Timer 2 Compare Low byte
COMP2L
AAH
0000 0000
Timer 2 Reload/Capture High byte
RCAP2H
CBH
0000 0000
Timer 2 Reload/Capture Low byte
RCAP2L
CAH
0000 0000
Timer/Counter 2 Control Register
T2CON
C8H
0000 0000
Timer/Counter 2 High byte
TH2
CDH
0000 0000
Timer/Counter 2 Low byte
TL2
CCH
0000 0000
Interrupt Enable Register 0
IEN0
A8H
0000 0000
Interrupt Enable Register 1
IEN1
E8H
0000 0000
Interrupt Enable Register 2
IEN2
F1H
0000 0000
Interrupt Priority Register 0
IP0
B8H
0000 0000
Interrupt Priority Register 1
IP1
F8H
0000 0000
Interrupt Priority Register 2
IP2
F9H
0000 0000
Interrupt Sensitivity Register 1
ISE1
E1H
0000 0000
Interrupt Polarity Register
IX1
E9H
0000 0000
Interrupt Request Flag Register 1
IRQ1
C0H
0000 0000
LVDCON
F2H
0000 0000
RSTAT
E6H
XXX1 1000
Serial Port Buffer
S0BUF
99H
0000 0000
Serial Port Control Register
S0CON
98H
0000 0000
Address Register
S1ADR
DBH
0000 0000
Serial Control Register
S1CON
D8H
0000 0000
Data Shift Register
S1DAT
DAH
0000 0000
Serial Status Register
S1STA
D9H
1111 1000
Watchdog Timer Control Register
WDCON
A5H
1010 0101
Watchdog Timer Interval Register
WDTIM
FFH
0000 0000
Interrupt logic
Low Voltage Detection
LVD Control Register
PORACO
Reset Status Register
UART
I2C-bus interface
Watchdog timer
1999 Apr 16
9
Philips Semiconductors
Product specification
Low-voltage microcontroller with 63-kbyte
OTP program memory and 2-kbyte RAM
REGISTER NAME
P87CL881H
REGISTER MNEMONIC
SFR ADDRESS
RESET VALUE(2)
OTP interface
OTP Address High Register
OAH
D5
X00X XXXX
OTP Address Low Register
OAL
D4
XXXX XXXX
OTP Data Register
ODATA
D6
XXXX XXXX
OTP In-System Programming Register
OISYS
DC
000X 0000
OTP Test Register
OTEST
D7
0000 0000
Notes
1. E7H and FDH are reserved locations and must not be written to.
2. Where: X = undefined state.
6.2
6.2.1
To enable a port pin alternative function, the port bit latch
in its SFR must contain a logic 1.
I/O facilities
PORTS
Each port consists of a latch (Special Function Registers
P0 to P3), an output driver and input buffer. All ports have
internal pull-ups. Figure 3(a) shows that the strong
transistor P1 is turned on for only 1 oscillator period after a
LOW-to-HIGH transition in the port latch. When on, it turns
on P3 (a weak pull-up) through the inverter IN1. This
inverter and transistor P3 form a latch which holds the
logic 1.
The P87CL881 has 32 I/O lines treated as 32 individually
addressable bits or as four parallel 8-bit addressable ports.
Ports 0, 1, 2 and 3 perform the following alternative
functions:
Port 0 Provides the multiplexed low-order address and
data bus for expanding the device with standard
memories and peripherals.
Port 1 Used for a number of special functions:
6.2.2
• P1.0 to P1.7 provides the inputs for the external
interrupts INT2 to INT9
I/O port output configurations are determined by the
settings in the port configuration SFRs. Each port has two
associated SFRs: PnCFGA and PnCFGB, where ‘n’
indicates the specific port number (0 to 3). One bit in each
of the 2 SFRs relates to the output setting for the
corresponding port pin, allowing any combination of the
2 output types to be mixed on those port pins.
For example, the output type of P1.3 is controlled by
setting bit 3 in the SFRs P1CFGA and P1CFGB.
• P1.0/T2 and P1.1/T2EX for external inputs of Timer 2
• P1.2/T2COMP for external activation and compare
output of Timer 2
• P1.4/CLK for the clock output
• P1.6/SCL and P1.7/SDA for the I2C-bus interface are
real open-drain outputs or high-impedance; no other
port configurations are available.
The port pins may be individually configured via the SFRs
with one of the following modes (P1.6 and P1.7 can be
open-drain or high-impedance but never have any diodes
against VDD).
Port 2 Provides the high-order address bus when
expanding the device with external program
memory and/or external data memory.
Port 3 Pins can be configured individually to provide:
Mode 0 Open-drain; quasi-bidirectional I/O with
n-channel open-drain output. Use as an output
(e.g. Port 0 for external memory accesses
(EA = 0) or access above the built-in memory
boundary) requires the connection of an external
pull-up resistor. The ESD protection diodes
against VDD and VSS are still present. Except for
the I2C-bus pins P1.6 and P1.7, ports which are
configured as open-drain still have a protection
diode to VDD. See Fig.3a.
• P3.0/RXD/data and P3.1/TXD/clock which are serial
port receiver input and transmitter output (UART)
• P3.2/INT0 and P3.3/INT1 are external interrupt request
inputs
• P3.4/T0 and P3.5/T1 as counter inputs
• P3.6/WR and P3.7/RD are control signals to write and
read to external memories.
1999 Apr 16
PORT I/O CONFIGURATION
10
Philips Semiconductors
Product specification
Low-voltage microcontroller with 63-kbyte
OTP program memory and 2-kbyte RAM
Mode 1 Standard port; quasi-bidirectional I/O with
pull-up. The strong pull-up p1 is turned on for
only one oscillator periods after a LOW-to-HIGH
transition in the port latch. After these two
oscillator periods the port is only weakly driven
through p2 and ‘very weakly’ driven through p3.
See Fig.3b.
P87CL881H
Tables 2 and 3 show the configuration register settings for
the four output configurations. The electrical
characteristics of each output configuration are specified
in Chapter 8. The default port configuration after reset is
given in Table 2.
In case of external memory access, the appropriate
options for ports P0, P2 and P3.6/P3.7 (WR/RD, only in
case of external data memory access) must be set by
software.
Mode 2 High-impedance; this mode turns all port output
drivers off. Thus, the pin will not source or sink
current and may be used as an input-only pin with
no internal drivers for an external device to
overcome. See Fig.3c.
For Special Function Registers for port configurations/data
please refer to Table 2, note 1.
Mode 3 Push-pull; output with drive capability in both
polarities. In this mode, pins can only be used as
outputs. See Fig.3d.
Table 3
Port configuration register settings
MODE(1)
PORT OUTPUT CONFIGURATION
PnCFGA
PnCFGB
NORMAL PORTS
I2C-BUS PORTS (P1.6 AND P1.7)
0
0
0
open-drain
open-drain
1
1
0
quasi-bidirectional
open-drain
2
0
1
high-impedance
high-impedance
3
1
1
push-pull
open-drain
Note
1. Mode changes may cause glitches to occur during transitions. When modifying both registers, write instructions
should be carried out consecutively.
1999 Apr 16
11
Philips Semiconductors
Product specification
Low-voltage microcontroller with 63-kbyte
OTP program memory and 2-kbyte RAM
handbook, full pagewidth
P87CL881H
VDD external
VDD
this diode is not
implemented
on the I2C-bus pins
external
pull-up
I/O pin
Q
from port latch
n
VSS
VSS
MBK004
input data
a. Open-drain.
VDD
strong pull-up
handbook, full pagewidth
1 oscillator
period
p2
p3
p1
I/O pin
Q
from port latch
n
IN1
VSS
VSS
input data
MBK001
b. Standard/quasi-bidirectional.
VDD
handbook, full pagewidth
this diode is not
implemented
on the I2C-bus pins
input data
I/O pin
VSS
MBK002
c. High-impedance.
strong pull-up
handbook, full pagewidth
VDD
VDD
p
I/O pin
Q
from port latch
n
VSS
VSS
input data
MBK003
d. Push-pull.
Fig.3 Port configuration options.
1999 Apr 16
12
Philips Semiconductors
Product specification
Low-voltage microcontroller with 63-kbyte
OTP program memory and 2-kbyte RAM
6.3
P87CL881H
instructions in the same way as in the 80C51 structure, so
with P0 and P2 as data/address bus and P3.6 and P3.7 as
write and read timing signals. Note that the external data
memory cannot be accessed with R0 and R1 as address
pointer if the AUX-RAM is enabled (ARD = 0, default after
reset).
Internal data memory
The internal data memory is divided into three physically
separated parts:
256 bytes of RAM, 128 bytes of Special Function
Registers and 1792 bytes of AUX-RAM. These can be
addressed each in a different way (see also Table 4).
The Special Function Registers (SFR) can only be
addressed directly in the address range from 128 to 255.
1. RAM 0 to 127 can be addressed directly and indirectly
as in the 80C51; address pointers are R0 and R1 of
the selected register-bank
Four register banks, each 8 registers wide, occupy
locations 0 through 31 in the lower RAM area. Only one of
these banks may be enabled at a time. The next 16 bytes,
locations 32 through 47, contain 128 directly addressable
bit locations. The stack can be located anywhere in the
internal 256 bytes RAM. The stack depth is only limited by
the available internal RAM space of 256 bytes (see Fig.4).
2. RAM 128 to 255 can only be addressed indirectly;
address pointers are R0 and R1 of the selected
register bank
3. AUX-RAM 0 to 1791 is indirectly addressable via the
AUX-RAM Page Register (XRAMP) and MOVX-Ri
instructions, unless it is disabled by setting ARD = 1.
AUX-RAM 0 to 1791 is also indirectly addressable as
external data memory via MOVX-datapointer
instruction, unless it is disable by setting ARD = 1.
When executing from internal program memory, an
access to AUX-RAM 0 to 1791 when ARD = 0 will not
affect the ports P0, P2, P3.6 and P3.7.
Table 4
Internal data memory map
LOCATION
An access to external data memory locations higher
than 1791 will be performed with the MOVX @ DPTR
ADDRESS
ADDRESSING
RAM
0 to 127
direct and indirect
AUX-RAM
0 to 1791
indirect only with MOVX
RAM
128 to 255
indirect only
SFR
128 to 255
direct only
FFFFH
handbook, full pagewidth
FFFFH
FBFFH
(ARD = 0/1)
0700H
PAGE 6
06FFH
PAGE 5
FFH
INDIRECT
ADDRESSING
7FH
INTERNAL
EXTERNAL
(EA = 1)
(EA = 0)
00H
0
0
PAGE 4
DIRECT
(ARD = 1)
PAGE 2
INDIRECT AND
DIRECT
ADDRESSING
PAGE 1
PAGE 0
0000H
INTERNAL RAM
PROGRAM MEMORY
INTERNAL
AUX-RAM
(ARD = 0)
DATA MEMORY
Fig.4 Memory map.
1999 Apr 16
PAGE 3
13
EXTERNAL DATA
MEMORY
MGL618
Philips Semiconductors
Product specification
Low-voltage microcontroller with 63-kbyte
OTP program memory and 2-kbyte RAM
6.3.1
P87CL881H
AUX-RAM PAGE REGISTER (XRAMP)
The AUX-RAM Page Register is used to select one of the seven 256 bytes pages of the internal 1792-byte AUX-RAM
for MOVX-accesses via R0 or R1. Its reset value is ‘XXXX X000’ (AUX-RAM page 0).
Table 5
AUX-RAM Page Register (SFR address FAH)
7
6
5
4
3
2
1
0
−
−
−
−
−
XRAMP2
XRAMP1
XRAMP0
Table 6
Description of XRAMP bits
BIT
SYMBOL
FUNCTION
7 to 3
−
reserved, undefined during read, a write operation must write logic 0 to these locations
2
XRAMP2
AUX-RAM page select bit 2
1
XRAMP1
AUX-RAM page select bit 1
0
XRAMP0
AUX-RAM page select bit 0
Table 7
ARD(1)
Memory locations for all possible MOVX accesses
XRAMP2 XRAMP1 XRAMP0
ACCESS
0
0
0
0
AUX-RAM page 0 (address 0 to 255)
0
0
0
1
AUX-RAM page 1 (address 256 to 511)
0
0
1
0
AUX-RAM page 2 (address 512 to 767)
0
0
1
1
AUX-RAM page 3 (address 768 to 1023)
0
1
0
0
AUX-RAM page 4 (address 1024 to 1279)
0
1
0
1
AUX-RAM page 5 (address 1280 to 1535)
0
1
1
0
AUX-RAM page 6 (address 1536 to 1791)
0
1
1
1
no valid memory access
1
X
X
X
external RAM locations 0 to 255
0
X
X
X
AUX-RAM locations 0 to 1791 external
RAM locations 1792 to 65535
1
X
X
X
external RAM locations 0 to 65535
INSTRUCTION TYPE
MOVX @ Ri, A and
MOVX @ A, Ri
MOVX @ DPTR, A and
MOVX A, DPTR
Note
1. ARD (AUX-RAM Disable) corresponds to bit 6 in the Special Function Register PCON (address 87H).
1999 Apr 16
14
Philips Semiconductors
Product specification
Low-voltage microcontroller with 63-kbyte
OTP program memory and 2-kbyte RAM
6.4
6.4.2
OTP programming
6.4.1
The 63-kbyte One-Time Programmable (OTP) memory
can be programmed by using an OM4260 programmer
together with a programmer adapter OM5510. Since the
memory is programmable only once, programming an
already programmed address results in a logical AND of
the old and new code. The OTP code can be read out by
the programmer for verification.
In the In-System Programming mode the complete
address space OTP can be programmed.
The user should take care not to overwrite the existing
code.
Signature bytes
For In-System Programming four SFRs are used to control
the OTP.
The OTP memory contains three signature bytes which
can be read by the programmer to identify the device.
A special address space has been used for these bytes
which does not influence the user address space.
The values of the signature bytes are:
Table 8
SFRs for In-System Programming
SFR NAME
(030H) = 15H, indicates manufactured by Philips
Semiconductors
(031H) = D6H, indicates P87CL881H
(060H) = 00H, currently not used.
6.4.2.1
IN-SYSTEM PROGRAMMING MODE
In the In-System Programming mode the OTP can be
programmed under control of the CPU. A program to
control programming has to be available in the OTP. This
mode can be used to program several bytes in the OTP if
the chip is already in a system e.g. to store tuning
parameters.
OTP PROGRAMMING
6.4.1.1
P87CL881H
DESCRIPTION
OAH
OTP Address High Register
OAL
OTP Address Low Register
ODATA
OTP Data Register
OISYS
OTP In-System Register
OTP In-System Programming Register (OISYS)
The OISYS SFR controls the In-System Programming mode. The data that has to be programmed is stored in the SFR
ODATA and the address for this data in the SFRs OAH and OAL.
Table 9
OTP In-System Programming Register (SFR address DCH)
7
6
5
4
3
2
1
0
−
−
−
VPon
0
SIG
WE
InSysMode
Table 10 Description of OISYS bits
BIT
SYMBOL
7 to 5
−
4
VPon
DESCRIPTION
These bits are reserved.
VPP status (read only).
3
0
2
SIG
Signature bytes enable.
1
WE
Write Enable, enables programming.
0
InSysMode
1999 Apr 16
This bit is reserved and must be kept to logic 0.
In-System Programming status bit.
15
Philips Semiconductors
Product specification
Low-voltage microcontroller with 63-kbyte
OTP program memory and 2-kbyte RAM
6.4.2.2
P87CL881H
The signature bytes (and other test addresses) are always
readable independent of the security.
Mode entry
The In-System Programming mode is entered by setting
the InSysMode bit of the OISYS SFR. The I2C-bus is used
for data transfer in this mode. If the I2C-bus interface is
addressed by an external master, the interface generates
an interrupt request. The interrupt handler can now read
the OISYS SFR and determine the status of the external
high voltage (VPon). If high voltage is not present the
interrupt is a standard I2C-bus interrupt.
6.4.2.6
How to connect the PORENABLE/VPP pin in
the In-System Programming mode
If high voltage is present the In-System program interrupt
routine has to start that writes the InSysMode bit
(OISYS.0) and controls the address and data transfer.
If the VPP pin is dual-mode (e.g. PORENABLE/VPP), ICs
connected to the signal PORENABLE must be able to
withstand up to 13 V, i.e. cannot have clamping diodes or
low break-down voltages. If the pin is connected to a fixed
voltage (VDD or VSS) there must be a way of switching-off
this connection on the PCB. A possible implementation is
presented in Fig.5.
The program voltage has to be available and stable for at
least 10 µs before the mode is entered and has to be
stable until the circuit has left the In-System Programming
mode. The high voltage can be applied for maximum
60 seconds during the complete lifetime of the circuit.
In the example (see Fig.5) the POR is enabled in normal
mode of operation (pin PORENABLE/VPP = 1 by the
pull-up), but the VPP source must supply enough current
in Rp in order to guarantee a minimum 12.5 V on the
PORENABLE/VPP pin.
6.4.2.3
Note that if in the application the Power-on reset is
disabled (pin PORENABLE/VPP = 0), applying a high
voltage to the PORENABLE/VPP pin will also enable the
POR circuit. This will cause a reset independent of the
actual VDD value.
Program cycle
The data and address must be supplied to the
microcontroller and the control program has to write the
SFRs: ODATA, OAH and OAL. A timer has to be initialized
for a 100 µs cycle and the WE bit of the OISYS SFR must
be set. Now the core has to be set into Idle mode. As long
as the circuit is in Idle mode a programming pulse is
applied. After the interrupt request of the timer the OTP is
available for normal code fetching.
handbook, halfpage
VDD
Rp
The address applied to the OAH and OAL SFRs must be
in the 63 kbytes address space.
6.4.2.4
VPP pad on PCB
Verify for In-System Programming
44
Verify is done in similar way as programming. The circuit
is put into Idle mode and at the start of this mode the sense
amplifiers are switched to verify mode and a read cycle is
started. The timer has to be initialized for a cycle of at least
1 µs. The address is supplied by the SFRs OAH and OAL.
The WE bit of the OISYS SFR has to be reset. The OTP
output data is latched in the ODATA SFR. After Idle mode
is finished this SFR can be read in a normal way. To be
sure that the verified data is written into the SFR it is
advised to write FFH into the ODATA SFR before a verify
is started.
6.4.2.5
1
33
6
P87CL881H
11
23
12
Signature bytes
22
MBL001
The signature bytes can be read by setting the SIG bit of
the OISYS SFR and applying the address of the signature
byte. Applying a write pulse while the SIG bit of the OISYS
SFR is HIGH is forbidden although the contents of the
signature bytes will never be destroyed.
1999 Apr 16
34
Fig.5
16
Example of PORENABLE/VPP connection
on a PCB.
Philips Semiconductors
Product specification
Low-voltage microcontroller with 63-kbyte
OTP program memory and 2-kbyte RAM
6.5
Oscillator circuitry
6.6
General information on the oscillator circuitry can be found
in the “TELX family” data sheet.
6.5.1
6.6.1
Non-conformance
PROGRAMMING INTERFACE/TRANSPARENT MODE
The transparent mode is a special operating mode of the
microcontroller used for parallel and In-System OTP
programming.
RESONATOR REQUIREMENTS
For correct function of the oscillator, the values
of R1 and C0 of the chosen resonator (quartz or PXE) must
be below the line shown in Fig.6a. The value of the parallel
resistor R0 must be less than 47 kΩ. The wiring between
chip and resonator should be kept as short as possible.
For certain combinations of data written to Port 2 (used for
control signal during parallel programming mode) the
Transparent mode may be incorrectly active during normal
operation of the microcontroller. In this case, a transition
on any of the Port 0 pins can influence the read out of the
on-chip program memory resulting in incorrect code
execution.
To avoid this problem, the InSysMode bit in the OTP
In-System Programming Register (SFR address DCH)
must be set in the start-up sequence of the program code.
MDA088
500
P87CL881H
handbook, halfpage
R1
(Ω)
Apart from preventing incorrect operation as described
above, the setting of this bit does not affect the normal
operation.
400
300
(1)
(2) (3)
6.6.2
200
MOVC INSTRUCTION LIMITATION
The ‘MOVC’ access to a data or program byte stored in
internal ROM/OTP-memory is inhibited while fetching
code from external program memory in roll-over mode.
100
Roll-over mode means that the CPU executes code out of
the external program memory because the program
counter exceeds the highest address for internal program
memory. The affected address range is FC00H to FFFFH.
0
20
0
40
60
Co (pF)
80
6.6.3
C1e and C2e are the external load capacitances; normally not needed
due to integrated load capacitances of typically 10 pF.
(1) C1e = C2e = 22 pF.
(2) C1e = C2e = 0 pF.
LOW VOLTAGE DETECTION
The LVDI bit (LVDCON.6) may be incorrectly set due to a
glitch on the LVD output when the LVD is enabled by
changing the bits LVDCON<3:0> from ‘0000’ to any value
within the range ‘0001’ to ‘0101’. If bit EA in register IEN0
is enabled, an unwanted interrupt may occur.
(3) C1e = C2e = 12 pF.
a. Resonator curves for 3.58 MHz.
A software workaround for this problem exist. During the
initialisation sequence:
handbook, halfpage
C1
L1
• Enable LVD by writing to register LVDCON
R1
• Enable LVD interrupt by writing to register IEN2
R0
• Clear the LVDI bit by writing to LVDCON a second time
• Set bit EA in register IEN0 (ensures LVDI to be cleared
after initialisation).
MGL137
C0
b. Resonator equivalent circuit.
Fig.6 Resonator requirements for the ACO.
1999 Apr 16
17
Philips Semiconductors
Product specification
Low-voltage microcontroller with 63-kbyte
OTP program memory and 2-kbyte RAM
P87CL881H
7 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VDD
supply voltage
−0.5
+4.0
V
VI
input voltage on any pin with respect to ground (VSS)
−0.5
VDD + 0.5
V
Ptot
total power dissipation
−
800
mW
Tstg
storage temperature
−65
+150
°C
8 DC CHARACTERISTICS
VDD = 2.7 to 3.6 V; VSS = 0 V; fxtal = 1 to 10 MHz; Tamb = −25 to +70 °C; all voltages with respect to VSS; unless
otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VDD
supply voltage
operating
2.7
−
3.6
V
RAM data retention in
Power-down mode
1.0
−
3.6
V
VPP
OTP programming voltage
IDD
supply current operating
VDD = 3 V; fxtal = 7 MHz; note 1
Tamb = 25 °C
IDD(id)
supply current Idle mode
VDD = 3 V; fxtal = 7 MHz; note 2
Tamb = 25 °C
IDD(pd)
supply current Power-down VDD = 3 V; Tamb = 25 °C; note 3
mode
POR and LVD enabled
POR and LVD disabled
IDD(block)
supply current per block:
−
13.0
V
−
4.8
mA
−
3.7
−
mA
−
−
0.7
mA
−
0.58
−
mA
−
2
5
µA
−
50
−
nA
−
220
−
µA
I2C-bus
−
180
−
µA
UART
−
180
−
µA
Timer T2
−
180
−
µA
Timer T0 or T1
−
10
−
µA
Watchdog
1999 Apr 16
VDD = 3 V; fxtal = 7 MHz; Tamb = 25 °C;
notes 4 and 5
12.5
−
18
Philips Semiconductors
Product specification
Low-voltage microcontroller with 63-kbyte
OTP program memory and 2-kbyte RAM
SYMBOL
PARAMETER
P87CL881H
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Inputs (ports, RST and PORENABLE)
−
VIL
LOW-level input voltage
notes 6 and 7
0
VIH
HIGH-level input voltage
note 6
0.8VDD −
0.2VDD V
VDD
V
IIL
LOW-level input current
(ports in Mode 1)
VIN = 0.4 V; note 8 and Fig.8
−
10
50
µA
IIL(T)
LOW-level input current;
HIGH-to-LOW transition
(ports in Mode 1)
VIN = 0.2VDD; note 8 and Fig.8
−
200
1000
µA
IILEAK
input leakage current (ports VSS ≤ VI ≤ VDD
in Mode 0 or 2)
−
−
1
µA
Outputs (ports and RST)
IOL
LOW-level output current;
except SDA and SCL
VOL = 0.4 V
2
−
−
mA
IOL2
LOW-level output current;
SDA and SCL
VOL = 0.4 V; note 9
3
−
−
mA
IOH
HIGH-level output current
except (push-pull options
only)
VOH = VDD − 0.4 V
2
−
−
mA
IRST
RST pull-up current source VDD = 3 V; VOH = VDD − 0.4 V
0.05
0.2
−
µA
−
0.6
2.5
µA
VDD = 3 V; VOH = VSS
POR (Power-on reset) for the LVD (Low Voltage Detection), see note 10
VPORH
trip level HIGH
(option 5 in “TELX family
specification”)
2.13
2.37
2.61
V
VPORL
trip level LOW
(option B in “TELX family
specification”)
−
1.30
−
V
ACO (Amplitude Controlled Oscillator)
VXTAL1
external clock signal
amplitude peak-to-peak
500
−
VDD
mV
zi(XTAL1)
input impedance on XTAL1
300
1000
−
kΩ
C1i; C2i
input capacitance on
XTAL1 and XTAL2
−
10
−
pF
90
100
110
µs
notes 5 and 11
In-System Programming for the OTP
tprog
program cycle time
tprog(security) program cycle time security note 12
180
200
220
µs
tver
verify cycle time
1
−
−
µs
tVPP(setup)
program voltage setup time
10
−
−
µs
tVPP(max)
maximum program voltage
time
cumulative for the product lifetime
−
−
60
s
IVPP
program voltage current
In-System Programming
−
−
40
mA
1999 Apr 16
19
Philips Semiconductors
Product specification
Low-voltage microcontroller with 63-kbyte
OTP program memory and 2-kbyte RAM
P87CL881H
Notes
1. The operating supply current is measured with all output pins disconnected; VIL = VSS; VIH = VDD; RST = VDD; XTAL1
driven with square wave; XTAL2 not connected; fetch of NOP instructions; all derivative blocks disabled.
2. The Idle mode supply current is measured with all output pins and RST disconnected; VIL = VSS; VIH = VDD; XTAL1
driven with square wave; XTAL2 not connected; all derivative blocks disabled.
3. The power-down current is measured with all output pins and RST disconnected; VIL = VSS; VIH = VDD; XTAL1 and
XTAL2 not connected.
4. The typical currents are only for the specific block. To calculate the typical power consumption of the microcontroller,
the current consumption of the CPU must be added. Example: the typical current consumption of the microcontroller
in operating mode with CPU, Watchdog and UART active can be calculated as (3.7 + 0.220 + 0.18) mA = 4.1 mA at
VDD = 3 V and fXTAL = 7 MHz.
5. Verified on sampling basis.
6. The input threshold voltage of P1.6/SCL and P1.7/SDA meet the I2C-bus specification. Therefore, an input voltage
below 0.3VDD will be recognized as a logic 0 and an input voltage above 0.7VDD will be recognized as a logic 1.
7. For pin PORENABLE the VIL max is 0.1VDD.
8. Not valid for pins SDA, SCL, RST and PORENABLE.
9. The maximum allowed load capacitance CL is in this case limited to around 200 pF.
10. The LVD is tested according to the “TELX family specification, Chapter - Low voltage detection”.
11. C1i/C2i are the total internal capacitances (including gate capacitance and leadframe capacitance).
12. Can also be done by two 100 µs pulses.
handbook, full pagewidth
MGL506
500 µA
I IL(T)
II
IIL
10 µA
0
0.3VDD
0.5VDD
Fig.7 Input current.
1999 Apr 16
20
VDD
Philips Semiconductors
Product specification
Low-voltage microcontroller with 63-kbyte
OTP program memory and 2-kbyte RAM
P87CL881H
MGL626
MGL625
1.0
5.3
handbook, halfpage
handbook, halfpage
IDD
(mA)
IDD(id)
(mA)
4.7
0.8
4.1
0.6
3.5
0.4
2.9
2.2
Fig.8
2.6
3
3.4
0.2
2.2
3.8
4.2
VDD (V)
Typical operating current as a function of
VDD; Tamb = 25 °C; fxtal = 7 MHz.
Fig.9
MDA085
4
handbook, halfpage
IDD(pd)
(µA)
(1)
3
(2)
2
1
(3)
(4)
0
0
(1)
(2)
(3)
(4)
1
2
3
VDD (V)
4
POR and LVD enabled (Tamb = 70 °C).
POR and LVD enabled (Tamb = 25 °C).
POR and LVD disabled (Tamb = 70 °C).
POR and LVD disabled (Tamb = 25 °C).
Fig.10 Typical power-down current as a function of
VDD.
1999 Apr 16
21
2.6
3
3.4
3.8
4.2
VDD (V)
Typical Idle current as a function of VDD;
Tamb = 25 °C; fxtal = 7 MHz.
Philips Semiconductors
Product specification
Low-voltage microcontroller with 63-kbyte
OTP program memory and 2-kbyte RAM
P87CL881H
9 AC CHARACTERISTICS
VDD = 3 V; VSS = 0 V; Tamb = −25 to +70 °C; CL = 50 pF for Port 0, ALE and PSEN; CL = 80 pF for all other outputs
unless otherwise specified. All values verified on sampling basis.
VARIABLE CLOCK
SYMBOL
PARAMETER
UNIT
MIN.
MAX.
External program memory
tLHLL
ALE pulse width
tCLK
−
ns
tAVLL
address valid to ALE LOW
0.5tCLK − 10
−
ns
tLLAX
address hold after ALE LOW
0.5tCLK
−
ns
tLLIV
ALE LOW to valid instruction in
−
2tCLK − 25
ns
tLLPL
ALE LOW to PSEN LOW
0.5tCLK
−
ns
tPLPH
PSEN pulse width
1.5tCLK
−
ns
tPLIV
PSEN LOW to valid instruction in
−
1.5tCLK − 35
ns
tPXIX
input instruction hold after PSEN
0
−
ns
tPXIZ
input instruction float after PSEN
−
0.5tCLK
ns
tAVIV
address to valid instruction in
−
2.5tCLK − 35
ns
tPLAZ
PSEN LOW to address float
−
5
ns
External data memory
tRLRH
RD pulse width
3tCLK
−
ns
tWLWH
WR pulse width
3tCLK
−
ns
tAVLL
address valid to ALE LOW
0.5tCLK
−
ns
tLLAX
address hold after ALE LOW
0.5tCLK
−
ns
tRLDV
RD LOW to valid data in
−
2.5tCLK
ns
tRHDX
data hold after RD
0
−
ns
tRHDZ
data float after RD
−
tCLK
ns
tLLDV
ALE LOW to valid data in
−
4tCLK
ns
tAVDV
address to valid data in
−
4.5tCLK − 30
ns
tLLWL
ALE LOW to RD or WR LOW
1.5tCLK − 15
1.5tCLK + 15
ns
tAVWL
address valid to RD or WR LOW
2tCLK
−
ns
tWHLH
RD or WR HIGH to ALE HIGH
0.5tCLK − 5
0.5tCLK + 5
ns
tQVWX
data valid to WR transition
0.5tCLK
−
ns
tQVWH
data valid time WR HIGH
3.5tCLK
−
ns
tWHQX
data hold after WR
0.5tCLK
−
ns
tRLAZ
RD LOW to address float
−
0
ns
1999 Apr 16
22
Philips Semiconductors
Product specification
Low-voltage microcontroller with 63-kbyte
OTP program memory and 2-kbyte RAM
P87CL881H
one machine cycle
handbook, full pagewidth
S1
P1 P2
S2
P1 P2
S3
P1 P2
S4
P1 P2
one machine cycle
S5
P1 P2
S6
P1 P2
S1
P1 P2
S2
P1 P2
S3
P1 P2
S4
P1 P2
S5
P1 P2
S6
P1 P2
XTAL1
INPUT
ALE
dotted lines
are valid when
RD or WR are
active
PSEN
only active
during a read
from external
data memory
RD
only active
during a write
to external
data memory
WR
external
program
memory
fetch
BUS
(PORT 0)
inst.
in
PORT 2
read or
write of
external data
memory
BUS
(PORT 0)
PORT 2
PORT
OUTPUT
address
A0 - A7
inst.
in
address A8 - A15
inst.
in
address
A0 - A7
address
A0 - A7
inst.
in
address A8 - A15
inst.
in
address
A0 - A7
address A8 - A15
address
A0 - A7
inst.
in
address A8 - A15
address A8 - A15
address
A0 - A7
data output or data input
address A8 - A15 or Port 2 out
old data
address
A0 - A7
address A8 - A15
new data
PORT
INPUT
sampling time of I/O port pins during input (including INT0 and INT1)
SERIAL
PORT
CLOCK
MGA180
Fig.11 Instruction cycle timing.
1999 Apr 16
23
Philips Semiconductors
Product specification
Low-voltage microcontroller with 63-kbyte
OTP program memory and 2-kbyte RAM
P87CL881H
t CY
handbook, full pagewidth
t LLIV
t LHLL
ALE
t LLPL
t PLPH
PSEN
t LLAX
t AVLL
PORT 0
t PLIV
t PXIZ
A0 to A7
inst. input
t PLAZ
A0 to A7
inst. input
t PXIX
t AVIV
PORT 2
address A8 to A15
address A8 to A15
MGA176
Fig.12 Read from external program memory.
t CY
handbook, full pagewidth
t LHLL
t LLDV
t WHLH
ALE
PSEN
t LLWL
t RLRH
RD
t AVLL
t LLAX
t RHDZ
t RLDV
t AVWL
PORT 0
A0 to A7
t RHDX
data input
t RLAZ
tAVDV
PORT 2
address A8 to A15 (DPH) or Port 2
MGA177
Fig.13 Read from external data memory.
1999 Apr 16
24
Philips Semiconductors
Product specification
Low-voltage microcontroller with 63-kbyte
OTP program memory and 2-kbyte RAM
P87CL881H
t CY
handbook, full pagewidth
t LHLL
t WHLH
ALE
PSEN
t LLWL
t WLWH
WR
t AVWL
t AVLL
t LLAX
t QVWH
t WHQX
t QVWX
PORT 0
A0 to A7
data output
PORT 2
address A8 to A15 (DPH) or Port 2
MGA178
Fig.14 Write to external data memory.
9.1
AC testing
AC testing inputs are driven at 2.4 V for a HIGH level and 0.45 V for a LOW level. Timing measurements are taken at
2.0 V for a HIGH level and 0.8 V for a LOW level, see Fig.15a. The float state is defined as the point at which a Port 0
pin sinks 3.2 mA or sources 400 µA at the voltage test levels, see Fig.15b.
handbook, full pagewidth
VOH(min)
VOL(max)
VIH(min)
VIL(max)
MGL620
a. AC inputs during testing are driven at VOH(min) for a logic 1 and VOL(max) for a logic 0. Timing measurements
are made at VIH(min) for a logic 1 and VIL(max) for a logic 0.
handbook, full pagewidth
VLOAD = 0.5 VDD
VLOAD − 0.1 V
VOH − 0.1 V
VLOAD − 0.1 V
VOL − 0.1 V
MGL619
b. For timing purposes, a port is no longer floating when a 100 mV change from load voltage occurs and begins
to float when a 100 mV change from the loaded VOH/VOL level occurs. IOH/IOL > 1.6 mA.
Fig.15 AC testing input, output waveform (a) and float waveform (b).
1999 Apr 16
25
Philips Semiconductors
Product specification
Low-voltage microcontroller with 63-kbyte
OTP program memory and 2-kbyte RAM
P87CL881H
10 PACKAGE OUTLINE
LQFP44: plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm
SOT389-1
c
y
X
33
23
A
34
22
ZE
e
Q
E HE
A A2
(A 3)
A1
w M
θ
pin 1 index
bp
44
Lp
L
12
detail X
11
1
ZD
e
v M A
w M
bp
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
mm
1.60
0.15
0.05
1.45
1.35
0.25
0.45
0.30
c
D (1)
E (1)
e
HD
HE
L
0.20 10.10 10.10
12.15 12.15
1.0
0.80
0.12 9.90 9.90
11.85 11.85
Lp
Q
v
w
y
0.75
0.45
0.70
0.57
0.20
0.20
0.10
Z D (1) Z E (1)
θ
1.14
0.85
7
0o
1.14
0.85
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
95-12-19
SOT389-1
1999 Apr 16
EUROPEAN
PROJECTION
26
o
Philips Semiconductors
Product specification
Low-voltage microcontroller with 63-kbyte
OTP program memory and 2-kbyte RAM
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
11 SOLDERING
11.1
Introduction to soldering surface mount
packages
• For packages with leads on two sides and a pitch (e):
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
11.2
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
11.3
11.4
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
1999 Apr 16
P87CL881H
27
Philips Semiconductors
Product specification
Low-voltage microcontroller with 63-kbyte
OTP program memory and 2-kbyte RAM
11.5
P87CL881H
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
REFLOW(1)
WAVE
BGA, SQFP
not suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not
PLCC(3),
SO, SOJ
suitable
suitable(2)
suitable
suitable
suitable
LQFP, QFP, TQFP
not recommended(3)(4)
suitable
SSOP, TSSOP, VSO
not recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
1999 Apr 16
28
Philips Semiconductors
Product specification
Low-voltage microcontroller with 63-kbyte
OTP program memory and 2-kbyte RAM
P87CL881H
12 DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
13 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
14 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1999 Apr 16
29
Philips Semiconductors
Product specification
Low-voltage microcontroller with 63-kbyte
OTP program memory and 2-kbyte RAM
NOTES
1999 Apr 16
30
P87CL881H
Philips Semiconductors
Product specification
Low-voltage microcontroller with 63-kbyte
OTP program memory and 2-kbyte RAM
NOTES
1999 Apr 16
31
P87CL881H
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Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1999
SCA63
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
465008/00/01/pp32
Date of release: 1999 Apr 16
Document order number:
9397 750 05026