PHILIPS PCA5007H

INTEGRATED CIRCUITS
DATA SHEET
PCA5007
Pager baseband controller
Product specification
File under Integrated Circuits, IC17
1998 Oct 07
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
CONTENTS
14
APPENDIX 1: SPECIAL MODES OF THE
PCA5007
Overview
OTP parallel programming mode
Test modes
1
FEATURES
2
ORDERING INFORMATION
3
GENERAL DESCRIPTION
14.1
14.2
14.3
4
BLOCK DIAGRAM
15
5
PINNING
APPENDIX 2: THE PARALLEL
PROGRAMMING MODE
6
FUNCTIONAL DESCRIPTION
6.1
6.2
6.3
Introduction
General description
Entering the parallel programming mode
Address space
Single byte programming
Multiple byte programming
High voltage timing
OTP test modes
Signature bytes
Security
16
APPENDIX 3: OS SHEET
17
APPENDIX 4: BONDING PAD LOCATIONS
18
PACKAGE OUTLINE
19
SOLDERING
19.1
19.2
19.3
19.4
Introduction
Reflow soldering
Wave soldering
Repairing soldered joints
20
DEFINITIONS
6.18
6.19
6.20
6.21
6.22
General
CPU timing
Overview on the different clocks used within
the PCA5007
Memory organization
Addressing
I/O facilities
Timer/event counters
I2C-bus serial I/O
Serial interface SIO0: UART
76.8 kHz oscillator
Clock correction
6 MHz oscillator
Real-time clock
Wake-up counter
Tone generator
Watchdog timer
2 or 4-FSK demodulator, filter and clock
recovery circuit
AFC-DAC
Interrupt system
Idle and power-down operation
Reset
DC/DC converter
15.1
15.2
15.3
15.4
15.5
15.6
15.7
15.8
15.9
15.10
21
LIFE SUPPORT APPLICATIONS
22
PURCHASE OF PHILIPS I2C COMPONENTS
7
INSTRUCTION SET
7.1
Instruction Map
8
LIMITING VALUES
9
EXTERNAL COMPONENTS
10
DC CHARACTERISTICS
11
AC CHARACTERISTICS
12
CHARACTERISTIC CURVES
13
TEST AND APPLICATION INFORMATION
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
6.17
1998 Oct 07
2
Philips Semiconductors
Product specification
Pager baseband controller
1
PCA5007
FEATURES
• Operating temperature from: −10 to +55 °C
• Supply voltage range with on-chip DC/DC converter:
0.9 to 1.6 V
• Low operating and standby current consumption
• On-chip DC/DC converter generates the supply voltage
for the PCA5007 and external circuitry from a single cell
battery
• Decoding of paging data
– POCSAG or APOC phase 1, advanced high speed
paging protocols are also supported
• Battery low detector
– Supported data rates: 1200, 1600, 2400 and 3200
symbols/s using a 76.8 kHz crystal oscillator
• Low electromagnetic noise emission
• Full static asynchronous 80C51 CPU (8-bit CPU)
– Demodulation of Zero-IF I and Q 4 or 2 level FSK
input or direct data input
• Recovery from lowest power standby Idle mode to full
speed operation within microseconds
– Noise filtering of data input and symbol clock
reconstruction
• 20 kbytes of One-Time Programmable (OTP) memory
and 1-kbyte of RAM on-chip
– De-interleaving, error checking and correction, sync
word detection address recognition, buffering and
more is done in software
• 27 general purpose I/O port lines (4 ports with interrupt
possibility)
• 15 different interrupt sources with selectable priority
– All user functions (keypad interface, alerter control,
display, etc.) are implemented in software.
• 2 standard timer/event counters T0 and T1
• Musical tone generator for beeper, controlled by the
microcontroller
• I2C-bus serial port (single 100 kHz master transmitter
and receiver)
• Watchdog timer
• Subset of standard UART serial port (8 and 9-bit
transmission at 4800/9600 bits/s)
• 48-pin LQFP package.
• 76.8 kHz crystal oscillator reference with digital clock
correction for real time and paging protocol
• Real-Time Clock (RTC)
• Receiver and synthesizer control
– Receiver control by software through general
purpose I/Os
– Synthesizer control by software through general
purpose I/Os
– 6-bit DAC for AFC to the receiver local oscillator
– Dedicated protocol timer.
2
ORDERING INFORMATION
TYPE
NUMBER(1)
PACKAGE
PRODUCT TYPE
PCA5007H/XXX pre-programmed OTP
NAME
DESCRIPTION
VERSION
LQFP48
plastic low profile quad flat package; 48 leads;
body 7 × 7 × 1.4 mm
SOT313-2
Note
1. Please refer to the Order Entry Form (OEF) for this device for the full type number to use when ordering. This type
number will also specify the required OTP code.
1998 Oct 07
3
Philips Semiconductors
Product specification
Pager baseband controller
3
PCA5007
The instruction set of the PCA5007 is based on that of the
80C51. The PCA5007 also functions as an arithmetic
processor having facilities for both binary and BCD
arithmetic plus bit-handling capabilities. The instruction set
consists of over 100 instructions: 49 one-byte,
46 two-byte, and 16 three-byte.
GENERAL DESCRIPTION
The PCA5007 pager baseband controller is manufactured
in an advanced CMOS/OTP technology.
The PCA5007 is an 8-bit microcontroller especially suited
for pagers. For this purpose, features such as a
4 or 2 level FSK demodulator, filter, clock recovery,
protocol timer, DC/DC converter optimized for small
paging systems and RTC are integrated on-chip.
This data sheet details the properties of the PCA5007.
For details of the I2C-bus functions see “The I2C-bus and
how to use it”. For details on the basic 80C51 properties
and features see “Data Handbook IC20”.
The device is optimized for low power consumption.
The PCA5007 has several software selectable modes for
power reduction: Idle and power-down mode of the
microcontroller, and standby and off mode of the DC/DC
converter.
1998 Oct 07
4
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ZERO-IF
4L DEMODULATOR
VPP
AFCOUT
PORT
CONTROL
DAC
RAM
AT
8
P2
5
PROCESSOR
80C51
4
P3
7
P1
TIMER 0
INTERRUPT
CONTROL
VIND
DC/DC
CONVERTER
P0
OTP/ROM
TONE
GENERATOR
6 MHz
OSCILLATOR
VDD(DC)
VSS(DC)
8
P0
WATCHDOG
Philips Semiconductors
SYMBOL SAMPLING
CLOCK RECOVERY
Pager baseband controller
BLOCK DIAGRAM
DIGITAL
FILTER
2
4
andbook, full pagewidth
1998 Oct 07
I(D1), Q(D0)
TIMER 1
P2
P3
(T0, T1,
INT0, INT1)
P1
(SDA, SCL,
RXD, TXD)
UART SIO
various clocks
VBAT
2
VDD
VSS 2
RESETIN
MODE AND
TEST CONTROL
WAKE-UP
RTC
CLOCK
GENERATOR
CLOCK
CORRECTION
76.8 kHz
OSCILLATOR
MGR107
ALE, PSEN, EA TCLK
Fig.1 Block diagram.
XTL1
PCA5007
supplied by VBAT
3
XTL2
Product specification
RESOUT
I2C SIO
POWER
CONTROLLER
Philips Semiconductors
Product specification
Pager baseband controller
5
PCA5007
PINNING
SYMBOL
PIN
TYPE
DESCRIPTION
P3.4 and P3.5
1 and 2
I/O
Port 3: P3.4 and P3.5 are configured as push-pull output only (option 3R; see
Section 6.6). Using the software input commands or the secondary port
function is possible by driving the port 3 output lines accordingly:
P3.4 secondary function: T0 (counter input for T0)
P3.5 secondary function: T1 (counter input for T1)
AT
3
O
Beeper high volume control output. Used to drive external bipolar transistor.
P2.0 to P2.7
4 to 11
I/O
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups (option 1S;
see Section 6.6.3). As inputs, port 2 pins that are externally pulled LOW will
source current because of the internal pull-ups. (see Chapter “DC
characteristics”: Ipu). Port 2 emits the high-order address byte during fetches
from external program memory. In this application, it uses strong internal
pull-ups when emitting logic 1s. Port 2 is also used to control the parallel
programming mode of the on-chip OTP.
P0.0 to P0.4
12 to 16
I/O
Port 0: Port 0 is a bidirectional I/O port with internal pull-ups (option 1S; see
Section 6.6.3). Port 0 pins that have logic 1s written to them are pulled HIGH by
the internal pull-ups and can be used as inputs. Port 0 is also the multiplexed
low-order address and data bus during access to external program and data
memory. In this application, it uses strong internal pull-ups when emitting 1s.
Port 0 also outputs the code bytes during OTP programming verification.
VDDA
17
S
supply voltage for the analog parts of the PCA5007 and the
receiver/synthesizer control signals (Port 0 pins)
AFCOUT
18
O
Buffered analog output of DAC for automatic receiver frequency control.
A voltage proportional to the offset of the receiver frequency can be generated.
Can be enabled/disabled by software.
I(D1)
19
I
input from receiver: may be demodulated NRZ signal or Zero-IF. In phase
limited signal
Q(D0)
20
I
input from receiver: may be demodulated NRZ signal or Zero-IF, Quadrature
limited signal.
ground signal reference (for the analog parts) (connected to substrate)
21
S
P0.5 to P0.7
22 to 24
I/O
Port 0: Port 0 is a bidirectional I/O port with internal pull-ups (option 1R,1R and
1S; see Section 6.6.3). Port 0 pins that have logic 1s written to them are pulled
HIGH by the internal pull-ups and can be used as inputs. Port 0 is also the
multiplexed low-order address and data bus during access to external program
and data memory. In this application, it uses strong internal pull-ups when
emitting 1s. Port 0 also outputs the code bytes during OTP programming
verification.
P1.0 to P1.2
25 to 27
I/O
Port 1: Port 1 is an 8-bit quasi bidirectional I/O port with internal pull-ups.
Port 1 pins that have logic 1s written to them are pulled HIGH by the internal
pull-ups and can be used as inputs. As inputs, port 1 pins that are externally
pulled LOW will source current because of the internal pull-ups (see
Chapter “DC characteristics”: Ipu). P1.0 to P1.2 have external interrupts INT2 to
INT4 assigned.
28
I/O
If the UART is disabled (ENS1 in S1CON.4 = 0) then P1.3 can be used as
general purpose P1 port pin. If the UART function is required, then a logic 1
must be written to P1.3. This I/O then becomes the RXD/data line of the UART.
VSSA
P1.3
1998 Oct 07
6
Philips Semiconductors
Product specification
Pager baseband controller
SYMBOL
PCA5007
PIN
TYPE
DESCRIPTION
P1.4
29
I/O
If the UART is disabled (ENS1 in S1CON.4 = 0) then P1.4 can be used as
general purpose P1 port pin. If the UART function is required, then a logic 1
must be written to P1.4. This I/O then becomes the TXD/clock line of the UART.
P1.4 has external interrupt INT6 (X6) assigned.
VSS
30
S
ground (connected to substrate)
VDD
31
S
supply voltage for the core logic and most peripheral drivers of the PCA5007
(see VDDA)
ALE
32
I/O
Address Latch Enable: output pulse for latching the low byte of the address
during an access to external memory.
PSEN
33
I/O
Program Store Enable: the read strobe to external program memory. When
the device is executing code from the external program memory, PSEN is
activated for each code byte fetch.
EA
34
I/O
External Access Enable: EA must be externally held LOW to enable the
device to fetch code from external program memory locations 0000H to 4FFFH.
If EA is held HIGH, the device executes from internal program memory unless
the program counter contains an address greater the 4FFFH (20 kbytes).
TCLK
35
I
clock input for use as timing reference in external access mode and emulation
VPP
36
S
Programming voltage (12.5 V) for the OTP. Is connected to VSS in the
application.
P1.6(SCL)
37
I/O
If the I2C-bus is disabled (ENS1 in S1CON.6 = 0) then P1.6 can be used as
general purpose P1 port pin. If the I2C-bus function is required, then a logic 1
must be written to P1.6. This I/O then becomes the clock line of the I2C-bus.
P1.6 is equipped with an open-drain output buffer. The pin has no clamp diode
to VDD.
P1.7(SDA)
38
I/O
If the I2C-bus is disabled (ENS1 in S1CON.6 = 0) then P1.7 can be used as
general purpose P1 port pin. If the I2C-bus function is required, then a logic 1
must be written to P1.7. This I/O then becomes the data line of the I2C-bus.
P1.7 is equipped with an open-drain output buffer. The pin has no clamp diode
to VDD.
XTL2
39
O
output from the current source oscillator amplifier
XTL1
40
I
input to the inverting oscillator amplifier and time reference for pager decoder,
real-time clock and timers
VBAT
41
S
Supply terminal from battery. Is used for supplying parts of the chip that need to
operate at all times.
VDD(DC)
42
O
Supply voltage output of the DC/DC converter. An external capacitor is
required.
VIND
43
I
Current input for the DC/DC converter. The booster inductor needs to be
connected externally.
VSS(DC)
44
S
ground (connected to substrate) OTP
RESETIN
45
I
Schmitt trigger reset input for the PCA5007. External R and C need to be
connected to the battery supply. All internal storage elements (except
microcontroller RAM) are initialized when this input is activated.
1998 Oct 07
7
Philips Semiconductors
Product specification
Pager baseband controller
SYMBOL
RESOUT
P3.2 to P3.3
PCA5007
PIN
TYPE
DESCRIPTION
46
O
Monitor output for the emulation system. Is active (LOW) whenever a reset is
applied to the microcontroller. (a reset can be forced by RESETIN, watchdog or
wake-up from DC/DC converter in off mode). A reset to the microcontroller
initializes all SFRs and port pins; it has no impact on the blocks operating from
VBAT.
47 and 48
I/O
Port 3: P3.2 and P3.3 are configured as push-pull output only (option 3R; see
Section 6.6). Using the software input commands or the secondary port
function is possible by driving the port 3 output lines accordingly:
P3.2 secondary function: INT0 (external interrupt 0)
P3.4
37 P1.6
38 P1.7
39 XTL2
40 XTL1
41 VBAT
42 VDD(DC)
43 VIND
44 VSS(DC)
45 RESETIN
47 P3.2
48 P3.3
handbook, full pagewidth
46 RESOUT
P3.3 secondary function: INT1 (external interrupt 1)
36 VPP
1
P3.5 2
35 TCLK
34 EA
AT 3
P2.0 4
33 PSEN
P2.1 5
32 ALE
P2.2 6
31 VDD
PCA5007H
P2.3 7
30 VSS
P2.4 8
29 P1.4
P2.5 9
28 P1.3
P2.6 10
27 P1.2
Fig.2 Pin configuration.
1998 Oct 07
8
P0.7 24
P0.6 23
P0.5 22
VSSA 21
Q(D0) 20
I(D1) 19
VDDA 17
AFCOUT 18
P0.4 16
P0.3 15
25 P1.0
P0.2 14
26 P1.1
P0.0 12
P0.1 13
P2.7 11
MGR108
Philips Semiconductors
Product specification
Pager baseband controller
6
PCA5007
TANGRAM is a high level programming language which
allows the description of parallel and sequential processes
that can be compiled into logic on silicon. The CPU has the
following features:
FUNCTIONAL DESCRIPTION
6.1
General
The PCA5007 contains a high-performance CMOS
microcontroller and the required peripheral circuitry to
implement high-speed pagers for the modern paging
protocols. For this purpose, features such as FSK
demodulator, protocol timer, real-time clock and DC/DC
converter have been integrated on-chip.
• No clock is needed. Every function within the CPU is self
timed and always runs at the maximum speed that a
given silicon die under the current operating conditions
(supply voltage and temperature) allows.
• The CPU fetches opcodes with maximum speed until a
special mode (e.g. Idle) is entered that stops this
sequence.
The microcontroller embedded within the PCA5007
implements the standard 80C51 architecture and supports
the complete instruction set of the 80C51 with all
addressing modes.
• Only bytes that are required are fetched from the
program memory. The dummy read cycles which exist in
the standard 80C51 have been omitted to save power.
The PCA5007 contains 20 kbytes of OTP program
memory; 1-kbyte of static read/write data memory,
27 I/O lines, two 16-bit timer/event counters, a
fifteen-source two priority-level, nested interrupt structure
and on-chip oscillator and timing circuit.
• To further speed up the execution of a program, the next
sequential byte is always fetched from the code memory
during the execution of the current command. In the
event of jumps the prefetched byte is discarded.
• Since no clocks are required, the operating power
consumption is essentially lower compared to
conventional architectures and Idle power consumption
is reduced to nearly zero (leakage only).
The PCA5007 devices have several software selectable
modes of reduced activity for power reduction; Idle for the
CPU and standby or off for the DC/DC converter. The Idle
mode freezes the CPU while allowing the RAM, timers,
serial I/O and interrupt system to continue functioning.
The standby mode for the DC/DC converter allows a high
efficiency of the latter at low currents and the off mode
reduces the supply voltage to the battery level. In the off
mode the RAM contents are preserved, the real-time clock
and protocol timer are operating, but all other chip
functions are inoperative.
• Clocks are only required as timing references for
timers/counters and for generating the timing to the
off-chip world.
6.2.2
When code is executed in internal access mode (EA = 1),
the opcodes are fetched from the on-chip OTP. The OTP
is a self timed block which delivers data at maximum
speed. This is the preferred operating mode of the
PCA5007.
Two serial interfaces are provided on-chip; a UART serial
interface and an I2C-bus serial interface. The I2C-bus
serial interface has byte oriented master functions allowing
communication with a whole family of I2C-bus compatible
slave devices.
6.2
6.2.3
CPU timing
When code is executed in external access mode (EA = 0),
the opcodes are fetched from an off-chip memory using
the standard signals ALE, PSEN and P0, P2 for
multiplexed data and address information. In this mode the
identical hardware configurations as for a standard 80C51
system can be used, even if the timing for ALE and PSEN
is slightly different because it is generated from an internal
oscillator.
BASICS
The implementation of the CPU of the PCA5007 as a block
in handshake technology has become possible through
the TANGRAM tool set, developed in the Philips Natlab in
Eindhoven.
1998 Oct 07
EXECUTION OF PROGRAMS FROM EXTERNAL CODE
MEMORY
The internal CPU timing of the PCA5007 is completely
different to other implementations of this core. The CPU is
realized in asynchronous handshaking technology, which
results in extremely low power consumption and low EMC
noise generation.
6.2.1
EXECUTION OF PROGRAMS FROM INTERNAL CODE
MEMORY
9
Philips Semiconductors
Product specification
Pager baseband controller
6.3
PCA5007
Overview on the different clocks used within the PCA5007
Figure 3 gives an overview on the clocks available within the PCA5007 for the different functions.
handbook, full pagewidth
76.8 kHz
TONE GENERATOR
(both clock edges
are used)
76.8 kHz
UART
(both clock edges
are used)
76.8 kHz
TIMER 1
(both clock edges
are used)
76.8 kHz
OSCILLATOR
76.8 kHz
DEMODULATOR/
CLOCK RECOVERY
÷150
256 Hz
DIVIDER
÷9600
FOR
THE
DIFFERENT ÷2400
FREQUENCIES
4 Hz
CORR
CLOCK
CORRECTION
CCON.7
38.4 kHz
÷4
TIMER 0
REAL-TIME CLOCK
16 Hz
9.6 kHz
WATCHDOG
WAKE-UP COUNTER
76.8 kHz
6 MHz
6 MHz
OSCILLATOR
DIVIDER
400 kHz
OS6CON.7
6 MHz
OS6CON.7
DC/DC CONVERTER
I2C-BUS
MICROCONTROLLER
OUTPUT AND
EXTERNAL ACCESS
MGR109
Fig.3 Overview on the clocks used within the PCA5007.
1998 Oct 07
10
Philips Semiconductors
Product specification
Pager baseband controller
6.4
PCA5007
Memory organization
6.4.2
The PCA5007 has a program memory (OTP) plus data
memory (RAM) on-chip. The device has separate address
spaces for program and data memory (see Fig.4). If ports
P0 and P2 are not used as I/O signals these pins can be
used to address up to 64 kbytes of external program
memory. In this case, the CPU generates the latch signal
(ALE) for an external address latch and the read strobe
(PSEN) for external program memory. External data
memory is not supported.
6.4.1
DATA MEMORY
The PCA5007 contains 1024 bytes of internal RAM
(consisting of 256 bytes standard RAM and 768 bytes
AUX-RAM) and Special Function Registers (SFRs).
Figure 4 shows the internal data memory space divided
into the lower 128 bytes the upper 128 bytes and the SFR
space and 768 bytes auxiliary RAM. Internal RAM
locations 0 to 127 are directly and indirectly addressable.
Internal RAM locations 128 to 255 are only indirectly
addressable. The SFR locations 128 to 255 are only
directly addressable and the auxiliary RAM is indirectly
addressable as external RAM (MOVX). External Data
Memory (EDM) is not supported.
PROGRAM MEMORY
After reset the CPU begins execution of the program
memory at location 0000H. The program memory can be
implemented in either internal OTP or external memory.
If the EA pin is strapped to VDD, then program memory
fetches are directed to the internal program memory. If the
EA pin is strapped to VSS, then program memory fetches
are directed to external memory.
6.4.3
SPECIAL FUNCTION REGISTERS
The second 128 bytes are the address locations of the
special function registers. Table 1 shows the special
function registers space. The SFRs include the port
latches, timers, peripheral control, serial I/O registers, etc.
These registers can only be accessed by direct
addressing. There are 128 bit addressable locations in the
SFR address space (those SFRs whose addresses are
divisible by eight).
Programming the on-chip OTP is detailed in Chapter 15.
Usually Philips will deliver programmed parts to a
customer. Supply of blank engineering samples is
possible, but then Philips cannot give any guarantee on
the programmability and retention of the program memory.
FFFFH
handbook, full pagewidth
EXTERNAL
2FFH
FFH
4FFFH
DIRECT
INDIRECT
ADDRESSING ADDRESSING
INTERNAL
(EAN = 1)
EXTERNAL
(EAN = 0)
80H
7FH
00H
INDIRECT AND
DIRECT
ADDRESSING
INDIRECT
ADDRESSING
WITH DPTR
INDIRECT
ADDRESSING
WITH Ri, DPTR
100H
0FFH
000H
0
Internal RAM
SFR space
PROGRAM MEMORY
Internal XRAM
External XRAM
is not supported
DATA MEMORY
MGR110
Fig.4 Memory map.
1998 Oct 07
11
Philips Semiconductors
Product specification
Pager baseband controller
6.5
PCA5007
• Special function registers through Direct
Addressing
• Program memory Look-Up Tables (LUTs) through
Base-Register plus Index-Register-Indirect.
The PCA5007 has five methods for addressing source
operands:
• Register
The PCA5007 is classified as an 8-bit device since the
internal ROM, RAM, Special Function Registers (SFRs),
Arithmetic Logic Unit (ALU) and external data bus are all
8 bits wide. It performs operations on bit, nibble, byte and
double-byte data types.
• Direct
• Register-Indirect
• Immediate
• Base-Register plus Index-Register-Indirect.
Facilities are available for byte transfer, logic and integer
arithmetic operations. Data transfer, logic and conditional
branch operations can be performed directly on Boolean
variables to provide excellent bit handling.
The first three methods can be used for addressing
destination operands. Most instructions have a
‘destination/source’ field that specifies the data type,
addressing methods and operands involved. For
operations other than MOVs, the destination operand is
also a source operand.
While the PCA5007 is executing code from the internal
memory, ALE and PSEN pins are inactive with
ALE = LOW and PSEN = HIGH.
Access to memory addressing is as follows:
External XRAM is not supported for this device, since
P3.7 (RD) and P3.6 (WR) pins are not available. If the
external XRAM is accessed accidentally, no PSEN or ALE
cycle is done and actual P0 values are read. Internal
XRAM access is not visible from outside the chip (no ALE,
PSEN, P0 and P2 activity).
• Registers in one of the four 8-register banks through
Register-Direct or Register-Indirect
• Maximum 1024 bytes of internal data RAM through
Direct or Register-Indirect
– Bytes 0 to 127 of internal RAM may be addressed
directly/indirectly. Bytes 128 to 255 of internal RAM
share their address location with the SFRs and so
may only be addressed Register-Indirect as data
RAM.
– Bytes 0 to 768 of AUX-RAM can only be addressed
indirectly via MOVX. Bytes 256 to 768 can only be
addressed using indirect addressing with the data
pointer, while bytes 0 to 255 may be also addressed
using R0 or R1.
1998 Oct 07
12
Philips Semiconductors
Product specification
Pager baseband controller
Table 1
ADDR
(HEX)
PCA5007
Special Function Registers Overview; note 1
NAME
7
6
5
4
3
2
1
0
R/W
RESET
VALUE
COMMENT
bit addressable
80
P0
R/W
9FH
81
SP
R/W
07H
82
DPL
R/W
00H
83
DPH
R/W
00H
87
PCON
SMOD
XRE
ENIS
−
GF1
GF0
PD
IDL
R/W
00H
88
TCON
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
R/W
00H
GATE
C/T
M1
M0
GATE
C/T
M1
M0
bit addressable
89
TMOD
R/W
00H
8A
TL0
R/W
00H
8B
TL1
R/W
00H
8C
TH0
R/W
00H
8D
TH1
R/W
00H
90
P1
R/W
FFH
R/W
00H
R/W
00H
R/W
00H
note 2
ENB
−
−
−
−
−
−
92
TGCON
93
TG0
94
WUCON
95
WUC0
R/W
00H
note 2
96
WUC1
R/W
00H
note 2
98
S0CON
R/W
00H
bit addressable
RUN
CLK2
bit addressable
WUP
SM0
SM1
ENB
−
TEST
−
CPL
REN
Z1
Z0
TB8
RB8
LOAD
TI
SET
RI
99
S0BUF
9E
AFCON
A0
P2
A5
WDCON
COND
WD3
WD2
WD1
WD0
−
−
LD
A8
IEN0/IE
EA
EWU
ES1
ES0
ET1
EX1
ET0
EX0
B0
P3
B8
IP/IP0
AFC5 AFC4 AFC3 AFC2
−
PWU
PS1
PS0
PT1
PX1
AFC1
PT0
R/W
00H
AFC0 R/W
00H
R/W
FFH
R/W
00H
PX0
bit addressable
R/W
00H
bit addressable
R/W
C3H
bit addressable
R/W
00H
bit addressable
C0
IRQ1
IQ9
IQ8
IQ7
IQ6
IQ5
IQ4
IQ3
IQ2
R/W
00H
bit addressable
CD
RTCON
MIN
−
−
−
−
W/R
LOAD
SET
R/W
00H
note 2
CE
RTC0
R/W
00H
note 2
R/W
00H
bit addressable
BLI(3) R/W
03H
D0
PSW
D1
DCCON0
D2
DCCON1
P(3)
CY
AC
F0
RS1
RS0
OV
OFF
SBY
RXE
SBLI
−
−
STB(3)
VBG1 VBG0 VLO1 VLO0
−
−
−
SF2
SF1
SF0
ENB
−
−
R/W
00H
MFR R/W
00H
D3
OS6CON
D4
OS6M0
D8
S1CON
−
ENS1
STA
STO
SI
AA
−
−
SC4
SC3
SC2
SC1
SC0
0
0
0
SF4
SF3
R
00H
R/W
00H
bit addressable
D9
S1STA
R
78H
DA
S1DAT
R/W
00H
E0
ACC
R/W
00H
bit addressable
E8
IEN1
bit addressable
E9
IX1
1998 Oct 07
EMIN
EWD
EDC
EX6
ESC
EX4
EX3
EX2
R/W
00H
IL9
IL8
IL7
IL6
IL5
IL4
IL3
IL2
R/W
00H
13
Philips Semiconductors
Product specification
Pager baseband controller
ADDR
(HEX)
NAME
PCA5007
7
6
5
4
3
2
1
0
R/W
RESET
VALUE
ENB
M
−
RES
LEV
BD2
BD1
BD0
R/W
00H
AVG1
AVG0
R
00H
B1
B0
R/W
00H
R/W
00H
EC
DMD0
ED
DMD1
ENA
EE
DMD2
ENC
EF
DMD3
F0
B
F8
IP1
PMIN
PWD
FC
CCON
ENB
PLUS TEST CIV17 CIV16
FD
CC0
CIV7
CIV6
FE
CC1
AVG6 AVG5 AVG4 AVG3 AVG2
−
−
BF
TEST
B2
ENA is RW
R/W
00H
bit addressable
PX4
PX3
PX2
R/W
00H
bit addressable
−
BYPAS
SET
R/W
00H
CIV2
CIV1
CIV0 R/W
00H
CIV15 CIV14 CIV13 CIV12 CIV11 CIV10
CIV9
CIV8 R/W
00H
PDC
CIV5
PX6
CIV4
PSC
CIV3
Notes
1. An empty field in this map indicates a bit that can be read from or written to by software.
2. Value only reset with RESETIN and not or only partly with an off-restart sequence.
3. This bit cannot be changed by writing to it.
7FH
handbook, halfpage
30H
2FH
bit-addressable space
(bit addresses 0 to 7F)
R7
20H
1FH
R0
R7
18H
17H
R0
R7
10H
0FH
R0
R7
08H
07H
R0
0
4 banks of 8 registers
(R0 to R7)
MLA560 - 1
Fig.5 The lower 128 bytes of internal data memory.
1998 Oct 07
COMMENT
14
Philips Semiconductors
Product specification
Pager baseband controller
6.6
6.6.1
PCA5007
Port 3 Pins are configured as strong push-pull outputs
(see Table 5 for configuration details).
The following alternative Port 3 functions are
available, but to avoid short-circuiting of the port
pins, the input signals cannot be applied externally
to the Port 3 pins. The alternative function can only
be stimulated via the respective port output
function:
I/O facilities
PORTS
The PCA5007 has 27 I/O lines treated as 27 individually
addressable bits or as four parallel 8-bit addressable ports.
Ports 0 and 2 are complete, Port 1 has only 7 and Port 3
has only 4 pins externally available. Ports 0, 1, 2 and 3
perform the following alternative functions:
• External interrupt request inputs INT0/P3.2 and
INT1/P3.3
Port 0 Is also used for external access, parallel OTP
programming mode and emulation (see Table 2 for
configuration details):
• Counter inputs T0/P3.4 and T1/P3.5.
• Provides the multiplexed low-order address and
data bus for expanding the device with standard
memories and peripherals
To enable a port pin alternative function, the port bit latch
in its SFR must contain a logic 1.
Each port consists of a latch (SFRs P0 to P3), an output
driver and input buffer. Standard ports have internal
pull-ups. Figure 6a shows that the strong transistor p1 is
turned on for only a short time after a LOW-to-HIGH
transition in the port latch. When on, it turns on p3 (a weak
pull-up) through the inverter IN1. This inverter and p3 form
a latch which holds the logic 1.
• Provides access to the OTP data I/O lines in OTP
parallel programming mode.
Port 1 Used for a number of alternative functions
(see Table 3 for configuration details):
• Provides the inputs for the external interrupts
INT2/P1.0 to INT4/P1.2 and INT6/P1.4
• SCL/P1.6 and SDA/P1.7 for the I2C-bus interface
are real open-drain outputs; no other port
configurations are available
6.6.2
I/O port output configurations are determined on-chip
according to one of the options illustrated in Fig.6. They
cannot be changed by software.
• RXD/P1.3 and TXD/P1.4 for the UART data input
and output.
Port 2 Is also used for external access, parallel OTP
programming mode and emulation (see Table 4 for
configuration details):
• Provides the high-order address bus when
expanding the device with external program
memory
• Allows control of the on-chip OTP parallel
programming mode.
1998 Oct 07
PORT I/O CONFIGURATION (OPTIONS)
15
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
VDD
handbook, full pagewidth
weak pull-up
delay >50 ns
p2
strong pull-up
hold pull-up
p3
p1
I/O pin
Q
from port latch
n
IN1
VSS
VSS
input data
MGR111
a. Standard/quasi-bidirectional (option 1).
VDD
handbook, full pagewidth
VDD
strong pull-up
p1
I/O pin
Q
from port latch
n
VSS
VSS
input data
MGR112
b. Push-pull (option 3).
VDD external
handbook, full pagewidth
I/O pin
Q
from port latch
SLEW
RATE
CONTROL
n
VSS
VSS
input data
LOW-PASS
FILTER
MGR113
c. Open-drain (only SDA/P1.7, SCL/P1.6; option 2).
Fig.6 Port configuration options.
1998 Oct 07
16
external
pull-up
Philips Semiconductors
Product specification
Pager baseband controller
6.6.3
PCA5007
PORT I/O CONFIGURATION
Tables 2 to 6 show the hardwired configuration for the different I/Os of the PCA5007.
Table 2
Port 0 configuration; notes 1 and 2
PORT PIN
CONFIGURATION
PULL-UP INPUT RESET
DRIVE
POSSIBLE
APPLICATION IN A
PAGER
P0.0
quasi bidirectional I/O (option 1S)
yes
hys
HIGH
0.75 mA
LCD_enable (O)
P0.1
quasi bidirectional I/O (option 1S)
yes
hys
HIGH
0.75 mA
SPI_enable (O)
P0.2
quasi bidirectional I/O (option 1S)
yes
hys
HIGH
0.75 mA
SPI_clock (O)
P0.3
quasi bidirectional I/O (option 1S)
yes
hys
HIGH
0.75 mA
SPI_data (O)
P0.4
quasi bidirectional I/O (option 1S)
yes
hys
HIGH
0.75 mA
SPI_data (I)
P0.5
quasi bidirectional I/O (option 1R)
yes
hys
LOW
0.75 mA
RXE (O)
P0.6
quasi bidirectional I/O (option 1R)
yes
hys
LOW
0.75 mA
ROE (O)
P0.7
quasi bidirectional I/O (option 1S)
yes
hys
HIGH
0.75 mA
bandwidth (O)/RSSI (I)
Notes
1. Option 1S means port configuration option 1 with post-reset set to HIGH; option 1R means post-reset state will be
LOW.
2. ‘hys’ means input stage with hysteresis.
Table 3
Port 1 configuration
PORT PIN
CONFIGURATION
PULL-UP INPUT RESET
DRIVE
POSSIBLE
APPLICATION IN A
PAGER
P1.0
quasi bidirectional I/O (option 1S)
yes
hys
HIGH
0.75 mA
Key
P1.1
quasi bidirectional I/O (option 1S)
yes
hys
HIGH
0.75 mA
Key
P1.2
quasi bidirectional I/O (option 1S)
yes
hys
HIGH
0.75 mA
Key
P1.3
quasi bidirectional I/O (option 1S)
yes
hys
HIGH
0.75 mA
RXD
P1.4
quasi bidirectional I/O (option 1S)
yes
hys
HIGH
0.75 mA
TXD
P1.5
not available
P1.6
I2C-bus open-drain I/O (option 2S)
(slew rate limited)
no
hys
HIGH
2.25 mA
SCL
P1.7
I2C-bus open-drain I/O (option 2S)
(slew rate limited)
no
hys
HIGH
2.25 mA
SDA
DRIVE
POSSIBLE
APPLICATION IN A
PAGER
Table 4
Port 2 configuration
PORT PIN
CONFIGURATION
PULL-UP INPUT RESET
P2.0
quasi bidirectional I/O (option 1S)
yes
hys
HIGH
0.75 mA
LCD_Data
P2.1
quasi bidirectional I/O (option 1S)
yes
hys
HIGH
0.75 mA
LCD_Data
P2.2
quasi bidirectional I/O (option 1S)
yes
hys
HIGH
0.75 mA
LCD_Data
P2.3
quasi bidirectional I/O (option 1S)
yes
hys
HIGH
0.75 mA
LCD_Data
1998 Oct 07
17
Philips Semiconductors
Product specification
Pager baseband controller
PORT PIN
CONFIGURATION
PCA5007
PULL-UP INPUT RESET
DRIVE
POSSIBLE
APPLICATION IN A
PAGER
P2.4
quasi bidirectional I/O (option 1S)
yes
hys
HIGH
0.75 mA
LCD_Data
P2.5
quasi bidirectional I/O (option 1S)
yes
hys
HIGH
0.75 mA
LCD_Data
P2.6
quasi bidirectional I/O (option 1S)
yes
hys
HIGH
0.75 mA
LCD_Data
P2.7
quasi bidirectional I/O (option 1S)
yes
hys
HIGH
0.75 mA
LCD_Data
DRIVE
POSSIBLE
APPLICATION IN A
PAGER
Table 5
Port 3 configuration
PORT PIN
CONFIGURATION
PULLUP
INPUT RESET
P3.0
not available
P3.1
not available
P3.2
push-pull output (option 3R)
no
hys
LOW
3 mA
call LED
P3.3
push-pull output (option 3R)
no
hys
LOW
3 mA
vibrator
P3.4
push-pull output (option 3R)
no
hys
LOW
3 mA
backlight
P3.5
push-pull output (option 3R)
no
hys
LOW
3 mA
LCD R/W/RXD Enable
P3.6
not available
P3.7
not available
The port configuration is fixed and cannot be reconfigured by software or ROM code.
Table 6
Other pins
PORT PIN
CONFIGURATION
PULL-UP INPUT RESET
POSSIBLE
APPLICATION IN A
PAGER
3 mA
tone generator output
AT
push-pull output
no
I(D1)
digital input
no
hys
Q(D0)
digital input
no
hys
TCLK
digital input
no
hys
RESETIN
digital input
no
hys
RESOUT
push-pull output
no
XTL1
analog input/output (10 pF)
no
XTL2
analog input/output (10 pF)
no
AFCOUT
analog output
no
ALE
quasi bidirectional I/O
yes
hys
HIGH
1.5 mA
PSEN
quasi bidirectional I/O
yes
hys
HIGH
0.75 mA
EA
3-state I/O with bus keeper
hold
buffer
HIGH
0.75 mA
1998 Oct 07
LOW
DRIVE
reset input
LOW
1.5 mA
hys
reset output
to crystal quartz
to crystal quartz
18
Philips Semiconductors
Product specification
Pager baseband controller
6.7
PCA5007
In the timer mode the timers count events on the XTL1
input. Timer 0 counts through a prescaler at a rate of
256 Hz and Timer 1 counts directly on both edges of the
XTL1 signal at a rate of 153.6 kHz. The nominal frequency
of the XTL1 signal is 76.8 kHz.
Timer/event counters
The PCA5007 contains two 16-bit timer/event counters,
Timer 0 and Timer 1, which can perform the following
functions:
• Measure time intervals and pulse durations
In the counter mode, the register is incremented in
response to a HIGH-to-LOW transition at P3.4 (T0) and
P3.5 (T1).
• Count events
• Generate interrupt requests
• Generate output on comparator match
Besides the different input frequencies and the
non-availability of Mode 3, both Timer 0 and Timer 1
behave identically to the standard 80C51 Timer 0 and
Timer 1.
• Generate a Pulse Width Modulated (PWM) output
signal.
Timer 0 and Timer 1 can be programmed independently to
operate in four modes:
Mode 0: 8-bit timer or 8-bit counter each with
divide-by-32 prescaler
Mode 1: 16-bit time interval or event counter
Mode 2: 8-bit time interval or event counter with
automatic reload upon overflow
Mode 3: this mode of the standard 80C51 is not
available.
handbook, full pagewidth
XTL1
÷ 300
256 Hz
C/T = 0
TL0
TH0
TL1
TH1
C/T = 1
T0
TR0
Gate
INT0
XTL1
153.6 kHz
C/T = 0
C/T = 1
T1
MGR114
TR1
Gate
INT1
Detailed configuration of the 4 available modes is found in the 80C51 family hardware description (“Philips Semiconductors IC20 Data Handbook”).
Fig.7 Timer/counter 0 and 1: clock sources and control logic.
1998 Oct 07
19
Philips Semiconductors
Product specification
Pager baseband controller
6.8
PCA5007
I2C-bus serial I/O
DIFFERENCES TO A STANDARD I2C-BUS INTERFACE
6.8.1
The serial port supports the 2-line I2C-bus which consists
of a data line (SDA) and a clock line (SCL). These lines
also function as the I/O port lines P1.7 and P1.6
respectively. The system is unique because data
transport, clock generation, address recognition and bus
control arbitration are all controlled by hardware.
The I2C-bus serial I/O has complete autonomy in byte
handling. The implementation in the PCA5007 operates in
single master mode as:
The I2C-bus interface of the PCA5007 implements the
standard for master receiver and transmitter as defined in
e.g. P83CL781/782 with the following restrictions:
• The baud rate is fixed to 100 kHz derived from the
on-chip 6 MHz oscillator. Therefore bits CR0, CR1 and
CR2 in the S1CON SFR are not available.
• Only single master functions are implemented.
– Slave address (S1ADR) is not available
• Master transmitter
– Status register (S1STA) reports only status defined
for the MST/TRX and MST/REC modes
• Master receiver.
– Multimaster operation is not supported.
These functions are controlled by the S1CON register.
S1STA is the status register whose contents may also be
used as a vector to various service routines. S1DAT is the
data shift register. The block diagram of the I2C-bus
serial I/O is shown in Fig.8.
handbook, full pagewidth
SHIFT REGISTER
SDA
INTERNAL BUS
S1DAT
ARBITRATION LOGIC
SCL
BUS CLOCK GENERATOR
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
S1CON
7
S1STA
MGL449
Fig.8 Block diagram of I2C-bus serial I/O.
1998 Oct 07
20
Philips Semiconductors
Product specification
Pager baseband controller
6.8.2
PCA5007
SERIAL CONTROL REGISTER (S1CON)
Table 7
Serial Control Register (S1CON, SFR address D8H)
7
6
5
4
3
2
1
0
−
ENS1
STA
STO
SI
AA
−
−
Table 8
Description of the S1CON bits
BIT
SYMBOL
FUNCTION
S1CON.7
−
S1CON.6
ENS1
Enable Serial I/O. When ENS1 = 0, the serial I/O is disabled. SDA and SCL outputs are
in the high-impedance state; P1.6 and P1.7 function as open-drain ports. When
ENS1 = 1, the serial I/O is enabled. Output port latches P1.6 and P1.7 must be set to
logic 1.
S1CON.5
STA
START flag. If STA is set while the SIO is in master mode, SIO will generate a repeated
START condition.
S1CON.4
STO
STOP flag. With this bit set while in master mode a STOP condition is generated. When
a STOP condition is detected on the I2C-bus, the SIO hardware clears the STO flag.
S1CON.3
SI
CR2 is not available.
SIO interrupt flag. This flag is set, and an interrupt is generated, after any of the
following events occur:
• A START condition is generated in master mode
• A data byte has been received or transmitted in master mode (even if arbitration is lost).
If this flag is set, the I2C-bus is halted (by pulling down SCL). Received data is only valid
until this flag is reset.
S1CON.2
AA
Assert Acknowledge. When this bit is set, an acknowledge (LOW level to SDA) is
returned during the acknowledge clock pulse on the SCL line when:
• A data byte is received while the device is programmed to be a master receiver.
When this bit is reset, no acknowledge is returned.
S1CON.1
−
S1CON.0
−
CR1 and CR0 are not available.
DATA SHIFT REGISTER (S1DAT)
6.8.3
S1DAT contains the serial data to be transmitted or data which has just been received. Bit 7 is transmitted or received
first; i.e. data shifted from left to right.
Table 9
6.8.4
Data Shift Register (S1DAT, SFR address DAH)
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
ADDRESS REGISTER (S1ADR)
The slave address register is not available since slave mode is not supported.
6.8.5
SERIAL STATUS REGISTER (S1STA)
The contents of this register may be used as a vector to a service routine. This optimizes the response time of the
software and consequently that of the I2C-bus. S1STA is a read-only register. The status codes for all available modes
of a single master I2C-bus interface are given in Tables 12 to 14.
1998 Oct 07
21
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
Table 10 Serial Status Register (S1STA and SFR address D9H)
7
6
5
4
3
2
1
0
SC4
SC3
SC2
SC1
SC0
0
0
0
Table 11 Description of the S1STA bits
BIT
SYMBOL
S1STA.3 to S1STA.7
SC4 to SC0
S1STA.0 to S1STA.2
−
FUNCTION
5-bit status code
these 3 bits are held LOW
Table 12 MST/TRX mode
S1STA VALUE
DESCRIPTION
08H
a START condition has been transmitted
10H
a repeated START condition has been transmitted
18H
SLA and W have been transmitted, ACK has been received
20H
SLA and W have been transmitted, ACK received
28H
DATA of S1DAT has been transmitted, ACK received
30H
DATA of S1DAT has been transmitted, ACK received
Table 13 MST/REC mode
S1STA VALUE
40H
DESCRIPTION
SLA and R have been transmitted, ACK received
48H
SLA and R have been transmitted, ACK received
50H
DATA has been received, ACK returned
58H
DATA has been received, ACK returned
Table 14 Miscellaneous
S1STA VALUE
78H
DESCRIPTION
no information available (reset value); the serial interrupt flag SI, is not yet set
Table 15 Symbols used in Tables 12 to 14
SYMBOL
DESCRIPTION
SLA
7-bit slave address
R
read bit
W
write bit
ACK
acknowledgement (acknowledge bit = logic 0)
ACK
no acknowledgement (acknowledge bit = logic 1)
DATA
8-bit data byte to or from I2C-bus
MST
master
SLV
slave
TRX
transmitter
REC
receiver
1998 Oct 07
22
Philips Semiconductors
Product specification
Pager baseband controller
6.9
PCA5007
The serial port can operate in 2 modes:
Serial interface SIO0: UART
Mode 1 10 bits are transmitted (through TXD) or received
(through RXD): a START bit (0), 8 data bits (LSB
first) and a STOP bit (1). On receive, the stop bit
goes into RB8 in special function register S0CON
(see Figs 9 and 10).
The UART interface of the PCA5007 implements a subset
of the complete standard as defined in e.g. the P80CL580.
6.9.1
DIFFERENCES TO THE STANDARD 80C51 UART
The following deviations from the standard exist:
Mode 2 11 bits are transmitted (through TXD) or received
(through RXD): a START bit (0), 8 data bits (LSB
first), a programmable 9th data bit and a STOP
bit (1). On transmit, the 9th data bit (TB8 in
S0CON) can be assigned the value of 0 or 1.
Or, for example, the parity bit (P, in the PSW)
could be moved into TB8. On receive, the
9th data bit goes into RB8 in S0CON, while the
STOP bit is ignored (see Figs 9 and 11).
• If [SM1 and SM0] = 10 then Mode 1 (8-bit data
transmission) is selected, with a fixed baud rate
(4800/9600 bits/s)
• If [SM1 and SM0] = 01 then Mode 2 (9-bit data
transmission) is selected, with a fixed baud rate
(4800/9600 bits/s)
• Modes 0 and 3 and the variable baud rate selection
using Timer 1 overflow is not available
• The SM2 bit has no function
In both modes the baud rate can be selected to either
4800 or 9600 depending on the SMOD bit in the PCON
SFR. If SMOD = 0 the baud rate is 4800, if SMOD = 1 the
baud rate is 9600 with a 76.8 kHz quartz crystal.
• The time reference for Modes 1 and 2 is taken from the
f OSC
76.8 kHz oscillator, instead of the original ----------12
6.9.2
In both modes, transmission is initiated by any instruction
that uses S0BUF as a destination register. Reception is
initiated by the incoming start bit if REN = 1.
UART MODES
This serial port is full duplex which means that it can
transmit and receive simultaneously. It is also
receive-buffered and can commence reception of a
second byte before a previously received byte has been
read from the register. However, if the first byte has not
been read by the time the reception of the second byte is
complete, the second byte will be lost. The serial port
receive and transmit registers are both accessed via the
special function register S0BUF. Writing to S0BUF loads
the transmit register and reading from S0BUF accesses a
physically separate receive register.
SERIAL PORT CONTROL REGISTER (S0CON)
6.9.3
The serial port control and status register is the special
function register S0CON (see Table 16). The register
contains not only the mode selection bits, but also the
9th data bit for transmit and receive (TB8 and RB8), and
the serial port interrupt bits (TI and RI).
Table 16 Serial Port Control Register (S0CON, SFR address 98H)
7
6
5
4
3
2
1
0
SM0
SM1
−
REN
TB8
RB8
TI
RI
1998 Oct 07
23
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
Table 17 Description of the S0CON bits
BIT
SYMBOL
FUNCTION
S0CON.7
SM0
this bit together with the SM1 bit, is used to select the serial port mode; see Table 18
S0CON.6
SM1
this bit together with the SM0 bit, is used to select the serial port mode; see Table 18
S0CON.5
−
S0CON.4
REN
this bit enables serial reception and is set by software to enable reception, and cleared by
software to disable reception
S0CON.3
TB8
this bit is the 9th data bit that will be transmitted in Mode 2; set or cleared by software as
desired
S0CON.2
RB8
in Mode 2, this bit is the 9th data bit received; in Mode 1 it is the stop bit that was received
S0CON.1
TI
The transmit interrupt flag; Set by hardware at the end of the 8th bit time in Mode 0, or at
the beginning of the stop bit time in the other modes, in any serial transmission; must be
cleared by software.
S0CON.0
RI
The receive interrupt flag; Set by hardware at the end of the 8th bit time in Mode 0, or
halfway through the stop bit time in the other modes, in any serial transmission (for exception
see SM2); must be cleared by software.
SM2 is not available
Table 18 Selection of the serial port modes
SM0
SM1
MODE
DESCRIPTION
0
1
1
8-bit UART
1
0
2
9-bit UART
BAUD RATE
1⁄ f
16 osc
1⁄ f
16 osc
or 1⁄8fosc
or 1⁄8fosc
UART DATA REGISTER (S0BUF)
6.9.4
The UART data register (S0BUF) contains the serial data to be transmitted or data which has just been received. Bit 0
is transmitted or received first.
Table 19 Data Shift Register (S0BUF, SFR address 99H)
6.9.5
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
BAUD RATES
The baud rate in Modes 1 and 2 depends on the value of the SMOD bit in SFR PCON and may be calculated as:
SMOD
2
Baud rate = ----------------- × f osc
16
• If SMOD = 0, (which is the value on reset), the baud rate is 1⁄16fosc
• If SMOD = 1, the baud rate is 1⁄8fosc.
1998 Oct 07
24
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
handbook, full pagewidth
INTERNAL BUS
TB8
write to
SBUF
XTL1
D S
Q
TXD
S0 BUFFER
CL
2
0
SHIFT
1
ZERO DETECTOR
CSMOD at
PCON.7
STOP BIT
START
TX CONTROL
8
TX CLOCK
SHIFT
DATA
SEND
T1
serial port
interrupt
8
sample
HIGH-TO-LOW
TRANSITION
DETECTOR
RX CLOCK
START
R1
RX CONTROL
LOAD
SBUF
SHIFT
INPUT SHIFT
REGISTER
(9-BITS)
BIT
DETECTOR
SHIFT
RXD
LOAD
SBUF
S0 BUFFER
READ
SBUF
INTERNAL BUS
MGL452
Fig.9 Serial port Mode 1and Mode 2.
1998 Oct 07
25
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T
R
A
N
S
M
I
T
SEND
DATA
SHIFT
D0
TXD
D2
D1
D4
D3
D5
D6
D7
STOP BIT
Philips Semiconductors
WRITE TO SBUF
Pager baseband controller
1998 Oct 07
TX CLOCK
START BIT
TI
÷8 RESET
26
RX CLOCK
START BIT
RXD
D0
D1
D2
D3
D4
D5
D6
D7
STOP BIT
BIT DETECTOR SAMPLE TIME
SHIFT
RI
MGL451
Product specification
Fig.10 Serial port Mode 1 timing.
PCA5007
handbook, full pagewidth
R
E
C
E
I
V
E
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SEND
T
R
A
N
S
M
I
T
DATA
SHIFT
D0
TXD
D1
D3
D2
D4
D5
D6
D7
TB8
STOP BIT
START BIT
Philips Semiconductors
WRITE TO SBUF
Pager baseband controller
1998 Oct 07
TX CLOCK
TI
STOP BIT GEN
÷8 RESET
R
E
C
E
I
V
E
START BIT
RXD
D0
D1
D2
D3
D4
D5
D6
D7
RB8
STOP BIT
BIT DETECTOR SAMPLE TIME
SHIFT
RI
MGL450
Product specification
Fig.11 Serial port Mode 2 timing.
PCA5007
handbook, full pagewidth
27
RX CLOCK
Philips Semiconductors
Product specification
Pager baseband controller
6.10
6.10.1
PCA5007
The whole circuit operates directly at the battery supply.
The 76.8 kHz oscillator cannot be disabled. It also
continues its operation during DC/DC converter off or
8051 stop mode.
76.8 kHz oscillator
FUNCTION
The oscillator produces a reference frequency of 76.8 kHz.
The frequency offset is compensated for by a separate
digital clock correction block. The oscillator operates
directly on VBAT and is always enabled.
6.10.2
The simplest application configuration is shown in Fig.12a.
C1 and C2 can be added to operate a crystal at its
optimum load condition. The resulting capacitance of the
series connection of C1 and C2 must be smaller than 5 pF
for a guaranteed start-up of the oscillator.
OSCILLATOR CIRCUITRY
The on-chip inverting oscillator amplifier is a single NMOS
transistor supplied with a constant current. The amplitude
visible at terminals XTL1 and XTL2 is therefore not a full
rail swing with a very high impedance. To reduce the
power consumption, the input Schmitt trigger buffer is
limited to approximately 100 kHz maximum frequency.
handbook, full pagewidth
76.8 kHz
10 pF
76.8 kHz
10 pF
XTL1
10 pF
XTL2
76.8 kHz
10 pF
XTL1
10 pF
XTL2
10 pF
XTL1
XTL2
76.8 kHz
76.8 kHz
VP = VBAT
2 MΩ
C1
(a)
fmax = 100 kHz
2 MΩ
C2
(b)
Fig.12 Oscillator circuit.
1998 Oct 07
28
MGR115
(c)
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
Crystal offset correction can be performed with a
resolution of 5 ppm.
6.11 Clock correction
6.11.1
FUNCTION
This block also generates the timing reference signals for
other functional blocks such as the RTC (4 Hz), watchdog
(16 Hz), Timer 0 (256 Hz), wake-up counter (9600 Hz)
and the demodulator/clock recovery block. The generation
of these timing references is always active and cannot be
disabled.
The clock correction block is connected to the 76.8 kHz
oscillator. It operates directly from VBAT. By means of the
clock correction circuit a digital adjustment of the 76.8 kHz
oscillator signal is implemented.
An 18-bit interval counter inserts or deletes one pulse from
the 76.8 kHz clock each time its count has expired.
The interval is stored by the processor to the 18-bit interval
register CIV. Addition or deletion is performed by
hardware.
handbook, full pagewidth
VDD supply
SFR to
microcontroller
SET
ENB
PLUS
BYPASS
CIV0 to CIV17
TEST
RESET
with each
OFF cycle
R
INTERVAL LATCH
(18-BIT)
Q
internal
set flag
D
1
STORE
reload data
Q
D
RESET only
on RESETIN
76.8 kHz
INTERVAL COUNTER
(18-BIT)
(RELOAD ON CARRY)
&
CARRY
ADD/DELETE
ONE PULSE
ON CARRY
÷2
VBAT supply
Fig.13 Block diagram for clock compensation.
1998 Oct 07
29
corrected
38.4 kHz
MGR116
Philips Semiconductors
Product specification
Pager baseband controller
6.11.2
PCA5007
CLOCK CORRECTION CONTROL REGISTER (CCON)
The CCON special function register is used to control the clock correction by software.
Table 20 Clock Correction Control Register (CCON, SFR address FCH)
7
6
5
4
3
2
1
0
ENB
PLUS
TEST
CIV17
CIV16
−
BYPASS
SET
Table 21 Description of the CCON bits
BIT
SYMBOL
FUNCTION
CCON.7
ENB
Enable clock correction. If ENB = 1 has been set, then correction is enabled and will
stay enabled even when the DC/DC converter is shut down and restarted.
CCON.6
PLUS
± sign for value. If PLUS = 1 then clock pulses are inserted, or else deleted.
CCON.5
TEST
Test signal, must always be logic 0 in normal mode. It is s used during test to bypass
the first 9 FFs in the timing generator divider chain. If TEST = 1 the clock rate of the
signals 9600 Hz and 256 Hz is doubled and the frequency on 16 Hz and 4 Hz is
multiplied by 300.
CCON.4
CIV17
bit 17 of interval value, is used as extension of CC0 and CC1
CCON.3
CIV16
CCON.2
−
CCON.1
BYPASS
Test signal, must always be logic 0 in normal mode. It is used during test to generate
76.8 kHz on all outputs of the timing generator (4 Hz, 16 Hz, 256 Hz and 9600 Hz).
CCON.0
SET
A load signal to the interval register. After a logic 0 to logic 1 transition of this bit the
value of ENB, PLUS, TEST, BYPASS and CIV are copied into the local latches with the
next 76.8 kHz clock pulse. The duration of one MOV instruction is long enough for the
set operation to complete. The SFR values must remain stable for at least one oscillator
period because the actual transfer happens synchronized with the local clock
(see Figs 14 and 16).
bit 16 of interval value, is used as extension of CC0 and CC1
unused.
CLOCK CORRECTION INTERVAL REGISTERS (CC0 AND CC1)
6.11.3
The CC0 and CC1 special function registers (together with CCON.3 and CCON.4) are used to define the interval between
subsequent clock correction actions.
Table 22 Clock Correction Interval Register (CC0, SFR address FDH)
7
6
5
4
3
2
1
0
CIV7
CIV6
CIV5
CIV4
CIV3
CIV2
CIV1
CIV0
Table 23 Clock Correction Interval Register (CC1, SFR address FEH)
7
6
5
4
3
2
1
0
CIV15
CIV14
CIV13
CIV12
CIV11
CIV10
CIV9
CIV8
1998 Oct 07
30
Philips Semiconductors
Product specification
Pager baseband controller
6.11.4
PCA5007
EXAMPLE SEQUENCE TO SET ANOTHER CLOCK CORRECTION INTERVAL
PLUS, ENB
and CIV
handbook, full pagewidth
valid value in SFR
must stay valid for
one period of 76.8 kHz
SET
MGR117
Fig.14 Sequence for setting the clock compensation.
MOV CC0, #(CIV7 to CIV0).
MOV CC1, #(CIV8 to CIV15).
MOV CCON, #D4H.
MOV CCON, #D5H.
6.11.5
TIMING
Figures 15 and 16 illustrate how the clock correction works and how the access of the microcontroller is synchronized to
the local operation.
[CIV] − 5
[CIV] − 4
[CIV] − 3
[CIV] − 2
[CIV] − 1
[CIV]
0
1
2
3
4
5
6
7
[CIV] − 5
[CIV] − 4
[CIV] − 3
[CIV] − 2
[CIV] − 1
0
1
2
3
4
5
6
Interval counter
[CIV]
handbook, full pagewidth
76.8 kHz
38.4 kHz
CORR for
clock recovery
corrected
38.4 kHz
with PLUS = 1
corrected
38.4 kHz
with PLUS = 0
MGR118
After (CIV) clock ticks of 76.8 kHz or 38.4 kHz one correction is made.
Fig.15 Operation of clock compensation.
1998 Oct 07
31
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
(SFR)
handbook,SET
full pagewidth
SET flag (local)
76.8 kHz
store (local)
data (SFR)
K
data (local)
K
reload from
local data
counter
I
I−1
I−2
I−3
I−4
1
0
K
K−1
K−2
MGR119
Fig.16 Synchronization of local counter operation and access from the microcontroller.
6.12
6.12.1
The DC/DC converter does not need the 6 MHz clock
when set in the standby mode.
6 MHz oscillator
FUNCTION
If the 6 MHz output is required as a frequency source for
other blocks (e.g. I2C-bus) the software needs to enable it
explicitly by setting ENB = 1. Besides the DC/DC
converter the following functions require the operation of
the 6 MHz oscillator:
The 6 MHz oscillator provides the clock for the DC/DC
converter, the I2C-bus interface, the port I/Os and for the
external memory access timing (ALE/PSEN).
The 6 MHz oscillator is a 5 inverter stage current
controlled ring oscillator. The oscillator is optimized for low
operating current consumption.
• I2C-bus block as basic time reference
• Port output logic. Software commands that write to the
ports need this clock to complete the operation (if a
program ‘hangs’, this could be the problem).
The actual frequency of the oscillator can be measured by
activating the MFR signal. An 8-bit counter will then be
reset and will start counting at the first rising edge of the
76.8 kHz signal and will stop counting at the next rising
edge of the 76.8 kHz signal. The processor then can read
the contents of the MFR counter.
• Code fetching from external memories needs the clock
for the ALE/PSEN timing (e.g. LJMP 5000H needs this
clock for completion).
When the ENB bit has been set by software, the clock will
be available internally after the start-up time of this
oscillator. The start-up time is 2 to 3 periods of the
76.8 kHz reference frequency.
The processor can adjust the oscillator frequency using
the F0 to F4 signals (control of source current for ring
oscillator).
The 6 MHz oscillator is enabled by hardware only during
the start-up phase and whenever the DC/DC converter
needs the 6 MHz clock. In all other cases the 6 MHz
oscillator is switched off by hardware.
1998 Oct 07
32
Philips Semiconductors
Product specification
Pager baseband controller
6.12.2
PCA5007
6 MHZ OSCILLATOR CONTROL REGISTER (OS6CON)
The OS6CON special function register is used to control the operation of the on-chip 6 MHz oscillator. The 6 MHz
oscillator can be controlled as follows:
• It can be enabled or disabled. Disabling this oscillator when the DC/DC converter is in standby mode and no port I/O
nor I2C-bus activity is required saves current.
• The frequency of the oscillator can be adjusted by setting the SFx bits accordingly
• The actual frequency of the oscillator can be measured by writing the MFR bit to logic 1.
Table 24 6 MHz Oscillator Control Register (OS6CON, SFR address D3H)
7
6
5
4
3
2
1
0
ENB
−
SF4
SF3
SF2
SF1
SF0
MFR
Table 25 Description of the OS6CON bits
BIT
SYMBOL
FUNCTION
OS6CON.7
ENB
Enable oscillator. If ENB = 1 then the function is enabled. The enable bit is only
cleared when the processor writes the bit to logic 0, or if the DC/DC converter is put into
‘OFF’ state and a reset is generated during the following power-up sequence.
OS6CON.6
−
OS6CON.5
SF4
OS6CON.4
SF3
OS6CON.3
SF2
OS6CON.2
SF1
OS6CON.1
SF0
OS6CON.0
MFR
6.12.3
unused
Set frequency. This 5-bit value adjusts the current of the ring oscillator and thus the
frequency. Writing a small value decreases the frequency. The nominal frequency of
6 MHz is assigned to code (SF4, SF3, SF2, SF1 SF0) = 00000. The resolution of the
frequency adjustment is 200 kHz per step, the range is approximately 3 to 9 MHz.
In order to start with the nominal frequency the MSB bit is inverted in this SFR.
Measure frequency. If a positive pulse is issued on this SFR-bit a frequency
measurement cycle is executed. The duration of this cycle is one period of 76.8 kHz.
The count of 6 MHz periods during the measurement cycle is reported back in OS6M0.
The bit must be reset by software.
6 MHZ OSCILLATOR MEASURED FREQUENCY REGISTER (OS6M0)
The actual frequency of the 6 MHz on-chip oscillator can be calculated from the value in the OS6M0 special function
register, after a Measure Frequency operation (MFR).
Table 26 6 MHz Oscillator Measured Frequency Register (OS6M0, SFR address D4H)
7
6
5
4
3
2
1
0
MF7
MF6
MF5
MF4
MF3
MF2
MF1
MF0
The value stored in this SFR is the counted number of 6 MHz cycles during one 76.8 kHz period. The frequency of the
6 MHz oscillator is therefore f = MF × 76800 Hz with a resolution of 76800 Hz.
1998 Oct 07
33
Philips Semiconductors
Product specification
Pager baseband controller
6.12.4
PCA5007
ENABLING OF THE 6 MHZ OSCILLATOR
handbook, full pagewidth
S0CON,
S0BUF
I2C-BUS
SERIAL INTERFACE
PORT I/O
EXTERNAL ACCESS
PX
&
MICROCONTROLLER
OS6CON,
ENB
6 MHz OSCILLATOR
≥1
ENB
F6M
ENB
DC/DC CONVERTER
MGR120
Fig.17 Relationship between 6 MHz oscillator, DC/DC converter and microcontroller.
6.13
6.13.1
If the DC/DC converter is not active when this happens,
the DC/DC converter is started first, and a
power-up/restart sequence of the microcontroller follows.
The MIN bit remains set during this procedure.
Real-time clock
FUNCTION
The Real-Time Clock (RTC) consists of an 8-bit counter
that is active at all times. To save power it is operated
directly on VBAT. It counts up on every 4 Hz clock pulse
(corrected clock).
6.13.2
The RTCCON special function register is used to control
the operation of the on-chip real-time clock function.
The RTC can be read from and written to by the processor.
When it reaches 239, the signal MINUTE is activated. This
signal resets the counter to 0 (at the next clock pulse), and
generates a MIN-interrupt for the processor.
The microcontroller ‘sees’ the minute interrupt as if it was
an X9 interrupt. It can be enabled and disabled and must
be cleared as an X9 interrupt (CLR IQ9).
1998 Oct 07
REAL-TIME CLOCK CONTROL REGISTER (RTCON)
34
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
Table 27 RTC Control Register (RTCCON, SFR address CDH)
7
6
5
4
3
2
1
0
MIN
−
−
−
−
W/R
LOAD
SET
Table 28 Description of the RTCON bits
BIT
SYMBOL
FUNCTION
RTCON.7
MIN
MIN is activated when the counter reaches 239. MIN is used to generate the interrupt
request signal MINUTE. In order to complete the interrupt cycle and reset the interrupt
source, the processor has to clear MIN. This must be done in a 2 step operation writing
MIN and then applying a positive edge to SET.
RTCON.6
−
unused
RTCON.5
−
unused
RTCON.4
−
unused
RTCON.3
−
unused
RTCON.2
W/R
Before the RTC time can be set by software, the updating of the SFR by the RTC must
be disabled. This is done by writing the W/R bit to logic 1. The W/R bit is cleared by
hardware after the next 4 Hz clock, when the RTC has been loaded with its next value.
RTCON.1
LOAD
Load RTC with contents of RTC0. LOAD is sampled with the positive edge of the set
flag SET. If LOAD is not HIGH during a SET operation, only the MIN flag is (re)set by the
command.
RTCON.0
SET
Latch signal for the real-time clock. With the pulse on SET the content of MIN is
copied into the ‘real’ MIN latch. This is necessary because the RTC has to be active at
all times independant of the microcontroller.
REAL-TIME CLOCK DATA REGISTER (RTC0)
6.13.3
Table 29 RTC Data Register (RTC0, SFR address CEH)
7
6
5
4
3
2
1
0
QSECS7
QSECS6
QSECS5
QSECS4
QSECS3
QSECS2
QSECS1
QSECS0
The value stored in this SFR is the actual 4 Hz count since the last MINUTE interrupt. The contents of this counter can
be read from and written to by software. The contents of this counter are only initialized when RESETIN is activated.
During an OFF sequence, the RTC continues its operation.
The value of the RTC data register is only updated while the STB flag in the DCCON0 SFR is HIGH, i.e. the DC/DC
converter is able to sustain the VDD supply voltage. If the STB flag is at logic 0 the real-time clock continues its operation,
the MINUTE interrupt occurs regularly, but the SFR is not updated.
1998 Oct 07
35
Philips Semiconductors
Product specification
Pager baseband controller
6.13.4
PCA5007
Sequence to clear an interrupt of the RTC:
EXAMPLE SEQUENCE FOR PROGRAMMING THE RTC:
CLR IQ9; Interrupt request flag is IQ9
Sequence to set another value into the RTC:
MOV RTCON, #06H; set LOAD, W/R bits
MOV RTCON, #00H; clear also MIN flag in the SFR
MOV RTC0, #(new value); load new RTC value into
SFR
MOV RTCON, #01H; now set the data valid flag (SET)
in the SFR.
MOV RTCON, #07H; now set the data valid flag (SET)
in the SFR.
6.13.5
TIMING
The interface between 2 and 1 V regions is implemented
similar to the clock correction block. The sequence for
writing values is identical (see Fig.13).
handbook, full pagewidth
4 Hz
update by
hardware
i
data (RTC0)
i+1
MOV RTC0 #m
update by
hardware
data must be valid until here
m+1
m
cleared by hardware
W/R (RTCON)
MOV RTCON #...
LOAD (RTCON)
SET (RTCON)
internal SET flag
internal store
internal write
RTC value
i
i+1
m
m+1
MGR121
Fig.18 Operation of RTC to microcontroller interface.
1998 Oct 07
36
Philips Semiconductors
Product specification
Pager baseband controller
6.14
6.14.1
PCA5007
The counter is implemented as a 16-bit ripple-down
counter. It can be loaded from the wake-up reload latch by
a signal from the processor. When the counter is loaded it
automatically starts if the RUN signal is active. When the
counter reaches zero the wake-up signal becomes active
and may generate an interrupt. The wake-up signal
automatically reloads the counter (modulo N counter).
The counter is stopped when the RUN signal is written to
logic 0. Auto reloading of the counter is also possible,
when the DC/DC converter is not operating (i.e. VDD is
below 1.8 V).
Wake-up counter
FUNCTION
The wake-up counter is intended to be used as a protocol
timer. It can be programmed to wake-up the processor
when the protocol needs an action. Amongst others this
may be:
• Switching on the DC/DC converter at time 0
• Enabling the receiver at time 1
• Enabling the demodulator and clock recovery function
at time 2 before relevant data is expected.
The contents of the wake-up counter cannot be read by the
processor. Reading WUC0 and WUC1 reflects the
contents of the 16-bit wake-up register (set by the
microcontroller).
The time to wake-up is defined as a 16-bit value containing
the number of 9600 Hz ticks. The maximum time interval
that can be spawn with one cycle then equals 6.8 s.
The wake-up counter and its reload latch are supplied by
VBAT and operate independent of the 2 V supply.
The interface between the 2 and 1 V regions is
implemented similar to the clock correction block.
The sequence for writing values is identical (see Fig.14).
A reset to the microcontroller does not clear the wake-up
counter control flags or the reload latch, but clears the
reload register (see Fig.19).
handbook, full pagewidth
≥1
Interrupt
SFR to
microcontroller
VDD supply
CPL
SET
RUN
LOAD WUP
TEST
Z1
RESET
with each
OFF cycle
WU0 to WU15
Z0
wake-up DC/DC converter
R
WU RELOAD LATCH
(16-BIT)
Q
internal
SET FLAG
D
1
D
STORE
RESET only
on RESETIN
reload data
Q
≥1
reload
9600 Hz
WU COUNTER
(16-BIT)
&
CARRY
VBAT supply
Fig.19 Block diagram of the wake-up counter.
1998 Oct 07
37
MGR122
Philips Semiconductors
Product specification
Pager baseband controller
6.14.2
PCA5007
WAKE-UP COUNTER CONTROL REGISTER (WUCON)
The WUCON special function register is used to control the operation of the wake-up counter by software.
Table 30 Wake-up Counter Control Register (WUCON, SFR address 94H)
7
6
5
4
3
2
1
0
RUN
WUP
TEST
CPL
Z1
Z0
LOAD
SET
Table 31 Description of the WUCON bits
BIT
SYMBOL
FUNCTION
WUCON.7
RUN
Control signal from the processor.
WUCON.6
WUP
Latched Wake-Up signal. The bit is set by hardware (or software) and generates a
wake-up interrupt if enabled and the DC/DC STB bit is set. The bit needs to be cleared
by software (SFR and 1 V bits). A SET sequence is required to clear the flag on the 1 V
side. Attention: reading the bit reads the contents of the ‘real’ wake-up flag on the 1 V
side, (read/modify/write commands will fail on this bit).
WUCON.5
TEST
Test control signal (uses 76.8 kHz as clock input for high and low counter).
WUCON.4
CPL
WUCON.3
Z1
WUCON.2
Z0
WUCON.1
LOAD
WUCON.0
SET
6.14.3
Set operation completed. Bit set by hardware when the last operation is completed
and the SFRs are again ready to accept new settings. The bit generates a wake-up
interrupt if enabled. The bit needs to be cleared by software.
2 bits that are only reset by a primary RESETIN. The bits can be written to and read
from by the software. The bits are not cleared when the DC/DC converter is switched
off. Same procedure for setting the bits as WU0 to WU15 (reading these bits returns the
‘real’ flags on the 1 V side; read/modify/write commands will fail on this bit).
Load wake-up counter with contents of reload latch (see Fig.19). Is sampled on the
positive edge of SET.
Clock signal for writing to RUN or wake-up SFR (on 1 V level).
WAKE-UP DATA REGISTERS (WUC0, WUC1)
The WUC0 and WUC1 special function registers are used to define the interval to the next wake-up interrupt.
Table 32 Low Wake-UP Register (WUC0, SFR address 95H)
7
6
5
4
3
2
1
0
WU7
WU6
WU5
WU4
WU3
WU2
WU1
WU0
Table 33 High Wake-UP Register (WUC1, SFR address 96H)
7
6
5
4
3
2
1
0
WU15
WU14
WU13
WU12
WU11
WU10
WU9
WU8
1998 Oct 07
38
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
WU0 to WU15 is a 16-bit register that is loaded by the
processor. The contents of this register will be loaded into
a 16-bit reload latch with a positive pulse on SET and into
the 16-bit ripple-down counter with a positive pulse on
LOAD.
6.14.4
Sequence to set another reload value:
MOV WUC1, #(high VALUE)
MOV WUC0, #(low VALUE)
The value stored in the wake-up counter cannot be read by
software. The contents of this counter are only initialized
when RESETIN is activated. During an off sequence, the
wake-up counter continues its operation.
MOV WUCON, #82H; set RUN and LOAD bit
MOV WUCON, #83H; activate SET flag
MOV PCON, #01H; >>> IDLE, WAIT FOR CPL
INTERRUPT.
The wake-up interrupt can only occur while the STB flag in
the DCCON0 SFR is HIGH, i.e. the DC/DC converter is
able to sustain the VDD supply voltage. If the STB flag is at
logic 0 the wake-up counter continues its operation, the
WUP flag is set when expired (but can still be checked by
software) but an interrupt is not generated.
6.14.5
EXAMPLE SEQUENCE FOR CONTROLLING THE
WAKE-UP COUNTER
TIMING
handbook, full pagewidth
9600 Hz
transfer to 1 V registers completed, data may change again
m
data in SFR
LOAD
SET bit in SFR
internal SET flag
internal STORE
internal data
counter value
m
i
i−1
m
CPL bit in WUCON
(generates interrupt
if enabled)
set by hardware
cleared by software
MGR123
Fig.20 Operation of wake-up counter to microcontroller interface.
1998 Oct 07
m−1
39
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
handbook, full pagewidth
9600 Hz
only WUCON data to be transferred,
no reload for WUC0, WUC1
LOAD
SET bit in SFR
SET to transfer
modified WUP
to 1 V side
internal SET flag
counter value
0
WUP flag on 1 V side
generates DC/DC
wake-up if required
m−1
m
WUP remains
HIGH if not cleared
set by
hardware
SFR and 1 V WUP are different
WUP in WUCON SFR
(generates interrupt if enabled)
set by
hardware
cleared by
software
set by
hardware
CPL in WUCON SFR
(generates interrupt if enabled)
cleared by
software
MGR124
Fig.21 Wake-up interrupt sequence.
6.15
6.15.1
Tone generator
FUNCTION
The tone generator is implemented by a programmable divider from 76.8 kHz. An 8-bit value is used to define the cycle
of a modulo N counter. The output of the modulo N counter is divided-by-2 to produce a symmetrical output signal.
The counter is running when enabled.
76.8 kHz
The output frequency at the pin AT is defined as: f AT = ----------------------- if TFREQ ≥ 1. If TFREQ = 0 then fAT = 76.8 kHz.
TFREQ
A secondary clock signal can be used as clock input to the modulo N counter. This input is required to generate the
accurate resonance frequency of certain acoustic alerters (e.g. 512, 687, 1024, 1365, 2048, 2730, 4096).
The tone volume can be controlled by setting the frequency on or off alerter resonance.
6.15.2
INTERFACES
SFR ADDRESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TGCON (92H)
ENB
CLK2
−
−
−
−
−
−
TFREQ7
TFREQ6
TFREQ5
TFREQ4
TFREQ3
TFREQ2
TFREQ1
TFREQ0
TG0 (93H)
1998 Oct 07
40
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
SFR:
6.16
• TFREQ0 to TFREQ7: 8-bit register containing the
divisor of the tone. Loaded by the processor.
6.16.1
FUNCTION
The watchdog timer consists of an 8-bit down counter.
The binary number defined with WD3 to WD0 defines the
expiry time of the watchdog timer between 1 to 16 s. Once
enabled this counter is running continuously. Once expired
the timer produces firstly an interrupt and finally a reset.
The software must reload the watchdog in regular intervals
to avoid expiry.
• ENB: Enable frequency generator. Control signal from
processor.
• CLK2: Use secondary clock input for tone generation.
If set a 32768 Hz clock signal is generated from the
primary 76800 Hz clock signal and used as a timing
reference for the tone generator.
A positive edge on the LD SFR bit (re)loads the counter
with the value of WD3 to WD0, sets the LOW bits to logic 1
and activates this counter if it is not yet running. However,
to prepare the (re)loading a positive edge must be applied
to the COND bit in WDCON. In this way at least two
locations in software must be passed before the counter
can be reloaded. After reset the counter is not running.
Only after the first LD it is clocked continuously by a clock
pulse of 16 Hz until the DC/DC converter is switched off or
an external reset is applied.
Inputs:
• 76.8 kHz: Input to the tone counter.
Outputs:
• AT: Output for alerter. Is logic 0 when disabled:
76.8 kHz
f AT = ----------------------TFREQ
6.15.3
Watchdog timer
GENERATION OF THE 32768 HZ REFERENCE
The 32768 Hz reference is generated from 76800 Hz
according to the following algorithm:
forever do
begin
for 10 times do {
from 7 clocks on 76.8 kHz generate
3 pulses on 32 kHz
}
from 5 clocks on 76.8 kHz generate
2 pulses on 32 kHz
end
If the next LD signal is not given within the defined expiry
interval an overflow occurs and the processor will be reset
(signal WDR). A WDI interrupt is issued one clock cycle
before the reset is applied. This gives the opportunity to
avoid the reset if required. The maximum watchdog expiry
time is thus 254 × 16 Hz ticks to the WD interrupt and
255 × 16 Hz ticks to the reset.
If the DC/DC converter is in the off mode, the watchdog
timer is suspended.
WATCHDOG TIMER CONTROL REGISTER (WDCON)
6.16.2
The WDCON special function register is used to control the operation of the on-chip watchdog timer.
Table 34 Watchdog Control Register (WDCON, SFR address A5H)
7
6
5
4
3
2
1
0
COND
WD3
WD2
WD1
WD0
−
−
LD
1998 Oct 07
41
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
Table 35 Description of the WDCON bits
BIT
SYMBOL
FUNCTION
WDCON.7
COND
WDCON.6
WD3
WDCON.5
WD2
WDCON.4
WD1
WDCON.3
WD0
WDCON.2
−
unused
WDCON.1
−
unused
WDCON.0
LD
6.16.3
Load condition. Control signal from processor.
WD0 to WD3 is the preset value for the high nibble of the watchdog timer. The value is
the number of seconds to expiry of the watchdog.
Load watchdog timer with WD0 to WD3. Control signal from processor.
The offset coding is given in Table 37.
SAMPLE SEQUENCE TO RELOAD THE WATCHDOG
Both the filter and direct modes are intended for
applications with an external demodulator. In this case, at
the I and Q pins, there are fed NRZ data. In the 4-FSK
situation the MSB is at pin I and the LSB is at pin Q. In the
2-FSK situation, only pin I is used; pin Q must be
connected to VSS. In these two modes, the offset
calculation and compensation cannot be performed.
The sequence to reload the watchdog with 1 s is:
MOV WDCON, #80H; prepare condition.
MOV WDCON, #01H; reload the timer.
6.17
2 or 4-FSK demodulator, filter and clock
recovery circuit
6.17.1
FUNCTION
In the filter mode (M = 1 and BF = 0), the data is filtered
and then sent to the clock recovery. In the direct mode
(M = 1 and BF = 1), no function of the demodulator is
performed. Consequently there is no filtering on the data
which is sent directly to the clock recovery.
The aim of the demodulator and clock recovery circuitry is
to take the signal from the receiver, to format it into
symbols and to transfer it to the processor. The two blocks
use the 76.8 kHz clock.
The demodulator decodes the incoming signal and
generates a sequence of NRZ data. This data is fed to the
clock recovery block which regenerates the
synchronization clock. This clock is used to sample and to
shift the symbols into register DMD3.
6.17.1.1
Table 36 Modulation coding
Demodulator and filter
The demodulator can operate both with 2-FSK and 4-FSK
(selected by the LEV bit). For both types of input signals
the so called demodulator, filter and direct modes are
allowed. The operational mode is selected on the basis of
the M bit and BF bit.
In the demodulator mode (M = 0 and BF = X) the I and Q
signals are decoded according to Table 36.
Operating in this mode, an offset compensation can be
performed and the calculated offset value is stored into
register DMD1, in the field AVG. The offset value can be
used by the processor to adjust the analog AFC output
voltage.
1998 Oct 07
42
2-FSK
4-FSK
FREQUENCY
(Hz)
D1
D0
D1
D0
+4800
1
X
1
0
+1600
1
X
1
1
−1600
0
X
0
1
−4800
0
X
0
0
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
The recovered clock is used to sample and shift to left into
an internal register one bit each symbol period in 2-FSK
and two bits in 4-FSK. The symbol period is determined by
bits BD2 to BD0. On the basis of BD bits the demodulator
filter length is also set.
Table 37 Offset coding (two’s compliment)
OFFSET (Hz)
MAGNITUDE
(AVG6 TO AVG0)
−9450
0111111
−9300
0111110
...
...
−300
0000010
−150
0000001
0
0000000
150
1111111
300
1111110
...
...
9300
1000001
9450
1000000
6.17.1.2
In the clock recovery, a pulse (SYMCLK) is generated
each N-bit, where ‘N’ is defined by means of bits B2 to B0.
This pulse is used to update the DMD3 register. Moreover,
it can be used as an interrupt to the processor through the
IRQ1.3 (symbol interrupt).
The interrupt informs the controller that ‘N’ bits are
available in the DMD3 register.
6.17.2
DEMODULATOR CONTROL REGISTER (DMD0)
The demodulator control register DMD0 contains the
control bits for enabling the demodulator function and
setting its mode and data rate.
Clock recovery
The clock recovery regenerates the synchronization clock
using the edges of the incoming NRZ data. When the NRZ
data have no edges for a long time, the synchronization is
maintained by means of the correction information from
the clock correction block.
Table 38 Demodulator Control Register (DMD0, SFR address ECH)
7
6
5
4
3
2
1
0
ENB
M
−
RES
LEV
BD2
BD1
BD0
Table 39 Description of the DMD0 bits
BIT
SYMBOL
DMD0.7
ENB
DMD0.6
M
FUNCTION
enable demodulator function
mode selection: logic 0 = I/Q from zero-IF receiver, logic 1 = NRZ data
DMD0.5
−
DMD0.4
RES
reserved for future implementation
DMD0.3
LEV
if set to logic 0 2-FSK demodulation, if set to logic 1 4-FSK demodulation
DMD0.2
BD2
baud rate setting; see Table 40
DMD0.1
BD1
DMD0.0
BD0
1998 Oct 07
not used
43
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
Table 40 Baud rate for bits BD2, BD1 and BD0
BITS
BAUD RATE
6.17.3
BD2
BD1
BD0
0
0
0
1200 symbols/s
0
0
1
2400 symbols/s
0
1
0
1600 symbols/s
0
1
1
3200 symbols/s
1
0
0
undefined
1
0
1
undefined
1
1
0
undefined
1
1
1
undefined
DEMODULATOR AVERAGING REGISTER (DMD1)
The demodulator averaging register DMD1 contains the control bit for enabling the averaging function, used for the offset
compensation during demodulation and the coded average (offset) value.
Table 41 Demodulator Averaging Register (DMD1, SFR address EDH)
7
6
5
4
3
2
1
0
ENA
AVG6
AVG5
AVG4
AVG3
AVG2
AVG1
AVG0
Table 42 Description of the DMD1 bits
BIT
SYMBOL
FUNCTION
DMD1.7
ENA
enable averaging function/offset calculation
DMD1.6
AVG6
DMD1.5
AVG5
DMD1.4
AVG4
7-bit value indicating the offset value of the demodulator. This is an indication of the LO
offset frequency and will be used to determine the AFC output voltage. For coding
see Table 37.
DMD1.3
AVG3
DMD1.2
AVG2
DMD1.1
AVG1
DMD1.0
AVG0
1998 Oct 07
44
Philips Semiconductors
Product specification
Pager baseband controller
6.17.4
PCA5007
CLOCK RECOVERY CONTROL REGISTER (DMD2)
The clock recovery control register DMD2 contains the control bits for enabling the clock recovery function and setting
its mode.
Whenever the clock recovery function is enabled (DMD2.7 = 1) the positive edge of the synchronized SYMCLK signal
will force a SymClk interrupt through the IRQ1.3 request flag after [B2, B1 and B0] received bits (see Section 6.19
Table 50).
Table 43 Clock Recovery Control Register (DMD2, SFR address EEH)
7
6
5
4
3
2
1
0
ENC
−
BF
−
TEST
B2
B1
B0
Table 44 Description of the DMD2 bits
BIT
SYMBOL
FUNCTION
DMD2.7
ENC
DMD2.6
−
DMD2.5
BF
DMD2.4
−
DMD2.3
TEST
DMD2.2
B2
DMD2.1
B1
If LEV = 0 then 000 = 1-bit, 001 = 2-bit to 111 = 8-bit
DMD2.0
B0
If LEV = 1 then 00X = 2-bit, 01X = 4-bit, 10X = 6-bit and 11X = 8-bit.
6.17.5
enable clock recovery function
not used
bypass demodulator filter
not used
reserved, should always beat logic 0
Select number of bits per interrupt:
DEMODULATOR DATA REGISTER (DMD3)
The demodulator data register DMD3 contains the (demodulated) recovered received symbols.
Table 45 Demodulator Data Register (DMD3, SFR address EFH)
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Table 46 Description of the DMD3 bits
BIT
SYMBOL
DMD3.7
D7
DMD3.6
D6
DMD3.5
D5
DMD3.4
D4
DMD3.3
D3
DMD3.2
D2
DMD3.1
D1
DMD3.0
D0
1998 Oct 07
FUNCTION
Recovered symbols. The number of relevant bits are set with DMD2[2 to 0].
45
Philips Semiconductors
Product specification
Pager baseband controller
6.18
PCA5007
AFC-DAC
6.18.1
FUNCTION
The AFC digital-to-analog converter provides an analog signal to the receiver to reduce its frequency offset. The analog
signal is available at pin 18 (AFCOUT).
For low noise sensitivity the DAC output is buffered and can drive a load impedance of 10 kΩ (max.). The output swing
is from rail-to-rail VDD. When the enable signal ENB is at logic 1 a linear binary conversion is performed according to
Table 47.
Below 0.2 V the linearity at the output voltage is not ideal.
When ENB is at logic 0 the AFCOUT pin is tied to VSS and all currents are switched off.
Table 47 Coding of the AFC-DAC
CODE
OUTPUT VOLTAGE
000000
0
000001
1 × 1⁄64VDD
...
...
N
N×
1⁄ V
64 DD
63 ×
1⁄ V
64 DD
...
...
111111
6.18.2
AFC-DAC CONTROL/DATA REGISTER (AFCON)
The AFC-DAC Control/Data register AFCON contains the control bit for enabling the AFC-DAC and the data bits for
setting the output voltage.
Table 48 AFC-DAC Control/Data Register (AFCON, SFR address 9EH)
7
6
5
4
3
2
1
0
ENB
−
AFC5
AFC4
AFC3
AFC2
AFC1
AFC0
Table 49 Description of the AFCON bits
BIT
SYMBOL
AFCON.7
ENB
AFCON.6
−
AFCON.5
AFC5
AFCON.4
AFC4
AFCON.3
AFC3
AFCON.2
AFC2
AFCON.1
AFC1
AFCON.0
AFC0
1998 Oct 07
FUNCTION
enable DAC output
not used.
6-bit value for DAC output according to Table 47
46
Philips Semiconductors
Product specification
Pager baseband controller
6.19
PCA5007
6.19.1
Interrupt system
External events and the real-time-driven on-chip
peripherals require service by the CPU asynchronously to
the execution of any particular section of code. To tie the
asynchronous activities of these functions to normal
program execution a multiple-source, two-priority-level,
nested interrupt system is provided. The interrupt system
is shown in Fig.27. The PCA5007 acknowledges interrupt
requests from fifteen sources as follows:
OVERVIEW
The interrupt controller implemented in the PCA5007 has
15 interrupt sources, of which some are level sensitive and
some are edge sensitive. The interrupt controller samples
all active sources during one instruction cycle; evaluation
of the interrupts is then performed. A priority decoder
decides which interrupt is serviced. Each interrupt has its
own vector pointing to an 8 bytes long program segment.
A low priority interrupt can be interrupted by a high priority
interrupt, but not by another low priority interrupt i.e. only
two interrupt levels are possible. Between the RETI
instruction (Return from Interrupt) and the LCALL to a next
interrupt, there is at least one instruction of the lower
program level executed (see Fig.22).
• INT0 to INT4 and INT6
• Timer 0 and Timer 1
• Wake-up counter
• I2C-bus serial I/O
• UART transmitter and receiver
An interrupt is performed with a long subroutine call
(LCALL) to vector address, which is determined by the
respective interrupt. During LCALL the PC is pushed onto
the stack. Returning from interrupt with RETI, the PC is
popped from the stack.
• Demodulator
• DC/DC converter
• Watchdog timer
• Real-time clock (MINUTE).
Each interrupt vectors to a separate location in program
memory for its service routine. Each source can be
individually enabled or disabled by its corresponding bit in
the Interrupt Enable Registers (IEN0 and IEN1).
The priority level is selected via the Interrupt Priority
Registers (IP0 and IP1). All enabled sources can be
globally disabled or enabled.
Level 20
Level 21
handbook, full pagewidth
RETI
RETI
Interrupt level 2x
IP = 1
RETI
Interrupt level 1
IP = 0
IP = 1
Program level 0
one
instruction
MGR125
Fig.22 Interrupt hierarchy.
1998 Oct 07
47
Philips Semiconductors
Product specification
Pager baseband controller
6.19.2
PCA5007
Clearing the flags: During the forced LCALL the interrupt
flag of the relevant interrupt is cleared by hardware, if
applicable, otherwise by software.
INTERRUPT PROCESS
Sample the interrupt lines: The interrupt lines are
latched at the beginning of each instruction cycle.
Emulation: During emulation the interrupts may be
disabled. This is performed during break mode. With INTD
asserted, all the interrupts are disabled.
Analyse the requests: The sampled interrupt lines will be
analysed with respect to the relevant Interrupt Enable
register (IEx) and Interrupt Priority register (IPx).
The process will deliver the vector of the highest interrupt
request and the priority information. Depending on the
interrupt level and the priority of the interrupt in progress,
an interrupt request to the core is performed. The vector
address will be passed to the core process.
Idle or power-down: When Idle (PCON.0) or power-down
(PCON.1) is set, the interrupt controller waits for the
according WUI signal. Because the interrupt controller is
waiting for WUI, all activity in the circuit will be stopped,
thus no handshake can be completed. The WUI signal for
Idle is the OR of all the interrupt request bits and the reset.
For power-down the WUI signal is built only with the Port 1
interrupt request flags and the reset.
Interrupt request to core:
Level 0: The interrupt request to the core is performed,
when at least one instruction is performed since the
RETI from Level 1.
6.19.3
Level 1: The interrupt request is performed, when at
least one instruction is performed since the RETI from
Level 21 and the request has high priority.
The implementation of the interrupt controller related
SFRs for enabling and disabling interrupts is identical to a
standard 80C51, but the interrupt sources have been
changed according to Table 50.
Level 20: No request is performed.
Level 21: No request is performed.
Emulation: In break mode no interrupt request is
performed.
Update the interrupt level:
Level 0: In the event of a high priority interrupt the new
level will be Level 20. If it is a low priority interrupt, the
new level will be Level 1.
Level 1: In the event of a high priority interrupt, the new
level will be Level 21. A low priority interrupt is not
performed, the level is unchanged. On RETI the new
level will be Level 0.
Level 20: On RETI, the new level is Level 0.
Level 21: On RETI, the new level is Level 1.
Level 1: On RETI, the new level is Level 0.
Level 0: The new level is Level 0.
1998 Oct 07
INTERRUPT CONTROLLER RELATED SFRS
48
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
Table 50 Interrupt controller related SFRs: IEN0 (A8H), IEN1 (E8H), IP0 (B8H), IP1 (F8H), IRQ1 (C0H), TCON (88H),
WUCON (94H) and RTCON (CDH)
BITS
CONV.
NAME
SOURCE
NOTES
IEN0 address A8H: interrupt enable for X0, X1, T0, T1, T2, S0, S1 and global interrupt enable (note 1)
0
EX0
P3.2
1
ET0
TIMER 0
2
EX1
P3.3
3
ET1
TIMER 1
4
ES0
UART
5
ES1
I2C
6
ET2
7
EA
Enables or disables EXTERNAL0 interrupt. If EX0 = 0, the external interrupt 0 is
disabled.
Enables or disables the TIMER 0 overflow interrupt. If ET0 = 0, the Timer 0 interrupt
is disabled.
Enables or disables the EXTERNAL1 interrupt. If EX1 = 0, external interrupt 1 is
disabled.
Enables or disables TIMER 1 overflow interrupt. If ET1 = 0, the Timer 1 interrupt is
disabled.
Enables or disables the UART interrupt. If ES0 = 0, the UART interrupt is disabled.
Enables or disables the I2C-bus interrupt. If ES1 = 0, the I2C-bus interrupt is disabled.
WAKE-UP Enables or disables the WAKE-UP interrupt. If ET2 = 0, the wake-up interrupt is
disabled.
/
Disables all interrupts. If EA = 0, no interrupt will be acknowledged. If EA = 1, each
interrupt source is individually enabled or disabled by setting or clearing its enable bit.
IEN1 address E8H: interrupt enable for X2 to X9 (note 1)
0
EX2
P1.0
Enables or disables interrupts on P1.0. If EX2 = 0, the corresponding interrupt is
disabled.
1
EX3
P1.1
Enables or disables interrupts on P1.1. If EX3 = 0, the corresponding interrupt is
disabled.
2
EX4
P1.2
Enables or disables interrupts on P1.2. If EX4 = 0, the corresponding interrupt is
disabled.
3
EX5
SYMBOL
Enables or disables the SYMBOL interrupt. If EX5 = 0, the SYMBOL interrupt is
disabled.
4
EX6
P1.4
Enables or disables interrupts on P1.4. If EX6 = 0, the corresponding interrupt is
disabled.
5
EX7
DC/DC
6
EX8
WDI
Enables or disables interrupts on the WATCHDOG. If EX8 = 0, the WDINT interrupt is
disabled.
7
EX9
MIN
Enables or disables REAL-TIME CLOCK interrupt. If EX9 = 0, the MINUTE interrupt
is disabled.
Enables or disables the DC/DC CONVERTER interrupt. If EX7 = 0, the DC/DC
converter interrupt is disabled.
IP0 address B8H: interrupt priority for X0, X1, T0, T1, T2, S0 and S1 (note 2)
0
PX0
P3.2
Defines the EXTERNAL0 interrupt 0 priority level. PX0 = 1 programs it to the higher
priority level.
1
PT0
TIMER 0
Enables or disables the TIMER 0 interrupt priority level. PT0 = 1 programs it to the
higher priority level.
2
PX1
P3.3
Defines the EXTERNAL1 interrupt priority level. PX1 = 1 programs it to the higher
priority level.
3
PT1
TIMER 1
1998 Oct 07
Defines the TIMER 1 interrupt priority level. PT1 = 1 programs it to the higher priority
level.
49
Philips Semiconductors
Product specification
Pager baseband controller
BITS
CONV.
NAME
SOURCE
4
PS0
UART
5
PS1
I2C
6
PT2
7
−
PCA5007
NOTES
Defines the UART interrupt priority level. PS0 = 1 programs it to the higher priority
level.
Defines the I2C-bus interrupt priority level. PS1 = 1 programs it to the higher priority
level.
WAKE-UP Defines the WAKE-UP interrupt priority level. PT2 = 1 programs it to the higher
priority level.
/
unused
IP1 address F8H: interrupt priority for X2 to X9 (note 2)
0
PX2
P1.0
Defines the EXTERNAL2 interrupt priority level 1. PX2 = 1 programs it to the higher
priority level.
1
PX3
P1.1
Defines the EXTERNAL3 interrupt priority level 1. PX3 = 1 programs it to the higher
priority level.
2
PX4
P1.2
Defines the EXTERNAL4 interrupt priority level 1. PX4 = 1 programs it to the higher
priority level.
3
PX5
SYMBOL
4
PX6
P1.4
Defines the EXTERNAL6 interrupt priority level 1. PX6 = 1 programs it to the higher
priority level.
5
PX7
DC/DC
Defines the DC/DC CONVERTER interrupt priority level 1. PX7 = 1 programs it to the
higher priority level.
6
PX8
WDI
Defines the WATCHDOG interrupt priority level 1. PX8 = 1 programs it to the higher
priority level.
7
PX9
MIN
Defines the REAL-TIME CLOCK interrupt priority level 1. PX9 = 1 programs it to the
higher priority level.
Defines the SYMBOL interrupt priority level 1. PX5 = 1 programs it to the higher
priority level.
TCON address 88H: timer/counter mode control register
0
IT0
P3.2
EXTERNAL0 interrupt type control bit. Set/cleared by software to specify falling
edge/low level triggered external interrupt.
1
IE0
P3.2
EXTERNAL0 interrupt flag. Set by hardware when external Interrupt detected.
Cleared by hardware.
2
IT1
P3.3
EXTERNAL1 interrupt type control bit. Set/cleared by software to specify falling
edge/low level triggered external interrupt.
3
IE1
P3.3
EXTERNAL1 interrupt flag. Set by hardware when external Interrupt detected.
Cleared by hardware.
4
TR0
TIMER 0
Timer 0 run control bit. Set/cleared by software to turn timer on/off.
5
TF0
TIMER 0
Timer 0 overflow flag. Set by hardware on timer/counter overflow. Cleared by
hardware or software.
6
TR1
TIMER 1
Timer 1 run control bit. Set/cleared by software to turn timer on/off.
7
TF1
TIMER 1
Timer 1 overflow flag. Set by hardware on timer/counter overflow. Cleared by
hardware or software.
IRQ1 address C0H: interrupt request register for X2 to X9
0
IQ2
P1.0
Interrupt request flag from P1.0.
1
IQ3
P1.1
Interrupt request flag from P1.1.
1998 Oct 07
50
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
BITS
CONV.
NAME
SOURCE
2
IQ4
P1.2
3
IQ5
SYMBOL
4
IQ6
P1.4
5
IQ7
DC/DC
6
IQ8
WDI
Interrupt request flag from watchdog timer. Set by hardware or software. Cleared by
software.
7
IQ9
MIN
Interrupt request flag from real-time clock interrupt. Set by hardware or software.
Cleared by software.
NOTES
Interrupt request flag from P1.2.
Interrupt request flag from clock recovery circuit. Set by hardware or software.
Cleared by software.
Interrupt request flag from P1.4.
Interrupt request flag from DC/DC CONVERTER. Set by hardware or software.
Cleared by software.
WUCON address 94H: wake-up counter control register
0
SET
−
Latch signal to copy content of WUC to peripheral register.
1
LOAD
−
Parallel load signal for wake-up counter.
2
Z0
−
3
Z1
−
4
CPL
−
5
unused
−
6
WUP
−
WUP interrupt flag from wake-up counter timer. Set by hardware or software. Cleared
by software.
7
RUN
−
RUN bit for wake-up counter.
Complete interrupt flag from wake-up counter timer. Set by hardware or software.
Cleared by software.
RTCON address CDH: real-time clock control register
0
SET
−
Latch signal to copy content of WUC to peripheral register.
1
LOAD
−
Load RTC0 value from SFR to RTC.
2
W/R
−
Disable write back to SFR.
3 to 6
unused
−
7
MIN
−
Interrupt request flag from RTC. Set by hardware or software. Cleared by software.
Notes
1. IEN0 and IEN1: These are two 8-bit registers that control the enabling of the 15 interrupt sources individually as well
as a global enable/disable for all of the sources.
2. IP0 and IP1: These are two 8-bit registers that set priority for each interrupt source. IP0 actually contains only 7 bits
as IP.7 is not implemented. This bit will always read as logic 0.
1998 Oct 07
51
Philips Semiconductors
Product specification
Pager baseband controller
6.19.4
PCA5007
PORT 3 INTERRUPTS: P3.2 AND P3.3
6.19.5
INT0 and INT1 are level or edge sensitive.
The programming is performed with TCON. Since P3.2
and P3.3 are configured as push-pull outputs, these
interrupts can only be triggered by output commands to
these ports and not by external events.
WAKE-UP INTERRUPT
The wake-up interrupt (T2) is the level sensitive OR
function of the WUP bit or CPL bit in the WUCON SFR.
The wake-up interrupt is mapped to the T2 vector
(see Fig.24). These flags are set by hardware and need to
be cleared by software. For more information see
Section 6.14.
TCON.0 (IT0): Interrupt 0 type control bit. Set/cleared by
software to specify falling edge/low level triggered
external interrupt (see Fig.23).
WUCON.6 (WUP): WUP interrupt flag. Attention: writing
and reading this SFR bit does not access the same flag.
The flag is set by hardware and needs to be cleared by
software.
TCON.1 (IE0): Interrupt 0 flag. Set by hardware when
an external interrupt is detected. Cleared by hardware
when the service routine is called.
WUCON.4 (CPL): Complete flag. The previous set
instruction is completed. The settings of the SFR have
been copied to the peripheral block. The flag is set by
hardware and needs to be cleared by software.
TCON.2 (IT1): Interrupt 1 type control bit. Set/cleared by
software to specify falling edge/low level triggered
external interrupt.
TCON.3 (IE1): Interrupt 0 flag. Set by hardware when
an external interrupt is detected. Cleared by hardware
when the service routine is called.
handbook, full pagewidth
Pad Port 3.2
0
INT0
X0
IE0
1
IT0
(interrupt edge flag)
MGR126
Fig.23 External interrupt Port 3.2 and Port 3.3 (INT0 and INT1).
handbook, full pagewidth
WUP
WAKE-UP
COUNTER
≥1
T2
CPL
MGR1127
Fig.24 Wake-up interrupt.
1998 Oct 07
52
Philips Semiconductors
Product specification
Pager baseband controller
6.19.6
PCA5007
The IRQ bits are not set if the corresponding enable is not
set.
PORT 1 INTERRUPTS: PORT 1.0 TO PORT 1.4
(INT2 TO INT6)
IRQ1.3: (symbol interrupt); this interrupt request flag, if
enabled, is set if the demodulator (clock recovery) has
data ready, that should be read by the microcontroller.
The event is called symbol clock or SymClk, because in
one mode of operation one symbol is delivered per
interrupt. The flag is set by hardware and needs to be
cleared by software.
Four Port 1 lines can be used as external interrupt inputs
(see Fig.25). When enabled (IEN1 SFR), each of these
lines can wake-up the device from power-down. Using the
IX1 register, each of these port lines may be set active to
either HIGH or LOW. IRQ1 is the interrupt request flag
register. Each flag, if the interrupt is enabled, will send an
interrupt request, but must be cleared by software, i.e. via
the interrupt software. The Port 1 interrupt request flags
can only be set if the corresponding interrupt enable bit is
set.
6.19.7
IRQ1.5: (DC/DC converter interrupt); this interrupt
request flag, if enabled, is set if the DC/DC converter is
not able to deliver the required current (STB flag
cleared). The flag is set by hardware and needs to be
cleared by software.
MORE INTERRUPTS: SYMCLK, DC/DC
CONVERTER, WATCHDOG AND MINUTE
IRQ1.6: (watchdog interrupt); this interrupt request flag,
if enabled, is set if the watchdog timer will expire within
1⁄ s. The flag is set by hardware and needs to be
16
cleared by software.
The decoder blocks generate events that can force an
interrupt when enabled (IEN0 and IEN1 SFR). These
interrupts are mapped to the corresponding P1 interrupt
request flag register bits (see Fig.26). Each flag, if the
interrupt is enabled, will send an interrupt request and
must be cleared by software, i.e. via the interrupt service
routine.
IRQ1.7: (minute interrupt); this interrupt request flag, if
enabled, is set once each minute by the real-time clock.
The flag is set by hardware and needs to be cleared by
software.
handbook, full pagewidth
Pad Port 1.0
0
INT2
X2
IRQ1.0
1
IX1.0
IEN1.0
wake-up.0
MGR128
Fig.25 Interrupt Port 1.0.
handbook, full pagewidth
CLOCK
RECOVERY
BLOCK
SymClk
IRQ1.3
X5
IEN1.3
MGR129
Fig.26 SymClk (as an example for any of the 4 mentioned interrupts).
1998 Oct 07
53
Philips Semiconductors
Product specification
Pager baseband controller
6.19.8
PCA5007
INTERRUPT HANDLING
Figure 27 shows the conventions for interrupt assignments and priorities.
Arbitration of several simultaneous interrupts can be seen from Fig.27. The sampled interrupt with the highest priority will
be handled first (assuming that the interrupt priority is default).
Setting of interrupt request flags for X2 to X9 is masked by the corresponding interrupt enable bit (IEN1).
cleared
handbook, vector
full pagewidth
function
Port
Name
Flag
by
IEN0/1
X0
IE0
I2C-bus
S1
SI
SW
SymClk
X5
SYM
0B
HW
Timer 0
T0
TF0
33
SW
Wake-up
T2
WUP
5B
SW
INT6
P1.4
X6
IQ6
13
HW
INT1
P3.3
X1
IE1
3B
SW
INT2
P1.0
X2
IQ2
63
SW
DC/DC
X7
DC
1B
HW
Timer 1
T1
TF1
43
SW
INT3
X3
IQ3
6B
SW
WDINT
X8
WDI
23
SW
UART
S0
TI/RI
4B
SW
INT4
X4
IQ4
73
SW
MINUTE
X9
MIN
03
HW
INT0
2B
SW
53
P3.2
P1.1
P1.2
IP0/1
TCON.1
0.0
0.0
S1CON.3
0.5
0.5
IRQ1.3
1.3
1.3
TCON.5
0.1
0.1
WUCON.6
0.6
0.6
IRQ1.4
1.4
1.4
TCON.3
0.2
0.2
IRQ.0
1.0
1.0
IRQ1.5
1.5
1.5
TCON.7
0.3
0.3
IRQ1.1
1.1
1.1
IRQ1.6
1.6
1.6
S0CON.0/1
0.4
0.4
IRQ1.2
1.2
1.2
RTCON.7
1.7
1.7
PRIORITY
high
low
decreasing
priority
within
same
level
0.7
global
enable
The signal level applied to the EAN pin defines whether the interrupt vector code is fetched from external or internal ROM.
Fig.27 Interrupt assignment and priorities.
1998 Oct 07
54
MGR130
Philips Semiconductors
Product specification
Pager baseband controller
6.20
PCA5007
Idle and power-down operation
6.20.2
Idle and power-down are power saving modes of the
microcontroller that can be activated when no CPU activity
is required. Both modes do not stop the 76.8 kHz oscillator
nor disable any peripheral function.
POWER-DOWN MODE
• Wake-up counter
The instruction that sets PCON.1 is the last instruction
executed in the normal operating mode before the
power-down mode is activated. Once in the power-down
mode, the CPU status is preserved together with the stack
pointer, program counter, program status word and
accumulator. The RAM and all other registers maintain
their data during power-down mode. The status of the
external pins during power-down mode is shown in
Table 51.
• Watchdog counter
There are two ways to terminate the power-down mode:
• Real-time clock
1. Activation of an enabled external interrupt
(INT2 to INT9) will cause PCON.1 to be cleared by
hardware thus terminating the power-down mode.
The interrupt is serviced, and following the RETI
instruction, the next instruction to be executed will be
the one following the instruction that put the device in
the power-down mode.
The following functions remain active during the Idle
mode.
• Timer 0 and Timer 1
• Demodulator and clock recovery
• UART
• I2C-bus
• External interrupt.
6.20.1
IDLE MODE
2. The second way of terminating the power-down mode
is with an internal or external hardware reset. Reset
redefines all SFRs but does not affect the on-chip
RAM. Possible sources of an internal reset are
The instruction that sets PCON.0 is the last instruction
executed in the normal operating mode before the Idle
mode is activated. Once in the Idle mode, the CPU status
is preserved together with the stack pointer, program
counter, program status word and accumulator. The RAM
and all other registers maintain their data during Idle mode.
The status of the external pins during Idle mode is shown
in Table 51.
a) Watchdog reset if the watchdog had expired
b) OFF-ON reset if the DC/DC converter is restarted
from the off mode (wake-up counter or P1 pins).
The power-down mode is not especially useful. It has been
implemented for compatibility only. The Idle mode has the
same power saving capability and allows much more
flexible wake-up.
There are two ways to terminate the Idle mode:
1. Activation of any enabled interrupt will cause PCON.0
to be cleared by hardware thus terminating the Idle
mode. The interrupt is serviced, and following the
RETI instruction, the next instruction to be executed
will be the one following the instruction that put the
device into the Idle mode. The flag bits GF0 and GF1
may be used to determine whether the interrupt was
received during normal execution or during the Idle
mode. For example, the instruction that writes to
PCON.0 can also set or clear one or both flag bits.
When the Idle mode is terminated by an interrupt, the
service routine can examine the status of the flag bits.
6.20.3
OFF MODE
The off mode has been designed as the power saving
mode of the PCA5007. Shortly after entering this mode the
DC/DC converter is switched off and VDD is reduced to
VBAT. Directly after activating the off mode, the CPU must
be set in Idle mode.
The off mode is entered by:
1. ORL DCCON0, #80H
2. ORL PCON, #01H.
2. The second way of terminating the Idle mode is with an
internal or external hardware reset. Reset redefines all
SFRs but does not affect the on-chip RAM. Possible
sources of an internal reset are:
The off mode can be exited by one of the following events:
• RTC minute event
• Wake-up counter event
a) Watchdog reset if the watchdog had expired
• Event on any P1 pin
b) Off/on reset if the DC/DC converter is restarted
from the off mode (wake-up counter, RTC or
P1 pins).
• RESETIN active HIGH.
1998 Oct 07
55
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
Each of these events first starts the DC/DC converter to
ramp up VDD to 2.2 V. After an initial reset, generated by
the DC/DC converter when VDD is again at normal level, all
2 V blocks will restart their operation. The first instruction
will be fetched from address 0.
6.20.4
STATUS OF EXTERNAL PINS
The status of the external pins during Idle and power-down
mode is shown in Table 51.
The edge sensitive interrupts (minute and wake-up) from
the internal sources will have been lost during restart and
must be polled from their SFRs. Events from P1 pins can
be served after enabling the interrupts, since they are level
sensitive.
Table 51 Status of external pins during normal, Idle and power-down modes
MODE
Normal
Idle
Power-down
MEMORY
ALE
PSEN
PORT 0
PORT 1
PORT 2
PORT 3
internal
0
1
port data
port data
port data
port data
internal
1
1
port data
port data
port data
port data
external
1
1
pull-up HIGH
port data
address
port data
internal
0
0
pull-up HIGH
port data
port data
port data
external
0
0
pull-up HIGH
port data
address
port data
POWER CONTROL REGISTER (PCON)
6.20.5
The reduced power modes are activated by software using this special function register. PCON is not bit addressable.
Table 52 Power Control Register (PCON and SFR address 87H)
7
6
5
4
3
2
1
0
SMOD
XRE
ENIS
−
GF1
GF0
PD
IDL
Table 53 Power Control Register (PCON, SFR address 87H)
BIT
SYMBOL
FUNCTION
PCON.7
PCON.6
SMOD
XRE
PCON.5
ENIS
PCON.4
PCON.3
PCON.2
PCON.1
PCON.0
−
GF1
GF0
PD
IDL
Control bit to double data rate of UART, when set to logic 1.
If set to logic 1 enables external XRAM from address 0 on, if set to logic 0 the first
768 XRAM bytes are in internal XRAM, the higher addresses come from external
XRAM; see note 2.
Enable ISYNC. If bit is set, ISYNC can be monitored at pin EA in internal access mode.
The binary value of ISYNC changes each time a new instruction is fetched from
memory. This bit must not be set to logic 1 by user program!
reserved
General purpose flag bit.
General purpose flag bit.
Power-down bit. Setting this bit activates the power-down mode; see note 1.
Idle mode bit. Setting this bit activates the Idle mode; see note 1.
Notes
1. If logic 1s are written to PD and IDL at the same time, PD takes precedence. The reset value of PCON is (00000000).
2. This device does not support external XRAM access. Therefore the XRE bit is meaningless and should never be
written to logic 1.
1998 Oct 07
56
Philips Semiconductors
Product specification
Pager baseband controller
6.21
PCA5007
Reset
6.21.2
To initialize the PCA5007 a reset is performed by using
either of the 2 following methods:
An automatic reset can be obtained by connecting the
RESETIN pin to VBAT via a capacitor and to VSS via a
resistor. At power-on, the voltage on the RESETIN pin is
equal to VBAT and decreases from VBAT as the capacitor
charges through the resistor to VSS. VRESETIN must remain
higher than the threshold of the Schmitt trigger for a
duration of tRESETIN (see Chapter “AC characteristics”).
The reset configuration is shown in Fig.28.
• Applying an external reset signal to the RESETIN pin
• Via the on-chip watchdog timer.
The reset state of the output pins is given in separate
tables (Tables 2 to 6). The reset state of the SFRs is given
in a separate overview (see Table 1).
While a reset is applied to the device the output RESOUT
is driven LOW.
6.21.3
The internal RAM is not affected by reset. When VDD is
turned on, the RAM contents are indeterminate.
6.21.1
EXTERNAL POWER-ON RESET USING THE RESETIN
PIN
INTERNAL RESET
The watchdog which is available in the PCA5007
(see Section 6.16) will force a reset if it is enabled and
expires.
EXTERNAL RESET USING THE RESETIN PIN
A reset is also forced, when the DC/DC converter restarts
operation from the off mode (see Section 6.22.3).
The external reset input for the PCA5007 is the RESETIN
pin. A Schmitt trigger is used at the input for noise
rejection. Immediately after pin RESETIN goes HIGH, an
internal reset is executed. As a consequence the SFRs
and port pins adopt their reset state, ALE and PSEN are
held HIGH. As long as the RESETIN pin stays HIGH, the
reset state is maintained. When RESETIN goes LOW, the
device start-up sequence is executed (see Section 6.22).
All resets to the microcontroller can be observed as
negative pulses at the output RESOUT.
handbook, full pagewidth
VBAT
PCA5007
10 µF
RESETIN
RESOUT
RESET AND
POWER
CONTROLLER
watchdog
restart DC/DC
converter
VBAT
10 kΩ
VSS
internal reset
for microcontroller
MGR131
Fig.28 Application diagram for external power-on reset configuration.
1998 Oct 07
57
Philips Semiconductors
Product specification
Pager baseband controller
6.22
6.22.1
PCA5007
For a certain current load (IL) the controller settles to a
stable voltage VDD (IL) between 2.15 to 2.25 V. Increasing
the load decreases VDD (IL) by a small amount. When
VDD (IL) drops below 2.15 V the DC/DC converter
calculates a new set of coefficients and VDD (IL) settles
again between 2.15 and 2.25 V (see Fig.38).
DC/DC converter
FUNCTION
The DC/DC converter converts the voltage from a single
primary cell (0.9 to 1.6 V) to a nominal 2.2 V supply
voltage for on-chip and off-chip use. For EMC reasons a
special technique is used to minimize coil current ripples
under all load conditions.
The voltage generated by the DC/DC converter is
available at pin VDD(DC). The supply for all functions of the
chip is taken from the VDD and VDDA pins. The user has to
connect VDD(DC) to the other VDD pins. The supply used for
the reference and comparators is taken from VDDA.
A typical circuit configuration is shown in Fig.29.
handbook, full pagewidth
L
VBAT
0.9
to
1.6 V
D1
470 µH
VDD
VDD(DC)
VIND
Ci
4.7
µF
Co
4.7 µF
PCA5007
VBAT
VDD
VDDA
BLI
2.25 V
C1
RESETIN
R1
DIGITAL
CONTROL
BAND GAP
2.15 V
6 MHz
MICROCONTROLLER
VSS, VSSA
Fig.29 Typical operating circuit.
1998 Oct 07
58
MGR132
Philips Semiconductors
Product specification
Pager baseband controller
6.22.2
PCA5007
The efficiency is determined by the series resistance RS
and the current consumption of the converter itself. RS is
the sum of the battery resistance RBAT, the DC resistance
SRL of the coil, the on resistance of the MOSFET RDS,on
and the ESR of the output capacitor Co. Figure 32a shows
the efficiency when using a 470 µH coil with a SRL of 5 Ω
and a load capacitor of 4.7 µF with an ESR of 0.5 Ω.
In Fig.32b the efficiency for the same configuration is
shown but with a SRL of only 0.1 Ω. To increase efficiency
for extremely low output currents, the converter should be
set into standby mode (see Fig.33).
TYPICAL OPERATING CHARACTERISTICS
The maximum power delivered by the DC/DC converter is
given by equation (1).
2
( V Bat )
P o(max) ≤ -------------------4 × Rs
(1)
Rs is the total series resistance which is the sum of
RBAT + Rind + Rsw + ESR(Co). In Figs 30 and 31 the
maximum available output current (IL) is shown as a
function of VBAT and Rs.
MGR345
8
handbook, full pagewidth
Rs
(Ω)
7
15
30
35
20
6
25
40
30
5
4
20
35
45
40
25
55
50
30
35
40
3
55
50
60
70
65
80
70
2
0.8
1
60
45
1.2
75
1.4
75
90
100
VBAT (V)
VDD = 2.2 V; RS = RBAT + Rind + Rsw
Fig.30 Maximum available output current (mA) in normal mode.
1998 Oct 07
59
1.6
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
MGR346
8
handbook, full pagewidth
25
15
35
25
5
40
30
20
10
3.5
6
35
12.5
5
7.5
2
7
1
30
Rs
(Ω)
40
50
20
30
15
7.5
10
3.5
2
4
12.5
5
1
45
35
45
65
70
60
3
50
2
0.8
1
55
80
1.2
1.4
VBAT (V)
1.6
VDD = 2.2 V; Rs = RBAT + Rind + Rsw
Fig.31 Maximum available output current (mA) in standby mode.
MGR134
MGR135
100
100
handbook, halfpage
handbook, halfpage
η
η
(%)
(%)
(1)
(3)
(1)
(2)
80
80
(2)
(3)
60
60
40
40
20
20
0
0
4
8
12
16
0
20
0
4
8
12
a. Rs = 6 Ω.
b. Rs = 1 Ω.
(1) VBAT = 1.5 V.
(2) VBAT = 1.2 V.
(3) VBAT = 0.9 V.
Fig.32 Efficiency in normal mode as a function of load current.
1998 Oct 07
16
20
IL (mA)
IL (mA)
60
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
MGR136
100
handbook, halfpage
η
(%)
80
(1)
(2)
(3)
60
40
20
0
0
1
2
3
IL (mA)
4
(1) VBAT = 1.5 V.
(2) VBAT = 1.2 V.
(3) VBAT = 0.9 V.
Fig.33 Efficiency in standby mode as a function of load current.
6.22.3
6.22.3.1
4. Boost up VDD to 2.2 V using the internal 6 MHz clock
and the p-channel MOSFET. As soon as
VDD ≥ 2.15 V, the stable flag is set to indicate that the
system is powered-up successfully and the
microcontroller starts operating. The DC/DC converter
now stays in the normal mode of the normal operating
mode.
START-UP DESCRIPTION
Start-up from reset
An external RC network together with an on-chip Schmitt
trigger is used to generate a reset pulse after the insertion
of a new battery (see Section 6.21). A reset pulse at the
RESETIN pin resets the SFRs and the internal registers of
the DC/DC converter to the factory programmed values
and the start-up sequence shown in Fig.34 is started.
The reset pulse must be essentially longer then the rise
time of VBAT.
If a reset pulse is generated during normal operation, the
DC/DC converter immediately resets the whole system
and enters the start-up sequence.
The start-up sequence is divided into several steps:
6.22.3.2
1. Start-up 76.8 kHz crystal oscillator (256 clocks).
Start-up from off mode behaves exactly as start-up from
external reset (see Fig.34) except that:
2. Boost up of VDD to approximately 1.7 V using the
76.8 kHz clock. During this phase, the p-channel
MOSFET is switched off and the charge is transferred
via the external Schottky diode.
• The internal registers of the DC/DC converter are not
reset; however the DC/DC converter SFRs are reset.
off mode is exited when one of the following events occur:
1
3. Start of the 6 MHz clock  2 × -----------------------  ;
76.8 kHz
• Key pressed
• Minute interrupt
(see Section 6.12).
1998 Oct 07
Start-up from off mode
• Wake-up interrupt.
61
Philips Semiconductors
Product specification
Pager baseband controller
handbook, full pagewidth
PCA5007
microcontroller
DC/DC converter
RESETIN
reset internal register
VDD OK = 0
STABLE = 0
Delay = 256T
start DC/DC using
76.8 kHz clock
Wait until VDD > 1.7 V
(up to some ms)
RESTART =
INIT
Z_R active
RESOUT active
RESET
RESOUT active
VDD OK = 1
Delay = 2T
DC/DC uses 6 MHz
Wait until VDD > 2.2 V
(<1 ms)
OPERATING
STABLE = 1
NORM
STANDBY
microcontroller sets
OFF bit in
DCCON0 SFR
normal operation mode
watchdog
expires
MGR137
Delay = 15T
DC/DC:
VDD set to VBAT
VDD OK = 0
OFF
keys or
wake-up or
minute or
watchdog reset
(T = period of XTL1 input signal)
Fig.34 System power-up/off sequencing.
1998 Oct 07
62
Philips Semiconductors
Product specification
Pager baseband controller
6.22.4
6.22.4.1
PCA5007
When the load is so high that the required output current
cannot be delivered, the DC/DC converter resets the
signal STB and a DC/DC interrupt is issued to the
processor via IRQ SFR IRQ1.5. STB = 0 flags the inability
to deliver enough current in normal mode or in standby
mode. When the STB flag is set to logic 0, VDD can drop
very quickly, depending on the battery voltage and the
load.
DESCRIPTION OF OPERATING MODES
Normal operating mode
Once the system is powered-up successfully (STB = 1),
the DC/DC converter is in normal operating mode. This
mode has two sub modes:
• Normal mode
• Standby mode.
6.22.4.3
By setting/resetting the standby bit in DCCON0 (D1H), the
DC/DC converter switches between the normal mode and
the standby mode. Switching between these two modes is
possible at any time by software if the controller is in the
normal operating mode. Normal operating mode can be
exited by any of the following events:
Standby mode is a low current mode which can be used
when only the microcontroller is running and the quality of
VDD is not important. In standby mode the DC/DC
converter uses the 76.8 kHz clock instead of the 6 MHz
clock. This reduces the current consumption of the DC/DC
converter. The maximum output current in this mode is
limited to a few milliamperes (see Fig.31). In standby mode
VDD can be set to 1.9, 2.0, 2.1 or 2.2 V by setting the
VLO1 and VLO0 bits in DCCON1 to the corresponding
values. When the load is so high that the required output
current cannot be delivered, the DC/DC converter resets
the signal STB and a DC/DC interrupt is issued to the
processor via IRQ SFR IRQ1.5. In this case, the
microcontroller should switch-off the different loads and
switch to normal mode.
• HIGH level at the RESETIN pin
• A watchdog reset, which will force the same sequence
as an off command
• Writing the off bit in DCCON0.
Setting the off bit in DCCON0 forces the converter into
DC/DC converter off mode.
6.22.4.2
Normal mode
Normal mode is the high efficiency mode of the DC/DC
converter. In this mode the controller can keep VDD stable
at 2.2 V up to the maximum available current (see Fig.30).
The output voltage is regulated in a small window and the
current peaks in the coil are kept as small as possible
(see Fig.36). After a reset and the following start-up
sequence, the controller is in normal mode.
6.22.4.4
Off mode
The off mode can only be entered by setting the off bit in
DCCON0 by software. The DC/DC converter waits for
15 periods of the 76.8 kHz clock before it sets VDD to VBAT
and switches off completely (see Fig.34). In the off mode
the PMOS is conducting and therefore it is guaranteed that
VDD never drops below VBAT − 100 mV. When the DC/DC
converter is in the off mode, one of the following events
can restart the converter:
To shorten the settling time when the receiver is switched
on or off, the DC/DC converter uses 2 sets of coefficients.
One for low output current and one for high output current.
When the RXE bit in DCCON0 is set, the DC/DC converter
stores the actual coefficients for low output current and
switches to the coefficients for high load current. At the
same time, the receiver should be enabled. If the battery
voltage did not change very much since the last time the
receiver was on, the settling time is only a few
microseconds instead of a few hundreds of microseconds
when not using the RXE bit. When switching off the
receiver, the RXE bit in DCCON0 should be reset. In this
case, the DC/DC converter stores the new values for high
output current and restores the values for low output
current. It should be noted that the RXE bit does not
change the algorithm of the DC/DC converter but shortens
the settling time dramatically.
1998 Oct 07
Standby mode
• P1X (independent from interrupt enabling or polarity)
• Minute
• Wake-up
• RESETIN pulse.
63
Philips Semiconductors
Product specification
Pager baseband controller
6.22.5
PCA5007
VOLTAGE/CURRENT RIPPLE
The ripples are determined by VBAT, inductance L, Co, ESR (Equivalent Series Resistance of Co, switching frequency
and the load current IL. The ripples are illustrated in Fig.36. If ESR = 0 Ω, then Vripple = ∆V.
handbook, full pagewidth
IL
D1
L
ESR
P
VBAT
Ci
N
VC
VDD
IL
Co
MGR138
Fig.35 Circuit to analyse ripples.
handbook, full pagewidth
VDD
Vripple
∆V
t
IL
IL
Imean
Ipeak
Iripple
Imean
t
tp
tn
t
tn
MGR139
Tsw
a. Normal mode.
b. Standby mode.
Fig.36 Zoom-in on the voltage and current ripples.
1998 Oct 07
64
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
Table 54 Ripples in normal operating mode
MODE
STANDBY
tn
I peak = V BAT × ---L
NORM
tn = 6.51 µs
tn = 1 µs, 2 µs, 4 µs
tn
I ripple = V BAT × ---L
0.2 ≤ Dp ≤ 0.73
IL
I L(mean) = -----Dp
IL × tn
∆V = -------------Co
tn = 6.51 µs
V BAT × t n
V ripple = ----------------------- × ESR
L
tn = 6.51 µs
6.22.6
tn = 1 µs, 2 µs, 4 µs
IL × tn
∆V = -------------Co

1 V BAT × t n 
V ripple =  I mean + --- × -----------------------  × ESR
2
L
tn = 1 µs, 2 µs, 4 µs
SWITCHING FREQUENCIES
Depending on the load and more importantly on the battery voltage the controller uses different on and off times for the
NMOS and PMOS transistors. This results in different switching frequencies. If the 6 MHz ring oscillator is trimmed to
6 MHz (see Section 6.12) the switching frequency is 120 kHz ≤ fsw ≤ 400 kHz. A typical frequency behaviour is shown in
Fig.37.
MGR140
400
handbook, halfpage
fsw
(kHz)
(1)
300
(2)
200
(3)
100
0
4
8
12
16
20
IL (mA)
L = 470 µH; SRL = 5 Ω; Co = 4.7 µF; ESR = 0.5 Ω.
(1) VBAT = 1.5 V.
(2) VBAT = 1.2 V.
(3) VBAT = 1.0 V.
Fig.37 Switching frequencies.
1998 Oct 07
65
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
MGR141
handbook, full pagewidth
2.25
VDD
VDD (IL) mean
(V)
2.20
2.15
HF
ripple
2.10
0
4
8
12
16
IL (mA)
20
VBAT = 1.2 V; L = 470 µH; SRL = 5 Ω; Co = 4.7 µF; ESR = 0.5 Ω.
Fig.38 VDD as a function of load current.
6.22.7
VDD ADJUSTMENT
6.22.8
Battery low measurement is enabled by setting the SBLI
bit in DCCON0. 0.5 ms after setting SBLI to logic 1 the BLI
bit in DCCON0 will contain the measurement result. When
BLI = 0 the battery voltage is below 1.1 V. When BLI = 1
VBAT is above 1.1 V. When SBLI = 1 VBAT is measured
continuously. Setting SBLI to logic 0 disables the VBAT
comparator and BLI is set to logic 1. After a reset pulse at
RESETIN, SBLI is reset to logic 0.
VDD can be shifted in four steps by adjusting the band gap
voltage. The band gap voltage is set with the two bits
VBG1 and VBG0 in DCCON1, see Table 55.
Table 55 VDD adjustment
VBG1
VBG0
0
0
OUTPUT VOLTAGE
VDD
0
1
VDD − 50 mV
1
0
VDD + 50 mV
1
1
VDD + 100 mV
1998 Oct 07
BATTERY LOW MEASUREMENT
66
Philips Semiconductors
Product specification
Pager baseband controller
6.22.9
PCA5007
DC/DC CONTROL REGISTER (DCCON0)
The DCCON0 special function register is used to control the operation of the on-chip DC/DC converter.
Table 56 DC/DC Control Register (DCCON0, SFR address D1H)
7
6
5
4
3
2
1
0
OFF
SBY
RXE
SBLI
−
−
STB
BLI
Table 57 Description of the DCCON0 bits
BIT
SYMBOL
FUNCTION
DCCON0.7
OFF
Writing this SFR bit to logic 1 puts the DC/DC converter in the off mode (independent of
other control bits).
DCCON0.6
SBY
Writing this SFR bit to logic 1 puts the DC/DC converter in standby mode, where the
DC/DC converter is clocked from the 76.8 kHz oscillator and the ripple voltage will be
higher. If the DC/DC converter is unable to deliver enough current in SBY mode, the
software has to reset the SBY mode.
DCCON0.5
RXE
Writing this SFR bit to logic 1 uses the stored set of coefficients from a local register to
force the DC/DC converter into the state which is appropriate for the required current.
The contents of this local register are maintained when the DC/DC converter is set into
off state. For the first time after connecting VBAT a set of default coefficients is used.
Writing this bit to logic 0 copies the actual coefficients used momentary by the DC/DC
converter back to the local register.
DCCON0.4
SBLI
Writing this SFR bit to logic 1 enables the circuitry for measurement of the battery
voltage. The new BLI value is valid 0.5 ms later. In order to make a new measurement,
the receiver should draw current (continuous mode of DC/DC converter). If SBLI is
logic 0 (BLI measurement disabled) BLI will go to HIGH.
DCCON0.3
−
unused
DCCON0.2
−
unused
DCCON0.1
STB
Set by the DC/DC converter after power-up. Reset by the DC/DC converter if the
converter is not able to deliver the required power. The signal is set in SBY and non
SBY mode. This bit is read only.
DCCON0.0
BLI
Battery low indicator. Set by the DC/DC converter if VBAT < 1100 mV ±50 mV. This bit
is read only.
1998 Oct 07
67
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
6.22.10 DC/DC ADJUST CONTROL REGISTER (DCCON1)
The DCCON1 special function register is used to adjust the exact voltage levels of the on-chip DC/DC converter.
Table 58 DC/DC Adjust Control Register (DCCON1, SFR address D2H)
7
6
5
4
3
2
1
0
VBG1
VBG0
VLO1
VLO0
−
−
−
−
Table 59 Description of the DCCON1 bits
7
BIT
SYMBOL
FUNCTION
DCCON1.7
VBG1
DCCON1.6
VBG0
DCCON1.5
VLO1
DCCON1.4
VLO0
DCCON1.3
−
unused
DCCON1.2
−
unused
DCCON1.1
−
unused
DCCON1.0
−
unused
Adjustment for band gap voltage; used to trim the band gap voltage [00] = 1.260 V,
[01] = 1.233 V, [10] = 1.286 V, [11] = 1.312 V.
Adjustment for DC/DC converter output voltage in standby mode; [00] = 1.9 V,
[01] = 2.0 V, [10] = 2.1 V, [11] = 2.2 V.
INSTRUCTION SET
The PBB family uses a powerful instruction set which permits the expansion of on-chip CPU peripherals and optimizes
power consumption in Idle and active modes as well as byte efficiency and execution speed. Typical execution times and
energy consumption at a VDD of 2.2 V are given in Table 60. Attention: for most opcodes the numbers for execution
speed and energy are also strongly dependant on the data (ADD, SUBB, DEC, INC, MUL, DIV, DA, conditional jumps
etc.) and the operand address (CPU internal SFRs or SFRs in a peripheral block).
Table 60 Instruction set
MNEMONIC
DESCRIPTION
BYTES
EXEC.
TIME
(µs)
ENERGY
[NJ]
OPCODE
(HEX)
Arithmetic operations
ADD
A,Rn
add register to A
1
0.498
1.831
2*
ADD
A,direct
add direct byte to A
2
0.631
2.501
25
ADD
A,@Ri
add indirect RAM to A
1
0.529
1.990
26, 27
ADD
A,#data
add immediate data to A
2
0.583
2.262
24
ADDC
A,Rn
add register to A with carry flag
1
0.508
1.864
3*
ADDC
A,direct
add direct byte to A with carry flag
2
0.637
2.525
35
ADDC
A,@Ri
add indirect RAM to A with carry flag
1
0.539
2.030
36, 37
ADDC
A,#data
add immediate data to A with carry flag
2
0.597
2.304
34
SUBB
A,Rn
subtract register from A with borrow
1
0.497
1.861
9*
SUBB
A,direct
subtract direct byte from A with borrow
2
0.630
2.527
95
SUBB
A,@Ri
subtract indirect RAM from A with borrow
1
0.528
2.021
96, 97
1998 Oct 07
68
Philips Semiconductors
Product specification
Pager baseband controller
MNEMONIC
PCA5007
DESCRIPTION
BYTES
EXEC.
TIME
(µs)
ENERGY
[NJ]
OPCODE
(HEX)
2
0.582
2.287
94
SUBB
A,#data
subtract immediate data from A with
borrow
INC
A
increment A
1
0.459
2.475
04
INC
Rn
increment register
1
0.457
1.737
0*
INC
direct
increment direct byte
2
0.586
1.982
05
INC
@Ri
increment indirect RAM
1
0.493
1.982
06, 07
DEC
A
decrement A
1
0.459
1.489
14
DEC
Rn
decrement register
1
0.457
1.74
1*
DEC
direct
decrement direct byte
2
0.590
2.488
15
DEC
@Ri
decrement indirect RAM
1
0.489
1.972
16, 17
INC
DPTR
increment data pointer
1
0.384
1.345
A3
MUL
AB
multiply A & B
1
0.378
1.242
A4
DIV
AB
divide A by B
1
0.733
2.532
84
DA
A
decimal adjust A
1
0.426
1.363
D4
Logic operations
ANL
A,Rn
AND register to A
1
0.495
1.857
5*
ANL(1)
A,direct
AND direct byte to A
2
0.623
2.494
55
ANL
A,@Ri
AND indirect RAM to A
1
0.525
2.021
56, 57
ANL
A,#data
AND immediate data to A
2
0.583
2.272
54
ANL
direct,A
AND A to direct byte
2
0.650
2.639
52
ANL
direct,#data
AND immediate data to direct byte
3
0.719
3.138
53
ORL
A,Rn
OR register to A
1
0.459
1.605
4*
ORL(1)
A,direct
OR direct byte to A
2
0.584
2.248
45
ORL
A,@Ri
OR indirect RAM to A
1
0.486
1.767
46, 47
ORL
A,#data
OR immediate data to A
2
0.539
2.015
44
ORL
direct,A
OR A to direct byte
2
0.614
2.405
42
ORL
direct,#data
OR immediate data to direct byte
3
0.679
2.886
43
XRL
A,Rn
exclusive-OR register to A
1
0.459
1.715
6*
XRL(1)
A,direct
exclusive-OR direct byte to A
2
0.584
2.361
65
XRL
A,@Ri
exclusive-OR indirect RAM to A
1
0.486
1.873
66, 67
XRL
A,#data
exclusive-OR immediate data to A
2
0.540
2.128
64
XRL
direct,A
exclusive-OR A to direct byte
2
0.614
2.550
62
XRL
direct,#data
exclusive-OR immediate data to direct
byte
3
0.679
3.017
63
CLR
A
clear A
1
0.374
1.265
E4
CPL
A
complement A
1
0.398
1.511
F4
RL
A
rotate A left
1
0.383
1.388
23
RLC
A
rotate A left through the carry flag
1
0.383
1.390
33
RR
A
rotate A right
1
0.382
1.381
03
1998 Oct 07
69
Philips Semiconductors
Product specification
Pager baseband controller
MNEMONIC
PCA5007
DESCRIPTION
BYTES
EXEC.
TIME
(µs)
ENERGY
[NJ]
OPCODE
(HEX)
RRC
A
rotate A right through the carry flag
1
0.383
1.382
13
SWAP
A
swap nibbles within A
1
0.371
1.394
C4
1
0.377
1.406
E*
Data transfer
MOV
A,Rn
move register to A
MOV
A,direct
move direct byte to A
2
0.509
2.080
E5
MOV
A,@Ri
move indirect RAM to A
1
0.408
1.568
E6, E7
MOV
A,#data
move immediate data to A
2
0.426
1.752
74
MOV
Rn A
move A to register
1
0.344
1.347
F*
MOV
Rn,direct
move direct byte to register
2
0.602
2.654
A*
MOV
Rn,#data
move immediate data to register
2
0.415
1.839
7*
MOV
direct,A
move A to direct byte
2
0.477
2.024
F5
MOV
direct,Rn
move register to direct byte
2
0.536
2.294
8*
MOV
direct,direct
move direct byte to direct byte
3
0.661
2.950
85
MOV
direct,@Ri
move indirect RAM to direct byte
2
0.564
2.438
86, 87
MOV
direct,#data
move immediate data to direct byte
3
0.679
3.017
75
MOV
@RI,A
move A to indirect RAM
1
0.378
1.517
F6, F7
MOV
@Ri,direct
move direct byte to indirect RAM
2
0.633
2.629
A6, A7
MOV
@Ri,#data
move immediate data to indirect RAM
3
0.448
2.019
76, 77
MOV
DPTR,#data 16
load data pointer with a 16-bit constant
3
0.519
2.267
90
MOVC A,@A+DPTR
move code byte relative to DPTR to A
1
0.775
3.570
93
MOVC A,@A+PC
move code byte relative to PC to A
1
0.770
3.374
83
MOVX
A,@Ri
move external RAM (8-bit address) to A
1
0.707
2.732
E2, E3
MOVX
A,@DPTR
move external RAM (16-bit address) to A
1
0.710
2.605
E0
MOVX
@Ri,A
move A to external RAM (8-bit address)
1
0.629
2.595
F2, F3
MOVX
@DPTR,A
move A to external RAM (16-bit address)
1
0.631
2.439
F0
PUSH
direct
push direct byte onto stack
2
0.600
2.543
C0
POP
direct
pop direct byte from stack
2
0.606
2.548
D0
XCH
A,Rn
exchange register with A
1
0.513
1.847
C*
XCH
A,direct
exchange direct byte with A
2
0.645
2.526
C5
XCH
A,@Ri
exchange indirect RAM with A
1
0.544
2.024
C6, C7
XCHD
A,@Ri
exchange LOW-order nibble indirect RAM
with A
1
0.486
1.904
D6, D7
Boolean variable manipulation
CLR
C
clear carry flag
1
0.293
1.075
C3
CLR
bit
clear direct bit
2
0.597
2.509
C2
SETB
C
set carry flag
1
0.293
1.084
D3
SETB
bit
set direct bit
2
0.611
2.603
D2
CPL
C
complement carry flag
1
0.320
1.134
B3
CPL
bit
complement direct bit
2
0.583
2.471
B2
1998 Oct 07
70
Philips Semiconductors
Product specification
Pager baseband controller
MNEMONIC
PCA5007
DESCRIPTION
BYTES
EXEC.
TIME
(µs)
ENERGY
[NJ]
OPCODE
(HEX)
2
0.540
2.187
82
ANL
C,bit
AND direct bit to carry flag
ANL
C,/bit
AND complement of direct bit to carry flag
2
0.563
2.388
B0
ORL(2)
C,bit
OR direct bit to carry flag
2
0.561
2.341
72
ORL
C,/bit
OR complement of direct bit to carry flag
2
0.561
2.341
A0
MOV
C,bit
move direct bit to carry flag
2
0.610
2.542
A2
MOV
bit,C
move carry flag to direct bit
2
0.610
2.542
92
Program and machine control
ACALL addr11
absolute subroutine call
2
0.840
3.384
•1 addr
LCALL addr16
long subroutine call
3
1.082
4.562
12
RET
return from subroutine
1
1.082
4.562
22
RETI
return from interrupt
1
1.082
4.562
32
AJMP
addr11
absolute jump
2
0.670
2.524
♦1 addr
LJMP
addr16
long jump
3
0.840
3.384
02
SJMP
rel
short jump (relative address)
2
0.670
2.524
80
JMP
@A+DPTR
jump indirect relative to the DPTR
1
1.049
4.015
73
JZ
rel
jump if A is zero
2
0.639
2.224
60
JNZ
rel
jump if A is not zero
2
0.754
2.896
70
JC
rel
jump if carry flag is set
2
0.620
2.128
40
JNC
rel
jump if carry flag is not set
2
0.733
2.705
50
JB
bit,rel
jump if direct bit is set
3
0.788
3.095
20
JNB
bit,rel
jump if direct bit is not set
3
0.902
3.708
30
JBC
bit,rel
jump if direct bit is set and clear bit
3
0.894
3.520
10
CJNE
A,direct,rel
compare direct to A and jump if not equal
3
0.855
3.307
B5
CJNE
A,#data,rel
compare immediate to A and jump if not
equal
3
0.794
3.024
B4
CJNE
Rn,#data,rel
compare immediate to register and jump if
not equal
3
0.787
3.139
B*
CJNE
@Ri,#data,rel
compare immediate to indirect and jump if
not equal
3
0.822
3.333
B6, B7
DJNZ
Rn,rel
decrement register and jump if not zero
2
0.857
3.474
D*
DJNZ
direct,rel
decrement direct and jump if not zero
3
0.991
4.178
D5
no operation
1
0.284
1.027
00
NOP
Notes
1. This opcode works in a slightly different way to a standard 80C51 CPU. If the direct field addresses one of the I/O
ports (P0 to P3) then the standard 80C51 uses the port pin input state for the operation while the PCA5007 uses the
SFR contents.
2. This opcode works in a slightly different way to a standard 80C51 CPU. If the direct bit field addresses one of the
port bits, then the state of the corresponding port pin is written to the port SFR after execution of the instruction.
1998 Oct 07
71
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
Table 61 Notation for data addressing modes
SYMBOL
DESCRIPTION
Rn
working registers R0 to R7
direct
128 internal RAM locations and any special function register (SFR)
@Ri
indirect internal RAM location addressed by register R0 or R1
#data
8-bit constant included in instruction
#data 16
16-bit constant included as bytes 2 and 3 of instruction
bit
direct addressed bit in internal RAM or SFR
addr16
16-bit destination address. Used by LCALL and LJMP. The branch will be anywhere within the 64-kbyte
program memory address space.
addr11
11-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2-kbyte page
of program memory as the first byte of the following instruction.
rel
Signed (two's complement) 8-bit offset byte. Used by SJMP and all conditional jumps. Range is
−128 to +127 bytes relative to first byte of the following instruction.
Table 62 Hexadecimal opcode cross reference
SYMBOL
DESCRIPTION
*
8, 9, A, B, C, D, E and F.
•
11, 31, 51, 71, 91, B1, D1 and F1.
♦
01, 21, 41, 61, 81, A1, C1 and E1.
1998 Oct 07
72
1998 Oct 07
ORL
direct,#data
ANL
direct,#data
XRL
direct,#data
JMP
@A+DPTR
MOVC
A,@A+PC
MOVC
A,@A+DPTR
ORL
direct,A
ANL
direct,A
XRL
direct,A
ORL
C,bit
ANL
C,bit
MOV
bit,C
AJMP
addr11
ACALL
addr11
AJMP
addr11
ACALL
addr11
AJMP
addr11
ACALL
addr11
JC
rel
JNC
rel
JZ
rel
JNZ
rel
SJMP
rel
MOV
DPTR,#data 16
ORL
C,/bit
ANL
C,/bit
PUSH
direct
5
6
7
8
9
A
73
B
C
D
XRL
A,direct
MOV
direct,#data
XRL
A,#data
MOV
A,#data
MGL457
0
0
MOV
direct,A
CPL
A
1
MOVX @Ri,A
ACALL
addr11
MOVX
@DPTR,A
F
0
CLR
A
MOVX A,@Ri
1
E
MOV @Ri,A
MOV A,@Ri
XCHD A,@Ri
XCH A,@Ri
CJNE @Ri,#data,rel
MOV @Ri,direct
SUBB A,@Ri
MOV direct,@Ri
MOV @Ri,#data
XRL A,@Ri
ANL A,@Ri
ORL A,@Ri
ADDC A,@Ri
ADD A,@Ri
[email protected]
[email protected]
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
B
C
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
D
3
4
MOV Rn,direct
5
SUBB A, Rn
3
4
5
3
MOV direct,Rn
3
MOV Rn,#data
3
XRL A,Rn
3
ANL A,Rn
3
ORL A,Rn
3
ADDC A,Rn
3
ADD A,Rn
3
DEC Rn
3
INC Rn
2
2
2
2
2
4
4
4
4
3
4
MOV Rn,A
3
MOV A,Rn
3
DJNZ Rn,rel
3
XCH A,Rn
3
5
5
5
5
5
CJNE Rn,#data,rel
2
2
2
2
2
2
2
2
2
2
2
A
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
E
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
F
* MOV A, ACC is not a valid instruction.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
9
Pager baseband controller
0
AJMP
addr11
MOVX
A,@DPTR
0
0
DA
A
SETB
C
SETB
bit
ACALL
addr11
POP
direct
MOV
*
A,direct
SWAP
A
CLR
C
CLR
bit
AJMP
addr11
0
0
0
0
0
0
0
0
DJNZ
direct,rel
XCH
A,direct
CJNE
A,#data,rel
CPL
C
CPL
bit
ACALL
addr11
MUL
AB
INC
DPTR
CJNE
A,direct,rel
SUBB
A,direct
ANL
A,direct
ANL
A,#data
SUBB
A,#data
ORL
A,direct
ORL
A,#data
MOV
direct,direct
ADDC
A,direct
ADDC
A,#data
DIV
AB
0
ADD
A,direct
ADD
A,#data
0
0
0
DEC
direct
INC
direct
6
DEC
A
INC
A
5
MOV
C,bit
RLC
A
4
handbook, full pagewidth
AJMP
addr11
RETI
4
ACALL
addr11
JNB
bit,rel
RL
A
3
RET
AJMP
addr11
JB
bit,rel
RRC
A
LCALL
addr16
ACALL
addr11
2
RR
A
LJMP
addr16
3
AJMP
addr11
2
JBC
bit,rel
NOP
1
second hexadecimal character of opcode
7.1
1
0
0
first hexadecimal character of opcode
Philips Semiconductors
Product specification
PCA5007
Instruction map
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
8 LIMITING VALUES
According to the Absolute Maximum Ratings System (IEC 134); note 1
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VBAT
battery supply voltage
−0.5
+2.0
V
VDD
supply voltage
−0.5
+5.0
V
VI
input voltage (all inputs)
−0.3
VDD + 0.3
V
II/O
maximum sink/source current for all input/output pins
−10
+10
mA
IBAT, IIND
maximum supply current for pins VBAT and VIND
−
100
mA
IDD
maximum supply current for any supply pin
−
50
mA
Ptot
total power dissipation
−
100
mW
VESD(HBM)
maximum ESD stress level applied to VPP pin using human
body model
−
2000
V
VESD(MM)
maximum ESD stress level applied to VPP pin using machine
model
−
200
V
Tstg
storage temperature
−55
+125
°C
Tamb
operating ambient temperature (for all devices)
−10
+55
°C
Note
1. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to
VSS unless otherwise specified.
9
EXTERNAL COMPONENTS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Discrete components
L
inductor
330
470
1000
µH
Co
output capacitor
−
4.7
10.0
µF
RFB
feedback oscillator resistance
2.0
2.2
−
MΩ
RX1
parasitic serial resistance of quartz
−
−
20
kΩ
1998 Oct 07
74
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
10 DC CHARACTERISTICS
VSS = 0 V; VDD = 2.2 V; VBAT = 1.2 V; Tamb = −10 to +55 °C; all voltages referenced to VSS unless otherwise specified.;
DC/DC converter configured as indicated in note 1.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Battery supply
VBAT
battery operating voltage
note 2
0.9
1.2
1.6
V
IBAT(reset)
static reset supply current
VBAT = 1.2 V; pin
RESETIN at VBAT; XTL1
at VSS; P1.6, P1.7; I, Q,
EA, TCLK, VPP at VSS or
VDD; all outputs and I/Os
open-circuit
−
0.5
5
µA
IDD(reset)
static reset supply current
VDD = VBAT; pin RESETIN
at VBAT; XTL1 at VSS;
P1.6, P1.7, I, Q, EA,
TCLK, VPP at VSS or VDD;
all outputs and I/Os
open-circuit
−
0.5
10
µA
RNFET
NFET pin-to-pin resistance
Tamb = 25 °C; VDD = 2.2 V −
1.1
5
Ω
RPFET
PFET pin-to-pin resistance
Tamb = 25 °C; VDD = 2.2 V −
1.2
5
Ω
IL(NFET)
NFET leakage current
−
−
1
µA
IL(PFET)
PFET leakage current
−1
−
−
µA
INFET(max)
maximum allowed NFET
current
−
−
50
mA
IPFET(max)
maximum allowed PFET
current
−
−
50
mA
VBAT − 0.1 −
VBAT
V
VDD = VBAT; all inputs at
VSS or VDD; all outputs
and I/Os open-circuit
−
6
−
µA
note 3; programmable in
4 steps
1.8
1.9
2.3
V
1.9: [VLO, VLO] = 00
−
1.9
−
V
2.0: [VLO, VLO] = 01
−
2.0
−
V
DC/DC converter in off mode
VDD
DC supply voltage output
IBAT(off)
current consumed from
VBAT by the DC/DC
converter itself
DC/DC converter in standby mode
VDD
DC supply voltage
generated by the on-chip
DC/DC converter for the
PCA5007 and external
chips
2.1: [VLO, VLO] = 10
−
2.1
−
V
2.2: [VLO, VLO] = 11
−
2.2
−
V
−
100
mV
VDROP
DC voltage drop due to load IL = 500 µA; notes 3 and 4 −
Vripple(p-p)
ripple voltage (peak-to-peak notes 4 and 5
value)
−
50
−
mV
IBAT(stb)
current consumed from
VBAT by the DC/DC
converter itself
Tamb = 25 °C;
notes 6 and 7
−
25
−
µA
1998 Oct 07
75
Philips Semiconductors
Product specification
Pager baseband controller
SYMBOL
PARAMETER
PCA5007
CONDITIONS
MIN.
TYP.
MAX.
UNIT
IDD(max)(stb)
maximum delivered
continuous supply current
VBAT = 0.9 V; RS = 8 Ω;
notes 7 and 9; see Fig.31
1
−
−
mA
η(stb)
efficiency of DC/DC
converter in standby mode
VBAT = 1.2 V;
IDD = 100 µA; note 7
−
80
−
%
DC/DC converter in high current mode (non standby)
VDD
DC supply voltage
generated by the on-chip
DC/DC converter for the
PCA5007 and external
chips
note 3
2.2 − 6%
2.2
2.2 + 6%
V
VDD(av)
mean DC voltage
notes 3 and 4
2.1
2.2
2.3
V
notes 4 and 7
−
−
100
mV
−
−
100
mV
VHFripple(p-p) ripple voltage for
frequencies above 20 kHz
(peak-to-peak value)
VLFripple(p-p)
low frequency ripple voltage notes 4, 7 and 13
caused by load variations
(peak-to-peak value)
IBAT
current consumed from
VBAT by the DC/DC
converter itself
Tamb = 25 °C;
notes 7 and 8; see Fig.44
−
110
−
µA
IDD(max)
maximum delivered
continuous supply current
VBAT = 0.9 V; RS = 8 Ω;
notes 7 and 9; see Fig.30
10
−
−
mA
η(norm)
efficiency of DC/DC
converter
note 7
VBAT ≥ 1.2 V;
IDD = 3 mA
−
90
−
%
VBAT ≥ 1.2 V;
IDD = 10 mA
−
85
−
%
VBAT = 0.9 V;
IDD = 3 mA
−
85
−
%
VBAT = 0.9 V;
IDD = 10 mA
−
75
−
%
2.2
2.2
2.5
V
External supply current from VDD = 2.2 V, VBAT = 1.2 V
VDD
DC supply voltage (VDD and see Fig.57; note 10
VDDA pins)
IBAT
operating current
Tamb = 25 °C; 76.8 kHz
quartz
−
2
−
µA
IDD(stb)
operating standby mode
supply current from VDD
Tamb = 25 °C; note 6
−
12
−
µA
IDD(RX)
operating receive mode
supply current from VDD
Tamb = 25 °C; note 8
−
85
−
µA
1998 Oct 07
76
Philips Semiconductors
Product specification
Pager baseband controller
SYMBOL
PARAMETER
PCA5007
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply current from internal or external VDD = 2.2 V
IDD(micro)
supply current due to
Tamb = 25 °C; note 11
operation of microcontroller
−
0.7
−
mA/MIPS
IDD(UART)
increase in IDD due to
operation of the UART
Tamb = 25 °C
−
5
−
µA
IDD(IIC)
increase in IDD due to
operation of the I2C-bus
master
Tamb = 25 °C
−
20
−
µA
IDD(T0)
increase in IDD due to
Tamb = 25 °C
operation of timer/counter 0
−
0
−
µA
IDD(T1)
increase in IDD due to
Tamb = 25 °C
operation of timer/counter 1
−
2
−
µA
IDD(AFC)
supply current due to
operation of AFC-DAC
Tamb = 25 °C
−
60
−
µA
IDD(SBL)
supply current due to
Tamb = 25 °C
battery measurement active
(SBLI = 1)
−
20
−
µA
IDD(6MHz)
increase in IDD due to
activation of 6 MHz
oscillator in standby mode
−
50
−
µA
Tamb = 25 °C; frequency
adjusted to 6 MHz
OTP programming (OTP data retention can only be guaranteed if the devices are preprogrammed by Philips
Semiconductors; data retention cannot be guaranteed for customer programmed samples)
VDD(prog)
supply voltage during
programming
VPP
program supply voltage
IPP
program supply current
Tamb(prog)
operating ambient
temperature during
programming
note 10
note 12
2.2
−
3.6
V
12.5
−
13
V
−
24
−
mA
21
−
27
°C
1.23
1.26
1.29
V
Band gap (reference voltage for all comparators)
VBG
band gap voltage
[VBG1, VBG0] = 00
[VBG1, VBG0] = 01
−
1.233
−
V
[VBG1, VBG0] = 10
−
1.286
−
V
[VBG1, VBG0] = 11
−
1.312
−
V
Tamb = 25 °C
1.5
1.85
2.0
V
[VBG1, VBG0] = 00
1.05
1.1
1.15
V
Initial VDD OK detection
VDD(OK)
VDD OK indication
Battery low indicator
VBLI
1998 Oct 07
battery low indication
77
Philips Semiconductors
Product specification
Pager baseband controller
SYMBOL
PCA5007
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Digital input; pins I(D1), Q(D0) and TCLK
VIL
LOW-level input voltage
−
−
0.2VDD
V
VIH
HIGH-level input voltage
0.8VDD
−
−
V
IL
leakage current
−0.1
−
+0.1
µA
VI = VDD or VSS
Digital input; pin RESETIN
VIL
LOW-level input voltage
−
−
0.2VBAT
V
VIH
HIGH-level input voltage
0.8VBAT
−
−
V
IL
leakage current
VI = VDD or VSS
−0.1
−
+0.1
µA
−
−
0.2VDD
V
Digital input/output pin EA
VIL
LOW-level input voltage
output not sinking current
VIH
HIGH-level input voltage
output not sinking current
0.8VDD
−
−
V
Io(sink)
output sink current
VDD = 2.2 V; VI = 0.4 V
0.75
−
−
mA
Io(source)
output source current
VDD = 2.2 V;
VI = VDD − 0.4 V
−
−
−0.75
mA
INMOS(h)
NMOS hold current
VDD = 2.2 V; VI = 0.6 V
−
−
200
µA
IPMOS(h)
PMOS hold current
VDD = 2.2 V;
VI = VDD − 0.6 V
−200
−
−
µA
Digital output; pin RESOUT
Io(sink)
output sink current
VDD = 2.2 V; VI = 0.4 V
1.5
−
−
mA
Io(source)
output source current
VDD = 2.2 V;
VI = VDD − 0.4 V
−
−
−1.5
mA
Digital input/output; pin PSEN
VIL
LOW-level input voltage
output not sinking current
−
−
0.2VDD
V
VIH
HIGH-level input voltage
output not sinking current
0.8VDD
−
−
V
Io(sink)
output sink current
VDD = 2.2 V; VI = 0.4 V
0.75
−
−
mA
Io(source)
output source current
VDD = 2.2 V;
VI = VDD − 0.4 V
−
−
−0.75
mA
Ipu
weak pull-up current
VDD = 2.2 V; VI = 0 V
−20
−7
−2
µA
Digital input/output; pin ALE
VIL
LOW-level input voltage
output not sinking current
−
−
0.2VDD
V
VIH
HIGH-level input voltage
output not sinking current
0.8VDD
−
−
V
Io(sink)
output sink current
VDD = 2.2 V; VI = 0.4 V
1.5
−
−
mA
Io(source)
output source current
VDD = 2.2 V;
VI = VDD − 0.4 V
−
−
−1.5
mA
Ipu
weak pull-up current
VDD = 2.2 V; VI = 0 V
−20
−7
−2
µA
1998 Oct 07
78
Philips Semiconductors
Product specification
Pager baseband controller
SYMBOL
PCA5007
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Microcontroller input/output; ports P0, P1 and P2 pins (except P1.6 and P1.7)
VIL
LOW-level input voltage
output not sinking current
−
−
0.2VDD
V
VIH
HIGH-level input voltage
output not sinking current
0.8VDD
−
−
V
Io(sink)
output sink current
VDD = 2.2 V; VI = 0.4 V
0.75
−
−
mA
Io(source)
output source current
VDD = 2.2 V;
VI = VDD − 0.4 V
−
−
−0.75
mA
Ipu
weak pull-up current
VDD = 2.2 V; VI = 0 V
−20
−7
−2
µA
IPMOS(h)
PMOS hold current
VDD = 2.2 V; VI = 0.5VDD
−200
−70
−20
µA
Microcontroller output port P3
Io(sink)
output sink current
VDD = 2.2 V; VI = 0.6 V
4
−
−
mA
Io(source)
output source current
VDD = 2.2 V;
VI = VDD − 0.6 V
−
−
−6
mA
Open-drain pins SDA and SCL (P1.6 and P1.7)
VIL
LOW-level input voltage
output not sinking current
−
−
0.2VDD
V
VIH
HIGH-level input voltage
output not sinking current
0.8VDD
−
−
V
IL
leakage current
VI = VDD
−1
−
+1
µA
Isink(stat)
static output sink current
VDD = 2.2 V; VI = 0.4 V
2.25
−
−
mA
Isink(stat)(sc)
static output sink
short-circuit current
VDD = 2.2 V; VI = VDD
2.2
6
14
mA
AT output pin
Io(sink)
output sink current
VDD = 2.2 V; VI = 0.4 V
3
−
−
mA
Io(source)
output source current
VDD = 2.2 V;
VI = VDD − 0.4 V
−
−
−3
mA
76.8 kHz oscillator
VIL(XTAL1)
LOW-level input voltage at
pin XTL1
−
−
0.3
V
VIH(XTAL1)
HIGH-level input voltage at
pin XTL1
1
−
−
V
−1
−
+1
µA
0.8
1.1
µA
2
−
µA
ILI(XTL1)
leakage current at pin XTL1 VI = VBAT or VSS
Ibias
bias current from XTL2 to
VSS
VBAT = 1.6 V; XTL1 at VSS 0.5
Iop
operating current
consumption
VBAT = 1.6 V;
Rfb = 2.2 MΩ
gm
transconductance
Io = ±0.3 µA
5
20
60
µA/V
VWP
DC working point
−
550
−
mV
VAFC
resolution
−
1⁄
−
V
∆AFC
deviation for codes
between 010000 and
100000 from straight line
−0.25LSB
−
−
AFC-DAC
1998 Oct 07
79
64VDD
+0.25LSB
Philips Semiconductors
Product specification
Pager baseband controller
SYMBOL
PARAMETER
PCA5007
CONDITIONS
MIN.
TYP.
MAX.
UNIT
RL(DAC)
allowed resistive load at
DAC output
10
−
−
kΩ
CL(DAC)
allowed capacitive load at
DAC output
−
−
50
pF
Isource
AFCOUT source current
VDD = 2.2 V;
VAFCOUT = VDD − 0.4 V;
code = 111111
−
−895
−100
µA
Isink
AFCOUT sink current
VDD = 2.2 V;
VAFCOUT = 0.4 V;
code = 000000
10
25
−
µA
Notes
1. DC/DC converter configured with inductor of L = 470 µH, SRL = 5 Ω, input capacitance of Ci = 4.7 µF, ESR = 0.5 Ω,
VDD output capacitor Co = 4.7 µF, ESR = 0.5 Ω, RBAT < 1 Ω.
2. The required VBAT for starting the circuit after connecting it to the battery is 1.1 V. But once in place, the battery can
be used until it is discharged to 0.9 V.
3. This parameter is not tested during production; it is covered by other measurements.
4. The accuracy of the voltage is defined by maximum offset and ripple voltage. DC offset is defined by the accuracy
of the internal band gap reference and the offset of comparators, whereas the ripple voltage is defined by the limits
of the allowed voltage window of the regulated VDD.
5. The ripple in standby mode is defined by VBAT, L, tn and ESR (see Table 54).
6. PCA5007 set to standby mode by software: 76.8 kHz oscillator running, DC/DC converter running in standby mode,
all timers/counters disabled except RTC, microcontroller Idle, all outputs open-circuit, no supply current delivered to
external circuits.
7. This parameter depends on external components and is not tested during production; hence no guarantee.
8. PCA5007 set to receive mode by software: 76.8 kHz and 6 MHz oscillator running, DC/DC converter running in
normal mode, wake-up counter, clock compensation, watchdog timer, T0 and T1 enabled, demodulator set to direct
input data, AFC disabled, microcontroller Idle, all outputs open-circuit, no supply current delivered to external circuits.
9. Rs = total series resistance = RBAT + SRL + RDS(on) + ESR.
10. The minimum supply voltage is determined by the start-up sequence of the device. When the start-up sequence is
completed, the supply voltage can be lowered to 1.8 V.
11. The microcontroller operates with approximately1.9 million instructions per second at VDD = 2.2 V. The current
consumption at this supply voltage is 0.7 mA/MIPS (peripheral blocks as e.g. timers, DC/DC converter, I2C-bus,
UART, demodulator etc., are excluded). The current required from VDD is then 1.35 mA (typ.). This scales to
V DD
I BAT = ------------ × I DD = 2.5 mA sunk from VBAT.
V BAT
12. In mass program mode the current can increase to 100 mA.
13. This parameter is not tested during production; it is guaranteed by design.
1998 Oct 07
80
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
11 AC CHARACTERISTICS
VBAT = 0.9 to 1.6 V; VSS = 0 V; Tamb = −10 to +55 °C; all voltages referenced to VSS unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP
MAX.
UNIT
DC/DC converter; note 1
ton
turn on time
off to normal operation;
IL < 500 µA; note 2
−
−
5
ms
tch(mode)
mode change time
enable to standby and
reverse; note 2
−
−
1
ms
tstep
load step accommodation
delay until stable
load step from 10 µA to 6 mA;
note 3
−
−
1
ms
fsw
switching frequency
in normal mode; note 2
120
250
400
kHz
in standby mode
−
fXTL1
−
kHz
−
1⁄ t
2 XTL1
tXTL1
µs
20
−
−
µs
tch(L)
inductor charge time
in standby mode; note 4
RESET signal
tRESETIN(min) minimum duration of
RESETIN pulse
Microcontroller
tinstr(int)
internal instruction
execution time
internal access; VDD = 2.2 V;
Tamb = 25 °C; note 5
−
550
−
ns
tinstr(ext)
external instruction
execution time
external access; VDD = 2.2 V;
Tamb = 25 °C; note 5
−
650
−
ns
note 3
76784
76800
76816
Hz
76.8 kHz oscillator
fxtal
crystal frequency
fi(max)
max input frequency through
input buffer
−
−
100
kHz
C1
input capacitance
−
10 ±15%
−
pF
C2
output capacitance
−
10 ±15%
−
pF
(SF4, SF3, SF2, SF1,
SF0) = 00000
(reset condition)
3
5.4
8
MHz
(SF4, SF3, SF2, SF1,
SF0) = 10000
1
2.7
5
MHz
(SF4, SF3, SF2, SF1,
SF0) = 01111
6
7.6
11
MHz
5.85
6
6.15
MHz
note 2
−
20
30
µs
6 MHz oscillator
fi(osc)
oscillator input frequency
fi(osc) ± ∆f
adjusted frequency
td(en)
enable oscillator delay
1998 Oct 07
81
Philips Semiconductors
Product specification
Pager baseband controller
SYMBOL
PCA5007
PARAMETER
CONDITIONS
MIN.
TYP
MAX.
UNIT
ZIF (I and Q) demodulator
foffset
offset from 0 frequency
note 2
6
−
−
kHz
S/N
minimum signal strength
3% bit error rate; note 2
−
−
−95
dB(m)
t(ENA-AVG)
ENA to valid AVG value
3 kHz offset; note 2
−
−
100
ms
tENB
ENB to valid demodulator
output
24 samples per symbol;
note 2
−
−
1
symbol
duration
tENC
ENB to correct recovered
clock
note 2
12/12 positive/negative
transitions of data
tBR
changing baud rate to
correct recovered clock
note 2
2/2 positive/negative
transitions of data
All outputs
tr,f
rise and fall times for outputs CL = 20 pF
−
15
−
ns
Open-drain pins SDA and SCL (P1.7 and P1.6)
tnoise
noise suppression filter time
−
60
−
ns
∆V/∆t
slope for the falling edge
RL = 20 kΩ; CL = 50 pF;
VDD = 2.2 V
−
50
−
ns/V
δI/δt
slope for both edges
RL = 20 kΩ; CL = 50 pF
−
250
−
µA/ns
Io(sink)(swL)
dynamic output sink current
during switching low (Miller
compensated)
VDD = 2.2 V; RL = 20 kΩ;
CL = 50 pF
−
2
−
mA
OTP programming characteristics
tSU;VPP
VPP set-up time
10
−
−
µs
tW(prog)
program pulse width
100
−
−
µs
tW(prog)(sec)
program pulse security bits
200
−
−
µs
tW(prog)(rec)
program pulse recover time
1
−
−
µs
−
50
100
µs
−
0
−
dB
−
2.5
−
µs
AFC-DAC
tstart(DAC)
start-up time disabled DAC
to stable output for code
111111
PSRR
power supply ripple rejection
(VDD -> DAC)
tslew
slew time for analog output
from 10 to 90% for a voltage
step of 1 V
note 2
code 010000 <-> 110000
Notes
1. DC/DC converter configured with inductor of L = 470 µH, SRL = 5 Ω, input capacitance of Ci = 4.7 µF, ESR = 0.5 Ω,
VDD output capacitor Co = 4.7 µF, ESR = 0.5 Ω, RBAT < 1 Ω.
2. This parameter is not tested during production; it is guaranteed by design.
3. This parameter depends on external components.
4. At high load or low battery voltage the inductor charge time can be extended to a full XTL1 period, while the minimum
inductor discharge time remains an 1⁄2tXTL1 period.
5. The execution time is strongly dependant on command type and addressing mode (see Table 60).
1998 Oct 07
82
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
ALE, PSEN cycle
dth
3T
4T
5T
6T
0T
1T
2T
3T
4T
5T
....
6T
nT
ALE
tCE
PSEN
variable
execute time
P0
DATA input
P2
AH driven
sample P0
sample P0
instruction execution cycle
T
AL
driven
DATA input
T being the half period of the
internal 6 MHz oscillator for
normal external access and of
TCLK for emulation, programming
and test modes.
The minimum duration of one
cycle is 6T. It can be extended by
increments of [0 to n]T if the
execution of an instruction needs
more time (dependant of VDD, T,
temperature and opcode).
Execution of an opcode goes in
parallel with the external access
cycle for the next sequential byte.
Eventually an already fetched
byte is discarded depending on
the executed instruction (e.g. any
jump or return).
AH driven
MGR161
Fig.39 External access timing.
12 CHARACTERISTIC CURVES
MGR144
3
handbook, full pagewidth
IBAT
(mA)
2
(1)
(2)
1
0
0
0.4
0.8
1.2
1.6
MIPS
VBAT = 1.2 V.
(1) DC/DC converter in normal mode.
(2) DC/DC converter in standby mode.
Fig.40 Measured battery current consumption as function of mean microcontroller instruction rate.
1998 Oct 07
83
2
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
MGR145
10
handbook, full pagewidth
IBAT
(mA)
(1)
1
(2)
10−1
10−2
(3)
10−3
0
0.4
0.8
1.2
1.6
MIPS
VBAT = 1.2 V.
(1) DC/DC converter in normal mode.
(2) DC/DC converter in standby mode.
(3) DC/DC converter in off mode.
Fig.41 Measured battery current consumption as function of mean microcontroller instruction rate.
MGR146
10
handbook, halfpage
IBAT
(µA)
8
6
4
2
0
0.8
1
1.2
1.4
1.6
VBAT (V)
VDD = VBAT, microcontroller idle, all functions disabled.
Fig.42 Supply current in off mode.
1998 Oct 07
84
2
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
MGR147
50
handbook, halfpage
IBAT
(µA)
40
30
20
10
0
0.8
1
1.2
1.4
1.6
VBAT (V)
VDD = 1.9 V, microcontroller idle, all functions disabled.
Fig.43 Supply current in standby mode.
MGR148
200
handbook, halfpage
IBAT
(µA)
160
120
80
40
0
0.8
1
1.2
1.4
1.6
VBAT (V)
VDD = 2.2 V, microcontroller idle, all functions disabled.
This curve cannot be directly measured by varying VBAT because the shown current is the battery current in discontinuous mode. Changing the battery
voltage can force the DC/DC converter to enter the continuous mode. At a given battery voltage a mode change from continuous to discontinuous mode
happens only after a load reduction.
Fig.44 Supply current in normal mode.
1998 Oct 07
85
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
MGR149
3
handbook, halfpage
IBAT
(mA)
2
1
0
0.8
1
1.2
1.4
1.6
VBAT (V)
VDD = 1.9 V, microcontroller running at approximately 1.6 MIPS, all other functions disabled.
Fig.45 Supply current in standby mode.
MGR150
3
handbook, halfpage
MIPS
2
1
0
0.8
1
1.2
1.4
1.6
VBAT (V)
VDD = 1.9 V, microcontroller running at maximum speed.
Fig.46 CPU speed performance with DC/DC converter in standby mode.
1998 Oct 07
86
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
MGR349
1000
handbook, halfpage
MIPS/W
800
600
400
200
0
0.8
1
1.2
1.4
1.6
VBAT (V)
VDD = 1.9 V, microcontroller running at maximum speed.
Fig.47 Overall power/speed performance with DC/DC converter in standby mode.
MGR152
4
handbook, halfpage
IBAT
(mA)
3
2
1
0
0.8
1
1.2
1.4
1.6
VBAT (V)
VDD = 2.2 V, microcontroller running at approximately 2 MIPS, all other functions disabled.
Fig.48 Supply current in normal mode.
1998 Oct 07
87
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
MGR153
3
handbook, halfpage
MIPS
2
1
0
0.8
1
1.2
1.4
1.6
VBAT (V)
VDD = 2.2 V, microcontroller running at maximum speed.
Fig.49 CPU speed performance with DC/DC converter in normal mode.
MGR154
800
handbook, halfpage
MIPS/W
600
400
200
0
0.8
1
1.2
1.4
1.6
VBAT (V)
VDD = 2.2 V, microcontroller running at maximum speed.
Fig.50 Overall power/speed performance with DC/DC converter in normal mode.
1998 Oct 07
88
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
MGR155
4
handbook, halfpage
MIPS
3
2
1
0
1.8
2.2
2.6
3
3.4
3.8
VDD (V)
Fig.51 Speed performance PCA5007 when VDD is externally supplied (DC/DC converter not used).
MGR156
0
Ii
(µA)
handbook, halfpage
pull-up
current
−20
−40
−60
−80
hold current
−100
0
0.4
0.8
1.2
1.6
2
2.4
Vi (V)
Fig.52 Typical impedance characteristic of standard port in input mode.
1998 Oct 07
89
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
MGR157
200
handbook, halfpage
Ii
(µA)
100
0
−100
−200
0
0.4
0.8
1.2
1.6
2
2.4
Vi (V)
Fig.53 Typical impedance characteristic of EAN pin in input mode.
MGR158
0
OH
(mA)
−4
handbook,
halfpage
I
(1)
−8
(2)
−12
−16
−20
−24
(3)
0
0.4
0.8
1.2
1.6
2
2.4
VOH (V)
(1) Pins P0.X, P1.X, P2.X, PSEN and EAN.
(2) Pins RESOUTN and ALE.
(3) Pins P3.X and AT.
Fig.54 Typical output characteristics driven HIGH (digital output/port pins except P1.6 and P1.7).
1998 Oct 07
90
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
MGR159
24
OL
(mA)
20
handbook,
halfpage
I
16
(1)
12
(2)
8
(3)
4
0
0
0.4
0.8
1.2
1.6
2
2.4
VOL (V)
(1) Pins P3.X and AT.
(2) Pins RESOUTN and ALE.
(3) Pins P0.X, P1.X, P2.X, PSEN and EAN.
Fig.55 Typical output characteristics LOW (digital output/port pins except P1.6 and P1.7).
MGR160
24
handbook,
I halfpage
o
(mA)
20
16
12
8
4
0
0
0.4
0.8
1.2
1.6
2
2.4
Vo (V)
Fig.56 Typical output characteristics LOW for P1.6 and P1.7.
1998 Oct 07
91
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
13 TEST AND APPLICATION INFORMATION
IBAT
handbook, full pagewidth
VDD
10 µF
76.8 kHz
VBAT
48
P0.0
38
37
1
36
2
35
3
34
4
33
5
32
6
31
PCA5007H
7
30
8
29
9
28
10
27
11
26
12
25
P0.1
13
14
15
16
4.7 µF
P1.6
P1.7
XTL2
XTL1
VBAT
VDD(DC)
VIND
VSS(DC)
RESETIN
RESOUT
4.7
kΩ
17
18
19
20
21
22
23
VPP
TCLK
EA
PSEN
ALE
VDD
VSS
P1.4
P1.3
P1.2
P1.1
P1.0
24
P0.7
P2.7
39
P0.6
P2.6
40
P0.5
P2.5
41
VSSA
P2.4
42
Q(D0)
P2.3
43
I(D1)
P2.2
44
AFCOUT
P2.1
4.7
kΩ
2
MΩ
VDDA
P2.0
45
P0.4
AT
46
P0.3
P3.5
47
P0.2
P3.4
P3.2
P3.3
10 kΩ
IDD
VDD
MGR142
Fig.57 Test circuit for current measurements with external VDD supply.
1998 Oct 07
92
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
VDD
handbook, full pagewidth
10 µF
76.8 kHz
VBAT
48
P0.0
39
38
37
1
36
2
35
3
34
4
33
5
32
6
31
PCA5007H
7
30
8
29
9
28
10
27
11
26
12
25
P0.1
13
14
15
16
4.7 µF
P1.6
P1.7
XTL2
XTL1
VBAT
VDD(DC)
VIND
VSS(DC)
RESETIN
RESOUT
4.7
kΩ
17
18
19
20
21
22
23
VPP
TCLK
EA
PSEN
ALE
VDD
VSS
P1.4
P1.3
P1.2
P1.1
P1.0
24
P0.7
P2.7
40
P0.6
P2.6
41
P0.5
P2.5
42
VSSA
P2.4
43
Q(D0)
P2.3
4.7
kΩ
I(D1)
P2.2
44
AFCOUT
P2.1
470
µH
2
MΩ
VDDA
P2.0
45
P0.4
AT
46
P0.3
P3.5
47
P0.2
P3.4
P3.2
P3.3
10
kΩ
MGR143
Fig.58 Test circuit for current measurements with on-chip DC/DC converter.
1998 Oct 07
93
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
14 APPENDIX 1: SPECIAL MODES OF THE PCA5007
14.3
14.1
The test modes of the PCA5007 are used during the
production test of the circuit. Test modes are not intended
to be used by customers except test mode 2, the
demodulator and clock recovery test mode.
Overview
During the rising edge of the external RESOUT signal, the
state of pins ALE, PSEN and EA and P2.X is sampled and
stored. The following decoding (ALE, PSEN and P2) is
used to force the PCA5007 into different operating modes:
Test mode 2 may be used by customers for Bit Error Rate
(BER) measurements in closed-loop systems.
The following application diagram (see Fig.59) shows an
application, which enters this mode during start-up. After
the test mode is entered the PCA5007 starts execution of
code from the internal program memory. This code must
enable the demodulator and clock recovery in the required
modes. If the microcontroller is requested to make
port I/O, then a frequency of approximately 6 MHz with
VDD level needs to be supplied at the TCLK pin.
[1, 1, X] → RUN mode
[0, 1, X] → EMUlation modes (for P2 decoding refer to
Metalink documents)
[1, 0, Y] → test mode, submode Y
[0, 0, X] ≥ OTP parallel programming mode.
The customer will usually only see the normal RUN mode.
14.2
OTP parallel programming mode
The OTP parallel programming mode is used to access the
on-chip OTP directly from the device pins for programming
and verification. The OTP parallel programming mode and
its initialization are explained in detail in Chapter 15.
1998 Oct 07
Test modes
94
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
10 µF
76.8 kHz
VBAT
4.7
kΩ
48
P2.7
P0.0
VDD(DC)
XTL2
XTL1
VBAT
VIND
VSS(DC)
RESETIN
RESOUT
P1.7
38
37
1
36
2
35
3
34
4
33
5
32
6
31
PCA5007H
7
30
8
29
9
28
10
27
11
26
12
25
P0.1
13
14
15
16
17
18
19
20
21
22
23
VPP
TCLK
EA
PSEN
2.2 kΩ
ALE
VDD
VSS
P1.4
P1.3
P1.2
P1.1
P1.0
24
P0.7
P2.6
39
P0.6
P2.5
40
P0.5
P2.4
41
VSSA
P2.3
42
recovered D1
recovered D0
Q(D0)
2.2 kΩ
P2.2
43
I(D1)
2.2 kΩ
44
AFCOUT
P2.1
4.7
kΩ
2
MΩ
VDDA
P2.0
45
P0.4
2.2 kΩ
AT
46
P0.3
P3.5
recovered
symbol
clock
47
P0.2
P3.4
P3.2
P3.3
10 kΩ
P1.6
handbook, full pagewidth
2.2 V
I and Q supplied from receiver
MGR162
The OTP must contain code that enables the demodulator and clock recovery in the desired operating modes.
Fig.59 Application diagram for entering the demodulator test mode after reset.
1998 Oct 07
95
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
15 APPENDIX 2: THE PARALLEL PROGRAMMING
MODE
15.1
15.2
The PCA5007 is packaged in a LQFP48 package. Port 0
and Port 2 are available for programming. To program the
OTP of the PCA5007, multiplexing of addresses and data
is necessary. Port 0 is a bidirectional data port, used for
the memory addresses and the program and verify data.
Port 2 is an input port which controls the parallel
programming mode. A coarse block diagram of the OTP
interface in parallel programming mode is given in Fig.60.
Introduction
This section describes the parallel programming mode of
the PCA5007. Parallel programming mode is the mode
where the OTP is programmed by an EPROM
programmer or by a tester.
handbook, full pagewidth
(80C51)
General description
OTPIF
(OTP)
ADD
DO
ADDR
DI
normal
mode
OTP INTERFACE
DO
CTRL
CONTROL
parallel programming mode
TEST
CONTROL
ADDL
LATCH
ADDH
LATCH
CONTROL
LOGIC
P2
P0
MGR163
Fig.60 The OTP interface in parallel programming mode.
1998 Oct 07
96
Philips Semiconductors
Product specification
Pager baseband controller
15.2.1
PCA5007
SIGNALS FOR THE PARALLEL PROGRAMMING MODE
In this configuration, the following signals are necessary to program the OTP:
Table 63 Pins for programming mode
OTP PIN
EPROM
PIN
TYPE
DESCRIPTION
COMMENTS
VPP
supply
VPP
programming voltage special pin/logic signal not time critical
VDD
supply
VDD
positive supply
GND
supply
GND
negative supply
P0.7 to P0.0
I/O
A<14:0>
address
Q<7:0>
data output
I<7:0>
data input
PS<2:0>
security bits input
20 kbyte addresses available
QS<2:0>
security bits output
P2.0/LS0
input
−
latch select 0
P2.1/LS1
input
−
latch select 1
programming mode
connected to P0.2 to P0.0 pins
latch select signals, see Table 64
P2.2/PGM
input
−
P2.3/RdStrb
input
CEP/MBPC read/strobe
read enable Clock (CEP) when PGM = 0;
strobe for the latches when PGM = 1
P2.4/GBMbpB
input
GB
output enable not/
Mult.BProg Not
read EPROM and set P0 as output; multiple byte
programming when PGM = 1
P2.5/WEB
input
WEB
Write Enable not
programs data if VPP is present
P2.6/SEC
input
SEC
select security bits
see Section 15.10
P2.7/SIG
input
SIG
read signature bytes
see Section 15.9
The control signals GBMbpB, PGM, LS1 and LS0 can be used to select the latches of the interface block and the internal
data latches of the OTP. Table 64 shows how the latches are selected.
RdStrb is used to open the selected latch. If PGM is not active the RdSTrb signal is used to start the OTP read cycle.
Table 64 Latch selection
P2.4/GBMbpB
P2.2/PGM
P2.1/LS1
P2.1/LS0
X
0
X
X
no latches selected
1
1
0
0
select test control latch
X
1
0
1
select lower address latch
X
1
1
0
select upper address latch
0
1
1
1
select internal data latch in multi byte programming
mode
1998 Oct 07
97
DESCRIPTION
Philips Semiconductors
Product specification
Pager baseband controller
handbook, full pagewidth
PCA5007
PROGRAMMER
PCA5007
ADDL/ADDH/DATA I/O
P0.0 to P0.7
LS0
P2.0
LS1
P2.1
PGM
P2.2
RdStrb
P2.3
GBMbpB
P2.4
WEB
P2.5
SIG
P2.6
SEC
P2.7
MIN
PSEN
MOUT2
ALE
MOUT1
EA
RESETN
VDD
VSS
RESETIN
VDD, VDDA, VDD(DC), VBAT
VSS, VSSA, VSS(DC)
VPP
VPP
CLOCK
TCLK, XTL1
MGR164
Fig.61 Parallel programming mode.
15.3
The test mode is activated by making EA equal to logic 1.
The mode entering sequence is given in Table 65.
Entering the parallel programming mode
The parallel programming mode has been implemented as
a general test mode of the PCA5007. This mode can be
entered by applying 000 to pins PSEN, ALE and EA during
reset. For the initializing sequence a clock of 76.8 kHz at
XTL1 is expected and the supply voltage VDD must be
higher then 2.2 V. At the rising edge of RESOUT these
signals are latched and the code 000 leads to parallel
programming mode. The high voltage pin VPP can be
either HIGH or VDD.
Before entering the parallel program mode Port 2 can be
an output port (dependent on the reset configuration of this
port). As soon as the parallel programmed mode is entered
Port 2 is an input.
After entering the parallel programming mode this mode
has to be initialized. The OTP test latch has to be loaded
with code 01H to set the sense amplifiers in verify mode.
Before a byte can be programmed a verify has to be
performed to ensure that the programming is not blocked
by the security (see Section 15.10). The address of this
verify cycle is not important and the address latches do not
have to be loaded. After this initialization the PCA5007 is
ready for programming. Parallel program mode
initialization is shown in Fig.64.
Since PSEN and ALE are output signals of the PCA5007
after reset, a pull-down (strong enough to overdrive the
internal 100 µA pull-up of the PCA5007) should be used to
drive the outputs LOW. Alternatively the LOW can be
driven with a 3-state buffer which is enabled with
RESOUT = LOW.
The security check can be replaced by another read action
e.g. reading the security or signature bytes
(see Section 15.9).
The microcontroller fetches instructions from Port 0 in
external mode. Data fetching is controlled by PSEN and
ALE. This is the standard data fetch in external mode.
A clock has to be supplied to TCLK while entering the
parallel programming mode. Before entering the parallel
programming mode, Port 2 should be set to 30H and the
microcontroller should be put in Idle mode by setting the bit
PCON.0 (address 87H).
1998 Oct 07
It should be noted that this paragraph is only
applicable for the first series. It can be neglected in the
future. To prevent problems with the self timed loop it is
advised to set the circuit in DC read mode during verify.
This is achieved by writing 09H instead of 01H into the
OTP test latch.
98
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
Table 65 Entering the parallel programming mode; note 1
PINS PSEN, ALE AND
EA
RESETIN
RESOUT
PORT 0
000
1
0
XX
reset
000
0
0
XX
259 or more slow clocks at XTL1
000
0
0→1
XX
prepare parallel programming mode, enter
external access mode, now clocks must be
provided on TCLK
ZZ0
0
1
02
LJMP 3000H
ZZ0
0
1
30
force P2 to 30H
ZZ0
0
1
00
ZZ0
0
1
00
discard fetch cycle
ZZ0
0
1
75
MOV PCON, 01H
ZZ0
0
1
87
make microcontroller idle
ZZ0
0
1
01
ZZ0
0
1
01
discard fetch cycle
ZZ1
0
1
XX
parallel programming mode active
DESCRIPTION
Note
1. Z = pin is output.
ALE, PSEN cycle
width
3T
4T
5T
6T
0T
1T
2T
3T
4T
5T
6T
....
nT
ALE
tCE
PSEN
variable
execute time
P0
DATA input
P2
AH driven
sample P0
sample P0
instruction execution cycle
T
AL
driven
DATA input
AH driven
MGR165
Fig.62 External access timing for programming mode entry.
1998 Oct 07
99
T is the half period of the clock
signal supplied to TCLK.
The minimum duration of one
cycle is 6T. It can be extended by
increments of [0 to n]T if the
execution of an instruction needs
more time (dependant of VDD, T,
temperature, opcode).
Execution of an opcode goes in
parallel with the external access
cycle for the next sequential byte.
Eventually an already fetched
byte is discarded depending on
the executed instruction (e.g. any
jump or return).
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
dummy fetch cycles, will be discarded
handbook, full pagewidth
00
P2
P0
00
02
30
00
00
00
XX
30
75
30
87
30
01
30
30
XX
ALE
PSEN
EA
RESOUT
ALE, PSEN latched
RESETIN
minimum 259 clocks
on XTL1
(f < 100 kHz)
clocking on TCLK(1)
(f = 500 kHz)
mode entry
microcontroller idle
parallel programming mode
(1) See Fig.8.
MGR166
Fig.63 Program mode.
set verify
check
mode
security
VDD = 12.5 to 13 V
handbook, full pagewidth
initialization ready
VPP
P0.7 to P0.0
01H
XX
P2.1/LS0
P2.0/LS1
P2.2/PGM
P2.3/RdStrb
P2.5/WEB
MGR167
Fig.64 Parallel program mode initialization.
1998 Oct 07
100
Philips Semiconductors
Product specification
Pager baseband controller
15.4
PCA5007
Address space
The PCA5007 has a 20 kbytes memory and therefore 15 address pins. Applying an address above 32 kbytes
(address<15> = 1) leads to the selection of the extra rows. The user should not apply these addresses during
programming.
15.5
Single byte programming
Programming and verifying is shown in Fig.65. The upper and lower address byte are loaded one after the other.
The address latch control signals select the proper latch and the RdStrb signal opens the latch (level sensitive).
The order of loading the latches is not important. The data is latched if write enable bar becomes active. After
programming a byte, this byte can be verified without reloading the addresses. If more bytes are programmed after each
other having the same upper address, it is not necessary to reload this upper address.
handbook, full pagewidth
Addr/data set-up
program
verify
VDD = 12.5 to 13 V
VPP
P0.0 to P0.7
Addr high
Addr low
Data in
Data out
P2.1/LS1
P2.0/LS0
P2.2/PGM
P2.3/RdStrb
100 µs
P2.5/WEB
P2.4/GBMbpB
MGR168
Fig.65 Single byte programming mode.
15.6
Multiple byte programming
A multiple byte programming mode has been implemented to increase programming speed. In this mode four bytes can
be programmed in parallel. The addresses of these four bytes have to be equal except for bit 0 and bit 1. Loading the
address and data latches is enabled by making PGM HIGH and GBMbpB LOW at the same time. Figure 66 shows the
address and data set-up and the program pulse. Loading the upper address is only necessary if it differs from the upper
address of the previous quadruple of bytes. In this mode the data latches are controlled by the RdStrb signal (level
sensitive). Figure 67 shows the verification in this mode. It should be noted that data 3 is verified before data 0. If this is
unwanted the lower address byte of data 0 has to be loaded before verifying data 0 and the lower address byte of data 1
before verifying data 1.
1998 Oct 07
101
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
Addr/data_0 to data_1 set-up
handbook, full pagewidth
program
VDD = 12.5 to 13 V
VPP
Addr
high
P0.0 to P0.7
Addr
Lo0
DI_0
Addr
Lo1
DI_1
Addr
Lo2
DI_2
Addr
Lo3
DI_3
P2.1/LL1
P2.0/LL0
P2.2/PGM
P2.3/RdStrb
P2.5/WEB
P2.4/GBMbpB
MGR169
Fig.66 Multiple byte programming mode (address and data load, programming pulse).
verify
handbook, full pagewidth
VDD = 12.5 to 13 V
VPP
P0.7 to P0.0
DO_3
Addr
Lo2
DO_2
Addr
Lo1
DO_1
Addr
Lo0
DO_0
P2.0/LL1
P2.1/LL0
P2.2/PGM
P2.3/RdStrb
P2.5/WEB
P2.4/GBMbpB
MGR170
Fig.67 Multiple byte programming mode (verify).
1998 Oct 07
102
Philips Semiconductors
Product specification
Pager baseband controller
15.7
High voltage timing
The external program voltage VPP has to be HIGH while a
program pulse is applied (WEB active). During verify it can
be either high or equal to the supply voltage. VPP has to be
stable for at least 10 µs before a program pulse can be
applied.
After applying a program pulse a recover time of 1 µs is
needed to discharge the internal high voltage nodes.
During this recover time the memory cannot be accessed
for verify.
Due to the above mentioned set-up time programming
time is reduced if VPP is continuously HIGH during
programming and verifying.
15.8
OTP test modes
OTP test modes will be selected from a test control latch
which can be loaded in parallel programming over Port 0.
The advantage of this is that the test modes of the OTP are
independent of the microcontroller. Table 66 shows the
OTP test modes coded in 7 bits. When a test mode is
loaded the control signals on Port 2 keep their original
functionality and can be used to execute the test mode.
Table 66 Definition of test modes
TCL(7 TO 0)
00000000
TEST MODE
normal mode (no test active)
XXXXXX01
verify mode (self timed)
XXXXXX10
margin 0 mode
XXXXXX11
margin 1 mode
XXXXX1XX
margin VP mode is active
XXXX1XXX
DC_Read mode is active
X001XXXX
drain stress test mode
X010XXXX
gate stress test mode
X011XXXX
mass programming test mode
X100XXXX
X101XXXX
PCA5007
The encoding is such that combinations of test modes are
possible, for instance TCB(7 to 0) = 00001100 enables
both the margin VP and DC_Read test modes.
The so called vt mode, needed to measure analog cell
characteristics, can be entered by making both P2.6/SIG
and P2.7/SEC active (see Fig.61). During normal
programming this mode should not be entered therefore it
is forbidden to make P2.6/SIG and P2.7/SEC HIGH at
the same time.
15.8.1
MASS PROGRAM MODE
The mass program mode can be used to program checker
boards. If this mode is active every internal data latch is
connected to four bit lines and 128 bits can be
programmed in parallel. To write a checker board
0011X0XX has to be loaded in the test register and the
circuit has to be set in the parallel program mode
(P2.2/PGM = 1 and P2.4/GBMbpB = 0). Then data from
address 00H is loaded to address 00 03H down to 00 00H.
For every even word line (A<6> = 0) a program pulse has
to be given at low addresses X0000000 and X0001000.
For the odd lines (A<6> = 1) the pulses have to be applied
to low address x100_0100 and x100_1100. In the user
address space a checker board can be programmed with
320 × 2 = 640 program pulses.
15.9
Signature bytes
Three signature bytes are available to identify the device.
These bytes can be read by doing a verify while the SIG
input (Port 2.6) is active. The contents of the signature
bytes is given in Table 67. Applying a write pulse while the
SIG input is HIGH is forbidden although the contents of the
signature bytes will never be destroyed. The signature
bytes are always readable independent on the security.
Table 67 Addresses and contents of the signature bytes
ADDRESS
CONTENTS
even column test mode
00 30H
15H
odd column test mode
00 31H
C7H
X110XXXX
even row test mode
00 60H
00H
X111XXXX
odd row test mode
1XXXXXXX
OTP interface test
1998 Oct 07
103
Philips Semiconductors
Product specification
Pager baseband controller
15.10 Security
To prevent programming or reading of EPROM contents
by third parties security can be set by programming the
security bits. These bits are located outside the normal
memory matrix and have input and output lines separated
from the normal OTP I/Os. Three bits are present, but only
two are actually used. The third bit can be used for future
extensions. Different levels of security can be set by
programming one or more bits. The bits are read in parallel
at every read cycle and interpreted with the following
definition:
• Level 0, bits 000, no security, no restrictions
• Level 1, bits 001, program disabled
• Level 2, bits 011, program and verify disabled.
The third security may be programmed without affecting
the functionality. However only the combinations 000, 001,
011 and 111 are possible.
After reset security Level 1 is loaded. To enable
programming a read or verify (GB pulse not necessary) is
needed to check the actual security level.
The security bits can be programmed the same as normal
bits. The bits have to be supplied to the three least
significant bits of Port 0.
1998 Oct 07
PCA5007
The SEC bit of Port 2 (bit 7) has to be HIGH during the
program cycle. Loading an address is not necessary.
If Port 2.7/SEC is HIGH during verify, the security bits can
be read on the three least significant bits of Port 0. After
programming 011 to the security bits only the security bits
and the signature bytes can be verified and verifying the
normal addresses is not possible any more. Verifying a
normal address while security Level 2 has been
programmed will result in reading 00H.
The programming time for the security bits is 200 µs
instead of 100 µs for a normal bit. This extra time can be
reached by applying one 200 µs program pulse or by
applying two standard pulses.
Although in this OTP an unprogrammed cell is a logic 1
and a programmed cell is a logic 0, a logic 1 has to be
programmed to increase the security level. The inversion
is performed by the interface block.
Since the security is checked at every read or verify
access, verifying is disabled immediately after
programming security Level 2. Programming is disabled if
a verify or a reset is applied after programming security
Level 1 or higher.
104
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
P1.6
P1.7
XTL2
XTL1
VBAT
VDD(DC)
VIND
VSS(DC)
RESOUT
P3.2
P3.3
handbook, full pagewidth
RESETIN
16 APPENDIX 3: OS SHEET
48 47 46 45 44 43 42 41 40 39 38 37
P3.4
P3.5
AT
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P0.0
1
2
36
3
35
VBAT
4
5
34
33
VPP
6
32
7
31
8
30
9
29
10
28
11
27
12
26
substrate VSS
25
VDD
13 14 15 16 17 18 19 20 21 22 23 24
P0.7
P0.6
P0.5
VSSA
Q(D0)
I(D1)
AFCOUT
VDDA
P0.4
P0.3
P0.2
P0.1
MGR171
Fig.68 Open/short-circuit diagram for PCA5007.
1998 Oct 07
105
VPP
TCLK
EA
PSEN
ALE
VDD
VSS
P1.4
P1.3
P1.2
P1.1
P1.0
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
17 APPENDIX 4: BONDING PAD LOCATIONS
handbook, full pagewidth
48 47 46 45 44 43 42
41
40
39
38
37
1
36
2
35
34
3
33
4
32
5
31
6
4.02
mm
PCA5007H
7
8
30
9
29
28
10
27
11
26
25
12
131415
16 17 18 19 20 21 22 23 24
4.01 mm
MGR172
Fig.69 Bonding pad locations.
Table 68 Bonding pad locations (dimensions in µm)
PAD
SYMBOL
BOND PIN
CENTRE x
BOND PIN
CENTRE y
PAD SIZE x, y
1
P3.4
91.0
3567.0
87.0
2
P3.5
91.0
3292.0
87.0
3
AT
91.0
3017.0
87.0
4
P2.0
91.0
2742.0
87.0
5
P2.1
91.0
2467.0
87.0
6
P2.2
91.0
2192.0
87.0
7
P2.3
91.0
1710.0
87.0
8
P2.4
91.0
1435.0
87.0
9
P2.5
91.0
1160.0
87.0
1998 Oct 07
106
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
PAD
SYMBOL
BOND PIN
CENTRE x
BOND PIN
CENTRE y
PAD SIZE x, y
10
P2.6
91.0
885.0
87.0
11
P2.7
91.0
610.0
87.0
12
P0.0
91.0
335.0
87.0
13
P0.1
330.0
91.0
87.0
14
P0.2
457.5
91.0
87.0
15
P0.3
580.0
91.0
87.0
16
P0.4
1972.5
91.0
87.0
17
VDDA
2170.0
91.0
87.0
18
AFCOUT
2365.0
91.0
87.0
19
I(D1)
2555.0
91.0
87.0
20
Q(D0)
2747.5
91.0
87.0
21
VSSA
2940.0
91.0
87.0
22
P0.5
3130.0
91.0
87.0
23
P0.6
3322.5
91.0
87.0
24
P0.7
3515.0
91.0
87.0
25
P1.0
3776.6
408.8
87.0
26
P1.1
3776.6
607.5
87.0
27
P1.2
3776.6
806.2
87.0
28
P1.3
3776.6
1005.0
87.0
29
P1.4
3776.6
1203.8
87.0
30
VSS
3776.6
1400.0
87.0
31
VDD
3776.6
2532.5
87.0
32
ALE
3776.6
2726.5
87.0
33
PSEN
3776.6
2920.5
87.0
34
EA
3776.6
3114.5
87.0
35
TCLK
3776.6
3308.5
87.0
36
VPP
3776.6
3502.5
87.0
37
P1.6
3321.7
3811.5
87.0
38
P1.7
2982.4
3811.5
87.0
39
XTL2
2663.1
3811.5
87.0
40
XTL1
2283.8
3811.5
87.0
41
VBAT
1964.5
3811.5
87.0
42
PowerPads_
1550.0
3811.5
84.0
43
PowerPads_
1310.0
3811.5
84.0
44
PowerPads_
1190.0
3811.5
87.0
45
RESETIN
953.2
3811.5
87.0
46
RESOUT
766.2
3811.5
87.0
47
P3.2
579.2
3811.5
87.0
48
P3.3
392.2
3811.5
87.0
1998 Oct 07
107
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
18 PACKAGE OUTLINE
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
c
y
X
36
25
A
37
24
ZE
e
E HE
A A2
(A 3)
A1
w M
pin 1 index
θ
bp
Lp
L
13
48
detail X
12
1
ZD
e
v M A
w M
bp
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
v
w
y
mm
1.60
0.20
0.05
1.45
1.35
0.25
0.27
0.17
0.18
0.12
7.1
6.9
7.1
6.9
0.5
9.15
8.85
9.15
8.85
1.0
0.75
0.45
0.2
0.12
0.1
Z D (1) Z E (1)
θ
0.95
0.55
7
0o
0.95
0.55
o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
94-12-19
97-08-01
SOT313-2
1998 Oct 07
EUROPEAN
PROJECTION
108
Philips Semiconductors
Product specification
Pager baseband controller
If wave soldering cannot be avoided, for LQFP
packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:
19 SOLDERING
19.1
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(order code 9398 652 90011).
19.2
Reflow soldering
Reflow soldering techniques are suitable for all LQFP
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250 °C.
19.3
PCA5007
Wave soldering
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
19.4
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Wave soldering is not recommended for LQFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
CAUTION
Wave soldering is NOT applicable for all LQFP
packages with a pitch (e) equal or less than 0.5 mm.
1998 Oct 07
Repairing soldered joints
109
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
20 DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
21 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
22 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1998 Oct 07
110
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
NOTES
1998 Oct 07
111
Philips Semiconductors – a worldwide company
Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
Tel. +61 2 9805 4455, Fax. +61 2 9805 4466
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010,
Fax. +43 160 101 1210
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773
Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 689 211, Fax. +359 2 689 102
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700
Colombia: see South America
Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,
Tel. +45 32 88 2636, Fax. +45 31 57 0044
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615800, Fax. +358 9 61580920
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,
Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 23 53 60, Fax. +49 40 23 536 300
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,
Tel. +30 1 4894 339/239, Fax. +30 1 4814 240
Hungary: see Austria
India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966
Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381
Middle East: see Italy
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. +48 22 612 2831, Fax. +48 22 612 2327
Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Tel. +65 350 2538, Fax. +65 251 6500
Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. +27 11 470 5911, Fax. +27 11 470 5494
South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 821 2382
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 93 301 6312, Fax. +34 93 301 4107
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. +90 212 279 2770, Fax. +90 212 282 6707
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
435102/750/01/pp112
Date of release: 1998 Oct 07
Document order number:
9397 750 03847