212209

AEC-Q100G Qualification Summary
100ld LQFP
Objective: Bolero 256k New Product Introduction Qualification
Freescale PN:
Part Name:
Technology:
Package:
Fab / Assembly /
Final Test Sites:
Maskset#:
Rev#:
Die Size (in mm)
W xLxT
Part Operating
Temp. Grade:
Customer Name(s):
PN(s):
Design Engr:
Phone #:
Product Engr:
Phone #:
Prod. Package
Phone #:
NPI PRQE:
Phone #:
MPC5602D
Bolero 256k
0.09um CMOS90 Z3 core
LQFP 100 14x14 x 1.4 Pitch 0.5
FSL-ATMC / FSL-KLM-FM
FSL-TJN-FM
M18Y
1
3.778 x 3.411 x 0.3302 (with scribe)
125°C
Grade 1
Trace/DateCode
General Market
Summary Revision #
Date:
Akshay Pathak
QUARTZ Tracking #:
Allan Scott
212209
(Signature/Date shown below may be electronic)
PPE Approval
Signature & Date:
NPI PRQE Plan Approval Douglas Blackwood
Signature & Date: 8th November 2011
P.L. Mei
Douglas Blackwood
DD88507
QCTAC1118
1.3
9th November 2011
DD88771
QCTAD1119
DD86284
QCTAA1122
CAB Approval 09191268M
Signature & Date: Neil Ross 9th November 2011
TESTS HIGHLIGHTED IN YELLOW WERE PERFORMED FOR THIS STUDY
This testing is performed by Freescale FSL-EKB, FSL-KLM, and FSL-ATX where noted in the Comments
GROUP A - ACCELERATED ENVIRONMENTAL STRESS TESTS
STRESS TEST
PC
HAST
Reference
J=JESD22
JESD22- Preconditioning :
A113
MSL 3 @ 260°C, +5/-0°C
J-STD-020 Pre and Post CSAM SS=11 units per lot per stress
test
JESD22- PC before HAST required for SMDs.
A110
Highly Accelerated Stress Test, Biased:
HAST = 130°C/85%RH for 96 hrs.
Bias = 5.5V
AC
JESD22A102
TC
JESD22A104
AEC Q100Appendix 3
STRESS TEST
PC + PTC
Test Conditions
(Surface Mount Devices Only - PC required
for THB, HAST, AC, UHST, TC, PC+PTC)
PC before AC required for SMDs.
Autoclave:
AC = 121°C/100%RH/15 psig for 96 hrs
End Point
Requirements
TEST @ RHC
TEST @ RH
TEST @ R
PC before TC required for SMDs
TEST @ HC
Temperature Cycle:
WBP =/> 3 grams
TC = -65°C to 150°C for 500 cycles.
WBP after TC on 5 devices from 1 lot; 2 bonds per
corner and one mid-bond per side on each device.
Record which pins were used.
Reference
Test Conditions
End Point
J=JESD22
(Surface Mount Devices Only - PC required
Requirements
for THB, HAST, AC, UHST, TC, PC+PTC)
JESD22- For SMD devices only.
TEST @ RH
A105
Preconditioning plus Power Temperture Cycle:
PTC
JESD22A105
Power Temperature Cycle:
PTC = ?°C to ?°C for 1000 cycles;
Bias = ?
TEST @ RH
HTSL
JESD22A103
High Temperature Storage Life:
150°C for 1008 hrs
TEST @ RHC
STRESS TEST
Reference
HTOL
JESD22A108
Minimum
Sample Size
# of Lots
Total Units
All surface mount devices prior to THB, HAST, AC,
UHST, TC, PC+PTC
77
3
231
77
3
231
77
3
231
Results
LotID-(#Rej/SS)
NA=Not Applicable
Comments
Lot1: 0/231
Lot2: 0/231
Lot3: 0/231
Performed in TJN
Lot1: 0/77
Lot2: 0/77
[1]
Lot3: 1/77
Performed in KLM
[1]
Lot3: 0/77 re-run
Lot1: 0/77
Lot2: 0/77
Lot3: 0/77
Lot1: 0/77
Lot2: 0/77
Lot3: 0/77
see 8D attached #136873a for details.
1 fail for EOS not attributed to Bolero 256k.
Performed in TJN
Performed in TJN
All Post 500TC wirepulls >3g
Minimum
Sample Size
# of Lots
Total Units
22
SMD only
0
0
23 SMDs;
45 non- SMD
0
0
77
0
0
Results
LotID-(#Rej/SS)
NA=Not Applicable
Comments
Low power device, not required.
Not required.
1. P< 1W
2. ∆Tj < 40°C
3. No Inductive Load
See EDR data to cover this item
TEST GROUP B - ACCELERATED LIFETIME SIMULATION TESTS
NBTI
ELFR
EDR
Test Conditions
End Point
Requirements
Minimum
Sample Size
# of Lots
Total Units
77
1
77
High Temperature Operating Life:
Ta= 125°C for 1008, 2016hrs FIO
Bias:
V dd = 5.0V nom : 6.0V Stress
Vin, Vdd_bv = 3.3V nom : 3.6V Stress
NVM cycling @125°C, as shown in EDR below, is
required
NVM in Checkerboard
TEST @ RHC
Identify the speed pattern that drifts the most and
create guardband if needed. (Two readpoints Time zero and at final NBTI readpoint). Serialised
units.
AEC Q100- Early Life Failure Rate:
008
Ta = 125°C for 48 hrs;
Bias:
V dd = 5.0V nom : 6.0V Stress
Vin, Vdd_bv = 3.3V nom : 3.6V Stress
10% of NVM cycling @125°C, as shown in EDR
below, is required
NVM in Checkerboard
TEST @ RHC
77
1
TEST @ RHC
800
1
AEC Q100- NVM Endurance, Data Retention,
005
C-Flash: 256k Array @ 125°C
( 2x16k, 3x32k, 1x128k)
100K W/E for 16k block size
10K W/E for 32k block size
1K W/E for 128k block size
TEST @ RHC
77
1
Results
LotID-(#Rej/SS)
NA=Not applicable
Lot1: 0/77
(1008hrs)
Comments
Performed in TJN
Generic Data
Lot2: 0/77 (3024hrs)
Lot3: 0/77 (1008hrs)
Lot4: 0/77 (1008hrs)
Generic Data:
Lot2,3,4: Quartz: 212019 Pictus 256k 100ld NPI
Qualification. Performed in TJN
77
Lot1: 0/77
Performed in TJN
800
Lot1: 0/800
Performed in TJN
Generic Data
Lot2: 0/400
Lot3: 0/400
Lot4: 0/787
Lot5: 0/813
Generic Data:
Lot2,3: Quartz: 212019 Pictus 256k 100ld NPI
Qualification. Performed in EKB
Lot4: Quartz: 212657 Bolero 1.5M 176ld
Qualification. Performed in EKB
Lot5: Quartz: 212658 Bolero 1.5M 144ld
Qualification. Performed in EKB
Lot1: 0/77
Performed in TJN
Generic Data
Lot1: 0/77
Lot2: 0/77
Lot3: 0/77
Generic Data:
Lot1,2,3: Quartz: 212019 Pictus 256k 100ld NPI
Qualification. Performed in EKB
Lot1: 0/77
Performed in TJN
Generic Data
Lot1: 0/77
Lot2: 0/77
Lot3: 0/77
Generic Data:
Lot1,2,3: Quartz: 212019 Pictus 256k 100ld NPI
Qualification. Performed in EKB
77
(1008hrs)
D-Flash: 64Kb Block @ 125°C
100K W/E for 16k block size
NVM in Checkerboard 504, 1008hrs @ 150°C
NVM Endurance, Data Retention,
TEST @ RHC
77
C-Flash 0: 256k Array @ -40°C
( 2x16k, 3x32k, 1x128k)
100K W/E for 16k block size
10K W/E for 32k block size
1K W/E for 128k block size
1
77
D-Flash: 64Kb Block @ -40°C
100K W/E for 16k block size
NVM in Checkerboard 504, 1008hrs @ 150°C
FORMPPAP004XLS
1 of 3
Freescale Rev U
Freescale PN: MPC5602D
Part Name: Bolero 256k
Customer Name(s): General Market
PN(s):
Summary Revision #
Date:
1.3
9th November 2011
TEST GROUP C - PACKAGE ASSEMBLY INTEGRITY TESTS
STRESS TEST
Reference
Test Conditions
End Point
Requirements
Minimum
Sample Size
# of Lots
Total Units
Results
LotID-(#Rej/SS)
NA=Not applicable
Comments
WBS
AEC Q100- Wire Bond shear
001
Cpk = or > 1.67
30 bonds
from minimum 5
units
1
5
Lot1: Cpk= 3.56
Performed in KLM
WBP
MilStd883- Wire Bond Pull
2011
Cond. C or D
Cpk = or > 1.67
30 bonds
from minimum 5
units
1
5
Lot1: Cpk= 3.33
Performed in KLM
>95% lead coverage
of critical areas
15
1
15
Lot1: 0/15
Performed in KLM
Cpk = or > 1.67
10
3
30
(w ) (l)
(h)
Lot1: Cpk= 3.02 3.21 4.11
Lot2: Cpk= 3.21 3.25 4.72
Lot3: Cpk= 3.82 3.56 3.58
Performed in KLM
Cpk = or >1.67
10
0
0
N/A, not required for leaded devices.
5
0
0
N/A, not required for SM devices.
SD
JESD22B102
PD
JESD22B100
Solderability;
8hr. Steam age (1 hr. for Au-plated leads) prior to
test.
If production burn-in is done, samples must also
undergo burn-in.
Physical Dimensions PD per 98A drawing
AEC-Q100- Solder Ball Shear;
010
Performed on all solder ball mounted packages e.g.
PBGA, Chip Scale, Micro Lead Frame (but NOT
Flip Chip).
Two 260°C reflow cycles before shear.
JESD22- Lead Integrity
B105
Not required for surface mount devices;
Only required for through-hole devices.
SBS
LI
(5 balls from a min. of
10 devices)
No lead breakage or
cracks
(10 leads from each
of 5 parts)
TEST GROUP D - DIE FABRICATION RELIABILITY TESTS
STRESS TEST
Reference
Test Conditions
End Point
Requirements
Minimum
Sample Size
# of Lots
Total Units
Results
LotID-(#Rej/SS)
NA=Not applicable
Comments
Electro Migration
Derivative Device on qualified The data, test method, calculations and internal
Process. Report available on criteria should be available to the customer upon
request
request for new technologies.
NBTI
Negative Bias Temperature Instability
Derivative Device on qualified The data, test method, calculations and internal
Process. Report available on criteria should be available to the customer upon
request
request for new technologies.
TDDB
Time Dependent Dielectric Breakdown
Derivative Device on qualified The data, test method, calculations and internal
Process. Report available on criteria should be available to the customer upon
request
request for new technologies.
HCI
Hot Carrier Injection
Derivative Device on qualified The data, test method, calculations and internal
Process. Report available on criteria should be available to the customer upon
request
request for new technologies.
SM
Stress Migration
Derivative Device on qualified The data, test method, calculations and internal
Process. Report available on criteria should be available to the customer upon
request
request for new technologies.
EM
FORMPPAP004XLS
2 of 3
Freescale Rev U
Freescale PN: MPC5602D
Part Name: Bolero 256k
Customer Name(s): General Market
PN(s):
Summary Revision #
Date:
1.3
9th November 2011
TEST GROUP E - ELECTRICAL VERIFICATION TESTS
STRESS TEST
Reference
Test Conditions
End Point
Requirements
Minimum
Sample Size
# of Lots
Total Units
All
All
All
TEST @ RH
2KV min.
3 units per
Voltage level
1
12
Lot1:
500V 0/3
1000V 0/3
1500V 0/3
2000V 0/3
Performed in KLM
AEC-Q100- ElectroStatic Discharge/
ESD
003
Machine Model Classification:
(MM)
Test @ 50 / 100 / 150 / 200/ 250 Volts
CLASSIFICATION
See AEC-Q100-003 for classification levels.
TEST @ RH
250V min.
3 units per
Voltage level
1
15
Lot1:
50V 0/3
100V 0/3
150V 0/3
200V 0/3
Performed in KLM
AEC-Q100- ElectroStatic Discharge/
ESD
011
Charged Device Model Classification:
(CDM)
Test @ 250 / 500 / 750 Volts
CLASSIFICATION
See AEC-Q100-011 for classification levels.
JESD78 Latch-up:
LU
plus
Test per JEDEC JESD78 with the AEC-Q100-004
AEC-Q100- requirements.
004
Ta= Operating Temperature Maximum
TEST @ RH
Corner pins =/> 750V;
All other pins =/>
500V
TEST @ RH
3 units per
Voltage level
1
9
Performed in KLM
6
1
6
Lot1:
250V 0/3
500V 0/3
750V 0/3
Lot1: 0/6
30
3
90
Freescale
48A
Pre- and Post Functional / Parametrics
Test software shall meet requirements of AECQ100-007.
Testing performed to the limits of device
specification in temperature and limit value.
AEC-Q100- ElectroStatic Discharge/
ESD
002
Human Body Model Classification:
(HBM)
Test @ 500 / 1000 / 1500 / 2000Volts
CLASSIFICATION
See AEC-Q100-002 for classification levels.
TEST
0 Fails
ED
AEC-Q100- Electrical Distribution
009,
Freescale
48A spec
TEST @ RHC
Cpk = or > 1.67
FG
AEC-Q100- Fault Grading
007
AEC-Q003 Characterization:
Performed on new technologies and part families.
FG shall be = or >
98% for qual units
AEC-Q100- Electro-Thermally Induced Gate Leakage;
006
155°C, 2.0 min, +400/-400 V
TEST @ R
6
1
SAE
J1752/3 Radiated
Emissions
AEC Q100012
<40dBuV
150kHz - 1GHz
1
CHAR
GL
EMC
SC
Electromagnetic Compatibility
(see AEC Q100 Appendix 5 for test applicability;
done on case-by-case basis per
customer/Freescale agreement)
Short Circuit Characterization
Applicable to all smart power devices. This test
and statistical evaluation (see section 4 of Q100012) shall be performed per agreement between
user and supplier on a case-by-case basis.
SER
JEDEC Unaccelerated:
JESD89-1 or
Accelerated:
JESD89-2 &
JESD89-3
Soft Error Rate
Applicable to devices with memory sizes 1Mbit
SRAM or DRAM based cells. Either test option (unaccelerated or accelerated) can be performed, in
accordance to the referenced specifications. This
test and its accept criteria is performed per
agreement between user and supplier on a case-bycase basis. Final test report shall include detailed
test facility location and altitude data.
STRESS TEST
Reference
Test Conditions
Results
LotID-(#Rej/SS)
NA=Not applicable
Lot1: DD86284
Lot2: DD88771
Lot3: DD88507
Comments
Performed in KLM
Lot1: Pass
Lot2: Pass
Lot3: Pass
Y
99%
Y
Report Available
Performed in EKB
6
Lot1: 0/6
Performed in KLM
1
1
Pass
Performed in ATX
10
0
0
Not applicable to microcontroller
3
0
0
Not applicable to microcontroller with RAM <
1Mbit
TEST GROUP F - DEFECT SCREENING TESTS
PAT
AEC Q001 Part Average Testing
SBA
AEC Q002 Statistical Bin Analysis
Generic
Quartz
212019
212657
212658
Data:
Device
MPC5602P
MPC6507B
MPC6507B
Mask
0M22Y
0M03Y
0M03Y
Revision
1.0
1.1
1.2
1.3
FORMPPAP004XLS
Title
Pictus 256k 100ld NPI Qualification
Bolero 1.5M 176ld Qualification
Boler0 1.5M 144ld Qualification
Revision Date
29th April 2009
15th April 2011
6th June 2011
9th November 2011
End Point
Requirements
Minimum
Sample Size
# of Lots
Total Units
Has PAT been
established for this
part?
Has SBYA been
established for this
part?
Fab
FSL-ATMC
FSL-ATMC
FSL-ATMC
Assembly
FSL-KLM
ASE-CL
FSL-KLM
Results
LotID-(#Rej/SS)
NA=Not applicable
implemented
Comments
implemented
Mould
SUMITOMO EME-G700E
HITACHI CEL-9240
SUMITOMO EME-G700E
Description
Original issue
Updated Cycling Requirements
Updated Qual locations and possible generic data
Added Results
3 of 3
Die Size
3.737x3.564x0.3302
5.082x5.301x0.33mm
5.082x5.301x0.33mm
CAB
09201374M
11161323M
11161323M
Douglas Blackwood
Douglas Blackwood
Douglas Blackwood
Douglas Blackwood
Freescale Rev U
Freescale 8D Report
8D Header
8D Title
SPC5602D (Bolero 256K 100ld Package qualification ) Post HAST Short Circuit fail
8D Abstract
One unit from lot (DD86284) of Bolero 256K 100ld package submitted to HAST has failed
at post stress testing on J750 ATE. The unit showed to have pins P10 (PE9) and P11
(PE10) shorted together and to Pin15 (Vdd_HV).
Corrective action #
C.A. Status
CLOSED
Creation Date
21-OCT-2011
Incident #
136873a
ICAP
FIUO
Point of Failure
HAST
Freescale Part#
SPC5602DMLL4
Part Common Name
BOLERO 256K
D1 Team Description
Name
Bruce Robertson
Douglas Blackwood
Allan Scott
Elton Osmani
Jason Goertz
Navin Kumar
Location
East Kilbride
East Kilbride
East Kilbride
East Kilbride
Austin
KLM
Function
Product Engineering Manager
NPI Quality
Product/Test Engineering
Product Engineering
Product Analysis Engineer
Reliability Engineer
Role
Team Member
Team Leader
Team Member
Team Member
Team Member
Team Member
Freescale Semiconductor Internal Use Only. Freescale TM and the Freescale logo are trademarks of Freescale
Semiconductor, Inc. All other product or service names are the property of their respective owners. ©Freescale Semiconductor,
Inc. 2006.
D2 Problem Description
Problem
Description
During the 100ld package qualification one unit failed continuity on the J750 test system
during post HAST stress testing. Further testing showed that the fail was a short circuit
between Pins 10 and 11 of the 100ld package.
The failure was verified using the J750 test system interfaced with the 100ld Final Test
hardware and using the Final Test qualification test program, testing was confirmed at
ambient temperature using both handler and hand test sockets.
Further verification was carried out on the bench using a standard multi-meter set on
resistance measurement.
Dut 1 recorded as : ECID W8X29Y33
Further analysis by Product analysis confirmed that there was a low ohmic reading
between the two pins and VDD_HV.
Full details of finding and subsequent findings listed below.
D3 Containment (Interim Containment Action ICA)
Containment
Final Test results showed that there was a short circuit between Pin 9 and Pin 10 of the
100ld package and VDD_HV. As continuity is at the very start of the test flow and is
included in every insertion then this fail was detected at the first test insertion.
QRA Test data log of failing device showed fail to a group of pins in continuity then
subsequent fail to specific pins in continuity, JVT, and DPS checks.
1008
1009
1010
1011
1085
1086
1060
1082
1083
1089
1090
4
4
4
4
4
4
4
4
4
4
4
FAIL
FAIL
FAIL
FAIL
FAIL
FAIL
FAIL
FAIL
FAIL
FAIL
FAIL
Cont_Fct_Vdd
Cont_Fct_Vdd
Cont_Fct_Sh_Vdd
Cont_Fct_Sh_Vdd
Cont_Sh_Dc_Vdd
Cont_Sh_Dc_Vdd
DPS_HV_Chk
JVT_SLOW_POS
JVT_SLOW_POS
JVT_SLOW_NEG
JVT_SLOW_NEG
cont_func_vdd_no_oscin
cont_func_vdd_no_oscout
cont_func_vdd_short_no_oscin
cont_func_vdd_short_no_oscout
PAD_73
PAD_74
VDD_HV_Main 836.0400 uA
PAD_73
PAD_74
PAD_73
PAD_74
Post Stress testing has contained and highlighted these as fails therefore containment is
part of the existing test flow and no changes are necessary.
This product is in qualification with no production parts shipped that require to be
contained.
Freescale Semiconductor Internal Use Only. Freescale TM and the Freescale logo are trademarks of Freescale
Semiconductor, Inc. All other product or service names are the property of their respective owners. ©Freescale Semiconductor,
Inc. 2006.
D4 Root Cause and Escape Point
Root Cause
Root cause for this failing unit is very difficult to ascertain, Product Analysis has
concluded that an EOS event took place but the actual source and cause of EOS has
not been established. Trace history of the part shows that it has been through all test
flows and only fails at the test insertion immediately following HAST.
•
QRA Testing of device at T0 completed in Final Test in TJN shows that the part
was a bin 1 and therefore has passed continuity and relevant JVT DPS tests.
1008
1009
1060
1082
1083
1089
1090
•
•
•
•
•
•
•
•
2
2
2
2
2
2
2
PASS
PASS
PASS
PASS
PASS
PASS
PASS
Cont_Fct_Vdd
Cont_Fct_Vdd
DPS_HV_Chk
JVT_SLOW_POS
JVT_SLOW_POS
JVT_SLOW_NEG
JVT_SLOW_NEG
cont_func_vdd_no_oscin
cont_func_vdd_no_oscout
PAD_73
PAD_74
PAD_73
PAD_74
Parts completed HAST in KLM and subsequently failed continuity at the first final
test (QRA) insertion.
Product Analysis confirmed leakage between the pins 10, 11, & 15 and VSS as
reported by test.
PA carried out an x-ray looking for possible internal shorts but this did not show
any defects.
CSAM was carried out on the part to highlight any voiding in the mould compound
that could provide a path for moisture ingression, no anomalies were detected
The part was flat-sectioned from the top of the package until the wires were
severed to just above the ball bonds.
It was confirmed that the short is on the die side only and not the package side.
The unit was then deprocessed and evidence of EOS was observed at the pins
which showed the failing condition:
The images below show EOS around the failing pins.
Fig1: Low magnification image of pad damage
Freescale Semiconductor Internal Use Only. Freescale TM and the Freescale logo are trademarks of Freescale
Semiconductor, Inc. All other product or service names are the property of their respective owners. ©Freescale Semiconductor,
Inc. 2006.
Fig2: SEM image showing EOS damage
Fig3: SEM image showing cross section through EOS damage
Occur Point
•
PA provided multiple cross sections through the damage area; however, no root
cause was identifiable in the analysis.
•
Hardware: HAST Board used to stress the units were inspected prior to use for
signs of wear and poor socket condition, following stress the same inspection was
performed looking for degradation of the boards – no issues were detected.
•
Human Error: To rule out the possibility of an orientation issues during loading of
the HAST boards an experiment was performed to rotate units in the board
through all combinations; this was repeated twice. Although the positioning of the
devices in the sockets meant incorrect voltages on the pins, PE were not able to
replicate the EOS damage and all units passed full production test afterwards.
Freescale Semiconductor Internal Use Only. Freescale TM and the Freescale logo are trademarks of Freescale
Semiconductor, Inc. All other product or service names are the property of their respective owners. ©Freescale Semiconductor,
Inc. 2006.
•
Design: A review, performed by both Freescale and ST Design Engineers, did not
show any concerns on either the port pins damaged in terms of weakness, design
fault, or with the Bias used during stress. The pads in question are identical to
those used in Bolero 1.5M.
Currently there are in excess of 229k units in the field with no returns for EOS on
these 2 pins;
Device
Qty
BOLERO_1.5M
Escape Point
•
229479
As the part was proven to be a pass unit post preconditioning, the unit in question
was found to fail at the first read point following the stress in which the EOS
occurred, and as such, did not escape the test/stress flow.
D5 Permanent Corrective Action
Corrective Actions
Due to the nature of this failure, corrective actions for this particular event are
difficult to define; root cause of the leakage fails has not been established. As
such, the team cannot implement corrective actions at this time.
D6 Validate Corrective Action
Validation
A further sample of 77 units from the same lot were processed through the same
stress flow (MSL 3 pre-conditioning @ 260°C followed by 96hrs HAST) with each
part uniquely identified in the HAST socket however no issues were seen and all
units passed full production test program.
D7 Prevent Recurrence
Prevent Recurrence
Action to prevent recurrence at this time cannot be implemented as root cause of
the failure is unknown.
D8 Recognise Team
Recognition
Although no root cause was identified, the team investigating the unit put in a
significant effort and were thanked for their time.
Freescale Semiconductor Internal Use Only. Freescale TM and the Freescale logo are trademarks of Freescale
Semiconductor, Inc. All other product or service names are the property of their respective owners. ©Freescale Semiconductor,
Inc. 2006.