Low-power dual PCB configurable multiple function gate

74AUP2G98
Low-power dual PCB configurable multiple function gate
Rev. 2 — 2 December 2015
Product data sheet
1. General description
The 74AUP2G98 is a dual configurable multiple function gate with Schmitt-trigger inputs.
Each gate within the device can be configured as any of the following logic functions
MUX, AND, OR, NAND, NOR, inverter and buffer; using the 3-bit input. All inputs can be
connected directly to VCC or GND.
This device ensures very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power down applications using IOFF. The IOFF
circuitry disables the output, preventing the potentially damaging backflow current through
the device when it is powered down.
2. Features and benefits
 Wide supply voltage range from 0.8 V to 3.6 V
 High noise immunity
 ESD protection:
 HBM JESD22-A114F exceeds 5000 V
 MM JESD22-A115-A exceeds 200 V
 CDM JESD22-C101E exceeds 1000 V
 Low static power consumption; ICC = 0.9 A (maximum)
 Latch-up performance exceeds 100 mA per JESD 78 Class II
 Inputs accept voltages up to 3.6 V
 Low noise overshoot and undershoot < 10 % of VCC
 IOFF circuitry provides partial power-down mode operation
 Multiple package options
 Specified from 40 C to +85 C and 40 C to +125 C
74AUP2G98
NXP Semiconductors
Low-power dual PCB configurable multiple function gate
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74AUP2G98DP
40 C to +125 C
TSSOP10
plastic thin shrink small outline package; 10 leads;
body width 3 mm
SOT552-1
74AUP2G98GU
40 C to +125 C
XQFN10
plastic, extremely thin quad flat package; no leads;
10 terminals; body 1.40  1.80  0.50 mm
SOT1160-1
74AUP2G98GF
40 C to +125 C
XSON10
plastic extremely thin small outline package; no leads; SOT1081-2
10 terminals; body 1.0  1.7  0.5 mm
4. Marking
Table 2.
Marking
Type number
Marking code[1]
74AUP2G98DP
a9
74AUP2G98GU
a9
74AUP2G98GF
a9
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Q$
Q<
Q%
Q&
DDD
Fig 1.
Logic diagram (one gate)
74AUP2G98
Product data sheet
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Rev. 2 — 2 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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74AUP2G98
NXP Semiconductors
Low-power dual PCB configurable multiple function gate
6. Pinning information
6.1 Pinning
$83*
$
9&&
%
<
&
&
<
%
*1'
$
DDD
Fig 2.
Pin configuration SOT552-1 (TSSOP10)
$83*
$
9&&
<
WHUPLQDO
LQGH[DUHD
$83*
&
&
%
$
*1'
<
9&&
%
<
&
&
<
%
*1'
$
%
$
7UDQVSDUHQWWRSYLHZ
7UDQVSDUHQWWRSYLHZ
DDD
Fig 3.
DDD
Pin configuration SOT1160-1 (XQFN10)
74AUP2G98
Product data sheet
Fig 4.
Pin configuration SOT1081-2 (XSON10)
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Rev. 2 — 2 December 2015
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74AUP2G98
NXP Semiconductors
Low-power dual PCB configurable multiple function gate
6.2 Pin description
Table 3.
Pin description
Symbol
Pin
Description
SOT552-1 and SOT1081-2 SOT1160-1
1A, 2A
1, 6
10, 5
data input
1B, 2B
2, 7
1, 6
data input
1C, 2C
3, 8
2, 7
data input
1Y, 2Y
9, 4
8, 3
data output
GND
5
4
ground (0 V)
VCC
10
9
supply voltage
7. Functional description
Table 4.
Function table[1]
Input
Output
nC
nB
nA
nY
L
L
L
H
L
L
H
H
L
H
L
L
L
H
H
L
H
L
L
H
H
L
H
L
H
H
L
H
H
H
H
L
[1]
H = HIGH voltage level; L = LOW voltage level.
7.1 Logic configurations
Table 5.
Function selection table
Logic function
Figure
2-input MUX with inverted output
see Figure 5
2-input NAND
see Figure 6
2-input NOR with one input inverted
see Figure 7
2-input AND with one input inverted
see Figure 7
2-input NAND with one input inverted
see Figure 8
2-input OR with one input inverted
see Figure 8
2-input NOR
see Figure 9
Buffer
see Figure 10
Inverter
see Figure 11
74AUP2G98
Product data sheet
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Rev. 2 — 2 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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74AUP2G98
NXP Semiconductors
Low-power dual PCB configurable multiple function gate
9&&
9&&
Q%
Q%
Q<
Q$
Q$
Q&
Q$
Q&
Q<
Q$
Q<
Q&
Q<
Q&
DDD
DDD
Pin numbers are not valid for SOT1160-1 package
Fig 5.
Pin numbers are not valid for SOT1160-1 package
2-input MUX with inverted output
Fig 6.
2-input NAND gate
9&&
9&&
Q$
Q&
Q<
Q$
Q&
Q$
Q<
Q%
Q&
Q&
Q<
Q%
Q%
Q&
Q<
Q<
Pin numbers are not valid for SOT1160-1 package
Pin numbers are not valid for SOT1160-1 package
2-input AND gate with input A inverted or
2-input NOR gate with inverted C input
Fig 8.
2-input OR gate with input B inverted or
2-input NAND gate with input C inverted
9&&
9&&
Q%
Q%
Q&
Q<
Q&
Q&
Q<
Q<
Q&
Q<
DDD
DDD
Pin numbers are not valid for SOT1160-1 package
Fig 9.
Q<
DDD
DDD
Fig 7.
Q&
Pin numbers are not valid for SOT1160-1 package
2-input NOR gate
Fig 10. Buffer
9&&
Q%
Q%
Q<
Q<
DDD
Pin numbers are not valid for SOT1160-1 package
Fig 11. Inverter
74AUP2G98
Product data sheet
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Rev. 2 — 2 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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74AUP2G98
NXP Semiconductors
Low-power dual PCB configurable multiple function gate
8. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
Conditions
VI < 0 V
[1]
VO < 0 V
[1]
Min
Max
Unit
0.5
+4.6
V
50
-
mA
0.5
+4.6
V
50
-
mA
0.5
+4.6
V
-
20
mA
VO
output voltage
Active mode and Power-down
mode
IO
output current
VO = 0 V to VCC
ICC
supply current
-
50
mA
IGND
ground current
50
-
mA
Tstg
storage temperature
65
+150
C
Ptot
total power dissipation
-
250
mW
[1]
[2]
Tamb = 40 C to +125 C
[2]
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For TSSOP10 package: above 125C the value of Ptot derates linearly with 8.33 mW/K.
For XQFN10 (SOT1160-1) package: above 128 C the value of Ptot derates linearly with 11.5 mW/K.
For XSON10 package: above 45 C the value of Ptot derates linearly with 2.4 mW/K.
9. Recommended operating conditions
Table 7.
Recommended operating conditions
Symbol
Parameter
VCC
VI
VO
output voltage
Tamb
Conditions
Min
Max
Unit
supply voltage
0.8
3.6
V
input voltage
0
3.6
V
Active mode
0
VCC
V
Power-down mode; VCC = 0 V
0
3.6
V
40
+125
C
ambient temperature
74AUP2G98
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 2 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
6 of 21
74AUP2G98
NXP Semiconductors
Low-power dual PCB configurable multiple function gate
10. Static characteristics
Table 8.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
IO = 20 A; VCC = 0.8 V to 3.6 V
VCC  0.1
-
-
V
IO = 1.1 mA; VCC = 1.1 V
0.75  VCC -
-
V
IO = 1.7 mA; VCC = 1.4 V
1.11
-
V
Tamb = 25 C
VOH
VOL
HIGH-level output voltage
LOW-level output voltage
VI = VT+ or VT
-
IO = 1.9 mA; VCC = 1.65 V
1.32
-
-
V
IO = 2.3 mA; VCC = 2.3 V
2.05
-
-
V
IO = 3.1 mA; VCC = 2.3 V
1.9
-
-
V
IO = 2.7 mA; VCC = 3.0 V
2.72
-
-
V
IO = 4.0 mA; VCC = 3.0 V
2.6
-
-
V
IO = 20 A; VCC = 0.8 V to 3.6 V
-
-
0.1
V
IO = 1.1 mA; VCC = 1.1 V
-
-
0.3  VCC
V
VI = VT+ or VT
IO = 1.7 mA; VCC = 1.4 V
-
-
0.31
V
IO = 1.9 mA; VCC = 1.65 V
-
-
0.31
V
IO = 2.3 mA; VCC = 2.3 V
-
-
0.31
V
IO = 3.1 mA; VCC = 2.3 V
-
-
0.44
V
IO = 2.7 mA; VCC = 3.0 V
-
-
0.31
V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.44
V
II
input leakage current
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
0.1
A
IOFF
power-off leakage current
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
0.2
A
IOFF
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
-
-
0.2
A
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
-
-
0.5
A
ICC
additional supply current
VI = VCC  0.6 V; IO = 0 A;
VCC = 3.3 V
-
-
40
A
CI
input capacitance
VCC = 0 V to 3.6 V; VI = GND or VCC
-
1.1
-
pF
CO
output capacitance
VO = GND; VCC = 0 V
-
1.7
-
pF
74AUP2G98
Product data sheet
[1]
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 2 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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74AUP2G98
NXP Semiconductors
Low-power dual PCB configurable multiple function gate
Table 8.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 40 C to +85 C
VOH
VOL
HIGH-level output voltage
LOW-level output voltage
VI = VT+ or VT
IO = 20 A; VCC = 0.8 V to 3.6 V
VCC  0.1
-
-
V
IO = 1.1 mA; VCC = 1.1 V
0.7  VCC
-
-
V
IO = 1.7 mA; VCC = 1.4 V
1.03
-
-
V
IO = 1.9 mA; VCC = 1.65 V
1.30
-
-
V
IO = 2.3 mA; VCC = 2.3 V
1.97
-
-
V
IO = 3.1 mA; VCC = 2.3 V
1.85
-
-
V
IO = 2.7 mA; VCC = 3.0 V
2.67
-
-
V
IO = 4.0 mA; VCC = 3.0 V
2.55
-
-
V
IO = 20 A; VCC = 0.8 V to 3.6 V
-
-
0.1
V
IO = 1.1 mA; VCC = 1.1 V
-
-
0.3  VCC
V
IO = 1.7 mA; VCC = 1.4 V
-
-
0.37
V
VI = VT+ or VT
IO = 1.9 mA; VCC = 1.65 V
-
-
0.35
V
IO = 2.3 mA; VCC = 2.3 V
-
-
0.33
V
IO = 3.1 mA; VCC = 2.3 V
-
-
0.45
V
IO = 2.7 mA; VCC = 3.0 V
-
-
0.33
V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.45
V
II
input leakage current
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
0.5
A
IOFF
power-off leakage current
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
0.5
A
IOFF
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
-
-
0.6
A
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
-
-
0.9
A
ICC
additional supply current
VI = VCC  0.6 V; IO = 0 A;
VCC = 3.3 V
-
-
50
A
74AUP2G98
Product data sheet
[1]
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Rev. 2 — 2 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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74AUP2G98
NXP Semiconductors
Low-power dual PCB configurable multiple function gate
Table 8.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 40 C to +125 C
VOH
HIGH-level output voltage
LOW-level output voltage
VOL
VI = VT+ or VT
IO = 20 A; VCC = 0.8 V to 3.6 V
VCC  0.11 -
-
V
IO = 1.1 mA; VCC = 1.1 V
0.6  VCC
-
-
V
IO = 1.7 mA; VCC = 1.4 V
0.93
-
-
V
IO = 1.9 mA; VCC = 1.65 V
1.17
-
-
V
IO = 2.3 mA; VCC = 2.3 V
1.77
-
-
V
IO = 3.1 mA; VCC = 2.3 V
1.67
-
-
V
IO = 2.7 mA; VCC = 3.0 V
2.40
-
-
V
IO = 4.0 mA; VCC = 3.0 V
2.30
-
-
V
IO = 20 A; VCC = 0.8 V to 3.6 V
-
-
0.11
V
IO = 1.1 mA; VCC = 1.1 V
-
-
0.33  VCC V
IO = 1.7 mA; VCC = 1.4 V
-
-
0.41
VI = VT+ or VT
V
IO = 1.9 mA; VCC = 1.65 V
-
-
0.39
V
IO = 2.3 mA; VCC = 2.3 V
-
-
0.36
V
IO = 3.1 mA; VCC = 2.3 V
-
-
0.50
V
IO = 2.7 mA; VCC = 3.0 V
-
-
0.36
V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.50
V
II
input leakage current
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
0.75
A
IOFF
power-off leakage current
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
0.75
A
IOFF
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
-
-
0.75
A
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
-
-
1.4
A
ICC
additional supply current
VI = VCC  0.6 V; IO = 0 A;
VCC = 3.3 V
-
-
75
A
[1]
[1]
One input at VCC  0.6 V, other input at VCC or GND.
74AUP2G98
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 2 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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74AUP2G98
NXP Semiconductors
Low-power dual PCB configurable multiple function gate
11. Dynamic characteristics
Table 9.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 13.
Symbol Parameter
Tamb = 25 C
Conditions
Tamb = 40 C to +125 C Unit
Min
Typ[1]
Max
Min
-
23.3
-
-
-
-
ns
Max
Max
(85 C) (125 C)
CL = 5 pF
tpd
propagation delay nA, nB, nC to nY; see Figure 12
[2]
VCC = 0.8 V
VCC = 1.1 V to 1.3 V
2.9
6.7
12.9
2.7
13.2
13.4
ns
VCC = 1.4 V to 1.6 V
2.4
4.8
7.7
2.4
8.3
8.7
ns
VCC = 1.65 V to 1.95 V
2.2
4.0
6.3
1.9
7.0
7.4
ns
VCC = 2.3 V to 2.7 V
2.0
3.2
4.6
1.8
5.2
5.4
ns
VCC = 3.0 V to 3.6 V
1.9
2.9
4.0
1.6
4.2
4.4
ns
-
27.1
-
-
-
-
ns
CL = 10 pF
tpd
propagation delay nA, nB, nC to nY; see Figure 12
[2]
VCC = 0.8 V
VCC = 1.1 V to 1.3 V
3.3
7.6
14.5
3.0
15.1
15.3
ns
VCC = 1.4 V to 1.6 V
2.7
5.4
8.8
2.8
9.5
9.9
ns
VCC = 1.65 V to 1.95 V
2.5
4.6
7.2
2.3
8.0
8.4
ns
VCC = 2.3 V to 2.7 V
2.4
3.8
5.3
2.2
5.9
6.2
ns
VCC = 3.0 V to 3.6 V
2.3
3.5
4.7
2.0
4.9
5.2
ns
-
30.6
-
-
-
-
ns
CL = 15 pF
tpd
propagation delay nA, nB, nC to nY; see Figure 12
[2]
VCC = 0.8 V
VCC = 1.1 V to 1.3 V
3.6
8.4
16.1
3.3
16.9
17.2
ns
VCC = 1.4 V to 1.6 V
3.0
6.0
9.7
3.1
10.5
11.0
ns
VCC = 1.65 V to 1.95 V
2.8
5.1
7.9
2.5
8.9
9.3
ns
VCC = 2.3 V to 2.7 V
2.7
4.2
5.9
2.5
6.6
7.0
ns
VCC = 3.0 V to 3.6 V
2.5
3.9
5.2
2.2
5.5
5.8
ns
-
38.7
-
-
-
-
ns
VCC = 1.1 V to 1.3 V
4.5
10.7
21.1
4.1
22.0
22.4
ns
VCC = 1.4 V to 1.6 V
3.8
7.6
12.3
3.8
13.5
14.2
ns
VCC = 1.65 V to 1.95 V
3.5
6.3
10.1
3.1
11.3
11.9
ns
VCC = 2.3 V to 2.7 V
3.4
5.3
7.5
3.2
8.4
8.9
ns
VCC = 3.0 V to 3.6 V
3.2
5.0
6.7
2.9
7.1
7.5
ns
CL = 30 pF
tpd
propagation delay nA, nB, nC to nY; see Figure 12
VCC = 0.8 V
74AUP2G98
Product data sheet
[2]
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 2 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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74AUP2G98
NXP Semiconductors
Low-power dual PCB configurable multiple function gate
Table 9.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 13.
Symbol Parameter
Tamb = 25 C
Conditions
Tamb = 40 C to +125 C Unit
Min
Typ[1]
Max
Min
-
2.7
-
-
-
-
pF
VCC = 1.1 V to 1.3 V
-
2.9
-
-
-
-
pF
VCC = 1.4 V to 1.6 V
-
3.0
-
-
-
-
pF
VCC = 1.65 V to 1.95 V
-
3.2
-
-
-
-
pF
VCC = 2.3 V to 2.7 V
-
3.8
-
-
-
-
pF
VCC = 3.0 V to 3.6 V
-
4.4
-
-
-
-
pF
Max
Max
(85 C) (125 C)
CL = 5 pF, 10 pF, 15 pF and 30 pF
[1]
All typical values are measured at nominal VCC.
[2]
tpd is the same as tPLH and tPHL
[3]
[3]
power dissipation fi = 1 MHz; VI = GND to VCC
capacitance
VCC = 0.8 V
CPD
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL  VCC2  fo) = sum of the outputs.
12. Waveforms
9,
Q$Q%Q&LQSXW
90
90
*1'
W3+/
W3/+
92+
90
Q<RXWSXW
90
92/
W3/+
W3+/
92+
Q<RXWSXW
90
92/
90
DDD
Measurement points are given in Table 10.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 12. Input nA, nB and nC to output nY propagation delay times.
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Table 10.
Measurement points
Supply voltage
Output
Input
VCC
VM
VM
VI
tr = tf
0.8 V to 3.6 V
0.5VCC
0.5  VCC
0.5  VCC
 3.0 ns
9&&
9(;7
Nȍ
*
9,
92
'87
&/
57
5/
DDF
Test data is given in Table 11.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 13. Test circuit for measuring switching times
Table 11.
Test data
Supply voltage
Load
VEXT
RL[1]
VCC
CL
0.8 V to 3.6 V
5 pF, 10 pF, 15 pF and 30 pF 5 k or 1 M
[1]
tPLH, tPHL
tPZH, tPHZ
tPZL, tPLZ
open
GND
2VCC
For measuring enable and disable times, RL = 5 k, for measuring propagation delays, setup and hold times and pulse width RL = 1
M.
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13. Transfer characteristics
Table 12. Transfer characteristics
Voltages are referenced to GND (ground = 0 V; for test circuit, see Figure 13.
Symbol Parameter
VT+
Tamb = 25 C
Conditions
positive-going
see Figure 14 and Figure 15
threshold voltage
VCC = 0.8 V
VCC = 1.1 V
VT
VH
Tamb = 40 C to +125 C
Unit
Min
Typ
Max
Min
Max
(85 C)
Max
(125 C)
0.30
-
0.60
0.30
0.60
0.62
V
0.53
-
0.90
0.53
0.90
0.92
V
VCC = 1.4 V
0.74
-
1.11
0.74
1.11
1.13
V
VCC = 1.65 V
0.91
-
1.29
0.91
1.29
1.31
V
VCC = 2.3 V
1.37
-
1.77
1.37
1.77
1.80
V
VCC = 3.0 V
1.88
-
2.29
1.88
2.29
2.32
V
0.10
-
0.60
0.10
0.60
0.60
V
VCC = 1.1 V
0.26
-
0.65
0.26
0.65
0.65
V
VCC = 1.4 V
0.39
-
0.75
0.39
0.75
0.75
V
negative-going
see Figure 14 and Figure 15
threshold voltage
VCC = 0.8 V
VCC = 1.65 V
0.47
-
0.84
0.47
0.84
0.84
V
VCC = 2.3 V
0.69
-
1.04
0.69
1.04
1.04
V
VCC = 3.0 V
0.88
-
1.24
0.88
1.24
1.24
V
(VT+  VT); see Figure 14, Figure 15, Figure 16 and Figure 17
hysteresis
voltage
VCC = 0.8 V
0.07
-
0.50
0.07
0.50
0.50
V
VCC = 1.1 V
0.08
-
0.46
0.08
0.46
0.46
V
VCC = 1.4 V
0.18
-
0.56
0.18
0.56
0.56
V
VCC = 1.65 V
0.27
-
0.66
0.27
0.66
0.66
V
VCC = 2.3 V
0.53
-
0.92
0.53
0.92
0.92
V
VCC = 3.0 V
0.79
-
1.31
0.79
1.31
1.31
V
14. Waveforms transfer characteristics
92
9,
97
97
9+
92
9,
9+
97
97
Fig 14. Transfer characteristic
74AUP2G98
Product data sheet
PQD
PQD
VT+ and VT limits at 70 % and 20 %.
Fig 15. Definition of VT+, VT and VH
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001aad691
240
ICC
(μA)
160
80
0
0
0.4
0.8
1.2
1.6
2.0
VI (V)
Fig 16. Typical transfer characteristics; VCC = 1.8 V
001aad692
1200
ICC
(μA)
800
400
0
0
1.0
2.0
3.0
VI (V)
Fig 17. Typical transfer characteristics; VCC = 3.0 V
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15. Package outline
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Low-power dual PCB configurable multiple function gate
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74AUP2G98
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16. Abbreviations
Table 13.
Abbreviations
Acronym
Description
CDM
Charged Device Model
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
PCB
Printed-Circuit Board
17. Revision history
Table 14.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74AUP2G98 v.2
20151202
Product data sheet
-
74AUP2G98 v.1
Modifications:
74AUP2G98 v.1
74AUP2G98
Product data sheet
•
•
Maximum value temperature range TSSOP10 (74AUP2G98DP) changed from 85 C to 125 C.
Removed 74AUP2G98GM (SOT1049-3).
20141104
Product data sheet
-
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Rev. 2 — 2 December 2015
-
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18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74AUP2G98
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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20. Contents
1
2
3
4
5
6
6.1
6.2
7
7.1
8
9
10
11
12
13
14
15
16
17
18
18.1
18.2
18.3
18.4
19
20
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 4
Logic configurations . . . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . 10
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Transfer characteristics . . . . . . . . . . . . . . . . . 13
Waveforms transfer characteristics. . . . . . . . 13
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18
Legal information. . . . . . . . . . . . . . . . . . . . . . . 19
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Contact information. . . . . . . . . . . . . . . . . . . . . 20
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 2 December 2015
Document identifier: 74AUP2G98