ATMEL AT89C51ED2

Features
• 80C52 Compatible
•
•
•
•
•
•
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•
•
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•
– 8051 Instruction Compatible
– Six 8-bit I/O Ports (64 Pins or 68 Pins Versions)
– Four 8-bit I/O Ports (44 Pins Version)
– Three 16-bit Timer/Counters
– 256 Bytes Scratch Pad RAM
– 9 Interrupt Sources with 4 Priority Levels
Integrated Power Monitor (POR/PFD) to Supervise Internal Power Supply
ISP (In-System Programming) Using Standard VCC Power Supply
2048 Bytes Boot ROM Contains Low Level Flash Programming Routines and a Default
Serial Loader
High-speed Architecture
– In Standard Mode:
40 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution)
60 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)
– In X2 mode (6 Clocks/machine cycle)
20 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution)
30 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)
64K Bytes On-chip Flash Program/Data Memory
– Byte and Page (128 Bytes) Erase and Write
– 100k Write Cycles
On-chip 1792 bytes Expanded RAM (XRAM)
– Software Selectable Size (0, 256, 512, 768, 1024, 1792 Bytes)
– 768 Bytes Selected at Reset for T89C51RD2 Compatibility
On-chip 2048 Bytes EEPROM Block for Data Storage (AT89C51ED2 Only)
– 100K Write Cycles
Dual Data Pointer
Variable Length MOVX for Slow RAM/Peripherals
Improved X2 Mode with Independent Selection for CPU and Each Peripheral
Keyboard Interrupt Interface on Port 1
SPI Interface (Master/Slave Mode)
8-bit Clock Prescaler
16-bit Programmable Counter Array
– High Speed Output
– Compare/Capture
– Pulse Width Modulator
– Watchdog Timer Capabilities
Asynchronous Port Reset
Full-duplex Enhanced UART with Dedicated Internal Baud Rate Generator
Low EMI (Inhibit ALE)
Hardware Watchdog Timer (One-time Enabled with Reset-Out), Power-off Flag
Power Control Modes: Idle Mode, Power-down Mode
Single Range Power Supply: 2.7V to 5.5V
Industrial Temperature Range (-40 to +85°C)
Packages: PLCC44, VQFP44, PLCC68, VQFP64, PDIL40
8-bit Flash
Microcontroller
AT89C51RD2
AT89C51ED2
Description
AT89C51RD2/ED2 is high performance CMOS Flash version of the 80C51 CMOS single chip 8-bit microcontroller. It contains a 64-Kbyte Flash memory block for code and
for data.
The 64-Kbytes Flash memory can be programmed either in parallel mode or in serial
mode with the ISP capability or with software. The programming voltage is internally
generated from the standard VCC pin.
Rev. 4235E–8051–04/04
1
The AT89C51RD2/ED2 retains all of the features of the Atmel 80C52 with 256 bytes of
internal RAM, a 9-source 4-level interrupt controller and three timer/counters. The
AT89C51ED2 provides 2048 bytes of EEPROM for nonvolatile data storage.
In addition, the AT89C51RD2/ED2 has a Programmable Counter Array, an XRAM of
1792 bytes, a Hardware Watchdog Timer, SPI interface, Keyboard, a more versatile
serial channel that facilitates multiprocessor communication (EUART) and a speed
improvement mechanism (X2 Mode).
The fully static design of the AT89C51RD2/ED2 allows to reduce system power consumption by bringing the clock frequency down to any value, including DC, without loss
of data.
The AT89C51RD2/ED2 has 2 software-selectable modes of reduced activity and an 8bit clock prescaler for further reduction in power consumption. In the Idle mode the CPU
is frozen while the peripherals and the interrupt system are still operating. In the Powerdown mode the RAM is saved and all other functions are inoperative.
The added features of the AT89C51RD2/ED2 make it more powerful for applications
that need pulse width modulation, high speed I/O and counting capabilities such as
alarms, motor control, corded phones, and smart card readers.
Table 1. Memory Size and I/O Pins
2
Package
Flash (Bytes)
XRAM (Bytes)
Total RAM (Bytes)
I/O
PLCC44/VQFP44/DIL40
64K
1792
2048
34
PLCC68/VQFP64
64K
1792
2048
50
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
Block Diagram
(2) (2)
XTALA1
Flash
64K x 8
RAM
256x8
XRAM
PCA
1792 x 8
Keyboard
T2
T2EX
(1) (1)
(1)
EUART
PCA
ECI
VSS
VCC
TxD
RxD
Figure 1. Block Diagram
(1)
Timer2
(1)
Keyboard
XTALA2
C51
CORE
Watch
-dog
EEPROM*
2K x 8
(AT89C51ED2)
IB-bus
CPU
ALE/ PROG
PSEN
EA
Timer 0
Timer 1
(2)
INT
Ctrl
External Bus
SPI
BOOT Regulator
2K x 8 POR / PFD
ROM
MISO
MOSI
SCK
SS
P5
P4
P3
P2
P1
(1) (1) (1)(1)
P0
INT1
(2) (2)
T1
(2) (2)
INT0
Port 0 Port 1Port 2 Port 3 Port4 Port 5
RESET
WR
Parallel I/O Ports &
(2)
T0
RD
(1): Alternate function of Port 1
(2): Alternate function of Port 3
3
4235E–8051–04/04
SFR Mapping
The Special Function Registers (SFRs) of the AT89C51RD2/ED2 fall into the following
categories:
•
4
C51 core registers: ACC, B, DPH, DPL, PSW, SP
•
I/O port registers: P0, P1, P2, P3, PI2
•
Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2,
RCAP2L, RCAP2H
•
Serial I/O port registers: SADDR, SADEN, SBUF, SCON
•
PCA (Programmable Counter Array) registers: CCON, CCAPMx, CL, CH, CCAPxH,
CCAPxL (x: 0 to 4)
•
Power and clock control registers: PCON
•
Hardware Watchdog Timer registers: WDTRST, WDTPRG
•
Interrupt system registers: IE0, IPL0, IPH0, IE1, IPL1, IPH1
•
Keyboard Interface registers: KBE, KBF, KBLS
•
SPI registers: SPCON, SPSTR, SPDAT
•
BRG (Baud Rate Generator) registers: BRL, BDRCON
•
Clock Prescaler register: CKRL
•
Others: AUXR, AUXR1, CKCON0, CKCON1
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
Table 2. C51 Core SFRs
Mnemonic
Add
Name
ACC
E0h
Accumulator
B
F0h
B Register
PSW
D0h
Program Status Word
SP
81h
Stack Pointer
DPL
82h
Data Pointer Low Byte
DPH
83h
Data Pointer High Byte
7
6
5
4
3
2
1
0
CY
AC
F0
RS1
RS0
OV
F1
P
7
6
5
4
3
2
1
0
SMOD1
SMOD0
-
POF
GF1
GF0
PD
IDL
Table 3. System Management SFRs
Mnemonic
Add
Name
PCON
87h
Power Control
AUXR
8Eh
Auxiliary Register 0
DPU
-
M0
XRS2
XRS1
XRS0
AUXR1
A2h
Auxiliary Register 1
-
-
ENBOOT
-
GF3
0
-
DPS
CKRL
97h
Clock Reload Register
-
-
-
-
-
-
-
-
CKCKON0
8Fh
Clock Control Register 0
-
WDTX2
PCAX2
SIX2
T2X2
T1X2
T0X2
X2
CKCKON1
AFh
Clock Control Register 1
-
-
-
-
-
-
-
SPIX2
EXTRAM
AO
Table 4. Interrupt SFRs
Mnemonic
Add
Name
7
6
5
4
3
2
1
0
IEN0
A8h
Interrupt Enable Control 0
EA
EC
ET2
ES
ET1
EX1
ET0
EX0
IEN1
B1h
Interrupt Enable Control 1
-
-
-
-
-
ESPI
IPH0
B7h
Interrupt Priority Control High 0
-
PPCH
PT2H
PHS
PT1H
PX1H
PT0H
PX0H
IPL0
B8h
Interrupt Priority Control Low 0
-
PPCL
PT2L
PLS
PT1L
PX1L
PT0L
PX0L
IPH1
B3h
Interrupt Priority Control High 1
-
-
-
-
-
SPIH
KBDH
IPL1
B2h
Interrupt Priority Control Low 1
-
-
-
-
-
SPIL
KBDL
7
6
5
4
3
2
KBD
Table 5. Port SFRs
Mnemonic
Add
Name
P0
80h
8-bit Port 0
P1
90h
8-bit Port 1
P2
A0h
8-bit Port 2
P3
B0h
8-bit Port 3
P4
C0h
8-bit Port 4
1
0
5
4235E–8051–04/04
Table 5. Port SFRs
Mnemonic
Add
Name
P5
D8h
8-bit Port 5
P5
C7h
8-bit Port 5 (byte addressable)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Table 6. Timer SFRs
Mnemonic
Add
Name
TCON
88h
Timer/Counter 0 and 1 Control
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
TMOD
89h
Timer/Counter 0 and 1 Modes
GATE1
C/T1#
M11
M01
GATE0
C/T0#
M10
M00
TL0
8Ah
Timer/Counter 0 Low Byte
TH0
8Ch
Timer/Counter 0 High Byte
TL1
8Bh
Timer/Counter 1 Low Byte
TH1
8Dh
Timer/Counter 1 High Byte
WDTRST
A6h
WatchDog Timer Reset
WDTPRG
A7h
WatchDog Timer Program
-
-
-
-
-
WTO2
WTO1
WTO0
T2CON
C8h
Timer/Counter 2 control
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2#
CP/RL2#
T2MOD
C9h
Timer/Counter 2 Mode
-
-
-
-
-
-
T2OE
DCEN
RCAP2H
CBh
Timer/Counter 2 Reload/Capture
High Byte
RCAP2L
CAh
Timer/Counter 2 Reload/Capture
Low Byte
TH2
CDh
Timer/Counter 2 High Byte
TL2
CCh
Timer/Counter 2 Low Byte
Table 7. PCA SFRs
Mnemo
-nic
Add Name
7
6
CCON
D8h
PCA Timer/Counter Control
CF
CR
CMOD
D9h
PCA Timer/Counter Mode
CIDL
WDTE
CL
E9h
PCA Timer/Counter Low Byte
CH
F9h
PCA Timer/Counter High Byte
5
4
3
2
1
0
CCF4
CCF3
CCF2
CCF1
CCF0
CPS1
CPS0
ECF
CCAPM0 DAh PCA Timer/Counter Mode 0
ECOM0
CAPP0
CAPN0
MAT0
TOG0
PWM0
ECCF0
CCAPM1 DBh PCA Timer/Counter Mode 1
ECOM1
CAPP1
CAPN1
MAT1
TOG1
PWM1
ECCF1
CCAPM2 DCh PCA Timer/Counter Mode 2
ECOM2
CAPP2
CAPN2
MAT2
TOG2
PWM2
ECCF2
CCAPM3 DDh PCA Timer/Counter Mode 3
ECOM3
CAPP3
CAPN3
MAT3
TOG3
PWM3
ECCF3
CCAPM4 DEh PCA Timer/Counter Mode 4
ECOM4
CAPP4
CAPN4
MAT4
TOG4
PWM4
ECCF4
6
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
Table 7. PCA SFRs (Continued)
Mnemo
-nic
Add Name
7
6
5
4
3
2
1
0
CCAP0H FAh
PCA Compare Capture Module 0 H CCAP0H7 CCAP0H6 CCAP0H5 CCAP0H4 CCAP0H3 CCAP0H2 CCAP0H1 CCAP0H0
CCAP1H FBh
PCA Compare Capture Module 1 H CCAP1H7 CCAP1H6 CCAP1H5 CCAP1H4 CCAP1H3 CCAP1H2 CCAP1H1 CCAP1H0
CCAP2H FCh PCA Compare Capture Module 2 H CCAP2H7 CCAP2H6 CCAP2H5 CCAP2H4 CCAP2H3 CCAP2H2 CCAP2H1 CCAP2H0
CCAP3H FDh PCA Compare Capture Module 3 H CCAP3H7 CCAP3H6 CCAP3H5 CCAP3H4 CCAP3H3 CCAP3H2 CCAP3H1 CCAP3H0
CCAP4H FEh
PCA Compare Capture Module 4 H CCAP4H7 CCAP4H6 CCAP4H5 CCAP4H4 CCAP4H3 CCAP4H2 CCAP4H1 CCAP4H0
CCAP0L
EAh PCA Compare Capture Module 0 L CCAP0L7 CCAP0L6
CCAP0L5
CCAP0L4 CCAP0L3 CCAP0L2 CCAP0L1
CCAP0L0
CCAP1L
EBh PCA Compare Capture Module 1 L CCAP1L7 CCAP1L6
CCAP1L5
CCAP1L4 CCAP1L3 CCAP1L2 CCAP1L1
CCAP1L0
CCAP2L
ECh PCA Compare Capture Module 2 L CCAP2L7 CCAP2L6
CCAP2L5
CCAP2L4 CCAP2L3 CCAP2L2 CCAP2L1
CCAP2L0
CCAP3L
EDh PCA Compare Capture Module 3 L CCAP3L7 CCAP3L6
CCAP3L5
CCAP3L4 CCAP3L3 CCAP3L2 CCAP3L1
CCAP3L0
CCAP4L
EEh PCA Compare Capture Module 4 L CCAP4L7 CCAP4L6
CCAP4L5
CCAP4L4 CCAP4L3 CCAP4L2 CCAP4L1
CCAP4L0
Table 8. Serial I/O Port SFRs
Mnemonic
Add
Name
SCON
98h
Serial Control
SBUF
99h
Serial Data Buffer
SADEN
B9h
Slave Address Mask
SADDR
A9h
Slave Address
BDRCON
9Bh
Baud Rate Control
BRL
9Ah
Baud Rate Reload
7
6
5
4
3
2
1
0
FE/SM0
SM1
SM2
REN
TB8
RB8
TI
RI
BRR
TBCK
RBCK
SPD
SRC
Table 9. SPI Controller SFRs
Mnemonic
Add
Name
7
6
5
4
3
2
1
0
SPCON
C3h
SPI Control
SPR2
SPEN
SSDIS
MSTR
CPOL
CPHA
SPR1
SPR0
SPSTA
C4h
SPI Status
SPIF
WCOL
SSERR
MODF
SPDAT
C5h
SPI Data
SPD7
SPD6
SPD5
SPD4
SPD3
SPD2
SPD1
SPD0
7
6
5
4
3
2
1
0
Table 10. Keyboard Interface SFRs
Mnemonic
Add
Name
KBLS
9Ch
Keyboard Level Selector
KBLS7
KBLS6
KBLS5
KBLS4
KBLS3
KBLS2
KBLS1
KBLS0
KBE
9Dh
Keyboard Input Enable
KBE7
KBE6
KBE5
KBE4
KBE3
KBE2
KBE1
KBE0
KBF
9Eh
Keyboard Flag Register
KBF7
KBF6
KBF5
KBF4
KBF3
KBF2
KBF1
KBF0
5
4
3
2
1
0
EEE
EEBUSY
Table 11. EEPROM data Memory SFR (AT89C51ED2 only)
Mnemonic
Add
Name
EECON
D2h
EEPROM Data Control
7
6
7
4235E–8051–04/04
Table 12 shows all SFRs with their address and their reset value.
Table 12. SFR Mapping
Bit
Addressable
0/8
F8h
F0h
E8h
1/9
2/A
3/B
4/C
5/D
6/E
PI2
CH
CCAP0H
CCAP1H
CCAP2H
CCAP3H
CCAP4H
XXXX XX11
0000 0000
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
P5 bit
addressable
CL
CCAP0L
CCAP1L
CCAP2L
CCAP3L
CCAP4L
0000 0000
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
E7h
CMOD
CCAPM0
CCAPM1
CCAPM2
CCAPM3
CCAPM4
00XX X000
X000 0000
X000 0000
X000 0000
X000 0000
X000 0000
D0h
PSW
0000 0000
FCON
XXXX 0000
EECON
xxxx xx00
C8h
T2CON
0000 0000
T2MOD
XXXX XX00
RCAP2L
0000 0000
B8h
B0h
A8h
A0h
98h
90h
88h
80h
EFh
ACC
0000 0000
CCON
C0h
FFh
F7h
00X0 0000
D8h
7/F
B
0000 0000
1111 1111
E0h
Non Bit Addressable
D7h
RCAP2H
0000 0000
TL2
0000 0000
TH2
0000 0000
P4
SPCON
SPSTA
SPDAT
1111 1111
0001 0100
0000 0000
XXXX XXXX
IPL0
SADEN
X000 000
0000 0000
DFh
CFh
P5 byte
Addressable
C7h
1111 1111
BFh
P3
IEN1
IPL1
IPH1
IPH0
1111 1111
XXXX X000
XXXX X000
XXXX X111
X000 0000
IEN0
SADDR
CKCON1
0000 0000
0000 0000
XXXX XXX0
P2
AUXR1
WDTRST
WDTPRG
1111 1111
0XXX X0X0
XXXX XXXX
XXXX X000
SCON
SBUF
BRL
BDRCON
KBLS
KBE
KBF
0000 0000
XXXX XXXX
0000 0000
XXX0 0000
0000 0000
0000 0000
0000 0000
P1
CKRL
1111 1111
TCON
TMOD
TL0
TL1
TH0
TH1
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
P0
1111 1111
SP
0000 0111
DPL
0000 0000
DPH
0000 0000
0/8
1/9
2/A
3/B
AUXR
XX00 1000
CKCON0
0000 0000
PCON
00X1 0000
4/C
5/D
6/E
AFh
A7h
9Fh
1111 1111
0000 0000
B7h
97h
8Fh
87h
7/F
reserved
8
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
Pin Configurations
P0.2/AD2
P0.3/AD3
P0.1/AD1
P0.0/AD0
VCC
P1.0/T2
NIC*
P1.1/T2EX/SS
P1.2/ECI
P1.3/CEX0
P1.4/CEX1
Figure 2. Pin Configurations
6 5 4 3 2 1 44 43 42 41 40
P1.5/CEX2/MISO
39
38
P0.4/AD4
P1.6/CEX3/SCK
7
8
P1.7/CEx4/MOSI
9
37
P0.6/AD6
RST
10
36
P0.7/AD7
P3.0/RxD
11
12
35
34
EA
NIC*
AT89C51RD2/ED2
P0.5/AD5
NIC*
P3.1/TxD
13
33
ALE/PROG
P3.2/INT0
P3.3/INT1
14
15
32
31
PSEN
P3.4/T0
P3.5/T1
16
30
P2.6/A14
17
29
P2.5/A13
PLCC44
P2.7/A15
P3.6/WR
26
25
PSEN
9
10
24
P2.6/A14
11
23
P2.5/A13
P0.7/AD7
RST
EA
ALE/PROG
P3.0/RxD
5
NIC*
6
PSEN
P2.7/AD15
P2.6/AD14
P2.5/AD13
P3.1/TxD
P3.2/INT0
7
8
P3.3/INT1
16
27
26
25
P2.4/AD12
P2.3/AD11
17
18
24
23
P2.2/AD10
XTAL1
19
20
22
21
P2.1/AD9
P2.0/AD8
P0.3/AD3
ALE/PROG
32
14
15
P0.2/AD2
27
9
3
4
28
P0.1/AD1
EA
P0.6/AD6
13
P0.0/AD0
P0.7/AD7
29
28
33
P1.6/CEX3/SCK
P1.7/CEX4/MOSI
31
11 AT89C51ED2 30
PDIL40 29
12
VCC
P0.6/AD6
30
P0.5/AD5
10
P1.0/T2
NIC*
P2.2/A10
P2.1/A9
NIC*
P2.0/A8
VSS
XTAL1
P2.3/A11
P2.4/A12
31
34
P3.7/RD
XTAL2
VSS
P0.4/AD4
2
7
8
P3.4/T0
P3.5/T1
AT89C51RD2/ED2
VQFP44 1.4
P0.5/AD5
NIC*
P2.7/A15
12 13 14 15 16 17 18 19 20 21 22
P2.4/A12
P3.5/T1
33
32
1
P2.3/A11
P3.4/T0
44 43 42 41 40 39 38 37 36 35 34
P1.5/CEX2/MISO
P2.2/A10
P3.2/INT0
P3.3/INT1
P0.3/AD3
P0.4/AD4
P2.1/A9
P3.0/RxD
P3.1/TxD
36
35
NIC*
P2.0/A8
P1.7CEX4/MOSI
RST
5
P1.1/T2EX/SS
6
P0.1/AD1
P0.2/AD2
VSS
P1.5/CEX2/MISO
P1.6/CEX3/SCK
37
P1.2/ECI
3
4
XTAL1
P1.2/ECI
P1.3CEX0
P1.4/CEX1
P1.3/CEX0
P0.0/AD0
XTAL2
VCC
39
38
P1.4/CEX1
40
2
P3.7/RD
1
P3.6/WR
P1.0/T2
P1.1/T2EX/SS
XTAL2
P3.7/RD
P3.6/WR
18 19 20 21 22 23 24 25 26 27 28
9
4235E–8051–04/04
P0.4/AD4
P5.4
P5.3
P0.5/AD5
P0.6/AD6
NIC
P0.7/AD7
EA
NIC
ALE
PSEN
NIC
P2.7/A15
P2.6/A14
P5.2
P5.1
P2.5/A13
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
AT89C51ED2
PLCC68
P5.0
P2.4/A12
P2.3/A11
P4.7
P2.2/A10
P2.1/A9
P2.0/A8
P4.6
NIC
VSS
P4.5
XTAL1
XTAL2
P3.7/RD
P4.4
P3.6/WR
P4.3
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
P0.4/AD4
P5.4
P5.3
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
NIC
ALE
PSEN#
P2.7/A15
P2.6/A14
P5.2
P5.1
P2.5/A13
P5.0
P1.5/CEX2/MISO
P1.6/CEX3/SCK
P1.7/CEX4/MOSI
RST
NIC
NIC
NIC
P3.0/RxD
NIC
NIC
NIC
NIC
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
P5.5
P0.3/AD3
P0.2/AD2
P5.6
P0.1/AD1
P0.0/AD0
P5.7
VCC
NIC
P1.0/T2
P4.0
P1.1/T2EX/SS
P1.2/ECI
P1.3/CEX0
P4.1
P1.4/CEX1
P4.2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AT89C51ED2
VQFP64
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P2.4/A12
P2.3/A11
P4.7
P2.2/A10
P2.1/A9
P2.0/A8
P4.6
NIC
VSS
P4.5
XTAL1
XTAL2
P3.7/RD
P4.4
P3.6/WR
P4.3
P4.2
P1.5/CEX2/MISO
P1.6/CEX3/SCK
P1.7/A17/CEX4/MOSI
RST
NIC
NIC
NIC
P3.0/RxD
NIC
NIC
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P5.5
P0.3/AD3
P0.2/AD2
P5.6
P0.1/AD1
P0.0/AD0
P5.7
VCC
NIC
P1.0/T2
P4.0
P1.1/T2EX/SS
P1.2/ECI
P1.3/CEX0
P4.1
P1.4/CEX1
NIC: Not Internaly Connected
10
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
Table 13. Pin Description
Pin Number
Type
Mnemonic
PLCC44 VQFP44
PLCC68
VQFP64
PDIL40
Name and Function
VSS
22
16
51
40
20
I
Ground: 0V reference
VCC
44
38
17
8
40
I
Power Supply: This is the power supply voltage for normal, idle and
power-down operation
P0.0 - P0.7
43 - 36
P1.0 - P1.7
2-9
37 - 30
40 - 44
1-3
15, 14,
12, 11,
9,6, 5, 3
6, 5, 3,
2, 64,
61,60,59
19, 21,
22, 23,
25, 27,
28, 29
10, 12,
13, 14,
16, 18,
19, 20
I/O
32-39
1-8
I/O
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that
have 1s written to them float and can be used as high impedance inputs.
Port 0 must be polarized to VCC or V SS in order to prevent any parasitic
current consumption. Port 0 is also the multiplexed low-order address
and data bus during access to external program and data memory. In this
application, it uses strong internal pull-up when emitting 1s. Port 0 also
inputs the code bytes during EPROM programming. External pull-ups are
required during program verification during which P0 outputs the code
bytes.
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1
pins that have 1s written to them are pulled high by the internal pull-ups
and can be used as inputs. As inputs, Port 1 pins that are externally
pulled low will source current because of the internal pull-ups. Port 1 also
receives the low-order address byte during memory programming and
verification.
Alternate functions for AT89C51RD2/ED2 Port 1 include:
2
3
4
40
41
42
19
21
22
10
12
13
1
2
3
I/O
P1.0: Input/Output
I/O
T2 (P1.0): Timer/Counter 2 external count input/Clockout
I/O
P1.1: Input/Output
I
T2EX: Timer/Counter 2 Reload/Capture/Direction Control
I
SS: SPI Slave Select
I/O
I
5
6
7
43
44
1
23
25
27
14
16
18
4
5
6
P1.2: Input/Output
ECI: External Clock for the PCA
I/O
P1.3: Input/Output
I/O
CEX0: Capture/Compare External I/O for PCA module 0
I/O
P1.4: Input/Output
I/O
CEX1: Capture/Compare External I/O for PCA module 1
I/O
P1.5: Input/Output
I/O
CEX2: Capture/Compare External I/O for PCA module 2
I/O
MISO: SPI Master Input Slave Output line
When SPI is in master mode, MISO receives data from the slave peripheral. When SPI is in slave mode, MISO outputs data to the master controller.
8
2
28
19
7
I/O
P1.6: Input/Output
I/O
CEX3: Capture/Compare External I/O for PCA module 3
I/O
SCK: SPI Serial Clock
11
4235E–8051–04/04
Table 13. Pin Description (Continued)
Pin Number
Type
Mnemonic
PLCC44 VQFP44
9
3
PLCC68
VQFP64
PDIL40
29
20
8
Name and Function
I/O
P1.7: Input/Output:
I/O
CEX4: Capture/Compare External I/O for PCA module 4
I/O
MOSI: SPI Master Output Slave Input line
When SPI is in master mode, MOSI outputs data to the slave peripheral.
When SPI is in slave mode, MOSI receives data from the master controller.
XTALA1
21
15
49
38
19
I
XTALA 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits.
XTALA2
20
14
48
37
18
O
XTALA 2: Output from the inverting oscillator amplifier
I/O
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2
pins that have 1s written to them are pulled high by the internal pull-ups
and can be used as inputs. As inputs, Port 2 pins that are externally
pulled low will source current because of the internal pull-ups. Port 2
emits the high-order address byte during fetches from external program
memory and during accesses to external data memory that use 16-bit
addresses (MOVX @DPTR).In this application, it uses strong internal
pull-ups emitting 1s. During accesses to external data memory that use
8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.
P2.0 - P2.7
P3.0 - P3.7
P4.0 - P4.7
P5.0 - P5.7
RST
12
24 - 31
18 - 25
54, 55,
56, 58,
59, 61,
64, 65
43, 44,
45, 47,
48, 50,
53, 54
21-28
11,
13 - 19
5,
7 - 13
34, 39,
40, 41,
42, 43,
45, 47
25, 28,
29, 30,
31, 32,
34, 36
10-17
11
5
34
25
10
I
RXD (P3.0): Serial input port
13
7
39
28
11
O
TXD (P3.1): Serial output port
14
8
40
29
12
I
INT0 (P3.2): External interrupt 0
15
9
41
30
13
I
INT1 (P3.3): External interrupt 1
16
10
42
31
14
I
T0 (P3.4): Timer 0 external input
17
11
43
32
15
I
T1 (P3.5): Timer 1 external input
18
12
45
34
16
O
WR (P3.6): External data memory write strobe
19
13
47
36
17
O
RD (P3.7): External data memory read strobe
-
20, 24,
26, 44,
46, 50,
53, 57
11, 15,
17,33,
35,39,
42, 46
I/O
Port 4: Port 4 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3
pins that have 1s written to them are pulled high by the internal pull-ups
and can be used as inputs. As inputs, Port 3 pins that are externally
pulled low will source current because of the internal pull-ups.
-
60, 62,
63, 7, 8,
10, 13,
16
49, 51,
52, 62,
63, 1, 4,
7
I/O
Port 5: Port 5 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3
pins that have 1s written to them are pulled high by the internal pull-ups
and can be used as inputs. As inputs, Port 3 pins that are externally
pulled low will source current because of the internal pull-ups.
I
Reset: A high on this pin for two machine cycles while the oscillator is
running, resets the device. An internal diffused resistor to VSS permits a
power-on reset using only an external capacitor to VCC. This pin is an output when the hardware watchdog forces a system reset.
-
-
10
4
30
21
-
-
9
I/O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3
pins that have 1s written to them are pulled high by the internal pull-ups
and can be used as inputs. As inputs, Port 3 pins that are externally
pulled low will source current because of the internal pull-ups. Port 3 also
serves the special features of the 80C51 family, as listed below.
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
Table 13. Pin Description (Continued)
Pin Number
Type
Mnemonic
PLCC44 VQFP44
PLCC68
VQFP64
PDIL40
Name and Function
Address Latch Enable/Program Pulse: Output pulse for latching the
low byte of the address during an access to external memory. In normal
operation, ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the
oscillator frequency, and can be used for external timing or clocking. Note
that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG) during Flash programming. ALE can be disabled by setting SFR’s AUXR.0 bit. With this
bit set, ALE will be inactive during internal fetches.
ALE/PRO
G
33
27
68
56
30
O (I)
PSEN
32
26
67
55
29
O
Program Strobe ENable: The read strobe to external program memory.
When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are
skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory.
EA
35
29
2
58
31
I
External Access Enable: EA must be externally held low to enable the
device to fetch code from external program memory locations 0000H to
FFFFH. If security level 1 is programmed, EA will be internally latched on
Reset.
13
4235E–8051–04/04
Port Types
AT89C51RD2/ED2 I/O ports (P1, P2, P3, P4, P5) implement the quasi-bidirectional output that is common on the 80C51 and most of its derivatives. This output type can be
used as both an input and output without the need to reconfigure the port. This is possible because when the port outputs a logic high, it is weakly driven, allowing an external
device to pull the pin low. When the pin is pulled low, it is driven strongly and able to sink
a fairly large current. These features are somewhat similar to an open drain output
except that there are three pull-up transistors in the quasi-bidirectional output that serve
different purposes. One of these pull-ups, called the "weak" pull-up, is turned on whenever the port latch for the pin contains a logic 1. The weak pull-up sources a very small
current that will pull the pin high if it is left floating. A second pull-up, called the "medium"
pull-up, is turned on when the port latch for the pin contains a logic 1 and the pin itself is
also at a logic 1 level. This pull-up provides the primary source current for a quasi-bidirectional pin that is outputting a 1. If a pin that has a logic 1 on it is pulled low by an
external device, the medium pull-up turns off, and only the weak pull-up remains on. In
order to pull the pin low under these conditions, the external device has to sink enough
current to overpower the medium pull-up and take the voltage on the port pin below its
input threshold.
The third pull-up is referred to as the "strong" pull-up. This pull-up is used to speed up
low-to-high transitions on a quasi-bidirectional port pin when the port latch changes from
a logic 0 to a logic 1. When this occurs, the strong pull-up turns on for a brief time, two
CPU clocks, in order to pull the port pin high quickly. Then it turns off again.
The DPU bit (bit 7 in AUXR register) allows to disable the permanent weak pull up of all
ports when latch data is logical 0.
The quasi-bidirectional port configuration is shown in Figure 3.
Figure 3. Quasi-Bidirectional Output
2 CPU
Clock Delay
P
P
Strong
P
Weak
Medium
Pin
Port Latch
Data
N
DPU
AUXR.7
Input
Data
14
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
Oscillator
To optimize the power consumption and execution time needed for a specific task, an
internal prescaler feature has been implemented between the oscillator and the CPU
and peripherals.
Registers
Table 14. CKRL Register
CKRL – Clock Reload Register (97h)
7
6
5
4
3
2
1
0
CKRL7
CKRL6
CKRL5
CKRL4
CKRL3
CKRL2
CKRL1
CKRL0
Bit Number
Mnemonic
7:0
CKRL
Description
Clock Reload Register
Prescaler value
Reset Value = 1111 1111b
Not bit addressable
Table 15. PCON Register
PCON – Power Control Register (87h)
7
6
5
4
3
2
1
0
SMOD1
SMOD0
-
POF
GF1
GF0
PD
IDL
Bit Number
Bit Mnemonic
Description
7
SMOD1
Serial Port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
6
SMOD0
Serial Port Mode bit 0
Cleared to select SM0 bit in SCON register.
Set to select FE bit in SCON register.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
POF
Power-off Flag
Cleared by software to recognize the next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can
also be set by software.
3
GF1
General-purpose Flag
Cleared by software for general-purpose usage.
Set by software for general-purpose usage.
2
GF0
General-purpose Flag
Cleared by software for general-purpose usage.
Set by software for general-purpose usage.
1
PD
Power-down Mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
0
IDL
Idle Mode bit
Cleared by hardware when interrupt or reset occurs.
Set to enter idle mode.
Reset Value = 00X1 0000b Not bit addressable
15
4235E–8051–04/04
Functional Block Diagram
Figure 4. Functional Oscillator Block Diagram
Reload
Reset
CKRL
FOSC
Xtal1
Osc
Xtal2
1
:2
0
8-bit
Prescaler-Divider
1
CLK
Periph
X2
0
CKCON0
Peripheral Clock
CLK
CPU
CPU Clock
Idle
CKRL = 0xFF?
Prescaler Divider
•
A hardware RESET puts the prescaler divider in the following state:
•
•
CKRL = FFh: FCLK CPU = FCLK PERIPH = FOSC/2 (Standard C51 feature)
Any value between FFh down to 00h can be written by software into CKRL register
in order to divide frequency of the selected oscillator:
•
CKRL = 00h: minimum frequency
FCLK CPU = FCLK PERIPH = FOSC/1020 (Standard Mode)
FCLK CPU = FCLK PERIPH = FOSC/510 (X2 Mode)
•
CKRL = FFh: maximum frequency
FCLK CPU = FCLK PERIPH = FOSC/2 (Standard Mode)
FCLK CPU = FCLK PERIPH = FOSC (X2 Mode)
FCLK CPU and FCLK PERIPH
In X2 Mode, for CKRL<>0xFF:
F OSC
F CPU = F CLKPER IPH = ----------------------------------------------
2 × ( 255 – CKRL )
In X1 Mode, for CKRL<>0xFF then:
F OSC
F CPU = F CLKPER IPH = ----------------------------------------------
4 × ( 255 – CKRL )
16
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
Enhanced Features
In comparison to the original 80C52, the AT89C51RD2/ED2 implements some new features, which are:
•
X2 Feature
X2 option
•
Dual Data Pointer
•
Extended RAM
•
Programmable Counter Array (PCA)
•
Hardware Watchdog
•
SPI interface
•
4-level interrupt priority system
•
Power-off flag
•
ONCE mode
•
ALE disabling
•
Some enhanced features are also located in the UART and the Timer 2
The AT89C51RD2/ED2 core needs only 6 clock periods per machine cycle. This feature
called ‘X2’ provides the following advantages:
•
Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
•
Save power consumption while keeping same CPU power (oscillator power saving).
•
Save power consumption by dividing dynamically the operating frequency by 2 in
operating and idle modes.
•
Increase CPU power by 2 while keeping same crystal frequency.
In order to keep the original C51 compatibility, a divider by 2 is inserted between the
XTAL1 signal and the main clock input of the core (phase generator). This divider may
be disabled by software.
Description
The clock for the whole circuit and peripherals is first divided by two before being used
by the CPU core and the peripherals.
This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is
bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%.
Figure 5 shows the clock generation block diagram. X2 bit is validated on the rising edge
of the XTAL1 ÷ 2 to avoid glitches when switching from X2 to STD mode. Figure 6
shows the switching mode waveforms.
Figure 5. Clock Generation Diagram
CKRL
2
XTAL1
FXTAL
FOSC
XTAL1:2
0
1
8-bit Prescaler
FCLK CPU
FCLK PERIPH
X2
CKCON0
17
4235E–8051–04/04
Figure 6. Mode Switching Waveforms
XTAL1
XTAL1:2
X2 Bit
FOSC
CPU Clock
STD Mode
X2 Mode
STD Mode
The X2 bit in the CKCON0 register (see Table 16) allows a switch from 12 clock periods
per instruction to 6 clock periods and vice versa. At reset, the speed is set according to
X2 bit of Hardware Security Byte (HSB). By default, Standard mode is active. Setting the
X2 bit activates the X2 feature (X2 mode).
The T0X2, T1X2, T2X2, UartX2, PcaX2, and WdX2 bits in the CKCON0 register (Table
16) and SPIX2 bit in the CKCON1 register (see Table 17) allows a switch from standard
peripheral speed (12 clock periods per peripheral clock cycle) to fast peripheral speed (6
clock periods per peripheral clock cycle). These bits are active only in X2 mode.
18
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
Table 16. CKCON0 Register
CKCON0 - Clock Control Register (8Fh)
7
6
5
4
3
2
1
0
-
WDX2
PCAX2
SIX2
T2X2
T1X2
T0X2
X2
Bit
Number
7
Bit
Mnemonic Description
Reserved The values for this bit are indeterminite. Do not set this bit.
Watchdog Clock
6
WDX2
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Programmable Counter Array Clock
5
PCAX2
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
periods per peripheral clock cycle.
Enhanced UART Clock (Mode 0 and 2)
4
SIX2
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
periods per peripheral clock cycle.
Timer2 Clock
3
T2X2
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Timer1 Clock
2
T1X2
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
periods per peripheral clock cycle.
Timer0 Clock
1
T0X2
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
periods per peripheral clock cycle.
CPU Clock
0
X2
Cleared to select 12 clock periods per machine cycle (STD mode) for CPU and
all the peripherals. Set to select 6 clock periods per machine cycle (X2 mode)
and to enable the individual peripherals’X2’ bits. Programmed by hardware after
Power-up regarding Hardware Security Byte (HSB), Default setting, X2 is
cleared.
Reset Value = 0000 000’HSB. X2’b (See “Hardware Security Byte”)
Not bit addressable
19
4235E–8051–04/04
Table 17. CKCON1 Register
CKCON1 - Clock Control Register (AFh)
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
SPIX2
Bit
Number
Bit
Mnemonic Description
7
-
Reserved
6
-
Reserved
5
-
Reserved
4
-
Reserved
3
-
Reserved
2
-
Reserved
1
-
Reserved
0
SPIX2
SPI (This control bit is validated when the CPU clock X2 is set; when X2 is low,
this bit has no effect).
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Reset Value = XXXX XXX0b
Not bit addressable
20
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
Dual Data Pointer
Register (DPTR)
The additional data pointer can be used to speed up code execution and reduce code
size.
The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external
memory, and a single bit called DPS = AUXR1.0 (see Table 18) that allows the program
code to switch between them (Refer to Figure 7).
Figure 7. Use of Dual Pointer
External Data Memory
7
0
DPS
AUXR1(A2H)
DPTR1
DPTR0
DPH(83H) DPL(82H)
21
4235E–8051–04/04
Table 18. AUXR1 Register
AUXR1- Auxiliary Register 1(0A2h)
7
6
5
4
3
2
1
0
-
-
ENBOOT
-
GF3
0
-
DPS
Bit
Bit
Number
Mnemonic Description
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
ENBOOT
Enable Boot Flash
Cleared to disable boot ROM.
Set to map the boot ROM between F800h - 0FFFFh.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
3
GF3
2
0
Always cleared
1
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0
DPS
This bit is a general-purpose user flag.(1)
Data Pointer Selection
Cleared to select DPTR0.
Set to select DPTR1.
Reset Value = XXXX XX0X0b
Not bit addressable
Note:
1. Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3.
ASSEMBLY LANGUAGE
; Block move using dual data pointers
; Modifies DPTR0, DPTR1, A and PSW
; note: DPS exits opposite of entry state
; unless an extra INC AUXR1 is added
;
00A2
AUXR1 EQU 0A2H
;
0000 909000MOV DPTR,#SOURCE ; address of SOURCE
0003 05A2 INC AUXR1 ; switch data pointers
0005 90A000 MOV DPTR,#DEST ; address of DEST
0008 LOOP:
0008 05A2 INC AUXR1 ; switch data pointers
000A E0 MOVX A,@DPTR ; get a byte from SOURCE
000B A3 INC DPTR ; increment SOURCE address
000C 05A2 INC AUXR1 ; switch data pointers
000E F0 MOVX @DPTR,A ; write the byte to DEST
000F A3 INC DPTR ; increment DEST address
0010 70F6JNZ LOOP ; check for 0 terminator
0012 05A2 INC AUXR1 ; (optional) restore DPS
22
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1
SFR. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example,
only the fact that DPS is toggled in the proper sequence matters, not its actual value. In
other words, the block move routine works the same whether DPS is '0' or '1' on entry.
Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in
the opposite state.
23
4235E–8051–04/04
Expanded RAM
(XRAM)
The AT89C51RD2/ED2 provides additional on-chip random access memory (RAM)
space for increased data parameter handling and high level language usage.
AT89C51RD2/ED2 device haS expanded RAM in external data space configurable up
to 1792 bytes (see Table 19).
The AT89C51RD2/ED2 internal data memory is mapped into four separate segments.
The four segments are:
1. The Lower 128 bytes of RAM (addresses 00h to 7Fh) are directly and indirectly
addressable.
2. The Upper 128 bytes of RAM (addresses 80h to FFh) are indirectly addressable
only.
3. The Special Function Registers, SFRs, (addresses 80h to FFh) are directly
addressable only.
4. The expanded RAM bytes are indirectly accessed by MOVX instructions, and
with the EXTRAM bit cleared in the AUXR register (see Table 19).
The lower 128 bytes can be accessed by either direct or indirect addressing. The Upper
128 bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy
the same address space as the SFR. That means they have the same address, but are
physically separate from SFR space.
Figure 8. Internal and External Data Memory Address
0FFh or 6FFh
0FFh
0FFh
Upper
128 Bytes
Internal
RAM
Indirect Accesses
XRAM
80h
0FFFFh
Special
Function
Register
Direct Accesses
External
Data
Memory
80h
7Fh
Lower
128 Bytes
Internal
RAM
Direct or Indirect
Accesses
00
00
00FFh up to 06FFh
0000
When an instruction accesses an internal location above address 7Fh, the CPU knows
whether the access is to the upper 128 bytes of data RAM or to SFR space by the
addressing mode used in the instruction.
24
•
Instructions that use direct addressing access SFR space. For example: MOV
0A0H, # data, accesses the SFR at location 0A0h (which is P2).
•
Instructions that use indirect addressing access the Upper 128 bytes of data RAM.
For example: MOV @R0, # data where R0 contains 0A0h, accesses the data byte
at address 0A0h, rather than P2 (whose address is 0A0h).
•
The XRAM bytes can be accessed by indirect addressing, with EXTRAM bit cleared
and MOVX instructions. This part of memory which is physically located on-chip,
logically occupies the first bytes of external data memory. The bits XRS0 and XRS1
are used to hide a part of the available XRAM as explained in Table 19. This can be
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
useful if external peripherals are mapped at addresses already used by the internal
XRAM.
•
With EXTRAM = 0, the XRAM is indirectly addressed, using the MOVX instruction in
combination with any of the registers R0, R1 of the selected bank or DPTR. An
access to XRAM will not affect ports P0, P2, P3.6 (WR) and P3.7 (RD). For
example, with EXTRAM = 0, MOVX @R0, # data where R0 contains 0A0H,
accesses the XRAM at address 0A0H rather than external memory. An access to
external data memory locations higher than the accessible size of the XRAM will be
performed with the MOVX DPTR instructions in the same way as in the standard
80C51, with P0 and P2 as data/address busses, and P3.6 and P3.7 as write and
read timing signals. Accesses to XRAM above 0FFH can only be done by the use of
DPTR.
•
With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard
80C51.MOVX @ Ri will provide an eight-bit address multiplexed with data on Port0
and any output port pins can be used to output higher order address bits. This is to
provide the external paging capability. MOVX @DPTR will generate a sixteen-bit
address. Port2 outputs the high-order eight address bits (the contents of DPH) while
Port0 multiplexes the low-order eight address bits (DPL) with data. MOVX @ Ri and
MOVX @DPTR will generate either read or write signals on P3.6 (WR) and P3.7
(RD).
The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and
upper RAM) internal data memory. The stack may not be located in the XRAM.
The M0 bit allows to stretch the XRAM timings; if M0 is set, the read and write pulses
are extended from 6 to 30 clock periods. This is useful to access external slow
peripherals.
25
4235E–8051–04/04
Registers
Table 19. AUXR Register
AUXR - Auxiliary Register (8Eh)
7
6
5
4
3
2
1
0
DPU
-
M0
XRS2
XRS1
XRS0
EXTRAM
AO
Bit
Number
Bit
Mnemonic Description
Disable Weak Pull-up
7
DPU
Cleared by software to activate the permanent weak pull-up (default)
Set by software to disable the weak pull-up (reduce power consumption)
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Pulse length
5
M0
Cleared to stretch MOVX control: the RD and the WR pulse length is 6 clock
periods (default).
Set to stretch MOVX control: the RD and the WR pulse length is 30 clock periods.
4
XRS2
XRAM Size
3
XRS1
XRS2
0
XRS1 XRS0
0
0
XRAM size
256 bytes
0
0
1
512 bytes
0
1
0
768 bytes(default)
0
1
1
1024 bytes
1
0
0
1792 bytes
2
XRS0
EXTRAM bit
Cleared to access internal XRAM using movx @ Ri/ @ DPTR.
1
EXTRAM
Set to access external memory.
Programmed by hardware after Power-up regarding Hardware Security Byte
(HSB), default setting, XRAM selected.
0
AO
ALE Output bit
Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if
X2 mode is used). (default) Set, ALE is active only during a MOVX or MOVC
instruction is used.
Reset Value = 0X00 10’HSB. XRAM’0b
Not bit addressable
26
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
Reset
Introduction
The reset sources are: Power Management, Hardware Watchdog, PCA Watchdog and
Reset input.
Figure 9. Reset schematic
Power
Monitor
Hardware
Watchdog
Internal Reset
PCA
Watchdog
RST
Reset Input
The Reset input can be used to force a reset pulse longer than the internal reset controlled by the Power Monitor. RST input has a pull-down resistor allowing power-on
reset by simply connecting an external capacitor to VCC as shown in Figure 10. Resistor
value and input characteristics are discussed in the Section “DC Characteristics” of the
AT89C51RD2/ED2 datasheet.
Figure 10. Reset Circuitry and Power-On Reset
VDD
To internal reset
RST
R
RST
+
RST
VSS
a. RST input circuitry
b. Power-on Reset
27
4235E–8051–04/04
Reset Output
As detailed in Section “Hardware Watchdog Timer”, page 86, the WDT generates a 96clock period pulse on the RST pin. In order to properly propagate this pulse to the rest of
the application in case of external capacitor or power-supply supervisor circuit, a 1 kΩ
resistor must be added as shown Figure 11.
Figure 11. Recommended Reset Output Schematic
VDD
+
RST
VDD
1K
AT89C51XD2
RST
VSS
28
To other
on-board
circuitry
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
Power Monitor
The POR/PFD function monitors the internal power-supply of the CPU core memories
and the peripherals, and if needed, suspends their activity when the internal power supply falls below a safety threshold. This is achieved by applying an internal reset to them.
By gen erating the Re se t the Power Monito r insures a correct start up whe n
AT89C51RD2/ED2 is powered up.
Description
In order to startup and maintain the microcontroller in correct operating mode, VCC has
to be stabilized in the VCC operating range and the oscillator has to be stabilized with a
nominal amplitude compatible with logic level VIH/VIL.
These parameters are controlled during the three phases: power-up, normal operation
and power going down. See Figure 12.
Figure 12. Power Monitor Block Diagram
VCC
CPU core
Power On Reset
Power Fail Detect
Voltage Regulator
Regulated
Supply
Memories
Peripherals
XTAL1
(1)
Internal Reset
RST pin
PCA
Watchdog
Note:
Hardware
Watchdog
1. Once XTAL1 High and low levels reach above and below VIH/VIL. a 1024 clock
period delay will extend the reset coming from the Power Fail Detect. If the power
falls below the Power Fail Detect threshold level, the Reset will be applied
immediately.
The Voltage regulator generates a regulated internal supply for the CPU core the memories and the peripherals. Spikes on the external Vcc are smoothed by the voltage
regulator.
29
4235E–8051–04/04
The Power fail detect monitor the supply generated by the voltage regulator and generate a reset if this supply falls below a safety threshold as illustrated in the Figure 13
below.
Figure 13. Power Fail Detect
Vcc
t
Reset
Vcc
When the power is applied, the Power Monitor immediately asserts a reset. Once the
internal supply after the voltage regulator reach a safety level, the power monitor then
looks at the XTAL clock input. The internal reset will remain asserted until the Xtal1 levels are above and below VIH and VIL. Further more. An internal counter will count 1024
clock periods before the reset is de-asserted.
If the internal power supply falls below a safety level, a reset is immediately asserted.
.
30
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
Timer 2
The Timer 2 in the AT89C51RD2/ED2 is the standard C52 Timer 2. It is a 16-bit
timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2 are
cascaded. It is controlled by T2CON (Table 20) and T2MOD (Table 21) registers. Timer
2 operation is similar to Timer 0 and Timer 1. C/T2 selects FOSC/12 (timer operation) or
external pin T2 (counter operation) as the timer clock input. Setting TR2 allows TL2 to
increment by the selected input.
Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These
modes are selected by the combination of RCLK, TCLK and CP/RL2 (T2CON).
Refer to the Atmel 8-bit Microcontroller Hardware Manual for the description of Capture
and Baud Rate Generator Modes.
Timer 2 includes the following enhancements:
Auto-reload Mode
•
Auto-reload mode with up or down counter
•
Programmable clock-output
The auto-reload mode configures Timer 2 as a 16-bit timer or event counter with automatic reload. If DCEN bit in T2MOD is cleared, Timer 2 behaves as in 80C52 (refer to
the Atmel C51 Microcontroller Hardware Manual). If DCEN bit is set, Timer 2 acts as an
Up/down timer/counter as shown in Figure 14. In this mode the T2EX pin controls the
direction of count.
When T2EX is high, Timer 2 counts up. Timer overflow occurs at FFFFh which sets the
TF2 flag and generates an interrupt request. The overflow also causes the 16-bit value
in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2.
When T2EX is low, Timer 2 counts down. Timer underflow occurs when the count in the
timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers.
The underflow sets TF2 flag and reloads FFFFh into the timer registers.
The EXF2 bit toggles when Timer 2 overflows or underflows according to the direction of
the count. EXF2 does not generate any interrupt. This bit can be used to provide 17-bit
resolution.
31
4235E–8051–04/04
Figure 14. Auto-reload Mode Up/Down Counter (DCEN = 1)
FCLK PERIPH
:6
0
1
T2
C/T2
TR2
T2CON
T2CON
(DOWN COUNTING RELOAD VALUE) T2EX:
If DCEN = 1, 1 = UP
FFh
FFh
If DCEN = 1, 0 = DOWN
(8-bit)
(8-bit)
If DCEN = 0, up counting
TOGGLE
T2CON
EXF2
TL2
TH2
(8-bit)
(8-bit)
TIMER 2
INTERRUPT
TF2
T2CON
RCAP2L RCAP2H
(8-bit)
(8-bit)
(UP COUNTING RELOAD VALUE)
Programmable
Clock-output
In the clock-out mode, Timer 2 operates as a 50% duty-cycle, programmable clock generator (See Figure 15). The input clock increments TL2 at frequency FCLK PERIPH/2. The
timer repeatedly counts to overflow from a loaded value. At overflow, the contents of
RCAP2H and RCAP2L registers are loaded into TH2 and TL2. In this mode, Timer 2
overflows do not generate interrupts. The formula gives the clock-out frequency as a
function of the system oscillator frequency and the value in the RCAP2H and RCAP2L
registers:
Clock –O utFrequency
F CLKPERIPH
= --------------------------------------------------------------------------------------------4 × ( 65536 – RCAP2H ⁄ RCAP2L )
For a 16 MHz system clock, Timer 2 has a programmable frequency range of 61 Hz
(FCLK PERIPH/216) to 4 MHz (FCLK PERIPH/4). The generated clock signal is brought out to
T2 pin (P1.0).
Timer 2 is programmed for the clock-out mode as follows:
•
Set T2OE bit in T2MOD register.
•
Clear C/T2 bit in T2CON register.
•
Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L
registers.
•
Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the
reload value or a different one depending on the application.
•
To start the timer, set TR2 run control bit in T2CON register.
It is possible to use Timer 2 as a baud rate generator and a clock generator simultaneously. For this configuration, the baud rates and clock frequencies are not
independent since both functions use the values in the RCAP2H and RCAP2L registers.
32
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
Figure 15. Clock-out Mode C/T2 = 0
FCLK PERIPH
:6
TR2
T2CON
TL2
(8-bit)
TH 2
(8-bit)
OVERFLOW
RCAP2L RCAP2H
(8-bit) (8-bit)
Toggle
T2
Q
D
T2OE
T2MOD
T2EX
EXF2
EXEN2
T2CON
T2CON
TIMER 2
INTERRUPT
33
4235E–8051–04/04
Registers
Table 20. T2CON Register
T2CON - Timer 2 Control Register (C8h)
7
6
5
4
3
2
1
0
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2#
CP/RL2#
Bit
Number
7
Bit
Mnemonic Description
TF2
Timer 2 overflow Flag
Must be cleared by software.
Set by hardware on Timer 2 overflow, if RCLK = 0 and TCLK = 0.
6
EXF2
Timer 2 External Flag
Set when a capture or a reload is caused by a negative transition on T2EX pin if
EXEN2 = 1.
When set, causes the CPU to vector to Timer 2 interrupt routine when Timer 2
interrupt is enabled.
Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down
counter mode (DCEN = 1).
5
RCLK
Receive Clock bit
Cleared to use timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3.
4
TCLK
Transmit Clock bit
Cleared to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.
Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3.
3
EXEN2
2
TR2
1
0
Timer 2 External Enable bit
Cleared to ignore events on T2EX pin for Timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is
detected, if Timer 2 is not used to clock the serial port.
Timer 2 Run control bit
Cleared to turn off Timer 2.
Set to turn on Timer 2.
C/T2#
Timer/Counter 2 select bit
Cleared for timer operation (input from internal clock system: FCLK PERIPH).
Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0
for clock out mode.
CP/RL2#
Timer 2 Capture/Reload bit
If RCLK = 1 or TCLK = 1, CP/RL2# is ignored and timer is forced to auto-reload
on Timer 2 overflow.
Cleared to auto-reload on Timer 2 overflows or negative transitions on T2EX pin
if EXEN2=1.
Set to capture on negative transitions on T2EX pin if EXEN2 = 1.
Reset Value = 0000 0000b
Bit addressable
34
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
Table 21. T2MOD Register
T2MOD - Timer 2 Mode Control Register (C9h)
7
6
5
4
3
2
1
0
-
-
-
-
-
-
T2OE
DCEN
Bit
Number
Bit
Mnemonic Description
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
1
T2OE
Timer 2 Output Enable bit
Cleared to program P1.0/T2 as clock input or I/O port.
Set to program P1.0/T2 as clock output.
0
DCEN
Down Counter Enable bit
Cleared to disable Timer 2 as up/down counter.
Set to enable Timer 2 as up/down counter.
Reset Value = XXXX XX00b
Not bit addressable
35
4235E–8051–04/04
Programmable
Counter Array (PCA)
The PCA provides more timing capabilities with less CPU intervention than the standard
timer/counters. Its advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated timer/counter which serves as the time base for
an array of five compare/capture modules. Its clock input can be programmed to count
any one of the following signals:
•
÷6
Peripheral clock frequency (FCLK PERIPH) ÷ 2
•
Timer 0 overflow
•
External input on ECI (P1.2)
•
Peripheral clock frequency (FCLK PERIPH)
Each compare/capture module can be programmed in any one of the following modes:
•
Rising and/or falling edge capture
•
Software timer
•
High-speed output
•
Pulse width modulator
Module 4 can also be programmed as a watchdog timer (see Section "PCA Watchdog
Timer", page 47).
When the compare/capture modules are programmed in the capture mode, software
timer, or high speed output mode, an interrupt can be generated when the module executes its function. All five modules plus the PCA timer overflow share one interrupt
vector.
The PCA timer/counter and compare/capture modules share Port 1 for external I/O.
These pins are listed below. If one or several bits in the port are not used for the PCA,
they can still be used for standard I/O.
PCA Component
External I/O Pin
16-bit Counter
P1.2/ECI
16-bit Module 0
P1.3/CEX0
16-bit Module 1
P1.4/CEX1
16-bit Module 2
P1.5/CEX2
16-bit Module 3
P1.6/CEX3
The PCA timer is a common time base for all five modules (see Figure 16). The timer
count source is determined from the CPS1 and CPS0 bits in the CMOD register
(Table 22) and can be programmed to run at:
36
•
1/6 the peripheral clock frequency (FCLK PERIPH)
•
1/2 the peripheral clock frequency (FCLK PERIPH)
•
The Timer 0 overflow
•
The input on the ECI pin (P1.2)
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
The CMOD register includes three additional bits associated with the PCA (See
Figure 16 and Table 22).
•
The CIDL bit which allows the PCA to stop during idle mode.
•
The WDTE bit which enables or disables the watchdog function on module 4.
•
The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in
the CCON SFR) to be set when the PCA timer overflows.
Figure 16. PCA Timer/Counter
To PCA
Modules
FCLK PERIPH/6
Overflow
FCLK PERIPH/2
CH
T0 OVF
IT
CL
16 Bit Up Counter
P1.2
CIDL
WDTE
CF
CR
CPS1
CPS0
ECF
CMOD
0xD9
CCF0
CCON
0xD8
Idle
CCF4 CCF3
CCF2 CCF1
37
4235E–8051–04/04
Table 22. CMOD Register
CMOD - PCA Counter Mode Register (D9h)
7
6
5
4
3
2
1
0
CIDL
WDTE
-
-
-
CPS1
CPS0
ECF
Bit
Number
Bit
Mnemonic Description
Counter Idle Control
7
CIDL
Cleared to program the PCA Counter to continue functioning during idle Mode.
Set to program PCA to be gated off during idle.
Watchdog Timer Enable
6
WDTE
Cleared to disable Watchdog Timer function on PCA Module 4.
Set to enable Watchdog Timer function on PCA Module 4.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2
CPS1
PCA Count Pulse Select
CPS1 CPS0 Selected PCA input
0
0
Internal clock FCLK PERIPH/6
1
0
CPS0
ECF
0
1
Internal clock FCLK PERIPH/2
1
0
Timer 0 Overflow
1
1
External clock at ECI/P1.2 pin (max rate = FCLK PERIPH/4)
PCA Enable Counter Overflow Interrupt
Cleared to disable CF bit in CCON to inhibit an interrupt.
Set to enable CF bit in CCON to generate an interrupt.
Reset Value = 00XX X000b
Not bit addressable
The CCON register contains the run control bit for the PCA and the flags for the PCA
timer (CF) and each module (Refer to Table 23).
38
•
Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by
clearing this bit.
•
Bit CF: The CF bit (CCON.7) is set when the PCA counter overflows and an
interrupt will be generated if the ECF bit in the CMOD register is set. The CF bit can
only be cleared by software.
•
Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1,
etc.) and are set by hardware when either a match or a capture occurs. These flags
also can only be cleared by software.
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
Table 23. CCON Register
CCON - PCA Counter Control Register (D8h)
7
6
5
4
3
2
1
0
CF
CR
-
CCF4
CCF3
CCF2
CCF1
CCF0
Bit
Number
Bit
Mnemonic Description
PCA Counter Overflow flag
7
CF
Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in
CMOD is set. CF
may be set by either hardware or software but can only be cleared by software.
PCA Counter Run control bit
6
CR
Must be cleared by software to turn the PCA counter off.
Set by software to turn the PCA counter on.
5
-
4
CCF4
Reserved
The value read from this bit is indeterminate. Do not set this bit.
PCA Module 4 interrupt flag
Must be cleared by software.
Set by hardware when a match or capture occurs.
PCA Module 3 interrupt flag
3
CCF3
Must be cleared by software.
Set by hardware when a match or capture occurs.
PCA Module 2 interrupt flag
2
CCF2
Must be cleared by software.
Set by hardware when a match or capture occurs.
PCA Module 1 interrupt flag
1
CCF1
Must be cleared by software.
Set by hardware when a match or capture occurs.
PCA Module 0 interrupt flag
0
CCF0
Must be cleared by software.
Set by hardware when a match or capture occurs.
Reset Value = 00X0 0000b
Not bit addressable
The watchdog timer function is implemented in Module 4 (See Figure 19).
The PCA interrupt system is shown in Figure 17.
39
4235E–8051–04/04
Figure 17. PCA Interrupt System
CF
CR
CCF4 CCF3 CCF2 CCF1 CCF0
CCON
0xD8
PCA Timer/Counter
Module 0
Module 1
To Interrupt
Priority Decoder
Module 2
Module 3
Module 4
CMOD.0
ECF
ECCFn CCAPMn.0
IEN0.6
EC
IEN0.7
EA
PCA Modules: each one of the five compare/capture modules has six possible functions. It can perform:
•
16-bit Capture, positive-edge triggered
•
16-bit Capture, negative-edge triggered
•
16-bit Capture, both positive and negative-edge triggered
•
16-bit Software Timer
•
16-bit High Speed Output
•
8-bit Pulse Width Modulator
In addition, Module 4 can be used as a Watchdog Timer.
Each module in the PCA has a special function register associated with it. These registers are: CCAPM0 for Module 0, CCAPM1 for Module 1, etc. (See Table 24). The
registers contain the bits that control the mode that each module will operate in.
40
•
The ECCF bit (CCAPMn.0 where n = 0, 1, 2, 3, or 4 depending on the module)
enables the CCF flag in the CCON SFR to generate an interrupt when a match or
compare occurs in the associated module.
•
PWM (CCAPMn.1) enables the pulse width modulation mode.
•
The TOG bit (CCAPMn.2) when set causes the CEX output associated with the
module to toggle when there is a match between the PCA counter and the modules
capture/compare register.
•
The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON
register to be set when there is a match between the PCA counter and the modules
capture/compare register.
•
The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge
that a capture input will be active on. The CAPN bit enables the negative edge, and
the CAPP bit enables the positive edge. If both bits are set both edges will be
enabled and a capture will occur for either transition.
•
The last bit in the register ECOM (CCAPMn.6) when set enables the comparator
function.
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
Table 24 shows the CCAPMn settings for the various PCA functions.
Table 24. CCAPMn Registers (n = 0-4)
CCAPM0 - PCA Module 0 Compare/Capture Control Register (0DAh)
CCAPM1 - PCA Module 1 Compare/Capture Control Register (0DBh)
CCAPM2 - PCA Module 2 Compare/Capture Control Register (0DCh)
CCAPM3 - PCA Module 3 Compare/Capture Control Register (0DDh)
CCAPM4 - PCA Module 4 Compare/Capture Control Register (0DEh)
7
6
5
4
3
2
1
0
-
ECOMn
CAPPn
CAPNn
MATn
TOGn
PWMn
ECCFn
Bit
Number
Bit
Mnemonic Description
7
-
6
ECOMn
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Enable Comparator
Cleared to disable the comparator function.
Set to enable the comparator function.
Capture Positive
5
CAPPn
4
CAPNn
Cleared to disable positive edge capture.
Set to enable positive edge capture.
Capture Negative
Cleared to disable negative edge capture.
Set to enable negative edge capture.
Match
3
MATn
2
TOGn
1
PWMn
When MATn = 1, a match of the PCA counter with this module's
compare/capture register causes the CCFn bit in CCON to be set, flagging an
interrupt.
Toggle
When TOGn = 1, a match of the PCA counter with this module's
compare/capture register causes the CEXn pin to toggle.
Pulse Width Modulation Mode
Cleared to disable the CEXn pin to be used as a pulse width modulated output.
Set to enable the CEXn pin to be used as a pulse width modulated output.
Enable CCF interrupt
0
CCF0
Cleared to disable compare/capture flag CCFn in the CCON register to generate
an interrupt.
Set to enable compare/capture flag CCFn in the CCON register to generate an
interrupt.
Reset Value = X000 0000b
Not bit addressable
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4235E–8051–04/04
Table 25. PCA Module Modes (CCAPMn Registers)
ECOMn
CAPPn
CAPNn
MATn
TOGn
PWMm
ECCFn Module Function
0
0
0
0
0
0
0
No Operation
X
1
0
0
0
0
X
16-bit capture by a positive-edge
trigger on CEXn
X
0
1
0
0
0
X
16-bit capture by a negative trigger
on CEXn
X
1
1
0
0
0
X
16-bit capture by a transition on
CEXn
1
0
0
1
0
0
X
16-bit Software Timer/Compare
mode.
1
0
0
1
1
0
X
16-bit High Speed Output
1
0
0
0
0
1
0
8-bit PWM
1
0
0
1
X
0
X
Watchdog Timer (module 4 only)
There are two additional registers associated with each of the PCA modules. They are
CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a
capture occurs or a compare should occur. When a module is used in the PWM mode
these registers are used to control the duty cycle of the output (See Table 26 &
Table 27).
Table 26. CCAPnH Registers (n = 0 - 4)
CCAP0H - PCA Module 0 Compare/Capture Control Register High (0FAh)
CCAP1H - PCA Module 1 Compare/Capture Control Register High (0FBh)
CCAP2H - PCA Module 2 Compare/Capture Control Register High (0FCh)
CCAP3H - PCA Module 3 Compare/Capture Control Register High (0FDh)
CCAP4H - PCA Module 4 Compare/Capture Control Register High (0FEh)
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
Bit
Number
7-0
Bit
Mnemonic Description
-
PCA Module n Compare/Capture Control
CCAPnH Value
Reset Value = 0000 0000b
Not bit addressable
42
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
Table 27. CCAPnL Registers (n = 0 - 4)
CCAP0L - PCA Module 0 Compare/Capture Control Register Low (0EAh)
CCAP1L - PCA Module 1 Compare/Capture Control Register Low (0EBh)
CCAP2L - PCA Module 2 Compare/Capture Control Register Low (0ECh)
CCAP3L - PCA Module 3 Compare/Capture Control Register Low (0EDh)
CCAP4L - PCA Module 4 Compare/Capture Control Register Low (0EEh)
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
Bit
Number
7-0
Bit
Mnemonic Description
-
PCA Module n Compare/Capture Control
CCAPnL Value
Reset Value = 0000 0000b
Not bit addressable
Table 28. CH Register
CH - PCA Counter Register High (0F9h)
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
Bit
Number
7-0
Bit
Mnemonic Description
-
PCA counter
CH Value
Reset Value = 0000 0000b
Not bit addressable
Table 29. CL Register
CL - PCA Counter Register Low (0E9h)
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
Bit
Number
7-0
Bit
Mnemonic Description
-
PCA Counter
CL Value
Reset Value = 0000 0000b
Not bit addressable
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4235E–8051–04/04
PCA Capture Mode
To use one of the PCA modules in the capture mode either one or both of the CCAPM
bits CAPN and CAPP for that module must be set. The external CEX input for the module (on port 1) is sampled for a transition. When a valid transition occurs the PCA
hardware loads the value of the PCA counter registers (CH and CL) into the module's
capture registers (CCAPnL and CCAPnH). If the CCFn bit for the module in the CCON
SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated
(Refer to Figure 18).
Figure 18. PCA Capture Mode
CF
CR
CCF4 CCF3 CCF2
CCF1 CCF0 CCO N
0xD8
PCA IT
PCA Counter/Timer
Cex.n
CH
CL
CCAPnH
CCAPnL
Capture
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CCAPMn, n= 0 to 4
0xDA to 0xDE
16-bit Software Timer/
Compare Mode
44
The PCA modules can be used as software timers by setting both the ECOM and MAT
bits in the modules CCAPMn register. The PCA timer will be compared to the module's
capture registers and when a match occurs an interrupt will occur if the CCFn (CCON
SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set (See Figure 19).
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
Figure 19. PCA Compare Mode and PCA Watchdog Timer
CCON
CF
Write to
CCAPnL
CR
CCF4 CCF3 CCF2 CCF1 CCF0
0xD8
Reset
PCA I T
Write to
CCAPnH
1
CCAPnH
0
CCAPnL
Enable
Match
16 bit comparator
CH
RESET *
CL
PCA counter/ timer
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
CIDL
WDTE
CPS1 CPS0
ECF
CCAPMn, n = 0 to 4
0xDA t o 0xDE
CMOD
0xD9
Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value,
otherwise an unwanted match could happen. Writing to CCAPnH will set the ECOM bit.
Once ECOM is set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t
occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this
reason, user software should write CCAPnL first, and then CCAPnH. Of course, the
ECOM bit can still be controlled by accessing to CCAPMn register.
High Speed Output Mode In this mode the CEX output (on port 1) associated with the PCA module will toggle
each time a match occurs between the PCA counter and the modules capture registers.
To activate this mode the TOG, MAT, and ECOM bits in the module's CCAPMn SFR
must be set (See Figure 20).
A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit.
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4235E–8051–04/04
Figure 20. PCA High Speed Output Mode
CCON
CF
Write to
CCA PnL
CR
CCF4 CCF3 CCF2 CCF1 CCF0
0xD8
Reset
PCA IT
Write to
CCAPnH
1
CCAPnH
0
CCAPnL
Enable
16 bit comparator
CH
Match
CL
CEXn
PCA counter/timer
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
CCAPMn, n = 0 to 4
0xDA to 0xDE
Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value,
otherwise an unwanted match could happen.
Once ECOM is set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t
occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this
reason, user software should write CCAPnL first, and then CCAPnH. Of course, the
ECOM bit can still be controlled by accessing to CCAPMn register.
Pulse Width Modulator
Mode
46
All of the PCA modules can be used as PWM outputs. Figure 21 shows the PWM function. The frequency of the output depends on the source for the PCA timer. All of the
modules will have the same frequency of output because they all share the PCA timer.
The duty cycle of each module is independently variable using the modules capture register CCAPLn. When the value of the PCA CL SFR is less than the value in the modules
CCAPLn SFR the output will be low, when it is equal to or greater than the output will be
high. When CL overflows from FF to 00, CCAPLn is reloaded with the value in CCAPHn.
This allows updating the PWM without glitches. The PWM and ECOM bits in the module's CCAPMn register must be set to enable the PWM mode.
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
Figure 21. PCA PWM Mode
CCAPnH
Overflow
CCAPnL
“0”
CEXn
Enable
8-bit Comparator
“1”
CL
PCA Counter/Timer
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
CCAPMn, n= 0 to 4
0xDA to 0xDE
PCA Watchdog Timer
An on-board watchdog timer is available with the PCA to improve the reliability of the
system without increasing chip count. Watchdog timers are useful for systems that are
susceptible to noise, power glitches, or electrostatic discharge. Module 4 is the only
PCA module that can be programmed as a watchdog. However, this module can still be
used for other modes if the watchdog is not needed. Figure 19 shows a diagram of how
the watchdog works. The user pre-loads a 16-bit value in the compare registers. Just
like the other compare modes, this 16-bit value is compared to the PCA timer value. If a
match is allowed to occur, an internal reset will be generated. This will not cause the
RST pin to be driven high.
In order to hold off the reset, the user has three options:
1. Periodically change the compare value so it will never match the PCA timer.
2. Periodically change the PCA timer value so it will never match the compare
values.
3. Disable the watchdog by clearing the WDTE bit before a match occurs and then
re-enable it.
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4235E–8051–04/04
The first two options are more reliable because the watchdog timer is never disabled as
in option #3. If the program counter ever goes astray, a match will eventually occur and
cause an internal reset. The second option is also not recommended if other PCA modules are being used. Remember, the PCA timer is the time base for all modules;
changing the time base for other modules would not be a good idea. Thus, in most applications the first solution is the best option.
This watchdog timer won’t generate a reset out on the reset pin.
48
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
Serial I/O Port
The serial I/O port in the AT89C51RD2/ED2 is compatible with the serial I/O port in the
80C52.
It provides both synchronous and asynchronous communication modes. It operates as a
Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes
(Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously
and at different baud rates
Serial I/O port includes the following enhancements:
Framing Error Detection
•
Framing error detection
•
Automatic address recognition
Framing bit error detection is provided for the three asynchronous modes (modes 1, 2
and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON register (See Figure 22).
Figure 22. Framing Error Block Diagram
SM0/FE
SM1
SM2
REN
TB8
RB8
TI
RI
SCON (98h)
Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)
SM0 to UART mode control (SMOD0 = 0)
SMOD1SMOD0
-
POF
GF1
GF0
PD
IDL
PCON (87h)
To UART framing error control
When this feature is enabled, the receiver checks each incoming data frame for a valid
stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous
transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in
SCON register (See Table 33.) bit is set.
Software may examine FE bit after each reception to check for data errors. Once set,
only software or a reset can clear FE bit. Subsequently received frames with valid stop
bits cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the
last data bit (See Figure 23. and Figure 24.).
Figure 23. UART Timings in Mode 1
RXD
D0
Start
bit
D1
D2
D3
D4
Data byte
D5
D6
D7
Stop
bit
RI
SMOD0=X
FE
SMOD0=1
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4235E–8051–04/04
Figure 24. UART Timings in Modes 2 and 3
RXD
D0
D1
Start
bit
D2
D3
D4
Data byte
D5
D6
D7
D8
Ninth Stop
bit
bit
RI
SMOD0=0
RI
SMOD0=1
FE
SMOD0=1
Automatic Address
Recognition
The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set).
Implemented in hardware, automatic address recognition enhances the multiprocessor
communication feature by allowing the serial port to examine the address of each
incoming command frame. Only when the serial port recognizes its own address, the
receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU
is not interrupted by command frames addressed to other devices.
If desired, the user may enable the automatic address recognition feature in mode 1.In
this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when
the received command frame address matches the device’s address and is terminated
by a valid stop bit.
To support automatic address recognition, a device is identified by a given address and
a broadcast address.
Note:
Given Address
The multiprocessor communication and automatic address recognition features cannot
be enabled in mode 0 (i. e. setting SM2 bit in SCON register in mode 0 has no effect).
Each device has an individual address that is specified in SADDR register; the SADEN
register is a mask byte that contains don’t-care bits (defined by zeros) to form the
device’s given address. The don’t-care bits provide the flexibility to address one or more
slaves at a time. The following example illustrates how a given address is formed.
To address a device by its individual address, the SADEN mask byte must be 1111
1111b.
For example:
SADDR0101 0110b
SADEN1111 1100b
Given0101 01XXb
The following is an example of how to use given addresses to address different slaves:
Slave A:SADDR1111 0001b
SADEN1111 1010b
Given1111 0X0Xb
Slave B:SADDR1111 0011b
SADEN1111 1001b
Given1111 0XX1b
Slave C:SADDR1111 0010b
SADEN1111 1101b
Given1111 00X1b
50
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
The SADEN byte is selected so that each slave may be addressed separately.
For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1.To communicate with slave A only, the master must send an address where bit 0 is clear (e. g.
1111 0000b).
For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with
slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both
set (e. g. 1111 0011b).
To communicate with slaves A, B and C, the master must send an address with bit 0 set,
bit 1 clear, and bit 2 clear (e. g. 1111 0001b).
Broadcast Address
A broadcast address is formed from the logical OR of the SADDR and SADEN registers
with zeros defined as don’t-care bits, e. g. :
SADDR 0101 0110b
SADEN 1111 1100b
Broadcast =SADDR OR SADEN1111 111Xb
The use of don’t-care bits provides flexibility in defining the broadcast address, however
in most applications, a broadcast address is FFh. The following is an example of using
broadcast addresses:
Slave A:SADDR1111 0001b
SADEN1111 1010b
Broadcast1111 1X11b,
Slave B:SADDR1111 0011b
SADEN1111 1001b
Broadcast1111 1X11B,
Slave C:SADDR=1111 0011b
SADEN1111 1101b
Broadcast1111 1111b
For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with
all of the slaves, the master must send an address FFh. To communicate with slaves A
and B, but not slave C, the master can send and address FBh.
Reset Addresses
On reset, the SADDR and SADEN registers are initialized to 00h, i. e. the given and
broadcast addresses are XXXX XXXXb (all don’t-care bits). This ensures that the serial
port will reply to any address, and so, that it is backwards compatible with the 80C51
microcontrollers that do not support automatic address recognition.
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4235E–8051–04/04
Registers
Table 30. SADEN Register
SADEN - Slave Address Mask Register (B9h)
7
6
5
4
3
2
1
0
3
2
1
0
Reset Value = 0000 0000b
Not bit addressable
Table 31. SADDR Register
SADDR - Slave Address Register (A9h)
7
6
5
4
Reset Value = 0000 0000b
Not bit addressable
Baud Rate Selection for
UART for Mode 1 and 3
The Baud Rate Generator for transmit and receive clocks can be selected separately via
the T2CON and BDRCON registers.
Figure 25. Baud Rate Selection
TIMER1
TIMER2
0
TIMER_BRG_RX
0
1
/ 16
Rx Clock
1
RCLK
RBCK
INT_BRG
TIMER1
TIMER2
0
1
TIMER_BRG_TX
0
1
/ 16
Tx Clock
TCLK
INT_BRG
52
TBCK
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
Table 32. Baud Rate Selection Table UART
Internal Baud Rate Generator
(BRG)
TCLK
RCLK
TBCK
RBCK
Clock Source
Clock Source
(T2CON)
(T2CON)
(BDRCON)
(BDRCON)
UART Tx
UART Rx
0
0
0
0
Timer 1
Timer 1
1
0
0
0
Timer 2
Timer 1
0
1
0
0
Timer 1
Timer 2
1
1
0
0
Timer 2
Timer 2
X
0
1
0
INT_BRG
Timer 1
X
1
1
0
INT_BRG
Timer 2
0
X
0
1
Timer 1
INT_BRG
1
X
0
1
Timer 2
INT_BRG
X
X
1
1
INT_BRG
INT_BRG
When the internal Baud Rate Generator is used, the Baud Rates are determined by the
BRG overflow depending on the BRL reload value, the value of SPD bit (Speed Mode)
in BDRCON register and the value of the SMOD1 bit in PCON register.
Figure 26. Internal Baud Rate
FPER
0
/6
auto reload counter
overflow
BRG
1
SPD
/2
0
INT_BRG
1
BRL
SMOD1
BRR
•
The baud rate for UART is token by formula:
Baud_Rate =
BRL = 256 -
2SMOD1 ⋅ FPER
6(1-SPD) ⋅ 32 ⋅ (256 -BRL)
2SMOD1 ⋅ FPER
⋅ 32 ⋅ Baud_Rate
(1-SPD)
6
53
4235E–8051–04/04
Table 33. SCON Register
SCON - Serial Control Register (98h)
7
6
5
4
3
2
1
0
FE/SM0
SM1
SM2
REN
TB8
RB8
TI
RI
Bit
Bit
Number
Mnemonic
Description
Framing Error bit (SMOD0=1)
FE
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0 must be set to enable access to the FE bit.
7
SM0
Serial port Mode bit 0
Refer to SM1 for serial port mode selection.
SMOD0 must be cleared to enable access to the SM0 bit.
6
SM1
Serial port Mode bit 1
SM0 SM1
Mode
0
0
Shift Register
0
1
8-bit UART
1
0
9-bit UART
1
1
9-bit UART
Baud Rate
FXTAL /12 (or FXTAL /6 in mode X2)
Variable
FXTAL /64 or FXTAL/32
Variable
Serial port Mode 2 bit / Multiprocessor Communication Enable bit
5
SM2
4
REN
3
TB8
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and
eventually mode 1.This bit should be cleared in mode 0.
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3
2
RB8
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
Receiver Bit 8 / Ninth bit received in modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not
used.
1
0
TI
Transmit Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning
of the stop bit in the other modes.
RI
Receive Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 23.
and Figure 24. in the other modes.
Reset Value = 0000 0000b
Bit addressable
54
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
Table 34. Example of Computed Value When X2=1, SMOD1=1, SPD=1
Baud Rates
FOSC = 16. 384 MHz
FOSC = 24MHz
BRL
Error (%)
BRL
Error (%)
115200
247
1.23
243
0.16
57600
238
1.23
230
0.16
38400
229
1.23
217
0.16
28800
220
1.23
204
0.16
19200
203
0.63
178
0.16
9600
149
0.31
100
0.16
4800
43
1.23
-
-
Table 35. Example of Computed Value When X2=0, SMOD1=0, SPD=0
Baud Rates
FOSC = 16. 384 MHz
FOSC = 24MHz
BRL
Error (%)
BRL
Error (%)
4800
247
1.23
243
0.16
2400
238
1.23
230
0.16
1200
220
1.23
202
3.55
600
185
0.16
152
0.16
The baud rate generator can be used for mode 1 or 3 (refer to Figure 25.), but also for
mode 0 for UART, thanks to the bit SRC located in BDRCON register (Table 42.)
UART Registers
Table 36. SADEN Register
SADEN - Slave Address Mask Register for UART (B9h)
7
6
5
4
3
2
1
0
2
1
0
Reset Value = 0000 0000b
Table 37. SADDR Register
SADDR - Slave Address Register for UART (A9h)
7
6
5
4
3
Reset Value = 0000 0000b
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4235E–8051–04/04
Table 38. SBUF Register
SBUF - Serial Buffer Register for UART (99h)
7
6
5
4
3
2
1
0
Reset Value = XXXX XXXXb
Table 39. BRL Register
BRL - Baud Rate Reload Register for the internal baud rate generator, UART (9Ah)
7
6
5
4
3
2
1
0
Reset Value = 0000 0000b
56
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
Table 40. T2CON Register
T2CON - Timer 2 Control Register (C8h)
7
6
5
4
3
2
1
0
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2#
CP/RL2#
Bit
Bit
Number
Mnemonic
7
TF2
Description
Timer 2 overflow Flag
Must be cleared by software.
Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0.
6
EXF2
Timer 2 External Flag
Set when a capture or a reload is caused by a negative transition on T2EX pin if
EXEN2=1.
When set, causes the CPU to vector to timer 2 interrupt routine when timer 2
interrupt is enabled.
Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down
counter mode (DCEN = 1)
5
RCLK
Receive Clock bit for UART
Cleared to use timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3.
4
TCLK
Transmit Clock bit for UART
Cleared to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3.
3
EXEN2
2
TR2
1
0
Timer 2 External Enable bit
Cleared to ignore events on T2EX pin for timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is
detected, if timer 2 is not used to clock the serial port.
Timer 2 Run control bit
Cleared to turn off timer 2.
Set to turn on timer 2.
C/T2#
Timer/Counter 2 select bit
Cleared for timer operation (input from internal clock system: FCLK PERIPH).
Set for counter operation (input from T2 input pin, falling edge trigger). Must be
0 for clock out mode.
CP/RL2#
Timer 2 Capture/Reload bit
If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on
timer 2 overflow.
Cleared to auto-reload on timer 2 overflows or negative transitions on T2EX pin
if EXEN2=1.
Set to capture on negative transitions on T2EX pin if EXEN2=1.
Reset Value = 0000 0000b
Bit addressable
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Table 41. PCON Register
PCON - Power Control Register (87h)
7
6
5
4
3
2
1
0
SMOD1
SMOD0
-
POF
GF1
GF0
PD
IDL
Bit
Bit
Number
Mnemonic
7
SMOD1
6
SMOD0
5
-
4
POF
Power-Off Flag
Cleared to recognize next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set
by software.
3
GF1
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
2
GF0
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
1
PD
Power-Down mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
0
IDL
Idle mode bit
Cleared by hardware when interrupt or reset occurs.
Set to enter idle mode.
Description
Serial port Mode bit 1 for UART
Set to select double baud rate in mode 1, 2 or 3.
Serial port Mode bit 0 for UART
Cleared to select SM0 bit in SCON register.
Set to select FE bit in SCON register.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reset Value = 00X1 0000b
Not bit addressable
Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset
doesn’t affect the value of this bit.
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Table 42. BDRCON Register
BDRCON - Baud Rate Control Register (9Bh)
7
6
5
4
3
2
1
0
-
-
-
BRR
TBCK
RBCK
SPD
SRC
Bit
Number
Bit
Mnemonic
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
BRR
Baud Rate Run Control bit
Cleared to stop the internal Baud Rate Generator.
Set to start the internal Baud Rate Generator.
3
TBCK
Transmission Baud rate Generator Selection bit for UART
Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
2
RBCK
Reception Baud Rate Generator Selection bit for UART
Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
1
SPD
Description
Baud Rate Speed Control bit for UART
Cleared to select the SLOW Baud Rate Generator.
Set to select the FAST Baud Rate Generator.
Baud Rate Source select bit in Mode 0 for UART
0
SRC
Cleared to select FOSC /12 as the Baud Rate Generator (FCLK PERIPH/6 in X2
mode).
Set to select the internal Baud Rate Generator for UARTs in mode 0.
Reset Value = XXX0 0000b
Not bit addressable
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Keyboard Interface
The AT89C51RD2/ED2 implements a keyboard interface allowing the connection of a
8 x n matrix keyboard. It is based on 8 inputs with programmable interrupt capability on
both high or low level. These inputs are available as alternate function of P1 and allow to
exit from idle and power-down modes.
The keyboard interfaces with the C51 core through 3 special function registers: KBLS,
the Keyboard Level Selection register (Table 45), KBE, the Keyboard interrupt Enable
register (Table 44), and KBF, the Keyboard Flag register (Table 43).
Interrupt
The keyboard inputs are considered as 8 independent interrupt sources sharing the
same interrupt vector. An interrupt enable bit (KBD in IE1) allows global enable or disable of the keyboard interrupt (see Figure 27). As detailed in Figure 28 each keyboard
input has the capability to detect a programmable level according to KBLS. x bit value.
Level detection is then reported in interrupt flags KBF.x that can be masked by software
using KBE. x bits.
This structure allow keyboard arrangement from 1 by n to 8 by n matrix and allows
usage of P1 inputs for other purpose.
Figure 27. Keyboard Interface Block Diagram
Vcc
0
P1:x
KBF.x
1
Internal Pullup
KBE.x
KBLS.x
Figure 28. Keyboard Input Circuitry
P1.0
Input Circuitry
P1.1
Input Circuitry
P1.2
Input Circuitry
P1.3
Input Circuitry
P1.4
Input Circuitry
P1.5
Input Circuitry
P1.6
Input Circuitry
P1.7
Input Circuitry
KBDIT
Power Reduction Mode
60
KBD
IE1
Keyboard Interface
Interrupt Request
P1 inputs allow exit from idle and power-down modes as detailed in Section “Power
Management”, page 82.
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Registers
Table 43. KBF Register
KBF-Keyboard Flag Register (9Eh)
7
6
5
4
3
2
1
0
KBF7
KBF6
KBF5
KBF4
KBF3
KBF2
KBF1
KBF0
Bit
Number
7
6
5
4
3
2
1
0
Bit
Mnemonic Description
KBF7
Keyboard line 7 flag
Set by hardware when the Port line 7 detects a programmed level. It generates a
Keyboard interrupt request if the KBKBIE.7 bit in KBIE register is set.
Must be cleared by software.
KBF6
Keyboard line 6 flag
Set by hardware when the Port line 6 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.6 bit in KBIE register is set.
Must be cleared by software.
KBF5
Keyboard line 5 flag
Set by hardware when the Port line 5 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.5 bit in KBIE register is set.
Must be cleared by software.
KBF4
Keyboard line 4 flag
Set by hardware when the Port line 4 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.4 bit in KBIE register is set.
Must be cleared by software.
KBF3
Keyboard line 3 flag
Set by hardware when the Port line 3 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.3 bit in KBIE register is set.
Must be cleared by software.
KBF2
Keyboard line 2 flag
Set by hardware when the Port line 2 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.2 bit in KBIE register is set.
Must be cleared by software.
KBF1
Keyboard line 1 flag
Set by hardware when the Port line 1 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.1 bit in KBIE register is set.
Must be cleared by software.
KBF0
Keyboard line 0 flag
Set by hardware when the Port line 0 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.0 bit in KBIE register is set.
Must be cleared by software.
Reset Value = 0000 0000b
This register is read only access, all flags are automatically cleared by reading the
register.
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Table 44. KBE Register
KBE-Keyboard Input Enable Register (9Dh)
7
6
5
4
3
2
1
0
KBE7
KBE6
KBE5
KBE4
KBE3
KBE2
KBE1
KBE0
Bit
Number
Bit
Mnemonic Description
7
KBE7
Keyboard line 7 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.7 bit in KBF register to generate an interrupt request.
6
KBE6
Keyboard line 6 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.6 bit in KBF register to generate an interrupt request.
5
KBE5
Keyboard line 5 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.5 bit in KBF register to generate an interrupt request.
4
KBE4
Keyboard line 4 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.4 bit in KBF register to generate an interrupt request.
3
KBE3
Keyboard line 3 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.3 bit in KBF register to generate an interrupt request.
2
KBE2
Keyboard line 2 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.2 bit in KBF register to generate an interrupt request.
1
KBE1
Keyboard line 1 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.1 bit in KBF register to generate an interrupt request.
0
KBE0
Keyboard line 0 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.0 bit in KBF register to generate an interrupt request.
Reset Value = 0000 0000b
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Table 45. KBLS Register
KBLS-Keyboard Level Selector Register (9Ch)
7
6
5
4
3
2
1
0
KBLS7
KBLS6
KBLS5
KBLS4
KBLS3
KBLS2
KBLS1
KBLS0
Bit
Number
Bit
Mnemonic Description
7
KBLS7
Keyboard line 7 Level Selection bit
Cleared to enable a low level detection on Port line 7.
Set to enable a high level detection on Port line 7.
6
KBLS6
Keyboard line 6 Level Selection bit
Cleared to enable a low level detection on Port line 6.
Set to enable a high level detection on Port line 6.
5
KBLS5
Keyboard line 5 Level Selection bit
Cleared to enable a low level detection on Port line 5.
Set to enable a high level detection on Port line 5.
4
KBLS4
Keyboard line 4 Level Selection bit
Cleared to enable a low level detection on Port line 4.
Set to enable a high level detection on Port line 4.
3
KBLS3
Keyboard line 3 Level Selection bit
Cleared to enable a low level detection on Port line 3.
Set to enable a high level detection on Port line 3.
2
KBLS2
Keyboard line 2 Level Selection bit
Cleared to enable a low level detection on Port line 2.
Set to enable a high level detection on Port line 2.
1
KBLS1
Keyboard line 1 Level Selection bit
Cleared to enable a low level detection on Port line 1.
Set to enable a high level detection on Port line 1.
0
KBLS0
Keyboard line 0 Level Selection bit
Cleared to enable a low level detection on Port line 0.
Set to enable a high level detection on Port line 0.
Reset Value = 0000 0000b
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Serial Port Interface
(SPI)
The Serial Peripheral Interface Module (SPI) allows full-duplex, synchronous, serial
communication between the MCU and peripheral devices, including other MCUs.
Features
Features of the SPI Module include the following:
Signal Description
•
Full-duplex, three-wire synchronous transfers
•
Master or Slave operation
•
Eight programmable Master clock rates
•
Serial clock with programmable polarity and phase
•
Master Mode fault error flag with MCU interrupt capability
•
Write collision flag protection
Figure 29 shows a typical SPI bus configuration using one Master controller and many
Slave peripherals. The bus is made of three wires connecting all the devices.
Figure 29. SPI Master/Slaves Interconnection
Slave 1
MISO
MOSI
SCK
SS
MISO
MOSI
SCK
SS
VDD
Slave 4
Slave 3
MISO
MOSI
SCK
SS
0
1
2
3
MISO
MOSI
SCK
SS
MISO
MOSI
SCK
SS
PORT
Master
Slave 2
The Master device selects the individual Slave devices by using four pins of a parallel
port to control the four SS pins of the Slave devices.
Master Output Slave Input
(MOSI)
This 1-bit signal is directly connected between the Master Device and a Slave Device.
The MOSI line is used to transfer data in series from the Master to the Slave. Therefore,
it is an output signal from the Master, and an input signal to a Slave. A Byte (8-bit word)
is transmitted most significant bit (MSB) first, least significant bit (LSB) last.
Master Input Slave Output
(MISO)
This 1-bit signal is directly connected between the Slave Device and a Master Device.
The MISO line is used to transfer data in series from the Slave to the Master. Therefore,
it is an output signal from the Slave, and an input signal to the Master. A Byte (8-bit
word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last.
SPI Serial Clock (SCK)
This signal is used to synchronize the data movement both in and out of the devices
through their MOSI and MISO lines. It is driven by the Master for eight clock cycles
which allows to exchange one Byte on the serial lines.
Slave Select (SS)
Each Slave peripheral is selected by one Slave Select pin (SS). This signal must stay
low for any message for a Slave. It is obvious that only one Master (SS high level) can
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drive the network. The Master may select each Slave device by software through port
pins (Figure 30). To prevent bus conflicts on the MISO line, only one slave should be
selected at a time by the Master for a transmission.
In a Master configuration, the SS line can be used in conjunction with the MODF flag in
the SPI Status register (SPSTA) to prevent multiple masters from driving MOSI and
SCK (see Error conditions).
A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state.
The SS pin could be used as a general-purpose if the following conditions are met:
•
The device is configured as a Master and the SSDIS control bit in SPCON is set.
This kind of configuration can be found when only one Master is driving the network
and there is no way that the SS pin could be pulled low. Therefore, the MODF flag in
the SPSTA will never be set(1).
•
The Device is configured as a Slave with CPHA and SSDIS control bits set (2). This
kind of configuration can happen when the system comprises one Master and one
Slave only. Therefore, the device should always be selected and there is no reason
that the Master uses the SS pin to select the communicating Slave device.
Note:
1. Clearing SSDIS control bit does not clear MODF.
2. Special care should be taken not to set SSDIS control bit when CPHA = ’0’ because
in this mode, the SS is used to start the transmission.
Baud Rate
In Master mode, the baud rate can be selected from a baud rate generator which is controlled by three bits in the SPCON register: SPR2, SPR1 and SPR0.The Master clock is
selected from one of seven clock rates resulting from the division of the internal clock by
2, 4, 8, 16, 32, 64 or 128.
Table 46 gives the different clock rates selected by SPR2:SPR1:SPR0.
Table 46. SPI Master Baud Rate Selection
SPR2
SPR1
SPR0
Clock Rate
Baud Rate Divisor (BD)
0
0
0
FCLK PERIPH /2
2
0
0
1
FCLK PERIPH /4
4
0
1
0
FCLK PERIPH/8
8
0
1
1
FCLK PERIPH /16
16
1
0
0
FCLK PERIPH /32
32
1
0
1
FCLK PERIPH /64
64
1
1
0
FCLK PERIPH /128
128
1
1
1
Don’t Use
No BRG
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Functional Description
Figure 30 shows a detailed structure of the SPI Module.
Figure 30. SPI Module Block Diagram
Internal Bus
SPDAT
FCLK PERIPH
Clock
Divider
/4
/8
/16
/32
/64
/128
Shift Register
7
6
5
4
3
2
1
0
Receive Data Register
Pin
Control
Logic
Clock
Logic
M
S
Clock
Select
SPR2
MOSI
MISO
SCK
SS
SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0
SPCON
SPI Interrupt Request
SPI
Control
8-bit bus
1-bit signal
SPSTA
SPIF WCOL
Operating Modes
-
MODF
-
-
-
-
The Serial Peripheral Interface can be configured in one of the two modes: Master mode
or Slave mode. The configuration and initialization of the SPI Module is made through
one register:
•
The Serial Peripheral Control register (SPCON)
Once the SPI is configured, the data exchange is made using:
•
SPCON
•
The Serial Peripheral STAtus register (SPSTA)
•
The Serial Peripheral DATa register (SPDAT)
During an SPI transmission, data is simultaneously transmitted (shifted out serially) and
received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sampling on the two serial data lines (MOSI and MISO). A Slave Select line (SS) allows
individual selection of a Slave SPI device; Slave devices that are not selected do not
interfere with SPI bus activities.
When the Master device transmits data to the Slave device via the MOSI line, the Slave
device responds by sending data to the Master device via the MISO line. This implies
full-duplex transmission with both data out and data in synchronized with the same clock
(Figure 31).
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Figure 31. Full-Duplex Master-Slave Interconnection
8-bit Shift register
SPI
Clock Generator
MISO
MISO
MOSI
MOSI
SCK
SS
Master MCU
8-bit Shift register
SCK
VDD
SS
VSS
Slave MCU
Master Mode
The SPI operates in Master mode when the Master bit, MSTR (1) , in the SPCON register
is set. Only one Master SPI device can initiate transmissions. Software begins the transmission from a Master SPI Module by writing to the Serial Peripheral Data Register
(SPDAT). If the shift register is empty, the Byte is immediately transferred to the shift
register. The Byte begins shifting out on MOSI pin under the control of the serial clock,
SCK. Simultaneously, another Byte shifts in from the Slave on the Master’s MISO pin.
The transmission ends when the Serial Peripheral transfer data flag, SPIF, in SPSTA
becomes set. At the same time that SPIF becomes set, the received Byte from the Slave
is transferred to the receive data register in SPDAT. Software clears SPIF by reading
the Serial Peripheral Status register (SPSTA) with the SPIF bit set, and then reading the
SPDAT.
Slave Mode
The SPI operates in Slave mode when the Master bit, MSTR (2), in the SPCON register is
cleared. Before a data transmission occurs, the Slave Select pin, SS, of the Slave
device must be set to ’0’. SS must remain low until the transmission is complete.
In a Slave SPI Module, data enters the shift register under the control of the SCK from
the Master SPI Module. After a Byte enters the shift register, it is immediately transferred to the receive data register in SPDAT, and the SPIF bit is set. To prevent an
overflow condition, Slave software must then read the SPDAT before another Byte
enters the shift register (3). A Slave SPI must complete the write to the SPDAT (shift register) at least one bus cycle before the Master SPI starts a transmission. If the write to
the data register is late, the SPI transmits the data already in the shift register from the
previous transmission. The maximum SCK frequency allowed in slave mode is FCLK PERIPH
/4.
Transmission Formats
Software can select any of four combinations of serial clock (SCK) phase and polarity
using two bits in the SPCON: the Clock Polarity (CPOL (4) ) and the Clock Phase
(CPHA4). CPOL defines the default SCK line level in idle state. It has no significant
effect on the transmission format. CPHA defines the edges on which the input data are
sampled and the edges on which the output data are shifted (Figure 32 and Figure 33).
The clock phase and polarity should be identical for the Master SPI device and the communicating Slave device.
1.
The SPI Module should be configured as a Master before it is enabled (SPEN set). Also,
the Master SPI should be configured before the Slave SPI.
2.
3.
The SPI Module should be configured as a Slave before it is enabled (SPEN set).
The maximum frequency of the SCK for an SPI configured as a Slave is the bus clock
speed.
Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN = ’0’).
4.
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Figure 32. Data Transmission Format (CPHA = 0)
SCK Cycle Number
1
2
3
4
5
6
7
8
MSB
bit6
bit5
bit4
bit3
bit2
bit1
LSB
bit6
bit5
bit4
bit3
bit2
bit1
LSB
SPEN (Internal)
SCK (CPOL = 0)
SCK (CPOL = 1)
MOSI (from Master)
MISO (from Slave)
MSB
SS (to Slave)
Capture Point
Figure 33. Data Transmission Format (CPHA = 1)
1
2
3
4
5
6
7
8
MOSI (from Master)
MSB
bit6
bit5
bit4
bit3
bit2
bit1
LSB
MISO (from Slave)
MSB
bit6
bit5
bit4
bit3
bit2
bit1
SCK Cycle Number
SPEN (Internal)
SCK (CPOL = 0)
SCK (CPOL = 1)
LSB
SS (to Slave)
Capture Point
Figure 34. CPHA/SS Timing
MISO/MOSI
Byte 1
Byte 2
Byte 3
Master SS
Slave SS
(CPHA = 0)
Slave SS
(CPHA = 1)
As shown in Figure 32, the first SCK edge is the MSB capture strobe. Therefore, the
Slave must begin driving its data before the first SCK edge, and a falling edge on the SS
pin is used to start the transmission. The SS pin must be toggled high and then low
between each Byte transmitted (Figure 34).
Figure 33 shows an SPI transmission in which CPHA is ’1’. In this case, the Master
begins driving its MOSI pin on the first SCK edge. Therefore, the Slave uses the first
SCK edge as a start transmission signal. The SS pin can remain low between transmissions (Figure 34). This format may be preferred in systems having only one Master and
only one Slave driving the MISO data line.
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Error Conditions
The following flags in the SPSTA signal SPI error conditions:
Mode Fault (MODF)
Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS)
pin is inconsistent with the actual mode of the device. MODF is set to warn that there
may be a multi-master conflict for system control. In this case, the SPI system is
affected in the following ways:
•
An SPI receiver/error CPU interrupt request is generated
•
The SPEN bit in SPCON is cleared. This disables the SPI
•
The MSTR bit in SPCON is cleared
When SS Disable (SSDIS) bit in the SPCON register is cleared, the MODF flag is set
when the SS signal becomes ’0’.
However, as stated before, for a system with one Master, if the SS pin of the Master
device is pulled low, there is no way that another Master attempts to drive the network.
In this case, to prevent the MODF flag from being set, software can set the SSDIS bit in
the SPCON register and therefore making the SS pin as a general-purpose I/O pin.
Clearing the MODF bit is accomplished by a read of SPSTA register with MODF bit set,
followed by a write to the SPCON register. SPEN Control bit may be restored to its original set state after the MODF bit has been cleared.
Write Collision (WCOL)
A Write Collision (WCOL) flag in the SPSTA is set when a write to the SPDAT register is
done during a transmit sequence.
WCOL does not cause an interruption, and the transfer continues uninterrupted.
Clearing the WCOL bit is done through a software sequence of an access to SPSTA
and an access to SPDAT.
Overrun Condition
An overrun condition occurs when the Master device tries to send several data Bytes
and the Slave devise has not cleared the SPIF bit issuing from the previous data Byte
transmitted. In this case, the receiver buffer contains the Byte sent after the SPIF bit was
last cleared. A read of the SPDAT returns this Byte. All others Bytes are lost.
This condition is not detected by the SPI peripheral.
SS Error Flag (SSERR)
A Synchronous Serial Slave Error occurs when SS goes high before the end of a
received data in slave mode. SSERR does not cause in interruption, this bit is cleared
by writing 0 to SPEN bit (reset of the SPI state machine).
Interrupts
Two SPI status flags can generate a CPU interrupt requests:
Table 47. SPI Interrupts
Flag
Request
SPIF (SP data transfer)
SPI Transmitter Interrupt request
MODF (Mode Fault)
SPI Receiver/Error Interrupt Request (if SSDIS = ’0’)
Serial Peripheral data transfer flag, SPIF: This bit is set by hardware when a transfer
has been completed. SPIF bit generates transmitter CPU interrupt requests.
Mode Fault flag, MODF: This bit becomes set to indicate that the level on the SS is
inconsistent with the mode of the SPI. MODF with SSDIS reset, generates receiver/error
CPU interrupt requests. When SSDIS is set, no MODF interrupt request is generated.
Figure 35 gives a logical view of the above statements.
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Figure 35. SPI Interrupt Requests Generation
SPIF
SPI Transmitter
CPU Interrupt Request
SPI
CPU Interrupt Request
MODF
SPI Receiver/error
CPU Interrupt Request
SSDIS
Registers
There are three registers in the Module that provide control, status and data storage functions. These registers
are describes in the following paragraphs.
Serial Peripheral Control
Register (SPCON)
•
The Serial Peripheral Control Register does the following:
•
Selects one of the Master clock rates
•
Configure the SPI Module as Master or Slave
•
Selects serial clock polarity and phase
•
Enables the SPI Module
•
Frees the SS pin for a general-purpose
Table 48 describes this register and explains the use of each bit
Table 48. SPCON Register
SPCON - Serial Peripheral Control Register (0C3H)
7
6
5
4
3
2
1
0
SPR2
SPEN
SSDIS
MSTR
CPOL
CPHA
SPR1
SPR0
Bit Number
Bit Mnemonic
7
SPR2
6
SPEN
Description
Serial Peripheral Rate 2
Bit with SPR1 and SPR0 define the clock rate.
Serial Peripheral Enable
Cleared to disable the SPI interface.
Set to enable the SPI interface.
SS Disable
Cleared to enable SS in both Master and Slave modes.
5
SSDIS
4
MSTR
Set to disable SS in both Master and Slave modes. In Slave mode,
this bit has no effect if CPHA =’0’. When SSDIS is set, no MODF
interrupt request is generated.
Serial Peripheral Master
Cleared to configure the SPI as a Slave.
Set to configure the SPI as a Master.
Clock Polarity
3
CPOL
Cleared to have the SCK set to ’0’ in idle state.
Set to have the SCK set to ’1’ in idle low.
Clock Phase
2
CPHA
Cleared to have the data sampled when the SCK leaves the idle
state (see CPOL).
Set to have the data sampled when the SCK returns to idle state (see
CPOL).
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Bit Number
Bit Mnemonic
SPR1
1
0
SPR0
Description
SPR2
SPR1
SPR0 Serial Peripheral Rate
0
0
0
FCLK PERIPH /2
0
0
1
FCLK PERIPH /4
0
1
0
FCLK PERIPH /8
0
1
1
FCLK PERIPH /16
1
0
0
FCLK PERIPH /32
1
0
1
FCLK PERIPH /64
1
1
0
FCLK PERIPH /128
1
1
1
Invalid
Reset Value = 0001 0100b
Not bit addressable
Serial Peripheral Status Register
(SPSTA)
The Serial Peripheral Status Register contains flags to signal the following conditions:
•
Data transfer complete
•
Write collision
•
Inconsistent logic level on SS pin (mode fault error)
Table 49 describes the SPSTA register and explains the use of every bit in the register.
Table 49. SPSTA Register
SPSTA - Serial Peripheral Status and Control register (0C4H)
7
6
5
4
3
2
1
0
SPIF
WCOL
SSERR
MODF
-
-
-
-
Bit
Number
Bit
Mnemonic Description
Serial Peripheral Data Transfer Flag
7
SPIF
Cleared by hardware to indicate data transfer is in progress or has been
approved by a clearing sequence.
Set by hardware to indicate that the data transfer has been completed.
Write Collision Flag
6
WCOL
Cleared by hardware to indicate that no collision has occurred or has been
approved by a clearing sequence.
Set by hardware to indicate that a collision has been detected.
Synchronous Serial Slave Error Flag
5
SSERR
Set by hardware when SS is de-asserted before the end of a received data.
Cleared by disabling the SPI (clearing SPEN bit in SPCON).
Mode Fault
4
MODF
Cleared by hardware to indicate that the SS pin is at appropriate logic level, or
has been approved by a clearing sequence.
Set by hardware to indicate that the SS pin is at inappropriate logic level.
3
-
2
-
Reserved
The value read from this bit is indeterminate. Do not set this bit
Reserved
The value read from this bit is indeterminate. Do not set this bit.
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Bit
Number
Bit
Mnemonic Description
1
-
0
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reset Value = 00X0 XXXXb
Not Bit addressable
Serial Peripheral DATa Register
(SPDAT)
The Serial Peripheral Data Register (Table 50) is a read/write buffer for the receive data
register. A write to SPDAT places data directly into the shift register. No transmit buffer is
available in this model.
A Read of the SPDAT returns the value located in the receive buffer and not the content
of the shift register.
Table 50. SPDAT Register
SPDAT - Serial Peripheral Data Register (0C5H)
7
6
5
4
3
2
1
0
R7
R6
R5
R4
R3
R2
R1
R0
Reset Value = Indeterminate
R7:R0: Receive data bits
SPCON, SPSTA and SPDAT registers may be read and written at any time while there
is no on-going exchange. However, special care should be taken when writing to them
while a transmission is on-going:
72
•
Do not change SPR2, SPR1 and SPR0
•
Do not change CPHA and CPOL
•
Do not change MSTR
•
Clearing SPEN would immediately disable the peripheral
•
Writing to the SPDAT will cause an overflow.
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
Interrupt System
The AT89C51RD2/ED2 has a total of 9 interrupt vectors: two external interrupts (INT0
and INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, SPI interrupt, Keyboard interrupt and the PCA global interrupt. These interrupts are shown in
Figure 36.
Figure 36. Interrupt Control System
High Priority
Interrupt
IPH, IPL
3
INT0
IE0
0
3
TF0
0
3
INT1
IE1
0
3
Interrupt
Polling
Sequence, Decreasing from
High to Low Priority
TF1
0
3
PCA IT
0
RI
TI
3
TF2
EXF2
3
0
0
3
KBD IT
0
3
SPI IT
0
Low Priority
Interrupt
Individual Enable
Global Disable
Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt Enable register (Table 54 and Table 56). This register also
contains a global disable bit, which must be cleared to disable all interrupts at once.
Each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing a bit in the Interrupt Priority register (Table 57) and in the
Interrupt Priority High register (Table 55 and Table 56) shows the bit values and priority
levels associated with each combination.
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4235E–8051–04/04
Registers
The PCA interrupt vector is located at address 0033H, the SPI interrupt vector is located
at address 004BH and Keyboard interrupt vector is located at address 003BH. All other
vectors addresses are the same as standard C52 devices.
Table 51. Priority Level Bit Values
IPH.x
IPL.x
Interrupt Level Priority
0
0
0 (Lowest)
0
1
1
1
0
2
1
1
3 (Highest)
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another
low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt
source.
If two interrupt requests of different priority levels are received simultaneously, the
request of higher priority level is serviced. If interrupt requests of the same priority level
are received simultaneously, an internal polling sequence determines which request is
serviced. Thus within each priority level there is a second priority structure determined
by the polling sequence.
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AT89C51RD2/ED2
Interrupt Sources and
Vector Addresses
Table 52. Interrupt Sources and Vector Addresses
Interrupt
Request
Vector
Number
Polling Priority
Interrupt Source
Address
0
0
Reset
1
1
INT0
IE0
0003h
2
2
Timer 0
TF0
000Bh
3
3
INT1
IE1
0013h
4
4
Timer 1
IF1
001Bh
5
6
UART
RI+TI
0023h
6
7
Timer 2
TF2+EXF2
002Bh
7
5
PCA
CF + CCFn (n = 0 - 4)
0033h
8
8
Keyboard
KBDIT
003Bh
9
9
-
-
0043h
10
10
SPI
SPIIT
004Bh
0000h
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Table 53. IENO Register
IEN0 - Interrupt Enable Register (A8h)
7
6
5
4
3
2
1
0
EA
EC
ET2
ES
ET1
EX1
ET0
EX0
Bit
Number
Bit
Mnemonic Description
7
EA
6
EC
Enable All interrupt bit
Cleared to disable all interrupts.
Set to enable all interrupts.
PCA interrupt enable bit
Cleared to disable.
Set to enable.
5
ET2
Timer 2 overflow interrupt Enable bit
Cleared to disable timer 2 overflow interrupt.
Set to enable timer 2 overflow interrupt.
4
ES
Serial port Enable bit
Cleared to disable serial port interrupt.
Set to enable serial port interrupt.
3
ET1
Timer 1 overflow interrupt Enable bit
Cleared to disable timer 1 overflow interrupt.
Set to enable timer 1 overflow interrupt.
2
EX1
External interrupt 1 Enable bit
Cleared to disable external interrupt 1.
Set to enable external interrupt 1.
1
ET0
Timer 0 overflow interrupt Enable bit
Cleared to disable timer 0 overflow interrupt.
Set to enable timer 0 overflow interrupt.
0
EX0
External interrupt 0 Enable bit
Cleared to disable external interrupt 0.
Set to enable external interrupt 0.
Reset Value = 0000 0000b
Bit addressable
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Table 54. IPL0 Register
IPL0 - Interrupt Priority Register (B8h)
7
6
5
4
3
2
1
0
-
PPCL
PT2L
PSL
PT1L
PX1L
PT0L
PX0L
Bit
Number
Bit
Mnemonic Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
7
-
6
PPCL
PCA interrupt Priority bit
Refer to PPCH for priority level.
5
PT2L
Timer 2 overflow interrupt Priority bit
Refer to PT2H for priority level.
4
PSL
Serial port Priority bit
Refer to PSH for priority level.
3
PT1L
Timer 1 overflow interrupt Priority bit
Refer to PT1H for priority level.
2
PX1L
External interrupt 1 Priority bit
Refer to PX1H for priority level.
1
PT0L
Timer 0 overflow interrupt Priority bit
Refer to PT0H for priority level.
0
PX0L
External interrupt 0 Priority bit
Refer to PX0H for priority level.
Reset Value = X000 0000b
Bit addressable
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Table 55. IPH0 Register
IPH0 - Interrupt Priority High Register (B7h)
7
6
5
4
3
2
1
0
-
PPCH
PT2H
PSH
PT1H
PX1H
PT0H
PX0H
Bit
Number
7
6
5
4
3
2
1
0
Bit
Mnemonic Description
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
PPCH
PCA interrupt Priority high bit.
PPCH
PPCL
Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PT2H
Timer 2 overflow interrupt Priority High bit
PT2H
PT2L
Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PSH
Serial port Priority High bit
PSH
PSL
Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PT1H
Timer 1 overflow interrupt Priority High bit
PT1H
PT1L
Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PX1H
External interrupt 1 Priority High bit
PX1H
PX1L
Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PT0H
Timer 0 overflow interrupt Priority High bit
PT0H
PT0L
Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PX0H
External interrupt 0 Priority High bit
PX0H
PX0L
Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
Reset Value = X000 0000b
Not bit addressable
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Table 56. IEN1 Register
IEN1 - Interrupt Enable Register (B1h)
7
6
5
4
3
2
1
0
-
-
-
-
-
ESPI
-
KBD
Bit
Number
Bit
Mnemonic Description
7
-
Reserved
6
-
Reserved
5
-
Reserved
4
-
Reserved
3
-
Reserved
2
ESPI
SPI interrupt Enable bit
Cleared to disable SPI interrupt.
Set to enable SPI interrupt.
1
0
Reserved
KBD
Keyboard interrupt Enable bit
Cleared to disable keyboard interrupt.
Set to enable keyboard interrupt.
Reset Value = XXXX X000b
Bit addressable
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Table 57. IPL1 Register
IPL1 - Interrupt Priority Register (B2h)
7
6
5
4
3
2
1
0
-
-
-
-
-
SPIL
TWIL
KBDL
Bit
Number
Bit
Mnemonic Description
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2
SPIL
1
-
0
KBDL
SPI interrupt Priority bit
Refer to SPIH for priority level.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Keyboard interrupt Priority bit
Refer to KBDH for priority level.
Reset Value = XXXX X000b
Bit addressable
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AT89C51RD2/ED2
Table 58. IPH1 Register
IPH1 - Interrupt Priority High Register (B3h)
7
6
5
4
3
2
1
0
-
-
-
-
-
SPIH
-
KBDH
Bit
Number
Bit
Mnemonic Description
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2
SPIH
1
-
0
KBDH
SPI interrupt Priority High bit
SPIH
SPIL
Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Keyboard interrupt Priority High bit
KB DH
KBDL
Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
Reset Value = XXXX X000b
Not bit addressable
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Power Management
Introduction
Two power reduction modes are implemented in the AT89C51RD2/ED2. The Idle mode
and the Power-Down mode. These modes are detailed in the following sections. In addition to these power reduction modes, the clocks of the core and peripherals can be
dynamically divided by 2 using the X2 mode detailed in Section “Enhanced Features”,
page 17.
Idle Mode
Idle mode is a power reduction mode that reduces the power consumption. In this mode,
program execution halts. Idle mode freezes the clock to the CPU at known states while
the peripherals continue to be clocked. The CPU status before entering Idle mode is
preserved, i.e., the program counter and program status word register retain their data
for the duration of Idle mode. The contents of the SFRs and RAM are also retained. The
status of the Port pins during Idle mode is detailed in Table 59.
Entering Idle Mode
To e nt e r Id le mo d e , se t th e I DL bit in P C O N re g is te r (s e e Ta b le 6 0 ) . Th e
AT89C51RD2/ED2 enters Idle mode upon execution of the instruction that sets IDL bit.
The instruction that sets IDL bit is the last instruction executed.
Note:
Exiting Idle Mode
If IDL bit and PD bit are set simultaneously, the AT89C51RD2/ED2 enters Power-Down
mode. Then it does not go in Idle mode when exiting Power-Down mode.
There are two ways to exit Idle mode:
1. Generate an enabled interrupt.
–
Hardware clears IDL bit in PCON register which restores the clock to the
CPU. Execution resumes with the interrupt service routine. Upon completion
of the interrupt service routine, program execution resumes with the
instruction immediately following the instruction that activated Idle mode.
The general purpose flags (GF1 and GF0 in PCON register) may be used to
indicate whether an interrupt occurred during normal operation or during Idle
mode. When Idle mode is exited by an interrupt, the interrupt service routine
may examine GF1 and GF0.
2. Generate a reset.
–
Note:
Power-Down Mode
82
A logic high on the RST pin clears IDL bit in PCON register directly and
asynchronously. This restores the clock to the CPU. Program execution
momentarily resumes with the instruction immediately following the
instruction that activated the Idle mode and may continue for a number of
clock cycles before the internal reset algorithm takes control. Reset
initializes the AT89C51RD2/ED2 and vectors the CPU to address C:0000h.
During the time that execution resumes, the internal RAM cannot be accessed; however,
it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port
pins, the instruction immediately following the instruction that activated Idle mode should
not write to a Port pin or to the external RAM.
The Power-Down mode places the AT89C51RD2/ED2 in a very low power state.
Power-Down mode stops the oscillator, freezes all clock at known states. The CPU status prior to entering Power-Down mode is preserved, i.e., the program counter, program
status word register retain their data for the duration of Power-Down mode. In addition,
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
the SFR and RAM contents are preserved. The status of the Port pins during PowerDown mode is detailed in Table 59.
Note:
Entering Power-Down Mode
VCC may be reduced to as low as VRET during Power-Down mode to further reduce
power dissipation. Take care, however, that VDD is not reduced until Power-Down mode
is invoked.
To enter Power-Down mode, set PD bit in PCON register. The AT89C51RD2/ED2
enters the Power-Down mode upon execution of the instruction that sets PD bit. The
instruction that sets PD bit is the last instruction executed.
Exiting Power-Down Mode
Note:
If VCC was reduced during the Power-Down mode, do not exit Power-Down mode until
VCC is restored to the normal operating level.
There are two ways to exit the Power-Down mode:
1. Generate an enabled external interrupt.
–
The AT89C51RD2/ED2 provides capability to exit from Power-Down using
INT0#, INT1#.
Hardware clears PD bit in PCON register which starts the oscillator and
restores the clocks to the CPU and peripherals. Using INTx# input,
execution resumes when the input is released (see Figure 37). Execution
resumes with the interrupt service routine. Upon completion of the interrupt
service routine, program execution resumes with the instruction immediately
following the instruction that activated Power-Down mode.
Note:
The external interrupt used to exit Power-Down mode must be configured as level sensitive (INT0# and INT1#) and must be assigned the highest priority. In addition, the
duration of the interrupt must be long enough to allow the oscillator to stabilize. The execution will only resume when the interrupt is deasserted.
Note:
Exit from power-down by external interrupt does not affect the SFRs nor the internal RAM
content.
Figure 37. Power-Down Exit Waveform Using INT1:0#
INT1:0#
OSC
Active phase
Power-down phase
Oscillator restart phase
Active phase
2. Generate a reset.
–
Note:
A logic high on the RST pin clears PD bit in PCON register directly and
asynchronously. This starts the oscillator and restores the clock to the CPU
and peripherals. Program execution momentarily resumes with the
instruction immediately following the instruction that activated Power-Down
mode and may continue for a number of clock cycles before the internal
reset algorithm takes control. Reset initializes the AT89C51RD2/ED2 and
vectors the CPU to address 0000h.
During the time that execution resumes, the internal RAM cannot be accessed; however,
it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port
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pins, the instruction immediately following the instruction that activated the Power-Down
mode should not write to a Port pin or to the external RAM.
Note:
Exit from power-down by reset redefines all the SFRs, but does not affect the internal
RAM content.
Table 59. Pin Conditions in Special Operating Modes
84
Mode
Port 0
Port 1
Port 2
Port 3
Port 4
ALE
PSEN#
Reset
Floating
High
High
High
High
High
High
Idle
(internal
code)
Data
Data
Data
Data
Data
High
High
Idle
(external
code)
Floating
Data
Data
Data
Data
High
High
PowerDown
(internal
code)
Data
Data
Data
Data
Data
Low
Low
PowerDown
(external
code)
Floating
Data
Data
Data
Data
Low
Low
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AT89C51RD2/ED2
Registers
Table 60. PCON Register
PCON (S87:h) Power configuration Register
7
6
5
4
3
2
1
0
-
-
-
-
GF1
GF0
PD
IDL
Bit
Number
Bit
Mnemonic Description
Reserved
The value read from these bits is indeterminate. Do not set these bits.
7-4
-
3
GF1
General Purpose flag 1
One use is to indicate whether an interrupt occurred during normal operation or
during Idle mode.
2
GF0
General Purpose flag 0
One use is to indicate whether an interrupt occurred during normal operation or
during Idle mode.
PD
Power-Down Mode bit
Cleared by hardware when an interrupt or reset occurs.
Set to activate the Power-Down mode.
If IDL and PD are both set, PD takes precedence.
IDL
Idle Mode bit
Cleared by hardware when an interrupt or reset occurs.
Set to activate the Idle mode.
If IDL and PD are both set, PD takes precedence.
1
0
Reset Value= XXXX 0000b
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Hardware Watchdog
Timer
The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the Watchdog Timer
ReSeT (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable
the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location
0A6H. When WDT is enabled, it will increment every machine cycle while the oscillator
is running and there is no way to disable the WDT except through reset (either hardware
reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH
pulse at the RST-pin.
Using the WDT
To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR
location 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH
and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when it
reaches 16383 (3FFFH) and this will reset the device. When WDT is enabled, it will
increment every machine cycle while the oscillator is running. This means the user must
reset the WDT at least every 16383 machine cycle. To reset the WDT the user must
write 01EH and 0E1H to WDTRST. WDTRST is a write only register. The WDT counter
cannot be read or written. When WDT overflows, it will generate an output RESET pulse
at the RST-pin. The RESET pulse duration is 96 x TCLK PERIPH, where T CLK PERIPH= 1/FCLK
PERIPH. To make the best use of the WDT, it should be serviced in those sections of code
that will periodically be executed within the time required to prevent a WDT reset.
To have a more powerful WDT, a 27 counter has been added to extend the Time-out
capability, ranking from 16 ms to 2s @ FOSCA = 12 MHz. To manage this feature, refer to
WDTPRG register description, Table 61. The WDTPRG register should be configured
before the WDT activation sequence, and can not be modified until next reset.
Table 61. WDTRST Register
WDTRST - Watchdog Reset Register (0A6h)
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
Reset Value = XXXX XXXXb
Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in
sequence.
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Table 62. WDTPRG Register
WDTPRG - Watchdog Timer Out Register (0A7h)
7
6
5
4
3
2
1
0
-
-
-
-
-
S2
S1
S0
Bit
Number
Bit
Mnemonic Description
7
-
6
-
5
-
4
-
3
-
2
S2
WDT Time-out select bit 2
1
S1
WDT Time-out select bit 1
0
S0
WDT Time-out select bit 0
Reserved
The value read from this bit is undetermined. Do not try to set this bit.
S2 S1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
S0
0
1
0
1
0
1
0
1
Selected Time-out
(214 - 1) machine cycles, 16. 3 ms @ FOSCA =12 MHz
(215 - 1) machine cycles, 32.7 ms @ FOSCA=12 MHz
(216 - 1) machine cycles, 65. 5 ms @ FOSCA =12 MHz
(217 - 1) machine cycles, 131 ms @ FOSCA=12 MHz
(218 - 1) machine cycles, 262 ms @ FOSCA=12 MHz
(219 - 1) machine cycles, 542 ms @ FOSCA=12 MHz
(220 - 1) machine cycles, 1.05 ms @ FOSCA=12 MHz
(221 - 1) machine cycles, 2.09 ms @ FOSCA=12 MHz
Reset Value = XXXX X000
WDT during Power-down In Power-down mode the oscillator stops, which means the WDT also stops. While in
Power-down mode the user does not need to service the WDT. There are 2 methods of
and Idle
exiting Power-down mode: by a hardware reset or via a level activated external interrupt
which is enabled prior to entering Power-down mode. When Power-down is exited with
hardware reset, servicing the WDT should occur as it normally should whenever the
AT89C51RD2/ED2 is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the
interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the
device while the interrupt pin is held low, the WDT is not started until the interrupt is
pulled high. It is suggested that the WDT be reset during the interrupt service routine.
To ensure that the WDT does not overflow within a few states of exiting of powerdown, it
is better to reset the WDT just before entering powerdown.
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the
AT89C51RD2/ED2 while in Idle mode, the user should always set up a timer that will
periodically exit Idle, service the WDT, and re-enter Idle mode.
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ONCE® Mode (ONChip Emulation)
The ONCE mode facilitates testing and debugging of systems using AT89C51RD2/ED2
without removing the circuit from the board. The ONCE mode is invoked by driving certain pins of the AT89C51RD2/ED2; the following sequence must be exercised:
•
Pull ALE low while the device is in reset (RST high) and PSEN is high.
•
Hold ALE low as RST is deactivated.
While the AT89C51RD2/ED2 is in ONCE mode, an emulator or test CPU can be used to
drive the circuit. Table 63 shows the status of the port pins during ONCE mode.
Normal operation is restored when normal reset is applied.
Table 63. External Pin Status During ONCE Mode
88
ALE
PSEN
Port 0
Port 1
Port 2
Port 3
Port I2
XTALA1/2
XTALB1/2
Weak
pull-up
Weak
pull-up
Float
Weak
pull-up
Weak
pull-up
Weak
pull-up
Float
Active
Active
AT89C51RD2/ED2
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AT89C51RD2/ED2
Power-off Flag
The power-off flag allows the user to distinguish between a “cold start” reset and a
“warm start” reset.
A cold start reset is the one induced by VCC switch-on. A warm start reset occurs while
VCC is still applied to the device and could be generated for example by an exit from
power-down.
The power-off flag (POF) is located in PCON register (Table 64). POF is set by hardware when VCC rises from 0 to its nominal voltage. The POF can be set or cleared by
software allowing the user to determine the type of reset.
Table 64. PCON Register
PCON - Power Control Register (87h)
7
6
5
4
3
2
1
0
SMOD1
SMOD0
-
POF
GF1
GF0
PD
IDL
Bit
Number
Bit
Mnemonic Description
7
SMOD1
Serial port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
6
SMOD0
Serial port Mode bit 0
Cleared to select SM0 bit in SCON register.
Set to select FE bit in SCON register.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
POF
Power-Off Flag
Cleared by software to recognize the next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by
software.
3
GF1
General-purpose Flag
Cleared by user for general-purpose usage.
Set by user for general-purpose usage.
2
GF0
General-purpose Flag
Cleared by user for general-purpose usage.
Set by user for general-purpose usage.
1
PD
Power-down mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
0
IDL
Idle mode bit
Cleared by hardware when interrupt or reset occurs.
Set to enter idle mode.
Reset Value = 00X1 0000b
Not bit addressable
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Reduced EMI Mode
The ALE signal is used to demultiplex address and data buses on port 0 when used with
external program or data memory. Nevertheless, during internal code execution, ALE
signal is still generated. In order to reduce EMI, ALE signal can be disabled by setting
AO bit.
The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no
longer output but remains active during MOVX and MOVC instructions and external
fetches. During ALE disabling, ALE pin is weakly pulled high.
Table 65. AUXR Register
AUXR - Auxiliary Register (8Eh)
7
6
5
4
3
2
1
0
DPU
-
M0
XRS2
XRS1
XRS0
EXTRAM
AO
Bit
Number
Bit
Mnemonic Description
Disable Weak Pull-up
7
DPU
Cleared by software to activate the permanent weak pull-up (default)
Set by software to disable the weak pull-up (reduce power consumption)
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Pulse length
5
M0
Cleared to stretch MOVX control: the RD and the WR pulse length is 6 clock
periods (default).
Set to stretch MOVX control: the RD and the WR pulse length is 30 clock periods.
4
XRS2
XRAM Size
3
XRS1
XRS2
0
2
XRS0
XRS1
0
XRS0
0
XRAM size
256 bytes
0
0
1
512 bytes
0
1
0
768 bytes(default)
0
1
1
1024 bytes
1
0
0
1792 bytes
EXTRAM bit
Cleared to access internal XRAM using MOVX @ Ri/ @ DPTR.
1
EXTRAM
Set to access external memory.
Programmed by hardware after Power-up regarding Hardware Security Byte
(HSB), default setting, XRAM selected.
0
AO
ALE Output bit
Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if
X2 mode is used) (default). Set, ALE is active only during a MOVX or MOVC
instruction is used.
Reset Value = XX00 10’HSB. XRAM’0b
Not bit addressable
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EEPROM Data
Memory
This feature is available only for the AT89C51ED2 device.
The 2K bytes on-chip EEPROM memory block is located at addresses 0000h to 07FFh
of the XRAM/ERAM memory space and is selected by setting control bits in the EECON
register.
A read or write access to the EEPROM memory is done with a MOVX instruction.
Write Data
Data is written by byte to the EEPROM memory block as for an external RAM memory.
The following procedure is used to write to the EEPROM memory:
•
Check EEBUSY flag
•
If the user application interrupts routines use XRAM memory space: Save and
disable interrupts.
•
Load DPTR with the address to write
•
Store A register with the data to be written
•
Set bit EEE of EECON register
•
Execute a MOVX @DPTR, A
•
Clear bit EEE of EECON register
•
Restore interrupts.
•
EEBUSY flag in EECON is then set by hardware to indicate that programming is in
progress and that the EEPROM segment is not available for reading or writing.
•
The end of programming is indicated by a hardware clear of the EEBUSY flag.
Figure 38 represents the optimal write sequence to the on-chip EEPROM data memory.
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Figure 38. Recommended EEPROM Data Write Sequence
EEPROM Data Write
Sequence
EEBusy
Cleared?
Save & Disable IT
EA= 0
EEPROM Data Mapping
EECON = 02h (EEE=1)
Data Write
DPTR= Address
ACC= Data
Exec: MOVX @DPTR, A
EEPROM Mapping
EECON = 00h (EEE=0)
Restore IT
Last Byte
to Load?
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Read Data
The following procedure is used to read the data stored in the EEPROM memory:
•
Check EEBUSY flag
•
If the user application interrupts routines use XRAM memory space: Save and
disable interrupts.
•
Load DPTR with the address to read
•
Set bit EEE of EECON register
•
Execute a MOVX A, @DPTR
•
Clear bit EEE of EECON register
•
Restore interrupts.
Figure 39. Recommended EEPROM Data Read Sequence
EEPROM Data Read
Sequence
EEBusy
Cleared?
Save & Disable IT
EA= 0
EEPROM Data Mapping
EECON = 02h (EEE=1)
Data Read
DPTR= Address
ACC= Data
Exec: MOVX A, @DPTR
Last Byte
to Read?
EEPROM Data Mapping
EECON = 00h (EEE = 0
Restore IT
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Registers
Table 66. EECON Register
EECON (0D2h)
EEPROM Control Register
7
6
5
4
3
2
1
0
-
-
-
-
-
-
EEE
EEBUSY
Bit Number
Bit
Mnemonic
7-2
-
1
EEE
Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Enable EEPROM Space bit
Set to map the EEPROM space during MOVX instructions (Write or Read to
the EEPROM.
Clear to map the XRAM space during MOVX.
0
EEBUSY
Programming Busy flag
Set by hardware when programming is in progress.
Cleared by hardware when programming is done.
Can not be set or cleared by software.
Reset Value = XXXX XX00b
Not bit addressable
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Flash/EEPROM
Memory
The Flash memory increases EEPROM and ROM functionality with in-circuit electrical
erasure and programming. It contains 64K bytes of program memory organized respectively in 512 pages of 128 bytes. This memory is both parallel and serial In-System
Programmable (ISP). ISP allows devices to alter their own program memory in the
actual end product under software control. A default serial loader (bootloader) program
allows ISP of the Flash.
The programming does not require external dedicated programming voltage. The necessary high programming voltage is generated on-chip using the standard VCC pins of
the microcontroller.
Features
Flash Programming and
Erasure
•
Flash EEPROM Internal Program Memory
•
Boot vector allows user provided Flash loader code to reside anywhere in the Flash
memory space. This configuration provides flexibility to the user.
•
Default loader in Boot ROM allows programming via the serial port without the need
of a user provided loader.
•
Up to 64K bytes external program memory if the internal program memory is
disabled (EA = 0).
•
Programming and erasing voltage with standard power supply
•
Read/Programming/Erase:
–
Byte-wise read without wait state
–
Byte or page erase and programming (10 ms)
•
Typical programming time (64K bytes) is 22s with on chip serial bootloader
•
Parallel programming with 87C51 compatible hardware interface to programmer
•
Programmable security for the code in the Flash
•
100K write cycles
•
10 years data retention
The 64-K byte Flash is programmed by bytes or by pages of 128 bytes. It is not necessary to erase a byte or a page before programming. The programming of a byte or a
page includes a self erase before programming.
There are three methods of programming the Flash memory:
1. The on-chip ISP bootloader may be invoked which will use low level routines to
program the pages. The interface used for serial downloading of Flash is the
UART.
2. The Flash may be programmed or erased in the end-user application by calling
low-level routines through a common entry point in the Boot ROM.
3. The Flash may be programmed using the parallel method by using a conventional EPROM programmer. The parallel programming method used by these
devices is similar to that used by EPROM 87C51 but it is not identical and the
commercially available programmers need to have support for the
AT89C51RD2/ED2. The bootloader and the Application Programming Interface
(API) routines are located in the BOOT ROM.
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Flash Registers and
Memory Map
Hardware Register
The AT89C51RD2/ED2 Flash memory uses several registers for its management:
•
Hardware registers can only be accessed through the parallel programming modes
which are handled by the parallel programmer.
•
Software registers are in a special page of the Flash memory which can be
accessed through the API or with the parallel programming modes. This page,
called "Extra Flash Memory", is not in the internal Flash program memory
addressing space.
The only hardware register of the AT89C51RD2/ED2 is called Hardware Security Byte
(HSB).
Table 67. Hardware Security Byte (HSB)
7
6
5
4
3
2
1
0
X2
BLJB
OSC
-
XRAM
LB2
LB1
LB0
Bit
Number
7
Bit
Mnemonic
X2
Description
X2 Mode
Programmed (‘0’ value) to force X2 mode (6 clocks per instruction) after reset.
Unprogrammed (‘1’ Value) to force X1 mode, Standard Mode, after reset
(Default).
Boot Loader Jump Bit
6
BLJB
Unprogrammed (‘1’ value) to start the user’s application on next reset at address
0000h.
Programmed (‘0’ value) to start the boot loader at address F800h on next reset
(Default).
Oscillator Bit
5
OSC
Programmed to allow oscillator B at startup
Unprogrammed this bit to allow oscillator A at startup (Default).
4
-
3
XRAM
Reserved
XRAM config bit (only programmable by programmer tools)
Programmed to inhibit XRAM.
Unprogrammed, this bit to valid XRAM (Default).
2-0
LB2-0
User Memory Lock Bits (only programmable by programmer tools)
See Table 68
Boot Loader Jump Bit (BLJB)
One bit of the HSB, the BLJB bit, is used to force the boot address:
Flash Memory Lock Bits
96
•
When this bit is programmed (‘1’ value) the boot address is 0000h.
•
When this bit is unprogrammed (‘1’ value) the boot address is F800h. By default,
this bit is unprogrammed and the ISP is enabled.
The three lock bits provide different levels of protection for the on-chip code and data
when programmed as shown in Table 68.
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AT89C51RD2/ED2
Table 68. Program Lock Bits
Program Lock Bits
Security
Level
LB0
LB1
LB2
1
U
U
U
2
P
U
U
Protection Description
No program lock features enabled.
MOVC instruction executed from external program memory is disabled
from fetching code bytes from internal memory, EA is sampled and
latched on reset, and further parallel programming of the on chip code
memory is disabled.
ISP and software programming with API are still allowed.
3
X
P
U
Same as 2, also verify code memory through parallel programming
interface is disabled.
4
X
X
P
Same as 3, also external execution is disabled (Default).
Note:
U: Unprogrammed or "one" level.
P: Programmed or "zero" level.
X: Do not care
WARNING: Security level 2 and 3 should only be programmed after Flash and code
verification.
These security bits protect the code access through the parallel programming interface.
They are set by default to level 4. The code access through the ISP is still possible and
is controlled by the "software security bits" which are stored in the extra Flash memory
accessed by the ISP firmware.
To load a new application with the parallel programmer, a chip erase must first be done.
This will set the HSB in its inactive state and will erase the Flash memory. The part reference can always be read using Flash parallel programming modes.
Default Values
Software Registers
The default value of the HSB provides parts ready to be programmed with ISP:
•
BLJB: Programmed force ISP operation.
•
X2: Unprogrammed to force X1 mode (Standard Mode).
•
XRAM: Unprogrammed to valid XRAM
•
LB2-0: Security level four to protect the code from a parallel access with maximum
security.
Several registers are used in factory and by parallel programmers. These values are
used by Atmel ISP.
These registers are in the "Extra Flash Memory" part of the Flash memory. This block is
also called "XAF" or eXtra Array Flash. They are accessed in the following ways:
•
Commands issued by the parallel memory programmer.
•
Commands issued by the ISP software.
•
Calls of API issued by the application software.
Several software registers are described in Table 69.
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Table 69. Default Values
Mnemonic
Definition
Default value
Description
SBV
Software Boot Vector
FCh
BSB
Boot Status Byte
0FFh
SSB
Software Security Byte
FFh
Copy of the Manufacturer Code
58h
Atmel
Copy of the Device ID #1: Family Code
D7h
C51 X2, Electrically Erasable
Copy of the Device ID #2: Memories Size
and Type
ECh
AT89C51RD2/ED2 64KB
Copy of the Device ID #3: Name and
Revision
EFh
AT89C51RD2/ED2 64KB,
Revision 0
After programming the part by ISP, the BSB must be cleared (00h) in order to allow the
application to boot at 0000h.
The content of the Software Security Byte (SSB) is described in Table 70 and Table 71.
To assure code protection from a parallel access, the HSB must also be at the required
level.
Table 70. Software Security Byte
7
6
5
4
3
2
1
0
-
-
-
-
-
-
LB1
LB0
Bit
Number
Bit
Mnemonic Description
7
-
Reserved
Do not clear this bit.
6
-
Reserved
Do not clear this bit.
5
-
Reserved
Do not clear this bit.
4
-
Reserved
Do not clear this bit.
3
-
Reserved
Do not clear this bit.
2
-
Reserved
Do not clear this bit.
1-0
LB1-0
User Memory Lock Bits
See Table 71
The two lock bits provide different levels of protection for the on-chip code and data,
when programmed as shown in Table 71.
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Table 71. Program Lock Bits of the SSB
Program Lock Bits
Security
Level
LB0
LB1
1
U
U
No program lock features enabled.
2
P
U
ISP programming of the Flash is disabled.
3
X
P
Same as 2, also verify through ISP programming interface is disabled.
Note:
Flash Memory Status
Protection Description
U: Unprogrammed or "one" level.
P: Programmed or "zero" level.
X: Do not care
WARNING: Security level 2 and 3 should only be programmed after Flash and code
verification.
AT89C51RD2/ED2 parts are delivered in standard with the ISP ROM bootloader.
After ISP or parallel programming, the possible contents of the Flash memory are summarized in Figure 40:
Figure 40. Flash Memory Possible Contents
FFFFh
Virgin
Application
Virgin
or
Application
Application
Dedicated
ISP
Virgin
or
Application
Virgin
or
Application
Dedicated
ISP
0000h
Default
Memory Organization
After ISP
After ISP
After Parallel
Programming
After Parallel
Programming
After Parallel
Programming
When the EA pin is high, the processor fetches instructions from internal program Flash.
If the EA pin is tied low, all program memory fetches are from external memory.
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Bootloader Architecture
Introduction
The bootloader manages communication according to a specifically defined protocol to
provide the whole access and service on Flash memory. Furthermore, all accesses and
routines can be called from the user application.
Figure 41. Diagram Context Description
Access Via
Specific
Protocol
Bootloader
Flash Memory
Access From
User
Application
Acronyms
ISP: In-System Programming
SBV: Software Boot Vector
BSB: Boot Status Byte
SSB: Software Security Bit
HW: Hardware Byte
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Functional Description
Figure 42. Bootloader Functional Description
External Host with
Specific Protocol
Communication
User
Application
User Call
Management (API)
ISP Communication
Management
Flash Memory
Management
Flash
Memory
On the above diagram, the on-chip bootloader processes are:
•
ISP Communication Management
The purpose of this process is to manage the communication and its protocol between
the on-chip bootloader and a external device. The on-chip ROM implements a serial
protocol (see section “Bootloader Protocol”). This process translate serial communication frame (UART) into Flash memory access (read, write, erase, etc.).
•
User Call Management
Several Application Program Interface (API) calls are available for use by an application
program to permit selective erasing and programming of Flash pages. All calls are made
through a common interface (API calls), included in the ROM bootloader. The programming functions are selected by setting up the microcontroller’s registers before making a
call to a common entry point (0xFFF0). Results are returned in the registers. The purpose on this process is to translate the registers values into internal Flash Memory
Management.
•
Flash Memory Management
This process manages low level access to Flash memory (performs read and write
access).
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Bootloader Functionality
The bootloader can be activated by two means: Hardware conditions or regular boot
process.
The Hardware conditions (EA = 1, PSEN = 0) during the Reset# falling edge force the
on-chip bootloader execution. This allows an application to be built that will normally
execute the end user’s code but can be manually forced into default ISP operation.
As PSEN is a an output port in normal operating mode after reset, user application
should take care to release PSEN after falling edge of reset signal. The hardware conditions are sampled at reset signal falling edge, thus they can be released at any time
when reset input is low.
To ensure correct microcontroller startup, the PSEN pin should not be tied to ground
during power-on (See Figure 43).
Figure 43. Hardware conditions typical sequence during power-on.
VCC
PSEN
RST
The on-chip bootloader boot process is shown Figure 44.
Table 72. Bootloader Process Description
Purpose
Hardware Conditions
The Hardware Conditions force the bootloader execution whatever
BLJB, BSB and SBV values.
The Boot Loader Jump Bit forces the application execution.
BLJB = 0 => Bootloader execution
BLJB = 1 => Application execution
BLJB
The BLJB is a fuse bit in the Hardware Byte.
It can be modified by hardware (programmer) or by software (API).
Note: The BLJB test is performed by hardware to prevent any
program execution.
SBV
The Software Boot Vector contains the high address of customer
bootloader stored in the application.
SBV = FCh (default value) if no customer bootloader in user Flash.
Note: The customer bootloader is called by JMP [SBV]00h
instruction.
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Boot Process
Figure 44. Bootloader Process
RESET
If BLJB = 0 then ENBOOT Bit (AUXR1) is Set
else ENBOOT Bit (AUXR1) is Cleared
Yes (PSEN = 0, EA = 1, and ALE =1 or Not Connected)
Hardware
Hardware
Condition?
FCON = 00h
FCON = F0h
BLJB = 1
ENBOOT = 0
BLJB!= 0
?
BLJB = 0
ENBOOT = 1
F800h
Software
FCON = 00h
?
Yes = Hardware Boot Conditions
BSB = 00h
?
PC = 0000h
User Application
SBV = FCh
?
USER BOOT LOADER
Atmel BOOT LOADER
PC= [SBV]00h
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ISP Protocol Description
Physical Layer
Frame Description
The UART used to transmit information has the following configuration:
•
Character: 8-bit data
•
Parity: none
•
Stop: 2 bits
•
Flow control: none
•
Baudrate: autobaud is performed by the bootloader to compute the baudrate
chosen by the host.
The Serial Protocol is based on the Intel Hex-type records.
Intel Hex records consist of ASCII characters used to represent hexadecimal values and
are summarized below.
Figure 45. Intel Hex Type Frame
•
Record
Mark
’:’
Reclen
Load
Offset
1-byte
1-byte
2-bytes
Record
Type
1-byte
Data
or
Info
n-bytes
Checksum
1-byte
Record Mark:
Record Mark is the start of frame. This field must contain ’:’.
•
Reclen:
Reclen specifies the number of bytes of information or data which follows the Record
Type field of the record.
•
Load Offset:
Load Offset specifies the 16-bit starting load offset of the data bytes, therefore this field
is used only for Data Program Record (see Section “ISP Commands Summary”).
•
Record Type:
Record Type specifies the command type. This field is used to interpret the remaining
information within the frame. The encoding for all the current record types is described
in Section “ISP Commands Summary”.
•
Data/Info:
Data/Info is a variable length field. It consists of zero or more bytes encoded as pairs of
hexadecimal digits. The meaning of data depends on the Record Type.
•
Checksum:
The two’s complement of the 8-bit bytes that result from converting each pair of ASCII
hexadecimal digits to one byte of binary, and including the Reclen field to and including
the last byte of the Data/Info field. Therefore, the sum of all the ASCII pairs in a record
after converting to binary, from the Reclen field to and including the Checksum field, is
zero.
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Functional Description
Software Security Bits (SSB)
The SSB protects any Flash access from ISP command.
The command "Program Software Security Bit" can only write a higher priority level.
There are three levels of security:
•
level 0: NO_SECURITY (FFh)
This is the default level.
From level 0, one can write level 1 or level 2.
•
level 1: WRITE_SECURITY (FEh)
For this level it is impossible to write in the Flash memory, BSB and SBV.
The Bootloader returns ’P’ on write access.
From level 1, one can write only level 2.
•
level 2: RD_WR_SECURITY (FCh
The level 2 forbids all read and write accesses to/from the Flash/EEPROM memory.
The Bootloader returns ’L’ on read or write access.
Only a full chip erase in parallel mode (using a programmer) or ISP command can reset
the software security bits.
From level 2, one cannot read and write anything.
Table 73. Software Security Byte Behavior
Level 0
Level 1
Level 2
Flash/EEPROM
Any access allowed
Read-only access allowed
Any access not allowed
Fuse Bit
Any access allowed
Read-only access allowed
Any access not allowed
BSB & SBV
Any access allowed
Read-only access allowed
Any access not allowed
SSB
Any access allowed
Write level 2 allowed
Read-only access allowed
Manufacturer
Info
Read-only access allowed
Read-only access allowed
Read-only access allowed
Bootloader Info
Read-only access allowed
Read-only access allowed
Read-only access allowed
Erase Block
Allowed
Not allowed
Not allowed
Full Chip Erase
Allowed
Allowed
Allowed
Blank Check
Allowed
Allowed
Allowed
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Full Chip Erase
The ISP command "Full Chip Erase" erases all user Flash memory (fills with FFh) and
sets some bytes used by the bootloader at their default values:
•
BSB = FFh
•
SBV = FCh
•
SSB = FFh
The Full Chip Erase does not affect the bootloader.
Checksum Error
When a checksum error is detected, send ‘X’ followed with CR&LF.
Flow Description
Overview
An initialization step must be performed after each Reset. After microcontroller reset,
the bootloader waits for an autobaud sequence (see section ‘Autobaud Performances’).
When the communication is initialized, the protocol depends on the record type
requested by the host.
FLIP, a software utility to implement ISP programming with a PC, is available from the
Atmel web site.
Communication Initialization
The host initializes the communication by sending a ’U’ character to help the bootloader
to compute the baudrate (autobaud).
Figure 46. Initialization
Bootloader
Host
106
Init Communication
"U"
If (Not Received "U")
Else
Communication Opened
"U"
Performs Autobaud
Sends Back “U” Character
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Autobaud Performances
The ISP feature allows a wide range of baud rates in the user application. It is also
adaptable to a wide range of oscillator frequencies. This is accomplished by measuring
the bit-time of a single bit in a received character. This information is then used to program the baud rate in terms of timer counts based on the oscillator frequency. The ISP
f e a tu r e r e q u ir e s th a t a n in itia l c h a ra c te r (a n u p p e rc a s e U ) b e se n t t o t h e
AT89C51RD2/ED2 to establish the baud rate. Table show the autobaud capability.
Table 74. Autobaud Performances
Frequency (MHz)
Baudrate (kHz)
1.8432
2
2.4576
3
3.6864
4
5
6
7.3728
2400
OK
OK
OK
OK
OK
OK
OK
OK
OK
4800
OK
-
OK
OK
OK
OK
OK
OK
OK
9600
OK
-
OK
OK
OK
OK
OK
OK
OK
19200
OK
-
OK
OK
OK
-
-
OK
OK
38400
-
-
OK
OK
-
OK
OK
OK
57600
-
-
-
-
OK
-
-
-
OK
115200
-
-
-
-
-
-
-
-
OK
Frequency (MHz)
Baudrate (kHz)
8
10
11.0592
12
14.746
16
20
24
26.6
2400
OK
OK
OK
OK
OK
OK
OK
OK
OK
4800
OK
OK
OK
OK
OK
OK
OK
OK
OK
9600
OK
OK
OK
OK
OK
OK
OK
OK
OK
19200
OK
OK
OK
OK
OK
OK
OK
OK
OK
38400
-
-
OK
OK
OK
OK
OK
OK
OK
57600
-
-
OK
-
OK
OK
OK
OK
OK
115200
-
-
OK
-
OK
-
-
-
-
Command Data Stream
Protocol
All commands are sent using the same flow. Each frame sent by the host is echoed by
the bootloader.
107
4235E–8051–04/04
Figure 47. Command Flow
Host
Sends First Character of the
Frame
Sends Frame (made of 2 ASCII
Characters Per Byte)
Echo Analysis
108
Bootloader
":"
":"
If (not received ":")
Else
Sends Echo and Start
Reception
Gets Frame, and Sends Back Echo
for Each Received Byte
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
Write/Program Commands
Description
This flow is common to the following frames:
•
Flash/EEPROM Programming Data Frame
•
EOF or Atmel Frame (only Programming Atmel Frame)
•
Config Byte Programming Data Frame
•
Baud Rate Frame
Figure 48. Write/Program Flow
Bootloader
Host
Write Command
Send Write Command
Wait Write Command
OR
Checksum Error
Wait Checksum Error
’X’ & CR & LF
Send Checksum Error
COMMAND ABORTED
NO_SECURITY
OR
Wait Security Error
’P’ & CR & LF
Send Security Error
COMMAND ABORTED
Wait Programming
’.’ & CR & LF
Wait COMMAND_OK
Send COMMAND_OK
COMMAND FINISHED
Example
Programming Data (write 55h at address 0010h in the Flash)
HOST
: 01 0010 00 55 9A
BOOTLOADER
: 01 0010 00 55 9A . CR LF
HOST
: 02 0000 03 05 01 F5
BOOTLOADER
: 02 0000 03 05 01 F5. CR LF
Programming Atmel function (write SSB to level 2)
Writing Frame (write BSB to 55h)
HOST
: 03 0000 03 06 00 55 9F
BOOTLOADER
: 03 0000 03 06 00 55 9F . CR LF
109
4235E–8051–04/04
Blank Check Command
Description
Figure 49. Blank Check Flow
Bootloader
Host
Blank Check Command
Send Blank Check Command
Wait Blank Check Command
OR
Checksum Error
’X’ & CR & LF
Wait Checksum Error
Send Checksum Error
COMMAND ABORTED
Flash Blank
OR
’.’ & CR & LF
Wait COMMAND_OK
Send COMMAND_OK
COMMAND FINISHED
address & CR & LF
Wait Address not
Erased
Send First Address
not Erased
COMMAND FINISHED
Example
Blank Check ok
HOST
: 05 0000 04 0000 7FFF 01 78
BOOTLOADER
: 05 0000 04 0000 7FFF 01 78 . CR LF
Blank Check ok at address xxxx
HOST
: 05 0000 04 0000 7FFF 01 78
BOOTLOADER
: 05 0000 04 0000 7FFF 01 78 xxxx CR LF
Blank Check with checksum error
110
HOST
: 05 0000 04 0000 7FFF 01 70
BOOTLOADER
: 05 0000 04 0000 7FFF 01 70 X CR LF CR LF
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
Display Data Description
Figure 50. Display Flow
Bootloader
Host
Display Command
Send Display Command
Wait Display Command
OR
Checksum error
Wait Checksum Error
’X’ & CR & LF
Send Checksum Error
COMMAND ABORTED
RD_WR_SECURITY
OR
Wait Security Error
’L’ & CR & LF
Send Security Error
COMMAND ABORTED
Read Data
All Data Read
Complet Frame
"Address = "
"Reading Value"
CR & LF
Wait Display Data
Send Display Data
All Data Read
All Data Read
COMMAND FINISHED
COMMAND FINISHED
Note:
The maximum size of block is 400h. To read more than 400h bytes, the Host must send a new command.
Example
Display data from address 0000h to 0020h
HOST
: 05 0000 04 0000 0020 00 D7
BOOTLOADER
: 05 0000 04 0000 0020 00 D7
BOOTLOADER
0000=-----data------ CR LF (16 data)
BOOTLOADER
0010=-----data------ CR LF (16 data)
BOOTLOADER
0020=data CR LF
( 1 data)
111
4235E–8051–04/04
Read Function Description
This flow is similar for the following frames:
•
Reading Frame
•
EOF Frame/ Atmel Frame (only reading Atmel Frame)
Figure 51. Read Flow
Bootloader
Host
Read Command
Send Read Command
Wait Read Command
OR
Checksum error
Wait Checksum Error
’X’ & CR & LF
Send Checksum error
COMMAND ABORTED
RD_WR_SECURITY
OR
Wait Security Error
’L’ & CR & LF
Send Security error
COMMAND ABORTED
Read Value
’value’ & ’.’ & CR & LF
Wait Value of Data
Send Data Read
COMMAND FINISHED
Example
Read function (read SBV)
HOST
: 02 0000 05 07 02 F0
BOOTLOADER
: 02 0000 05 07 02 F0 Value . CR LF
Atmel Read function (read Bootloader version)
112
HOST
: 02 0000 01 02 00 FB
BOOTLOADER
: 02 0000 01 02 00 FB Value . CR LF
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
ISP Commands Summary
Table 75. ISP Commands Summary
Command
Command Name
00h
Program Code
Data[0]
Data[1]
Command Effect
Program Nb Code Byte.
Bootloader will accept up to 128 (80h) data bytes. The data
bytes should be 128 byte page flash boundary.
00h
Erase block0 (0000h-1FFFh)
20h
Erase block1 (2000h-3FFFh)
40h
Erase block2 (4000h-7FFFh)
80h
Erase block3 (8000h- BFFFh)
C0h
Erase block4 (C000h- FFFFh)
03h
00h
Hardware Reset
04h
00h
Erase SBV & BSB
00h
Program SSB level 1
01h
Program SSB level 2
00h
Program BSB (value to write in data[2])
01h
Program SBV (value to write in data[2])
07h
-
Full Chip Erase (This command needs about 6 sec to be
executed)
0Ah
04h
Program BLJB fuse (value to write in data[2])
08h
Program X2 fuse (value to write in data[2])
01h
03h
Write Function
05h
06h
04h
Display Function
Data[0:1] = start address
Display Code
Data [2:3] = end address
Blank Check
Data[4] = 00h:Display Code
Data[4] = 01h: Blank check
Display EEPROM data
Data[4] = 02h: Display EEPROM
00h
Manufacturer Id
01h
Device Id #1
02h
Device Id #2
03h
Device Id #3
00h
Read SSB
01h
Read BSB
02h
Read SBV
06h
Read Extra Byte
00h
Read Hardware Byte
00h
Read Device Boot ID1
01h
Read Device Boot ID2
00h
Read Bootloader Version
00h
05h
Read Function
07h
0Bh
0Eh
0Fh
07h
Program EEPROM data
Program Nn EEprom Data Byte.
Bootloader will accept up to 128 (80h) data bytes.
113
4235E–8051–04/04
API Call Description
The IAP allows to reprogram a microcontroller on-chip Flash memory without removing
it from the system and while the embedded application is running.
The user application can call some Application Programming Interface (API) routines
allowing IAP. These API are executed by the bootloader.
To call the corresponding API, the user must use a set of Flash_api routines which can
be linked with the application.
Example of Flash_api routines are available on the Atmel web site on the software application note:
C Flash Drivers for the AT89C51RD2/ED2
The API calls description and arguments are shown in Table 76.
Process
The application selects an API by setting R1, ACC, DPTR0 and DPTR1 registers.
All calls are made through a common interface “USER_CALL” at the address FFF0h.
The jump at the USER_CALL must be done by LCALL instruction to be able to comeback in the application.
Before jump at the USER_CALL, the bit ENBOOT in AUXR1 register must be set.
Constraints
The interrupts are not disabled by the bootloader.
Interrupts must be disabled by user prior to jump to the USER_CALL, then re-enabled
when returning.
Interrupts must also be disabled before accessing EEPROM Data then re-enabled after.
The user must take care of hardware watchdog before launching a Flash operation.
Table 76. API Call Summary
Command
R1
A
DPTR0
DPTR1
Returned Value
Command Effect
READ MANUF ID
00h
XXh
0000h
XXh
ACC = Manufacturer
Id
Read Manufacturer identifier
READ DEVICE ID1
00h
XXh
0001h
XXh
ACC = Device Id 1
Read Device identifier 1
READ DEVICE ID2
00h
XXh
0002h
XXh
ACC = Device Id 2
Read Device identifier 2
READ DEVICE ID3
00h
XXh
0003h
XXh
ACC = Device Id 3
Read Device identifier 3
ERASE BLOCK
01h
XXh
DPH = 00h
Erase block 0
DPH = 20h
Erase block 1
DPH = 40h
Erase block 2
Address of
byte to
program
XXh
114
00h
ACC = DPH
Program one Data Byte in user Flash
Erase Software boot vector and boot status
byte. (SBV = FCh and BSB = FFh)
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
Table 76. API Call Summary (Continued)
Command
R1
A
DPTR0
DPTR1
Returned Value
DPH = 00h
Set SSB level 1
DPL = 00h
DPH = 00h
Set SSB level 2
DPL = 01h
PROGRAM SSB
05h
XXh
Command Effect
00h
ACC = SSB value
DPH = 00h
Set SSB level 0
DPL = 10h
DPH = 00h
Set SSB level 1
DPL = 11h
PROGRAM BSB
06h
New BSB
value
0000h
XXh
none
Program boot status byte
PROGRAM SBV
06h
New SBV
value
0001h
XXh
none
Program software boot vector
READ SSB
07h
XXh
0000h
XXh
ACC = SSB
Read Software Security Byte
READ BSB
07h
XXh
0001h
XXh
ACC = BSB
Read Boot Status Byte
READ SBV
07h
XXh
0002h
XXh
ACC = SBV
Read Software Boot Vector
PROGRAM DATA
PAGE
09h
Number of
byte to
program
Address of
the first byte
to program in
the Flash
memory
Address in
XRAM of the
first data to
program
ACC = 0: DONE
Remark: number of bytes to program is
limited such as the Flash write remains in a
single 128 bytes page. Hence, when ACC
is 128, valid values of DPL are 00h, or, 80h.
PROGRAM X2 FUSE
0Ah
0008h
XXh
none
Program X2 fuse bit with ACC
PROGRAM BLJB
FUSE
0Ah
0004h
XXh
none
Program BLJB fuse bit with ACC
READ HSB
0Bh
XXh
XXXXh
XXh
ACC = HSB
Read Hardware Byte
READ BOOT ID1
0Eh
XXh
DPL = 00h
XXh
ACC = ID1
Read boot ID1
READ BOOT ID2
0Eh
XXh
DPL = 01h
XXh
ACC = ID2
Read boot ID2
READ BOOT VERSION
0Fh
XXh
XXXXh
XXh
ACC = Boot_Version
Read bootloader version
Fuse value
00h or 01h
Fuse value
00h or 01h
Program up to 128 bytes in user Flash.
115
4235E–8051–04/04
Electrical Characteristics
Absolute Maximum Ratings
Note:
I = industrial ........................................................-40°C to 85 °C
Storage Temperature .................................... -65°C to + 150°C
Voltage on VCC to VSS ......................................-0.5V to + 6.5V
VVoltage on Any Pin to VSS .......................-0.5V to VCC + 0.5V
Power Dissipation ........................................................... 1 W(2)
Stresses at or above those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure
to absolute maximum rating conditions may affect
device reliability.
Power dissipation is based on the maximum allowable die temperature and the thermal resistance of
the package.
DC Parameters for Standard Voltage
TA = -40°C to +85°C; VSS = 0V;
VCC =2.7V to 5.5V and F = 0 to 40 MHz (both internal and external code execution)
VCC =4.5V to 5.5V and F = 0 to 60 MHz (internal code execution only)
Symbol
Parameter
Min
VIL
Input Low Voltage
VIH
Input High Voltage except RST, XTAL1
VIH1
Input High Voltage RST, XTAL1
Typ
Max
Unit
Test Conditions
-0.5
0.2 VCC - 0.1
V
0.2 VCC + 0.9
VCC + 0.5
V
0.7 VCC
VCC + 0.5
V
0.3
V
IOL = 100 µA(4)
0.45
V
IOL = 1.6 mA(4)
1.0
V
IOL = 3.5 mA(4)
0.45
V
IOL = 0.8 mA(4)
0.3
V
IOL = 200 µA(4)
0.45
V
IOL = 3.2 mA(4)
1.0
V
IOL = 7.0 mA(4)
0.45
V
IOL = 1.6 mA(4)
VCC = 4.5V to 5.5V
VOL
Output Low Voltage, ports 1, 2, 3, 4 (6)
VCC = 2.7V to 5.5V
VCC = 4.5V to 5.5V
VOL1
Output Low Voltage, port 0, ALE, PSEN (6)
VCC = 2.7V to 5.5V
VCC = 5V ± 10%
VOH
Output High Voltage, ports 1, 2, 3, 4
VCC - 0.3
V
IOH = -10 µA
VCC - 0.7
V
IOH = -30 µA
VCC - 1.5
V
IOH = -60 µA
0.9 VCC
V
IOH = -10 µA
VCC = 2.7V to 5.5V
116
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
TA = -40°C to +85°C; VSS = 0V;
VCC =2.7V to 5.5V and F = 0 to 40 MHz (both internal and external code execution)
VCC =4.5V to 5.5V and F = 0 to 60 MHz (internal code execution only) (Continued)
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VCC = 5V ± 10%
VOH1
Output High Voltage, port 0, ALE, PSEN
VCC - 0.3
V
IOH = -200 µA
VCC - 0.7
V
IOH = -3.2 mA
VCC - 1.5
V
IOH = -7.0 mA
0.9 VCC
V
IOH = -10 µA
VCC = 2.7V to 5.5V
RRST
RST Pull-down Resistor
50
200(5)
250
kΩ
IIL
Logical 0 Input Current ports 1, 2, 3, 4 and 5
-50
µA
VIN = 0.45V
ILI
Input Leakage Current
±10
µA
0.45V < VIN < VCC
ITL
Logical 1 to 0 Transition Current, ports 1, 2, 3, 4
-650
µA
VIN = 2.0V
CIO
Capacitance of I/O Buffer
10
pF
FC = 3 MHz
TA = 25°C
IPD
Power-down Current
150
µA
2.7 < VCC < 5.5V(3)
75
ICCOP
Power Supply Current on normal mode
0.4 x Frequency (MHz) + 5
mA
VCC = 5.5V(1)
ICCIDLE
Power Supply Current on idle mode
0.3 x Frequency (MHz) + 5
mA
VCC = 5.5V(2)
Power Supply Current on flash or EEdata write
0.8 x Frequency (MHz) + 15
mA
VCC = 5.5V
17
ms
2.7 < VCC < 5.5V
ICCWRITE
tWRITE
Notes:
Flash or EEdata programming time
7
1. Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 55), VIL =
VSS + 0.5V, VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used
(see Figure 52).
2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH , TCHCL = 5 ns, VIL = VSS + 0.5V, VIH = VCC 0.5V; XTAL2 N.C; Port 0 = VCC; EA = RST = VSS (see Figure 53).
3. Power-down ICC is measured with all output pins disconnected; EA = VSS, PORT 0 = VCC; XTAL2 NC.; RST = VSS (see Figure 54).
4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports 1
and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0
transitions during bus operation. In the worst cases (capacitive loading 100 pF), the noise pulse on the ALE line may exceed
0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not necessary.
5. Typical values are based on a limited number of samples and are not guaranteed. The values listed are at room temperature
and 5V.
6. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
Port 0: 26 mA
Ports 1, 2 and 3: 15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
117
4235E–8051–04/04
Figure 52. ICC Test Condition, Active Mode
VCC
ICC
VCC
VCC
P0
VCC
RST
EA
XTAL2
XTAL1
(NC)
CLOCK
SIGNAL
VSS
All other pins are disconnected.
Figure 53. ICC Test Condition, Idle Mode
VCC
ICC
VCC
VCC
P0
RST
EA
XTAL2
XTAL1
VSS
(NC)
CLOCK
SIGNAL
All other pins are disconnected.
Figure 54. ICC Test Condition, Power-down Mode
VCC
ICC
VCC
VCC
P0
RST
(NC)
EA
XTAL2
XTAL1
VSS
All other pins are disconnected.
Figure 55. Clock Signal Waveform for ICC Tests in Active and Idle Modes
VCC-0.5V
0.45V
TCLCH
TCHCL
TCLCH = TCHCL = 5ns.
118
0.7VCC
0.2VCC-0.1
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
AC Parameters
Explanation of the AC
Symbols
Each timing symbol has 5 characters. The first character is always a “T” (stands for
time). The other characters, depending on their positions, stand for the name of a signal
or the logical status of that signal. The following is a list of all the characters and what
they stand for.
Example:TAVLL = Time for Address Valid to ALE Low.
TLLPL = Time for ALE Low to PSEN Low.
(Load Capacitance for port 0, ALE and PSEN = 100 pF; Load Capacitance for all other
outputs = 80 pF.)
Table 77 Table 80, and Table 83 give the description of each AC symbols.
Table 78, Table 79, Table 81 and Table 84 gives the range for each AC parameter.
Table 78, Table 79 and Table 85 give the frequency derating formula of the AC parameter for each speed range description. To calculate each AC symbols. take the x value in
the correponding column (-M) and use this value in the formula.
Example: TLLIU for -M and 20 MHz, Standard clock.
x = 35 ns
T 50 ns
TCCIV = 4T - x = 165 ns
External Program Memory
Characteristics
Table 77. Symbol Description
Symbol
T
Parameter
Oscillator clock period
TLHLL
ALE pulse width
TAVLL
Address Valid to ALE
TLLAX
Address Hold After ALE
TLLIV
ALE to Valid Instruction In
TLLPL
ALE to PSEN
TPLPH
PSEN Pulse Width
TPLIV
PSEN to Valid Instruction In
TPXIX
Input Instruction Hold After PSEN
TPXIZ
Input Instruction Float After PSEN
TAVIV
Address to Valid Instruction In
TPLAZ
PSEN Low to Address Float
119
4235E–8051–04/04
Table 78. AC Parameters for a Fix Clock
Symbol
-M
Units
Min
Max
T
25
ns
TLHLL
35
ns
TAVLL
5
ns
TLLAX
5
ns
TLLIV
n 65
ns
TLLPL
5
ns
TPLPH
50
ns
TPLIV
30
TPXIX
0
ns
ns
TPXIZ
10
ns
TAVIV
80
ns
TPLAZ
10
ns
Table 79. AC Parameters for a Variable Clock
120
Symbol
Type
Standard Clock
X2 Clock
X parameter for
-M range
Units
TLHLL
Min
2T-x
T-x
15
ns
TAVLL
Min
T-x
0.5 T - x
20
ns
TLLAX
Min
T-x
0.5 T - x
20
ns
TLLIV
Max
4T-x
2T-x
35
ns
TLLPL
Min
T-x
0.5 T - x
15
ns
TPLPH
Min
3T-x
1.5 T - x
25
ns
TPLIV
Max
3T-x
1.5 T - x
45
ns
TPXIX
Min
x
x
0
ns
TPXIZ
Max
T-x
0.5 T - x
15
ns
TAVIV
Max
5T-x
2.5 T - x
45
ns
TPLAZ
Max
x
x
10
ns
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
External Program Memory
Read Cycle
12 TCLCL
TLHLL
TLLIV
ALE
TLLPL
TPLPH
PSEN
TLLAX
TAVLL
PORT 0
INSTR IN
TPLIV
TPLAZ
A0-A7
TPXAV
TPXIZ
TPXIX
INSTR IN
A0-A7
INSTR IN
TAVIV
PORT 2
External Data Memory
Characteristics
ADDRESS
OR SFR-P2
ADDRESS A8-A15
ADDRESS A8-A15
Table 80. Symbol Description
Symbol
Parameter
TRLRH
RD Pulse Width
TWLWH
WR Pulse Width
TRLDV
RD to Valid Data In
TRHDX
Data Hold After RD
TRHDZ
Data Float After RD
TLLDV
ALE to Valid Data In
TAVDV
Address to Valid Data In
TLLWL
ALE to WR or RD
TAVWL
Address to WR or RD
TQVWX
Data Valid to WR Transition
TQVWH
Data Set-up to WR High
TWHQX
Data Hold After WR
TRLAZ
RD Low to Address Float
TWHLH
RD or WR High to ALE high
121
4235E–8051–04/04
Table 81. AC Parameters for a Fix Clock
-M
Symbol
Min
Max
Units
TRLRH
125
ns
TWLWH
125
ns
95
TRLDV
ns
0
TRHDX
ns
TRHDZ
25
ns
TLLDV
155
ns
TAVDV
160
ns
105
ns
TLLWL
45
TAVWL
70
ns
TQVWX
5
ns
TQVWH
155
ns
TWHQX
10
ns
TRLAZ
0
ns
TWHLH
5
45
ns
Table 82. AC Parameters for a Variable Clock
122
Symbol
Type
Standard
Clock
X2 Clock
X parameter for
-M range
Units
TRLRH
Min
6T-x
3T-x
25
ns
TWLWH
Min
6T-x
3T-x
25
ns
TRLDV
Max
5T-x
2.5 T - x
30
ns
TRHDX
Min
x
x
0
ns
TRHDZ
Max
2T-x
T-x
25
ns
TLLDV
Max
8T-x
4T -x
45
ns
TAVDV
Max
9T-x
4.5 T - x
65
ns
TLLWL
Min
3T-x
1.5 T - x
30
ns
TLLWL
Max
3T+x
1.5 T + x
30
ns
TAVWL
Min
4T-x
2T-x
30
ns
TQVWX
Min
T-x
0.5 T - x
20
ns
TQVWH
Min
7T-x
3.5 T - x
20
ns
TWHQX
Min
T-x
0.5 T - x
15
ns
TRLAZ
Max
x
x
0
ns
TWHLH
Min
T-x
0.5 T - x
20
ns
TWHLH
Max
T+x
0.5 T + x
20
ns
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
External Data Memory Write
Cycle
TWHLH
ALE
PSEN
TLLWL
TWLWH
WR
TQVWX
TLLAX
PORT 0
TWHQX
TQVWH
A0-A7
DATA OUT
TAVWL
PORT 2
ADDRESS
OR SFR-P2
ADDRESS A8-A15 OR SFR P2
External Data Memory Read Cycle
TWHLH
TLLDV
ALE
PSEN
TLLWL
TRLRH
RD
TRHDZ
TAVDV
TLLAX
PORT 0
TRHDX
A0-A7
DATA IN
TRLAZ
TAVWL
PORT 2
ADDRESS
OR SFR-P2
Serial Port Timing - Shift
Register Mode
ADDRESS A8-A15 OR SFR P2
Table 83. Symbol Description
Symbol
Parameter
TXLXL
Serial port clock cycle time
TQVHX
Output data set-up to clock rising edge
TXHQX
Output data hold after clock rising edge
TXHDX
Input data hold after clock rising edge
TXHDV
Clock rising edge to input data valid
123
4235E–8051–04/04
Table 84. AC Parameters for a Fix Clock
-M
Symbol
Min
Max
TXLXL
300
ns
TQVHX
200
ns
TXHQX
30
ns
TXHDX
0
ns
TXHDV
Units
117
ns
Table 85. AC Parameters for a Variable Clock
Symbol
Type
Standard
Clock
X2 Clock
X Parameter For
-M Range
TXLXL
Min
12 T
6T
TQVHX
Min
10 T - x
5T-x
50
ns
TXHQX
Min
2T-x
T-x
20
ns
TXHDX
Min
x
x
0
ns
TXHDV
Max
10 T - x
5 T- x
133
ns
Units
ns
Shift Register Timing
Waveforms
INSTRUCTION
0
1
2
3
4
5
6
7
8
ALE
TXLXL
CLOCK
TXHQX
TQVXH
OUTPUT DATA
WRITE to SBUF
INPUT DATA
0
1
2
3
4
5
6
TXHDX
TXHDV
VALID
VALID
VALID
SET TI
VALID
VALID
VALID
VALID
VALID
SET RI
CLEAR RI
External Clock Drive
Waveforms
7
VCC-0.5V
0.45V
0.7VCC
0.2VCC-0.1
TCHCL
TCHCX
TCLCH
TCLCX
TCLCL
124
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
AC Testing Input/Output
Waveforms
VCC -0.5V
0.2 VCC + 0.9
INPUT/OUTPUT
0.2 VCC - 0.1
0.45V
AC inputs during testing are driven at VCC - 0.5 for a logic “1” and 0.45V for a logic “0”.
Timing measurement are made at VIH min for a logic “1” and VIL max for a logic “0”.
Float Waveforms
FLOAT
VOH - 0.1V
VOL + 0.1V
VLOAD
VLOAD + 0.1V
VLOAD - 0.1V
For timing purposes as port pin is no longer floating when a 100 mV change from load
voltage occurs and begins to float when a 100 mV change from the loaded VOH/V OL level
occurs. IOL/IOH ≥ ± 20 mA.
Clock Waveforms
Valid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2.
125
4235E–8051–04/04
Figure 56. Internal Clock Signals
INTERNAL
CLOCK
STATE4
STATE5
STATE6
STATE1
STATE2
STATE3
STATE4
STATE5
P1
P1
P1
P1
P1
P1
P1
P1
P2
P2
P2
P2
P2
P2
P2
P2
XTAL2
ALE
THESE SIGNALS ARE NOT ACTIVATED DURING THE
EXECUTION OF A MOVX INSTRUCTION
EXTERNAL PROGRAM MEMORY FETCH
PSEN
P0
DATA
SAMPLED
FLOAT
P2 (EXT)
PCL OUT
DATA
SAMPLED
FLOAT
PCL OUT
DATA
SAMPLED
FLOAT
PCL OUT
INDICATES ADDRESS TRANSITIONS
READ CYCLE
RD
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
P0
DPL OR Rt OUT
DATA
SAMPLED
FLOAT
INDICATES DPH OR P2 SFR TO PCH TRANSITION
P2
WRITE CYCLE
WR
P0
PCL OUT (EVEN IF PROGRAM
MEMORY IS INTERNAL)
DPL OR Rt OUT
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
DATA OUT
P2
INDICATES DPH OR P2 SFR TO PCH TRANSITION
PORT OPERATION
MOV PORT SRC
OLD DATA NEW DATA
P0 PINS SAMPLED
P0 PINS SAMPLED
MOV DEST P0
MOV DEST PORT (P1. P2. P3)
(INCLUDES INTO. INT1. TO T1)
SERIAL PORT SHIFT CLOCK
P1, P2, P3 PINS SAMPLED
RXD SAMPLED
P1, P2, P3 PINS SAMPLED
RXD SAMPLED
TXD (MODE 0)
This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however,
ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propagation also varies from output to output and component. Typically though (TA = 25°C fully loaded) RD and WR propagation
delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC
specifications.
126
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
Ordering Information
Table 86. Possible Order Entries
Part Number
Data EEPROM
Supply Voltage
Temperature
Range
Package
Packing
Product Marking
PLCC44
Stick
AT89C51RD2-IM
VQFP44
Tray
AT89C51RD2-IM
AT89C51RD2-RDTIM(1)
VQFP64
Tray
AT89C51RD2-IM
(1)
PLCC68
Stick
AT89C51RD2-IM
PLCC44
Stick
AT89C51ED2-IM
VQFP44
Tray
AT89C51ED2-IM
PDIL40
Stick
AT89C51ED2-IM
AT89C51ED2- SMSIM
PLCC68
Stick
AT89C51ED2-IM
AT89C51ED2-RDTIM
VQFP64
Tray
AT89C51ED2-IM
AT89C51RD2-SLSIM
AT89C51RD2-RLTIM
No
AT89C51RD2-SMSIM
2.7V - 5.5V
AT89C51ED2-SLSIM
AT89C51ED2-RLTIM
AT89C51ED2-3CSIM
Note:
Yes
Industrial
1. For PLCC68 and VQFP64 packages, please contact Atmel sales office for availability.
127
4235E–8051–04/04
Packaging Information
PLCC44
128
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
VQFP44
129
4235E–8051–04/04
PLCC68
130
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
VQFP64
131
4235E–8051–04/04
PDIL40
132
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
Datasheet Change
Log for
AT89C51RD2/ED2
Changes from 4235A 04/03 to 4135B - 06/03
1. VIH min changed from 0.2 V CC + 1.1 to 0.2 VCC + 0.9.
2. Added POR/PFD and reset specific sections.
3. Added DIL40 package.
4. Added Flash write programming time specification.
Changes from 4235B 06/03 to 4235C - 08/03
1. Changed maximum frequency to 60 MHz in X1 mode and 30 MHz in X2 mode
for Vcc = 4.5V to 5.5V and internal code execution.
2. Added PDIL40 Packaging for AT89C51ED2.
Changes from 4235C 08/03 to 4235D - 12/03
1. Improved explanations throughout the document.
Changes from 4235D 12/03 to 4235E - 04/04
1. Improved explanations throughout the document.
133
4235E–8051–04/04
Table of Contents
Features ................................................................................................. 1
Description ............................................................................................ 1
Block Diagram ....................................................................................... 3
SFR Mapping ......................................................................................... 4
Pin Configurations ................................................................................ 9
Port Types ........................................................................................... 14
Oscillator ............................................................................................. 15
Registers............................................................................................................. 15
Functional Block Diagram ...................................................................................16
Enhanced Features ............................................................................. 17
X2 Feature .......................................................................................................... 17
Dual Data Pointer Register (DPTR) ................................................... 21
Expanded RAM (XRAM) ..................................................................... 24
Registers............................................................................................................. 26
Reset .................................................................................................... 27
Introduction ......................................................................................................... 27
Reset Input ......................................................................................................... 27
Reset Output .......................................................................................................28
Power Monitor ..................................................................................... 29
Description.......................................................................................................... 29
Timer 2 ................................................................................................. 31
Auto-reload Mode ............................................................................................... 31
Programmable
Clock-output ................................................................................................................. 32
Registers............................................................................................................. 34
Programmable Counter Array (PCA) ................................................ 36
PCA Capture Mode.............................................................................................
16-bit Software Timer/ Compare Mode...............................................................
High Speed Output Mode ...................................................................................
Pulse Width Modulator Mode..............................................................................
PCA Watchdog Timer .........................................................................................
i
44
44
45
46
47
AT89C51RD2/ED2
4235E–8051–04/04
AT89C51RD2/ED2
Serial I/O Port ...................................................................................... 49
Framing Error Detection .....................................................................................
Automatic Address Recognition..........................................................................
Registers.............................................................................................................
Baud Rate Selection for UART for Mode 1 and 3...............................................
UART Registers..................................................................................................
49
50
52
52
55
Keyboard Interface ............................................................................. 60
Registers............................................................................................................. 61
Serial Port Interface (SPI) ................................................................... 64
Features.............................................................................................................. 64
Signal Description............................................................................................... 64
Functional Description ........................................................................................ 66
Interrupt System ................................................................................. 73
Registers............................................................................................................. 74
Interrupt Sources and Vector Addresses............................................................ 75
Power Management ............................................................................ 82
Introduction .........................................................................................................
Idle Mode ............................................................................................................
Power-Down Mode .............................................................................................
Registers.............................................................................................................
82
82
82
85
Hardware Watchdog Timer ................................................................ 86
Using the WDT ................................................................................................... 86
WDT during Power-down and Idle...................................................................... 87
ONCE® Mode (ON- Chip Emulation) .................................................. 88
Power-off Flag ..................................................................................... 89
Reduced EMI Mode ............................................................................. 90
EEPROM Data Memory ....................................................................... 91
Write Data........................................................................................................... 91
Read Data........................................................................................................... 93
Registers............................................................................................................. 94
Flash/EEPROM Memory ..................................................................... 95
Features..............................................................................................................
Flash Programming and Erasure ........................................................................
Flash Registers and Memory Map......................................................................
Flash Memory Status..........................................................................................
Memory Organization .........................................................................................
95
95
96
99
99
ii
4235E–8051–04/04
Bootloader Architecture .................................................................................... 100
ISP Protocol Description ...................................................................................104
Functional Description ...................................................................................... 105
Flow Description ............................................................................................... 106
API Call Description.......................................................................................... 114
Electrical Characteristics ................................................................. 116
Absolute Maximum Ratings .............................................................................. 116
DC Parameters for Standard Voltage ...............................................................116
AC Parameters ................................................................................................. 119
Ordering Information ........................................................................ 127
Packaging Information ..................................................................... 128
PLCC44 ............................................................................................................
VQFP44 ............................................................................................................
PLCC68 ............................................................................................................
VQFP64 ............................................................................................................
PDIL40..............................................................................................................
128
129
130
131
132
Datasheet Change Log for AT89C51RD2/ED2 ............................... 133
Changes from 4235A -04/03 to 4135B - 06/03 .................................................
Changes from 4235B -06/03 to 4235C - 08/03.................................................
Changes from 4235C - 08/03 to 4235D - 12/03................................................
Changes from 4235D - 12/03 to 4235E - 04/04................................................
133
133
133
133
Table of Contents .................................................................................. i
iii
AT89C51RD2/ED2
4235E–8051–04/04
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4235E–8051–04/04
/0M