16Mb SDRAM Ordering Information EM 48 1M 16 2 2 V T A – 6 L EOREX Memory EDO/FPM D-RAMBUS DDRSDRAM DDRSGRAM SGRAM SDRAM : : : : : : Power Blank : Standard L : Low power I : Industrial 40 41 42 43 46 48 F: PB free package Density 16M : 16 Mega Bits 8M : 8 Mega Bits 4M : 4 Mega Bits 2M : 2 Mega Bits 1M : 1 Mega Bit Min Cycle Time ( Max Freq.) -5 : 5ns ( 200MHz ) -6 : 6ns ( 167MHz ) -7 : 7ns ( 143MHz ) -75 : 7.5ns ( 133MHz ) -8 : 8ns ( 125MHz ) -10 : 10ns ( 100MHz ) Organization 8 : x8 9 : x9 16 : x16 18 : x18 32 : x32 Refresh 1 : 1K, 8 : 8K 2 : 2K, 6 :16K 4 : 4K Bank 2 : 2Bank 6 : 16Bank 4 : 4Bank 3 : 32Bank 8 : 8Bank Revision A : 1st B : 2nd C : 3rd D :4th Package C: CSP B: uBGA T: TSOP Q: TQFP P: PQFP ( QFP ) Interface V: 3.3V R: 2.5V 1/18 Rev.01 16Mb SDRAM 16Mb ( 2Banks ) Synchronous DRAM EM481M1622VTA (1Mx16) Description The EM481M1622VTA is Synchronous Dynamic Random Access Memory (SDRAM) organized as 512K x 2 banks x 16 bits. All inputs and outputs are synchronized with the positive edge of the clock. The 16Mb SDRAM uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate at 3.3V low power memory system. It also provides auto refresh with power saving / down mode. All inputs and outputs voltage levels are compatible with LVTTL . Feature • Fully synchronous to positive clock edge 3.3V +/- 0.3V power supply • LVTTL compatible with multiplexed address • Programmable Burst Length (B/ L) - 1,2,4,8 or full page • Programmable CAS Latency (C/ L) - 2 or 3 • Data Mask (DQM) for Read / Write masking • Programmable wrap sequence - Sequential ( B/ L = 1/2/4/8/full page ) - Interleave ( B/ L = 1/2/4/8 ) • Burst read with single-bit write operation • All inputs are sampled at the rising edge of the system clock. • Auto refresh and self refresh • 2,048 refresh cycles / 32ms • Single * EOREX reserves the right to change products or specification without notice. 2/18 Rev.01 16Mb SDRAM Pin Assignment ( Top View ) VDD 1 50 VSS DQ0 2 49 DQ15 DQ1 3 48 DQ14 VSSQ 4 47 VSSQ DQ2 5 46 DQ13 DQ3 6 45 DQ12 VDDQ 7 44 VDDQ DQ4 8 43 DQ11 DQ5 9 42 DQ10 VSSQ 10 41 VSSQ DQ6 11 40 DQ9 DQ7 12 39 DQ8 VDDQ 13 38 VDDQ LDQM 14 37 NC /WE 15 36 UDQM /CAS 16 35 CLK /RAS 17 34 CKE /CS 18 33 NC BA 19 32 A9 A10 20 31 A8 A0 21 30 A7 A1 22 29 A6 A2 23 28 A5 A3 24 27 A4 VDD 25 26 VSS 50pin TSOP-II 3/18 Rev.01 16Mb SDRAM Pin Descriptions ( Simplified ) Pin Name CLK /CS System Clock Chip select Pin Function CKE Clock Enable A0 ~ A10 Address BA Bank Address /RAS Row address strobe /CAS Column address strobe Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. /WE Write Enable Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. UDQM /LDQM Data input/output Mask DQ0 ~ 15 Data input/output VDD/VSS Power supply/Ground VDD and VSS are power supply pins for internal circuits. VDDQ/VSSQ Power supply/Ground VDDQ and VSSQ are power supply pins for the output buffers. NC No connection Master Clock Input(Active on the Positive rising edge) Selects chip when active Activates the CLK when “H” and deactivates when “L”. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. Row address (A0 to A10) is determined by A0 to A10 level at the bank active command cycle CLK rising edge. CA(CA0 to CA7) is determined by A0 to A7 level at the read or write command cycle CLK rising edge. And this column address becomes burst access start address. A10 defines the pre-charge mode. When A10 = High at the pre-charge command cycle, all banks are pre-charged. But when A10 = Low at the pre-charge command cycle, only the bank that is selected by BA is pre-charged. Selects which bank is to be active. Latches Row Addresses on the positive rising edge of the CLK with /RAS “L”. Enables row access & pre-charge. DQM controls I/O buffers. DQ pins have the same function as I/O pins on a conventional DRAM. This pin is recommended to be left No Connection on the device. 4/18 Rev.01 16Mb SDRAM Block Diagram Auto/Self Refresh Counter A0 A1 DQM A6 A7 Memory Array Write DQM Control Data In A8 S/A & I/O gating A9 Col. Decoder A10 DQi Data Out Col. Add. Buffer BA Read DQM Control Col. Add. Counter Mode Register Set DQM A5 Row Decoder A4 Address Register A3 Row Add. Buffer A2 Burst Counter Timing Register CLK CKE /CS /RAS /CAS /WE DQM 5/18 Rev.01 16Mb SDRAM Simplified State Diagram Self Refresh LF SE LF SE Mode Register Set MRS it Ex CBR Refresh REF IDLE CK E↓ ACT CK E wi th Wr ite CKE BS T Re ad Read READ Write CKE WRITEA CKE POWER ON Precharge Active Power Down CKE↓ READ Suspend CKE READA PR E CKE↓ th wi Read ad Re WRITE E PR WRITEA Suspend CKE↓ CKE↓ Row Active Write WRITE Suspend Power Down CKE↓ CKE READA Suspend Precharge Manual Input Automatic Sequence 6/18 Rev.01 16Mb SDRAM Address Input for Mode Register Set BA A10 A9 A8 A7 Operation Mode A6 A5 A4 A3 CAS Latency BT Sequential 1 2 4 8 Reserved Reserved Reserved Full Page BA 0 0 A10 0 0 A9 0 1 A8 0 0 A7 0 0 A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A1 A0 Burst Length Burst Length Interleave A2 1 0 2 0 4 0 8 0 Reserved 1 Reserved 1 Reserved 1 Reserved 1 Burst Type Interleave Sequential CAS Latency Reserved 2 3 Reserved Reserved Reserved Reserved Reserved A2 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 A3 0 1 A4 0 1 0 1 0 1 0 1 Operation Mode Normal Burst read with Single-bit Write 7/18 Rev.01 16Mb SDRAM Burst Type ( A3 ) Burst Length 2 4 8 Full Page * A2 A1 A0 XX0 XX1 X0 0 X0 1 X1 0 X1 1 000 001 010 011 100 101 110 111 nnn Sequential Addressing 01 10 0123 1230 2301 3012 01234567 12345670 23456701 34567012 45670123 56701234 67012345 70123456 Cn Cn+1 Cn+2 …... Interleave Addressing 01 10 0123 1032 2301 3210 01234567 10325476 23016745 32107654 45670123 54761032 67452301 76543210 - * Page length is a function of I/O organization and column addressing x16 (CA0 ~ CA7) : Full page = 256 bits 8/18 Rev.01 16Mb SDRAM Truth Table 1. Command Truth Table Command Symbol Ignore Command No operation Burst stop Read Read with auto pre-charge Write Write with auto pre-charge Bank activate Pre-charge select bank Pre-charge all banks Mode register set CKE n-1 n H H H H H H H H H H H X X X X X X X X X X X DESL NOP BSTH READ READA WRIT WRITA ACT PRE PALL MRS /CS /RAS /CAS /WE H L L L L L L L L L L X H H H H H L L L L L X H H L L L H H H H L BA X H L H H L H H L L L A10 A9~A0 X X X V V V V V V X L X X X L H L H V L H L X X X V V V V V X X V Note : H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input 2. DQM Truth Table Command Symbol CKE /CS n-1 n ENB MASK H H X X H L BSTH READ READA WRIT WRITA ACT PRE PALL MRS H H H H H H H H H X X X X X X X X X L L L L L L L L L ( EM481M1622VT ) Data w rite / output enable Data mask / output disable ( EM481M1622VT ) Upper byte w rite enable / output enable Read Read w ith auto pre-charge Write Write w ith auto pre-charge Bank activate Pre-charge select bank Pre-charge all banks Mode register set Note : H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input 3. CKE Truth Table Command Command Activating Any Clock suspend Idle Idle Clock suspend mode entry Clock suspend mode Clock suspend mode exit CBR refresh command Self refresh entry Self refresh Self refresh exit Idle Power down Pow er dow n entry Pow er dow n exit Symbol REF SELF CKE n-1 n H L L H H L L H L L L H H L H H L H /CS /RAS /CAS /WE Addr. X X X L L L H X X X X X L L H X X X X X X L L H X X X X X X H H H X X X X X X X X X X X X Re m ark H = High level, L = Low level, X = High or Low level (Don't care) 9/18 Rev.01 16Mb SDRAM 4. Operative Command Table Current state Idle Row active Re ad Write /CS /R /C /W H L L L L L L L H L L L L L L L H L L L L L L L L H L L L L L L L L X H H H L L L L X H H H L L L L X H H H L L L L L X H H H L L L L L X H L L H H L L X H L L H H L L X H H L L H H L L X H H L L H H L L X X H L H L H L X X H L H L H L X H L H L H L H L X H L H L H L H L Addr. Command Action Notes X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code X X X BA/CA/A10 BA/CA/A10 BA/RA BA/A10 X Op-Code X X X BA/CA/A10 BA/CA/A10 BA/RA BA/A10 X Op-Code DESL NOP or BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP or BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Nop or pow er dow n Nop or pow er dow n ILLEGAL ILLEGAL Row activating Nop Refresh or self refresh Mode register accessing Nop Nop Begin read : Determine AP Begin w rite : Determine AP ILLEGAL Precharge ILLEGAL ILLEGAL Continue burst to end → Row active Continue burst to end → Row active Burst stop → Row active Terminate burst, new read : Determine AP Terminate burst, start w rite : Determine AP ILLEGAL Terminate burst, pre-charging ILLEGAL ILLEGAL Continue burst to end → Write recovering Continue burst to end → Write recovering Burst stop → Row active Terminate burst, start read : Determine AP 7, 8 Terminate burst, new w rite : Determine AP 7 ILLEGAL Terminate burst, pre-charging ILLEGAL ILLEGAL 2 2 3 3 Re m ark H = High level, L = Low level, X = High or Low level (Don't care) 10/18 Rev.01 4 5 5 3 6 4 7 7, 8 3 4 7,8 7 3 9 16Mb SDRAM Current state Re ad w ith AP Write w ith AP Pre charging Row activating /CS /R /C /W Addr. Command H L L L L L L L L X H H H H L L L L X H H L L H H L L X X H X L X H BA/CA/A10 L BA/CA/A10 H BA/RA L BA, A10 H X L Op-Code DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS H X X X X DESL L H H H X NOP L L L L L L L H L L L L L L L L H L L L L L L L L H H H L L L L X H H H H L L L L X H H H H L L L L H L L H H L L X H H L L H H L L X H H L L H H L L L H L H L H L X H L H L H L H L X H L H L H L H L X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code X X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code X X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Action Continue burst to end → Precharging Continue burst to end → Precharging ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL burst to end → Write recovering w ith auto precharge Continue burst to end → Write recovering w ith auto precharge ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop → Enter idle after tRP Nop → Enter idle after tRP ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop → Enter idle after tRP ILLEGAL ILLEGAL Nop → Enter idle after tRCD Nop → Enter idle after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Notes 3 3 3 3 3 3 3 3 3 3 3 3 3 3,10 3 Re m ark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Precharge 11/18 Rev.01 16Mb SDRAM Current state Write re cove ring Write re cove ring w ith AP Re freshing M ode Re giste r Acces sing /CS /R /C /W Addr. Command Action DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP/ BST READ/WRIT ACT/PRE/PALL REF/SELF/MRS DESL NOP BST READ/WRIT ACT/PRE/PALL/ REF/SELF/MRS Nop → Enter row active after tDPL Nop → Enter row active after tDPL Nop → Enter row active after tDPL Start read, Determine AP New w rite, Determine AP ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop → Enter precharge after tDPL Nop → Enter precharge after tDPL Nop → Enter precharge after tDPL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop → Enter idle after tRC Nop → Enter idle after tRC ILLEGAL ILLEGAL ILLEGAL Nop Nop ILLEGAL ILLEGAL H L L L L L L L L H L L L L L L L L H L L L L H L L L X H H H H L L L L X H H H H L L L L X H H L L X H H H X H H L L H H L L X H H L L H H L L X H L H L X H H L X H L H L H L H L X H L H L H L H L X X X X X X H L X X X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code X X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code X X X X X X X X X L L X X X Notes 8 3 3 3,8 3 3 ILLEGAL Re m ark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Precharge Notes 1. All entries assume that CKE w as active (High level) during the preceding clock cycle. 2. If all banks are idle, and CKE is inactive (Low level), SDRAM w ill enter Pow er dow n mode. All input buffers except CKE w ill be disabled. 3. Illegal to bank in specified states; → Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. 4. If all banks are idle, and CKE is inactive (Low level), SDRAM w ill enter Self refresh mode. All input buffers except CKE w ill be disabled. 5. Illegal if tRCD is not satisfied. 6. Illegal if tRAS is not satisfied. 7. Must satisfy burst interrupt condition. 8. Must satisfy bus contention, bus turn around, and/or w rite recovery requirements. 9. Must mask preceding data w hich don't satisfy tDPL. 10. Illegal if tRRD is not satisfied. 12/18 Rev.01 16Mb SDRAM 5. Command Truth Table for CKE Current state CKE n-1 H L L Se lf re fre sh L L L H H H Se lf re fre sh H re covery H H H H H Pow er dow n L L H H H H H Both banks H idle H H H H L H Row active L H Any state H other than L liste d above L n X H H H H L H H H H L L L L X H L H H H H H L L L L L X X X H L H L /CS /R /C /W X H L L L X H L L L H L L L X X X H L L L L H L L L L X X X X X X X X X H H L X X H H L X H H L X X X X H L L L X H L L L X X X X X X X X X H L X X X H L X X H L X X X X X X H L L X X H L L X X X X X X X X X X X X X X X X X X X X X X X X X X X H L X X X H L X X X X X X X Addr. Action X X X X X X X X X X X X X X X X X X Op-Code X Op-Code X X X X X X INVALID, CLK (n – 1) w ould exit self refresh Self refresh recovery Self refresh recovery ILLEGAL ILLEGAL Maintain self refresh Idle after tRC Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL INVALID, CLK(n-1) w ould exit pow er dow n Exit pow er dow n → Idle Maintain pow er dow n mode Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refresh Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refer to operations in Operative Command Table Self refresh Refer t o operations in Operative Command Table Pow er dow n Refer to operations in Operative Command Table Pow er dow n Refer to operations in Operative Command Table Begin clock suspend next cycle Exit clock suspend next cycle Maintain clock suspend Notes 1 1 1 2 Re m ark : H = High level, L = Low level, X = High or Low level (Don't care) Notes 1. Self refresh can be entered only from the both banks idle state. Pow er dow n can be entered only from both banks idle or row active state. 2. Must be legal command as defined in Operative Command Table. 13/18 Rev.01 16Mb SDRAM Absolute Maximum Ratings Symbol Item Rating Units VIN, VOUT Input, Output Voltage -0.3 ~ 4.6 V VDD, VDDQ Power Supply Voltage -0.3 ~ 4.6 V TOP Operating Temperature 0 ~ 70 °C TSTG Storage Temperature -55 ~ 150 °C PD Power Dissipation 1 W IOS Short Circuit Current 50 mA Note : Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specif ication. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operation Conditions ( Ta = 0 ~ 70°C ) Symbol Parameter Min. Typical Max. Units VDD Power Supply Voltage 3.0 3.3 3.6 V VDDQ Power Supply Voltage (for I/O Buffer) 3.0 3.3 3.6 V VIH Input logic high voltage 2.0 VDD+0.3 V VIL Input logic low voltage -0.3 0.8 V Note : 1. All voltage referred to V SS. 2. V IH (max) = 5.6V for pulse w idth ≤ 3ns 3. V IL (min) = -2.0V for pulse w idth ≤ 3ns Capacitance ( Vcc =3.3V, f = 1MHz, Ta = 25°C ) Symbol Parameter Min. Max. Units CCLK Clock capacitance 2.5 4.0 pF CI Input capacitance for CLK, CKE, Address, /CS, /RAS, /CAS, /WE, DQML,DQMU 2.5 5.0 pF CO Input/Output capacitance 4.0 6.5 pF 14/18 Rev.01 16Mb SDRAM Recommended DC Operating Conditions ( VDD = 3.3V +/- 0.3 V, Ta = 0 ~ 70 °C , Ta = -40 to 85°C for 6I) MAX Parameter Symbol Operating current ICC1 Burst length = 1, tRC ≥ tRC (min), IOL = 0 mA, One bank active Precharge standby current in power down mode ICC2P CKE ≤ V IL (max.), tCk = 15 ns ICC2PS CKE ≤ V IL (max.), tCk = ∞ ICC2N CKE ≥ V IL (min.), tCK = 15 ns, /CS ≥ V IH (min.) Input signals are changed one time during 30ns ICC2NS Precharge standby current in non-power down mode Active standby current in power down mode Active standby current in non-power down mode Test condition 100 6/6I/6L 7/7L 90 80 Units Notes mA 1 2 / 0.7* mA 5 2 / 0.7* mA 5 20 mA CKE ≥ V IL (min.), tCK = ∞ Input signals are stable 8 mA ICC3P CKE ≤ VIL(max), tCK = 15ns 5 mA ICC3PS CKE ≤ VIL(max), tCK = ∞ 5 mA ICC3N CKE ≥ VIL(min), tCK = 15ns,/ CS ≥ VIH(min) Input signals are changed one time during 30ns 30 mA ICC3NS CKE ≥ VIL(min), tCK = ∞ Input signals are stable 20 mA operating current (Burst mode) ICC4 tCCD = 2CLKs , IOL = 0 mA Refresh current ICC5 tRC ≥ tRC(min.) Self Refresh current 5 ICC6 CKE ≤ 0.2V CL=3 CL=2 180 160 140 130 120 110 2 0.3 mA 2 mA 3 mA 4 5 Note : 1. ICC1 depends on output loading and cycle rates. Specified values are obtained w ith the output open. Input signals are changed only one time during tCK(min) 2. ICC4 depends on output loading and cycle rates. Specified values are obtained w ith the output open. Input signals are changed only one time during tCK(min) 3. Input signals are changed only one time during tCK(min) 4. Standard pow er version. 5. * Low pow er version. 15/18 Rev.01 16Mb SDRAM Recommended DC Operating Conditions ( Continued ) Parameter Symbol Input leakage current IIL Output leakage current Test condition Min. Max. Unit 0 ≤ VI ≤ VDDQ, VDDQ=VDD All other pins not under test=0 V -0.5 +0.5 uA IOL 0 ≤ VO ≤ VDDQ, DOUT is disabled -0.5 +0.5 uA High level output voltage VOH Io = -4mA 2.4 Low level output voltage VOL Io = +4mA V 0.4 V AC Operating Test Conditions ( VDD = 3.3V +/- 0.3 V, Ta = 0 ~ 70 °C , Ta = -40 to 85°C for 6I ) Output Reference Level 1.4V / 1.4V Output Load See diagram as below Input Signal Level 2.4V / 0.4V Transition Time of Input Signals 2ns Input Reference Level 1.4V Vtt = 1.4V 50Ω Output Z = 50Ω 50pF 16/18 Rev.01 16Mb SDRAM Operating AC Characteristics ( VDD = 3.3V +/- 0.3 V, Ta = 0 ~ 70 °C , Ta = -40 to 85°C for 6I) Parameter Clock cycle time Access time from CLK Symbol CL = 3 CL = 2 CL = 3 CL = 2 tCK -5 Min. -6/6I/6L Max. Min. Max. -7/7L Min. Max. Units Notes 5 6 7 ns 7 7.5 8 ns 4.5 tAC 5 5.5 5.5 5.5 ns 5 ns CLK high level width tCH 1.5 2 2.75 2 ns CLK low level width tCL 1.5 2 2.75 2 ns 1.5 2 22 ns 2 ns Data-out hold time Data-out high impedance time CL = 3 CL = 2 CL = 3 CL = 2 tOH 1.5 tHZ 5 2 6 2 7 ns ns Data-out low impedance time tLZ 0 0 1 ns Input hold time 1 1 1 ns Input setup time tIH tIS 1.5 1.5 1.5 ns ACTIVE to ACTIVE command period tRC 54 60 65 ns 2 ACTIVE to PRECHARGE command period tRAS 40 ns 2 PRECHARGE to ACTIVE command period tRP 18 18 18 ns 2 ACTIVE to READ/WRITE delay time tRCD 14 18 20 ns 2 ACTIVE(one) to ACTIVE(another) command tRRD 10 12 14 ns 2 READ/WRITE command to READ/WRITE command tCCD 1 1 1 CLK Data-in to PRECHARGE command tDPL 2 2 2 CLK Data-in to BURST stop command tBDL 1 1 1 CLK 3 3 3 CLK 2 CLK Data-out to high impedance from PRECHARGE command CL = 3 CL = 2 Refresh time(2,048 cycle) tROH tREF 100k 42 32 100k 32 45 100k 32 ms ＊ All voltages referenced to Vss. Note : 1. tHZ defines the time at which the output achieve the open circuit condition and is not referenced to output voltage levels. 2. These parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows : The number of clock cycles = Specified value of timing/clock period (Count fractions as a whole number) 17/18 Rev.01 16Mb SDRAM Package Dimension 18/18 Rev.01