ATMEL ATMEGA1284

Features
• High-performance, Low-power Atmel® AVR® 8-bit Microcontroller
• Advanced RISC Architecture
•
•
•
•
•
•
•
•
•
– 131 Powerful Instructions – Most Single-clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20MIPS Throughput at 20MHz
– On-chip 2-cycle Multiplier
High Endurance Non-volatile Memory segments
– 16/32/64/128KBytes of In-System Self-programmable Flash program memory
– 512/1K/2K/4KBytes EEPROM
– 1/2/4/16KBytes Internal SRAM
– Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM
– Data retention: 20 years at 85°C/ 100 years at 25°C(1)
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– Programming Lock for Software Security
QTouch® library support
– Capacitive touch buttons, sliders and wheels
– QTouch and QMatrix acquisition
– Up to 64 sense channels
JTAG (IEEE std. 1149.1 Compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– One/two 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
– Real Time Counter with Separate Oscillator
– Six PWM Channels
– 8-channel, 10-bit ADC
Differential mode with selectable gain at 1x, 10x or 200x
– Byte-oriented Two-wire Serial Interface
– Two Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and
Extended Standby
I/O and Packages
– 32 Programmable I/O Lines
– 40-pin PDIP, 44-lead TQFP, 44-pad VQFN/QFN/MLF
– 44-pad DRQFN
– 49-ball VFBGA
Operating Voltages
– 1.8 - 5.5V
Speed Grades
– 0 - 4MHz @ 1.8 - 5.5V
– 0 - 10MHz @ 2.7 - 5.5V
– 0 - 20MHz @ 4.5 - 5.5V
Power Consumption at 1MHz, 1.8V, 25°C
– Active: 0.4mA
– Power-down Mode: 0.1µA
– Power-save Mode: 0.6µA (Including 32kHz RTC)
Note:
1. See ”Data Retention” on page 9 for details.
8-bit Atmel
Microcontroller
with
16/32/64/128K
Bytes In-System
Programmable
Flash
ATmega164A
ATmega164PA
ATmega324A
ATmega324PA
ATmega644A
ATmega644PA
ATmega1284
ATmega1284P
Summary
8272CS–AVR–06/11
ATmega164A/PA/324A/PA/644A/PA/1284/P
1. Pin Configurations
1.1
Pinout - PDIP/TQFP/VQFN/QFN/MLF for ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P
Figure 1-1.
Pinout
(PCINT8/XCK0/T0) PB0
(PCINT9/CLKO/T1) PB1
(PCINT10/INT2/AIN0) PB2
(PCINT11/OC0A/AIN1) PB3
(PCINT12/OC0B/SS) PB4
(PCINT13/ICP3/MOSI) PB5
(PCINT14/OC3A/MISO) PB6
(PCINT15/OC3B/SCK) PB7
RESET
VCC
GND
XTAL2
XTAL1
(PCINT24/RXD0/T3) PD0
(PCINT25/TXD0) PD1
(PCINT26/RXD1/INT0) PD2
(PCINT27/TXD1/INT1) PD3
(PCINT28/XCK1/OC1B) PD4
(PCINT29/OC1A) PD5
(PCINT30/OC2B/ICP) PD6
PA0 (ADC0/PCINT0)
PA1 (ADC1/PCINT1)
PA2 (ADC2/PCINT2)
PA3 (ADC3/PCINT3)
PA4 (ADC4/PCINT4)
PA5 (ADC5/PCINT5)
PA6 (ADC6/PCINT6)
PA7 (ADC7/PCINT7)
AREF
GND
AVCC
PC7 (TOSC2/PCINT23)
PC6 (TOSC1/PCINT22)
PC5 (TDI/PCINT21)
PC4 (TDO/PCINT20)
PC3 (TMS/PCINT19)
PC2 (TCK/PCINT18)
PC1 (SDA/PCINT17)
PC0 (SCL/PCINT16)
PD7 (OC2A/PCINT31)
PB4 (SS/OC0B/PCINT12)
PB3 (AIN1/OC0A/PCINT11)
PB2 (AIN0/INT2/PCINT10)
PB1 (T1/CLKO/PCINT9)
PB0 (XCK0/T0/PCINT8)
GND
VCC
PA0 (ADC0/PCINT0)
PA1 (ADC1/PCINT1)
PA2 (ADC2/PCINT2)
PA3 (ADC3/PCINT3)
TQFP/QFN/MLF
(PCINT13/ICP3/MOSI) PB5
(PCINT14/OC3A/MISO) PB6
(PCINT15/OC3B/SCK) PB7
RESET
VCC
GND
XTAL2
XTAL1
(PCINT24/RXD0/T3) PD0
(PCINT25/TXD0) PD1
(PCINT26/RXD1/INT0) PD2
(PCINT27/TXD1/INT1)
(PCINT28/XCK1/OC1B)
(PCINT29/OC1A)
(PCINT30/OC2B/ICP)
(PCINT31/OC2A)
PD3
PD4
PD5
PD6
PD7
VCC
GND
(PCINT16/SCL) PC0
(PCINT17/SDA) PC1
(PCINT18/TCK) PC2
(PCINT19/TMS) PC3
PA4 (ADC4/PCINT4)
PA5 (ADC5/PCINT5)
PA6 (ADC6/PCINT6)
PA7 (ADC7/PCINT7)
AREF
GND
AVCC
PC7 (TOSC2/PCINT23)
PC6 (TOSC1/PCINT22)
PC5 (TDI/PCINT21)
PC4 (TDO/PCINT20)
Note:
The large center pad underneath the VQFN/QFN/MLF package should be soldered to ground on
the board to ensure good mechanical stability.
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8272CS–AVR–06/11
ATmega164A/PA/324A/PA/644A/PA/1284/P
1.2
Pinout - DRQFN for ATmega164A/164PA/324A/324PA
Figure 1-2.
DRQFN - Pinout
Top view
Bottom view
A24
B20
A23
B19
A22
B18
A21
B17
A20
B16
A19
A19
B16
A20
B17
A21
B18
A22
B19
A23
B20
A24
A1
A18
B1
B15
A17
B2
B14
B3
B4
A2
A3
A4
Table 1-1.
B1
B14
B2
A16
B13
A16
B13
B3
A15
B12
A15
A2
A3
A4
B4
A14
B12
A14
B11
A13
B11
A13
B5
A5
A6
A12
B10
A11
B9
A10
B8
A9
B7
A8
B6
A7
B8
A10
B9
A11
B10
A12
B7
A9
A8
A7
B6
A6
A1
B15
A17
A5
B5
A18
DRQFN - Pinout
A1
PB5
A7
PD3
A13
PC4
A19
PA3
B1
PB6
B6
PD4
B11
PC5
B16
PA2
A2
PB7
A8
PD5
A14
PC6
A20
PA1
B2
RESET
B7
PD6
B12
PC7
B17
PA0
A3
VCC
A9
PD7
A15
AVCC
A21
VCC
B3
GND
B8
VCC
B13
GND
B18
GND
A4
XTAL2
A10
GND
A16
AREF
A22
PB0
B4
XTAL1
B9
PC0
B14
PA7
B19
PB1
A5
PD0
A11
PC1
A17
PA6
A23
PB2
B5
PD1
B10
PC2
B15
PA5
B20
PB3
A6
PD2
A12
PC3
A18
PA4
A24
PB4
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8272CS–AVR–06/11
ATmega164A/PA/324A/PA/644A/PA/1284/P
1.3
Pinout - VFBGA for ATmega164A/164PA/324A/324PA
Figure 1-3.
VFBGA - Pinout
Top view
1
2
3
4
5
Bottom view
6
7
7
6
5
4
3
2
1
A
A
B
B
C
C
D
D
E
E
F
F
G
G
Table 1-2.
BGA - Pinout
1
2
3
4
5
6
7
A
GND
PB4
PB2
GND
VCC
PA2
GND
B
PB6
PB5
PB3
PB0
PA0
PA3
PA5
C
VCC
RESET
PB7
PB1
PA1
PA6
AREF
D
GND
XTAL2
PD0
GND
PA4
PA7
GND
E
XTAL1
PD1
PD5
PD7
PC5
PC7
AVCC
F
PD2
PD3
PD6
PC0
PC2
PC4
PC6
G
GND
PD4
VCC
GND
PC1
PC3
GND
4
8272CS–AVR–06/11
ATmega164A/PA/324A/PA/644A/PA/1284/P
2. Overview
The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is a low-power CMOS 8-bit
microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P
achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize
power consumption versus processing speed.
2.1
Block Diagram
Figure 2-1.
Block Diagram
PA7..0
PB7..0
VCC
RESET
GND
Power
Supervision
POR / BOD &
RESET
PORT A (8)
PORT B (8)
Watchdog
Timer
Analog
Comparator
A/D
Converter
Watchdog
Oscillator
USART 0
XTAL1
Oscillator
Circuits /
Clock
Generation
EEPROM
Internal
Bandgap reference
XTAL2
SPI
8bit T/C 0
CPU
16bit T/C 1
16bit T/C 1
JTAG/OCD
8bit T/C 2
TWI
PORT C (8)
TOSC2/PC7
TOSC1/PC6
PC5..0
FLASH
SRAM
16bit T/C 3
USART 1
PORT D (8)
PD7..0
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than
conventional CISC microcontrollers.
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8272CS–AVR–06/11
ATmega164A/PA/324A/PA/644A/PA/1284/P
The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P provide the following features:
16/32/64/128Kbytes of In-System Programmable Flash with Read-While-Write capabilities,
512/1K/2K/4Kbytes EEPROM, 1/2/4/16Kbytes SRAM, 32 general purpose I/O lines, 32 general
purpose working registers, Real Time Counter (RTC), three flexible Timer/Counters with compare modes and PWM, 2 USARTs, a byte oriented 2-wire Serial Interface, a 8-channel, 10-bit
ADC with optional differential input stage with programmable gain, programmable Watchdog
Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface,
also used for accessing the On-chip Debug system and programming and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM,
Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode
saves the register contents but freezes the Oscillator, disabling all other chip functions until the
next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to
run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC
Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and
ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up
combined with low power consumption. In Extended Standby mode, both the main Oscillator
and the Asynchronous Timer continue to run.
Atmel offers the QTouch® library for embedding capacitive touch buttons, sliders and wheels
functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers
robust sensing and includes fully debounced reporting of touch keys and includes Adjacent Key
Suppression® (AKS™) technology for unambiguous detection of key events. The easy-to-use
QTouch Suite toolchain allows you to explore, develop and debug your own touch applications.
The device is manufactured using Atmel’s high-density nonvolatile memory technology. The Onchip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial
interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program
running on the AVR core. The boot program can use any interface to download the application
program in the application Flash memory. Software in the Boot Flash section will continue to run
while the Application Flash section is updated, providing true Read-While-Write operation. By
combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,
the Atmel ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control
applications.
The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is supported with a full suite of
program and system development tools including: C compilers, macro assemblers, program
debugger/simulators, in-circuit emulators, and evaluation kits.
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8272CS–AVR–06/11
ATmega164A/PA/324A/PA/644A/PA/1284/P
2.2
Comparison Between ATmega164A, ATmega164PA, ATmega324A, ATmega324PA,
ATmega644A, ATmega644PA, ATmega1284 and ATmega1284P
Table 2-1.
Differences between ATmega164A, ATmega164PA, ATmega324A, ATmega324PA, ATmega644A,
ATmega644PA, ATmega1284 and ATmega1284P
Device
Flash
EEPROM
RAM
ATmega164A
16 K
512
1K
ATmega164PA
16 K
512
1K
ATmega324A
32 K
1K
2K
ATmega324PA
32 K
1K
2K
ATmega644A
64 K
2K
4K
ATmega644PA
64 K
2K
4K
ATmega1284
128 K
4K
16 K
ATmega1284P
128 K
4K
16 K
Units
bytes
2.3
2.3.1
Pin Descriptions
VCC
Digital supply voltage.
2.3.2
GND
Ground.
2.3.3
Port A (PA7:PA0)
Port A serves as analog inputs to the Analog-to-digital Converter.
Port A also serves as an 8-bit bi-directional I/O port with internal pull-up resistors (selected for
each bit). The Port A output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port A pins that are externally pulled low will source current if
the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes
active, even if the clock is not running.
Port A also serves the functions of various special features
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on page 80.
2.3.4
of
the
Port B (PB7:PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on page 82.
2.3.5
of
the
Port C (PC7:PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
7
8272CS–AVR–06/11
ATmega164A/PA/324A/PA/644A/PA/1284/P
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port C also serves the functions of the JTAG interface, along with special features of the
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on page 85.
2.3.6
Port D (PD7:PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D also serves the functions of various special features
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on page 88.
2.3.7
of
the
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in ”System and Reset
Characteristics” on page 337. Shorter pulses are not guaranteed to generate a reset.
2.3.8
XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
2.3.9
XTAL2
Output from the inverting Oscillator amplifier.
2.3.10
AVCC
AVCC is the supply voltage pin for Port A and the Analog-to-digital Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected
to VCC through a low-pass filter.
2.3.11
AREF
This is the analog reference pin for the Analog-to-digital Converter.
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8272CS–AVR–06/11
ATmega164A/PA/324A/PA/644A/PA/1284/P
3. Resources
A comprehensive set of development tools, application notes and datasheetsare available for
download on http://www.atmel.com/avr.
4. About Code Examples
This documentation contains simple code examples that briefly show how to use various parts of
the device. Be aware that not all C compiler vendors include bit definitions in the header files
and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.
The code examples assume that the part specific header file is included before compilation. For
I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and
"STS" combined with "SBRS", "SBRC", "SBR", and "CBR".
Note:
1.
5. Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less
than 1 PPM over 20 years at 85°C or 100 years at 25°C.
6. Capacitive touch sensing
The Atmel® QTouch® Library provides a simple to use solution to realize touch sensitive interfaces on most Atmel AVR ® microcontrollers. The QTouch Library includes support for the
QTouch and QMatrix® acquisition methods.
Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library
for the AVR Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the touch sensing API’s to retrieve the channel information
and determine the touch sensor states.
The QTouch Library is FREE and downloadable from the Atmel website at the following location:
www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the
Atmel QTouch Library User Guide - also available for download from the Atmel website.
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ATmega164A/PA/324A/PA/644A/PA/1284/P
7. Register Summary
Address
(0xFF)
Bit 7
Bit 6
Bit 5
Bit 4
Reserved
Name
-
-
-
-
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
(0xFE)
Reserved
-
-
-
-
-
-
-
-
(0xFD)
Reserved
-
-
-
-
-
-
-
-
(0xFC)
Reserved
-
-
-
-
-
-
-
-
(0xFB)
Reserved
-
-
-
-
-
-
-
(0xFA)
Reserved
-
-
-
-
-
-
-
(0xF9)
Reserved
-
-
-
-
-
-
-
(0xF8)
Reserved
-
-
-
-
-
-
-
-
(0xF7)
Reserved
-
-
-
-
-
-
-
-
(0xF6)
Reserved
-
-
-
-
-
-
-
-
(0xF5)
Reserved
-
-
-
-
-
-
-
(0xF4)
Reserved
-
-
-
-
-
-
-
-
(0xF3)
Reserved
-
-
-
-
-
-
-
-
(0xF2)
Reserved
-
-
-
-
-
-
-
-
(0xF1)
Reserved
-
-
-
-
-
-
-
(0xF0)
Reserved
-
-
-
-
-
-
-
(0xEF)
Reserved
-
-
-
-
-
-
-
(0xEE)
Reserved
-
-
-
-
-
-
-
-
(0xED)
Reserved
-
-
-
-
-
-
-
-
(0xEC)
Reserved
-
-
-
-
-
-
-
-
(0xEB)
Reserved
-
-
-
-
-
-
-
(0xEA)
Reserved
-
-
-
-
-
-
-
-
(0xE9)
Reserved
-
-
-
-
-
-
-
-
(0xE8)
Reserved
-
-
-
-
-
-
-
-
(0xE7)
Reserved
-
-
-
-
-
-
-
(0xE6)
Reserved
-
-
-
-
-
-
-
-
(0xE5)
Reserved
-
-
-
-
-
-
-
-
(0xE4)
Reserved
-
-
-
-
-
-
-
-
(0xE3)
Reserved
-
-
-
-
-
-
-
(0xE2)
Reserved
-
-
-
-
-
-
-
(0xE1)
Reserved
-
-
-
-
-
-
-
(0xE0)
Reserved
-
-
-
-
-
-
-
(0xDF)
Reserved
-
-
-
-
-
-
-
-
(0xDE)
Reserved
-
-
-
-
-
-
-
-
(0xDD)
Reserved
-
-
-
-
-
-
-
-
(0xDC)
Reserved
-
-
-
-
-
-
-
(0xDB)
Reserved
-
-
-
-
-
-
-
-
(0xDA)
Reserved
-
-
-
-
-
-
-
-
(0xD9)
Reserved
-
-
-
-
-
-
-
-
(0xD8)
Reserved
-
-
-
-
-
-
-
-
(0xD7)
Reserved
-
-
-
-
-
-
-
-
(0xD6)
Reserved
-
-
-
-
-
-
-
-
(0xD5)
Reserved
-
-
-
-
-
-
-
-
(0xD4)
Reserved
-
-
-
-
-
-
-
-
(0xD3)
Reserved
-
-
-
-
-
-
-
-
(0xD2)
Reserved
-
-
-
-
-
-
-
-
(0xD1)
Reserved
-
-
-
-
-
-
-
-
(0xD0)
Reserved
-
-
-
-
-
-
-
-
(0xCF)
Reserved
-
-
-
-
-
-
-
-
(0xCE)
UDR1
(0xCD)
UBRR1H
-
-
-
UBRR1L
(0xCB)
Reserved
-
-
(0xCA)
UCSR1C
UMSEL11
UMSEL10
(0xC9)
UCSR1B
RXCIE1
TXCIE1
(0xC8)
UCSR1A
RXC1
TXC1
(0xC7)
Reserved
-
UDR0
(0xC5)
UBRR0H
-
-
USART1 I/O Data Register
(0xCC)
(0xC6)
-
-
Page
192
USART1 Baud Rate Register High Byte
196/209
USART1 Baud Rate Register Low Byte
196/209
-
-
-
-
-
UPM11
UPM10
USBS1
UCSZ11/UDORD0(5)
UCSZ10/UCPHA0(5)
UCPOL1
194/208
UDRIE1
RXEN1
TXEN1
UCSZ12
RXB81
TXB81
193/207
UDRE1
FE1
DOR1
UPE1
U2X1
MPCM1
192/207
-
-
-
-
-
-
-
-
-
-
-
-
USART0 I/O Data Register
(0xC4)
UBRR0L
(0xC3)
Reserved
-
-
(0xC2)
UCSR0C
UMSEL01
UMSEL00
(0xC1)
UCSR0B
RXCIE0
TXCIE0
192
USART0 Baud Rate Register High Byte
196/209
USART0 Baud Rate Register Low Byte
196/209
-
-
-
-
-
UPM01
UPM00
USBS0
UCSZ01/UDORD0(5)
UCSZ00/UCPHA0(5)
UCPOL0
194/208
UDRIE0
RXEN0
TXEN0
UCSZ02
RXB80
TXB80
193/207
10
8272CS–AVR–06/11
ATmega164A/PA/324A/PA/644A/PA/1284/P
Address
(0xC0)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
UCSR0A
Name
RXC0
TXC0
UDRE0
FE0
DOR0
UPE0
U2X0
MPCM0
192/207
(0xBF)
Reserved
-
-
-
-
-
-
-
-
(0xBE)
Reserved
-
-
-
-
-
-
-
-
(0xBD)
TWAMR
TWAM6
TWAM5
TWAM4
TWAM3
TWAM2
TWAM1
TWAM0
-
238
(0xBC)
TWCR
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
-
TWIE
235
(0xBB)
TWDR
(0xBA)
TWAR
TWA6
TWA5
TWA4
TWA3
2-wire Serial Interface Data Register
TWA2
TWA1
TWA0
TWGCE
237
238
(0xB9)
TWSR
TWS7
TWS6
TWS5
TWS4
TWS3
-
TWPS1
TWPS0
237
(0xB8)
TWBR
(0xB7)
Reserved
-
-
-
-
-
-
-
-
2-wire Serial Interface Bit Rate Register
235
(0xB6)
ASSR
-
EXCLK
AS2
TCN2UB
OCR2AUB
OCR2BUB
TCR2AUB
TCR2BUB
(0xB5)
Reserved
-
-
-
-
-
-
-
-
161
(0xB4)
OCR2B
Timer/Counter2 Output Compare Register B
160
(0xB3)
OCR2A
Timer/Counter2 Output Compare Register A
160
(0xB2)
TCNT2
Timer/Counter2 (8 Bit)
(0xB1)
TCCR2B
FOC2A
FOC2B
-
-
WGM22
CS22
CS21
CS20
159
(0xB0)
TCCR2A
COM2A1
COM2A0
COM2B1
COM2B0
-
-
WGM21
WGM20
156
(0xAF)
Reserved
-
-
-
-
-
-
-
-
160
(0xAE)
Reserved
-
-
-
-
-
-
-
-
(0xAD)
Reserved
-
-
-
-
-
-
-
-
(0xAC)
Reserved
-
-
-
-
-
-
-
-
(0xAB)
Reserved
-
-
-
-
-
-
-
-
(0xAA)
Reserved
-
-
-
-
-
-
-
-
(0xA9)
Reserved
-
-
-
-
-
-
-
-
(0xA8)
Reserved
-
-
-
-
-
-
-
-
(0xA7)
Reserved
-
-
-
-
-
-
-
-
(0xA6)
Reserved
-
-
-
-
-
-
-
-
(0xA5)
Reserved
-
-
-
-
-
-
-
-
(0xA4)
Reserved
-
-
-
-
-
-
-
-
(0xA3)
Reserved
-
-
-
-
-
-
-
-
(0xA2)
Reserved
-
-
-
-
-
-
-
-
(0xA1)
Reserved
-
-
-
-
-
-
-
-
(0xA0)
Reserved
-
-
-
-
-
-
-
-
(0x9F)
Reserved
-
-
-
-
-
-
-
-
(0x9E)
Reserved
-
-
-
-
-
-
-
-
(0x9D)
Reserved
-
-
-
-
-
-
-
-
(0x9C)
Reserved
-
-
-
-
-
-
-
-
(0x9B)
OCR3BH
Timer/Counter3 - Output Compare Register B High Byte
137
(0x9A)
OCR3BL
Timer/Counter3 - Output Compare Register B Low Byte
137
(0x99)
OCR3AH
Timer/Counter3 - Output Compare Register A High Byte
136
(0x98)
OCR3AL
Timer/Counter3 - Output Compare Register A Low Byte
136
(0x97)
ICR3H
Timer/Counter3 - Input Capture Register High Byte
137
(0x96)
ICR3L
Timer/Counter3 - Input Capture Register Low Byte
137
(0x95)
TCNT3H
Timer/Counter3 - Counter Register High Byte
136
(0x94)
TCNT3L
Timer/Counter3 - Counter Register Low Byte
(0x93)
Reserved
-
-
-
(0x92)
TCCR3C
FOC3A
FOC3B
-
-
-
-
-
-
135
(0x91)
TCCR3B
ICNC3
ICES3
-
WGM33
WGM32
CS32
CS31
CS30
134
132
-
-
-
136
-
-
(0x90)
TCCR3A
COM3A1
COM3A0
COM3B1
COM3B0
-
-
WGM31
WGM30
(0x8F)
Reserved
-
-
-
-
-
-
-
-
(0x8E)
Reserved
-
-
-
-
-
-
-
-
(0x8D)
Reserved
-
-
-
-
-
-
-
-
(0x8C)
Reserved
-
-
-
-
-
-
-
-
(0x8B)
OCR1BH
Timer/Counter1 - Output Compare Register B High Byte
137
(0x8A)
OCR1BL
Timer/Counter1 - Output Compare Register B Low Byte
137
(0x89)
OCR1AH
Timer/Counter1 - Output Compare Register A High Byte
136
(0x88)
OCR1AL
Timer/Counter1 - Output Compare Register A Low Byte
136
(0x87)
ICR1H
Timer/Counter1 - Input Capture Register High Byte
137
(0x86)
ICR1L
Timer/Counter1 - Input Capture Register Low Byte
137
(0x85)
TCNT1H
Timer/Counter1 - Counter Register High Byte
136
(0x84)
TCNT1L
Timer/Counter1 - Counter Register Low Byte
(0x83)
Reserved
-
-
-
(0x82)
TCCR1C
FOC1A
FOC1B
-
-
-
-
-
-
135
(0x81)
TCCR1B
ICNC1
ICES1
-
WGM13
WGM12
CS12
CS11
CS10
134
(0x80)
TCCR1A
COM1A1
COM1A0
COM1B1
COM1B0
-
-
WGM11
WGM10
132
(0x7F)
DIDR1
-
-
-
-
-
-
AIN1D
AIN0D
242
-
-
-
136
-
-
11
8272CS–AVR–06/11
ATmega164A/PA/324A/PA/644A/PA/1284/P
Address
Name
(0x7E)
DIDR0
(0x7D)
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
ADC7D
ADC6D
ADC5D
ADC4D
ADC3D
ADC2D
ADC1D
ADC0D
262
-
-
-
-
-
-
-
-
(0x7C)
ADMUX
REFS1
REFS0
ADLAR
MUX4
MUX3
MUX2
MUX1
MUX0
258
(0x7B)
ADCSRB
-
ACME
-
-
-
ADTS2
ADTS1
ADTS0
241
(0x7A)
ADCSRA
ADEN
ADSC
ADATE
ADIF
ADIE
ADPS2
ADPS1
ADPS0
260
(0x79)
ADCH
ADC Data Register High byte
(0x78)
ADCL
ADC Data Register Low byte
(0x77)
Reserved
-
-
-
-
-
-
-
-
(0x76)
Reserved
-
-
-
-
-
-
-
-
(0x75)
Reserved
-
-
-
-
-
-
-
-
(0x74)
Reserved
-
-
-
-
-
-
-
-
(0x73)
PCMSK3
PCINT31
PCINT30
PCINT29
PCINT28
PCINT27
PCINT26
PCINT25
PCINT24
(0x72)
Reserved
-
-
-
-
-
-
-
-
261
261
70
(0x71)
TIMSK3
-
-
ICIE3
-
-
OCIE3B
OCIE3A
TOIE3
139
(0x70)
TIMSK2
-
-
-
-
-
OCIE2B
OCIE2A
TOIE2
162
(0x6F)
TIMSK1
-
-
ICIE1
-
-
OCIE1B
OCIE1A
TOIE1
138
(0x6E)
TIMSK0
-
-
-
-
-
OCIE0B
OCIE0A
TOIE0
109
(0x6D)
PCMSK2
PCINT23
PCINT22
PCINT21
PCINT20
PCINT19
PCINT18
PCINT17
PCINT16
70
(0x6C)
PCMSK1
PCINT15
PCINT14
PCINT13
PCINT12
PCINT11
PCINT10
PCINT9
PCINT8
70
(0x6B)
PCMSK0
PCINT7
PCINT6
PCINT5
PCINT4
PCINT3
PCINT2
PCINT1
PCINT0
71
(0x6A)
Reserved
-
-
-
-
-
-
-
-
(0x69)
EICRA
-
-
ISC21
ISC20
ISC11
ISC10
ISC01
ISC00
67
(0x68)
PCICR
-
-
-
-
PCIE3
PCIE2
PCIE1
PCIE0
69
(0x67)
Reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PRTWI
PRTIM2
PRTIM0
PRUSART1
PRTIM1
PRSPI
PRUSART0
PRADC
-
-
-
-
-
-
-
-
(0x66)
OSCCAL
(0x65)
Reserved
(0x64)
PRR
(0x63)
Reserved
(0x62)
Reserved
(0x61)
CLKPR
(0x60)
WDTCSR
Oscillator Calibration Register
40
48
-
-
-
-
-
-
-
-
CLKPCE
-
-
-
CLKPS3
CLKPS2
CLKPS1
CLKPS0
40
WDIF
WDIE
WDP3
WDCE
WDE
WDP2
WDP1
WDP0
59
I
T
H
S
V
N
Z
C
11
0x3F (0x5F)
SREG
0x3E (0x5E)
SPH
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
12
0x3D (0x5D)
SPL
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
12
0x3C (0x5C)
Reserved
-
-
-
-
-
-
-
-
0x3B (0x5B)
Reserved
-
-
-
-
-
-
-
-
0x3A (0x5A)
Reserved
-
-
-
-
-
-
-
-
0x39 (0x59)
Reserved
-
-
-
-
-
-
-
-
0x38 (0x58)
Reserved
-
-
-
-
-
-
-
-
0x37 (0x57)
SPMCSR
SPMIE
RWWSB
SIGRD
RWWSRE
BLBSET
PGWRT
PGERS
SPMEN
0x36 (0x56)
Reserved
-
-
-
-
-
-
-
-
295
0x35 (0x55)
MCUCR
JTD
BODS(6)
BODSE(6)
PUD
-
-
IVSEL
IVCE
91/278
0x34 (0x54)
MCUSR
-
-
-
JTRF
WDRF
BORF
EXTRF
PORF
58/278
0x33 (0x53)
SMCR
-
-
-
-
SM2
SM1
SM0
SE
47
0x32 (0x52)
Reserved
-
-
-
-
-
-
-
-
0x31 (0x51)
OCDR
0x30 (0x50)
ACSR
ACD
ACBG
ACO
ACI
ACIE
ACIC
ACIS1
ACIS0
0x2F (0x4F)
Reserved
-
-
-
-
-
-
-
-
-
-
-
SPI2X0
172
CPOL0
CPHA0
SPR01
SPR00
171
On-Chip Debug Register
268
SPI 0 Data Register
260
0x2E (0x4E)
SPDR
0x2D (0x4D)
SPSR
SPIF0
WCOL0
-
-
0x2C (0x4C)
SPCR
SPIE0
SPE0
DORD0
MSTR0
0x2B (0x4B)
GPIOR2
General Purpose I/O Register 2
0x2A (0x4A)
GPIOR1
General Purpose I/O Register 1
0x29 (0x49)
Reserved
0x28 (0x48)
OCR0B
Timer/Counter0 Output Compare Register B
108
0x27 (0x47)
OCR0A
Timer/Counter0 Output Compare Register A
108
0x26 (0x46)
TCNT0
Timer/Counter0 (8 Bit)
0x25 (0x45)
TCCR0B
FOC0A
FOC0B
-
-
WGM02
CS02
-
-
-
-
173
29
29
-
-
-
-
108
CS01
CS00
107
0x24 (0x44)
TCCR0A
COM0A1
COM0A0
COM0B1
COM0B0
-
-
WGM01
WGM00
108
0x23 (0x43)
GTCCR
TSM
-
-
-
-
-
PSRASY
PSRSYNC
163
0x22 (0x42)
EEARH
-
-
-
-
0x21 (0x41)
EEARL
EEPROM Address Register Low Byte
0x20 (0x40)
EEDR
EEPROM Data Register
0x1F (0x3F)
EECR
0x1E (0x3E)
GPIOR0
0x1D (0x3D)
EIMSK
-
-
EEPM1
EEPROM Address Register High Byte
EEPM0
EERIE
24
24
24
EEMPE
EEPE
EERE
24
INT1
INT0
68
General Purpose I/O Register 0
-
-
-
-
-
29
INT2
12
8272CS–AVR–06/11
ATmega164A/PA/324A/PA/644A/PA/1284/P
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
0x1C (0x3C)
Address
EIFR
Name
-
-
-
-
-
INTF2
INTF1
INTF0
68
0x1B (0x3B)
PCIFR
-
-
-
-
PCIF3
PCIF2
PCIF1
PCIF0
69
0x1A (0x3A)
Reserved
-
-
-
-
-
-
-
-
0x19 (0x39)
Reserved
-
-
-
-
-
-
-
-
0x18 (0x38)
TIFR3
-
-
ICF3
-
-
OCF3B
OCF3A
TOV3
140
0x17 (0x37)
TIFR2
-
-
-
-
-
OCF2B
OCF2A
TOV2
162
0x16 (0x36)
TIFR1
-
-
ICF1
-
-
OCF1B
OCF1A
TOV1
139
0x15 (0x35)
TIFR0
-
-
-
-
-
OCF0B
OCF0A
TOV0
109
0x14 (0x34)
Reserved
-
-
-
-
-
-
-
-
0x13 (0x33)
Reserved
-
-
-
-
-
-
-
-
0x12 (0x32)
Reserved
-
-
-
-
-
-
-
-
0x11 (0x31)
Reserved
-
-
-
-
-
-
-
-
0x10 (0x30)
Reserved
-
-
-
-
-
-
-
-
0x0F (0x2F)
Reserved
-
-
-
-
-
-
-
-
0x0E (0x2E)
Reserved
-
-
-
-
-
-
-
-
0x0D (0x2D)
Reserved
-
-
-
-
-
-
-
-
0x0C (0x2C)
Reserved
-
-
-
-
-
-
-
-
0x0B (0x2B)
PORTD
PORTD7
PORTD6
PORTD5
PORTD4
PORTD3
PORTD2
PORTD1
PORTD0
92
0x0A (0x2A)
DDRD
DDD7
DDD6
DDD5
DDD4
DDD3
DDD2
DDD1
DDD0
92
92
0x09 (0x29)
PIND
PIND7
PIND6
PIND5
PIND4
PIND3
PIND2
PIND1
PIND0
0x08 (0x28)
PORTC
PORTC7
PORTC6
PORTC5
PORTC4
PORTC3
PORTC2
PORTC1
PORTC0
92
0x07 (0x27)
DDRC
DDC7
DDC6
DDC5
DDC4
DDC3
DDC2
DDC1
DDC0
92
0x06 (0x26)
PINC
PINC7
PINC6
PINC5
PINC4
PINC3
PINC2
PINC1
PINC0
92
0x05 (0x25)
PORTB
PORTB7
PORTB6
PORTB5
PORTB4
PORTB3
PORTB2
PORTB1
PORTB0
91
0x04 (0x24)
DDRB
DDB7
DDB6
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0
91
0x03 (0x23)
PINB
PINB7
PINB6
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
91
0x02 (0x22)
PORTA
PORTA7
PORTA6
PORTA5
PORTA4
PORTA3
PORTA2
PORTA1
PORTA0
91
0x01 (0x21)
DDRA
DDA7
DDA6
DDA5
DDA4
DDA3
DDA2
DDA1
DDA0
91
0x00 (0x20)
PINA
PINA7
PINA6
PINA5
PINA4
PINA3
PINA2
PINA1
PINA0
91
Notes:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on
all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions
work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O registers as data space using LD and ST instructions, $20 must be added to these addresses.
The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is a complex microcontroller with more peripheral units
than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O
space from $60 - $FF, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
5. USART in SPI Master Mode.
6. Only available in the ATmega164PA/324PA/644PA/1284P.
13
8272CS–AVR–06/11
ATmega164A/PA/324A/PA/644A/PA/1284/P
8. Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
Add two Registers
Rd ← Rd + Rr
Z,C,N,V,H
ADC
Rd, Rr
Add with Carry two Registers
Rd ← Rd + Rr + C
Z,C,N,V,H
1
ADIW
Rdl,K
Add Immediate to Word
Rdh:Rdl ← Rdh:Rdl + K
Z,C,N,V,S
2
SUB
Rd, Rr
Subtract two Registers
Rd ← Rd - Rr
Z,C,N,V,H
1
SUBI
Rd, K
Subtract Constant from Register
Rd ← Rd - K
Z,C,N,V,H
1
SBC
Rd, Rr
Subtract with Carry two Registers
Rd ← Rd - Rr - C
Z,C,N,V,H
1
SBCI
Rd, K
Subtract with Carry Constant from Reg.
Rd ← Rd - K - C
Z,C,N,V,H
1
SBIW
Rdl,K
Subtract Immediate from Word
Rdh:Rdl ← Rdh:Rdl - K
Z,C,N,V,S
2
AND
Rd, Rr
Logical AND Registers
Rd ← Rd • Rr
Z,N,V
1
ANDI
Rd, K
Logical AND Register and Constant
Rd ← Rd • K
Z,N,V
1
OR
Rd, Rr
Logical OR Registers
Rd ← Rd v Rr
Z,N,V
1
ORI
Rd, K
Logical OR Register and Constant
Rd ← Rd v K
Z,N,V
1
EOR
Rd, Rr
Exclusive OR Registers
Rd ← Rd ⊕ Rr
Z,N,V
1
1
COM
Rd
One’s Complement
Rd ← 0xFF − Rd
Z,C,N,V
1
NEG
Rd
Two’s Complement
Rd ← 0x00 − Rd
Z,C,N,V,H
1
SBR
Rd,K
Set Bit(s) in Register
Rd ← Rd v K
Z,N,V
1
CBR
Rd,K
Clear Bit(s) in Register
Rd ← Rd • (0xFF - K)
Z,N,V
1
INC
Rd
Increment
Rd ← Rd + 1
Z,N,V
1
DEC
Rd
Decrement
Rd ← Rd − 1
Z,N,V
1
TST
Rd
Test for Zero or Minus
Rd ← Rd • Rd
Z,N,V
1
CLR
Rd
Clear Register
Rd ← Rd ⊕ Rd
Z,N,V
1
SER
Rd
Set Register
Rd ← 0xFF
None
1
MUL
Rd, Rr
Multiply Unsigned
R1:R0 ← Rd x Rr
Z,C
2
MULS
Rd, Rr
Multiply Signed
R1:R0 ← Rd x Rr
Z,C
2
MULSU
Rd, Rr
Multiply Signed with Unsigned
R1:R0 ← Rd x Rr
Z,C
2
FMUL
Rd, Rr
Fractional Multiply Unsigned
R1:R0 ← (Rd x Rr) << 1
Z,C
2
FMULS
Rd, Rr
Fractional Multiply Signed
R1:R0 ← (Rd x Rr) << 1
Z,C
2
FMULSU
Rd, Rr
Fractional Multiply Signed with Unsigned
R1:R0 ← (Rd x Rr) << 1
Z,C
2
2
BRANCH INSTRUCTIONS
RJMP
k
IJMP
Relative Jump
PC ← PC + k + 1
None
Indirect Jump to (Z)
PC ← Z
None
2
JMP
k
Direct Jump
PC ← k
None
3
RCALL
k
Relative Subroutine Call
PC ← PC + k + 1
None
4
Indirect Call to (Z)
PC ← Z
None
4
Direct Subroutine Call
PC ← k
None
5
RET
Subroutine Return
PC ← STACK
None
5
RETI
Interrupt Return
PC ← STACK
I
5
ICALL
CALL
k
CPSE
Rd,Rr
Compare, Skip if Equal
if (Rd = Rr) PC ← PC + 2 or 3
None
CP
Rd,Rr
Compare
Rd − Rr
Z, N,V,C,H
1
CPC
Rd,Rr
Compare with Carry
Rd − Rr − C
Z, N,V,C,H
1
CPI
Rd,K
Compare Register with Immediate
Rd − K
Z, N,V,C,H
SBRC
Rr, b
Skip if Bit in Register Cleared
if (Rr(b)=0) PC ← PC + 2 or 3
None
1/2/3
1/2/3
1
SBRS
Rr, b
Skip if Bit in Register is Set
if (Rr(b)=1) PC ← PC + 2 or 3
None
1/2/3
SBIC
P, b
Skip if Bit in I/O Register Cleared
if (P(b)=0) PC ← PC + 2 or 3
None
1/2/3
SBIS
P, b
Skip if Bit in I/O Register is Set
if (P(b)=1) PC ← PC + 2 or 3
None
1/2/3
BRBS
s, k
Branch if Status Flag Set
if (SREG(s) = 1) then PC←PC+k + 1
None
1/2
BRBC
s, k
Branch if Status Flag Cleared
if (SREG(s) = 0) then PC←PC+k + 1
None
1/2
BREQ
k
Branch if Equal
if (Z = 1) then PC ← PC + k + 1
None
1/2
BRNE
k
Branch if Not Equal
if (Z = 0) then PC ← PC + k + 1
None
1/2
BRCS
k
Branch if Carry Set
if (C = 1) then PC ← PC + k + 1
None
1/2
BRCC
k
Branch if Carry Cleared
if (C = 0) then PC ← PC + k + 1
None
1/2
BRSH
k
Branch if Same or Higher
if (C = 0) then PC ← PC + k + 1
None
1/2
BRLO
k
Branch if Lower
if (C = 1) then PC ← PC + k + 1
None
1/2
BRMI
k
Branch if Minus
if (N = 1) then PC ← PC + k + 1
None
1/2
BRPL
k
Branch if Plus
if (N = 0) then PC ← PC + k + 1
None
1/2
BRGE
k
Branch if Greater or Equal, Signed
if (N ⊕ V= 0) then PC ← PC + k + 1
None
1/2
BRLT
k
Branch if Less Than Zero, Signed
if (N ⊕ V= 1) then PC ← PC + k + 1
None
1/2
BRHS
k
Branch if Half Carry Flag Set
if (H = 1) then PC ← PC + k + 1
None
1/2
BRHC
k
Branch if Half Carry Flag Cleared
if (H = 0) then PC ← PC + k + 1
None
1/2
BRTS
k
Branch if T Flag Set
if (T = 1) then PC ← PC + k + 1
None
1/2
BRTC
k
Branch if T Flag Cleared
if (T = 0) then PC ← PC + k + 1
None
1/2
BRVS
k
Branch if Overflow Flag is Set
if (V = 1) then PC ← PC + k + 1
None
1/2
14
8272CS–AVR–06/11
ATmega164A/PA/324A/PA/644A/PA/1284/P
Mnemonics
Operands
Description
Operation
Flags
#Clocks
BRVC
k
Branch if Overflow Flag is Cleared
if (V = 0) then PC ← PC + k + 1
None
1/2
BRIE
k
Branch if Interrupt Enabled
if ( I = 1) then PC ← PC + k + 1
None
1/2
BRID
k
Branch if Interrupt Disabled
if ( I = 0) then PC ← PC + k + 1
None
1/2
BIT AND BIT-TEST INSTRUCTIONS
SBI
P,b
Set Bit in I/O Register
I/O(P,b) ← 1
None
2
CBI
P,b
Clear Bit in I/O Register
I/O(P,b) ← 0
None
2
LSL
Rd
Logical Shift Left
Rd(n+1) ← Rd(n), Rd(0) ← 0
Z,C,N,V
1
LSR
Rd
Logical Shift Right
Rd(n) ← Rd(n+1), Rd(7) ← 0
Z,C,N,V
1
ROL
Rd
Rotate Left Through Carry
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Z,C,N,V
1
ROR
Rd
Rotate Right Through Carry
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
Z,C,N,V
1
ASR
Rd
Arithmetic Shift Right
Rd(n) ← Rd(n+1), n=0..6
Z,C,N,V
1
SWAP
Rd
Swap Nibbles
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
None
1
BSET
s
Flag Set
SREG(s) ← 1
SREG(s)
1
BCLR
s
Flag Clear
SREG(s) ← 0
SREG(s)
1
BST
Rr, b
Bit Store from Register to T
T ← Rr(b)
T
1
BLD
Rd, b
Bit load from T to Register
Rd(b) ← T
None
1
SEC
Set Carry
C←1
C
1
CLC
Clear Carry
C←0
C
1
SEN
Set Negative Flag
N←1
N
1
CLN
Clear Negative Flag
N←0
N
1
SEZ
Set Zero Flag
Z←1
Z
1
CLZ
Clear Zero Flag
Z←0
Z
1
SEI
Global Interrupt Enable
I←1
I
1
CLI
Global Interrupt Disable
I←0
I
1
SES
Set Signed Test Flag
S←1
S
1
CLS
Clear Signed Test Flag
S←0
S
1
SEV
Set Twos Complement Overflow.
V←1
V
1
CLV
Clear Twos Complement Overflow
V←0
V
1
SET
Set T in SREG
T←1
T
1
CLT
Clear T in SREG
T←0
T
1
SEH
CLH
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
H←1
H←0
H
H
1
1
Rd ← Rr
Rd+1:Rd ← Rr+1:Rr
None
1
None
1
1
DATA TRANSFER INSTRUCTIONS
MOV
Rd, Rr
Move Between Registers
MOVW
Rd, Rr
Copy Register Word
LDI
Rd, K
Load Immediate
Rd ← K
None
LD
Rd, X
Load Indirect
Rd ← (X)
None
2
LD
Rd, X+
Load Indirect and Post-Inc.
Rd ← (X), X ← X + 1
None
2
2
LD
Rd, - X
Load Indirect and Pre-Dec.
X ← X - 1, Rd ← (X)
None
LD
Rd, Y
Load Indirect
Rd ← (Y)
None
2
LD
Rd, Y+
Load Indirect and Post-Inc.
Rd ← (Y), Y ← Y + 1
None
2
LD
Rd, - Y
Load Indirect and Pre-Dec.
Y ← Y - 1, Rd ← (Y)
None
2
LDD
Rd,Y+q
Load Indirect with Displacement
Rd ← (Y + q)
None
2
LD
Rd, Z
Load Indirect
Rd ← (Z)
None
2
LD
Rd, Z+
Load Indirect and Post-Inc.
Rd ← (Z), Z ← Z+1
None
2
LD
Rd, -Z
Load Indirect and Pre-Dec.
Z ← Z - 1, Rd ← (Z)
None
2
LDD
Rd, Z+q
Load Indirect with Displacement
Rd ← (Z + q)
None
2
LDS
Rd, k
Load Direct from SRAM
Rd ← (k)
None
2
ST
X, Rr
Store Indirect
(X) ← Rr
None
2
ST
X+, Rr
Store Indirect and Post-Inc.
(X) ← Rr, X ← X + 1
None
2
ST
- X, Rr
Store Indirect and Pre-Dec.
X ← X - 1, (X) ← Rr
None
2
ST
Y, Rr
Store Indirect
(Y) ← Rr
None
2
ST
Y+, Rr
Store Indirect and Post-Inc.
(Y) ← Rr, Y ← Y + 1
None
2
ST
- Y, Rr
Store Indirect and Pre-Dec.
Y ← Y - 1, (Y) ← Rr
None
2
STD
Y+q,Rr
Store Indirect with Displacement
(Y + q) ← Rr
None
2
ST
Z, Rr
Store Indirect
(Z) ← Rr
None
2
ST
Z+, Rr
Store Indirect and Post-Inc.
(Z) ← Rr, Z ← Z + 1
None
2
ST
-Z, Rr
Store Indirect and Pre-Dec.
Z ← Z - 1, (Z) ← Rr
None
2
STD
Z+q,Rr
Store Indirect with Displacement
(Z + q) ← Rr
None
2
STS
k, Rr
Store Direct to SRAM
(k) ← Rr
None
2
Load Program Memory
R0 ← (Z)
None
3
LPM
LPM
Rd, Z
Load Program Memory
Rd ← (Z)
None
3
LPM
Rd, Z+
Load Program Memory and Post-Inc
Rd ← (Z), Z ← Z+1
None
3
Store Program Memory
(Z) ← R1:R0
None
-
IN
Rd, P
In Port
Rd ← P
None
1
OUT
P, Rr
Out Port
P ← Rr
None
1
SPM
15
8272CS–AVR–06/11
ATmega164A/PA/324A/PA/644A/PA/1284/P
Mnemonics
Operands
Description
Operation
Flags
#Clocks
PUSH
Rr
Push Register on Stack
STACK ← Rr
None
2
POP
Rd
Pop Register from Stack
Rd ← STACK
None
2
MCU CONTROL INSTRUCTIONS
NOP
No Operation
None
1
SLEEP
Sleep
(see specific descr. for Sleep function)
None
1
WDR
BREAK
Watchdog Reset
Break
(see specific descr. for WDR/timer)
For On-chip Debug Only
None
None
1
N/A
16
8272CS–AVR–06/11
ATmega164A/PA/324A/PA/644A/PA/1284/P
9. Ordering Information
9.1
ATmega164A
Speed (MHz)(3)
20
Notes:
Power Supply
1.8 - 5.5V
Ordering Code(2)
Package(1)
ATmega164A-AU
ATmega164A-AUR(5)
ATmega164A-PU
ATmega164A-MU
ATmega164A-MUR(5)
ATmega164A-MCH(4)
ATmega164A-MCHR(4)(5)
ATmega164A-CU
ATmega164A-CUR(5)
44A
44A
40P6
44M1
44M1
44MC
44MC
49C2
49C2
Operational Range
Industrial
(-40oC to 85oC)
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC see ”Speed Grades” on page 335.
4. NiPdAu Lead Finish.
5. Tape & Reel.
Package Type
44A
44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
40P6
40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)
44M1
44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Thermally Enhanced Plastic Very Thin Quad Flat No-Lead (VQFN)
44MC
44-lead (2-row Staggered), 5 x 5 x 1.0 mm body, 2.60 x 2.60 mm Exposed Pad, Quad Flat No-Lead Package (QFN)
49C2
49-ball, (7 x 7 Array) 0.65 mm Pitch, 5 x 5 x 1 mm, Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA)
17
8272CS–AVR–06/11
ATmega164A/PA/324A/PA/644A/PA/1284/P
9.2
ATmega164PA
Speed (MHz)(3)
20
Notes:
Power Supply
1.8 - 5.5V
Ordering Code(2)
Package(1)
ATmega164PA-AU
ATmega164PA-AUR(5)
ATmega164PA-PU
ATmega164PA-MU
ATmega164PA-MUR(5)
ATmega164PA-MCH(4)
ATmega164PA-MCHR(4)(5)
ATmega164PA-CU
ATmega164PA-CUR(5)
44A
44A
40P6
44M1
44M1
44MC
44MC
49C2
49C2
Operational Range
Industrial
(-40oC to 85oC)
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC see ”Speed Grades” on page 335.
4. NiPdAu Lead Finish.
5. Tape & Reel.
Package Type
44A
44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
40P6
40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)
44M1
44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Thermally Enhanced Plastic Very Thin Quad Flat No-Lead (VQFN)
44MC
44-lead (2-row Staggered), 5 x 5 x 1.0 mm body, 2.60 x 2.60 mm Exposed Pad, Quad Flat No-Lead Package (QFN)
49C2
49-ball, (7 x 7 Array) 0.65 mm Pitch, 5 x 5 x 1 mm, Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA)
18
8272CS–AVR–06/11
ATmega164A/PA/324A/PA/644A/PA/1284/P
9.3
ATmega324A
Speed (MHz)(3)
20
Notes:
Power Supply
1.8 - 5.5V
Ordering Code(2)
Package(1)
ATmega324A-AU
ATmega324A-AUR(5)
ATmega324A-PU
ATmega324A-MU
ATmega324A-MUR(5)
ATmega324A-MCH(4)
ATmega324A-MCHR(4)(5)
ATmega324A-CU
ATmega324A-CUR(5)
44A
44A
40P6
44M1
44M1
44MC
44MC
49C2
49C2
Operational Range
Industrial
(-40oC to 85oC)
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC see ”Speed Grades” on page 335.
4. NiPdAu Lead Finish.
5. Tape & Reel.
Package Type
44A
44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
40P6
40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)
44M1
44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Thermally Enhanced Plastic Very Thin Quad Flat No-Lead (VQFN)
44MC
44-lead (2-row Staggered), 5 x 5 x 1.0 mm body, 2.60 x 2.60 mm Exposed Pad, Quad Flat No-Lead Package (QFN)
49C2
49-ball, (7 x 7 Array) 0.65 mm Pitch, 5 x 5 x 1 mm, Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA)
19
8272CS–AVR–06/11
ATmega164A/PA/324A/PA/644A/PA/1284/P
9.4
ATmega324PA
Speed (MHz)(3)
20
Notes:
Power Supply
1.8 - 5.5V
Ordering Code(2)
Package(1)
ATmega324PA-AU
ATmega324PA-AUR(5)
ATmega324PA-PU
ATmega324PA-MU
ATmega324PA-MUR(5)
ATmega324PA-MCH(4)
ATmega324PA-MCHR(4)(5)
ATmega324PA-CU
ATmega324PA-CUR(5)
44A
44A
40P6
44M1
44M1
44MC
44MC
49C2
49C2
Operational Range
Industrial
(-40oC to 85oC)
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC see ”Speed Grades” on page 335.
4. NiPdAu Lead Finish.
5. Tape & Reel.
Package Type
44A
44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
40P6
40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)
44M1
44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Thermally Enhanced Plastic Very Thin Quad Flat No-Lead (VQFN)
44MC
44-lead (2-row Staggered), 5 x 5 x 1.0 mm body, 2.60 x 2.60 mm Exposed Pad, Quad Flat No-Lead Package (QFN)
49C2
49-ball, (7 x 7 Array) 0.65 mm Pitch, 5 x 5 x 1 mm, Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA)
20
8272CS–AVR–06/11
ATmega164A/PA/324A/PA/644A/PA/1284/P
9.5
ATmega644A
Speed (MHz)(3)
20
Notes:
Power Supply
1.8 - 5.5V
Ordering Code(2)
Package(1)
ATmega644A-AU
ATmega644A-AUR(4)
ATmega644A-PU
ATmega644A-MU
ATmega644A-MUR(4)
44A
44A
40P6
44M1
44M1
Operational Range
Industrial
(-40oC to 85oC)
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC see ”Speed Grades” on page 335.
4. Taper & Reel.
Package Type
44A
44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
40P6
40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)
44M1
44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Thermally Enhanced Plastic Very Thin Quad Flat No-Lead (VQFN)
21
8272CS–AVR–06/11
ATmega164A/PA/324A/PA/644A/PA/1284/P
9.6
ATmega644PA
Speed (MHz)(3)
20
Notes:
Power Supply
1.8 - 5.5V
Ordering Code(2)
Package(1)
ATmega644PA-AU
ATmega644PA-AUR(4)
ATmega644PA-PU
ATmega644PA-MU
ATmega644PA-MUR(4)
44A
44A
40P6
44M1
44M1
Operational Range
Industrial
(-40oC to 85oC)
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC see ”Speed Grades” on page 335.
4. Taper & Reel.
Package Type
44A
44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
40P6
40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)
44M1
44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Thermally Enhanced Plastic Very Thin Quad Flat No-Lead (VQFN)
22
8272CS–AVR–06/11
ATmega164A/PA/324A/PA/644A/PA/1284/P
9.7
ATmega1284
Speed (MHz)(3)
20
Notes:
Power Supply
1.8 - 5.5V
Ordering Code(2)
Package(1)
ATmega1284-AU
ATmega1284-AUR(4)
ATmega1284-PU
ATmega1284-MU
ATmega1284-MUR(4)
44A
44A
40P6
44M1
44M1
Operational Range
Industrial
(-40oC to 85oC)
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC see ”Speed Grades” on page 335.
4. Tape & Reel.
Package Type
44A
44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
40P6
40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)
44M1
44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
23
8272CS–AVR–06/11
ATmega164A/PA/324A/PA/644A/PA/1284/P
9.8
ATmega1284P
Speed (MHz)(3)
20
Notes:
Power Supply
1.8 - 5.5V
Ordering Code(2)
Package(1)
ATmega1284P-AU
ATmega1284P-AUR(4)
ATmega1284P-PU
ATmega1284P-MU
ATmega1284P-MUR(4)
44A
44A
40P6
44M1
44M1
Operational Range
Industrial
(-40oC to 85oC)
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC see ”Speed Grades” on page 335.
4. Tape & Reel.
Package Type
44A
44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
40P6
40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)
44M1
44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
24
8272CS–AVR–06/11
ATmega164A/PA/324A/PA/644A/PA/1284/P
10. Packaging Information
10.1
44A
PIN 1 IDENTIFIER
PIN 1
e
B
E1
E
D1
D
C
0°~7°
A1
A2
A
L
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10 mm maximum.
SYMBOL
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
11.75
12.00
12.25
D1
9.90
10.00
10.10
E
11.75
12.00
12.25
E1
9.90
10.00
10.10
B
0.30
–
0.45
C
0.09
–
0.20
L
0.45
–
0.75
e
NOTE
Note 2
Note 2
0.80 TYP
2010-10-20
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
DRAWING NO.
REV.
44A
C
25
8272CS–AVR–06/11
ATmega164A/PA/324A/PA/644A/PA/1284/P
10.2
40P6
D
PIN
1
E1
A
SEATING PLANE
A1
L
B
B1
e
E
0º ~ 15º
C
COMMON DIMENSIONS
(Unit of Measure = mm)
REF
MIN
NOM
MAX
A
–
–
4.826
A1
0.381
–
–
SYMBOL
eB
Notes:
1. This package conforms to JEDEC reference MS-011, Variation AC.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
D
52.070
–
52.578
E
15.240
–
15.875
E1
13.462
–
13.970
B
0.356
–
0.559
B1
1.041
–
1.651
L
3.048
–
3.556
C
0.203
–
0.381
eB
15.494
–
17.526
e
NOTE
Note 2
Note 2
2.540 TYP
09/28/01
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual
Inline Package (PDIP)
DRAWING NO.
40P6
REV.
B
26
8272CS–AVR–06/11
ATmega164A/PA/324A/PA/644A/PA/1284/P
10.3
44M1
D
Marked Pin# 1 ID
E
SEATING PLANE
A1
TOP VIEW
A3
A
K
L
Pin #1 Corner
D2
1
2
3
Option A
SIDE VIEW
Pin #1
Triangle
E2
Option B
K
Option C
b
e
Pin #1
Chamfer
(C 0.30)
Pin #1
Notch
(0.20 R)
BOTTOM VIEW
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
A
0.80
0.90
1.00
A1
–
0.02
0.05
A3
0.20 REF
b
0.18
0.23
0.30
D
6.90
7.00
7.10
D2
5.00
5.20
5.40
E
6.90
7.00
7.10
E2
5.00
5.20
5.40
e
Note: JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-3.
NOTE
0.50 BSC
L
0.59
0.64
0.69
K
0.20
0.26
0.41
9/26/08
Package Drawing Contact:
packagedrawings@atmel.com
TITLE
44M1, 44-pad, 7 x 7 x 1.0 mm Body, Lead
Pitch 0.50 mm, 5.20 mm Exposed Pad, Thermally
Enhanced Plastic Very Thin Quad Flat No
Lead Package (VQFN)
GPC
ZWS
DRAWING NO.
REV.
44M1
H
27
8272CS–AVR–06/11
ATmega164A/PA/324A/PA/644A/PA/1284/P
10.4
44MC
C
Pin 1 ID
D
SIDE VIEW
y
A1
E
A
TOP VIEW
eT/2
A19
eR
A24
B20
B16
A1
A18
COMMON DIMENSIONS
(Unit of Measure = mm)
B1
B15
b
R0.20
0.40
D2
eT
SYMBOL
MIN
NOM
MAX
A
0.80
0.90
1.00
A1
0.00
0.02
0.05
b
0.18
0.23
0.30
C
B5
B11
A6
A13
B10
B6
A12
L
0.20 REF
D
4.90
5.00
5.10
D2
2.55
2.60
2.65
E
4.90
5.00
5.10
E2
2.55
2.60
2.65
eT
–
0.70
–
eR
–
0.40
–
K
0.45
–
–
L
0.30
0.35
0.40
y
0.00
–
0.075
A7
L
E2
BOTTOM VIEW
Note:
NOTE
1. The terminal #1 ID is a Laser-marked Feature.
Package Drawing Contact:
packagedrawings@atmel.com
L
TITLE
44MC, 44QFN (2-Row Staggered), 5 x 5 x 1.00 mm Body,
2.60 x 2.60 mm Exposed Pad, Quad Flat No Lead Package
9/13/07
DRAWING NO. REV.
44MC
A
28
8272CS–AVR–06/11
ATmega164A/PA/324A/PA/644A/PA/1284/P
10.5
49C2
E
A1 BALL ID
0.10
D
A1
TOP VIEW
A
A2
SIDE VIEW
E1
G
e
F
E
D
D1
COMMON DIMENSIONS
(Unit of Measure = mm)
C
B
1
A1 BALL CORNER
MIN
NOM
MAX
A
–
–
1.00
A1
0.20
–
–
A2
0.65
–
–
D
4.90
5.00
5.10
SYMBOL
A
2
3
4
5
b
6
7
e
BOTTOM VIEW
49 - Ø0.35 ± 0.05
D1
E
3.90 BSC
4.90
5.00
E1
b
NOTE
5.10
3.90 BSC
0.30
0.35
e
0.40
0.65 BSC
3/14/08
Package Drawing Contact:
packagedrawings@atmel.com
TITLE
49C2, 49-ball (7 x 7 Array), 0.65 mm Pitch,
5.0 x 5.0 x 1.0 mm, Very Thin, Fine-Pitch
Ball Grid Array Package (VFBGA)
GPC
CBD
DRAWING NO.
REV.
49C2
A
29
8272CS–AVR–06/11
ATmega164A/PA/324A/PA/644A/PA/1284/P
11. Errata
11.1
11.1.1
Errata for ATmega164A
Rev. E
No known Errata.
11.2
11.2.1
Errata for ATmega164PA
Rev. E
No known Errata.
11.3
11.3.1
Errata for ATmega324A
Rev. F
No known Errata.
11.4
11.4.1
Errata for ATmega324PA
Rev. F
No known Errata.
11.5
11.5.1
Errata for ATmega644A
Rev. F
No known Errata.
11.6
11.6.1
Errata for ATmega644PA
Rev. F
No known Errata.
11.7
11.7.1
Errata for ATmega1284
Rev. B
No known Errata.
11.8
11.8.1
Errata for ATmega1284P
Rev. B
No known Errata.
30
8272CS–AVR–06/11
ATmega164A/PA/324A/PA/644A/PA/1284/P
12. Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The
referring revision in this section are referring to the document revision.
12.1
Rev. 8272C - 06/11
1.
12.2
Updated ”ATmega1284P DC Characteristics” on page 334.
Rev. 8272B - 05/11
1.
2.
3.
4.
5.
6.
Added Atmel QTouch Library Support and QTouch Sensing Capability Features.
Replaced Figure 1-1 on page 2 by an updated “Pinout” that includes Timer/Counter3.
Replaced Figure 7-1 on page 10 by an updated “Block Diagram of the AVR Architecture” that
includes Timer/Counter3.
Added ”RAMPZ – Extended Z-pointer Register for ELPM/SPM(1)” on page 15.
Added ”PRR1 – Power Reduction Register 1” on page 49.
Renamed PRR to ”PRR0 – Power Reduction Register 0” on page 48.
7.
Updated ”PCIFR – Pin Change Interrupt Flag Register” on page 69. PCICR replaces EIMSR in
the PCIF3, PCIF2, PCIF1 and PCIF0 bit description.
8.
Updated ”PCMSK3 – Pin Change Mask Register 3” on page 70. PCIE3 replaces PCIE2 in the bit
description.
9.
Updated ”Alternate Functions of Port B” on page 82 to include Timer/Counter3
10.
Updated ”Alternate Functions of Port D” on page 88 to include Timer/Counter3
11.
Added ”TCNT3H and TCNT3L –Timer/Counter3” on page 136
12.
Added ”OCR3AH and OCR3AL – Output Compare Register3 A” on page 137
13.
Added ”OCR3BH and OCR3BL – Output Compare Register3 B” on page 137
14.
Added ”TIMSK3 – Timer/Counter3 Interrupt Mask Register” on page 139
15.
Updated All “SPI – Serial Peripheral Interface” “Register Description” to reflect ATmega1284 and
ATmega1284P.
16.
Updated ”Addressing the Flash During Self-Programming” on page 284 to include RAMPZ
register.
17.
Updated Table 27-16 on page 314. tWD_EEPROM is 3.6ms instead of 9ms.
18.
BODS and BODSE bits denoted as R/W
19.
Description of external pin modes below table 16-9 removed.
20.
Updated ”Register Summary” on page 10 to include Timer/Counter3.
21.
Updated the datasheet with Atmel new style guide.
31
8272CS–AVR–06/11
ATmega164A/PA/324A/PA/644A/PA/1284/P
12.3
Rev. 8272A - 01/10
1.
Initial revision (Based on ATmega164PA/324PA/644PA/1284P datasheet 8252G-AVR-11/09 and
on ATmega644 datasheet 2593N-AVR-09/09).
2.
Changes done:
– Non-picoPower devices added: ATmega164A/324A/644A/1284
– Updated Table 2-1 on page 7
– Updated Table 10-1 on page 42
– Updated ”Sleep Modes” on page 42 and ”BOD Disable(1)” on page 43
– Updated ”Register Description” on page 67
– Updated ”USART” on page 174 and ”USART in SPI Mode” on page 201
– Updated ”Signature Bytes” on page 300 and ”Page Size” on page 300
– Added ”DC Characteristics” on page 329 for non-picoPower devices.
– Added ”ATmega164A Typical Characteristics” on page 345
– Added ”ATmega324A Typical Characteristics” on page 397
– Added ”ATmega644A Typical Characteristics” on page 449
– Added ”ATmega1284 Typical Characteristics” on page 501
– Added ”Ordering Information” on page 17 for non-picoPower devices
– Added ”Errata for ATmega164A” on page 30
– Added ”Errata for ATmega324A” on page 30
– Added ”Errata for ATmega644PA” on page 30
– Added ”Errata for ATmega1284” on page 30
32
8272CS–AVR–06/11
Atmel Corporation
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Fax: (+81)(3) 3523-7581
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8272CS–AVR–06/11