MPC5606B Microcontroller Reference Manual

MPC5606BK Microcontroller
Reference Manual
Devices Supported:
MPC5606BK
MPC5605BK
MPC5606BKRM
Rev. 2
05/2014
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Chapter 1
Preface
1.1
1.2
1.3
1.4
1.5
1.6
1.7
Overview .........................................................................................................................................21
Audience ..........................................................................................................................................21
Guide to this reference manual ........................................................................................................21
Register description conventions ....................................................................................................25
References .......................................................................................................................................26
How to use the MPC5606BK documents .......................................................................................26
1.6.1
The MPC5606BK document set .....................................................................................26
1.6.2
Reference manual content ..............................................................................................27
Using the MPC5606BK ..................................................................................................................28
1.7.1
Hardware design .............................................................................................................28
1.7.2
Input/output pins .............................................................................................................29
1.7.3
Software design ..............................................................................................................29
1.7.4
Other features .................................................................................................................30
Chapter 2
Introduction
2.1
2.2
2.3
2.4
2.5
The MPC5606BK microcontroller family ......................................................................................31
MPC5606BK device comparison ....................................................................................................31
Device block diagram ......................................................................................................................32
Feature details .................................................................................................................................35
2.4.1
e200z0h core processor ..................................................................................................35
2.4.2
Crossbar switch (XBAR) ................................................................................................35
2.4.3
Interrupt Controller (INTC) ............................................................................................35
2.4.4
System Integration Unit Lite (SIUL) ..............................................................................36
2.4.5
Flash memory .................................................................................................................36
2.4.6
SRAM .............................................................................................................................38
2.4.7
Memory Protection Unit (MPU) ....................................................................................38
2.4.8
Boot Assist Module (BAM) ...........................................................................................38
2.4.9
Enhanced Modular Input Output System (eMIOS) ........................................................39
2.4.10
Deserial Serial Peripheral Interface Module (DSPI) ......................................................40
2.4.11
Controller Area Network module (FlexCAN) ................................................................40
2.4.12
System clocks and clock generation ...............................................................................41
2.4.13
System timers .................................................................................................................42
2.4.14
System watchdog timer ..................................................................................................43
2.4.15
Inter-Integrated Circuit (I2C) module ............................................................................43
2.4.16
On-chip voltage regulator (VREG) ................................................................................43
2.4.17
Analog-to-Digital Converter (ADC) ..............................................................................44
2.4.18
Enhanced Direct Memory Access controller (eDMA) ...................................................45
2.4.19
Cross Trigger Unit (CTU) ..............................................................................................45
2.4.20
Serial communication interface module (LINFlex) .......................................................46
2.4.21
JTAG Controller (JTAGC) .............................................................................................47
Developer support ..........................................................................................................................47
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Chapter 3
Memory Map
Chapter 4
Signal description
4.1
4.2
Package pinouts ...............................................................................................................................53
Pin muxing ......................................................................................................................................55
Chapter 5
Microcontroller Boot
5.1
5.2
5.3
Boot mechanism ..............................................................................................................................75
5.1.1
Flash memory boot .........................................................................................................76
5.1.2
Serial boot mode .............................................................................................................78
5.1.3
Censorship ......................................................................................................................78
Boot Assist Module (BAM) ............................................................................................................83
5.2.1
BAM software flow ........................................................................................................83
5.2.2
LINFlex (RS232) boot ....................................................................................................91
5.2.3
FlexCAN boot ................................................................................................................92
System Status and Configuration Module (SSCM) ........................................................................94
5.3.1
Introduction ....................................................................................................................94
5.3.2
Features ...........................................................................................................................94
5.3.3
Modes of operation .........................................................................................................95
5.3.4
Memory map and register description ............................................................................95
Chapter 6
Clock Description
6.1
6.2
6.3
6.4
6.5
6.6
Clock architecture .........................................................................................................................105
Clock gating ..................................................................................................................................106
Fast external crystal oscillator (FXOSC) digital interface ............................................................107
6.3.1
Main features ................................................................................................................107
6.3.2
Functional description ..................................................................................................107
6.3.3
Register description ......................................................................................................108
Slow external crystal oscillator (SXOSC) digital interface ..........................................................109
6.4.1
Introduction ..................................................................................................................109
6.4.2
Main features ................................................................................................................109
6.4.3
Functional description ..................................................................................................109
6.4.4
Register description ......................................................................................................110
Slow internal RC oscillator (SIRC) digital interface .................................................................... 111
6.5.1
Introduction .................................................................................................................. 111
6.5.2
Functional description ..................................................................................................112
6.5.3
Register description ......................................................................................................112
Fast internal RC oscillator (FIRC) digital interface ......................................................................113
6.6.1
Introduction ..................................................................................................................113
6.6.2
Functional description ..................................................................................................113
6.6.3
Register description ......................................................................................................114
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6.7
6.8
Frequency-modulated phase-locked loop (FMPLL) .....................................................................115
6.7.1
Introduction ..................................................................................................................115
6.7.2
Overview ......................................................................................................................115
6.7.3
Features .........................................................................................................................115
6.7.4
Memory map ................................................................................................................116
6.7.5
Register description ......................................................................................................116
6.7.6
Functional description ..................................................................................................120
6.7.7
Recommendations ........................................................................................................122
Clock monitor unit (CMU) ............................................................................................................123
6.8.1
Introduction ..................................................................................................................123
6.8.2
Main features ................................................................................................................123
6.8.3
Block diagram ..............................................................................................................124
6.8.4
Functional description ..................................................................................................124
6.8.5
Memory map and register description ..........................................................................126
Chapter 7
Clock Generation Module (MC_CGM)
7.1
7.2
7.3
7.4
7.5
7.6
Overview .......................................................................................................................................131
Features .........................................................................................................................................132
Modes of operation ........................................................................................................................133
7.3.1
Normal and reset modes of operation ...........................................................................133
External signal description ............................................................................................................133
Memory map and register definition .............................................................................................133
7.5.1
Register descriptions ....................................................................................................137
7.5.2
Output Clock Division Select Register (CGM_OCDS_SC) ........................................138
7.5.3
System Clock Select Status Register (CGM_SC_SS) ..................................................139
Functional Description ..................................................................................................................142
7.6.1
System Clock Generation .............................................................................................142
7.6.2
Output Clock Multiplexing ...........................................................................................143
7.6.3
Output Clock Division Selection ..................................................................................144
Chapter 8
Mode Entry Module (MC_ME)
8.1
8.2
8.3
8.4
Overview .......................................................................................................................................145
8.1.1
Features .........................................................................................................................145
8.1.2
Modes of operation .......................................................................................................146
External signal description ............................................................................................................147
Memory map and register definition .............................................................................................147
8.3.1
Register descriptions ....................................................................................................150
Functional description ...................................................................................................................163
8.4.1
Mode transition request ................................................................................................163
8.4.2
Modes details ................................................................................................................164
8.4.3
Mode transition process ................................................................................................167
8.4.4
Protection of mode configuration registers ..................................................................175
8.4.5
Mode transition interrupts ............................................................................................175
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8.4.6
Application example .....................................................................................................177
Chapter 9
Reset Generation Module (MC_RGM)
9.1
9.2
9.3
9.4
Introduction ...................................................................................................................................179
9.1.1
Overview ......................................................................................................................179
9.1.2
Features .........................................................................................................................180
9.1.3
Modes of operation .......................................................................................................181
External signal description ............................................................................................................181
Memory map and register definition .............................................................................................182
9.3.1
Register descriptions ....................................................................................................183
Functional description ...................................................................................................................188
9.4.1
Reset state machine ......................................................................................................188
9.4.2
Destructive resets ..........................................................................................................191
9.4.3
External reset ................................................................................................................192
9.4.4
Functional resets ...........................................................................................................192
9.4.5
Alternate event generation ............................................................................................192
9.4.6
Boot mode capturing ....................................................................................................193
Chapter 10
Power Control Unit (MC_PCU)
10.1 Introduction ...................................................................................................................................195
10.1.1
Overview ......................................................................................................................195
10.1.2
Features .........................................................................................................................196
10.1.3
Modes of operation .......................................................................................................196
10.2 External signal description ............................................................................................................197
10.3 Memory map and register definition .............................................................................................197
10.3.1
Register descriptions ....................................................................................................199
10.4 Functional description ...................................................................................................................202
10.4.1
General .........................................................................................................................202
10.4.2
Reset / Power-On Reset ................................................................................................203
10.4.3
MC_PCU configuration ................................................................................................203
10.4.4
Mode transitions ...........................................................................................................203
10.5 Initialization information ...............................................................................................................205
10.6 Application information ................................................................................................................206
10.6.1
STANDBY Mode Considerations ................................................................................206
Chapter 11
Voltage Regulators and Power Supplies
11.1 Voltage regulators ..........................................................................................................................207
11.1.1
High power regulator (HPREG) ...................................................................................207
11.1.2
Low power regulator (LPREG) ....................................................................................207
11.1.3
Ultra low power regulator (ULPREG) .........................................................................208
11.1.4
LVDs and POR .............................................................................................................208
11.1.5
VREG digital interface .................................................................................................208
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11.1.6
Register description ......................................................................................................209
11.2 Power supply strategy ...................................................................................................................209
11.3 Power domain organization ...........................................................................................................210
Chapter 12
Wakeup Unit (WKPU)
12.1
12.2
12.3
12.4
Overview .......................................................................................................................................213
Features .........................................................................................................................................215
External signal description ............................................................................................................216
Memory map and register description ...........................................................................................216
12.4.1
Memory map ................................................................................................................216
12.4.2
NMI Status Flag Register (NSR) ..................................................................................217
12.4.3
NMI Configuration Register (NCR) .............................................................................218
12.4.4
Wakeup/Interrupt Status Flag Register (WISR) ...........................................................219
12.4.5
Interrupt Request Enable Register (IRER) ...................................................................219
12.4.6
Wakeup Request Enable Register (WRER) ..................................................................220
12.4.7
Wakeup/Interrupt Rising-Edge Event Enable Register (WIREER) .............................220
12.4.8
Wakeup/Interrupt Falling-Edge Event Enable Register (WIFEER) .............................221
12.4.9
Wakeup/Interrupt Filter Enable Register (WIFER) ......................................................221
12.4.10 Wakeup/Interrupt Pullup Enable Register (WIPUER) .................................................222
12.5 Functional description ...................................................................................................................222
12.5.1
General .........................................................................................................................222
12.5.2
Non-maskable interrupts ..............................................................................................223
12.5.3
External wakeups/interrupts .........................................................................................224
12.5.4
On-chip wakeups ..........................................................................................................226
Chapter 13
Real Time Clock / Autonomous Periodic Interrupt (RTC/API)
13.1
13.2
13.3
13.4
Overview .......................................................................................................................................227
Features .........................................................................................................................................227
Device-specific information ..........................................................................................................229
Modes of operation ........................................................................................................................229
13.4.1
Functional mode ...........................................................................................................229
13.4.2
Debug mode ..................................................................................................................230
13.5 Register descriptions .....................................................................................................................230
13.5.1
RTC Supervisor Control Register (RTCSUPV) ...........................................................230
13.5.2
RTC Control Register (RTCC) .....................................................................................231
13.5.3
RTC Status Register (RTCS) ........................................................................................233
13.5.4
RTC Counter Register (RTCCNT) ...............................................................................234
13.6 RTC functional description ...........................................................................................................234
13.7 API functional description ............................................................................................................235
Chapter 14
CAN Sampler
14.1 Introduction ...................................................................................................................................237
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14.2 Main features .................................................................................................................................237
14.3 Memory map and register description ...........................................................................................238
14.3.1
Control Register (CR) ...................................................................................................238
14.3.2
CAN Sampler Sample Registers 0–11 ..........................................................................239
14.4 Functional description ...................................................................................................................239
14.4.1
Enabling/disabling the CAN sampler ...........................................................................240
14.4.2
Selecting the Rx port ....................................................................................................240
14.4.3
Baud rate generation .....................................................................................................241
Chapter 15
e200z0h Core
15.1
15.2
15.3
15.4
Overview .......................................................................................................................................245
Microarchitecture summary ..........................................................................................................245
Block diagram ...............................................................................................................................247
Features .........................................................................................................................................247
15.4.1
Instruction unit features ................................................................................................248
15.4.2
Integer unit features ......................................................................................................248
15.4.3
Load/Store unit features ...............................................................................................249
15.4.4
e200z0h system bus features ........................................................................................249
15.5 Core registers and programmer’s model .......................................................................................249
Chapter 16
Enhanced Direct Memory Access (eDMA)
16.1 Device-specific features ................................................................................................................253
16.2 Introduction ...................................................................................................................................253
16.2.1
Features .........................................................................................................................254
16.3 Memory map and register definition .............................................................................................255
16.3.1
Memory map ................................................................................................................255
16.3.2
Register descriptions ....................................................................................................257
16.4 Functional description ...................................................................................................................278
16.4.1
eDMA basic data flow ..................................................................................................280
16.5 Initialization / application information ..........................................................................................283
16.5.1
eDMA initialization ......................................................................................................283
16.5.2
DMA programming errors ............................................................................................285
16.5.3
DMA request assignments ............................................................................................286
16.5.4
DMA arbitration mode considerations .........................................................................286
16.5.5
DMA transfer ................................................................................................................287
16.5.6
TCD status ....................................................................................................................290
16.5.7
Channel linking ............................................................................................................291
16.5.8
Dynamic programming .................................................................................................292
Chapter 17
eDMA Channel Multiplexer (DMA_MUX)
17.1 Introduction ...................................................................................................................................295
17.2 Features .........................................................................................................................................295
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17.3 Modes of operation ........................................................................................................................296
17.4 External signal description ............................................................................................................296
17.5 Memory map and register definition .............................................................................................296
17.5.1
Channel configuration registers (CHCONFIGn) ..........................................................297
17.6 DMA_MUX inputs .......................................................................................................................298
17.6.1
DMA_MUX peripheral sources ...................................................................................298
17.6.2
DMA_MUX periodic trigger inputs .............................................................................300
17.7 Functional description ...................................................................................................................300
17.7.1
eDMA channels with periodic triggering capability ....................................................300
17.7.2
eDMA channels with no triggering capability .............................................................302
17.8 Initialization/Application information ...........................................................................................303
17.8.1
Reset .............................................................................................................................303
17.8.2
Enabling and configuring sources ................................................................................303
Chapter 18
Interrupt Controller (INTC)
18.1
18.2
18.3
18.4
Introduction ...................................................................................................................................307
Features .........................................................................................................................................307
Block diagram ...............................................................................................................................309
Modes of operation ........................................................................................................................309
18.4.1
Normal mode ................................................................................................................309
18.5 Memory map and register description ...........................................................................................311
18.5.1
Module memory map ...................................................................................................311
18.5.2
Register description ......................................................................................................311
18.6 Functional description ...................................................................................................................319
18.6.1
Interrupt request sources ...............................................................................................327
18.6.2
Priority management ....................................................................................................328
18.6.3
Handshaking with processor .........................................................................................330
18.7 Initialization/application information ............................................................................................332
18.7.1
Initialization flow .........................................................................................................332
18.7.2
Interrupt exception handler ...........................................................................................332
18.7.3
ISR, RTOS, and task hierarchy .....................................................................................334
18.7.4
Order of execution ........................................................................................................335
18.7.5
Priority ceiling protocol ................................................................................................336
18.7.6
Selecting priorities according to request rates and deadlines .......................................336
18.7.7
Software configurable interrupt requests ......................................................................337
18.7.8
Lowering priority within an ISR ..................................................................................338
18.7.9
Negating an interrupt request outside of its ISR ..........................................................338
18.7.10 Examining LIFO contents ............................................................................................339
Chapter 19
Crossbar Switch (XBAR)
19.1 Introduction ...................................................................................................................................341
19.2 Block diagram ...............................................................................................................................341
19.3 Overview .......................................................................................................................................342
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19.4 Features .........................................................................................................................................342
19.5 Modes of operation ........................................................................................................................342
19.5.1
Normal mode ................................................................................................................342
19.5.2
Debug mode ..................................................................................................................342
19.6 Functional description ...................................................................................................................342
19.6.1
Overview ......................................................................................................................342
19.6.2
General operation .........................................................................................................343
19.6.3
Master ports ..................................................................................................................343
19.6.4
Slave ports ....................................................................................................................344
19.6.5
Priority assignment .......................................................................................................344
19.6.6
Arbitration ....................................................................................................................344
Chapter 20
System Integration Unit Lite (SIUL)
20.1
20.2
20.3
20.4
Introduction ...................................................................................................................................347
Overview .......................................................................................................................................347
Features .........................................................................................................................................349
External signal description ............................................................................................................349
20.4.1
Detailed signal descriptions ..........................................................................................350
20.5 Memory map and register description ...........................................................................................351
20.5.1
SIUL memory map .......................................................................................................351
20.5.2
Register protection ........................................................................................................352
20.5.3
Register descriptions ....................................................................................................353
20.6 Functional description ...................................................................................................................372
20.6.1
Pad control ....................................................................................................................372
20.6.2
General purpose input and output pads (GPIO) ...........................................................372
20.6.3
External interrupts ........................................................................................................373
20.7 Pin muxing ....................................................................................................................................374
Chapter 21
Memory Protection Unit (MPU)
21.1
21.2
21.3
21.4
21.5
Introduction ...................................................................................................................................375
Features .........................................................................................................................................376
Modes of operation ........................................................................................................................377
External signal description ............................................................................................................377
Memory map and register description ...........................................................................................377
21.5.1
Memory map ................................................................................................................378
21.5.2
Register description ......................................................................................................379
21.6 Functional description ...................................................................................................................390
21.6.1
Access evaluation macro ..............................................................................................390
21.6.2
Putting it all together and AHB error terminations ......................................................391
21.7 Initialization information ...............................................................................................................392
21.8 Application information ................................................................................................................392
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Chapter 22
Inter-Integrated Circuit Bus Controller Module (I2C)
22.1 Introduction ...................................................................................................................................397
22.1.1
Overview ......................................................................................................................397
22.1.2
Features .........................................................................................................................397
22.1.3
Block diagram ..............................................................................................................398
22.2 External signal description ............................................................................................................398
22.2.1
SCL ...............................................................................................................................398
22.2.2
SDA ..............................................................................................................................398
22.3 Memory map and register description ...........................................................................................398
22.3.1
Module memory map ...................................................................................................398
22.3.2
I2C Bus Address Register (IBAD) ...............................................................................399
22.3.3
I2C Bus Frequency Divider Register (IBFD) ...............................................................400
22.3.4
I2C Bus Control Register (IBCR) .................................................................................406
22.3.5
I2C Bus Status Register (IBSR) ....................................................................................407
22.3.6
I2C Bus Data I/O Register (IBDR) ...............................................................................408
22.3.7
I2C Bus Interrupt Configuration Register (IBIC) .........................................................409
22.4 DMA Interface ..............................................................................................................................409
22.5 Functional description ...................................................................................................................411
22.5.1
I-Bus protocol ...............................................................................................................411
22.5.2
Interrupts .......................................................................................................................414
22.6 Initialization/application information ............................................................................................415
22.6.1
I2C programming examples ..........................................................................................415
Chapter 23
LIN Controller (LINFlex)
23.1 Introduction ...................................................................................................................................421
23.2 Main features .................................................................................................................................421
23.2.1
LIN mode features ........................................................................................................421
23.2.2
UART mode features ....................................................................................................421
23.2.3
Features common to LIN and UART ...........................................................................421
23.3 General description .......................................................................................................................422
23.4 Fractional baud rate generation .....................................................................................................423
23.5 Operating modes ...........................................................................................................................425
23.5.1
Initialization mode ........................................................................................................426
23.5.2
Normal mode ................................................................................................................426
23.5.3
Low power mode (Sleep) .............................................................................................426
23.6 Test modes .....................................................................................................................................426
23.6.1
Loop Back mode ...........................................................................................................426
23.6.2
Self Test mode ..............................................................................................................427
23.7 Memory map and registers description .........................................................................................427
23.7.1
Memory map ................................................................................................................427
23.8 Functional description ...................................................................................................................453
23.8.1
UART mode ..................................................................................................................453
23.8.2
LIN mode ......................................................................................................................455
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23.8.3
23.8.4
8-bit timeout counter ....................................................................................................463
Interrupts .......................................................................................................................465
Chapter 24
LIN Controller (LINFlexD)
24.1 Introduction ...................................................................................................................................467
24.2 Main features .................................................................................................................................467
24.2.1
LIN mode features ........................................................................................................468
24.2.2
UART mode features ....................................................................................................468
24.3 The LIN protocol ...........................................................................................................................469
24.3.1
Dominant and recessive logic levels ............................................................................469
24.3.2
LIN frames ....................................................................................................................469
24.3.3
LIN header ....................................................................................................................470
24.3.4
Response .......................................................................................................................471
24.4 LINFlexD and software intervention ............................................................................................472
24.5 Summary of operating modes .......................................................................................................472
24.6 Controller-level operating modes ..................................................................................................473
24.6.1
Initialization mode ........................................................................................................473
24.6.2
Normal mode ................................................................................................................474
24.6.3
Sleep (low-power) mode ..............................................................................................474
24.7 LIN modes .....................................................................................................................................474
24.7.1
Master mode .................................................................................................................474
24.7.2
Slave mode ...................................................................................................................476
24.7.3
Slave mode with identifier filtering ..............................................................................478
24.7.4
Slave mode with automatic resynchronization .............................................................481
24.8 Test modes .....................................................................................................................................482
24.8.1
Loop Back mode ...........................................................................................................482
24.8.2
Self Test mode ..............................................................................................................483
24.9 UART mode ..................................................................................................................................483
24.9.1
Data frame structure .....................................................................................................483
24.9.2
Buffer ............................................................................................................................485
24.9.3
UART transmitter .........................................................................................................485
24.9.4
UART receiver ..............................................................................................................486
24.10 Memory map and register description ...........................................................................................488
24.10.1 LIN control register 1 (LINCR1) .................................................................................488
24.10.2 LIN interrupt enable register (LINIER) .......................................................................491
24.10.3 LIN status register (LINSR) .........................................................................................493
24.10.4 LIN error status register (LINESR) ..............................................................................496
24.10.5 UART mode control register (UARTCR) .....................................................................497
24.10.6 UART mode status register (UARTSR) .......................................................................500
24.10.7 LIN timeout control status register (LINTCSR) ..........................................................502
24.10.8 LIN output compare register (LINOCR) ......................................................................503
24.10.9 LIN timeout control register (LINTOCR) ....................................................................504
24.10.10 LIN fractional baud rate register (LINFBRR) ..............................................................505
24.10.11 LIN integer baud rate register (LINIBRR) ...................................................................505
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24.10.12 LIN checksum field register (LINCFR) .......................................................................506
24.10.13 LIN control register 2 (LINCR2) .................................................................................507
24.10.14 Buffer identifier register (BIDR) ..................................................................................508
24.10.15 Buffer data register least significant (BDRL) ..............................................................509
24.10.16 Buffer data register most significant (BDRM) .............................................................510
24.10.17 Identifier filter enable register (IFER) ..........................................................................511
24.10.18 Identifier filter match index (IFMI) ..............................................................................512
24.10.19 Identifier filter mode register (IFMR) ..........................................................................513
24.10.20 Identifier filter control registers (IFCR0–IFCR15) ......................................................513
24.10.21 Global control register (GCR) ......................................................................................514
24.10.22 UART preset timeout register (UARTPTO) .................................................................516
24.10.23 UART current timeout register (UARTCTO) ...............................................................516
24.10.24 DMA Tx enable register (DMATXE) ...........................................................................517
24.10.25 DMA Rx enable register (DMARXE) ..........................................................................518
24.11 DMA interface ...............................................................................................................................518
24.11.1 Master node, TX mode .................................................................................................519
24.11.2 Master node, RX mode .................................................................................................522
24.11.3 Slave node, TX mode ...................................................................................................524
24.11.4 Slave node, RX mode ...................................................................................................527
24.11.5 UART node, TX mode .................................................................................................530
24.11.6 UART node, RX mode .................................................................................................532
24.11.7 Use cases and limitations ..............................................................................................535
24.12 Functional description ...................................................................................................................536
24.12.1 8-bit timeout counter ....................................................................................................536
24.12.2 Interrupts .......................................................................................................................537
24.12.3 Fractional baud rate generation ....................................................................................539
24.13 Programming considerations .........................................................................................................540
24.13.1 Master node ..................................................................................................................540
24.13.2 Slave node ....................................................................................................................541
24.13.3 Extended frames ...........................................................................................................545
24.13.4 Timeout .........................................................................................................................545
24.13.5 UART mode ..................................................................................................................546
Chapter 25
FlexCAN
25.1 Information specific to this device ................................................................................................547
25.1.1
Device-specific features ...............................................................................................547
25.2 Introduction ...................................................................................................................................547
25.2.1
Overview ......................................................................................................................548
25.2.2
FlexCAN module features ............................................................................................549
25.2.3
Modes of operation .......................................................................................................549
25.3 External signal description ............................................................................................................550
25.3.1
Overview ......................................................................................................................550
25.3.2
Signal descriptions ........................................................................................................551
25.4 Memory map/register definition ....................................................................................................551
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25.4.1
FlexCAN memory mapping .........................................................................................551
25.4.2
Message Buffer Structure .............................................................................................553
25.4.3
Rx FIFO structure .........................................................................................................556
25.4.4
Register descriptions ....................................................................................................557
25.5 Functional description ...................................................................................................................576
25.5.1
Overview ......................................................................................................................576
25.5.2
Local priority transmission ...........................................................................................577
25.5.3
Transmit process ...........................................................................................................577
25.5.4
Arbitration process .......................................................................................................578
25.5.5
Receive process ............................................................................................................579
25.5.6
Matching process ..........................................................................................................580
25.5.7
Data coherence .............................................................................................................581
25.5.8
Rx FIFO ........................................................................................................................584
25.5.9
CAN protocol related features ......................................................................................584
25.5.10 Modes of operation details ...........................................................................................588
25.5.11 Interrupts .......................................................................................................................589
25.5.12 Bus interface .................................................................................................................590
25.6 Initialization/application information ............................................................................................591
25.6.1
FlexCAN initialization sequence ..................................................................................591
25.6.2
FlexCAN addressing and RAM size configurations ....................................................592
Chapter 26
Deserial Serial Peripheral Interface (DSPI)
26.1 Introduction ...................................................................................................................................593
26.2 Features .........................................................................................................................................594
26.3 Modes of operation ........................................................................................................................595
26.3.1
Master mode .................................................................................................................595
26.3.2
Slave mode ...................................................................................................................595
26.3.3
Module Disable mode ...................................................................................................595
26.3.4
Debug mode ..................................................................................................................596
26.4 External signal description ............................................................................................................596
26.4.1
Signal overview ............................................................................................................596
26.4.2
Signal names and descriptions ......................................................................................596
26.5 Memory map and register description ...........................................................................................597
26.5.1
Memory map ................................................................................................................597
26.5.2
DSPI Module Configuration Register (DSPIx_MCR) .................................................598
26.5.3
DSPI Transfer Count Register (DSPIx_TCR) ..............................................................601
26.5.4
DSPI Clock and Transfer Attributes Registers 0–5 (DSPIx_CTARn) .........................602
26.5.5
DSPI Status Register (DSPIx_SR) ...............................................................................610
26.5.6
DSPI DMA / Interrupt Request Select and Enable Register (DSPIx_RSER) ..............612
26.5.7
DSPI PUSH TX FIFO Register (DSPIx_PUSHR) .......................................................614
26.5.8
DSPI POP RX FIFO Register (DSPIx_POPR) ............................................................616
26.5.9
DSPI Transmit FIFO Registers 0–3 (DSPIx_TXFRn) .................................................617
26.6 Functional description ...................................................................................................................618
26.6.1
Modes of operation .......................................................................................................619
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26.6.2
Start and stop of DSPI transfers ...................................................................................620
26.6.3
Serial peripheral interface (SPI) configuration .............................................................621
26.6.4
DSPI baud rate and clock delay generation ..................................................................624
26.6.5
Transfer formats ...........................................................................................................627
26.6.6
Continuous serial communications clock .....................................................................634
26.6.7
Interrupt/DMA requests ................................................................................................635
26.6.8
Power saving features ...................................................................................................637
26.7 Initialization and application information .....................................................................................638
26.7.1
How to change queues ..................................................................................................638
26.7.2
Baud rate settings .........................................................................................................638
26.7.3
Delay settings ...............................................................................................................640
26.7.4
Calculation of FIFO pointer addresses .........................................................................640
Chapter 27
Timers
27.1 Introduction ...................................................................................................................................645
27.2 Technical overview ........................................................................................................................645
27.2.1
Overview of the STM ...................................................................................................647
27.2.2
Overview of the eMIOS ...............................................................................................647
27.2.3
Overview of the PIT .....................................................................................................649
27.3 System Timer Module (STM) .......................................................................................................649
27.3.1
Introduction ..................................................................................................................649
27.3.2
External signal description ...........................................................................................650
27.3.3
Memory map and register definition ............................................................................650
27.3.4
Functional description ..................................................................................................654
27.4 Enhanced Modular IO Subsystem (eMIOS) .................................................................................655
27.4.1
Introduction ..................................................................................................................655
27.4.2
External signal description ...........................................................................................658
27.4.3
Memory map and register description ..........................................................................658
27.4.4
Functional description ..................................................................................................670
27.4.5
Initialization/Application information ..........................................................................700
27.5 Periodic Interrupt Timer (PIT) ......................................................................................................704
27.5.1
Introduction ..................................................................................................................704
27.5.2
Features .........................................................................................................................704
27.5.3
Signal description .........................................................................................................705
27.5.4
Memory map and register description ..........................................................................705
27.5.5
Functional description ..................................................................................................709
27.5.6
Initialization and application information ....................................................................710
Chapter 28
Analog-to-Digital Converter (ADC)
28.1 Overview .......................................................................................................................................715
28.1.1
Device-specific features ...............................................................................................715
28.1.2
Device-specific implementation ...................................................................................716
28.2 Introduction ...................................................................................................................................717
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15
28.3 Functional description ...................................................................................................................717
28.3.1
Analog channel conversion ..........................................................................................717
28.3.2
Analog clock generator and conversion timings ..........................................................720
28.3.3
ADC sampling and conversion timing .........................................................................720
28.3.4
ADC CTU (Cross Triggering Unit) ..............................................................................725
28.3.5
Presampling ..................................................................................................................726
28.3.6
Programmable analog watchdog ..................................................................................727
28.3.7
DMA functionality .......................................................................................................728
28.3.8
Interrupts .......................................................................................................................728
28.3.9
External decode signals delay ......................................................................................729
28.3.10 Power-down mode ........................................................................................................729
28.3.11 Auto-clock-off mode ....................................................................................................729
28.4 Register descriptions .....................................................................................................................730
28.4.1
Introduction ..................................................................................................................730
28.4.2
Control logic registers ..................................................................................................737
28.4.3
Interrupt registers ..........................................................................................................740
28.4.4
DMA registers ..............................................................................................................748
28.4.5
Threshold registers .......................................................................................................752
28.4.6
Presampling registers ....................................................................................................753
28.4.7
Conversion timing registers CTR[0..2] ........................................................................756
28.4.8
Mask registers ...............................................................................................................757
28.4.9
Delay registers ..............................................................................................................761
28.4.10 Data registers ................................................................................................................763
28.4.11 Watchdog register .........................................................................................................765
Chapter 29
Cross Triggering Unit (CTU)
29.1
29.2
29.3
29.4
Introduction ...................................................................................................................................779
Main features .................................................................................................................................779
Block diagram ...............................................................................................................................779
Memory map and register descriptions .........................................................................................779
29.4.1
Event Configuration Registers (CTU_EVTCFGRx) (x = 0...63) .................................780
29.5 Functional description ...................................................................................................................781
29.5.1
Channel value ...............................................................................................................783
Chapter 30
Flash Memory
30.1
30.2
30.3
30.4
Introduction ...................................................................................................................................789
Main features .................................................................................................................................790
Block diagram ...............................................................................................................................790
Functional description ...................................................................................................................791
30.4.1
Module structure ...........................................................................................................791
30.4.2
Flash memory module sectorization .............................................................................792
30.4.3
TestFlash block .............................................................................................................793
30.4.4
Shadow sector ...............................................................................................................795
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30.5
30.6
30.7
30.8
30.4.5
User mode operation .....................................................................................................795
30.4.6
Reset .............................................................................................................................796
30.4.7
Power-down mode ........................................................................................................797
30.4.8
Low power mode ..........................................................................................................797
Register description .......................................................................................................................798
30.5.1
CFlash register description ...........................................................................................799
30.5.2
DFlash register description ...........................................................................................834
Programming considerations .........................................................................................................857
30.6.1
Modify operation ..........................................................................................................857
30.6.2
Double word program ...................................................................................................858
30.6.3
Sector erase ...................................................................................................................860
Platform flash memory controller .................................................................................................868
30.7.1
Introduction ..................................................................................................................868
30.7.2
Memory map and register description ..........................................................................871
Functional description ...................................................................................................................880
30.8.1
Access protections ........................................................................................................880
30.8.2
Read cycles – Buffer miss ............................................................................................880
30.8.3
Read cycles – Buffer hit ...............................................................................................881
30.8.4
Write cycles ..................................................................................................................881
30.8.5
Error termination ..........................................................................................................881
30.8.6
Access pipelining ..........................................................................................................881
30.8.7
Flash error response operation ......................................................................................882
30.8.8
Bank0 page read buffers and prefetch operation ..........................................................882
30.8.9
Bank1 Temporary Holding Register .............................................................................884
30.8.10 Read-while-write functionality .....................................................................................885
30.8.11 Wait-state emulation .....................................................................................................886
Chapter 31
Static RAM (SRAM)
31.1
31.2
31.3
31.4
Introduction ...................................................................................................................................889
Low power configuration ..............................................................................................................889
Register memory map ...................................................................................................................889
SRAM ECC mechanism ................................................................................................................890
31.4.1
Access timing ...............................................................................................................890
31.4.2
Reset effects on SRAM accesses ..................................................................................891
31.5 Functional description ...................................................................................................................891
31.6 Initialization and application information .....................................................................................891
Chapter 32
Register Protection
32.1
32.2
32.3
32.4
32.5
Introduction ...................................................................................................................................895
Features .........................................................................................................................................895
Modes of operation ........................................................................................................................896
External signal description ............................................................................................................896
Memory map and register description ...........................................................................................896
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17
32.5.1
Memory map ................................................................................................................897
32.5.2
Register description ......................................................................................................898
32.6 Functional description ...................................................................................................................900
32.6.1
General .........................................................................................................................900
32.6.2
Change lock settings .....................................................................................................900
32.6.3
Access errors ................................................................................................................904
32.7 Reset ..............................................................................................................................................904
32.8 Protected registers .........................................................................................................................904
Chapter 33
Software Watchdog Timer (SWT)
33.1
33.2
33.3
33.4
33.5
Overview .......................................................................................................................................913
Features .........................................................................................................................................913
Modes of operation ........................................................................................................................913
External signal description ............................................................................................................914
Memory map and register description ...........................................................................................914
33.5.1
Memory map ................................................................................................................914
33.5.2
Register description ......................................................................................................915
33.6 Functional description ...................................................................................................................919
Chapter 34
Error Correction Status Module (ECSM)
34.1
34.2
34.3
34.4
Introduction ...................................................................................................................................923
Overview .......................................................................................................................................923
Features .........................................................................................................................................923
Memory map and register description ...........................................................................................923
34.4.1
Memory map ................................................................................................................923
34.4.2
Register description ......................................................................................................924
34.4.3
Register protection ........................................................................................................942
Chapter 35
IEEE 1149.1 Test Access Port Controller (JTAGC)
35.1
35.2
35.3
35.4
35.5
Introduction ...................................................................................................................................945
Block diagram ...............................................................................................................................945
Overview .......................................................................................................................................945
Features .........................................................................................................................................946
Modes of operation ........................................................................................................................946
35.5.1
Reset .............................................................................................................................946
35.5.2
IEEE 1149.1-2001 defined test modes .........................................................................946
35.6 External signal description ............................................................................................................947
35.7 Memory map and register description ...........................................................................................947
35.7.1
Instruction register ........................................................................................................947
35.7.2
Bypass register ..............................................................................................................948
35.7.3
Device identification register .......................................................................................948
35.7.4
Boundary scan register .................................................................................................949
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35.8 Functional description ...................................................................................................................949
35.8.1
JTAGC reset configuration ...........................................................................................949
35.8.2
IEEE 1149.1-2001 (JTAG) Test Access Port ................................................................949
35.8.3
TAP controller state machine .......................................................................................949
35.8.4
JTAGC instructions ......................................................................................................951
35.8.5
Boundary scan ..............................................................................................................953
35.9 e200z0 OnCE controller ................................................................................................................953
35.9.1
e200z0 OnCE controller block diagram .......................................................................953
35.9.2
e200z0 OnCE controller functional description ...........................................................954
35.9.3
e200z0 OnCE controller register description ...............................................................954
35.10 Initialization/application information ............................................................................................956
Appendix A
Revision History
A.1
Changes between revisions 1 and 2 ............................................................................................957
MPC5606BK Microcontroller Reference Manual, Rev. 2
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19
MPC5606BK Microcontroller Reference Manual, Rev. 2
20
Freescale Semiconductor
Chapter 1 Preface
Chapter 1
Preface
1.1
Overview
The primary objective of this document is to define the functionality of the MPC5606BK microcontroller
for use by software and hardware developers. The MPC5606BK is built on Power Architecture®
technology and integrates technologies that are important for today’s automotive vehicle body
applications.
The information in this book is subject to change without notice, as described in the disclaimers on the title
page. As with any technical documentation, it is the reader’s responsibility to be sure he or she is using the
most recent version of the documentation.
To locate any published errata or updates for this document, visit the Freescale Web site at freescale.com.
1.2
Audience
This manual is intended for system software and hardware developers and applications programmers who
want to develop products with the MPC5606BK device. It is assumed that the reader understands operating
systems, microprocessor system design, basic principles of software and hardware, and basic details of the
Power Architecture.
1.3
Guide to this reference manual
Table 1-1. Guide to this reference manual
Chapter
#
Description
Functional group
Title
2
Introduction
General overview, family description, feature list, and
information on how to use the reference manual in
conjunction with other available documents.
Introductory
material
3
Memory Map
Memory map of all peripherals and memory.
Memory map
4
Signal description
Pinout diagrams and descriptions of all pads.
Signals
5
Microcontroller Boot
Boot
• Boot mechanism
• Describes what configuration is required by the
user and what processes are involved when the
microcontroller boots from flash memory or serial
boot modes.
• Describes censorship.
• Boot Assist Module (BAM)
Features of BAM code and when it's used.
• System Status and
Configuration Module
(SSCM)
Reports information about current state and
configuration of the microcontroller.
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21
Chapter 1 Preface
Table 1-1. Guide to this reference manual (continued)
Chapter
#
Title
6
Clock Description
Description
Functional group
• Covers configuration of all of the clock sources in
the system.
• Describes the Clock Monitor Unit (CMU).
Clocks and power
(includes operating
mode configuration
Determines how the clock sources are used (including and how to wake up
clock dividers) to generate the reference clocks for all
from low power
of the modules and peripherals.
mode)
7
Clock Generation Module
(MC_CGM)
8
Mode Entry Module (MC_ME)
Determines the clock source, memory, power, and
peripherals that are available in each operating mode.
9
Reset Generation Module
(MC_RGM)
Manages the process of entering and exiting reset,
allows reset sources to be configured (including
LVDs), and provides status reporting.
10
Power Control Unit (MC_PCU) Controls the power to different power domains within
the microcontroller (allowing SRAM to be selectively
powered in STANDBY mode).
11
Voltage Regulators and Power
Supplies
Information on voltage regulator implementation.
Includes enable bit for 5 V LVD (see also MC_RGM).
12
Wakeup Unit (WKPU)
Always-active analog block. Details configuration of
two internal (API/RTC) and 27 external (pin) low
power mode wakeup sources.
13
Real Time Clock / Autonomous Details configuration and operation of timers that are
Periodic Interrupt (RTC/API)
predominately used for system wakeup.
14
CAN Sampler
Details on how to configure the CAN sampler, which is
used to capture the identifier frame of a CAN message
when the microcontroller is in low power mode.
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Chapter 1 Preface
Table 1-1. Guide to this reference manual (continued)
Chapter
#
Description
Functional group
Core platform
modules
Title
15
e200z0h Core
Overview on cores. For more details consult the core
reference manuals available on www.freescale.com.
16
Enhanced Direct Memory
Access (eDMA)
Operation and configuration information on the
32-channel direct memory access that can be used to
transfer data between any memory mapped locations.
Certain peripherals have eDMA triggers that can be
used to feed configuration data to, or read results from
the peripherals.
17
eDMA Channel Multiplexer
(DMA_MUX)
Operation and configuration information for the eDMA
multiplexer, which takes the possible eDMA sources
(triggers from the DSPI, eMIOS, I2C, ADC, and
LINFlexD) and multiplexes them onto the eDMA
channels.
18
Interrupt Controller (INTC)
Provides the configuration and control of all of the
external interrupts (non-core) that are then routed to
the IVOR4 core interrupt vector.
19
Crossbar Switch (XBAR)
Describes the connections of the XBAR masters and
slaves on this microcontroller.
21
Memory Protection Unit (MPU) The MPU sits on the slave side of the XBAR and
allows highly configurable control over all master
accesses to the memory.
20
System Integration Unit Lite
(SIUL)
How to configure the pins or ports for input or output
functions including external interrupts.
Ports
22
Inter-Integrated Circuit Bus
Controller Module (I2C)
Communication
modules
23
LIN Controller (LINFlex)
These chapters describe the configuration and
operation of the various communication modules.
Some of these modules support DMA requests to fill /
empty buffer queues to minimize CPU overhead.
24
LIN Controller (LINFlexD)
25
FlexCAN
26
Deserial Serial Peripheral
Interface (DSPI)
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Chapter 1 Preface
Table 1-1. Guide to this reference manual (continued)
Chapter
Description
#
27
Functional group
Title
Timers
Timer modules
• Technical overview
Gives an overview of the available system timer
modules showing links to other modules as well as
tables detailing the external pins associated with
eMIOS timer channels.
• System Timer Module
(STM)
A simple 32-bit free running counter with 4 compare
channels with interrupt on match. It can be read at any
time; this is very useful for measuring execution times.
• Enhanced Modular IO
Subsystem (eMIOS)
Highly configurable timer module(s) supporting PWM,
output compare, and input capture features. Includes
interrupt and eDMA support.
• Periodic Interrupt Timer
(PIT)
Set of 32-bit countdown timers that provide periodic
events (which can trigger an interrupt) with automatic
reload.
28
Analog-to-Digital Converter
(ADC)
Details the configuration and operation of the ADC
modules as well as detailing the channels that are
shared between the 10-bit and 12-bit ADC. The ADC
is tightly linked to the INTC, eDMA, PIT, and CTU.
When used in conjunction with these other modules,
the CPU overhead for an ADC conversion is
significantly reduced.
29
Cross Triggering Unit (CTU)
The CTU allows an ADC conversion to be
automatically triggered based on an eMIOS event (like
a PWM output going high) or a PIT_RTI event with no
CPU intervention.
30
Flash Memory
Details the code and data flash memory structure
(with ECC), block sizes and the flash memory port
configuration, including wait states, line buffer
configuration, and pre-fetch control.
31
Static RAM (SRAM)
Details the structure of the SRAM (with ECC). There
are no user configurable registers associated with the
SRAM.
ADC system
Memory
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Chapter 1 Preface
Table 1-1. Guide to this reference manual (continued)
Chapter
#
1.4
Description
Functional group
Integrity
Title
32
Register Protection
Certain registers in each peripheral can be protected
from further writes using the register protection
mechanism detailed in this section. Registers can
either be configured to be unlocked via a soft lock bit
or locked unit the next reset.
33
Software Watchdog Timer
(SWT)
The SWT offers a selection of configurable modes that
can be used to monitor the operation of the
microcontroller and /or reset the device or trigger an
interrupt if the SWT is not correctly serviced. The SWT
is enabled out of reset.
34
Error Correction Status Module Provides information about the last reset, general
(ECSM)
device information, system fault information and
detailed ECC error information.
35
IEEE 1149.1 Test Access Port
Controller (JTAGC)
Used for boundary scan as well as device debug.
Debug
Register description conventions
The register information for MPC5606BK is presented in:
• Memory maps containing:
— An offset from the module’s base address
— The name and acronym/abbreviation of each register
— The page number on which each register is described
• Register figures
• Field-description tables
• Associated text
The register figures show the field structure using the conventions in Figure 1-1.
R
0
R FIELD1
1
FIELD2
R
W
W
W
Reserved bits
R
Read-only fields
0
W FIELD1
0
Read/write fields
0
R
FIELD
FIELD2
W
w1c
Write-only fields
FIELD
“Write 1 to clear” field
(field will always read 0)
Figure 1-1. Register figure conventions
The numbering of register bits and fields on MPC5606BK is as follows:
MPC5606BK Microcontroller Reference Manual, Rev. 2
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25
Chapter 1 Preface
•
•
1.5
Register bit numbers, shown at the top of each figure, use the standard Power Architecture bit
ordering (0, 1, 2, ...) where bit 0 is the most significant bit (MSB).
Multi-bit fields within a register use conventional bit ordering (..., 2, 1, 0) where bit 0 is the least
significant bit (LSB).
References
In addition to this reference manual, the following documents provide additional information on the
operation of the MPC5606BK:
• IEEE 1149.1-2001 standard—IEEE Standard Test Access Port and Boundary-Scan Architecture
• Power Architecture Book E V1.0
(http://www.freescale.com/files/32bit/doc/user_guide/BOOK_EUM.pdf)
1.6
How to use the MPC5606BK documents
This section:
• Describes how the MPC5606BK documents provide information on the microcontroller
• Makes recommendations on how to use the documents in a system design
1.6.1
The MPC5606BK document set
The MPC5606BK document set comprises:
• This reference manual (provides information on the features of the logical blocks on the device and
how they are integrated with each other)
• The device data sheet (specifies the electrical characteristics of the device)
• The device product brief
The following reference documents (available online at www.freescale.com) are also available to support
the CPU on this device:
• Programmer’s Reference Manual for Freescale Embedded Processors
• e200z0 Power Architecture Core Reference Manual
• Variable-Length Encoding (VLE) Programming Environments Manual
The aforementioned documents describe all of the functional and electrical characteristics of the
MPC5606BK microcontroller.
Depending on your task, you may need to refer to multiple documents to make design decisions. However,
in general the use of the documents can be divided up as follows:
• Use the reference manual (this document) during software development and when allocating
functions during system design.
• Use the data sheet when designing hardware and optimizing power consumption.
• Use the CPU reference documents when:
— Configuring CPU memory and branch optimizations
MPC5606BK Microcontroller Reference Manual, Rev. 2
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Chapter 1 Preface
— Doing detailed software development in assembly language
— Debugging complex software interactions
1.6.2
Reference manual content
The content in this document focuses on the functionality of the microcontroller rather than its
performance. Most chapters describe the functionality of a particular on-chip module, such as a CAN
controller or timer. The remaining chapters describe how these modules are integrated into the memory
map, how they are powered and clocked, and the pin-out of the device.
In general, when an individual module is enabled for use all of the detail required to configure and operate
it is contained in the dedicated chapter. In some cases there are multiple implementations of this module,
however, there is only one chapter for each type of module in use. For this reason, the address of registers
in each module is normally provided as an offset from a base address that can be found in Chapter 3,
Memory Map. The benefit of this approach is that software developed for a particular module can be easily
reused on this device and on other related devices that use the same modules.
The steps to enable a module for use varies but typically these require configuration of the integration
features of the microcontroller. The module will normally have to be powered and enabled at system level,
then a clock may have to be explicitly chosen, and finally (if required) the input and output connections to
the external system must be configured.
The primary integration chapters of the reference manual contain most of the information required to
enable the modules. There are special cases where a chapter may describe module functionality and some
integration features for convenience — for example, the microcontroller input/output (SIUL) module.
Integration and functional content is provided in the manual as shown in Table 1-2.
Table 1-2. Reference manual integration and functional content
Chapter
Integration content
Functional content
Introduction
• The main features on chip
—
• A summary of the functions provided by
each module
Memory Map
—
How the memory map is allocated,
including:
• Internal RAM
• Flash memory
• External memory-mapped resources
and the location of the registers used by
the peripherals1
Signal Description
How the signals from each of the modules —
are combined and brought to a particular
pin on a package
Boot Assist Module
CPU boot sequence from reset
Implementation of the boot options if
internal flash memory is not used
Clock Description
Clocking architecture of the device (which Description of operation of different clock
clock is available for the system and each sources
peripheral)
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Chapter 1 Preface
Table 1-2. Reference manual integration and functional content (continued)
Chapter
Integration content
Functional content
eDMA Channel Multiplexer Source values for module eDMA channels How to connect a module eDMA channel
to the eDMA module
Interrupt Controller
Interrupt vector table
Operation of the module
Mode Entry Module
Module numbering for control and status
Operation of operating modes
System Integration Unit
Lite
How input signals are mapped to individual Operation of GPIO
modules including external interrupt pins
Voltage regulators and
power supplies
Power distribution to the MCU
—
Wakeup Unit
Allocation of inputs to the Wakeup Unit
Operation of the wakeup feature
1
1.7
To find the address of a register in a particular module take the start address of the module given in the memory
map and add the offset for the register given in the module chapter.
Using the MPC5606BK
There are many different approaches to designing a system using the MPC5606BK so the guidance in this
section is provided as an example of how the documents can be applied in this task.
Familiarity with the MPC5606BK modules can help ensure that its features are being optimally used in a
system design. Therefore, the current chapter is a good starting point. Further information on the detailed
features of a module are provided within the module chapters. These, combined with the current chapter,
should provide a good introduction to the functions available on the MCU.
1.7.1
Hardware design
The MPC5606BK requires that certain pins are connected to particular power supplies, system functions,
and other voltage levels for operation.
The MPC5606BK internal logic operates from 1.2 V (nominal) supplies that are normally supplied by the
on-chip voltage regulator from a 5 V or 3.3 V supply. The 3.3–5 V (±10%) supply is also used to supply
the input/output pins on the MCU. Chapter 4, Signal description, describes the power supply pin names,
numbers, and their purpose. For more detail on the voltage supply of each pin, see Chapter 11, Voltage
Regulators and Power Supplies. For specifications of the voltage ranges and limits and decoupling of the
power supplies see the MPC5606BK data sheet.
Certain pins have dedicated functions that affect the behavior of the MCU after reset. These include pins
to force test or alternate boot conditions and debug features. These are described in Chapter 4, Signal
description, and a hardware designer should take care that these pins are connected to allow correct
operation.
Beyond power supply and pins that have special functions there are also pins that have special system
purposes such as oscillator and reset pins. These are also described in Chapter 4, Signal description. The
reset pin is bidirectional, and its function is closely tied to the reset generation module [Chapter 9, Reset
Generation Module (MC_RGM)]. The crystal oscillator pins are dedicated to this function but the
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Freescale Semiconductor
Chapter 1 Preface
oscillator is not started automatically after reset. The oscillator module is described in Section 6.3, Fast
external crystal oscillator (FXOSC) digital interface, along with the internal clock architecture and the
other oscillator sources on chip.
1.7.2
Input/output pins
The majority of the pins on the MCU are input/output pins, which may either operate as general purpose
pins or be connected to a particular on-chip module. The arrangement allows a function to be available on
several pins. The system designer should allocate the function for the pin before connecting to external
hardware. The software should then choose the correct function to match the hardware. The pad
characteristics can vary depending on the functions on the pad. Chapter 4, Signal description, describes
each pad type (for example, S, M, or J). Two pads may be able to carry the same function but have different
pad types. The electrical specification of the pads is described in the data sheet dependent on the function
enabled and the pad type.
There are three modules that configure the various functions available:
• System Integration Unit Lite (SIUL)
• Wakeup Unit (WKPU)
• 32 KHz oscillator (SXOSC)
The SIUL configures the digital pin functions. Each pin has a register (PCR) in the module that allows
selection of the output functions that is connected to the pin. The available settings for the PCR are
described in Section 4.2, Pin muxing. Inputs are selected using the PSMI registers; these are described in
Chapter 20, System Integration Unit Lite (SIUL). (PSMI registers connect a module to one of several pins,
whereas the PCR registers connect a pin to one of several modules).
The WKPU provides the ability to cause interrupts and wake the MCU from low power modes, and
operates independently from the SIUL.
In addition to digital I/O functions, the SXOSC is a “special function” that provides a slow external crystal.
The SXOSC is enabled independently from the digital I/O, which means that the digital function on the
pin must be disabled when the SXOSC is active.
The ADC functions are enabled using the PCRs.
1.7.3
Software design
Certain modules provide system integration functions, and other modules (such as timers) provide specific
functions.
From reset, the modules involved in configuring the system for application software are:
• Boot Assist Module (BAM) — determines the selected boot source
• Reset Generation Module (MC_RGM) — determines the behavior of the MCU when various reset
sources are triggered and reports the source of the reset
• Mode Entry Module (MC_ME) — controls the operating mode the MCU is in and configures the
peripherals, clocks, and power supplies for each of the modes
• Power Control Unit (MC_PCU) — determines which power domains are active
MPC5606BK Microcontroller Reference Manual, Rev. 2
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Chapter 1 Preface
•
Clock Generation Module (MC_CGM) — chooses the clock source for the system and many
peripherals
After reset, the MCU will automatically select the appropriate reset source and begin to execute code. At
this point the system clock is the 16 MHz FIRC (internal) oscillator, the CPU is in supervisor mode and
all the memory is available. Initialization is required before most peripherals may be used and before the
SRAM can be read (since the SRAM is protected by ECC, the syndrome will generally be uninitialized
after reset and reads would fail the check). Accessing disabled features causes error conditions or
interrupts.
A typical startup routine would involve initializing the software environment including stacks, heaps,
memory, and variable initialization; and configuring the MCU for the application.
The MC_ME module enables the modules and other features like clocks. It is therefore an essential part
of the initialization and operation software. In general, the software will configure an MC_ME mode to
make certain peripherals, clocks, and memory active and then switch to that mode.
Chapter 6, Clock Description, includes a graphic of the clock architecture of the MCU. This can be used
to determine how to configure the MC_CGM module. In general software will configure the module to
enable the required clocks and PLLs and route these to the active modules.
After these steps are complete it is possible to configure the input/output pins and the modules for the
application.
1.7.4
Other features
The MC_ME module manages low power modes and so it is likely that it will be used to switch into
different configurations (module sets, clocks) depending on the application requirements.
The MCU includes two other features to improve the integrity of the application:
• It is possible to enable a software watchdog (SWT) immediately at reset or afterwards to help
detect code runaway.
• Individual register settings can be protected from unintended writes using the features of the
Register Protection module. The protected registers are shown in Chapter 32, Register Protection.
Other integration functionality is provided by the System Status and Configuration Module (SSCM).
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Chapter 2 Introduction
Chapter 2
Introduction
2.1
The MPC5606BK microcontroller family
The MPC5606BK is a family of Power Architecture®-based microcontrollers that target automotive
vehicle body applications such as:
• Central body electronics
• Vehicle body controllers
• Smart junction boxes
• Front modules
• Body peripherals
• Door control
• Seat control
The MPC5606BK family expands the range of the MPC560xB/C microcontroller family. It provides the
scalability needed to implement platform approaches and delivers the performance required by
increasingly sophisticated software architectures. The advanced and cost-efficient host processor core of
the MPC5606BK automotive controller family complies with the Power Architecture embedded category,
and only implements the VLE (variable-length encoding) APU, providing improved code density. It
operates at speeds as high as 64 MHz and offers high performance processing optimized for low power
consumption. It also capitalizes on the available development infrastructure of current Power Architecture
devices and is supported with software drivers, operating systems, and configuration code to assist with
users implementations.
This document describes the features of the family and options available within the family members, and
highlights important electrical and physical characteristics of the device.
2.2
MPC5606BK device comparison
Table 2-1 summarizes the MPC5606BK family of microcontrollers.
Table 2-1. MPC5606BK family comparison1
Feature
Package
MPC5605BK
100 LQFP
144 LQFP
CPU
Execution
MPC5606BK
176 LQFP
100 LQFP
144 LQFP
176 LQFP
e200z0h
speed2
Code flash memory
Up to 64 MHz
768 KB
Data flash memory
SRAM
1024 KB
1 MB
64 (4 x 16) KB
64 KB
64 KB
MPU
8-entry
eDMA
16 ch
80 KB
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Chapter 2 Introduction
Table 2-1. MPC5606BK family comparison1 (continued)
Feature
MPC5605BK
MPC5606BK
10-bit ADC
Yes
dedicated
3
7 ch
15 ch
29 ch
shared with 12-bit ADC
7 ch
15 ch
29 ch
19 ch
12-bit ADC
Yes
dedicated4
5 ch
shared with 10-bit ADC
19 ch
5
Total timer I/O
eMIOS
37 ch,
16-bit
64 ch,
16-bit
Counter / OPWM / ICOC6
10 ch
ICOC7
7 ch
O(I)PWM / OPWFMB / OPWMCB /
37 ch,
16-bit
64 ch,
16-bit
O(I)PWM / ICOC8
7 ch
14 ch
7 ch
14 ch
OPWM / ICOC9
13 ch
33 ch
13 ch
33 ch
SCI (LINFlex)
4
6
8
4
6
8
SPI (DSPI)
3
5
6
3
5
6
77
121
149
CAN (FlexCAN)
6
I2C
1
32 KHz oscillator
GPIO10
Yes
77
121
149
Debug
JTAG
1
Feature set dependent on selected peripheral multiplexing; table shows example.
Based on 125 C ambient operating temperature.
3 Not shared with 12-bit ADC, but possibly shared with other alternate functions.
4 Not shared with 10-bit ADC, but possibly shared with other alternate functions.
5 Refer to eMIOS section of device reference manual for information on the channel configuration and functions.
6 Each channel supports a range of modes including Modulus counters, PWM generation, Input Capture, Output Compare.
7 Each channel supports a range of modes including PWM generation with dead time, Input Capture, Output Compare.
8 Each channel supports a range of modes including PWM generation, Input Capture, Output Compare, Period and Pulse width
measurement.
9 Each channel supports a range of modes including PWM generation, Input Capture, and Output Compare.
10 Maximum I/O count based on multiplexing with peripherals.
2
2.3
Device block diagram
Figure 2-1 shows a top-level block diagram of the MPC5606BK.
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Chapter 2 Introduction
JTAG
SRAM
80 KB
Code Flash Data Flash
1.0 MB
64 KB
SRAM
Controller
Flash memory
controller
eDMA
(Master)
Data
NMI
(Master)
SIUL
Voltage
Regulator
Interrupt requests
from peripheral
blocks
NMI
INTC
Clocks
MPU
Instructions
e200z0h
32-bit 3 × 3 Crossbar Switch
(Master)
JTAG Port
(Slave)
(Slave)
Interrupt
request with
wakeup
functionality
(Slave)
MPU
Registers
WKPU
CMU
FMPLL
RTC
STM
SWT
ECSM
MC_RGM MC_CGM
PIT
MC_ME MC_PCU
BAM
SSCM
I2C
6x
FlexCAN
Peripheral Bridge
Interrupt
Request
SIUL
Reset Control
19 ch 10-bit/12-bit
ADC
External
Interrupt
Request
29 ch 10-bit
ADC
8x
LINFlex
64 ch
eMIOS
CTU
6x
DSPI
5 ch 12-bit
ADC
IMUX
GPIO &
Pad Control
I/O
...
...
...
...
...
Legend:
ADC
BAM
FlexCAN
CFlash
CMU
CTU
DFlash
DSPI
eDMA
eMIOS
FMPLL
I2C
IMUX
INTC
JTAG
Analog-to-Digital Converter
Boot Assist Module
Controller Area Network
Code flash memory
Clock Monitor Unit
Cross Triggering Unit
Data flash memory
Deserial Serial Peripheral Interface
Enhanced Direct Memory Access
Enhanced Modular Input Output System
Frequency-Modulated Phase-Locked Loop
Inter-integrated Circuit Bus
Internal Multiplexer
Interrupt Controller
JTAG controller
LINFlex
MC_CGM
MC_ME
MPU
NMI
MC_PCU
MC_RGM
PIT
RTC
SIUL
SRAM
SSCM
STM
SWT
WKPU
Serial Communication Interface (LIN support)
Clock Generation Module
Mode Entry Module
Memory Protection Unit
Non-Maskable Interrupt
Power Control Unit
Reset Generation Module
Periodic Interrupt Timer
Real-Time Clock
System Integration Unit Lite
Static Random-Access Memory
System Status Configuration Module
System Timer Module
Software Watchdog Timer
Wakeup Unit
Figure 2-1. MPC5606BK block diagram
Table 2-2 summarizes the functions of the blocks present on the MPC5606BK.
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Chapter 2 Introduction
Table 2-2. MPC5606BK series block summary
Block
Function
Analog-to-digital converter (ADC)
Converts analog voltages to digital values
Boot assist module (BAM)
A block of read-only memory containing VLE code which is executed according to the
boot mode of the device
Clock generation module (MC_CGM) Provides logic and control required for the generation of system and peripheral clocks
Crossbar switch (XBAR)
Supports simultaneous connections between three master ports and three slave ports.
The crossbar supports a 32-bit address bus width and a 64-bit data bus width.
Cross triggering unit (CTU)
Enables synchronization of ADC conversions with a timer event from the eMIOS or from
the PIT
Deserial serial peripheral interface
(DSPI)
Provides a synchronous serial interface for communication with external devices
Enhanced modular input output
system (eMIOS)
Provides the functionality to generate or measure events
Flash memory
Provides non-volatile storage for program code, constants and variables
FlexCAN (controller area network)
Supports the standard CAN communications protocol
Frequency-modulated phase-locked
loop (FMPLL)
Generates high-speed system clocks and supports programmable frequency modulation
Internal multiplexer (IMUX) SIU
subblock
Allows flexible mapping of peripheral interface on the different pins of the device
Inter-integrated circuit (I2C™) bus
A two wire bidirectional serial bus that provides a simple and efficient method of data
exchange between devices
Interrupt controller (INTC)
Provides priority-based preemptive scheduling of interrupt requests
JTAG controller
Provides the means to test chip functionality and connectivity while remaining transparent
to system logic when not in test mode
LINFlex controller
Manages a high number of LIN (Local Interconnect Network protocol) messages
efficiently with a minimum of CPU load
Memory protection unit (MPU)
Provides hardware access control for all memory references generated in a device
Periodic interrupt timer (PIT)
Produces periodic interrupts and triggers
Real-time counter (RTC)
A free running counter used for time keeping applications, the RTC can be configured to
generate an interrupt at a predefined interval independent of the mode of operation (run
mode or low-power mode)
Reset generation module (MC_RGM) Centralizes reset sources and manages the device reset sequence of the device
Static random-access memory
(SRAM)
Provides storage for program code, constants, and variables
System integration unit lite (SIUL)
Provides control over all the electrical pad controls and up 32 ports with 16 bits of
bidirectional, general-purpose input and output signals and supports up to 32 external
interrupts with trigger event configuration
System timer module (STM)
Provides a set of output compare events to support the Automotive Open System
Architecture (AUTOSAR) and operating system tasks
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Chapter 2 Introduction
2.4
2.4.1
Feature details
e200z0h core processor
The e200z0h core includes the following features:
• High performance, e200z0h core processor for managing peripherals and interrupts
• Single issue 4-stage pipelined in-order execution, 32-bit Power Architecture CPU
• Variable length encoding (VLE), allowing mixed 16-bit and 32-bit instructions
— Results in efficient code size footprint
— Minimizes impact on performance
• Branch processing acceleration using lookahead instruction buffer
• Load/store unit
— 1-cycle load latency
— Misaligned access support
— No load-to-use pipeline bubbles
• 32-bit general purpose registers (GPRs)
• Separate instruction bus and load/store bus Harvard architecture
• Hardware vectored interrupt support
• Multi-cycle divide word (divw) and load multiple word (lmw) store multiple word (smw) multiple
class instructions, can be interrupted to prevent increases in interrupt latency
2.4.2
Crossbar switch (XBAR)
The following summarizes the MPC5606BK’s implementation of the crossbar switch:
• Three master ports:
— CPU instruction bus
— CPU load/store bus
— eDMA
• Multiple bus slaves to enable access to flash memory, SRAM, and peripherals
• Crossbar supports as many as two consecutive transfers at any one time
• 32-bit internal address bus, 32-bit internal data bus
• Fixed priority arbitration based on port master
2.4.3
Interrupt Controller (INTC)
The MPC5606BK implements an interrupt controller that features the following:
• Unique 9-bit vector for each of the 231 separate interrupt sources
• Eight software triggerable interrupt sources
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Chapter 2 Introduction
•
•
•
2.4.4
16 priority levels with fixed hardware arbitration within priority levels for each interrupt source
Ability to modify the ISR or task priority
— Modifying the priority can be used to implement Priority Ceiling Protocol for accessing shared
resources
External high priority interrupt directly accessing the main core critical interrupt mechanism
System Integration Unit Lite (SIUL)
The SIUL features the following:
• As many as four levels of internal pin multiplexing, allowing exceptional flexibility in the
allocation of device functions for each package
• Centralized general purpose input output (GPIO) control of as many as 149 input/output pins
(package dependent)
• All GPIO pins independently configurable to support pull-up pull down, or no pull
• Reading and writing to GPIO supported both as individual pins and 16-bit wide ports
• All peripheral pins can be alternatively configured as both general purpose input or output pins
except ADC channels which support alternative configuration as general purpose inputs, with
selected pins able to also support outputs
• Direct readback of the pin value supported on all digital output pins through the SIUL
• Configurable digital input filter that can be applied to as many as 16 general purpose input pins for
noise elimination on external interrupts
• Register configuration protected against change with soft lock for temporary guard or hard lock to
prevent modification until next reset
• Support for two 32-bit virtual ports via the DSPI serialization
2.4.5
Flash memory
The on-chip flash memory on the MPC5606BK features the following:
• As much as 1.0 MB burst flash memory
— 4  128-bit page buffers with programmable prefetch control
— Typical flash-memory access time: 0 wait-state for buffer hits, 2 wait-states for page buffer
miss at 64 MHz
— Page buffers can be allocated for code-only, fixed partitions of code and data, all available for
any access
— 64-bit ECC with single-bit correction, double-bit detection for data integrity
• Censorship protection scheme to prevent flash-memory content visibility
• Separate dedicated data flash memory (DFlash) for EEPROM emulation
— Four erase sectors, each containing 16 KB of memory
— Offers read-while-write functionality from main program space
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Chapter 2 Introduction
•
•
•
•
Small block flash-memory arrangement in main array to support features such as boot block,
operating system block
Hardware managed flash memory writes, erase and verify sequence
Flash-memory partitioning (see Table 2-3)
Error correction status
— Configurable error-correcting codes (ECC) reporting for SRAM and flash memory
— Supports optional reporting of single-bit errors
— Protected mechanism for reporting of corrected ECC values
— Error address recorded including Access type and Master
— Flash-memory ECC reporting registers mirrored into ECSM address space but data comes
from the flash-memory module
— Flash-memory module can be interrogated to provide ECC bit error location
— Margin read for flash-memory array supported for initial program verification
Table 2-3. Flash memory partitioning
MPC5605B
MPC5606B
768 MB
1 MB
Array_A Flash_Base + 0x0000_0000
32 KB
32 KB
Flash_Base + 0x0000_8000
16 KB
16 KB
Flash_Base + 0x0000_C000
16 KB
16 KB
Flash_Base + 0x0001_0000
32 KB
32 KB
Flash_Base + 0x0001_8000
32 KB
32 KB
Flash_Base + 0x0002_0000
128 KB
128 KB
Flash_Base + 0x0004_0000
128 KB
128 KB
Flash_Base + 0x0006_0000
128 KB
128 KB
Array_B Flash_Base + 0x0008_0000
128 KB
128 KB
Flash_Base + 0x000A_0000
128 KB
128 KB
Flash_Base + 0x000C_0000
—
128 KB
Flash_Base + 0x000E_0000
—
128 KB
Array_C Flash_Base + 0x0010_0000
—
—
Flash_Base + 0x0012_0000
—
—
Flash_Base + 0x0014_0000
—
—
Flash_Base + 0x0016_0000
—
—
Array
Address
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Chapter 2 Introduction
Table 2-3. Flash memory partitioning (continued)
MPC5605B
MPC5606B
768 MB
1 MB
Array_D Data Flash Block + 0x0000_0000
16 KB
16 KB
Data Flash Block + 0x0000_4000
16 KB
16 KB
Data Flash Block + 0x0000_8000
16 KB
16 KB
Data Flash Block + 0x0000_C000
16 KB
16 KB
Array
2.4.6
Address
SRAM
The on-chip SRAM on the MPC5606BK features the following:
• As much as 80 KB general purpose SRAM
• Typical SRAM access time: 0 wait-state for reads and 32-bit writes; 1 wait-state for 8- and 16-bit
writes if back to back with a read to same memory block
• 32-bit ECC with single-bit correction, double-bit detection for data integrity
• Supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of memory
• User transparent ECC encoding and decoding for byte, half word, and word accesses
• Separate internal power domain applied to 32 KB SRAM block or 8 KB SRAM block during
STANDBY modes to retain contents during low power mode
2.4.7
Memory Protection Unit (MPU)
The MPU provides the following features
• Eight region descriptors for per-master protection
• Start and end address defined with 32-byte granularity
• Overlapping regions supported
• Protection attributes can optionally include process ID
• Protection offered for Threeconcurrent read ports
• Read and write attributes for all masters
• Execute and supervisor/user mode attributes for processor masters
2.4.8
Boot Assist Module (BAM)
The device implements a Boot Assist Module (BAM):
• Block of read-only memory containing VLE code which is executed according to boot mode of the
device
• Download of code into internal SRAM possible via FlexCAN or LINFlex, afterwhich code can be
executed
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Chapter 2 Introduction
2.4.9
Enhanced Modular Input Output System (eMIOS)
The MPC5606BK implements a scaled-down version of the eMIOS module:
• As many as 64 timed I/O channels with 16-bit counter resolution
• Buffered updates
• Support for shifted PWM outputs to minimize occurrence of concurrent edges
• Supports configurable trigger outputs for ADC conversion for synchronization to channel output
waveforms
• Edge-aligned output pulse width modulation
— Programmable pulse period and duty cycle
— Supports 0% and 100% duty cycle
— Shared or independent time bases
• DMA transfer support available
Table 2-4 shows the supported eMIOS modes.
Table 2-4. Supported eMIOS channel modes
Mode
Description
Channel type
Name
O(I)PWM /
Counter /
OPWFMB / O(I)PWM /
OPWM /
OPWMCB /
ICOC
ICOC
ICOC
OPWM /
ICOC
Double action output compare
DAOC
×
×
×
—
General purpose input / output
GPIO
×
×
×
×
Input filter
IPF
×
×
×
×
Input period measurement
IPM
×
×
×
—
IPWM
×
×
×
—
MC
×
—
—
—
MCB
×
×
—
—
Output pulse width and frequency modulation
buffered
OPWFMB
×
×
—
—
Output pulse width modulation buffered
OPWMB
—
×
×
×
Center aligned output PWM buffered with dead time OPWMCB
—
×
—
—
Output pulse width modulation trigger
OPWMT
×
×
×
×
Pulse edge accumulation
PEA
×
—
—
—
Pulse edge counting
PEC
×
—
—
—
Quadrature decode
QDEC
×
—
—
—
Single action input capture
SAIC
×
×
×
×
Single action output compare
SAOC
×
×
×
×
Input pulse width measurement
Modulus counter
Modulus counter buffered (up / down)
Table 2-5 shows the maximum eMIOS channel allocation.
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Chapter 2 Introduction
Table 2-5. eMIOS configuration
Maximum number of channels
Channel type
Total
eMIOS_0
eMIOS_1
5
5
10
7
0
7
O(I)PWM / ICOC
7
7
14
OPWM / ICOC4
13
20
33
Counter / OPWM / ICOC1
O(I)PWM / OPWFMB / OPWMCB / ICOC
2
3
1
Each channel supports a range of modes including Modulus counters, PWM generation, Input Capture, Output
Compare.
2
Each channel supports a range of modes including PWM generation with dead time, Input Capture, Output
Compare.
3
Each channel supports a range of modes including PWM generation, Input Capture, Output Compare, Period and
Pulse width measurement.
4
Each channel supports a range of modes including PWM generation, Input Capture, Output Compare.
2.4.10
Deserial Serial Peripheral Interface Module (DSPI)
The DSPI features the following:
• As many as six DSPI modules supported
• Full duplex, synchronous transfers
• Master or slave operation
• Programmable master bit rates
• Programmable clock polarity and phase
• End-of-transmission interrupt flag
• Programmable transfer baud rate
• Programmable data frames from 4 to 16 bits
• As many as six chip select lines available, depending on package and pin multiplexing, to enable
64 external devices to be selected using external muxing from a single DSPI
• As many as eight transfer types, independently configurable for each DSPI using the clock and
transfer attributes registers
• Chip select strobe available as alternate function on one of the chip select pins for deglitching
• FIFOs for buffering as many as four transfers on the transmit and receive side
• General purpose I/O functionality on pins when not used for SPI
• Queueing operation possible through use of eDMA
• 32-bit serialization of data enabling virtual GPIO ports on 2 DSPI modules
2.4.11
Controller Area Network module (FlexCAN)
The enhanced FlexCAN module features the following:
• As many as six FlexCAN modules supported
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Freescale Semiconductor
Chapter 2 Introduction
•
•
•
•
•
•
•
Compliant with CAN protocol specification, version 2.0B active
64 mailboxes per FlexCAN module
— Mailboxes configurable while module remains synchronized to CAN bus
— Each mailbox configurable as transmit or receive
Transmit features
— Supports configuration of multiple mailboxes to form message queues of scalable depth
— Arbitration scheme according to message ID or message buffer number
— Internal arbitration to guarantee no inner or outer priority inversion
— Transmit abort procedure and notification
Receive features
— Individual programmable filters for each mailbox
— Eight mailboxes configurable as a 6-entry receive FIFO
— Eight programmable acceptance filters for receive FIFO
Programmable clock source
— System clock
— Direct oscillator clock to avoid PLL jitter
Listen only mode capabilities
CAN sampler available for connection to one of available CAN module pads
— Supports capturing of first message identifier while in STOP or STANDBY modes
2.4.12
System clocks and clock generation
The following list summarizes the system clock and clock generation on the MPC5606BK:
• System clock can be derived from the following sources
— External crystal oscillator
— FMPLL
— 16 MHz fast internal RC oscillator
• Programmable output clock divider of system clock (1, 2, 4)
• Separate programmable peripheral bus clock divider ratio (1, 2, 4) applied to system clock
• Frequency modulated phase-locked loop (FMPLL)
— Input clock frequency from 4 MHz to 16 MHz
— Clock sources: external oscillator or internal FIRC oscillator
— Lock detect circuitry continuously monitors lock status
— Loss of clock (LOC) detection for reference and feedback clocks
— On-chip loop filter
– Improves electromagnetic interference performance
– Reduces number of external components required
• On-chip fast external crystal oscillator supporting 4 MHz to 16 MHz
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Chapter 2 Introduction
•
•
•
Dedicated 16 MHz fast internal RC oscillator
— Used as default clock source out of reset
— Provides clock for rapid startup from low power modes
— Provides back-up clock in the event of FMPLL or external oscillator clock failure
— Offers independent clock source for the watchdog timer
— 5% accuracy over the operating temperature range
— Trimming registers to support frequency adjustment with in-application calibration
Dedicated 128 kHz slow internal RC oscillator for low power mode operation and self wakeup
— 5% accuracy
— Trimming registers to support improve accuracy with in-application calibration
32-KHz low power external oscillator for low power real time clock
2.4.13
System timers
The system timers include:
• Peripheral Interrupt Timer (PIT) timers (including ADC trigger)
• One Real-Time Counter (RTC) timer
The PIT is an array of timers that can be used to raise interrupts, trigger CTU channels and ADC
conversions. The RTC supports wakeup from low power modes or real-time clock generation.
2.4.13.1
Periodic Interrupt Timer module (PIT)
The PIT features the following:
• Eight general purpose interrupt timers
• As many as two interrupt timers for triggering ADC injected conversions (one for 10-bit ADC, one
for 12-bit ADC)
• As many as four interrupt timers for triggering DMA transfers
• As many as two interrupt timers for triggering CTU
• 32-bit counter resolution
• Clocked by system clock frequency
2.4.13.2
Real-Time Counter (RTC)
The RTC features the following:
• Configurable resolution for different timeout periods
— 1 sec resolution for > 1 hour period
— 1 ms resolution for 2 second period
• Selectable clock sources
— 128 kHz slow internal RC oscillator
— Divided 16 MHz fast internal RC oscillator
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Chapter 2 Introduction
•
— External 32 KHz crystal
Supports continued operation through all resets except POR (power-on reset)
2.4.14
System watchdog timer
The watchdog on the MPC5606BK features the following:
• Activation by software or out of reset
• 32-bit modulus counter
• Clock source: robust 128 kHz slow internal RC oscillator (divisible by 1 to 32)
• Supports normal or windowed mode
• Configurable response on timeout: reset, interrupt, or interrupt followed by reset
• Reset by writing a software key to memory mapped register
• Support for protected access to watchdog control registers with optional soft and hard locks
— Soft lock allows temporary locking of configuration
— Once enabled, hard lock prevents any changes until after a reset
• Supports halting during low power modes
2.4.15
Inter-Integrated Circuit (I2C) module
The I2C module features the following:
• One I2C module supported
• 2-wire bidirectional serial bus for on-board communications
• Compatibility with I2C bus standard
• Multimaster operation
• Software-programmable for one of 256 different serial clock frequencies
• Software-selectable acknowledge bit
• Interrupt-driven, byte-by-byte data transfer
• Arbitration-lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
• Start and stop signal generation/detection
• Repeated START signal generation
• Acknowledge bit generation/detection
• Bus-busy detection
2.4.16
On-chip voltage regulator (VREG)
The on-chip voltage regulator includes the following features:
• Regulates 3.3 or 5 V ±10% input to generate all internal supplies for internal control
• Manages power gating
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Chapter 2 Introduction
•
•
•
Low power regulators support operation when in STOP and STANDBY modes to minimize power
consumption
Fast startup on-chip regulators for rapid exit from low power modes
Low voltage reset supported on all internal supplies
2.4.17
Analog-to-Digital Converter (ADC)
The ADC features the following:
• Two ADC modules, one 10-bit resolution and one 12-bit resolution supporting synchronous
conversions on channels
• 0–VDD common mode conversion range
• Independent reference supplies for each ADC
• Conversions times of < 1 µs available
• As many as 53 single ended inputs channels, expandable to 81 channels with external multiplexers
• As many as 19 shared channels, among which, 16 called ANP are mapped on dedicated pins, not
multiplexed with any other functionality, in order to improve the accuracy. All other channels,
called ANS or ANX are multiplexed with other functionalities.
— As many as 19 channels shared between 10-bit and 12-bit ADCs
— As many as five dedicated 12-bit ADC channels
— As many as 29 dedicated 10-bit ADC channels
• Externally multiplexed channels
— Internal control to support generation of external analog multiplexor selection
— Four internal channels optionally used to support externally multiplex inputs, providing
transparent control for additional ADC channels
— Each of the three channels supports as many as eight externally muxed inputs
— Individual dedicated result register also available for externally muxed conversion channels
— Three independently configurable sample and conversion times for high occurrence channels,
internally muxed channels and externally muxed channels
• Configurable right-aligned or left-aligned result formats
• Support for one-shot, scan and injection conversion modes
• Independently configurable parameters for channels:
— Offset refresh
— Sampling
• Conversion triggering support
— Internal conversion triggering from periodic interrupt timer (PIT) or timed I/O module
(eMIOS) through cross triggering unit (CTU)
— Internal conversion triggering from periodic interrupt timer (PIT)
— One input pin configurable as external conversion trigger source
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Chapter 2 Introduction
•
•
•
•
•
•
As many as six configurable analog comparator channels offering range comparison with triggered
alarm
— Greater than
— Less than
— Out of range
All unused analog pins available as general purpose input pins
Unused 10-bit ADC analog pins, with the exception of the 19 dedicated high accuracy channels,
available as general purpose output pins
Power-down mode
Supports DMA transfer of results based on end of conversion chain or each conversion
Separate dedicated DMA request for injection mode
2.4.18
Enhanced Direct Memory Access controller (eDMA)
The following summarizes the MPC5606BK’s implementation of the eDMA controller:
• 16 channels to support independent 8-, 16-, or 32-bit single value or block transfers
• Support of variable sized queues and circular queues
• Source and destination address registers independently configured to post-increment or remain
constant
• Each transfer initiated by peripheral, CPU, periodic timer interrupt, or eDMA channel request
• Peripheral DMA request sources possible from SPIs, I2C, 10-bit ADC, 12-bit ADC, eMIOS, and
GPIOs
• Each eDMA channel able to optionally send interrupt request to CPU on completion of single value
or block transfer
• DMA transfers possible between system memories and all accessible memory mapped locations
including peripheral and registers
• Programmable DMA channel mux allows assignment of any DMA source to any available DMA
channel with as many as 64 potential request sources
2.4.19
Cross Trigger Unit (CTU)
The CTU enables the synchronization of ADC conversions with a timer event. Its key features are:
• Single cycle delayed trigger output; trigger output is a combination of 64 (generic value) input
flags/events connected to different timers in the system
• Triggers ADC conversions from any eMIOS channel
• Triggers ADC conversions from as many as two dedicated PITs
• Maskable interrupt generation whenever a trigger output is generated
• One event configuration register dedicated to each timer event allows to define the corresponding
ADC channel
• Acknowledgment signal to eMIOS/PIT for clearing the flag
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Chapter 2 Introduction
•
Synchronization with ADC to avoid collision
2.4.20
Serial communication interface module (LINFlex)
The LINFlex on the MPC5606BK features the following:
• As many as eight LINFlex modules supported
• Supports LIN master mode, LIN slave mode and UART mode
• DMA connected on LINFlex_0 and LINFlex_1
• LINFlex_0 supporting LIN master and slave mode; LINFlex_1 to LINFlex_7 modules supporting
LIN master mode
• LIN state machine compliant to LIN 1.3, 2.0 and 2.1 specifications
• Handles LIN frame transmission and reception without CPU intervention
• LIN features
— Autonomous LIN frame handling
— Message buffer to store identified and up to 8 data bytes
— Supports message length of up to 64 bytes
— Detection and flagging of LIN errors
– Sync field; delimiter; ID parity; bit, framing; checksum and timeout errors
— Classic or extended checksum calculation
— Configurable break duration of up to 36-bit times
— Programmable baud rate prescalers (13-bit mantissa, 4-bit fractional)
— Diagnostic features
– Loop back; Self Test; LIN bus stuck dominant detection
— Interrupt driven operation with 16 interrupt sources
• LIN slave mode features
— Autonomous LIN header handling
— Autonomous LIN response handling
— 16 identifiers filters for discarding irrelevant LIN frames
• UART mode
— Full-duplex operation
— Standard non return-to-zero (NRZ) mark/space format
— Data buffers with 4-bytes receive, 4-bytes transmit
— Configurable word length (8-bit or 9-bit words)
— Error detection and flagging
– Parity, noise and framing errors
— Interrupt driven operation with four interrupt sources
— Separate transmitter and receiver CPU interrupt sources
— 16-bit programmable baud rate modulus counter and 16-bit fractional
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Freescale Semiconductor
Chapter 2 Introduction
— Two receiver wakeup methods
MPC5606BK devices include two functionally-different LINFlex controller types. These are
distinguished in the documentation by the abbreviations “LINFlex” and “LINFlexD”. The latter name
represents the DMA support available on this controller type. The MPC5606BK devices combine these
two types to provide as many as eight modules supporting the LINFlex protocol. Table 2-6 shows the
module (instance) numbers and the corresponding functional controller type.
Table 2-6. LINFlex numbering and naming
Module numbers
2.4.21
Module version
0 and 1
LINFlexD
2–7
LINFlex
JTAG Controller (JTAGC)
JTAG features the following:
• JTAG low pin count interface (IEEE 1149.1) test access port (TAP) interface
• Backward compatible to standard JTAG IEEE 1149.1-2001 test access port (TAP) interface
• Supports boundary scan testing
• All JTAG pins reusable in application as standard IOs
2.5
Developer support
The MPC5606BK MCU tools and third-party developers are similar to those used for the Freescale
MPC5500 product family, offering a widespread, established network of tool and software vendors.
The following development support will be available:
• Automotive evaluation boards (EVB) featuring CAN, LIN interfaces, and more
• Compilers
• Debuggers
• JTAG interface
The following software support will be available:
• OSEK solutions will be available from multiple third parties
• CAN and LIN drivers
• AutoSAR package
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Chapter 2 Introduction
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Chapter 3 Memory Map
Chapter 3
Memory Map
Table 3-1 shows the memory map for the MPC5606BK. All addresses on the device, including those that
are reserved, are identified in the table. The addresses represent the physical addresses assigned to each IP
block.
Table 3-1. MPC5606BK memory map
Start address
End address
Size (KB)
Region name
0x0000_0000
0x0000_7FFF
32
Code flash memory array 0
0x0000_8000
0x0000_BFFF
16
Code flash memory array 0
0x0000_C000
0x0000_FFFF
16
Code flash memory array 0
0x0001_0000
0x0001_7FFF
32
Code flash memory array 0
0x0001_8000
0x0001_FFFF
32
Code flash memory array 0
0x0002_0000
0x0003_FFFF
128
Code flash memory array 0
0x0004_0000
0x0005_FFFF
128
Code flash memory array 0
0x0006_0000
0x0007_FFFF
128
Code flash memory array 0
0x0008_0000
0x0009_FFFF
128
Code flash memory array 0
0x000A_0000
0x000B_FFFF
128
Code flash memory array 0
0x000C_0000
0x000D_FFFF
128
Code flash memory array 0
0x000E_0000
0x000F_FFFF
128
Code flash memory array 0
0x0010_0000
0x001F_FFFF
1024
Reserved
0x0020_0000
0x0020_3FFF
16
0x0020_4000
0x003F_FFFF
2032
0x0040_0000
0x0040_3FFF
16
0x0040_4000
0x007F_FFFF
4080
0x0080_0000
0x0080_3FFF
16
Data flash memory array 0
0x0080_4000
0x0080_7FFF
16
Data flash memory array 0
0x0080_8000
0x0080_BFFF
16
Data flash memory array 0
0x0080_C000
0x0080_FFFF
16
Data flash memory array 0
0x0081__0000
0x00BF_FFFF
4032
0x00C0_0000
0x00C0_3FFF
16
0x00C0_4000
0x00FF_FFFF
4080
0x0100_0000
0x1FFF_FFFF
507904
Flash memory emulation mapping
0x2000_0000
0x3FFF_FFFF
524288
Reserved
0x4000_0000
0x4001_3FFF
80
Flash memory shadow array
Reserved
Code flash memory array 0 test sector
Reserved
Reserved
Data flash memory array 0 test sector
Reserved
SRAM
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Chapter 3 Memory Map
Table 3-1. MPC5606BK memory map (continued)
Start address
End address
Size (KB)
0x4001_4000
0xBFFF_FFFF
2097072
Region name
Reserved
Off-platform peripherals
0xC000_0000
0xC3F8_7FFF
65056
Reserved
0xC3F8_8000
0xC3F8_BFFF
16
Code flash memory 0 configuration
0xC3F8_C000
0xC3F8_FFFF
16
Data flash memory 0 configuration
0xC3F9_0000
0xC3F9_3FFF
16
SIUL
0xC3F9_4000
0xC3F9_7FFF
16
WKPU
0xC3F9_8000
0xC3F9_FFFF
32
Reserved
0xC3FA_0000
0xC3FA_3FFF
16
eMIOS_0
0xC3FA_4000
0xC3FA_7FFF
16
eMIOS_1
0xC3FA_8000
0xC3FD_7FFF
192
Reserved
0xC3FD_8000
0xC3FD_BFFF
16
SSCM
0xC3FD_C000
0xC3FD_FFFF
16
MC_ME
0xC3FE_0000
0xC3FE_3FFF
16
MC_CGM
0xC3FE_4000
0xC3FE_7FFF
16
MC_RGM
0xC3FE_8000
0xC3FE_BFFF
16
MC_PCU
0xC3FE_C000
0xC3FE_FFFF
16
RTC/API
0xC3FF_0000
0xC3FF_3FFF
16
PIT
0xC3FF_4000
0xFFDF_FFFF
981040
0xFFE0_0000
0xFFE0_3FFF
16
ADC_0
0xFFE0_4000
0xFFE0_7FFF
16
ADC_1
0xFFE0_8000
0xFFE2_FFFF
160
Reserved
0xFFE3_0000
0xFFE3_3FFF
16
I2C_0
0xFFE3_4000
0xFFE3_FFFF
48
Reserved
0xFFE4_0000
0xFFE4_3FFF
16
LINFlex_0
0xFFE4_4000
0xFFE4_7FFF
16
LINFlex_1
0xFFE4_8000
0xFFE4_BFFF
16
LINFlex_2
0xFFE4_C000
0xFFE4_FFFF
16
LINFlex_3
0xFFE5_0000
0xFFE5_3FFF
16
LINFlex_4
0xFFE5_4000
0xFFE5_7FFF
16
LINFlex_5
0xFFE5_8000
0xFFE5_BFFF
16
LINFlex_6
0xFFE5_C000
0xFFE5_FFFF
16
LINFlex_7
0xFFE6_0000
0xFFE6_3FFF
16
Reserved
Reserved
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Chapter 3 Memory Map
Table 3-1. MPC5606BK memory map (continued)
Start address
End address
Size (KB)
Region name
0xFFE6_4000
0xFFE6_7FFF
16
CTU
0xFFE6_8000
0xFFE6_FFFF
32
Reserved
0xFFE7_0000
0xFFE7_3FFF
16
CAN sampler
0xFFE7_4000
0xFFE7_FFFF
48
Reserved
0xFFE8_0000
0xFFEF_FFFF
512
Mirrored range
0x3F80000—0xC3FFFFFF
0xFFF0_0000
0xFFF0_FFFF
64
Reserved
0xFFF1_0000
0xFFF1_3FFF
16
MPU
0xFFF1_4000
0xFFF3_7FFF
144
Reserved
0xFFF3_8000
0xFFF3_BFFF
16
SWT
0xFFF3_C000
0xFFF3_FFFF
16
STM
0xFFF4_0000
0xFFF4_3FFF
16
ECSM
0xFFF4_4000
0xFFF4_7FFF
16
eDMA
0xFFF4_8000
0xFFF4_BFFF
16
INTC
0xFFF4_C000
0xFFF8_FFFF
272
Reserved
0xFFF9_0000
0xFFF9_3FFF
16
DSPI_0
0xFFF9_4000
0xFFF9_7FFF
16
DSPI_1
0xFFF9_8000
0xFFF9_BFFF
16
DSPI_2
0xFFF9_C000
0xFFF9_FFFF
16
DSPI_3
0xFFFA_0000
0xFFFA_3FFF
16
DSPI_4
0xFFFA_4000
0xFFFA_7FFF
16
DSPI_5
0xFFFA_8000
0xFFFB_FFFF
96
Reserved
0xFFFC_0000
0xFFFC_3FFF
16
FlexCAN_0
0xFFFC_4000
0xFFFC_7FFF
16
FlexCAN_1
0xFFFC_8000
0xFFFC_BFFF
16
FlexCAN_2
0xFFFC_C000
0xFFFC_FFFF
16
FlexCAN_3
0xFFFD_0000
0xFFFD_3FFF
16
FlexCAN_4
0xFFFD_4000
0xFFFD_7FFF
16
FlexCAN_5
0xFFFD_8000
0xFFFD_BFFF
16
Reserved
0xFFFD_C000
0xFFFD_FFFF
16
DMA_MUX
0xFFFE_0000
0xFFFF_BFFF
144
Reserved
0xFFFF_C000
0xFFFF_FFFF
16
BAM
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Chapter 3 Memory Map
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Chapter 4 Signal Description
Chapter 4
Signal Description
4.1
Package pinouts
Figure 4-1, Figure 4-2, and Figure 4-3 show the location of the signals on the available packages for this
device.
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PB[2]
PC[8]
PC[13]
PC[12]
PE[7]
PE[6]
PE[5]
PE[4]
PC[4]
PC[5]
PE[3]
PE[2]
PH[9]
PC[0]
VSS_LV
VDD_LV
VDD_HV
VSS_HV
PC[1]
PH[10]
PA[6]
PA[5]
PC[2]
PC[3]
PE[12]
For more information on pin multiplexing on this chip, see Table 4-1.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
100 LQFP
Top view
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PA[11]
PA[10]
PA[9]
PA[8]
PA[7]
VDD_HV
VSS_HV
PA[3]
PB[15]
PD[15]
PB[14]
PD[14]
PB[13]
PD[13]
PB[12]
VDD_HV_ADC1
VSS_HV_ADC1
PD[11]
PD[10]
PD[9]
PB[7]
PB[6]
PB[5]
VDD_HV_ADC0
VSS_HV_ADC0
PC[7]
PA[15]
PA[14]
PA[4]
PA[13]
PA[12]
VDD_LV
VSS_LV
XTAL
VSS_HV
EXTAL
VDD_HV
PB[9]
PB[8]
PB[10]
PD[0]
PD[1]
PD[2]
PD[3]
PD[4]
PD[5]
PD[6]
PD[7]
PD[8]
PB[4]
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PB[3]
PC[9]
PC[14]
PC[15]
PA[2]
PE[0]
PA[1]
PE[1]
PE[8]
PE[9]
PE[10]
PA[0]
PE[11]
VSS_HV
VDD_HV
VSS_HV
RESET
VSS_LV
VDD_LV
VDD_BV
PC[11]
PC[10]
PB[0]
PB[1]
PC[6]
Figure 4-1. 100-pin LQFP pinout
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144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
PB[2]
PC[8]
PC[13]
PC[12]
PE[7]
PE[6]
PH[8]
PH[7]
PH[6]
PH[5]
PH[4]
PE[5]
PE[4]
PC[4]
PC[5]
PE[3]
PE[2]
PH[9]
PC[0]
VSS_LV
VDD_LV
VDD_HV
VSS_HV
PC[1]
PH[10]
PA[6]
PA[5]
PC[2]
PC[3]
PG[11]
PG[10]
PE[15]
PE[14]
PG[15]
PG[14]
PE[12]
Chapter 4 Signal Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
144 LQFP
Top view
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
PA[11]
PA[10]
PA[9]
PA[8]
PA[7]
PE[13]
PF[14]
PF[15]
VDD_HV
VSS_HV
PG[0]
PG[1]
PH[3]
PH[2]
PH[1]
PH[0]
PG[12]
PG[13]
PA[3]
PB[15]
PD[15]
PB[14]
PD[14]
PB[13]
PD[13]
PB[12]
VDD_HV_ADC1
VSS_HV_ADC1
PD[11]
PD[10]
PD[9]
PB[7]
PB[6]
PB[5]
VDD_HV_ADC0
VSS_HV_ADC0
PC[7]
PF[10]
PF[11]
PA[15]
PF[13]
PA[14]
PA[4]
PA[13]
PA[12]
VDD_LV
VSS_LV
XTAL
VSS_HV
EXTAL
VDD_HV
PB[9]
PB[8]
PB[10]
PF[0]
PF[1]
PF[2]
PF[3]
PF[4]
PF[5]
PF[6]
PF[7]
PD[0]
PD[1]
PD[2]
PD[3]
PD[4]
PD[5]
PD[6]
PD[7]
PD[8]
PB[4]
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
PB[3]
PC[9]
PC[14]
PC[15]
PG[5]
PG[4]
PG[3]
PG[2]
PA[2]
PE[0]
PA[1]
PE[1]
PE[8]
PE[9]
PE[10]
PA[0]
PE[11]
VSS_HV
VDD_HV
VSS_HV
RESET
VSS_LV
VDD_LV
VDD_BV
PG[9]
PG[8]
PC[11]
PC[10]
PG[7]
PG[6]
PB[0]
PB[1]
PF[9]
PF[8]
PF[12]
PC[6]
Figure 4-2. 144-pin LQFP pinout
MPC5606BK Microcontroller Reference Manual, Rev. 2
54
Freescale Semiconductor
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
176 LQFP
Top view
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
PA[11]
PA[10]
PA[9]
PA[8]
PA[7]
PE[13]
PF[14]
PF[15]
VDD_HV
VSS_HV
PG[0]
PG[1]
PH[3]
PH[2]
PH[1]
PH[0]
PG[12]
PG[13]
PA[3]
PI[13]
PI[12]
PI[11]
PI[10]
PI[9]
PI[8]
PB[15]
PD[15]
PB[14]
PD[14]
PB[13]
PD[13]
PB[12]
PD[12]
VDD_HV_ADC1
VSS_HV_ADC1
PB[11]
PD[11]
PD[10]
PD[9]
PB[7]
PB[6]
PB[5]
VDD_HV_ADC0
VSS_HV_ADC0
PC[7]
PF[10]
PF[11]
PA[15]
PF[13]
PA[14]
PA[4]
PA[13]
PA[12]
VDD_LV
VSS_LV
XTAL
VSS_HV
EXTAL
VDD_HV
PB[9]
PB[8]
PB[10]
PF[0]
PF[1]
PF[2]
PF[3]
PF[4]
PF[5]
PF[6]
PF[7]
PJ[3]
PJ[2]
PJ[1]
PJ[0]
PI[15]
PI[14]
PD[0]
PD[1]
PD[2]
PD[3]
PD[4]
PD[5]
PD[6]
PD[7]
VDD_HV
VSS_HV
PD[8]
PB[4]
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
PB[3]
PC[9]
PC[14]
PC[15]
PJ[4]
VDD_HV
VSS_HV
PH[15]
PH[13]
PH[14]
PI[6]
PI[7]
PG[5]
PG[4]
PG[3]
PG[2]
PA[2]
PE[0]
PA[1]
PE[1]
PE[8]
PE[9]
PE[10]
PA[0]
PE[11]
VSS_HV
VDD_HV
VSS_HV
RESET
VSS_LV
VDD_LV
VDD_BV
PG[9]
PG[8]
PC[11]
PC[10]
PG[7]
PG[6]
PB[0]
PB[1]
PF[9]
PF[8]
PF[12]
PC[6]
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
PB[2]
PC[8]
PC[13]
PC[12]
PI[0]
PI[1]
PI[2]
PI[3]
PE[7]
PE[6]
PH[8]
PH[7]
PH[6]
PH[5]
PH[4]
PE[5]
PE[4]
PC[4]
PC[5]
PE[3]
PE[2]
PH[9]
PC[0]
VSS_LV
VDD_LV
VDD_HV
VSS_HV
PC[1]
PH[10]
PA[6]
PA[5]
PC[2]
PC[3]
PI[4]
PI[5]
PH[12]
PH[11]
PG[11]
PG[10]
PE[15]
PE[14]
PG[15]
PG[14]
PE[12]
Chapter 4 Signal Description
Figure 4-3. 176-pin LQFP pinout
4.2
Pin muxing
Table 4-1 defines the pin list and muxing for this device.
Each entry of Table 4-1 shows all the possible configurations for each pin, via the alternate functions. The
default function assigned to each pin after reset is indicated by AF0.
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
55
Chapter 4 Signal Description
Pad type2
RESET
config.3
Pin number
I/O
direction
Peripheral
Table 4-1. Functional port pins
100
LQFP
PA[0]
PCR[0]
AF0
AF1
AF2
AF3
—
GPIO[0]
E0UC[0]
CLKOUT
E0UC[13]
WKUP[19]4
SIUL
eMIOS_0
MC_CGM
eMIOS_0
WKUP
I/O
I/O
O
I/O
I
M
Tristate
12
16
24
PA[1]
PCR[1]
AF0
AF1
AF2
AF3
—
GPIO[1]
E0UC[1]
NMI5
—
WKUP[2](4)
SIUL
eMIOS_0
WKUP
—
WKUP
I/O
I/O
I
—
I
S
Tristate
7
11
19
PA[2]
PCR[2]
AF0
AF1
AF2
AF3
—
GPIO[2]
E0UC[2]
—
MA[2]
WKUP[3](4)
SIUL
eMIOS_0
—
ADC_0
WKUP
I/O
I/O
—
O
I
S
Tristate
5
9
17
PA[3]
PCR[3]
AF0
AF1
AF2
AF3
—
—
GPIO[3]
E0UC[3]
LIN5TX
CS4_1
EIRQ[0]
ADC1_S[0]
SIUL
eMIOS_0
LINFlex_5
DSPI_1
SIUL
ADC_1
I/O
I/O
O
O
I
I
J
Tristate
68
90
114
PA[4]
PCR[4]
AF0
AF1
AF2
AF3
—
—
GPIO[4]
E0UC[4]
—
CS0_1
LIN5RX
WKUP[9](4)
SIUL
eMIOS_0
—
DSPI_1
LINFlex_5
WKUP
I/O
I/O
—
I/O
I
I
S
Tristate
29
43
51
PA[5]
PCR[5]
AF0
AF1
AF2
AF3
GPIO[5]
E0UC[5]
LIN4TX
—
SIUL
eMIOS_0
LINFlex_4
—
I/O
I/O
O
—
M
Tristate
79
118
146
PA[6]
PCR[6]
AF0
AF1
AF2
AF3
—
—
GPIO[6]
E0UC[6]
—
CS1_1
EIRQ[1]
LIN4RX
SIUL
eMIOS_0
—
DSPI_1
SIUL
LINFlex_4
I/O
I/O
—
O
I
I
S
Tristate
80
119
147
PA[7]
PCR[7]
AF0
AF1
AF2
AF3
—
—
GPIO[7]
E0UC[7]
LIN3TX
—
EIRQ[2]
ADC1_S[1]
SIUL
eMIOS_0
LINFlex_3
—
SIUL
ADC_1
I/O
I/O
O
—
I
I
J
Tristate
71
104
128
Port
pin
PCR
Alternate
register function1
Function
144
LQFP
176
LQFP
Port A
MPC5606BK Microcontroller Reference Manual, Rev. 2
56
Freescale Semiconductor
Chapter 4 Signal Description
GPIO[8]
E0UC[8]
E0UC[14]
—
EIRQ[3]
ABS[0]
LIN3RX
SIUL
eMIOS_0
eMIOS_0
—
SIUL
BAM
LINFlex_3
I/O
I/O
I/O
—
I
I
I
PCR[9]
AF0
AF1
AF2
AF3
N/A6
GPIO[9]
E0UC[9]
—
CS2_1
FAB
SIUL
eMIOS_0
—
DSPI_1
BAM
I/O
I/O
—
O
I
PA[10]
PCR[10]
AF0
AF1
AF2
AF3
—
GPIO[10]
E0UC[10]
SDA
LIN2TX
ADC1_S[2]
SIUL
eMIOS_0
I2C_0
LINFlex_2
ADC_1
PA[11]
PCR[11]
AF0
AF1
AF2
AF3
—
—
—
GPIO[11]
E0UC[11]
SCL
—
EIRQ[16]
LIN2RX
ADC1_S[3]
PA[12]
PCR[12]
AF0
AF1
AF2
AF3
—
—
PA[13]
PCR[13]
PA[14]
PA[15]
RESET
config.3
I/O
direction
AF0
AF1
AF2
AF3
—
N/A6
—
Pin number
Pad type2
Function
Peripheral
Table 4-1. Functional port pins (continued)
100
LQFP
144
LQFP
176
LQFP
S
Input,
weak
pull-up
72
105
129
S
Pulldown
73
106
130
I/O
I/O
I/O
O
I
J
Tristate
74
107
131
SIUL
eMIOS_0
I2C_0
—
SIUL
LINFlex_2
ADC_1
I/O
I/O
I/O
—
I
I
I
J
Tristate
75
108
132
GPIO[12]
—
E0UC[28]
CS3_1
EIRQ[17]
SIN_0
SIUL
—
eMIOS_0
DSPI_1
SIUL
DSPI_0
I/O
—
I/O
O
I
I
S
Tristate
31
45
53
AF0
AF1
AF2
AF3
GPIO[13]
SOUT_0
E0UC[29]
—
SIUL
DSPI_0
eMIOS_0
—
I/O
O
I/O
—
M
Tristate
30
44
52
PCR[14]
AF0
AF1
AF2
AF3
—
GPIO[14]
SCK_0
CS0_0
E0UC[0]
EIRQ[4]
SIUL
DSPI_0
DSPI_0
eMIOS_0
SIUL
I/O
I/O
I/O
I/O
I
M
Tristate
28
42
50
PCR[15]
AF0
AF1
AF2
AF3
—
GPIO[15]
CS0_0
SCK_0
E0UC[1]
WKUP[10](4)
SIUL
DSPI_0
DSPI_0
eMIOS_0
WKUP
I/O
I/O
I/O
I/O
I
M
Tristate
27
40
48
Port
pin
PCR
Alternate
register function1
PA[8]
PCR[8]
PA[9]
Port B
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
57
Chapter 4 Signal Description
GPIO[16]
CAN0TX
E0UC[30]
LIN0TX
SIUL
FlexCAN_0
eMIOS_0
LINFlex_0
I/O
O
I/O
O
PCR[17]
AF0
AF1
AF2
AF3
—
—
—
GPIO[17]
—
E0UC[31]
—
WKUP[4](4)
CAN0RX
LIN0RX
SIUL
—
eMIOS_0
—
WKUP
FlexCAN_0
LINFlex_0
I/O
—
I/O
—
I
I
I
PB[2]
PCR[18]
AF0
AF1
AF2
AF3
GPIO[18]
LIN0TX
SDA
E0UC[30]
SIUL
LINFlex_0
I2C_0
eMIOS_0
PB[3]
PCR[19]
AF0
AF1
AF2
AF3
—
—
GPIO[19]
E0UC[31]
SCL
—
WKUP[11](4)
LIN0RX
PB[4]
PCR[20]
AF0
AF1
AF2
AF3
—
—
—
PB[5]
PCR[21]
PB[6]
PCR[22]
RESET
config.3
I/O
direction
AF0
AF1
AF2
AF3
Pin number
Pad type2
Function
Peripheral
Table 4-1. Functional port pins (continued)
100
LQFP
144
LQFP
176
LQFP
M
Tristate
23
31
39
S
Tristate
24
32
40
I/O
O
I/O
I/O
M
Tristate
100
144
176
SIUL
eMIOS_0
I2C_0
—
WKUP
LINFlex_0
I/O
I/O
I/O
—
I
I
S
Tristate
1
1
1
—
—
—
—
ADC0_P[0]
ADC1_P[0]
GPIO[20]
—
—
—
—
ADC_0
ADC_1
SIUL
—
—
—
—
I
I
I
I
Tristate
50
72
88
AF0
AF1
AF2
AF3
—
—
—
—
—
—
—
ADC0_P[1]
ADC1_P[1]
GPIO[21]
—
—
—
—
ADC_0
ADC_1
SIUL
—
—
—
—
I
I
I
I
Tristate
53
75
91
AF0
AF1
AF2
AF3
—
—
—
—
—
—
—
ADC0_P[2]
ADC1_P[2]
GPIO[22]
—
—
—
—
ADC_0
ADC_1
SIUL
—
—
—
—
I
I
I
I
Tristate
54
76
92
Port
pin
PCR
Alternate
register function1
PB[0]
PCR[16]
PB[1]
MPC5606BK Microcontroller Reference Manual, Rev. 2
58
Freescale Semiconductor
Chapter 4 Signal Description
—
—
—
—
ADC0_P[3]
ADC1_P[3]
GPIO[23]
—
—
—
—
ADC_0
ADC_1
SIUL
—
—
—
—
I
I
I
PCR[24]
AF0
AF1
AF2
AF3
—
—
—
—
GPIO[24]
—
—
—
OSC32K_XTAL7
WKUP[25]
ADC0_S[0]
ADC1_S[4]
SIUL
—
—
—
OSC32K
WKUP
ADC_0
ADC_1
I
—
—
—
—
I
I
I
PB[9]
PCR[25]
AF0
AF1
AF2
AF3
—
—
—
—
GPIO[25]
—
—
—
OSC32K_EXTAL7
WKUP[26]
ADC0_S[1]
ADC1_S[5]
SIUL
—
—
—
OSC32K
WKUP
ADC_0
ADC_1
PB[10]
PCR[26]
AF0
AF1
AF2
AF3
—
—
—
GPIO[26]
—
—
—
WKUP[8]4
ADC0_S[2]
ADC1_S[6]
PB[11]
PCR[27]
AF0
AF1
AF2
AF3
—
PB[12]
PCR[28]
PB[13]
PCR[29]
RESET
config.3
I/O
direction
AF0
AF1
AF2
AF3
—
—
—
Pin number
Pad type2
Function
Peripheral
Table 4-1. Functional port pins (continued)
100
LQFP
144
LQFP
176
LQFP
I
Tristate
55
77
93
I
—
39
53
61
I
—
—
—
—
I
I
I
I
—
38
52
60
SIUL
—
—
—
WKUP
ADC_0
ADC_1
I/O
—
—
—
I
I
I
J
Tristate
40
54
62
GPIO[27]
E0UC[3]
—
CS0_0
ADC0_S[3]
SIUL
eMIOS_0
—
DSPI_0
ADC_0
I/O
I/O
—
I/O
I
J
Tristate
—
—
97
AF0
AF1
AF2
AF3
—
GPIO[28]
E0UC[4]
—
CS1_0
ADC0_X[0]
SIUL
eMIOS_0
—
DSPI_0
ADC_0
I/O
I/O
—
O
I
J
Tristate
61
83
101
AF0
AF1
AF2
AF3
—
GPIO[29]
E0UC[5]
—
CS2_0
ADC0_X[1]
SIUL
eMIOS_0
—
DSPI_0
ADC_0
I/O
I/O
—
O
I
J
Tristate
63
85
103
Port
pin
PCR
Alternate
register function1
PB[7]
PCR[23]
PB[8]
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
59
Chapter 4 Signal Description
Peripheral
I/O
direction
Pad type2
RESET
config.3
Table 4-1. Functional port pins (continued)
100
LQFP
PB[14]
PCR[30]
AF0
AF1
AF2
AF3
—
GPIO[30]
E0UC[6]
—
CS3_0
ADC0_X[2]
SIUL
eMIOS_0
—
DSPI_0
ADC_0
I/O
I/O
—
O
I
J
Tristate
65
87
105
PB[15]
PCR[31]
AF0
AF1
AF2
AF3
—
GPIO[31]
E0UC[7]
—
CS4_0
ADC0_X[3]
SIUL
eMIOS_0
—
DSPI_0
ADC_0
I/O
I/O
—
O
I
J
Tristate
67
89
107
Port
pin
PCR
Alternate
register function1
Function
Pin number
144
LQFP
176
LQFP
Port C
PC[0]8
PCR[32]
AF0
AF1
AF2
AF3
GPIO[32]
—
TDI
—
SIUL
—
JTAGC
—
I/O
—
I
—
M
Input,
weak
pull-up
87
126
154
PC[1]8
PCR[33]
AF0
AF1
AF2
AF3
GPIO[33]
—
TDO
—
SIUL
—
JTAGC
—
I/O
—
O
—
F9 Tristate
82
121
149
PC[2]
PCR[34]
AF0
AF1
AF2
AF3
—
GPIO[34]
SCK_1
CAN4TX
DEBUG[0]
EIRQ[5]
SIUL
DSPI_1
FlexCAN_4
SSCM
SIUL
I/O
I/O
O
O
I
M
Tristate
78
117
145
PC[3]
PCR[35]
AF0
AF1
AF2
AF3
—
—
—
GPIO[35]
CS0_1
MA[0]
DEBUG[1]
EIRQ[6]
CAN1RX
CAN4RX
SIUL
DSPI_1
ADC_0
SSCM
SIUL
FlexCAN_1
FlexCAN_4
I/O
I/O
O
O
I
I
I
S
Tristate
77
116
144
PC[4]
PCR[36]
AF0
AF1
AF2
AF3
—
—
—
GPIO[36]
E1UC[31]
—
DEBUG[2]
EIRQ[18]
SIN_1
CAN3RX
SIUL
eMIOS_1
—
SSCM
SIUL
DSPI_1
FlexCAN_3
I/O
I/O
—
O
I
I
I
M
Tristate
92
131
159
PC[5]
PCR[37]
AF0
AF1
AF2
AF3
—
GPIO[37]
SOUT_1
CAN3TX
DEBUG[3]
EIRQ[7]
SIUL
DSPI_1
FlexCAN_3
SSCM
SIUL
I/O
O
O
O
I
M
Tristate
91
130
158
MPC5606BK Microcontroller Reference Manual, Rev. 2
60
Freescale Semiconductor
Chapter 4 Signal Description
GPIO[38]
LIN1TX
E1UC[28]
DEBUG[4]
SIUL
LINFlex_1
eMIOS_1
SSCM
I/O
O
I/O
O
PCR[39]
AF0
AF1
AF2
AF3
—
—
GPIO[39]
—
E1UC[29]
DEBUG[5]
LIN1RX
WKUP[12](4)
SIUL
—
eMIOS_1
SSCM
LINFlex_1
WKUP
I/O
—
I/O
O
I
I
PC[8]
PCR[40]
AF0
AF1
AF2
AF3
GPIO[40]
LIN2TX
E0UC[3]
DEBUG[6]
SIUL
LINFlex_2
eMIOS_0
SSCM
PC[9]
PCR[41]
AF0
AF1
AF2
AF3
—
—
GPIO[41]
—
E0UC[7]
DEBUG[7]
WKUP[13](4)
LIN2RX
PC[10] PCR[42]
AF0
AF1
AF2
AF3
PC[11] PCR[43]
RESET
config.3
I/O
direction
AF0
AF1
AF2
AF3
Pin number
Pad type2
Function
Peripheral
Table 4-1. Functional port pins (continued)
100
LQFP
144
LQFP
176
LQFP
S
Tristate
25
36
44
S
Tristate
26
37
45
I/O
O
I/O
O
S
Tristate
99
143
175
SIUL
—
eMIOS_0
SSCM
WKUP
LINFlex_2
I/O
—
I/O
O
I
I
S
Tristate
2
2
2
GPIO[42]
CAN1TX
CAN4TX
MA[1]
SIUL
FlexCAN_1
FlexCAN_4
ADC_0
I/O
O
O
O
M
Tristate
22
28
36
AF0
AF1
AF2
AF3
—
—
—
GPIO[43]
—
—
MA[2]
WKUP[5](4)
CAN1RX
CAN4RX
SIUL
—
—
ADC_0
WKUP
FlexCAN_1
FlexCAN_4
I/O
—
—
O
I
I
I
S
Tristate
21
27
35
PC[12] PCR[44]
AF0
AF1
AF2
AF3
—
—
GPIO[44]
E0UC[12]
—
—
EIRQ[19]
SIN_2
SIUL
eMIOS_0
—
—
SIUL
DSPI_2
I/O
I/O
—
—
I
I
M
Tristate
97
141
173
PC[13] PCR[45]
AF0
AF1
AF2
AF3
GPIO[45]
E0UC[13]
SOUT_2
—
SIUL
eMIOS_0
DSPI_2
—
I/O
I/O
O
—
S
Tristate
98
142
174
PC[14] PCR[46]
AF0
AF1
AF2
AF3
—
GPIO[46]
E0UC[14]
SCK_2
—
EIRQ[8]
SIUL
eMIOS_0
DSPI_2
—
SIUL
I/O
I/O
I/O
—
I
S
Tristate
3
3
3
Port
pin
PCR
Alternate
register function1
PC[6]
PCR[38]
PC[7]
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
61
Chapter 4 Signal Description
AF0
AF1
AF2
AF3
—
GPIO[47]
E0UC[15]
CS0_2
—
EIRQ[20]
RESET
config.3
PC[15] PCR[47]
Function
Pad type2
PCR
Alternate
register function1
I/O
direction
Port
pin
Peripheral
Table 4-1. Functional port pins (continued)
100
LQFP
SIUL
eMIOS_0
DSPI_2
—
SIUL
I/O
I/O
I/O
—
I
M
Tristate
4
4
4
Pin number
144
LQFP
176
LQFP
Port D
PD[0]
PCR[48]
AF0
AF1
AF2
AF3
—
—
—
GPIO[48]
—
—
—
WKUP[27]
ADC0_P[4]
ADC1_P[4]
SIUL
—
—
—
WKUP
ADC_0
ADC_1
I
—
—
—
I
I
I
I
Tristate
41
63
77
PD[1]
PCR[49]
AF0
AF1
AF2
AF3
—
—
—
GPIO[49]
—
—
—
WKUP[28]
ADC0_P[5]
ADC1_P[5]
SIUL
—
—
—
WKUP
ADC_0
ADC_1
I
—
—
—
I
I
I
I
Tristate
42
64
78
PD[2]
PCR[50]
AF0
AF1
AF2
AF3
—
—
GPIO[50]
—
—
—
ADC0_P[6]
ADC1_P[6]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
43
65
79
PD[3]
PCR[51]
AF0
AF1
AF2
AF3
—
—
GPIO[51]
—
—
—
ADC0_P[7]
ADC1_P[7]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
44
66
80
PD[4]
PCR[52]
AF0
AF1
AF2
AF3
—
—
GPIO[52]
—
—
—
ADC0_P[8]
ADC1_P[8]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
45
67
81
PD[5]
PCR[53]
AF0
AF1
AF2
AF3
—
—
GPIO[53]
—
—
—
ADC0_P[9]
ADC1_P[9]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
46
68
82
MPC5606BK Microcontroller Reference Manual, Rev. 2
62
Freescale Semiconductor
Chapter 4 Signal Description
GPIO[54]
—
—
—
ADC0_P[10]
ADC1_P[10]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
PCR[55]
AF0
AF1
AF2
AF3
—
—
GPIO[55]
—
—
—
ADC0_P[11]
ADC1_P[11]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
PD[8]
PCR[56]
AF0
AF1
AF2
AF3
—
—
GPIO[56]
—
—
—
ADC0_P[12]
ADC1_P[12]
SIUL
—
—
—
ADC_0
ADC_1
PD[9]
PCR[57]
AF0
AF1
AF2
AF3
—
—
GPIO[57]
—
—
—
ADC0_P[13]
ADC1_P[13]
PD[10] PCR[58]
AF0
AF1
AF2
AF3
—
—
PD[11] PCR[59]
RESET
config.3
I/O
direction
AF0
AF1
AF2
AF3
—
—
Pin number
Pad type2
Function
Peripheral
Table 4-1. Functional port pins (continued)
100
LQFP
144
LQFP
176
LQFP
I
Tristate
47
69
83
I
Tristate
48
70
84
I
—
—
—
I
I
I
Tristate
49
71
87
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
56
78
94
GPIO[58]
—
—
—
ADC0_P[14]
ADC1_P[14]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
57
79
95
AF0
AF1
AF2
AF3
—
—
GPIO[59]
—
—
—
ADC0_P[15]
ADC1_P[15]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I
I
I
Tristate
58
80
96
PD[12] PCR[60]
AF0
AF1
AF2
AF3
—
GPIO[60]
CS5_0
E0UC[24]
—
ADC0_S[4]
SIUL
DSPI_0
eMIOS_0
—
ADC_0
I/O
O
I/O
—
I
J
Tristate
—
—
100
PD[13] PCR[61]
AF0
AF1
AF2
AF3
—
GPIO[61]
CS0_1
E0UC[25]
—
ADC0_S[5]
SIUL
DSPI_1
eMIOS_0
—
ADC_0
I/O
I/O
I/O
—
I
J
Tristate
62
84
102
Port
pin
PCR
Alternate
register function1
PD[6]
PCR[54]
PD[7]
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
63
Chapter 4 Signal Description
Peripheral
I/O
direction
Pad type2
RESET
config.3
Table 4-1. Functional port pins (continued)
100
LQFP
PD[14] PCR[62]
AF0
AF1
AF2
AF3
—
GPIO[62]
CS1_1
E0UC[26]
—
ADC0_S[6]
SIUL
DSPI_1
eMIOS_0
—
ADC_0
I/O
O
I/O
—
I
J
Tristate
64
86
104
PD[15] PCR[63]
AF0
AF1
AF2
AF3
—
GPIO[63]
CS2_1
E0UC[27]
—
ADC0_S[7]
SIUL
DSPI_1
eMIOS_0
—
ADC_0
I/O
O
I/O
—
I
J
Tristate
66
88
106
Port
pin
PCR
Alternate
register function1
Function
Pin number
144
LQFP
176
LQFP
Port E
PE[0]
PCR[64]
AF0
AF1
AF2
AF3
—
—
GPIO[64]
E0UC[16]
—
—
WKUP[6](4)
CAN5RX
SIUL
eMIOS_0
—
—
WKUP
FlexCAN_5
I/O
I/O
—
—
I
I
S
Tristate
6
10
18
PE[1]
PCR[65]
AF0
AF1
AF2
AF3
GPIO[65]
E0UC[17]
CAN5TX
—
SIUL
eMIOS_0
FlexCAN_5
—
I/O
I/O
O
—
M
Tristate
8
12
20
PE[2]
PCR[66]
AF0
AF1
AF2
AF3
—
—
GPIO[66]
E0UC[18]
—
—
EIRQ[21]
SIN_1
SIUL
eMIOS_0
—
—
SIUL
DSPI_1
I/O
I/O
—
—
I
I
M
Tristate
89
128
156
PE[3]
PCR[67]
AF0
AF1
AF2
AF3
GPIO[67]
E0UC[19]
SOUT_1
—
SIUL
eMIOS_0
DSPI_1
—
I/O
I/O
O
—
M
Tristate
90
129
157
PE[4]
PCR[68]
AF0
AF1
AF2
AF3
—
GPIO[68]
E0UC[20]
SCK_1
—
EIRQ[9]
SIUL
eMIOS_0
DSPI_1
—
SIUL
I/O
I/O
I/O
—
I
M
Tristate
93
132
160
PE[5]
PCR[69]
AF0
AF1
AF2
AF3
GPIO[69]
E0UC[21]
CS0_1
MA[2]
SIUL
eMIOS_0
DSPI_1
ADC_0
I/O
I/O
I/O
O
M
Tristate
94
133
161
PE[6]
PCR[70]
AF0
AF1
AF2
AF3
—
GPIO[70]
E0UC[22]
CS3_0
MA[1]
EIRQ[22]
SIUL
eMIOS_0
DSPI_0
ADC_0
SIUL
I/O
I/O
O
O
I
M
Tristate
95
139
167
MPC5606BK Microcontroller Reference Manual, Rev. 2
64
Freescale Semiconductor
Chapter 4 Signal Description
GPIO[71]
E0UC[23]
CS2_0
MA[0]
EIRQ[23]
SIUL
eMIOS_0
DSPI_0
ADC_0
SIUL
I/O
I/O
O
O
I
PCR[72]
AF0
AF1
AF2
AF3
GPIO[72]
CAN2TX
E0UC[22]
CAN3TX
SIUL
FlexCAN_2
eMIOS_0
FlexCAN_3
I/O
O
I/O
O
PE[9]
PCR[73]
AF0
AF1
AF2
AF3
—
—
—
GPIO[73]
—
E0UC[23]
—
WKUP[7](4)
CAN2RX
CAN3RX
SIUL
—
eMIOS_0
—
WKUP
FlexCAN_2
FlexCAN_3
PE[10]
PCR[74]
AF0
AF1
AF2
AF3
—
GPIO[74]
LIN3TX
CS3_1
E1UC[30]
EIRQ[10]
PE[11]
PCR[75]
AF0
AF1
AF2
AF3
—
—
PE[12]
PCR[76]
PE[13]
PE[14]
RESET
config.3
I/O
direction
AF0
AF1
AF2
AF3
—
Pin number
Pad type2
Function
Peripheral
Table 4-1. Functional port pins (continued)
100
LQFP
144
LQFP
176
LQFP
M
Tristate
96
140
168
M
Tristate
9
13
21
I/O
—
I/O
—
I
I
I
S
Tristate
10
14
22
SIUL
LINFlex_3
DSPI_1
eMIOS_1
SIUL
I/O
O
O
I/O
I
S
Tristate
11
15
23
GPIO[75]
E0UC[24]
CS4_1
—
LIN3RX
WKUP[14](4)
SIUL
eMIOS_0
DSPI_1
—
LINFlex_3
WKUP
I/O
I/O
O
—
I
I
S
Tristate
13
17
25
AF0
AF1
AF2
AF3
—
—
—
GPIO[76]
—
E1UC[19]10
—
EIRQ[11]
SIN_2
ADC1_S[7]
SIUL
—
eMIOS_1
—
SIUL
DSPI_2
ADC_1
I/O
—
I/O
—
I
I
I
J
Tristate
76
109
133
PCR[77]
AF0
AF1
AF2
AF3
GPIO[77]
SOUT_2
E1UC[20]
—
SIUL
DSPI_2
eMIOS_1
—
I/O
O
I/O
—
S
Tristate
—
103
127
PCR[78]
AF0
AF1
AF2
AF3
—
GPIO[78]
SCK_2
E1UC[21]
—
EIRQ[12]
SIUL
DSPI_2
eMIOS_1
—
SIUL
I/O
I/O
I/O
—
I
S
Tristate
—
112
136
Port
pin
PCR
Alternate
register function1
PE[7]
PCR[71]
PE[8]
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
65
Chapter 4 Signal Description
AF0
AF1
AF2
AF3
GPIO[79]
CS0_2
E1UC[22]
—
RESET
config.3
PCR[79]
Function
Pad type2
PE[15]
PCR
Alternate
register function1
I/O
direction
Port
pin
Peripheral
Table 4-1. Functional port pins (continued)
100
LQFP
SIUL
DSPI_2
eMIOS_1
—
I/O
I/O
I/O
—
M
Tristate
—
113
137
Pin number
144
LQFP
176
LQFP
Port F
PF[0]
PCR[80]
AF0
AF1
AF2
AF3
—
GPIO[80]
E0UC[10]
CS3_1
—
ADC0_S[8]
SIUL
eMIOS_0
DSPI_1
—
ADC_0
I/O
I/O
O
—
I
J
Tristate
—
55
63
PF[1]
PCR[81]
AF0
AF1
AF2
AF3
—
GPIO[81]
E0UC[11]
CS4_1
—
ADC0_S[9]
SIUL
eMIOS_0
DSPI_1
—
ADC_0
I/O
I/O
O
—
I
J
Tristate
—
56
64
PF[2]
PCR[82]
AF0
AF1
AF2
AF3
—
GPIO[82]
E0UC[12]
CS0_2
—
ADC0_S[10]
SIUL
eMIOS_0
DSPI_2
—
ADC_0
I/O
I/O
O
—
I
J
Tristate
—
57
65
PF[3]
PCR[83]
AF0
AF1
AF2
AF3
—
GPIO[83]
E0UC[13]
CS1_2
—
ADC0_S[11]
SIUL
eMIOS_0
DSPI_2
—
ADC_0
I/O
I/O
O
—
I
J
Tristate
—
58
66
PF[4]
PCR[84]
AF0
AF1
AF2
AF3
—
GPIO[84]
E0UC[14]
CS2_2
—
ADC0_S[12]
SIUL
eMIOS_0
DSPI_2
—
ADC_0
I/O
I/O
O
—
I
J
Tristate
—
59
67
PF[5]
PCR[85]
AF0
AF1
AF2
AF3
—
GPIO[85]
E0UC[22]
CS3_2
—
ADC0_S[13]
SIUL
eMIOS_0
DSPI_2
—
ADC_0
I/O
I/O
O
—
I
J
Tristate
—
60
68
PF[6]
PCR[86]
AF0
AF1
AF2
AF3
—
GPIO[86]
E0UC[23]
CS1_1
—
ADC0_S[14]
SIUL
eMIOS_0
DSPI_1
—
ADC_0
I/O
I/O
O
—
I
J
Tristate
—
61
69
PF[7]
PCR[87]
AF0
AF1
AF2
AF3
—
GPIO[87]
—
CS2_1
—
ADC0_S[15]
SIUL
—
DSPI_1
—
ADC_0
I/O
—
O
—
I
J
Tristate
—
62
70
MPC5606BK Microcontroller Reference Manual, Rev. 2
66
Freescale Semiconductor
Chapter 4 Signal Description
GPIO[88]
CAN3TX
CS4_0
CAN2TX
SIUL
FlexCAN_3
DSPI_0
FlexCAN_2
I/O
O
O
O
PCR[89]
AF0
AF1
AF2
AF3
—
—
—
GPIO[89]
E1UC[1]
CS5_0
—
WKUP[22](4)
CAN2RX
CAN3RX
SIUL
eMIOS_1
DSPI_0
—
WKUP
FlexCAN_2
FlexCAN_3
I/O
I/O
O
—
I
I
I
PF[10]
PCR[90]
AF0
AF1
AF2
AF3
GPIO[90]
CS1_0
LIN4TX
E1UC[2]
SIUL
DSPI_0
LINFlex_4
eMIOS_1
PF[11]
PCR[91]
AF0
AF1
AF2
AF3
—
—
GPIO[91]
CS2_0
E1UC[3]
—
WKUP[15](4)
LIN4RX
PF[12]
PCR[92]
AF0
AF1
AF2
AF3
PF[13]
PCR[93]
PF[14]
PF[15]
RESET
config.3
I/O
direction
AF0
AF1
AF2
AF3
Pin number
Pad type2
Function
Peripheral
Table 4-1. Functional port pins (continued)
100
LQFP
144
LQFP
176
LQFP
M
Tristate
—
34
42
S
Tristate
—
33
41
I/O
O
O
I/O
M
Tristate
—
38
46
SIUL
DSPI_0
eMIOS_1
—
WKUP
LINFlex_4
I/O
O
I/O
—
I
I
S
Tristate
—
39
47
GPIO[92]
E1UC[25]
LIN5TX
—
SIUL
eMIOS_1
LINFlex_5
—
I/O
I/O
O
—
M
Tristate
—
35
43
AF0
AF1
AF2
AF3
—
—
GPIO[93]
E1UC[26]
—
—
WKUP[16](4)
LIN5RX
SIUL
eMIOS_1
—
—
WKUP
LINFlex_5
I/O
I/O
—
—
I
I
S
Tristate
—
41
49
PCR[94]
AF0
AF1
AF2
AF3
GPIO[94]
CAN4TX
E1UC[27]
CAN1TX
SIUL
FlexCAN_4
eMIOS_1
FlexCAN_1
I/O
O
I/O
O
M
Tristate
—
102
126
PCR[95]
AF0
AF1
AF2
AF3
—
—
—
GPIO[95]
E1UC[4]
—
—
EIRQ[13]
CAN1RX
CAN4RX
SIUL
eMIOS_1
—
—
SIUL
FlexCAN_1
FlexCAN_4
I/O
I/O
—
—
I
I
I
S
Tristate
—
101
125
Port
pin
PCR
Alternate
register function1
PF[8]
PCR[88]
PF[9]
Port G
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
67
Chapter 4 Signal Description
GPIO[96]
CAN5TX
E1UC[23]
—
SIUL
FlexCAN_5
eMIOS_1
—
I/O
O
I/O
—
PCR[97]
AF0
AF1
AF2
AF3
—
—
GPIO[97]
—
E1UC[24]
—
EIRQ[14]
CAN5RX
SIUL
—
eMIOS_1
—
SIUL
FlexCAN_5
I/O
—
I/O
—
I
I
PG[2]
PCR[98]
AF0
AF1
AF2
AF3
GPIO[98]
E1UC[11]
SOUT_3
—
SIUL
eMIOS_1
DSPI_3
—
PG[3]
PCR[99]
AF0
AF1
AF2
AF3
—
GPIO[99]
E1UC[12]
CS0_3
—
WKUP[17](4)
PG[4] PCR[100]
AF0
AF1
AF2
AF3
PG[5] PCR[101]
RESET
config.3
I/O
direction
AF0
AF1
AF2
AF3
Pin number
Pad type2
Function
Peripheral
Table 4-1. Functional port pins (continued)
100
LQFP
144
LQFP
176
LQFP
M
Tristate
—
98
122
S
Tristate
—
97
121
I/O
I/O
O
—
M
Tristate
—
8
16
SIUL
eMIOS_1
DSPI_3
—
WKUP
I/O
I/O
O
—
I
S
Tristate
—
7
15
GPIO[100]
E1UC[13]
SCK_3
—
SIUL
eMIOS_1
DSPI_3
—
I/O
I/O
I/O
—
M
Tristate
—
6
14
AF0
AF1
AF2
AF3
—
—
GPIO[101]
E1UC[14]
—
—
WKUP[18](4)
SIN_3
SIUL
eMIOS_1
—
—
WKUP
DSPI_3
I/O
I/O
—
—
I
I
S
Tristate
—
5
13
PG[6] PCR[102]
AF0
AF1
AF2
AF3
GPIO[102]
E1UC[15]
LIN6TX
—
SIUL
eMIOS_1
LINFlex_6
—
I/O
I/O
O
—
M
Tristate
—
30
38
PG[7] PCR[103]
AF0
AF1
AF2
AF3
—
—
GPIO[103]
E1UC[16]
E1UC[30]
—
WKUP[20](4)
LIN6RX
SIUL
eMIOS_1
eMIOS_1
—
WKUP
LINFlex_6
I/O
I/O
I/O
—
I
I
S
Tristate
—
29
37
PG[8] PCR[104]
AF0
AF1
AF2
AF3
—
GPIO[104]
E1UC[17]
LIN7TX
CS0_2
EIRQ[15]
SIUL
eMIOS_1
LINFlex_7
DSPI_2
SIUL
I/O
I/O
O
I/O
I
S
Tristate
—
26
34
Port
pin
PCR
Alternate
register function1
PG[0]
PCR[96]
PG[1]
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68
Freescale Semiconductor
Chapter 4 Signal Description
Peripheral
I/O
direction
Pad type2
RESET
config.3
Table 4-1. Functional port pins (continued)
100
LQFP
PG[9] PCR[105]
AF0
AF1
AF2
AF3
—
—
GPIO[105]
E1UC[18]
—
SCK_2
WKUP[21]4
LIN7RX
SIUL
eMIOS_1
—
DSPI_2
WKUP
LINFlex_7
I/O
I/O
—
I/O
I
I
S
Tristate
—
25
33
PG[10] PCR[106]
AF0
AF1
AF2
AF3
—
GPIO[106]
E0UC[24]
E1UC[31]
—
SIN_4
SIUL
eMIOS_0
eMIOS_1
—
DSPI_4
I/O
I/O
I/O
—
I
S
Tristate
—
114
138
PG[11] PCR[107]
AF0
AF1
AF2
AF3
GPIO[107]
E0UC[25]
CS0_4
—
SIUL
eMIOS_0
DSPI_4
—
I/O
I/O
O
—
M
Tristate
—
115
139
PG[12] PCR[108]
AF0
AF1
AF2
AF3
GPIO[108]
E0UC[26]
SOUT_4
—
SIUL
eMIOS_0
DSPI_4
—
I/O
I/O
O
—
M
Tristate
—
92
116
PG[13] PCR[109]
AF0
AF1
AF2
AF3
GPIO[109]
E0UC[27]
SCK_4
—
SIUL
eMIOS_0
DSPI_4
—
I/O
I/O
I/O
—
M
Tristate
—
91
115
PG[14] PCR[110]
AF0
AF1
AF2
AF3
GPIO[110]
E1UC[0]
—
—
SIUL
eMIOS_1
—
—
I/O
I/O
—
—
S
Tristate
—
110
134
PG[15] PCR[111]
AF0
AF1
AF2
AF3
—
GPIO[111]
E1UC[1]
—
—
—
SIUL
eMIOS_1
—
—
—
I/O
I/O
—
—
—
M
Tristate
—
111
135
Port
pin
PCR
Alternate
register function1
Function
Pin number
144
LQFP
176
LQFP
Port H
PH[0] PCR[112]
AF0
AF1
AF2
AF3
—
GPIO[112]
E1UC[2]
—
—
SIN_1
SIUL
eMIOS_1
—
—
DSPI_1
I/O
I/O
—
—
I
M
Tristate
—
93
117
PH[1] PCR[113]
AF0
AF1
AF2
AF3
GPIO[113]
E1UC[3]
SOUT_1
—
SIUL
eMIOS_1
DSPI_1
—
I/O
I/O
O
—
M
Tristate
—
94
118
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Freescale Semiconductor
69
Chapter 4 Signal Description
Peripheral
I/O
direction
Pad type2
RESET
config.3
Table 4-1. Functional port pins (continued)
100
LQFP
PH[2] PCR[114]
AF0
AF1
AF2
AF3
GPIO[114]
E1UC[4]
SCK_1
—
SIUL
eMIOS_1
DSPI_1
—
I/O
I/O
I/O
—
M
Tristate
—
95
119
PH[3] PCR[115]
AF0
AF1
AF2
AF3
GPIO[115]
E1UC[5]
CS0_1
—
SIUL
eMIOS_1
DSPI_1
—
I/O
I/O
I/O
—
M
Tristate
—
96
120
PH[4] PCR[116]
AF0
AF1
AF2
AF3
GPIO[116]
E1UC[6]
—
—
SIUL
eMIOS_1
—
—
I/O
I/O
—
—
M
Tristate
—
134
162
PH[5] PCR[117]
AF0
AF1
AF2
AF3
GPIO[117]
E1UC[7]
—
—
SIUL
eMIOS_1
—
—
I/O
I/O
—
—
S
Tristate
—
135
163
PH[6] PCR[118]
AF0
AF1
AF2
AF3
GPIO[118]
E1UC[8]
—
MA[2]
SIUL
eMIOS_1
—
ADC_0
I/O
I/O
—
O
M
Tristate
—
136
164
PH[7] PCR[119]
AF0
AF1
AF2
AF3
GPIO[119]
E1UC[9]
CS3_2
MA[1]
SIUL
eMIOS_1
DSPI_2
ADC_0
I/O
I/O
O
O
M
Tristate
—
137
165
PH[8] PCR[120]
AF0
AF1
AF2
AF3
GPIO[120]
E1UC[10]
CS2_2
MA[0]
SIUL
eMIOS_1
DSPI_2
ADC_0
I/O
I/O
O
O
M
Tristate
—
138
166
PH[9]8 PCR[121]
AF0
AF1
AF2
AF3
GPIO[121]
—
TCK
—
SIUL
—
JTAGC
—
I/O
—
I
—
S
Input,
weak
pull-up
88
127
155
PH[10]8 PCR[122]
AF0
AF1
AF2
AF3
GPIO[122]
—
TMS
—
SIUL
—
JTAGC
—
I/O
—
I
—
M
Input,
weak
pull-up
81
120
148
PH[11] PCR[123]
AF0
AF1
AF2
AF3
GPIO[123]
SOUT_3
CS0_4
E1UC[5]
SIUL
DSPI_3
DSPI_4
eMIOS_1
I/O
O
I/O
I/O
M
Tristate
—
—
140
PH[12] PCR[124]
AF0
AF1
AF2
AF3
GPIO[124]
SCK_3
CS1_4
E1UC[25]
SIUL
DSPI_3
DSPI_4
eMIOS_1
I/O
I/O
I/O
—
M
Tristate
—
—
141
Port
pin
PCR
Alternate
register function1
Function
Pin number
144
LQFP
176
LQFP
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70
Freescale Semiconductor
Chapter 4 Signal Description
Peripheral
I/O
direction
Pad type2
RESET
config.3
Table 4-1. Functional port pins (continued)
100
LQFP
PH[13] PCR[125]
AF0
AF1
AF2
AF3
GPIO[125]
SOUT_4
CS0_3
E1UC[26]
SIUL
DSPI_4
DSPI_3
eMIOS_1
I/O
O
I/O
—
M
Tristate
—
—
9
PH[14] PCR[126]
AF0
AF1
AF2
AF3
GPIO[126]
SCK_4
CS1_3
E1UC[27]
SIUL
DSPI_4
DSPI_3
eMIOS_1
I/O
I/O
I/O
—
M
Tristate
—
—
10
PH[15] PCR[127]
AF0
AF1
AF2
AF3
GPIO[127]
SOUT_5
—
E1UC[17]
SIUL
DSPI_5
—
eMIOS_1
I/O
O
—
—
M
Tristate
—
—
8
Port
pin
PCR
Alternate
register function1
Function
Pin number
144
LQFP
176
LQFP
Port I
PI[0]
PCR[128]
AF0
AF1
AF2
AF3
GPIO[128]
E0UC[28]
—
—
SIUL
eMIOS_0
—
—
I/O
I/O
—
—
S
Tristate
—
—
172
PI[1]
PCR[129]
AF0
AF1
AF2
AF3
—
—
GPIO[129]
E0UC[29]
—
—
WKUP[24](4)
—
SIUL
eMIOS_0
—
—
WKUP
—
I/O
I/O
—
—
I
—
S
Tristate
—
—
171
PI[2]
PCR[130]
AF0
AF1
AF2
AF3
GPIO[130]
E0UC[30]
—
—
SIUL
eMIOS_0
—
—
I/O
I/O
—
—
S
Tristate
—
—
170
PI[3]
PCR[131]
AF0
AF1
AF2
AF3
—
—
GPIO[131]
E0UC[31]
—
—
WKUP[23](4)
—
SIUL
eMIOS_0
—
—
WKUP
—
I/O
I/O
—
—
I
—
S
Tristate
—
—
169
PI[4]
PCR[132]
AF0
AF1
AF2
AF3
GPIO[132]
E1UC[28]
SOUT_4
—
SIUL
eMIOS_1
DSPI_4
—
I/O
I/O
O
—
S
Tristate
—
—
143
PI[5]
PCR[133]
AF0
AF1
AF2
AF3
GPIO[133]
E1UC[29]
SCK_4
—
SIUL
eMIOS_1
DSPI_4
—
I/O
I/O
I/O
—
S
Tristate
—
—
142
PI[6]
PCR[134]
AF0
AF1
AF2
AF3
GPIO[134]
E1UC[30]
CS0_4
—
SIUL
eMIOS_1
DSPI_4
—
I/O
I/O
I/O
—
S
Tristate
—
—
11
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
71
Chapter 4 Signal Description
Peripheral
I/O
direction
Pad type2
RESET
config.3
Table 4-1. Functional port pins (continued)
100
LQFP
PI[7]
PCR[135]
AF0
AF1
AF2
AF3
GPIO[135]
E1UC[31]
CS1_4
—
SIUL
eMIOS_1
DSPI_4
—
I/O
I/O
I/O
—
S
Tristate
—
—
12
PI[8]
PCR[136]
AF0
AF1
AF2
AF3
—
GPIO[136]
—
—
—
ADC0_S[16]
SIUL
—
—
—
ADC_0
I/O
—
—
—
I
J
Tristate
—
—
108
PI[9]
PCR[137]
AF0
AF1
AF2
AF3
—
GPIO[137]
—
—
—
ADC0_S[17]
SIUL
—
—
—
ADC_0
I/O
—
—
—
I
J
Tristate
—
—
109
PI[10] PCR[138]
AF0
AF1
AF2
AF3
—
GPIO[138]
—
—
—
ADC0_S[18]
SIUL
—
—
—
ADC_0
I/O
—
—
—
I
J
Tristate
—
—
110
PI[11] PCR[139]
AF0
AF1
AF2
AF3
—
—
GPIO[139]
—
—
—
ADC0_S[19]
SIN_3
SIUL
—
—
—
ADC_0
DSPI_3
I/O
—
—
—
I
I
J
Tristate
—
—
111
PI[12] PCR[140]
AF0
AF1
AF2
AF3
—
GPIO[140]
CS0_3
—
—
ADC0_S[20]
SIUL
DSPI_3
—
—
ADC_0
I/O
I/O
—
—
I
J
Tristate
—
—
112
PI[13] PCR[141]
AF0
AF1
AF2
AF3
—
GPIO[141]
CS1_3
—
—
ADC0_S[21]
SIUL
DSPI_3
—
—
ADC_0
I/O
I/O
—
—
I
J
Tristate
—
—
113
PI[14] PCR[142]
AF0
AF1
AF2
AF3
—
—
GPIO[142]
—
—
—
ADC0_S[22]
SIN_4
SIUL
—
—
—
ADC_0
DSPI_4
I/O
—
—
—
I
I
J
Tristate
—
—
76
PI[15] PCR[143]
AF0
AF1
AF2
AF3
—
GPIO[143]
CS0_4
—
—
ADC0_S[23]
SIUL
DSPI_4
—
—
ADC_0
I/O
I/O
—
—
I
J
Tristate
—
—
75
Port
pin
PCR
Alternate
register function1
Function
Pin number
144
LQFP
176
LQFP
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Freescale Semiconductor
Chapter 4 Signal Description
Pad type2
RESET
config.3
Pin number
I/O
direction
Peripheral
Table 4-1. Functional port pins (continued)
100
LQFP
PJ[0]
PCR[144]
AF0
AF1
AF2
AF3
—
GPIO[144]
CS1_4
—
—
ADC0_S[24]
SIUL
DSPI_4
—
—
ADC_0
I/O
I/O
—
—
I
J
Tristate
—
—
74
PJ[1]
PCR[145]
AF0
AF1
AF2
AF3
—
—
GPIO[145]
—
—
—
ADC0_S[25]
SIN_5
SIUL
—
—
——
ADC_0
DSPI_5
I/O
—
—
—
I
I
J
Tristate
—
—
73
PJ[2]
PCR[146]
AF0
AF1
AF2
AF3
—
GPIO[146]
CS0_5
—
—
ADC0_S[26]
SIUL
DSPI_5
—
—
ADC_0
I/O
I/O
—
—
I
J
Tristate
—
—
72
PJ[3]
PCR[147]
AF0
AF1
AF2
AF3
—
GPIO[147]
CS1_5
—
—
ADC0_S[27]
SIUL
DSPI_5
—
—
ADC_0
I/O
I/O
—
—
I
J
Tristate
—
—
71
PJ[4]
PCR[148]
AF0
AF1
AF2
AF3
GPIO[148]
SCK_5
E1UC[18]
—
SIUL
DSPI_5
eMIOS_1
—
I/O
I/O
—
—
M
Tristate
—
—
5
Port
pin
PCR
Alternate
register function1
Function
144
LQFP
176
LQFP
Port J
1
2
3
4
5
6
7
8
Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIUL module.
PCR.PA = 00  AF0; PCR.PA = 01  AF1; PCR.PA = 10  AF2; PCR.PA = 11  AF3. This is intended to
select the output functions; to use one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless
of the values selected in the PCR.PA bitfields. For this reason, the value corresponding to an input only function
is reported as “—”.
See Table 4-2.
The RESET configuration applies during and after reset.
All WKUP pins also support external interrupt capability. See the WKPU chapter of the MPC5606BK
Microcontroller Reference Manual for further details.
NMI has higher priority than alternate function. When NMI is selected, the PCR.AF field is ignored.
“Not applicable” because these functions are available only while the device is booting. See the BAM chapter
of the MPC5606BK Microcontroller Reference Manual for details.
Value of PCR.IBE bit must be 0.
Out of reset all the functional pins except PC[0:1] and PH[9:10] are available to the user as GPIO.
PC[0:1] are available as JTAG pins (TDI and TDO respectively).
PH[9:10] are available as JTAG pins (TCK and TMS respectively).
It is up to the user to configure these pins as GPIO when needed.
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73
Chapter 4 Signal Description
9
PC[1] is a fast/medium pad but is in medium configuration by default. This pad is in Alternate Function 2 mode
after reset which has TDO functionality. The reset value of PCR.OBE is 1, but this setting has no impact as long
as this pad stays in AF2 mode. After configuring this pad as GPIO (PCR.PA = 0), output buffer is enabled as
reset value of PCR.OBE = 1.
10
Not available in 100LQFP package.
Table 4-2. Pad types
Type
Description
F
Fast
I
Input only with analog feature
J
Input/output with analog feature
M
Medium
S
Slow
MPC5606BK Microcontroller Reference Manual, Rev. 2
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Freescale Semiconductor
Chapter 5 Microcontroller Boot
Chapter 5
Microcontroller Boot
This chapter explains the process of booting the microcontroller. The following entities are involved in the
boot process:
• Boot Assist Module (BAM)
• System Status and Configuration Module (SSCM)
• Flash memory boot sectors (see Chapter 30, Flash Memory)
• Memory Management Unit (MMU)
5.1
Boot mechanism
This section describes the configuration required by the user, and the steps performed by the
microcontroller, in order to achieve a successful boot from flash memory or serial download modes.
Two external pins on the microcontroller are latched during reset, and determine whether the
microcontroller boots from flash memory or attempt a serial download via FlexCAN or LINFlex (RS232).
These are:
• FAB (Force Alternate Boot mode) on pin PA[9]
• ABS (Alternate Boot Select) on pin PA[8]
Table 5-1 describes the configuration options.
Table 5-1. Boot mode selection
Mode
FAB pin (PA[9])
ABS pin (PA[8])
Flash memory boot (default mode)
0
X
Serial boot (LINFlex)
1
0
Serial boot (FlexCAN)
1
1
The microcontroller has a weak pulldown on PA[9] and a weak pullup on PA[8]. This means that if nothing
external is connected to these pins, the microcontroller will enter flash memory boot mode by default. In
order to change the boot behavior, you should use external pullup or pulldown resistors on PA[9] and
PA[8]. If there is any external circuitry connected to either pin, you must ensure that this does not interfere
with the expected value applied to the pin at reset. Otherwise, the microcontroller may boot into an
unexpected mode after reset.
The SSCM preforms a lot of the automated boot activity including reading the latched value of the FAB
(PA[9]) pin to determine whether to boot from flash memory or serial boot mode. This is illustrated in
Figure 5-1.
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
75
Chapter 5 Microcontroller Boot
SSCM reads latched
values of PA[8] and
PA[9] pins
FAB = 0
FAB (PA[9]) value?
FAB = 1
ABS = 0
Boot from
flash memory
ABS = 1
ABS (PA[8]) value?
Serial boot
(LINFlex)
Serial boot
(FlexCAN)
Figure 5-1. Boot mode selection
5.1.1
Flash memory boot
In order to successfully boot from flash memory, you must program two 32-bit fields into one of 5 possible
boot blocks as detailed below. The entities to program are:
• 16-bit Reset Configuration Half Word (RCHW), which contains:
— A BOOT_ID field that must be correctly set to 0x5A in order to “validate” the boot sector
• 32-bit reset vector (this is the start address of the user code)
The location and structure of the boot sectors in flash memory are shown in Figure 5-2.
MPC5606BK Microcontroller Reference Manual, Rev. 2
76
Freescale Semiconductor
Chapter 5 Microcontroller Boot
0x0000_0000
Boot sector 0
32 KB
0x0000_8000
Boot sector 1
Boot sector structure
16 KB
0x0000_C000
7 8
Bit 0
0x0
(RCHW)
Boot sector 2
15 16
BOOT_ID
(0x5A)
Reserved
Bit 31
Reserved
16 KB
0x0001_0000
0x4
Boot sector 3
0x8
32 KB
0x0001_8000
32-bit reset vector (points to start address of application code)
Application code (from offset 0x8 and onward)
Boot sector 4
32 KB
Code flash memory
Figure 5-2. Boot sector structure
The RCHW fields are described in Table 5-2.
Table 5-2. RCHW field descriptions
Field
BOOT_ID
Description
Boot identifier.
If BOOT_ID = 0x5A, the boot sector is considered valid and bootable.
The SSCM performs a sequential search of each boot sector (starting at sector 0) for a valid BOOT_ID
within the RCHW. If a valid BOOT_ID is found, the SSCM reads the boot vector address. If a valid
BOOT_ID is not found, the SSCM starts the process of putting the microcontroller into static mode.
Finally, the SSCM sets the e200z0h core instruction pointer to the reset vector address and starts the core
running.
5.1.1.1
Static mode
If no valid BOOT_ID within the RCHW was found, the SSCM sets the CPU core instruction pointer to the
BAM address and the core starts to execute the code to enter static mode as follows:
• The core executes the “wait” instruction, which halts the core.
The sequence is illustrated in Figure 5-3.
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
77
Chapter 5 Microcontroller Boot
SSCM searches flash
boot sectors for valid
BOOT_ID (0x5A)
Yes
Valid
BOOT_ID found?
No
SSCM reads reset
vector address
SSCM transfers
execution to e200z0h core,
which runs BAM code
e200z0h core starts
executing code at
vector address
BAM code executes
wait instruction
System in static mode
(requires reset to recover)
Figure 5-3. Flash memory boot mode sequence
5.1.1.2
Alternate boot sectors
Some applications require an alternate boot sector so that the main boot code can be erased and
reprogrammed in the field. When an alternate boot is needed, you can create two bootable sectors:
• The valid boot sector located at the lowest address is the main boot sector.
• The valid boot sector located at the next available address is the alternate boot sector.
This scheme ensures that there is always one active boot sector even if the main boot sector is erased.
5.1.2
Serial boot mode
Serial boot provides a mechanism to download and then execute code into the microcontroller SRAM.
Code may be downloaded using either FlexCAN or LINFlex (RS232). After the SSCM has detected that
serial boot mode has been requested, execution is transferred to the BAM, which handles all of the serial
boot mode tasks. See Section 5.2, Boot Assist Module (BAM), for more details.
5.1.3
Censorship
Censorship can be enabled to protect the contents of the flash memory from being read or modified. In
order to achieve this, the censorship mechanism controls access to the:
• JTAG debug interface
• Serial boot mode (which could otherwise be used to download and execute code to query or modify
the flash memory)
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To regain access to the flash memory via JTAG or serial boot, a 64-bit password must be correctly entered.
CAUTION
When censorship has been enabled, the only way to regain access is with the
password. If this is forgotten or not correctly configured, then there is no
way back into the device.
Two 64-bit values stored in the shadow flash control the censorship (see Table 30-6 for a full description):
• Nonvolatile Private Censorship Password registers, NVPWD0 and NVPWD1
• Nonvolatile System Censorship Control registers, NVSCC0 and NVSCC1
5.1.3.1
Censorship password registers (NVPWD0 and NVPWD1)
The two private password registers combine to form a 64-bit password that should be programmed to a
value known only by you. After factory test these registers are programmed as shown below:
•
•
NVPWD0 = 0xFEED_FACE
NVPWD1 = 0xCAFE_BEEF
This means that even if censorship was inadvertently enabled by writing to the censorship control registers,
there is an opportunity to get back into the microcontroller using the default private password of
0xFEED_FACE_CAFE_BEEF.
When configuring the private password, each half word (16-bit) must contain at least one 1 and one 0.
Some examples of legal and illegal passwords are shown in Table 5-3:
Table 5-3. Examples of legal and illegal passwords
Legal (valid) passwords
0x0001_0001_0001_0001
0xFFFE_FFFE_FFFE_FFFE
0x1XXX_X2XX_XX4X_XXX8
Illegal (invalid) passwords
0x0000_XXXX_XXXX_XXXX
0xFFFF_XXXX_XXXX_XXXX
In uncensored devices it is possible to download code via LINFlex or FlexCAN (Serial Boot Mode) into
internal SRAM even if the 64-bit private password stored in the flash and provided during the boot
sequence is a password that does not conform to the password rules.
5.1.3.2
Nonvolatile System Censorship Control registers (NVSCC0 and
NVSCC1)
These registers are used together to define the censorship configuration. After factory test these registers
are programmed as shown below, which disables censorship:
• NVSCC0 = 0x55AA_55AA
• NVSCC1 = 0x55AA_55AA
Each 32-bit register is split into an upper and lower 16-bit field. The upper 16 bits (the SC field) are used
to control serial boot mode censorship. The lower 16 bits (the CW field) are used to control flash memory
boot censorship.
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CAUTION
If the contents of the shadow flash memory are erased and the NVSCC0,1
registers are not reprogrammed to a valid value, the microcontroller will be
permanently censored with no way for you to regain access. A
microcontroller in this state cannot be debugged or reflashed.
5.1.3.3
Censorship configuration
The steps to configuring censorship are:
1. Define a valid 64-bit password that conforms to the password rules.
2. Using the table and flow charts below, decide what level of censorship you require and configure
the NVSCC0,1 values.
3. Reprogram the shadow flash memory and NVPWD0,1 and NVSCC0,1 registers with your new
values. A POR is required before these will take effect.
CAUTION
If
(NVSCC0 and NVSCC1 do not match)
or
(Either NVSCC0 or NVSCC1 is not set to 0x55AA)
then the microcontroller will be permanently censored with no way to get
back in.
Table 5-4 shows all the possible modes of censorship. The red shaded areas are to be avoided as these show
the configuration for a device that is permanently locked out. If you wish to enable censorship with a
private password there is only one valid configuration — to modify the CW field in both NVSCC0,1
registers so they match but do not equal 0x55AA. This will allow you to enter the private password in both
serial and flash boot modes.
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Table 5-4. Censorship configuration and truth table
Boot configuration
FAB pin
state
0 (flash
memory
boot)
Serial
censorship
control word
(NVSCCn[SC])
Censorship
control word
(NVSCCn[CW])
Internal flash
memory
state
Uncensored
0xXXXX AND
NVSCC0 ==
NVSCC1
0x55AA AND
NVSCC0 ==
NVSCC1
Enabled
N/A
Private flash memory
password and
censored
0x55AA AND
NVSCC0 ==
NVSCC1
!0x55AA AND
NVSCC0 ==
NVSCC1
Enabled
NVPWD1,0
(SSCM reads
flash memory1)
!0x55AA
!0X55AA
Enabled
N/A
Control options
Censored with no
password access
(lockout)
1 (serial
boot)
Private flash memory
password and
uncensored
Serial
password
OR
NVSCC0 != NVSCC1
0x55AA AND NVSCC0 == NVSCC1
Enabled
NVPWD0,1
(BAM reads
flash memory1)
Private flash memory
password and
censored
0x55AA AND
NVSCC0 ==
NVSCC1
!0x55AA AND
NVSCC0 ==
NVSCC1
Enabled
NVPWD1,0
(SSCM reads
flash memory1)
Public password and
uncensored
!0x55AA AND
NVSCC0 !=
NVSCC1
0X55AA AND
NVSCC0 !=
NVSCC1
Enabled
Public
(0xFEED_FAC
E_CAFE_BEE
F)
Disabled
Public
(0xFEED_FAC
E_CAFE_BEE
F)
Public password and
censored (lockout)
JTAG
password
!0x55AA
OR NVSCC0 != NVSCC1
= Microcontroller permanently locked out
= Not applicable
1
When the SSCM reads the passwords from flash memory, the NVPWD0 and NVPWD1 password order is swapped, so you
have to submit the 64-bit password as {NVPWD1, NVPWD0}.
The flow charts in Figure 5-4 and Figure 5-5 provide a way to quickly check what will happen with
different configurations of the NVSCC0,1 registers as well as detailing the correct way to enter the serial
password. In the password examples, assume the 64-bit password has been programmed into the shadow
flash memory in the order {NVPWD0, NWPWD1} and has a value of 0x01234567_89ABCDEF.
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FAB = 0
(Flash boot mode)
NVSCC0 !=
NVSCC1
?
True
Censored with no
password access
(Locked out)
True
Censored with no
password access
(Locked out)
True
Censored with
private password
over JTAG
False
Both
SC and CW !=
0x55AA
?
False
JTAG password details:
Note:
SC = 0x55AA
CW != 0x55AA
?
Enter password as
{NVPWD1, NVPWD0}
example –
0x89ABCDEF_01234567
False
Uncensored
Figure 5-4. Censorship control in flash memory boot mode
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FAB = 1
(Serial boot mode)
NVSCC0 !=
NVSCC1
?
True
Censored with no
password access
(Locked out)
True
Censored with no
password access
(Locked out)
True
Public password,
Uncensored
True
Flash
(private) password,
Censored
Enter password as
{NVPWD1, NVPWD0}
example –
0x89ABCDEF_01234567
Flash
(private) password,
Uncensored
Enter password as
{NVPWD0, NVPWD1}
example –
0x01234567_89ABCDEF
False
Both
SC and CW !=
0x55AA
?
False
Serial password details:
Note:
CW = 0x55AA
SC != 0x55AA
?
Enter public password
0xFEEDFACE_CAFEBEEF
False
Note:
SC = 0x55AA
CW != 0x55AA
?
False
Figure 5-5. Censorship control in serial boot mode
5.2
Boot Assist Module (BAM)
The BAM consists of a block of ROM at address 0xFFFF_C000 containing VLE firmware. The BAM
provides 2 main functions:
• Manages the serial download (FlexCAN or LINFlex protocols supported) including support for a
serial password if censorship is enabled
• Places the microcontroller into static mode if flash memory boot mode is selected and a valid
BOOT_ID is not located in one of the boot sectors by the SSCM
5.2.1
BAM software flow
Figure 5-6 illustrates the BAM logic flow.
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BAM Entry
0xFFFF_C000
Save default
configuration
Check boot
mode at
SSCM_STATUS[BMODE]
Boot mode valid?
No
Restore default
configuration
STATIC mode
Yes
Download new
code and save in
SRAM
Restore default
configuration
Execute new
code
Figure 5-6. BAM logic flow
The initial (reset) device configuration is saved including the mode and clock configuration. This means
that the serial download software running in the BAM can make changes to the modes and clocking, and
then restore these to the default values before running the newly downloaded application code from the
SRAM.
The SSCM_STATUS[BMODE] field indicates which boot mode is to be executed (see Table 5-5). This
field is only updated during reset.
There are two conditions where the boot mode is not considered valid and the BAM pushes the
microcontroller into static mode after restoring the default configuration:
• BMODE = 011 (flash memory boot mode). This means that the SSCM has been unable to find a
valid BOOT_ID in the boot sectors so has called the BAM
• BMODE = reserved
In static mode a wait instruction is executed to halt the core.
For the FlexCAN and LINFlex serial boot modes, the respective area of BAM code is executed to
download the code to SRAM.
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Table 5-5. SSCM_STATUS[BMODE] values as used by BAM
BMODE value
Corresponding boot mode
000
Reserved
001
FlexCAN_0 serial boot loader
010
LINFlex_0 (RS232 /UART) serial boot loader
011
Flash memory boot mode
100–111
Reserved
After the code has been downloaded to SRAM, the BAM code restores the initial device configuration,
and then transfers execution to the start address of the downloaded code.
5.2.1.1
BAM resources
The BAM uses/initializes the following MCU resources:
• MC_ME and MC_CGM to initialize mode and clock sources
• FlexCAN_0, LINFlex _0 and the respective I/O pins when performing serial boot mode
• SSCM during password check
• SSCM to check the boot mode (see Table 5-5)
• 4–16 MHz fast external crystal oscillator
The system clock is selected directly from the 4–16 MHz fast external crystal oscillator. Thus, the external
oscillator frequency defines the baud rates used for serial download (see Table 5-6).
Table 5-6. Serial boot mode – baud rates
5.2.1.2
FXOSC frequency
(MHz)
LINFlex baud rate
(baud)
CAN bit rate
(bit/s)
fFXOSC
fFXOSC/833
fFXOSC/40
8
9600
200K
12
14400
300K
16
19200
400K
Download and execute the new code
From a high level perspective, the download protocol follows these steps:
1. Send the 64-bit password.
2. Send the start address, size of code to be downloaded (in bytes), and the VLE bit1.
3. Download the code.
Each step must be completed before the next step starts. After the download is complete (the specified
number of bytes is downloaded), the code executes from the start address.
1. Since the device supports only VLE code and not Book E code, this flag is used only for backward compatibility.
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The communication is done in half duplex manner, whereby the transmission from the host is followed by
the microcontroller transmission mirroring the transmission back to the host:
• Host sends data to the microcontroller and waits for a response.
• MCU echoes to host the data received.
• Host verifies if echo is correct:
— If data is correct, the host can continue to send data.
— If data is not correct, the host stops transmission and the microcontroller enters static mode.
All multi-byte data structures are sent with MSB first.
A more detailed description of these steps follows.
5.2.1.3
Censorship mode detection and serial password validation
Before the serial download can commence, the BAM code must determine which censorship mode the
microcontroller is in and which password to use. It does this by reading the PUB and SEC fields in the
SSCM Status Register (see Section 5.3.4.1, System Status Register (SSCM_STATUS)) as shown in
Table 5-7.
Table 5-7. BAM censorship mode detection
SSCM_STATUS register fields
Mode
Password comparison
PUB
SEC
1
0
Uncensored, public password
0xFEED_FACE_CAFE_BEEF
0
0
Uncensored, private password
NVPWD0,1 from flash memory via BAM
0
1
Censored, private password
NVPWD1,0 from flash memory via SSCM
When censorship is enabled, the flash memory cannot be read by application code running in the BAM or
in the SRAM. This means that the private password in the shadow flash memory cannot be read by the
BAM code. In this case the SSCM is used to obtain the private password from the flash memory of the
censored device. When the SSCM reads the private password it inverts the order of {NVPWD0,
NWPWD1} so the password entered over the serial download needs to be {NVPWD1, NVPWD0}.
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BAM tasks
Applicable password
BAM code is being
executed
(serial boot mode)
SSCM_STATUS register
PUB and SEC
bits are read
Public password
mode
?
PUB = 1
?
Is censorship
enabled
?
Yes
Public password,
Uncensored,
BAM can directly
check password
No
SEC = 1
?
Yes
Private password,
Censored,
SSCM needed to
check password
No
Private password,
Uncensored,
BAM can directly
check password
Start serial download
with password
Figure 5-7. BAM censorship mode detection
The first thing to be downloaded is the 64-bit password. If the password does not match the stored
password, then the BAM code pushes the microcontroller into static mode.
The way the password is compared with either the public or private password (depending on mode) varies
depending on whether censorship is enabled as described in the following subsections.
5.2.1.3.1
Censorship disabled (private or public passwords):
1. If the public password is used, the BAM code does a direct comparison between the serial password
and 0xFEED_FACE_CAFE_BEEF.
2. If the private password is used, the BAM code does a direct comparison between the serial
password and the private password in flash memory, {NVPWD0, NVPWD1}.
3. If the password does not match, the BAM code immediately terminates the download and pushes
the microcontroller into static mode.
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5.2.1.3.2
Censorship enabled (private password)
1. Since the flash is secured, the SSCM is required to read the private password.
2. The BAM code writes the serial password to the SSCM_PWCMPH and SSCM_PWCMPL
registers.
3. The BAM code then continues with the serial download (start address, data size, and data) until all
the data has been copied to the SRAM.
4. In the meantime the SSCM has compared the private password in flash with the serial download
password the BAM code wrote into SSCM_PWCMPH and SSCM_PWCMPL.
5. If the SSCM obtains a match in the passwords, the censorship is temporarily disabled (until the
next reset).
6. The SSCM updates the status of the security (SEC) bit to reflect whether the passwords matched
(SEC = 0) or not (SEC = 1)
7. Finally, the BAM code reads SEC. If SEC = 0, execution is transferred to the code in the SRAM.
If SEC = 1, the BAM code forces the microcontroller into static mode.
Figure 5-8 shows this in more detail.
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BAM tasks
SSCM tasks
Censorship enabled,
private password,
BAM running
serial boot mode
Serial password
received
BAM writes received
password to SSCM
registers
If any frame
is received
incorrectly,
BAM code
pushes
device into
static mode
SSCM compares
registers to private
password in flash
Upper 32-bits to
SSCM_PWCMPH
Lower 32-bits to
SSCM_PWCMPL
SSCM_PWCMPH to NVPWD1
SSCM_PWCMPL to NVPWD0
Start address
and data
length received
If passwords match,
un-censor device
until next POR
Data download
received
and copied to SRAM
Update SSCM_STATUS[SEC]
bit with
censorship state
BAM reads
SSCM_STATUS[SEC]
No
BAM code pushes
microcontroller into
static mode
Is SEC bit
cleared
?
Yes
BAM code transfers
execution to user
code in SRAM
Figure 5-8. BAM serial boot mode flow for censorship enabled and private password
With LINFlex, any receive error will result in static mode. With FlexCAN, the host will retransmit data if
there has been no acknowledgment from the microcontroller. However, there could be a situation where
the receiver configuration has an error, which would result in static mode entry.
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NOTE
In a censored device booting with serial boot mode, it is possible to read the
content of the four 32-bit flash memory locations that make up the boot
sector. For example, if the RCHW is stored at address 0x0000_0000, the
reads at address 0x0000_0000, 0x0000_0004, 0x0000_0008, and
0x0000_000C will return a correct value. No other flash memory locations
can be read.
5.2.1.4
Download start address, VLE bit and code size
The next 8 bytes received by the microcontroller contain a 32-bit start address, the VLE mode bit, and a
31-bit code length, as shown in Figure 5-9.
START_ADDRESS[31:16]
START_ADDRESS[15:0]
VLE
CODE_LENGTH[30:16]
CODE_LENGTH[15:0]
Figure 5-9. Start address, VLE bit, and download size in bytes
The VLE bit (Variable Length Instruction) is used to indicate whether the code to be downloaded is Book
VLE or Book III-E. This device family supports only VLE = 1; the bit is used for backward compatibility.
The Start Address defines where the received data will be stored and where the MCU will branch after the
download is finished. The start address is 32-bit word aligned and the 2 least significant bits are ignored
by the BAM code.
NOTE
The start address is configurable, but most not lie within the 0x4000_0000
to 0x4000_00FF address range.
The Length defines how many data bytes have to be loaded.
5.2.1.5
Download data
Each byte of data received is stored in the microcontroller’s SRAM, starting from the address specified in
the previous protocol step.
The address increments until the number of bytes of data received matches the number of bytes specified
by the code length.
Since the SRAM is protected by 32-bit wide Error Correction Code (ECC), the BAM code always writes
bytes into SRAM grouped into 32-bit words. If the last byte received does not fall onto a 32-bit boundary,
the BAM code fills any additional bytes with 0x0.
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Since the ECC on the SRAM has not been initialized (except for the bytes of data that have just been
downloaded), an additional dummy word of 0x0000_0000 is written at the end of the downloaded data
block to avoid any ECC errors during core prefetch.
5.2.1.6
Execute code
The BAM code waits for the last data byte to be received. If the operating mode is censored with a private
password, then the BAM reads the SSCM status register to determine whether the serial password matched
the private password. If there was a password match, then the BAM code restores the initial configuration
and transfers execution to the downloaded code start address in SRAM. If the passwords did not match,
the BAM code forces a static mode entry.
NOTE
The watchdog is disabled at the start of BAM code execution. In the case of
an unexpected issue during BAM code execution, the microcontroller may
be stalled and an external reset required to recover the microcontroller.
5.2.2
5.2.2.1
LINFlex (RS232) boot
Configuration
Boot according to the LINFlex boot mode download protocol (see Section 5.2.2.2, Protocol) is performed
by the LINFlex_0 module in UART (RS232) mode. Pins used are:
• LIN0TX mapped on PB[2]
• LIN0RX mapped on PB[3]
Boot from LINFlex uses the system clock driven by the 4–16 MHz external crystal oscillator (FXOSC).
The LINFlex controller is configured to operate at a baud rate = system clock frequency/833, using an 8-bit
data frame without parity bit and 1 stop bit.
Byte field
Start
bit
D0
D1
D2
D3
D4
D5
D6
D7
Stop
bit
Figure 5-10. LINFlex bit timing in UART mode
5.2.2.2
Protocol
Table 5-8 summarizes the protocol and BAM action during this boot mode.
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Table 5-8. UART boot mode download protocol
Protocol
Host sent message
step
5.2.3
5.2.3.1
BAM response
message
Action
1
64-bit password
(MSB first)
64-bit password
Password checked for validity and compared against
stored password.
2
32-bit store address
32-bit store address
Load address is stored for future use.
3
VLE bit + 31-bit
number of bytes
(MSB first)
VLE bit + 31-bit
number of bytes
(MSB first)
Size of download are stored for future use.
Verify if VLE bit is set to 1
4
8 bits of raw binary
data
8 bits of raw binary
data
8-bit data are packed into a 32-bit word. This word is
saved into SRAM starting from the “Load address”.
“Load address” increments until the number of data
received and stored matches the size as specified in the
previous step.
5
None
None
Branch to downloaded code
FlexCAN boot
Configuration
Boot according to the FlexCAN boot mode download protocol (see Section 5.2.3.2, Protocol) is performed
by the FlexCAN_0 module. Pins used are:
• CAN0TX mapped on PB[0]
• CAN0RX mapped on PB[1]
NOTE
When the serial download via FlexCAN is selected and the device is part of
a CAN network, the serial download may stop unexpectedly if there is any
other traffic on the network. To avoid this situation, ensure that no other
CAN device on the network is active during the serial download process.
Boot from FlexCAN uses the system clock driven by the 4–16 MHz fast external crystal oscillator.
The FlexCAN controller is configured to operate at a baud rate = system clock frequency/40 (see Table 5-6
for examples of baud rate).
It uses the standard 11-bit identifier format detailed in FlexCAN 2.0A specification.
FlexCAN controller bit timing is programmed with 10 time quanta, and the sample point is 2 time quanta
before the end, as shown in Figure 5-11.
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NRZ signal
SYNC_SEG
Time segment 1
Time segment 2
1
time quantum
7
time quanta
2
time quanta
1 bit time
Sample point
Transmit point
1 time quantum = 4 system clock periods
Figure 5-11. FlexCAN bit timing
5.2.3.2
Protocol
Table 5-9 summarizes the protocol and BAM action during this boot mode. All data are transmitted byte
wise.
Table 5-9. FlexCAN boot mode download protocol
Protoco
l
Host sent message
step
BAM response
message
Action
1
CAN ID 0x011 +
64-bit password
CAN ID 0x001 +
64-bit password
Password checked for validity and compared against stored
password
2
CAN ID 0x012 +
32-bit store
address + VLE
bit + 31-bit number of
bytes
CAN ID 0x002 +
Load address is stored for future use.
32-bit store
Size of download are stored for future use.
address + VLE
Verify if VLE bit is set to 1
bit + 31-bit number of
bytes
3
CAN ID 0x013 +
8 to 64 bits of raw
binary data
CAN ID 0x003 +
8 to 64 bits of raw
binary data
8-bit data are packed into 32-bit words. These words are
saved into SRAM starting from the “Load address”.
“Load address” increments until the number of data
received and stored matches the size as specified in the
previous step.
5
None
None
Branch to downloaded code
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5.3
5.3.1
System Status and Configuration Module (SSCM)
Introduction
The primary purpose of the SSCM is to provide information about the current state and configuration of
the system that may be useful for configuring application software and for debug of the system.
On microcontrollers with a separate STANDBY power domain, the System Status block is part of that
domain.
System Status and Configuration Module
RevID
Hardmacro
Core
Logic
Bus
Interface
Peripheral
Bus
Interface
System
Status
Password
Comparator
Figure 5-12. SSCM block diagram
5.3.2
Features
The SSCM includes these features:
• System Configuration and Status
— Memory sizes/status
— Microcontroller Mode and Security Status (including censorship and serial boot information)
— Search Code Flash for bootable sector
— Determine boot vector
• Device identification information (MCU ID registers)
• Debug Status Port enable and selection
• Bus and peripheral abort enable/disable
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5.3.3
Modes of operation
The SSCM operates identically in all system modes.
5.3.4
Memory map and register description
Table 5-10 shows the memory map for the SSCM. Note that all addresses are offsets; the absolute address
may be calculated by adding the specified offset to the base address of the SSCM.
Table 5-10. SSCM memory map
Address offset
Register
Location
0x00
System Status Register (SSCM_STATUS)
on page 95
0x02
System Memory Configuration Register (SSCM_MEMCONFIG)
on page 96
0x04
Reserved
0x06
Error Configuration (SSCM_ERROR)
on page 97
0x08
Debug Status Port Register (SSCM_DEBUGPORT)
on page 98
0x0A
Reserved
0x0C
Password Comparison Register High Word (SSCM_PWCMPH)
on page 99
0x10
Password Comparison Register Low Word (SSCM_PWCMPL)
on page 99
All registers are accessible via 8-bit, 16-bit, or 32-bit accesses. However, 16-bit accesses must be aligned
to 16-bit boundaries, and 32-bit accesses must be aligned to 32-bit boundaries. As an example, the
SSCM_STATUS register is accessible by a 16-bit read/write to address Base + 0x0002, but performing a
16-bit access to Base + 0x0003 is illegal.
5.3.4.1
System Status Register (SSCM_STATUS)
The System Status register is a read-only register that reflects the current state of the system.
Offset:0x00
R
Access: Read
0
1
2
3
4
0
0
0
0
0
0
0
0
0
0
5
6
PUB SEC
7
8
0
9
10
BMODE
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0/1
0/1
0/1
Figure 5-13. System Status Register (SSCM_STATUS)
Table 5-11. SSCM_STATUS allowed register accesses
Access type
8-bit
16-bit
32-bit1
Read
Allowed
Allowed
Allowed
Write
Not allowed
Not allowed
Not allowed
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1
All 32-bit accesses must be aligned to 32-bit addresses (i.e., 0x0, 0x4, 0x8 or 0xC).
Table 5-12. SSCM_STATUS field descriptions
Field
Description
PUB
Public Serial Access Status. This bit indicates whether serial boot mode with public password is
allowed.
1 Serial boot mode with public password is allowed
0 Serial boot mode with private flash memory password is allowed
SEC
Security Status. This bit reflects the current security state of the flash memory.
1 The flash memory is secured.
0 The flash memory is not secured.
BMODE
5.3.4.2
Device Boot Mode
000 Reserved
001 FlexCAN_0 Serial Boot Loader
010 LINFlex_0 Serial Boot Loader
011 Single Chip
100 Reserved
101 Reserved
110 Reserved
111 Reserved
This field is only updated during reset.
System Memory Configuration Register (SSCM_MEMCONFIG)
The System Memory Configuration register is a read-only register that reflects the memory configuration
of the system.
Offset: 0x02
R
Access: Read
0
1
2
3
4
0
0
0
0
0
x
x
x
x
x
5
6
7
8
9
PRSZ
10
11
PVLB
12
13
14
DTSZ
15
DVLD
W
Reset
x
x
x
x
x
1
x
x
x
x
1
Figure 5-14. System Memory Configuration Register (SSCM_MEMCONFIG)
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Table 5-13. SSCM_MEMCONFIG field descriptions
Field
Description
PRSZ
Code Flash Size
10000 128 KB
10001 256 KB
10010 384 KB
10011 512 KB
10101 768 KB
10111 1 MB
11011 1.5 MB
PVLB
Code Flash Available
This bit identifies whether or not the on-chip code Flash is available in the system memory map. The
Flash may not be accessible due to security limitations, or because there is no Flash in the system.
1 Code Flash is available
0 Code Flash is not available
DTSZ
Data Flash Size
0000 No Data Flash
0011 64 KB
DVLD
Data Flash Valid
This bit identifies whether or not the on-chip Data Flash is visible in the system memory map. The Flash
may not be accessible due to security limitations, or because there is no Flash in the system.
1 Data Flash is visible
0 Data Flash is not visible
Table 5-14. SSCM_MEMCONFIG allowed register accesses
Access type
8-bit
16-bit
32-bit
Read
Allowed
Allowed
Allowed
(also reads SSCM_STATUS
register)
Write
Not allowed
Not allowed
Not allowed
5.3.4.3
Error Configuration (SSCM_ERROR)
The Error Configuration register is a read-write register that controls the error handling of the system.
Offset: 0x06
R
Access: Read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
0
0
0
0
0
0
0
0
0
0
0
0
0
0
14
15
PAE RAE
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-15. Error Configuration (SSCM_ERROR)
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Table 5-15. SSCM_ERROR field descriptions
Field
Description
PAE
Peripheral Bus Abort Enable
This bit enables bus aborts on any access to a peripheral slot that is not used on the device. This feature
is intended to aid in debugging when developing application code.
1 Illegal accesses to non-existing peripherals produce a Prefetch or Data Abort exception
0 Illegal accesses to non-existing peripherals do not produce a Prefetch or Data Abort exception
RAE
Register Bus Abort Enable
This bit enables bus aborts on illegal accesses to off-platform peripherals. Illegal accesses are defined
as reads or writes to reserved addresses within the address space for a particular peripheral. This
feature is intended to aid in debugging when developing application code.
1 Illegal accesses to peripherals produce a Prefetch or Data Abort exception
0 Illegal accesses to peripherals do not produce a Prefetch or Data Abort exception
Transfers to Peripheral Bus resources may be aborted even before they reach the Peripheral Bus (that
is, at the PBRIDGE level). In this case, bits PAE and RAE will have no effect on the abort.
Table 5-16. SSCM_ERROR allowed register accesses
5.3.4.4
Access type
8-bit
16-bit
32-bit
Read
Allowed
Allowed
Allowed
Write
Allowed
Allowed
Not allowed
Debug Status Port Register (SSCM_DEBUGPORT)
The Debug Status Port register is used to (optionally) provide debug data on a set of pins.
Offset: 0x08
R
Access: Read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
0
0
0
0
0
0
0
0
0
0
0
0
0
13
14
15
DEBUG_MODE
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-16. Debug Status Port Register (SSCM_DEBUGPORT)
Table 5-17. SSCM_DEBUGPORT field descriptions
Field
Description
DEBUG_MODE Debug Status Port Mode
This field selects the alternate debug functionality for the Debug Status Port.
000 No alternate functionality selected
001 Mode 1 selected
010 Mode 2 selected
011 Mode 3 selected
100 Mode 4 selected
101 Mode 5 selected
110 Mode 6 selected
111 Mode 7 selected
Table 5-18 describes the functionality of the Debug Status Port in each mode.
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Table 5-18. Debug status port modes
Pin
Mode 1
1
1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 6
Mode 7
0
SSCM_STATUS SSCM_STATUS
[0]
[8]
SSCM_MEMCONFI
G[0]
SSCM_MEMCONFI
G[8]
Reserved
Reserved
Reserved
1
SSCM_STATUS SSCM_STATUS
[1]
[9]
SSCM_MEMCONFI
G[1]
SSCM_MEMCONFI
G[9]
Reserved
Reserved
Reserved
2
SSCM_STATUS SSCM_STATUS
[2]
[10]
SSCM_MEMCONFI
G[2]
SSCM_MEMCONFI
G[10]
Reserved
Reserved
Reserved
3
SSCM_STATUS SSCM_STATUS
[3]
[11]
SSCM_MEMCONFI
G[3]
SSCM_MEMCONFI
G[11]
Reserved
Reserved
Reserved
4
SSCM_STATUS SSCM_STATUS
[4]
[12]
SSCM_MEMCONFI
G[4]
SSCM_MEMCONFI
G[12]
Reserved
Reserved
Reserved
5
SSCM_STATUS SSCM_STATUS
[5]
[13]
SSCM_MEMCONFI
G[5]
SSCM_MEMCONFI
G[13]
Reserved
Reserved
Reserved
6
SSCM_STATUS SSCM_STATUS
[6]
[14]
SSCM_MEMCONFI
G[6]
SSCM_MEMCONFI
G[14]
Reserved
Reserved
Reserved
7
SSCM_STATUS SSCM_STATUS
[7]
[15]
SSCM_MEMCONFI
G[7]
SSCM_MEMCONFI
G[15]
Reserved
Reserved
Reserved
All signals are active high, unless otherwise noted
PIN[0..7] referred to in Table 5-18 equates to PC[2..9] (Pad 34..41).
Table 5-19. SSCM_DEBUGPORT allowed register accesses
1
5.3.4.5
Access type
8-bit
16-bit
32-bit1
Read
Allowed
Allowed
Not allowed
Write
Allowed
Allowed
Not allowed
All 32-bit accesses must be aligned to 32-bit addresses (i.e., 0x0, 0x4, 0x8 or 0xC).
Password comparison registers
These registers provide a means for the BAM code to unsecure the device via the SSCM if the password
has been provided via serial download.
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Chapter 5 Microcontroller Boot
Offset: 0x0C
R
Access: Read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
PWD_HI[31:16]
Reset
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
PWD_HI[15:0]
Reset
0
0
0
0
0
0
0
0
0
Figure 5-17. Password Comparison Register High Word (SSCM_PWCMPH)
Offset: 0x10
R
Access: Read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
PWD_LO[31:16]
Reset
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
PWD_LO[15:0]
Reset
0
0
0
0
0
0
0
0
0
Figure 5-18. Password Comparison Register Low Word (SSCM_PWCMPL)
Table 5-20. Password Comparison Register field descriptions
Field
Description
PWD_HI
Upper 32 bits of the password
PWD_LO
Lower 32 bits of the password
Table 5-21. SSCM_PWCMPH/L allowed register accesses
1
Access type
8-bit
16-bit
32-bit1
Read
Allowed
Allowed
Allowed
Write
Not allowed
Not allowed
Allowed
All 32-bit accesses must be aligned to 32-bit addresses (i.e., 0x0, 0x4, 0x8 or 0xC).
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In order to unsecure the device, the password needs to be written as follows: first the upper word to the
SSCM_PWCMPH register, then the lower word to the SSCM_PWCMPL register. The SSCM compares
the 64-bit password entered into the SSCM_PWCMPH / SSCM_PWCMPL registers with the
NVPWM[1,0] private password stored in the shadow flash. If the passwords match then the SSCM
temporarily uncensors the microcontroller.
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——— Clocks and power ———
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Chapter 6 Clock Description
Chapter 6
Clock Description
This chapter describes the clock architectural implementation for MPC5606BK.
6.1
Clock architecture
System clocks are generated from three sources:
• Fast external crystal oscillator 4–16 MHz (FXOSC)
• Fast internal RC oscillator 16 MHz (FIRC)
• Frequency modulated phase locked loop (FMPLL)
Additionally, there are two low power oscillators:
• Slow internal RC oscillator 128 kHz (SIRC)
• Slow external crystal oscillator 32 KHz (SXOSC)
The clock architecture is shown in Figure 6-1.
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Chapter 6 Clock Description
FXOSC
FXOSC_clk
/1 to /32
(4–16 MHz)
FXOSC_clk_div
Core
sys_clk
(e.g. 8 MHz)
Platform
FIRC_clk_div
FIRC_clk
FIRC
/1 to /32
(16 MHz)
System
Clock
(e.g. 16 MHz)
DMA
Selector
FMPLL
FMPLL_clk
(e.g. 64 MHz)
Peripheral
/1 to /16
CGM_AC0_SC
periph_set1_clk
Clock Monitor
Unit
Peripheral
/1 to /16
Reset
Safe
Interrupt
periph_set2_clk
periph_set3_clk
SXOSC_clk
/1 to /32
(32 KHz)
SXOSC_clk_div
Set 2
Peripheral
/1 to /16
SXOSC
Set 1
Set 3
SXOSC_clk_div
FIRC_div
rtc_clk
API/RTC
SIRC
SIRC_clk
/1 to /32
(128 kHz)
SIRC_clk_div
SIRC_clk_div
SIRC_clk
Watchdog
FXOSC_clk
/1, /2, /4, /8
FIRC_clk
FMPLL_clk
CLKOUT
(e.g. 64 MHz)
sys_clk
Selector
CLKOUT
rtc_clk
Figure 6-1. MPC5606BK system clock generation
6.2
Clock gating
The MPC5606BK provides the user with the possibility of gating the clock to the peripherals. Table 6-1
describes for each peripheral the associated gating register address. See the ME_PCTLn section in this
reference manual.
Additionally, peripheral set (1, 2 or 3) frequency can be configured to be an integer (1 to 16) divided
version of the main system clock. See the CGM_SC_DC0 section in this reference manual for details.
Table 6-1. MPC5606BK — Peripheral clock sources
Peripheral
RPP_Z0H Platform
DSPI_n
Register gating address offset
(base = 0xC3FD_C0C0)1
Peripheral set2
none (managed through ME mode)
—
4 + n (n = 0..5)
2
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Table 6-1. MPC5606BK — Peripheral clock sources (continued)
Register gating address offset
(base = 0xC3FD_C0C0)1
Peripheral set2
16 + n (n = 0..5)
2
ADC_0
32
3
ADC_1
33
3
I2C
44
1
48 + n (n = 0..7)
1
CTU
57
3
CANS
60
—
SIUL
68
—
WKUP
69
—
eMIOS_n
72 + n (n = 0..1)
3
RTC/API
91
—
PIT
92
—
CMU
104
—
Peripheral
FlexCAN_n
LINFlex_n
1
2
6.3
See the ME_PCTL section in this reference manual for details.
“—” means undivided system clock.
Fast external crystal oscillator (FXOSC) digital interface
The FXOSC digital interface controls the operation of the 4–16 MHz fast external crystal oscillator
(FXOSC). It holds control and status registers accessible for application.
6.3.1
•
•
•
•
6.3.2
Main features
Oscillator power-down control and status reporting through MC_ME block
Oscillator clock available interrupt
Oscillator bypass mode
Output clock division factors ranging from 1, 2, 3....32
Functional description
The FXOSC circuit includes an internal oscillator driver and an external crystal circuitry. It provides an
output clock that can be provided to the FMPLL or used as a reference clock to specific modules depending
on system needs.
The FXOSC can be controlled by the MC_ME module. The ME_xxx_MC[FXOSCON] bit controls the
powerdown of the oscillator based on the current device mode while ME_GS[S_XOSC] register provides
the oscillator clock available status.
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Chapter 6 Clock Description
After system reset, the oscillator is put into powerdown state, and software has to switch on when required.
Whenever the crystal oscillator is switched on from the off state, the OSCCNT counter starts. When it
reaches the value EOCV[7:0] × 512, the oscillator clock is made available to the system. Also, an interrupt
pending FXOSC_CTL[I_OSC] bit is set. An interrupt is generated if the interrupt mask bit M_OSC is set.
The oscillator circuit can be bypassed by setting FXOSC_CTL[OSCBYP]. This bit can only be set by
software. A system reset is needed to reset this bit. In this bypass mode, the output clock has the same
polarity as the external clock applied on the EXTAL pin and the oscillator status is forced to 1. The bypass
configuration is independent of the powerdown mode of the oscillator.
Table 6-2 shows the truth table of different oscillator configurations.
Table 6-2. Truth table of crystal oscillator
ME_xxx_MC[FXOSCON]
FXOSC_CTL[OSCBYP]
XTAL
EXTAL
FXOSC
Oscillator mode
0
0
No crystal,
High Z
No crystal,
High Z
0
Power down,
IDDQ
x
1
x
Ext clock
EXTAL
Bypass,
OSC disabled
1
0
Crystal
Crystal
EXTAL
Normal,
OSC enabled
Gnd
Ext clock
EXTAL
Normal,
OSC enabled
The FXOSC clock can be further divided by a configurable factor in the range 1 to 32 to generate the
divided clock to match system requirements. This division factor is specified by FXOSC_CTL[OSCDIV]
field.
6.3.3
Register description
Address: 0xC3FE_0000
R
W
RESET:
2
3
4
5
6
7
0
0
0
0
0
0
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
I_OSC2
RESET:
1
OSCBYP1
W
0
M_OSC
R
Access: Special read/write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EOCV
OSCDIV
0
0
0
0
0
0
Figure 6-2. Fast External Crystal Oscillator Control Register (FXOSC_CTL)
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1
2
You can read this field, and you can write a value of 1 to it. Writing a 0 has no effect. A reset will also clear this bit.
You can write a value of “0” or “1” to this field. However, writing a “1” will clear this field, and writing “0” will have no
effect on the field value.
Table 6-3. FXOSC_CTL field descriptions
Field
OSCBYP
EOCV
6.4.1
Crystal Oscillator bypass.
This bit specifies whether the oscillator should be bypassed or not.
0 Oscillator output is used as root clock
1 EXTAL is used as root clock
End of Count Value.
These bits specify the end of count value to be used for comparison by the oscillator stabilization
counter OSCCNT after reset or whenever it is switched on from the off state (OSCCNT runs on the
FXOSC). This counting period ensures that external oscillator clock signal is stable before it can
be selected by the system. When oscillator counter reaches the value EOCV × 512, the crystal
oscillator clock interrupt (I_OSC) request is generated. The OSCCNT counter will be kept under
reset if oscillator bypass mode is selected.
M_OSC
Crystal oscillator clock interrupt mask.
0 Crystal oscillator clock interrupt is masked.
1 Crystal oscillator clock interrupt is enabled.
OSCDIV
Crystal oscillator clock division factor.
This field specifies the crystal oscillator output clock division factor. The output clock is divided by
the factor OSCDIV+1.
I_OSC
6.4
Description
Crystal oscillator clock interrupt.
This bit is set by hardware when OSCCNT counter reaches the count value EOCV × 512.
0 No oscillator clock interrupt occurred.
1 Oscillator clock interrupt pending.
Slow external crystal oscillator (SXOSC) digital interface
Introduction
The SXOSC digital interface controls the operation of the 32 KHz slow external crystal oscillator
(SXOSC). It holds control and status registers accessible for application.
6.4.2
•
•
•
•
6.4.3
Main features
Oscillator powerdown control and status
Oscillator clock available interrupt
Oscillator bypass mode
Output clock division factors ranging from 1 to 32
Functional description
The SXOSC circuit includes an internal oscillator driver and an external crystal circuitry. It can be used as
a reference clock to specific modules depending on system needs.
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Chapter 6 Clock Description
The SXOSC can be controlled via the SXOSC_CTL register. The OSCON bit controls the powerdown
while bit S_OSC provides the oscillator clock available status.
After system reset, the oscillator is put to powerdown state, and software has to switch on when required.
Whenever the SXOSC is switched on from off state, the OSCCNT counter starts. When it reaches the value
EOCV[7:0] × 512, the oscillator clock is made available to the system. Also, an interrupt pending
SXOSC_CTL[I_OSC] bit is set. An interrupt will be generated if the interrupt mask bit M_OSC is set.
The oscillator circuit can be bypassed by writing SXOSC_CTL[OSCBYP] bit to 1. This bit can only be
set by software. A system reset is needed to reset this bit. In this bypass mode, the output clock has the
same polarity as the external clock applied on the OSC32K_EXTAL pin and the oscillator status is forced
to 1. The bypass configuration is independent of the powerdown mode of the oscillator.
Table 6-4 shows the truth table of different configurations of the oscillator.
Table 6-4. SXOSC truth table
SXOSC_CTL fields
OSC32K_XTAL
SXOSC
Oscillator MODE
0
Powerdown, IDDQ
External clock
OSC32K_EXTAL
Bypass, OSC disabled
Crystal
Crystal
OSC32K_EXTAL
Normal, OSC enabled
Ground
External clock
OSC32K_EXTAL
Normal, OSC enabled
OSCON
OSCBYP
0
0
x
1
x
1
0
OSC32K_EXTAL
No crystal, High Z No crystal, High Z
The SXOSC clock can be further divided by a configurable factor in the range 1 to 32 to generate the
divided clock to match system requirements. This division factor is specified by SXOSC_CTL[OSCDIV]
field.
Register description
Address: 0xC3FE_0040
W
RESET:
3
4
5
6
7
0
0
0
0
0
0
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
S_OSC
R
2
I_OSC2
RESET:
1
OSCBYP1
W
0
M_OSC
R
Access: Special read/write
0
0
0
0
0
0
0
0
0
EOCV
OSCDIV
0
0
0
0
0
0
OSCON
6.4.4
0
Figure 6-3. Slow External Crystal Oscillator Control Register (SXOSC_CTL)
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1
2
You can read this field, and you can write a value of 1 to it. Writing a 0 has no effect. A reset will also clear this bit.
You can write a value of “0” or “1” to this field. However, writing a “1” will clear this field, and writing “0” will have no
effect on the field value.
Table 6-5. SXOSC_CTL field descriptions
Field
Description
OSCBYP
EOCV
Crystal Oscillator bypass.
This bit specifies whether the oscillator should be bypassed or not.
0 Oscillator output is used as root clock.
1 OSC32K_EXTAL is used as root clock.
End of Count Value.
This field specifies the end of count value to be used for comparison by the oscillator stabilization
counter OSCCNT after reset or whenever it is switched on from the off state. This counting period
ensures that external oscillator clock signal is stable before it can be selected by the system. When
oscillator counter reaches the value EOCV × 512, the crystal oscillator clock interrupt (I_OSC)
request is generated. The OSCCNT counter will be kept under reset if oscillator bypass mode is
selected.
M_OSC
Crystal oscillator clock interrupt mask.
0 Crystal oscillator clock interrupt is masked.
1 Crystal oscillator clock interrupt is enabled.
OSCDIV
Crystal oscillator clock division factor.
This field specifies the crystal oscillator output clock division factor. The output clock is divided by
the factor OSCDIV + 1.
I_OSC
Crystal oscillator clock interrupt.
This field is set by hardware when OSCCNT counter reaches the count value EOCV × 512.
0 No oscillator clock interrupt occurred.
1 Oscillator clock interrupt pending.
S_OSC
Crystal oscillator status.
0 Crystal oscillator output clock is not stable.
1 Crystal oscillator is providing a stable clock.
OSCON
Crystal oscillator enable.
0 Crystal oscillator is switched off.
1 Crystal oscillator is switched on.
NOTE
The 32 KHz slow external crystal oscillator is by default always ON, but
can be configured OFF in standby by setting the OSCON bit.
6.5
6.5.1
Slow internal RC oscillator (SIRC) digital interface
Introduction
The SIRC digital interface controls the 128 kHz slow internal RC oscillator (SIRC). It holds control and
status registers accessible for application.
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Chapter 6 Clock Description
6.5.2
Functional description
The SIRC provides a low frequency (fSIRC) clock of 128 kHz requiring very low current consumption.
This clock can be used as the reference clock when a fixed base time is required for specific modules.
SIRC is always on in all device modes except STANDBY mode. In STANDBY mode, it is controlled by
SIRC_CTL[SIRCON_STDBY] bit. The clock source status is updated in SIRC_CTL[S_SIRC] bit.
The SIRC clock can be further divided by a configurable division factor in the range from 1 to 32 to
generate the divided clock to match system requirements. This division factor is specified by
SIRC_CTL[SIRCDIV] bits.
The SIRC output frequency can be trimmed using SIRC_CTL[SIRCTRIM]. After a power-on reset, the
SIRC is trimmed using a factory test value stored in test flash memory. However, after a power-on reset
the test flash memory value is not visible at SIRC_CTL[SIRCTRIM], and this field shows a value of zero.
Therefore, be aware that the SIRC_CTL[SIRCTRIM] does not reflect the current trim value until you have
written to this field. Pay particular attention to this feature when you initiate a read-modify-write operation
on SIRC_CTL, because a SIRCTRIM value of 0 may be unintentionally written back, and this may alter
the SIRC frequency. In this case, you should calibrate the SIRC using the CMU or be sure that you only
write to the upper 16 bits of this SIRC_CTL.
In this oscillator, two's complement trimming method is implemented. So the trimming code increases
from –16 to 15. As the trimming code increases, the internal time constant increases and frequency
reduces. Please refer to the device datasheet for average frequency variation of the trimming step.
6.5.3
Register description
Address: 0xC3FE_0080
R
Access: Read/write
0
1
2
3
4
5
6
7
8
9
10
0
0
0
0
0
0
0
0
0
0
0
11
12
13
14
15
SIRCTRIM
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
SIRCDIV
W
RESET:
0
0
0
0
0
0
1
1
SIRCON_STDBY
RESET:
S_SIRC
W
0
Figure 6-4. Low Power RC Control Register (SIRC_CTL)
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Chapter 6 Clock Description
Table 6-6. SIRC_CTL field descriptions
Field
Description
SIRCTRIM
SIRC trimming bits.
This field corresponds (via twos complement) to a trim factor of –16 to +15.
A +1 change in SIRCTRIM decreases the current frequency by SIRCTRIM (see the device data
sheet).
A –1 change in SIRCTRIM increases the current frequency by SIRCTRIM (see the device data
sheet).
SIRCDIV
SIRC clock division factor.
This field specifies the SIRC oscillator output clock division factor. The output clock is divided
by the factor SIRCDIV+1.
S_SIRC
SIRC clock status.
0 SIRC is not providing a stable clock.
1 SIRC is providing a stable clock.
SIRCON_STDBY
6.6
6.6.1
SIRC control in STANDBY mode.
0 SIRC is switched off in STANDBY mode.
1 SIRC is switched on in STANDBY mode.
Fast internal RC oscillator (FIRC) digital interface
Introduction
The FIRC digital interface controls the 16 MHz fast internal RC oscillator (FIRC). It holds control and
status registers accessible for application.
6.6.2
Functional description
The FIRC provides a high frequency (fFIRC) clock of 16 MHz. This clock can be used to accelerate the exit
from reset and wakeup sequence from low power modes of the system. It is controlled by the MC_ME
module based on the current device mode. The clock source status is updated in ME_GS[S_RC]. Please
see Chapter 8, Mode Entry Module (MC_ME), for further details.
The FIRC can be further divided by a configurable division factor in the range from 1 to 32 to generate the
divided clock to match system requirements. This division factor is specified by RC_CTL[RCDIV] bits.
The FIRC output frequency can be trimmed using FIRC_CTL[FIRCTRIM]. After a power-on reset, the
FIRC is trimmed using a factory test value stored in test flash memory. However, after a power-on reset
the test flash memory value is not visible at FIRC_CTL[FIRCTRIM], and this field will show a value of 0.
Therefore, be aware that the FIRC_CTL[FIRCTRIM] field does not reflect the current trim value until you
have written to it. Pay particular attention to this feature when you initiate a read-modify-write operation
on FIRC_CTL, because a FIRCTRIM value of zero may be unintentionally written back and this may alter
the FIRC frequency. In this case, you should calibrate the FIRC using the CMU or ensure that you write
only to the upper 16 bits of this FIRC_CTL.
In this oscillator, two's complement trimming method is implemented. So the trimming code increases
from –32 to 31. As the trimming code increases, the internal time constant increases and frequency
reduces. Please refer to the device datasheet for average frequency variation of the trimming step.
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Chapter 6 Clock Description
During STANDBY mode entry process, the FIRC is controlled based on ME_STANDBY_MC[RCON]
bit. This is the last step in the standby entry sequence. On any system wakeup event, the device exits
STANDBY mode and switches on the FIRC. The actual powerdown status of the FIRC when the device
is in standby is provided by RC_CTL[FIRCON_STDBY] bit.
6.6.3
Register description
Address: 0xC3FE_0060
R
Access: Read/write
0
1
2
3
4
5
6
7
8
9
0
0
0
0
0
0
0
0
0
0
10
11
12
13
14
15
FIRCTRIM
RESET:
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
FIRCON_STDBY
W
0
0
0
0
0
0
0
0
0
0
0
0
0
W
FIRCDIV
RESET:
0
0
0
0
0
0
0
0
Figure 6-5. FIRC Oscillator Control Register (FIRC_CTL)
Table 6-7. FIRC_CTL field descriptions
Field
Description
FIRCTRIM
FIRC trimming bits.
This field corresponds (via twos complement) to a trim factor of –16 to +15.
A +1 change in FIRCTRIM decreases the current frequency by FIRCTRIM (see the device data
sheet).
A –1 change in SIRCTRIM increases the current frequency by FIRCTRIM (see the device data
sheet).
FIRCDIV
FIRC clock division factor.
This field specifies the FIRC oscillator output clock division factor. The output clock is divided by
the factor FIRCDIV+1.
FIRCON_STDB FIRC control in STANDBY mode.
Y
0 FIRC is switched off in STANDBY mode.
1 FIRC is in STANDBY mode.
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Chapter 6 Clock Description
6.7
Frequency-modulated phase-locked loop (FMPLL)
6.7.1
Introduction
This section describes the features and functions of the FMPLL module implemented in the device.
6.7.2
Overview
The FMPLL enables the generation of high speed system clocks from a common 4–16 MHz input clock.
Further, the FMPLL supports programmable frequency modulation of the system clock. The FMPLL
multiplication factor and output clock divider ratio are all software configurable.
MPC5606BK has one FMPLL that can generate the system clock and takes advantage of the FM mode.
NOTE
The user must take care not to program the device with a frequency higher
than allowed (no hardware check).
The FMPLL block diagram is shown in Figure 6-6.
FIRC
FXOSC
CGM_AC0_SC
IDF
BUFFER
Charge
Pump
Low Pass
Filter
PHI
VCO
ODF
NDIV
Loop
Frequency
Divider
Figure 6-6. FMPLL block diagram
6.7.3
Features
The FMPLL has the following major features:
• Input clock frequency 4 MHz – 16 MHz
• Voltage controlled oscillator (VCO) range from 256 MHz to 512 MHz
• Frequency divider (FD) for reduced frequency operation without forcing the FMPLL to relock
• Frequency modulated FMPLL
— Modulation enabled/disabled through software
— Triangle wave modulation
• Programmable modulation depth
— ±0.25% to ±4% deviation from center spread frequency1
— 0.5% to +8% deviation from down spread frequency
— Programmable modulation frequency dependent on reference frequency
• Self-clocked mode (SCM) operation
1. Spread spectrum should be programmed in line with maximum datasheet frequency figures.
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Chapter 6 Clock Description
•
4 available modes
— Normal mode
— Progressive clock switching
— Normal mode with frequency modulation
— Powerdown mode
Memory map1
6.7.4
Table 6-8 shows the memory map of the FMPLL.
Table 6-8. FMPLL memory map
Base address: 0xC3FE_00A0
Address offset
Register
Location
0x0
Control Register (CR)
on page 116
0x4
Modulation Register (MR)
on page 119
6.7.5
Register description
The FMPLL operation is controlled by two registers. Those registers can be accessed and written in
supervisor mode only.
6.7.5.1
Control Register (CR)
Offset: 0x0
R
Access: Supervisor read/write
0
1
0
0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
IDF
ODF
NDIV
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
S_LOCK
PLL_FAIL_FLAG
1
EN_PLL_SW
R
W
Reset
w1c
0
0
0
0
0
0
0
0
0
0
0
0
0
PLL_FAIL_MASK
0
I_LOCK
Reset
UNLOCK_ONCE
W
0
w1c
0
1
Figure 6-7. Control Register (CR)
1. FMPLL_x are mapped through the ME_CGM register slot
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Chapter 6 Clock Description
Table 6-9. CR field descriptions
Field
Description
IDF
The value of this field sets the FMPLL input division factor as described in Table 6-10.
ODF
The value of this field sets the FMPLL output division factor as described in Table 6-11.
NDIV
The value of this field sets the FMPLL loop division factor as described in Table 6-12.
EN_PLL_SW
This bit is used to enable progressive clock switching. After the PLL locks, the PLL output initially
is divided by 8, and then progressively decreases until it reaches divide-by-1.
0 Progressive clock switching disabled.
1 Progressive clock switching enabled.
Note: Progressive clock switching should not be used if a non-changing clock is needed, such
as for serial communications, until the division has finished.
UNLOCK_ONCE This bit is a sticking indication of FMPLL loss of lock condition. UNLOCK_ONCE is set when the
FMPLL loses lock. Whenever the FMPLL reacquires lock, UNLOCK_ONCE remains set. Only a
power-on reset clears this bit.
I_LOCK
This bit is set by hardware whenever there is a lock/unlock event.
S_LOCK
This bit is an indication of whether the FMPLL has acquired lock.
0: FMPLL unlocked
1: FMPLL locked
Note:
PLL_FAIL_MASK This bit is used to mask the pll_fail output.
0 pll_fail not masked.
1 pll_fail masked.
PLL_FAIL_FLAG This bit is asynchronously set by hardware whenever a loss of lock event occurs while FMPLL
is switched on. It is cleared by software writing 1.
Table 6-10. Input divide ratios
IDF[3:0]
Input divide ratios
0000
Divide by 1
0001
Divide by 2
0010
Divide by 3
0011
Divide by 4
0100
Divide by 5
0101
Divide by 6
0110
Divide by 7
0111
Divide by 8
1000
Divide by 9
1001
Divide by 10
1010
Divide by 11
1011
Divide by 12
1100
Divide by 13
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Chapter 6 Clock Description
Table 6-10. Input divide ratios (continued)
IDF[3:0]
Input divide ratios
1101
Divide by 14
1110
Divide by 15
1111
Clock Inhibit
Table 6-11. Output divide ratios
ODF[1:0]
Output divide ratios
00
Divide by 2
01
Divide by 4
10
Divide by 8
11
Divide by 16
Table 6-12. Loop divide ratios
NDIV[6:0]
Loop divide ratios
0000000–0011111
—
0100000
Divide by 32
0100001
Divide by 33
0100010
Divide by 34
...
...
1011111
Divide by 95
1100000
Divide by 96
1100001–1111111
—
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Chapter 6 Clock Description
6.7.5.2
Modulation Register (MR)
Offset: 0x4
RESET:
R
W
RESET:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
SPRD_SEL
STRB_BYPASS
W
0
MOD_PERIOD
FM_EN
R
Access: Supervisor read/write
0
INC_STEP
0
0
0
0
0
0
0
0
Figure 6-8. Modulation Register (MR)
Table 6-13. MR field descriptions
Field
Description
STRB_BYPASS Strobe bypass.
The STRB_BYPASS signal is used to bypass the strobe signal used inside FMPLL to latch the
correct values for control bits (INC_STEP, MOD_PERIOD, and SPRD_SEL).
0 Strobe is used to latch FMPLL modulation control bits
1 Strobe is bypassed. In this case control bits need to be static. The control bits must be changed
only when FMPLL is in powerdown mode.
SPRD_SEL
Spread type selection.
The SPRD_SEL controls the spread type in Frequency Modulation mode.
0 Center SPREAD
1 Down SPREAD
MOD_PERIOD Modulation period.
The MOD_PERIOD field is the binary equivalent of the value modperiod derived from following
formula:
f ref
modperiod = -------------------4  f mod
where:
fref: represents the frequency of the feedback divider
fmod: represents the modulation frequency
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Chapter 6 Clock Description
Table 6-13. MR field descriptions (continued)
Field
FM_EN
INC_STEP
Description
Frequency Modulation Enable. The FM_EN enables the frequency modulation.
0 Frequency modulation disabled
1 Frequency modulation enabled
Increment step.
The INC_STEP field is the binary equivalent of the value incstep derived from following formula:
15
 2 – 1   md  MDF
incstep = round  ---------------------------------------------------------------
 100  5  MODPERIOD
where:
md: represents the peak modulation depth in percentage (Center spread — pk-pk = ±md,
Downspread — pk-pk = –2 × md)
MDF: represents the nominal value of loop divider (CR[NDIV])
6.7.6
6.7.6.1
Functional description
Normal mode
In Normal Mode the FMPLL inputs are driven by the CR. This means that, when the FMPLL is in lock
state, the FMPLL output clock (PHI) is derived by the reference clock (CLKIN) through this relation:
clkin  NDIV
phi = ---------------------------------IDF  ODF
where the value of IDF, NDIV, and ODF are set in the CR and can be derived from Table 6-10, Table 6-11,
and Table 6-12.
Table 6-14. FMPLL lookup table
Crystal frequency
(MHz)
FMPLL output
frequency (MHz)
8
16
40
CR field values
VCO frequency (MHz)
IDF
ODF
NDIV
32
0
2
32
256
64
0
2
64
512
80
0
1
40
320
32
1
2
32
256
64
1
2
64
512
80
1
1
40
320
32
4
2
32
256
64
4
2
64
512
80
3
1
32
320
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Chapter 6 Clock Description
6.7.6.2
Progressive clock switching
Progressive clock switching allows to switch the system clock to FMPLL output clock stepping through
different division factors. This means that the current consumption gradually increases and, in turn, voltage
regulator response is improved.
This feature can be enabled by programming CR[EN_PLL_SW] bit. When enabled, the system clock is
switched to divided PHI. The FMPLL_clk divider is then progressively decreased to the target divider as
shown in Table 6-15.
Table 6-15. Progressive clock switching on pll_select rising edge
Number of FMPLL output clock cycles
FMPLL_clk frequency
(FMPLL output clock frequency)
8
(FMPLL output clock frequency)/8
16
(FMPLL output clock frequency)/4
32
(FMPLL output clock frequency)/2
onward
FMPLL output clock frequency
FMPLL output clock
Division factors of 8, 4, 2 or 1
FMPLL_clk
Figure 6-9. FMPLL output clock division flow during progressive switching
6.7.6.3
Normal mode with frequency modulation
The FMPLL default mode is without frequency modulation enabled. When frequency modulation is
enabled, however, two parameters must be set to generate the desired level of modulation: the PERIOD
and the STEP. The modulation waveform is always a triangle wave and its shape is not programmable.
FM mode is activated in two steps:
1. Configure the FM mode characteristics: MOD_PERIOD, INC_STEP.
2. Enable the FM mode by programming bit FM_EN of the MR to 1. FM mode can only be enabled
when FMPLL is in lock state.
There are two ways to latch these values inside the FMPLL, depending on the value of bit STRB_BYPASS
in the MR.
If STRB_BYPASS is low, the modulation parameters are latched in the FMPLL only when the strobe
signal goes high for at least two cycles of CLKIN clock. The strobe signal is automatically generated in
the FMPLL digital interface when the modulation is enabled (FM_EN goes high) if the FMPLL is locked
(S_LOCK = 1), or when the modulation has been enabled (FM_EN = 1) and FMPLL enters lock state
(S_LOCK goes high).
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Chapter 6 Clock Description
If STRB_BYPASS is high, the strobe signal is bypassed. In this case, control bits (MOD_PERIOD[12:0],
INC_STEP[14:0], SPREAD_CONTROL) need to be static or hardwired to constant values. The control
bits must be changed only when the FMPLL is in powerdown mode.
The modulation depth in % is
100  5  INCSTEPxMODPERIOD
ModulationDepth =  -------------------------------------------------------------------------------------------15


 2 – 1   MDF
NOTE
The user must ensure that the product of INCTEP and MODPERIOD is less
than (215 – 1).
Figure 6-10. Frequency modulation
6.7.6.4
Powerdown mode
To reduce consumption, the FMPLL can be switched off when not required by programming the registers
ME_x_MC on the MC_ME module.
6.7.7
Recommendations
To avoid any unpredictable behavior of the FMPLL clock, it is recommended to follow these guidelines:
• The FMPLL VCO frequency should reside in the range 256 MHz to 512 MHz. Care is required
when programming the multiplication and division factors to respect this requirement.
• Once the PLL has been locked, only the output divider can be changed.
• Use PLL progressive clock switching to ramp system clock (/8, /4, /2, /1) automatically for the case
when PLL is enabled and selected as system clock.
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Chapter 6 Clock Description
•
6.8
6.8.1
MOD_PERIOD, INC_STEP, SPREAD_SEL bits should be modified before activating the FM
mode. Then strobe has to be generated to enable the new settings. If STRB_BYP is set to 1 then
MOD_PERIOD, INC_STEP, and SPREAD_SEL can be modified only when FMPLL is in
powerdown mode.
Clock monitor unit (CMU)
Introduction
The Clock Monitor Unit (CMU), also referred to as Clock Quality Checker or Clock Fault Detector, serves
two purposes. The main task is to permanently supervise the integrity of the various clock sources, for
example a crystal oscillator or FMPLL. In case the FMPLL leaves an upper or lower frequency boundary
or the crystal oscillator fails it can detect and forward these kind of events to the MC_ME and the
MC_CGM. The clock management unit in turn can then switch to a SAFE mode where it uses the default
safe clock source (FIRC), resets the device, or generates the interrupt according to the system needs.
It can also monitor the external crystal oscillator clock, which must be greater than the internal RC clock
divided by a division factor given by CMU_CSR[RCDIV], and generates a system clock transition request
or an interrupt when enabled.
The second task of the CMU is to provide a frequency meter, which allows to measure the frequency of
one clock source vs. a reference clock. This is useful to allow the calibration of the on-chip RC
oscillator(s), as well as being able to correct/calculate the time deviation of a counter that is clocked by the
RC oscillator.
6.8.2
•
•
•
•
Main features
FIRC, SIRC, SXOSC oscillator frequency measurement using FXOSC as reference clock
External oscillator clock monitoring with respect to FIRC_clk/n clock
FMPLL clock frequency monitoring for a high and low frequency range with FIRC as reference
clock
Event generation for various failures detected inside monitoring unit
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Chapter 6 Clock Description
6.8.3
Block diagram
CKSEL1[1:0]
FIRC_clk
CMU_MDR
00
SIRC_clk
01
SXOSC_clk
10
FIRC_clk
11
FXOSC_clk
MUX1
Frequency Meter
CMU_FDR
OLR_evt
XOSC Supervisor
FXOSC < FIRC / n
XXOSC ON/OFF
From MC_ME
CMU_HFREFR
FMPLL > hfref
OR
FMPLL < lfref
FMPLL
FHH_FLL_OR_evt_a
FMPLL ON/OFF
From MC_ME
CMU_LFREFR
FMPLL Supervisor
OLR_evt : It is the event signalling XOSC failure when asserted. When this signal is asserted, RGM may generate reset, interrupt
or SAFE request based on the RGM configuration.
FHH_FLL_OR_evt_a : It is the event signalling FMPLL failure when asserted. Based on the CMU_HFREFR and CMU_LFREFR
configuration, if the FMPLL is greater than hign frequency range or less than the low frequency range configuration, this signal is
generated. When this signal is asserted, RGM may generate reset, interrupt or SAFE request based on the RGM configuration.
Figure 6-11. Clock Monitor Unit diagram
6.8.4
Functional description
The clock and frequency names referenced in this block are defined as follows:
• FXOSC_clk: clock coming from the fast external crystal oscillator
• SXOSC_clk: clock coming from the slow external crystal oscillator
• SIRC_clk: clock coming from the slow (low frequency) internal RC oscillator
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Chapter 6 Clock Description
•
•
•
•
•
•
•
FIRC_clk: clock coming from the fast (high frequency) internal RC oscillator
FMPLL_clk: clock coming from the FMPLL
fFXOSC_clk: frequency of fast external crystal oscillator clock
fSXOSC_clk: frequency of slow external crystal oscillator clock
fSIRC_clk: frequency of slow (low frequency) internal RC oscillator
fFIRC_clk: frequency of fast (high frequency) internal RC oscillator
fFMPLL_clk: frequency of FMPLL clock
6.8.4.1
Crystal clock monitor
If fFXOSC_clk is less than fFIRC_clk divided by 2RCDIV bits of the CMU_CSR and the FXOSC_clk is ON as
signaled by the MC_ME, then:
• An event pending bit OLRI in CMU_ISR is set.
• A failure event OLR is signaled to the MC_RGM, which in turn can automatically switch to a safe
fallback clock and generate an interrupt or reset.
NOTE
Functional FXOSC monitoring can only be guaranteed when the FXOSC
frequency is greater than (FIRC / 2RCDIV) + 0.5 MHz.
6.8.4.2
FMPLL clock monitor
The fFMPLL_clk can be monitored by programming bit CME of the CMU_CSR register to 1. The
FMPLL_clk monitor starts as soon as bit CME is set. This monitor can be disabled at any time by writing
bit CME to 0.
If fFMPLL_clk is greater than a reference value determined by bits HFREF[11:0] of the CMU_HFREFR and
the FMPLL_clk is ON, as signaled by the MC_ME, then:
• An event pending bit FHHI in CMU_ISR is set.
• A failure event is signaled to the MC_RGM, which in turn can generate an interrupt or safe mode
request or functional reset, depending on the programming model.
If fFMPLL_clk is less than a reference value determined by bits LFREF[11:0] of the CMU_LFREFR and the
FMPLL_clk is ON, as signaled by the MC_ME, then:
• An event pending bit FLLI in CMU_ISR is set.
• A failure event FLL is signaled to the MC_RGM, which in turn can generate an interrupt or safe
mode request or functional reset, depending on the programming model.
NOTE
Functional FMPLL monitoring can only be guaranteed when the FMPLL
frequency is greater than (FIRC / 4) + 0.5 MHz.
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Chapter 6 Clock Description
NOTE
The internal RC oscillator is used as reliable reference clock for the clock
supervision. In order to avoid false events, proper programming of the
dividers is required. These have to take into account the accuracy and
frequency deviation of the internal RC oscillator.
NOTE
If PLL frequency goes out of range, the CMU shall generate FMPLL fll/fhh
event. It takes approximately 5 s to generate this event.
6.8.4.3
Frequency meter
The purpose of the frequency meter is twofold:
• To measure the frequency of the oscillators SIRC, FIRC or SXOSC
• To calibrate an internal RC oscillator (SIRC or FIRC) using a known frequency
Hint: This value can then be stored into the flash so that application software can reuse it later on.
The reference clock is always the FXOSC_clk. The frequency meter returns a precise value of frequencies
fSXOSC_clk, fFIRC_clk or fSIRC_clk according to CKSEL1 bit value. The measure starts when bit SFM (Start
Frequency Measure) in the CMU_CSR is set to 1. The measurement duration is given by the CMU_MDR
in numbers of clock cycles of the selected clock source with a width of 20 bits. Bit SFM is reset to 0 by
hardware once the frequency measurement is done, and the count is loaded in the CMU_FDR. The
frequency fx1 can be derived from the value loaded in the CMU_FDR as follows:
fx = (fFXOSC × MD) / n
Eqn. 6-1
where n is the value in the CMU_FDR and MD is the value in the CMU_MDR.
The frequency meter by default evaluates fFIRC_clk, but software can swap to fSIRC_clk or fSXOSC_clk by
programming the CKSEL bits in the CMU_CSR.
6.8.5
Memory map and register description
The memory map of the CMU is shown in Table 6-16.
Table 6-16. CMU memory map
Base address: 0xC3FE_0100
Register name
Address offset
Reset value
Location
Control Status Register (CMU_CSR)
0x00
0x00000006
on page 127
Frequency Display Register (CMU_FDR)
0x04
0x00000000
on page 128
High Frequency Reference Register FMPLL (CMU_HFREFR)
0x08
0x00000FFF on page 128
Low Frequency Reference Register FMPLL (CMU_LFREFR)
0x0C
0x00000000
on page 129
Interrupt Status Register (CMU_ISR)
0x10
0x00000000
on page 129
1. x = FIRC,SIRC or SXOSC
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Chapter 6 Clock Description
Table 6-16. CMU memory map (continued)
Base address: 0xC3FE_0100
Register name
Address offset
Reset value
Location
Reserved
0x14
0x00000000
—
Measurement Duration Register (CMU_MDR)
0x18
0x00000000
on page 130
Control Status Register (CMU_CSR)
R
Access: Read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
SFM1
Offset: 0x00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
CKSEL1
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
RCDIV
CME_A
6.8.5.1
1
0
1
Figure 6-12. Control Status Register (CMU_CSR)
1
You can read this field, and you can write a value of “1” to it. Writing a “0” has no effect. A reset will also clear this bit.
Table 6-17. CMU_CSR field descriptions
Field
Description
SFM
Start frequency measure.
The software can only set this bit to start a clock frequency measure. It is reset by hardware when
the measure is ready in the CMU_FDR register.
0 Frequency measurement completed or not yet started.
1 Frequency measurement not completed.
CKSEL1
Clock oscillator selection bit.
CKSEL1 selects the clock to be measured by the frequency meter.
00 FIRC_clk selected.
01 SIRC_clk selected.
10 SXOSC_clk selected.
11 FIRC_clk selected.
RCDIV
RC clock division factor.
These bits specify the RC clock division factor. The output clock is FIRC_clk divided by the factor
2RCDIV. This output clock is used to compare with FXOSC_clk for crystal clock monitor feature.The
clock division coding is as follows.
00 Clock divided by 1 (No division)
01 Clock divided by 2
10 Clock divided by 4
11 Clock divided by 8
CME_A
FMPLL_0 clock monitor enable.
0 FMPLL_0 monitor disabled.
1 FMPLL_0 monitor enabled.
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Chapter 6 Clock Description
6.8.5.2
Frequency Display Register (CMU_FDR)
Offset: 0x04
Access: Read-only
0
1
2
3
4
5
6
7
8
9
10
11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
12
13
14
15
FD[19:16]
W
Reset
R
FD[15:0]
W
Reset
0
0
0
0
0
0
0
0
0
Figure 6-13. Frequency Display Register (CMU_FDR)
.
Table 6-18. CMU_FDR field descriptions
Field
Description
FD
Measured frequency bits.
This register shows the measured frequency fx with respect to fFXOSC. The measured value is given
by the following formula: fx = (fFXOSC × MD) / n, where n is the value in CMU_FDR register.
Note: x = FIRC, SIRC or SXOSC.
6.8.5.3
High Frequency Reference Register FMPLL (CMU_HFREFR)
Offset: 0x08
Access: Read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
1
1
1
1
1
R
W
Reset
R
HFREF
W
Reset
1
1
1
1
1
1
1
Figure 6-14. High Frequency Reference Register FMPLL (CMU_HFREFR)
Table 6-19. CMU_HFREFR field descriptions
Field
Description
HFREF
High Frequency reference value.
This field determines the high reference value for the FMPLL clock. The reference value is given by:
(HFREF  16) × (fFIRC  4).
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Chapter 6 Clock Description
6.8.5.4
Low Frequency Reference Register FMPLL (CMU_LFREFR)
Offset: 0x0C
R
Access: Read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
LFREF
W
Reset
0
0
0
0
0
0
0
Figure 6-15. Low Frequency Reference Register FMPLL (CMU_LFREFR)
Table 6-20. CMU_LFREFR field descriptions
Field
Description
LFREF
6.8.5.5
Low Frequency reference value.
This field determines the low reference value for the FMPLL. The reference value is given by:
(LFREF  16) × (fFIRC  4).
Interrupt Status Register (CMU_ISR)
Offset: 0x10
R
Access: Read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
OLRI
R
FLLI
Reset
FHHI
W
w1c
w1c
w1c
0
0
0
Figure 6-16. Interrupt status register (CMU_ISR)
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Chapter 6 Clock Description
Table 6-21. CMU_ISR field descriptions
Field
Description
FHHI
FMPLL clock frequency higher than high reference interrupt.
This bit is set by hardware when fFMPLL_clk becomes higher than HFREF value and FMPLL_clk is ON
as signaled by the MC_ME. It can be cleared by software by writing 1.
0 No FHH event.
1 FHH event is pending.
FLLI
FMPLL clock frequency lower than low reference event.
This bit is set by hardware when fFMPLL_clk becomes lower than LFREF value and FMPLL_clk is ON
as signaled by the MC_ME. It can be cleared by software by writing 1.
0 No FLL event.
1 FLL event is pending.
OLRI
Oscillator frequency lower than RC frequency event.
This bit is set by hardware when fFXOSC_clk is lower than FIRC_clk/2RCDIV frequency and FXOSC_clk
is ON as signaled by the MC_ME. It can be cleared by software by writing 1.
0 No OLR event.
1 OLR event is pending.
6.8.5.6
Measurement Duration Register (CMU_MDR)
Offset: 0x18
R
Access: Read/write
0
1
2
3
4
5
6
7
8
9
10
11
0
0
0
0
0
0
0
0
0
0
0
0
12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
15
MD[15:0]
W
Reset
14
MD[19:16]
W
Reset
13
0
0
0
0
0
0
0
0
0
Figure 6-17. Measurement Duration Register (CMU_MDR)
Table 6-22. CMU_MDR field descriptions
Field
Description
MD
Measurement duration bits.
This field shows the measurement duration in numbers of clock cycles of the selected clock source.
This value is loaded in the frequency meter downcounter. When CMU_CSR[SFM] = 1, the
downcounter starts counting.
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Chapter 7 Clock Generation Module (MC_CGM)
Chapter 7
Clock Generation Module (MC_CGM)
7.1
Overview
The clock generation module (MC_CGM) generates reference clocks for all SoC blocks. The MC_CGM
selects one of the system clock sources to supply the system clock. The MC_ME controls the system clock
selection (see Chapter 8, Mode Entry Module (MC_ME), for more details). A set of MC_CGM registers
controls the clock dividers, which are utilized for divided system and peripheral clock generation. The
memory spaces of system and peripheral clock sources that have addressable memory spaces are accessed
through the MC_CGM memory space. The MC_CGM also selects and generates an output clock.
Figure 7-1 shows the MC_CGM block diagram.
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Chapter 7 Clock Generation Module (MC_CGM)
MC_CGM
FIRC
MC_ME
FXOSC
Registers
Platform Interface
MC_RGM
FMPLL
System Clock
Multiplexer/Divider
peripherals
PA[0]
core
Mapped Modules Interface
Output Clock
Selector/Divider
mapped
peripherals
Figure 7-1. MC_CGM block diagram
7.2
Features
The MC_CGM includes the following features:
• Generates system and peripheral clocks
• Selects and enables/disables the system clock supply from system clock sources according to
MC_ME control
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Chapter 7 Clock Generation Module (MC_CGM)
•
•
•
•
•
7.3
Contains a set of registers to control clock dividers for divided clock generation
Supports multiple clock sources and maps their address spaces to its memory map
Generates an output clock
Guarantees glitchless clock transitions when changing the system clock selection
Supports 8-, 16-, and 32-bit wide read/write accesses
Modes of operation
This section describes the basic functional modes of the MC_CGM.
7.3.1
Normal and reset modes of operation
During normal and reset modes of operation, the clock selection for the system clock is controlled by the
MC_ME.
7.4
External signal description
The MC_CGM delivers an output clock to the PA[0] pin for off-chip use and/or observation.
7.5
Memory map and register definition
Table 7-1. MC_CGM register description
Access
Address
Name
Description
Size
Location
Normal
Supervisor
Test
0xC3FE_0370
CGM_OC_EN
Output Clock Enable
word
read
read/write
read/write
on page 138
0xC3FE_0374
CGM_OCDS_SC
Output Clock Division
Select
byte
read
read/write
read/write
on page 138
0xC3FE_0378
CGM_SC_SS
System Clock Select
Status
byte
read
read
read
on page 139
0xC3FE_037C
CGM_SC_DC0
System Clock Divider
Configuration 0
byte
read
read/write
read/write
on page 140
0xC3FE_037D
CGM_SC_DC1
System Clock Divider
Configuration 1
byte
read
read/write
read/write
on page 140
0xC3FE_037E
CGM_SC_DC2
System Clock Divider
Configuration 2
byte
read
read/write
read/write
on page 140
0xC3FE_0380
CGM_AC0_SC
Aux Clock 0 Select
Control
word
read
read/write
read/write
on page 141
NOTE
Any access to unused registers as well as write accesses to read-only
registers will:
•
Not change register content
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Chapter 7 Clock Generation Module (MC_CGM)
•
Cause a transfer error
Table 7-2. MC_CGM memory map
Address
Name
0
1
2
3
27
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0xC3FE
_0000
…
0xC3FE
_001C
FXOSC registers
0xC3FE
_0020
…
0xC3FE
_003C
reserved
0xC3FE
_0040
…
0xC3FE
_005C
SXOSC registers
0xC3FE
_0060
…
0xC3FE
_007C
FIRC registers
0xC3FE
_0080
…
0xC3FE
_009C
SIRC registers
0xC3FE
_00A0
…
0xC3FE
_00BC
FMPLL registers
0xC3FE
_00C0
…
0xC3FE
_00DC
reserved
0xC3FE
_00E0
…
0xC3FE
_00FC
reserved
0xC3FE
_0100
…
0xC3FE
_011C
CMU registers
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Chapter 7 Clock Generation Module (MC_CGM)
Table 7-2. MC_CGM memory map (continued)
Address
Name
0
1
2
3
27
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0xC3FE
_0120
…
0xC3FE
_013C
reserved
0xC3FE
_0140
…
0xC3FE
_015C
reserved
0xC3FE
_0160
…
0xC3FE
_017C
reserved
0xC3FE
_0180
…
0xC3FE
_019C
reserved
0xC3FE
_01A0
…
0xC3FE
_01BC
reserved
0xC3FE
_01C0
…
0xC3FE
_01DC
reserved
0xC3FE
_01E0
…
0xC3FE
_01FC
reserved
0xC3FE
_0200
…
0xC3FE
_021C
reserved
0xC3FE
_0220
…
0xC3FE
_023C
reserved
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Chapter 7 Clock Generation Module (MC_CGM)
Table 7-2. MC_CGM memory map (continued)
Address
Name
0
1
2
3
27
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0xC3FE
_0240
…
0xC3FE
_025C
reserved
0xC3FE
_0260
…
0xC3FD
_C27C
reserved
0xC3FE
_0280
…
0xC3FE
_029C
reserved
0xC3FE
_02A0
…
0xC3FE
_02BC
reserved
0xC3FE
_02C0
…
0xC3FE
_02DC
reserved
0xC3FE
_02E0
…
0xC3FE
_02FC
reserved
0xC3FE
_0300
…
0xC3FE
_031C
reserved
0xC3FE
_0320
…
0xC3FE
_033C
reserved
0xC3FE
_0340
…
0xC3FE
_035C
reserved
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Chapter 7 Clock Generation Module (MC_CGM)
Table 7-2. MC_CGM memory map (continued)
Address
Name
0
1
2
3
27
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0xC3FE
_0360
…
0xC3FE
_036C
reserved
0xC3FE CGM_OC_EN R
_0370
W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EN
W
0xC3FE CGM_OCDS_ R
_0374 SC
W
0
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SELDIV
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SELCTL
0
0
0
0
W
0xC3FE CGM_SC_SS
_0378
R
SELSTAT
W
R
0
0
0
0
0xC3FE CGM_AC0_S
_0380 C
W
DE2
R
R
0
DE1
0xC3FE CGM_SC_DC R
_037C 0…2
W
DE0
W
DIV0
0
0
0
DIV1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DIV2
0
0
0
SELCTL
W
R
0
0
0
0
0
0
0
0
W
0xC3FE
_0400
…
0xC3FE
_3FFC
7.5.1
reserved
Register descriptions
All registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes. The bytes are ordered
according to big endian. For example, the CGM_OC_EN register may be accessed as a word at address
0xC3FE_0370, as a half-word at address 0xC3FE_0372, or as a byte at address 0xC3FE_0373.
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Chapter 7 Clock Generation Module (MC_CGM)
7.5.1.1
Output Clock Enable Register (CGM_OC_EN)
Address 0xC3FE_0370
R
Access: User read, Supervisor read/write, Test read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
EN
0
Figure 7-2. Output Clock Enable Register (CGM_OC_EN)
This register is used to enable and disable the output clock.
Table 7-3. Output Clock Enable Register (CGM_OC_EN) field descriptions
Field
Description
EN
7.5.2
Output Clock Enable control
0 Output Clock is disabled
1 Output Clock is enabled
Output Clock Division Select Register (CGM_OCDS_SC)
Address 0xC3FE_0374
R
2
0
1
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
Access: User read, Supervisor read/write, Test read/write
3
4
SELDIV
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SELCTL
W
Reset
Figure 7-3. Output Clock Division Select Register (CGM_OCDS_SC)
This register is used to select the current output clock source and its division factor before being delivered
at the output clock.
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Chapter 7 Clock Generation Module (MC_CGM)
Table 7-4. Output Clock Division Select Register (CGM_OCDS_SC) field descriptions
Field
Description
SELDIV Output Clock Division Select
00 output selected Output Clock without division
01 output selected Output Clock divided by 2
10 output selected Output Clock divided by 4
11 output selected Output Clock divided by 8
SELCTL Output Clock Source Selection Control — This value selects the current source for the output clock.
0000 4-16 MHz ext. xtal osc.
0001 16 MHz int. RC osc.
0010 freq. mod. PLL
0011 system clock
0100 RTC clock
0101 reserved
0110 reserved
0111 reserved
1000 reserved
1001 reserved
1010 reserved
1011 reserved
1100 reserved
1101 reserved
1110 reserved
1111 reserved
7.5.3
System Clock Select Status Register (CGM_SC_SS)
This register provides the current clock source selection for the following clocks:
• Undivided: system clock
• Divided by system clock divider 0: peripheral set 1 clock
• Divided by system clock divider 1: peripheral set 2 clock
• Divided by system clock divider 2: peripheral set 3 clock
See Figure 7-7 for details.
Address 0xC3FE_0378
R
Access: User read, Supervisor read, Test read
0
1
2
3
4
5
6
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
0
0
0
0
0
0
0
0
0
0
0
0
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SELSTAT
W
Reset
R
W
Reset
Figure 7-4. System Clock Select Status Register (CGM_SC_SS)
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Chapter 7 Clock Generation Module (MC_CGM)
Table 7-5. System Clock Select Status Register (CGM_SC_SS) field descriptions
Field
Description
SELSTAT
System Clock Source Selection Status — This value indicates the current source for the system clock.
0000 16 MHz int. RC osc.
0001 div. 16 MHz int. RC osc.
0010 4-16 MHz ext. xtal osc.
0011 div. ext. xtal osc.
0100 freq. mod. PLL
0101 reserved
0110 reserved
0111 reserved
1000 reserved
1001 reserved
1010 reserved
1011 reserved
1100 reserved
1101 reserved
1110 reserved
1111 system clock is disabled
7.5.3.1
System Clock Divider Configuration Registers (CGM_SC_DC0…2)
Address 0xC3FE_037C
0
R
W
Reset
R
W
Reset
Access: User read, Supervisor read/write, Test read/write
1
2
3
0
0
0
1
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
0
0
0
0
0
0
DE0
DE2
1
4
5
6
7
DIV0
0
9
10
11
0
0
0
1
0
0
0
0
0
0
0
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DE1
DIV2
0
8
0
0
12
13
14
15
DIV1
Figure 7-5. System Clock Divider Configuration Registers (CGM_SC_DC0…2)
These registers control the system clock dividers.
Table 7-6. System Clock Divider Configuration Registers (CGM_SC_DC0…2) Field Descriptions
Field
Description
DE0
Divider 0 Enable
0 Disable system clock divider 0
1 Enable system clock divider 0
DIV0
Divider 0 Division Value — The resultant peripheral set 1 clock will have a period DIV0 + 1 times that of
the system clock. If the DE0 is set to 0 (Divider 0 is disabled), any write access to the DIV0 field is ignored
and the peripheral set 1 clock remains disabled.
DE1
Divider 1 Enable
0 Disable system clock divider 1
1 Enable system clock divider 1
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Chapter 7 Clock Generation Module (MC_CGM)
Table 7-6. System Clock Divider Configuration Registers (CGM_SC_DC0…2) Field Descriptions (continued)
Field
Description
DIV1
Divider 1 Division Value — The resultant peripheral set 2 clock will have a period DIV1 + 1 times that of
the system clock. If the DE1 is set to 0 (Divider 1 is disabled), any write access to the DIV1 field is ignored
and the peripheral set 2 clock remains disabled.
DE2
Divider 2 Enable
0 Disable system clock divider 2
1 Enable system clock divider 2
DIV2
Divider 2 Division Value — The resultant peripheral set 3 clock will have a period DIV2 + 1 times that of
the system clock. If the DE2 is set to 0 (Divider 2 is disabled), any write access to the DIV2 field is ignored
and the peripheral set 3 clock remains disabled.
7.5.3.2
Auxiliary Clock 0 Select Control Register (CGM_AC0_SC)
Address 0xC3FE_0380
R
Access: User read, Supervisor read/write, Test read/write
0
1
2
3
0
0
0
0
4
R
6
0
0
0
0
0
0
0
16
17
18
19
20
21
0
0
0
0
0
0
0
0
0
0
0
0
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SELCTL
W
Reset
5
W
Reset
Figure 7-6. Auxiliary Clock 0 Select Control Register (CGM_AC0_SC)
This register is used to select the current clock source for the FMPLL reference clock.
Table 7-7. Auxiliary Clock 0 Select Control Register (CGM_AC0_SC) Field Descriptions
Field
Description
SELCTL Auxiliary Clock 0 Source Selection Control — This value selects the current source for auxiliary clock
0.
0000 FXOSC
0001 FIRC
0010 reserved
0011 reserved
0100 reserved
0101 reserved
0110 reserved
0111 reserved
1000 reserved
1001 reserved
1010 reserved
1011 reserved
1100 reserved
1101 reserved
1110 reserved
1111 reserved
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Chapter 7 Clock Generation Module (MC_CGM)
7.6
7.6.1
Functional Description
System Clock Generation
Figure 7-7 shows the block diagram of the system clock generation logic. The MC_ME provides the
system clock select and switch mask (see Chapter 8, Mode Entry Module (MC_ME), for more details),
and the MC_RGM provides the safe clock request (see Chapter 9, Reset Generation Module (MC_RGM),
for more details). The safe clock request forces the selector to select the 16 MHz int. RC osc. as the system
clock and to ignore the system clock select.
16 MHz int. RC osc.
system clock is disabled if
ME_<current mode>_MC.SYSCLK = 1111
0
1
2
3
4
div. 16 MHz int. RC osc.
4-16 MHz ext. xtal osc.
div. ext. xtal osc.
freq. mod. PLL
1
0
system clock
0
CGM_SC_DC0 Register
clock divider
peripheral set 1 clock
MC_RGM safe clock request
MC_ME clock select
CGM_SC_DC1 Register
CGM_SC_SS Register
clock divider
peripheral set 2 clock
CGM_SC_DC2 Register
clock divider
peripheral set 3 clock
Figure 7-7. MC_CGM System Clock Generation Overview
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Chapter 7 Clock Generation Module (MC_CGM)
7.6.1.1
System Clock Source Selection
During normal operation, the system clock selection is controlled:
• On a SAFE mode or reset event, by the MC_RGM
• Otherwise, by the MC_ME
7.6.1.2
System Clock Disable
During normal operation, the system clock can be disabled by the MC_ME.
7.6.1.3
System Clock Dividers
The MC_CGM generates three derived clocks from the system clock.
7.6.1.4
Dividers Functional Description
Dividers are utilized for the generation of divided system and peripheral clocks. The MC_CGM has the
following control registers for built-in dividers:
• Section 7.5.3.1, System Clock Divider Configuration Registers (CGM_SC_DC0…2)
The reset value of all counters is 1. If a divider has its DE bit in the respective configuration register set to
0 (the divider is disabled), any value in its DIVn field is ignored.
7.6.2
Output Clock Multiplexing
The MC_CGM contains a multiplexing function for a number of clock sources that can then be utilized as
output clock sources. The selection is done via the CGM_OCDS_SC register.
4-16 MHz ext. xtal osc.
16 MHz int. RC osc.
freq. mod. PLL
system clock
RTC clock
0
1
2
3
4
CGM_OC_EN Register
3
2
0
1
PA[0]
0
CGM_OCDS_SC.SELCTL
Register
CGM_OCDS_SC.SELDIV
Register
Figure 7-8. MC_CGM Output Clock Multiplexer and PA[0] Generation
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Chapter 7 Clock Generation Module (MC_CGM)
7.6.3
Output Clock Division Selection
The MC_CGM provides the following output signals for the output clock generation:
• PA[0] (see Figure 7-8). This signal is generated by utilizing one of the 3-stage ripple counter
outputs or the selected signal without division. The non-divided signal is not guaranteed to be 50%
duty cycle by the MC_CGM.
• the MC_CGM also has an output clock enable register (see Section 7.5.1.1, Output Clock Enable
Register (CGM_OC_EN)), which contains the output clock enable/disable control bit.
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Chapter 8 Mode Entry Module (MC_ME)
Chapter 8
Mode Entry Module (MC_ME)
8.1
Overview
The MC_ME controls the SoC modex and mode transition sequences in all functional states. It also
contains configuration, control, and status registers accessible for the application.
Figure 8-1 shows the MC_ME block diagram.
MC_ME
VREG
MC_PCU
Flashes
Registers
Platform Interface
MC_RGM
FIRC
MC_CGM
FXOSC
FMPLL
Device
Mode
State
Machine
core
peripherals
WKPU
Figure 8-1. MC_ME block diagram
8.1.1
Features
The MC_ME includes the following features:
• Control of the available modes by the ME_ME register
• Definition of various device mode configurations by the ME_<mode>_MC registers
• Control of the actual device mode by the ME_MCTL register
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Chapter 8 Mode Entry Module (MC_ME)
•
•
•
Capture of the current mode and various resource status within the contents of the ME_GS register
Optional generation of various mode transition interrupts
Status bits for each cause of invalid mode transitions
8.1.2
Modes of operation
The MC_ME is based on several device modes corresponding to different usage models of the device.
Each mode is configurable and can define a policy for energy and processing power management to fit
particular system requirements. An application can easily switch from one mode to another depending on
the current needs of the system. The operating modes controlled by the MC_ME are divided into system
and user modes. The system modes are modes such as RESET, DRUN, SAFE, and TEST. These modes
aim to ease the configuration and monitoring of the system. The user modes are modes such as RUN0…3,
HALT, STOP which can be configured to meet the application requirements in terms of energy
management and available processing power. The modes DRUN, SAFE, TEST, and RUN0…3 are the
device software running modes.
Table 8-1 describes the MC_ME modes.
Table 8-1. MC_ME mode descriptions
Name
Description
Entry
Exit
RESET
This is a chip-wide virtual mode during which the application System reset
is not active. The system remains in this mode until all
assertion from
resources are available for the embedded software to take MC_RGM
control of the device. It manages hardware initialization of
chip configuration, voltage regulators, oscillators, PLLs, and
flash modules.
System reset
deassertion from
MC_RGM
DRUN
This is the entry mode for the embedded software. It
provides full accessibility to the system and enables the
configuration of the system at startup. It provides the unique
gate to enter USER modes. BAM when present is executed
in DRUN mode.
System reset
deassertion from
MC_RGM,
software request
from SAFE, TEST,
and RUN0…3
System reset
assertion,
RUN0…3, TEST
via software, SAFE
via software or
hardware failure.
SAFE
This chip-wide service mode may be entered on the
detection of a recoverable error. It forces the system into a
predefined safe configuration from which the system may try
to recover.
Hardware failure,
System reset
software request
assertion, DRUN
from DRUN, TEST, via software
and RUN0…3
TEST
This chip-wide service mode provides a control environment Software request
for device self-test. It may enable the application to run its from DRUN
own self-test like flash checksum, memory BIST, etc.
System reset
assertion, DRUN
via software
RUN0…3
These are software running modes where most processing
activity is done. These various run modes allow to enable
different clock & power configurations of the system with
respect to each other.
System reset
assertion, SAFE
via software or
hardware failure,
other RUN0…3
modes, HALT,
STOP via software
Software request
from DRUN,
interrupt event
from HALT,
interrupt or wakeup
event from STOP
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Chapter 8 Mode Entry Module (MC_ME)
Table 8-1. MC_ME mode descriptions (continued)
Name
8.2
Description
Entry
Exit
HALT
This is a reduced-activity low-power mode during which the Software request
clock to the core is disabled. It can be configured to switch from RUN0…3
off analog peripherals like PLL, flash, main regulator, etc. for
efficient power management at the cost of higher wakeup
latency.
System reset
assertion, SAFE
on hardware
failure, RUN0…3
on interrupt event
STOP
This is an advanced low-power mode during which the clock Software request
to the core is disabled. It may be configured to switch off
from RUN0…3
most of the peripherals including oscillator for efficient
power management at the cost of higher wakeup latency.
System reset
assertion, SAFE
on hardware
failure, RUN0…3
on interrupt event
or wakeup event
External signal description
The MC_ME has no connections to any external pins.
8.3
Memory map and register definition
The MC_ME contains registers for:
• Mode selection and status reporting
• Mode configuration
• Mode transition interrupts status and mask control
Table 8-2. MC_ME register description
Access
Address
Name
Description
Location
Size
Normal Supervisor
Test
0xC3FD ME_GS
_C000
Global Status
word
read
read
read
0xC3FD ME_MCTL
_C004
Mode Control
word
read
read/write
read/write on page 152
0xC3FD ME_ME
_C008
Mode Enable
word
read
read/write
read/write on page 153
0xC3FD ME_IS
_C00C
Interrupt Status
word
read
read/write
read/write on page 154
0xC3FD ME_IM
_C010
Interrupt Mask
word
read
read/write
read/write on page 155
0xC3FD ME_IMTS
_C014
Invalid Mode Transition
Status
word
read
read/write
read/write on page 156
0xC3FD ME_DMTS
_C018
Debug Mode Transition
Status
word
read
read
read
on page 151
on page 157
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Chapter 8 Mode Entry Module (MC_ME)
Table 8-2. MC_ME register description (continued)
Access
Address
Name
Description
Location
Size
Normal Supervisor
Test
0xC3FD ME_RESET_MC
_C020
RESET Mode
Configuration
word
read
read
read
on page 159
0xC3FD ME_TEST_MC
_C024
TEST Mode
Configuration
word
read
read/write
read/write on page 159
0xC3FD ME_SAFE_MC
_C028
SAFE Mode
Configuration
word
read
read/write
read/write on page 160
0xC3FD ME_DRUN_MC
_C02C
DRUN Mode
Configuration
word
read
read/write
read/write on page 160
0xC3FD ME_RUN0_MC
_C030
RUN0 Mode
Configuration
word
read
read/write
read/write on page 161
0xC3FD ME_RUN1_MC
_C034
RUN1 Mode
Configuration
word
read
read/write
read/write on page 161
0xC3FD ME_RUN2_MC
_C038
RUN2 Mode
Configuration
word
read
read/write
read/write on page 161
0xC3FD ME_RUN3_MC
_C03C
RUN3 Mode
Configuration
word
read
read/write
read/write on page 161
0xC3FD ME_HALT_MC
_C040
HALT Mode
Configuration
word
read
read/write
read/write on page 161
0xC3FD ME_STOP_MC
_C048
STOP Mode
Configuration
word
read
read/write
read/write on page 161
NOTE
Any access to unused registers as well as write accesses to read-only
registers will:
•
•
Not change register content
Cause a transfer error
Table 8-3. MC_ME Memory Map
R
0
0
0
0
S_FIRC
W
0
0
0
0
0
S_SYSCLK
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
1
1
1
1
W
0xC3FD ME_MCTL
_C004
R
TARGET_MODE
W
R
W
1
0
1
0
KEY
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Chapter 8 Mode Entry Module (MC_ME)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
I_IMODE
I_SAFE
I_MTC
W
R
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
M_IMODE
M_SAFE
M_MTC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
S_DMA
S_NMA
R
M_ICONF
W
R
W
R
W
R
0
0
0
0
0
0
0
0
0
PMC_PROG
0
CFLASH_SC
0
DFLASH_SC
R
SYSCLK_SW
0xC3FD ME_DMTS
_C018
0
0
0
0
0
MVRON
w1c w1c w1c w1c w1c
MPH_BUSY
W
S_MTI
0xC3FD ME_IMTS
_C014
S_SEA
0xC3FD ME_IM
_C010
w1c w1c w1c w1c
S_MRI
W
0
0
SMR
0xC3FD ME_IS
_C00C
R
CORE_DBG
0xC3FD ME_ME
_C008
I_ICONF
Table 8-3. MC_ME Memory Map (continued)
W
R
0
W
0xC3FD
_C01C
R
0
0
0
0
0
0
0
0
PDO
0xC3FD ME_RESET_
_C020 MC
reserved
0
0
0
0
0
0
0
0
0
DFLAON
CFLAON
R
FIRCON
W
SYSCLK
W
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Chapter 8 Mode Entry Module (MC_ME)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MVRON
R
PDO
0xC3FD ME_TEST_M
_C024 C
PDO
Table 8-3. MC_ME Memory Map (continued)
DFLAON
CFLAON
DFLAON
CFLAON
0xC3FD ME_SAFE_M
_C028 C
R
0
MVRON
W
R
FIRCON
W
SYSCLK
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RUN0
DRUN
MVRON
0
RUN1
CFLAON
0
RUN2
DFLAON
PDO
CFLAON
PDO
DFLAON
0
RUN3
0xC3FD ME_DRUN_M
_C02C C
R
MVRON
W
0
0
0
0
0
0
0
0xC3FD
_C044
reserved
0xC3FD
_C0
…
0xC3FD
_C
reserved
0xC3FD ME_RUN_PC R
_C080 0…7
W
…
0xC3FD
_C09C
R
0
0
0
0
0
RESET
0
TEST
0xC3FD ME_RUN0…3
_C030 _MC
R
…
0xC3FD
W
_C03C
SAFE
W
W
0xC3FD
_C150
…
0xC3FD
_FFFC
8.3.1
reserved
Register descriptions
Unless otherwise noted, all registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes.
The bytes are ordered according to big endian. For example, the ME_RUN_PC0 register may be accessed
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Chapter 8 Mode Entry Module (MC_ME)
as a word at address 0xC3FD_C080, as a half-word at address 0xC3FD_C082, or as a byte at address
0xC3FD_C083.
8.3.1.1
Global Status Register (ME_GS)
Address 0xC3FD_C000
Access: User read, Supervisor read, Test read
W
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
S_FIRC
Reset
R
1
1
1
S_SYSCLK
W
Reset
0
0
1
0
0
0
0
Figure 8-2. Global Status Register (ME_GS)
This register contains global mode status.
Table 8-4. Global Status Register (ME_GS) Field Descriptions
Field
Description
S_CURREN Current device mode status
T_MODE
0000 RESET
0001 TEST
0010 SAFE
0011 DRUN
0100 RUN0
0101 RUN1
0110 RUN2
0111 RUN3
1000 HALT
1001 reserved
1010 STOP
1011 reserved
1100 reserved
1101
1110 reserved
1111 reserved
S_MTRANS Mode transition status
0 Mode transition process is not active
1 Mode transition is ongoing
S_PDO
Output power-down status — This bit specifies output power-down status of I/Os. This bit is
asserted whenever outputs of pads are forced to high impedance state or the pads power sequence
driver is switched off.
0 No automatic safe gating of I/Os used and pads power sequence driver is enabled
1 In SAFE/TEST modes, outputs of pads are forced to high impedance state and pads power
sequence driver is disabled. The inputs are level unchanged. In STOP mode, only pad power
sequence driver is disabled but the state of the output is kept.
S_MVR
Main voltage regulator status
0 Main voltage regulator is not ready
1 Main voltage regulator is ready for use
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Chapter 8 Mode Entry Module (MC_ME)
Table 8-4. Global Status Register (ME_GS) Field Descriptions (continued)
Field
Description
S_DFLA
Data flash availability status
00 Data flash is not available
01 Data flash is in power-down mode
10 Data flash is in low-power mode
11 Data flash is in normal mode and available for use
S_CFLA
Code flash availability status
00 Code flash is not available
01 Code flash is in power-down mode
10 Code flash is in low-power mode
11 Code flash is in normal mode and available for use
S_FIRC
fast internal RC oscillator (16 MHz) status
0 fast internal RC oscillator (16 MHz) is not stable
1 fast internal RC oscillator (16 MHz) is providing a stable clock
S_SYSCLK
8.3.1.2
System clock switch status — These bits specify the system clock currently used by the system.
0000 16 MHz int. RC osc.
0001 div. 16 MHz int. RC osc.
0010 4–16 MHz ext. xtal osc.
0011 div. ext. xtal osc.
0100 freq. mod. PLL
0101 reserved
0110 reserved
0111 reserved
1000 reserved
1001 reserved
1010 reserved
1011 reserved
1100 reserved
1101 reserved
1110 reserved
1111 system clock is disabled
Mode Control Register (ME_MCTL)
Address 0xC3FD_C004
Access: User read, Supervisor read/write, Test read/write
R
0
0
0
0
0
0
0
0
0
0
0
0
TARGET_MODE
W
Reset
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
R
1
0
1
0
0
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
W
Reset
KEY
1
0
1
0
0
1
0
1
Figure 8-3. Mode Control Register (ME_MCTL)
This register is used to trigger software-controlled mode changes. Depending on the modes as enabled by
ME_ME register bits, configurations corresponding to unavailable modes are reserved and access to
ME_<mode>_MC registers must respect this for successful mode requests.
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NOTE
Byte and half-word write accesses are not allowed for this register as a
predefined key is required to change its value.
Table 8-5. Mode Control Register (ME_MCTL) Field Descriptions
Field
Description
TARGET_M Target device mode — These bits provide the target device mode to be entered by software
ODE
programming. The mechanism to enter into any mode by software requires the write operation twice:
first time with key, and second time with inverted key. These bits are automatically updated by
hardware while entering SAFE on hardware request. Also, while exiting from the HALT and STOP
modes on hardware exit events, these are updated with the appropriate RUN0…3 mode value.
0000 RESET
0001 TEST
0010 SAFE
0011 DRUN
0100 RUN0
0101 RUN1
0110 RUN2
0111 RUN3
1000 HALT
1001 reserved
1010 STOP
1011 reserved
1100 reserved
1101
1110 reserved
1111 reserved
KEY
8.3.1.3
Control key — These bits enable write access to this register. Any write access to the register with
a value different from the keys is ignored. Read access will always return inverted key.
KEY: 0101101011110000 (0x5AF0)
INVERTED KEY: 1010010100001111 (0xA50F)
Mode Enable Register (ME_ME)
Address 0xC3FD_C008
R
Access: User read, Supervisor read/write, Test read/write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
0
0
0
1
1
1
W
0
1
Figure 8-4. Mode Enable Register (ME_ME)
This register allows a way to disable the device modes that are not required for a given device. RESET,
SAFE, DRUN, and RUN0 modes are always enabled.
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Chapter 8 Mode Entry Module (MC_ME)
Table 8-6. Mode Enable Register (ME_ME) Field Descriptions
Field
Description
STOP
STOP mode enable
0 STOP mode is disabled
1 STOP mode is enabled
HALT
HALT mode enable
0 HALT mode is disabled
1 HALT mode is enabled
RUN3
RUN3 mode enable
0 RUN3 mode is disabled
1 RUN3 mode is enabled
RUN2
RUN2 mode enable
0 RUN2 mode is disabled
1 RUN2 mode is enabled
RUN1
RUN1 mode enable
0 RUN1 mode is disabled
1 RUN1 mode is enabled
RUN0
RUN0 mode enable
0 RUN0 mode is disabled
1 RUN0 mode is enabled
DRUN
DRUN mode enable
0 DRUN mode is disabled
1 DRUN mode is enabled
SAFE
SAFE mode enable
0 SAFE mode is disabled
1 SAFE mode is enabled
TEST
TEST mode enable
0 TEST mode is disabled
1 TEST mode is enabled
RESET
8.3.1.4
RESET mode enable
0 RESET mode is disabled
1 RESET mode is enabled
Interrupt Status Register (ME_IS)
Address 0xC3FD_C00C
R
Access: User read, Supervisor read/write, Test read/write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
I_MTC
W
I_SAFE
R
I_IMODE
Reset
I_ICONF
W
w1c
w1c
w1c
w1c
0
0
0
0
Figure 8-5. Interrupt Status Register (ME_IS)
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This register provides the current interrupt status.
Table 8-7. Interrupt Status Register (ME_IS) Field Descriptions
Field
Description
I_ICONF
Invalid mode configuration interrupt — This bit is set whenever a write operation to
ME_<mode>_MC registers with invalid mode configuration is attempted. It is cleared by writing a 1
to this bit.
0 No invalid mode configuration interrupt occurred
1 Invalid mode configuration interrupt is pending
I_IMODE
Invalid mode interrupt — This bit is set whenever an invalid mode transition is requested. It is
cleared by writing a 1 to this bit.
0 No invalid mode interrupt occurred
1 Invalid mode interrupt is pending
I_SAFE
SAFE mode interrupt — This bit is set whenever the device enters SAFE mode on hardware
requests generated in the system. It is cleared by writing a 1 to this bit.
0 No SAFE mode interrupt occurred
1 SAFE mode interrupt is pending
I_MTC
Mode transition complete interrupt — This bit is set whenever the mode transition process
completes (S_MTRANS transits from 1 to 0). It is cleared by writing a 1 to this bit. This mode transition
interrupt bit will not be set while entering low-power modes HALT, STOP.
0 No mode transition complete interrupt occurred
1 Mode transition complete interrupt is pending
8.3.1.5
Interrupt Mask Register (ME_IM)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
0
0
0
0
0
0
0
0
0
0
0
0
M_IMODE
M_SAFE
M_MTC
R
Access: User read, Supervisor read/write, Test read/write
M_ICONF
Address 0xC3FD_C010
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
W
Reset
Figure 8-6. Interrupt Mask Register (ME_IM)
This register controls whether an event generates an interrupt or not.
Table 8-8. Interrupt Mask Register (ME_IM) Field Descriptions
Field
Description
M_ICONF
Invalid mode configuration interrupt mask
0 Invalid mode interrupt is masked
1 Invalid mode interrupt is enabled
M_IMODE
Invalid mode interrupt mask
0 Invalid mode interrupt is masked
1 Invalid mode interrupt is enabled
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Chapter 8 Mode Entry Module (MC_ME)
Table 8-8. Interrupt Mask Register (ME_IM) Field Descriptions (continued)
Field
Description
M_SAFE
SAFE mode interrupt mask
0 SAFE mode interrupt is masked
1 SAFE mode interrupt is enabled
M_MTC
Mode transition complete interrupt mask
0 Mode transition complete interrupt is masked
1 Mode transition complete interrupt is enabled
8.3.1.6
Invalid Mode Transition Status Register (ME_IMTS)
Address 0xC3FD_C014
R
Access: User read, Supervisor read/write, Test read/write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
S_SEA
Reset
S_NMA
W
S_DMA
R
S_MRI
Reset
S_MTI
W
w1c
w1c
w1c
w1c
w1c
0
0
0
0
0
Figure 8-7. Invalid Mode Transition Status Register (ME_IMTS)
This register provides the status bits for each cause of invalid mode interrupt.
Table 8-9. Invalid Mode Transition Status Register (ME_IMTS) Field Descriptions
Field
Description
S_MTI
Mode Transition Illegal status — This bit is set whenever a new mode is requested while some
other mode transition process is active (S_MTRANS is 1). Please see Section 8.4.5, Mode transition
interrupts, for the exceptions to this behavior. It is cleared by writing a 1 to this bit.
0 Mode transition requested is not illegal
1 Mode transition requested is illegal
S_MRI
Mode Request Illegal status — This bit is set whenever the target mode requested is not a valid
mode with respect to current mode. It is cleared by writing a 1 to this bit.
0 Target mode requested is not illegal with respect to current mode
1 Target mode requested is illegal with respect to current mode
S_DMA
Disabled Mode Access status — This bit is set whenever the target mode requested is one of those
disabled modes determined by ME_ME register. It is cleared by writing a 1 to this bit.
0 Target mode requested is not a disabled mode
1 Target mode requested is a disabled mode
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Table 8-9. Invalid Mode Transition Status Register (ME_IMTS) Field Descriptions (continued)
Field
Description
S_NMA
Non-existing Mode Access status — This bit is set whenever the target mode requested is one of
those non existing modes determined by ME_ME register. It is cleared by writing a 1 to this bit.
0 Target mode requested is an existing mode
1 Target mode requested is a non-existing mode
S_SEA
SAFE Event Active status — This bit is set whenever the device is in SAFE mode, SAFE event bit
is pending and a new mode requested other than RESET/SAFE modes. It is cleared by writing a 1 to
this bit.
0 No new mode requested other than RESET/SAFE while SAFE event is pending
1 New mode requested other than RESET/SAFE while SAFE event is pending
Debug Mode Transition Status Register (ME_DMTS)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DFLASH_SC
CFLASH_SC
0
0
0
0
0
0
SMR
0
SYSCLK_SW
R
CORE_DBG
Access: User read, Supervisor read/write, Test read/write
PMC_PROG
Address 0xC3FD_C018
0
0
0
0
0
0
0
0
0
MPH_BUSY
8.3.1.7
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
0
W
Reset
0
0
0
0
0
Figure 8-8. Debug Mode Transition Status Register (ME_DMTS)
This register provides the status of different factors that influence mode transitions. It is used to give an
indication of why a mode transition indicated by ME_GS.S_MTRANS may be taking longer than
expected.
NOTE
The ME_DMTS register does not indicate whether a mode transition is
ongoing. Therefore, some ME_DMTS bits may still be asserted after the
mode transition has completed.
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Chapter 8 Mode Entry Module (MC_ME)
Table 8-10. Debug Mode Transition Status Register (ME_DMTS) Field Descriptions
Field
Description
MPH_BUSY MC_ME/MC_PCU Handshake Busy indicator — This bit is set if the MC_ME has requested a mode
change from the MC_PCU and the MC_PCU has not yet responded. It is cleared when the MC_PCU
has responded.
0 Handshake is not busy
1 Handshake is busy
PMC_PROG MC_PCU Mode Change in Progress indicator — This bit is set if the MC_PCU is in the process of
powering up or down power domains. It is cleared when all power-up/down processes have
completed.
0 Power-up/down transition is not in progress
1 Power-up/down transition is in progress
CORE_DBG Processor is in Debug mode indicator — This bit is set while the processor is in debug mode.
0 The processor is not in debug mode
1 The processor is in debug mode
SMR
SAFE mode request from MC_RGM is active indicator — This bit is set if a hardware SAFE mode
request has been triggered. It is cleared when the hardware SAFE mode request has been cleared.
0 A SAFE mode request is not active
1 A SAFE mode request is active
FIRC_SC
FIRC State Change during mode transition indicator — This bit is set when the fast internal RC
oscillator (16 MHz) is requested to change its power up/down state. It is cleared when the fast internal
RC oscillator (16 MHz) has completed its state change.
0 No state change is taking place
1 A state change is taking place
SYSCLK_S
W
System Clock Switching pending status —
0 No system clock source switching is pending
1 A system clock source switching is pending
DFLASH_SC DFLASH State Change during mode transition indicator — This bit is set when the DFLASH is
requested to change its power up/down state. It is cleared when the DFLASH has completed its state
change.
0 No state change is taking place
1 A state change is taking place
CFLASH_SC CFLASH State Change during mode transition indicator — This bit is set when the CFLASH is
requested to change its power up/down state. It is cleared when the DFLASH has completed its state
change.
0 No state change is taking place
1 A state change is taking place
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Chapter 8 Mode Entry Module (MC_ME)
RESET Mode Configuration Register (ME_RESET_MC)
Address 0xC3FD_C020
Access: User read, Supervisor read/write, Test read/write
R
0
0
0
0
0
0
0
0
PDO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MVRON
8.3.1.8
DFLAON
CFLAON
1
1
1
Reset
FIRCON
W
R
1
1
SYSCLK
W
Reset
0
0
1
0
0
0
0
Figure 8-9. Invalid Mode Transition Status Register (ME_IMTS)
This register configures system behavior during RESET mode. Please see Table 8-11 for details.
8.3.1.9
TEST Mode Configuration Register (ME_TEST_MC)
Access: User read, Supervisor read/write, Test read/write
MVRON
Address 0xC3FD_C024
DFLAON
Reset
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
Reset
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
R
0
0
0
0
0
0
0
0
0
0
PDO
CFLAON
W
Figure 8-10. TEST Mode Configuration Register (ME_TEST_MC)
This register configures system behavior during TEST mode. Please see Table 8-11 for details.
NOTE
Byte and half-word write accesses are not allowed to this register.
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Chapter 8 Mode Entry Module (MC_ME)
SAFE Mode Configuration Register (ME_SAFE_MC)
Address 0xC3FD_C028
Access: User read, Supervisor read/write, Test read/write
R
0
0
0
0
0
0
0
0
0
0
0
0
PDO
MVRON
8.3.1.10
DFLAON
CFLAON
1
1
1
W
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
FIRCON
Reset
R
1
SYSCLK
W
Reset
0
0
1
0
0
0
0
Figure 8-11. SAFE Mode Configuration Register (ME_SAFE_MC)
This register configures system behavior during SAFE mode. Please see Table 8-11 for details.
NOTE
Byte and half-word write accesses are not allowed to this register.
8.3.1.11
DRUN Mode Configuration Register (ME_DRUN_MC)
Access: User read, Supervisor read/write, Test read/write
MVRON
Address 0xC3FD_C02C
DFLAON
Reset
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
Reset
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
R
0
0
0
0
0
0
0
0
PDO
0
0
CFLAON
W
Figure 8-12. DRUN Mode Configuration Register (ME_DRUN_MC)
This register configures system behavior during DRUN mode. Please see Table 8-11 for details.
NOTE
Byte and half-word write accesses are not allowed to this register.
NOTE
The values of CFLAON, and DFLAON are retained through STANDBY
mode.
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8.3.1.12
RUN0…3 Mode Configuration Registers (ME_RUN0…3_MC)
Access: User read, Supervisor read/write, Test read/write
MVRON
Address 0xC3FD_C030–0xC3FD_C03C
DFLAON
Reset
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
Reset
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
R
0
0
0
0
0
0
0
0
PDO
0
0
CFLAON
W
Figure 8-13. RUN0…3 Mode Configuration Registers (ME_RUN0…3_MC)
This register configures system behavior during RUN0…3 modes. Please see Table 8-11 for details.
NOTE
Byte and half-word write accesses are not allowed to this register.
8.3.1.13
HALT Mode Configuration Register (ME_HALT_MC)
Address 0xC3FD_C040
Access: User read, Supervisor read/write, Test read/write
Reset
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
Reset
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
Figure 8-14. HALT Mode Configuration Register (ME_HALT_MC)
This register configures system behavior during HALT mode. Please see Table 8-11 for details.
NOTE
Byte and half-word write accesses are not allowed to this register.
8.3.1.14
STOP Mode Configuration Register (ME_STOP_MC)
This register configures system behavior during STOP mode. Please see Table 8-11 for details.
NOTE
Byte and half-word write accesses are not allowed to this register.
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Table 8-11. Mode Confutation Registers (ME_<mode>_MC) Field Descriptions
Field
PDO
Description
I/O output power-down control — This bit controls the output power-down of I/Os.
0 No automatic safe gating of I/Os used and pads power sequence driver is enabled
1 In SAFE/TEST modes, outputs of pads are forced to high impedance state and pads power
sequence driver is disabled. The inputs are level unchanged. In STOP mode, only pad power
sequence driver is disabled but the state of the output is kept.
MVRON
Main voltage regulator control — This bit specifies whether main voltage regulator is switched off
or not while entering this mode.
0 Main voltage regulator is switched off
1 Main voltage regulator is switched on
DFLAON
Data flash power-down control — This bit specifies the operating mode of the data flash after
entering this mode.
00 Reserved
01 Data flash is in power-down mode
10 Data flash is in low-power mode
11 Data flash is in normal mode
Note: If the flash memory is to be powered down in any mode, then your software must ensure that
reset sources are configured as long resets in the RGM_FESS register (see Section 9.3.1.7,
Functional Event Short Sequence Register (RGM_FESS)).
CFLAON
Code flash power-down control — This bit specifies the operating mode of the program flash after
entering this mode.
00 Reserved
01 Code flash is in power-down mode
10 Code flash is in low-power mode
11 Code flash is in normal mode
FIRCON
fast internal RC oscillator (16 MHz) control
0 fast internal RC oscillator (16 MHz) is switched off
1 fast internal RC oscillator (16 MHz) is switched on
SYSCLK
System clock switch control — These bits specify the system clock to be used by the system.
0000 16 MHz int. RC osc.
0001 div. 16 MHz int. RC osc.
0010 4–16 MHz ext. xtal osc.
0011 div. ext. xtal osc.
0100 freq. mod. PLL
0101 reserved
0110 reserved
0111 reserved
1000 reserved
1001 reserved
1010 reserved
1011 reserved
1100 reserved
1101 reserved
1110 reserved
1111 system clock is disabled
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Chapter 8 Mode Entry Module (MC_ME)
8.4
8.4.1
Functional description
Mode transition request
The transition from one mode to another mode is normally handled by software by accessing the mode
control ME_MCTL register. But in case of special events, mode transition can be automatically managed
by hardware. In order to switch from one mode to another, the application should access ME_MCTL
register twice by writing
• The first time with the value of the key (0x5AF0) into the KEY bit field and the required target
mode into the TARGET_MODE bit field, and
• The second time with the inverted value of the key (0xA50F) into the KEY bit field and the
required target mode into the TARGET_MODE bit field.
Once a valid mode transition request is detected, the target mode configuration information is loaded from
the corresponding ME_<mode>_MC register. The mode transition request may require a number of cycles
depending on the programmed configuration, and software should check the S_CURRENT_MODE bit
field and the S_MTRANS bit of the global status register ME_GS to verify when the mode has been
correctly entered and the transition process has completed. For a description of valid mode requests, please
see Section 8.4.5, Mode transition interrupts.
Any modification of the mode configuration register of the currently selected mode will not be taken into
account immediately but on the next request to enter this mode. This means that transition requests such
as RUN0…3  RUN0…3, DRUN  DRUN, SAFE  SAFE, and TEST  TEST are considered valid
mode transition requests. As soon as the mode request is accepted as valid, the S_MTRANS bit is set till
the status in the ME_GS register matches the configuration programmed in the respective
ME_<mode>_MC register.
NOTE
It is recommended that software poll the S_MTRANS bit in the ME_GS
register after requesting a transition to HALT, STOP, or STANDBY modes.
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Chapter 8 Mode Entry Module (MC_ME)
SYSTEM MODES
recoverable
hardware failure
USER MODES
RUN0
SAFE
software
request
HALT
RUN1
RESET
DRUN
RUN2
STOP
RUN3
non-recoverable
failure
TEST
Figure 8-15. MC_ME mode diagram
8.4.2
8.4.2.1
Modes details
RESET mode
The device enters this mode on the following events:
• From SAFE, DRUN, RUN0…3, or TEST mode when the TARGET_MODE bit field of the
ME_MCTL register is written with 0000
• From any mode due to a system reset by the MC_RGM because of some non-recoverable hardware
failure in the system (see Chapter 9, Reset Generation Module (MC_RGM), for details)
Transition to this mode is instantaneous, and the system remains in this mode until the reset sequence is
finished. The mode configuration information for this mode is provided by the ME_RESET_MC register.
This mode has a predefined configuration, and the 16 MHz int. RC osc. is selected as the system clock.
8.4.2.2
DRUN mode
The device enters this mode on the following events.
• Automatically from RESET mode after completion of the reset sequence
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Chapter 8 Mode Entry Module (MC_ME)
•
From RUN0…3, SAFE, or TEST mode when the TARGET_MODE bit field of the ME_MCTL
register is written with 0011
As soon as any of the above events has occurred, a DRUN mode transition request is generated. The mode
configuration information for this mode is provided by the ME_DRUN_MC register. In this mode, the
flashes, all clock sources, and the system clock configuration can be controlled by software as required.
After system reset, the software execution starts with the default configuration selecting the 16 MHz int.
RC osc. as the system clock.
This mode is intended to be used by software to:
• Initialize all registers as per the system needs
NOTE
As flashes can be configured in low-power or power-down state in this
mode, software must ensure that the code executes from RAM before
changing to this mode.
8.4.2.3
SAFE mode
The device enters this mode on the following events:
• From DRUN, RUN0…3, or TEST mode when the TARGET_MODE bit field of the ME_MCTL
register is written with 0010
• From any mode except RESET due to a SAFE mode request generated by the MC_RGM because
of some potentially recoverable hardware failure in the system (see Chapter 9, Reset Generation
Module (MC_RGM), for details)
As soon as any of the above events has occurred, a SAFE mode transition request is generated. The mode
configuration information for this mode is provided by the ME_SAFE_MC register. This mode has a
predefined configuration, and the 16 MHz int. RC osc. is selected as the system clock.
If the SAFE mode is requested by software while some other mode transition process is ongoing, the new
target mode becomes the SAFE mode regardless of other pending requests. In this case, the new mode
request is not interpreted as an invalid request.
NOTE
If software requests to change to the SAFE mode and then requests to
change back to the parent mode before the mode transition is completed, the
device’s final mode after mode transition will be the parent mode. However,
this is not recommended software behavior. It is recommended for software
to wait until the S_MTRANS bit is cleared after requesting a change to
SAFE before requesting another mode change.
As long as a SAFE event is active, the system remains in the SAFE mode and no write access is allowed
to the ME_MCTL register.
This mode is intended to be used by software to:
• Assess the severity of the cause of failure and then to either
— Reinitialize the device via the DRUN mode, or
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Chapter 8 Mode Entry Module (MC_ME)
— Completely reset the device via the RESET mode.
If the outputs of the system I/Os need to be forced to a high impedance state upon entering this mode, the
PDO bit of the ME_SAFE_MC register should be set. The input levels remain unchanged.
8.4.2.4
TEST mode
The device enters this mode on the following events:
• From the DRUN mode when the TARGET_MODE bit field of the ME_MCTL register is written
with 0001
As soon as any of the above events has occurred, a TEST mode transition request is generated. The mode
configuration information for this mode is provided by the ME_TEST_MC register. Except for the main
voltage regulator, all resources of the system are configurable in this mode. The system clock to the whole
system can be stopped by programming the SYSCLK bit field to 1111, and in this case, the only way to
exit this mode is via a device reset.
This mode is intended to be used by software to execute on-chip test routines.
NOTE
As flash modules can be configured to a low-power or power-down state in
these modes, software must ensure that the code will execute from RAM
before it changes to this mode.
8.4.2.5
RUN0…3 modes
The device enters one of these modes on the following events:
• From the DRUN another RUN0…3 mode when the TARGET_MODE bit field of the ME_MCTL
register is written with 0100…0111
• From the HALT mode by an interrupt event
• From the STOP mode by an interrupt or wakeup event
As soon as any of the above events occur, a RUN0…3 mode transition request is generated. The mode
configuration information for these modes is provided by ME_RUN0…3_MC registers. In these modes,
the flashes, all clock sources, and the system clock configuration can be controlled by software as required.
These modes are intended to be used by software to execute application routines.
NOTE
As flash modules can be configured to a low-power or power-down state in
these modes, software must ensure that the code will execute from RAM
before it changes to this mode.
8.4.2.6
HALT mode
The device enters this mode on the following events:
• From one of the RUN0…3 modes when the TARGET_MODE bit field of the ME_MCTL register
is written with 1000.
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As soon as any of the above events occur, a HALT mode transition request is generated. The mode
configuration information for this mode is provided by ME_HALT_MC register. This mode is quite
configurable, and the ME_HALT_MC register should be programmed according to the system needs. The
flashes can be put in power-down mode as needed. If there is a HALT mode request while an interrupt
request is active, the device mode does not change, and an invalid mode interrupt is not generated.
This mode is intended as a first level low-power mode with
• The core clock frozen
• Only a few peripherals running
and to be used by software to wait until it is required to do something and then to react quickly (that is,
within a few system clock cycles of an interrupt event).
8.4.2.7
STOP mode
The device enters this mode on the following events:
• From one of the RUN0…3 modes when the TARGET_MODE bit field of the ME_MCTL register
is written with 1010.
As soon as any of the above events occur, a STOP mode transition request is generated. The mode
configuration information for this mode is provided by the ME_STOP_MC register. This mode is fully
configurable, and the ME_STOP_MC register should be programmed according to the system needs. The
flashes can be put in power-down mode as needed. If there is a STOP mode request while any interrupt or
wakeup event is active, the device mode does not change, and an invalid mode interrupt is not generated.
This can be used as an advanced low-power mode with the core clock frozen and almost all peripherals
stopped.
This mode is intended as an advanced low-power mode with
• The core clock frozen
• Almost all peripherals stopped
and to be used by software to wait until it is required to do something with no need to react quickly (e.g.
allow for system clock source to be restarted).
This mode can be used to stop all clock sources, thus preserving the device status. When exiting the STOP
mode, the fast internal RC oscillator (16 MHz) clock is selected as the system clock until the target clock
is available.
8.4.3
Mode transition process
The process of mode transition follows the following steps in a predefined manner depending on the
current device mode and the requested target mode. In many cases of mode transition, not all steps need
to be executed based on the mode control information, and some steps may not be valid according to the
mode definition itself.
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8.4.3.1
Target mode request
The target mode is requested by accessing the ME_MCTL register with the required keys. This mode
transition request by software must be a valid request satisfying a set of predefined rules to initiate the
process. If the request fails to satisfy these rules, it is ignored, and the TARGET_MODE bit field is not
updated. An optional interrupt can be generated for invalid mode requests. See Section 8.4.5, Mode
transition interrupts, for details.
In the case of mode transitions occurring because of hardware events such as a reset, a SAFE mode request,
or interrupt requests and wakeup events to exit from low-power modes, the TARGET_MODE bit field of
the ME_MCTL register is automatically updated with the appropriate target mode. The mode change
process start is indicated by the setting of the mode transition status bit S_MTRANS of the ME_GS
register.
A RESET mode requested via the ME_MCTL register is passed to the MC_RGM, which generates a
global system reset and initiates the reset sequence. The RESET mode request has the highest priority, and
the MC_ME is kept in the RESET mode during the entire reset sequence.
The SAFE mode request has the next highest priority after reset which can be generated by software via
the ME_MCTL register from all software running modes including DRUN, RUN0…3, and TEST or by
the MC_RGM after the detection of system hardware failures, which may occur in any mode.
8.4.3.2
Target mode configuration loading
On completion of the Target mode request, the target mode configuration from the
ME_<target mode>_MC register is loaded to start the resources (voltage sources, clock sources, flashes,
pads, etc.) control process.
An overview of resource control possibilities for each mode is shown in Table 8-12. A indicates that a
given resource is configurable for a given mode.
Table 8-12. MC_ME resource control overview
Mode
Resource
RESET
TEST
SAFE
DRUN
RUN0

FIRC
on
on
on

CFLASH
normal
normal
normal

DFLASH
normal
normal
normal
on
on
STOP
STANDBY



on
on
on
on
on




normal
normal
low-power
powerdown




normal
normal
low-power
powerdown


on
on
MVREG
on
HALT
on
on
powerdown
powerdown
off
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Table 8-12. MC_ME resource control overview (continued)
Mode
Resource
RESET
PDO
off
8.4.3.3
TEST
SAFE


off
on
DRUN
RUN0
HALT
STOP
STANDBY

off
off
off
off
on
Peripheral Clocks Disable
On completion of the Target mode request, the MC_ME requests each peripheral to enter its stop mode
when:
The MC_ME does not automatically request peripherals to enter their stop
modes if the power domains in which they are residing are to be turned off
due to a mode change. Therefore, it is software’s responsibility to ensure
that those peripherals that are to be powered down are configured in the
MC_ME to be frozen.
Each peripheral that may block or disrupt a communication bus to which it is connected ensures that these
outputs are forced to a safe or recessive state when the device enters the SAFE mode.
8.4.3.4
Processor low-power mode entry
If, on completion of the Peripheral Clocks Disable, the mode transition is to the HALT mode, the MC_ME
requests the processor to enter its halted state. The processor acknowledges its halt state request after
completing all outstanding bus transactions.
If, on completion of the Peripheral Clocks Disable, the mode transition is to the STOP mode, the MC_ME
requests the processor to enter its stopped state. The processor acknowledges its stop state request after
completing all outstanding bus transactions.
8.4.3.5
Processor and System Memory Clock Disable
If, on completion of the Processor low-power mode entry, the mode transition is to the HALT STOP mode
and the processor is in its appropriate halted or stopped state, the MC_ME disables the processor and
system memory clocks to achieve further power saving.
The clocks to the processor and system memories are unaffected for all transitions between software
running modes including DRUN, RUN0…3, and SAFE.
CAUTION
Clocks to the whole device including the processor and system memories
can be disabled in TEST mode.
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8.4.3.6
Clock sources switch-on
On completion of the Processor low-power mode entry, the MC_ME controls all clock sources that affect
the system clock based on the <clock source>ON bits of the ME_<current mode>_MC and
ME_<target mode>_MC registers. The following system clock sources are controlled at this step:
• The fast internal RC oscillator (16 MHz)
The clock sources that are required by the target mode are switched on. The duration required for the
output clocks to be stable depends on the type of source, and all further steps of mode transition depending
on one or more of these clocks waits for the stable status of the respective clocks. The availability status
of these system clocks is updated in the S_<clock source> bits of ME_GS register.
The clock sources that need to be switched off are unaffected during this process in order to not disturb the
system clock, which might require one of these clocks before switching to a different target clock.
It is also possible to automatically switch-on the FXOSC after exiting STANDBY mode, by programming
ME_DRUN_MC[FXOSC] = 1 prior to STANDBY entry. After the chip exits STANDBY mode, your
software should wait for FXOSC to be switched-on before any mode transition request in order to avoid a
mode request illegal event.
8.4.3.7
Main voltage regulator switch-on
On completion of the Target mode request, if the main voltage regulator needs to be switched on from its
off state based on the MVRON bit of the ME_<current mode>_MC and ME_<target mode>_MC
registers, the MC_ME requests the MC_PCU to power-up the regulator and waits for the output voltage
stable status in order to update the S_MVR bit of the ME_GS register.
This step is required only during the exit of the low-power modes HALT and STOP. In this step, the fast
internal RC oscillator (16 MHz) is switched on regardless of the target mode configuration, as the main
voltage regulator requires the 16 MHz int. RC osc. during power-up in order to generate the voltage status.
8.4.3.8
Flash modules switch-on
On completion of the Main voltage regulator switch-on, if a flash module needs to be switched to normal
mode from its low-power or power-down mode based on the CFLAON and DFLAON bit fields of the
ME_<current mode>_MC and ME_<target mode>_MC registers, the MC_ME requests the flash to exit
from its low-power/power-down mode. When the flash modules are available for access, the S_CFLA and
S_DFLA bit fields of the ME_GS register are updated to 11 by hardware.
If the main regulator is also off in device low-power modes, then during the exit sequence, the flash is kept
in its low-power state and is switched on only when the Main voltage regulator switch-on process has
completed.
CAUTION
It is illegal to switch the flashes from low-power mode to power-down mode
and from power-down mode to low-power mode. The MC_ME, however,
does not prevent this nor does it flag it.
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8.4.3.9
Pad outputs-on
On completion of the Main voltage regulator switch-on, if the PDO bit of the ME_<target mode>_MC
register is cleared, then
• All pad outputs are enabled to return to their previous state
• The I/O pads power sequence driver is switched on
8.4.3.10
Processor and memory clock enable
If the mode transition is from any of the low-power modes HALT or STOP to RUN0…3, the clocks to the
processor and system memories are enabled. The process of enabling these clocks is executed only after
the Flash modules switch-on process is completed.
8.4.3.11
Processor low-power mode exit
If the mode transition is from any of the low-power modes HALTSTOP to RUN0…3, the MC_ME
requests the processor to exit from its halted or stopped state. This step is executed only after the Processor
and memory clock enable process is completed.
8.4.3.12
System clock switching
Based on the SYSCLK bit field of the ME_<current mode>_MC and ME_<target mode>_MC registers,
if the target and current system clock configurations differ, the following method is implemented for clock
switching.
• The target clock configuration for the 16 MHz int. RC osc. is effective only when the S_FIRC bit
of the ME_GS register is set by hardware (i.e. the fast internal RC oscillator (16 MHz) has
stabilized).
• If the clock is to be disabled, the SYSCLK bit field should be programmed with 1111. This is
possible only in the TEST mode.
The current system clock configuration can be observed by reading the S_SYSCLK bit field of the ME_GS
register, which is updated after every system clock switching. Until the target clock is available, the system
uses the previous clock configuration.
System clock switching starts only after
• The Clock sources switch-on process has completed if the target system clock source needs to be
switched on
An overview of system clock source selection possibilities for each mode is shown in Table 8-13. A 
indicates that a given clock source is selectable for a given mode.
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Chapter 8 Mode Entry Module (MC_ME)
Table 8-13. MC_ME system clock selection overview
System
Clock
Source
16 MHz
int. RC
osc.
system
clock is
disabled
1
Mode
RESET
TEST
SAFE
DRUN
RUN0
HALT
STOP

(default)

(default)

(default)

(default)

(default)

(default)

(default)


STANDBY

(default)
disabling the system clock during TEST mode will require a reset in order to exit TEST mode
8.4.3.13
Pad switch-off
If the PDO bit of the ME_<target mode>_MC register is 1 then
• The outputs of the pads are forced to the high impedance state if the target mode is SAFE or TEST
This step is executed only after the Peripheral Clocks Disable process is completed.
8.4.3.14
Clock sources switch-off
<clock source><mode>if a given clock source<clock source>.
This step is executed only after
• System clock switching process is completed in order not to lose the current system clock during
mode transition.
8.4.3.15
Flash switch-off
Based on the CFLAON and DFLAON bit fields of the ME_<current mode>_MC and
ME_<target mode>_MC registers, if any of the flash modules is to be put in a low-power state, the
MC_ME requests the flash to enter the corresponding low-power state and waits for the deassertion of
flash ready status signal. The exact low-power mode status of the flash modules is updated in the S_CFLA
and S_DFLA bit fields of the ME_GS register. This step is executed only when Processor and System
Memory Clock Disable process is completed.
8.4.3.16
Main voltage regulator switch-off
Based on the MVRON bit of the ME_<current mode>_MC and ME_<target mode>_MC registers, if the
main voltage regulator is to be switched off, the MC_ME requests it to power down and clears the
availability status bit S_MVR of the ME_GS register.
This step is required only during the entry of low-power modes like HALT and STOP. This step is executed
only after completing the following processes:
• Flash switch-off
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•
The device consumption is less than the predefined threshold value (i.e. the S_DC bit of the
ME_GS register is 0).
8.4.3.17
Current mode update
The current mode status bit field S_CURRENT_MODE of the ME_GS register is updated with the target
mode bit field TARGET_MODE of the ME_MCTL register when:
• All the updated status bits in the ME_GS register match the configuration specified in the
ME_<target mode>_MC register
• Power sequences are done
• Clock disable/enable process is finished
• Processor low-power mode (halt/stop) entry and exit processes are finished
Software can monitor the mode transition status by reading the S_MTRANS bit of the ME_GS register.
The mode transition latency can differ from one mode to another depending on the resources’ availability
before the new mode request and the target mode’s requirements.
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Chapter 8 Mode Entry Module (MC_ME)
Start
Write ME_MCTL register
SAFE mode request
interrupt/wakeup event
Clock sources
Switch-On
Main VREG
Switch-On
PLL
Switch-On
FLASH
Switch-On
Power Domain
Switch-On
ANALOG ON
S_MTRANS = 1
Target Mode Request
Pad
Outputs -On
Peripheral Clocks
Enable
Processor
Low-Power
Entry
Processor
Low-Power
Exit
System Clock
Switching
Processor &
Memory
Clock Disable
FLASH
Switch-Off
Power Domain
Switch-Off
Main VREG
Switch-Off
N
PLL
Switch-Off
PAD
Outputs -Off
Target
STANDBY
Current Mode Update
Y
STANDBY
Request
Clock sources
Switch-Off
ANALOG OFF
Processor &
Memory
Clock Enable
DIGITAL CONTROL
Peripheral Clocks
Disable
S_MTRANS = 0
End
Figure 8-16. MC_ME transition diagram
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Chapter 8 Mode Entry Module (MC_ME)
8.4.4
Protection of mode configuration registers
While programming the mode configuration registers ME_<mode>_MC, the following rules must be
respected. Otherwise, the write operation is ignored and an invalid mode configuration interrupt may be
generated.
• FIRC must be on if the system clock is one of the following:
— The 16 MHz int. RC osc.
• The Configuration 00 for the CFLAON and DFLAON bit fields are reserved.
• MVREG must be on if any of the following is active:
— CFLASH
— DFLASH
• System clock configurations marked as reserved may not be selected.
• Configuration 1111 for the SYSCLK bit field is allowed only for the TEST mode, and only in this
case may all system clock sources be turned off.
CAUTION
If the system clock is stopped during TEST mode, the device can exit only
via a system reset.
8.4.5
Mode transition interrupts
The following are the three interrupts related to mode transition implemented in the MC_ME.
8.4.5.1
Invalid mode configuration interrupt
Whenever a write operation is attempted to the ME_<mode>_MC registers violating the protection rules
mentioned in the Section 8.4.4, Protection of mode configuration registers, the interrupt pending bit
I_ICONF of the ME_IS register is set, and an interrupt request is generated if the mask bit M_ICONF of
ME_IM register is 1.
8.4.5.2
Invalid mode transition interrupt
The mode transition request is considered invalid under the following conditions:
• If the system is in the SAFE mode and the SAFE mode request from MC_RGM is active, and if
the target mode requested is other than RESET or SAFE, then this new mode request is considered
to be invalid, and the S_SEA bit of the ME_IMTS register is set.
• If the TARGET_MODE bit field of the ME_MCTL register is written with a value different from
the specified mode values (i.e. a non existing mode), an invalid mode transition event is generated.
When such a non existing mode is requested, the S_NMA bit of the ME_IMTS register is set. This
condition is detected regardless of whether the proper key mechanism is followed while writing
the ME_MCTL register.
• If some of the device modes are disabled as programmed in the ME_ME register, their respective
configurations are considered reserved, and any access to the ME_MCTL register with those
values results in an invalid mode transition request. When such a disabled mode is requested, the
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Chapter 8 Mode Entry Module (MC_ME)
•
•
S_DMA bit of the ME_IMTS register is set. This condition is detected regardless of whether the
proper key mechanism is followed while writing the ME_MCTL register.
If the target mode is not a valid mode with respect to current mode, the mode request illegal status
bit S_MRI of the ME_IMTS register is set. This condition is detected only when the proper key
mechanism is followed while writing the ME_MCTL register. Otherwise, the write operation is
ignored.
If further new mode requests occur while a mode transition is in progress (the S_MTRANS bit of
the ME_GS register is 1), the mode transition illegal status bit S_MTI of the ME_IMTS register is
set. This condition is detected only when the proper key mechanism is followed while writing the
ME_MCTL register. Otherwise, the write operation is ignored.
NOTE
As the causes of invalid mode transitions may overlap at the same time, the
priority implemented for invalid mode transition status bits of the
ME_IMTS register in the order from highest to lowest is S_SEA, S_NMA,
S_DMA, S_MRI, and S_MTI.
As an exception, the mode transition request is not considered as invalid under the following conditions:
• A new request is allowed to enter the RESET or SAFE mode irrespective of the mode transition
status.
• As the exit of HALT and STOP modes depends on the interrupts of the system, which can occur at
any instant, these requests to return to RUN0…3 modes are always valid.
• In order to avoid any unwanted lockup of the device modes, software can abort a mode transition
by requesting the parent mode if, for example, the mode transition has not completed after a
software determined reasonable amount of time for whatever reason. The parent mode is the device
mode before a valid mode request was made.
• Self-transition requests (e.g. RUN0  RUN0) are not considered as invalid even when the mode
transition process is active (i.e. S_MTRANS is 1). During the low-power mode exit process, if the
system is not able to enter the respective RUN0…3 mode properly (i.e. all status bits of the ME_GS
register match with configuration bits in the ME_<mode>_MC register), then software can only
request the SAFE or RESET mode. It is not possible to request any other mode or to go back to the
low-power mode again.
Whenever an invalid mode request is detected, the interrupt pending bit I_IMODE of the ME_IS register
is set, and an interrupt request is generated if the mask bit M_IMODE is ME_IM register is 1.
8.4.5.3
SAFE mode transition interrupt
Whenever the system enters the SAFE mode as a result of a SAFE mode request from the MC_RGM due
to a hardware failure, the interrupt pending bit I_SAFE of the ME_IS register is set, and an interrupt is
generated if the mask bit M_SAFE of ME_IM register is 1.
The SAFE mode interrupt pending bit can be cleared only when the SAFE mode request is deasserted by
the MC_RGM (see Chapter 9, Reset Generation Module (MC_RGM), for details on how to clear a SAFE
mode request). If the system is already in SAFE mode, any new SAFE mode request by the MC_RGM
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also sets the interrupt pending bit I_SAFE. However, the SAFE mode interrupt pending bit is not set when
the SAFE mode is entered by a software request (i.e. programming of ME_MCTL register).
8.4.5.4
Mode transition complete interrupt
Whenever the system completes a mode transition fully (i.e. the S_MTRANS bit of ME_GS register
transits from 1 to 0), the interrupt pending bit I_MTC of the ME_IS register is set, and interrupt request is
generated if the mask bit M_MTC of the ME_IM register is 1. The interrupt bit I_MTC is not set when
entering low-power modes HALT and STOP in order to avoid the same event requesting the exit of these
low-power modes.
8.4.6
Application example
Figure 8-17 shows an example application flow for requesting a mode change and then waiting until the
mode transition has completed.
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Chapter 8 Mode Entry Module (MC_ME)
START of mode change
N
Config
for target mode
okay?
Write ME_<target mode>_MC register
Y
Write ME_MCTL with target mode
and key
Write ME_MCTL with target mode
and inverted key
Start timer
S_MTRANS
cleared?
N
Y
Timer
expired?
N
Stop timer
Y
mode change DONE
Write ME_MCTL with current or
SAFE mode and key
Write ME_MCTL with current or
SAFE mode and inverted key
Figure 8-17. MC_ME application example flow diagram
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Chapter 9 Reset Generation Module (MC_RGM)
Chapter 9
Reset Generation Module (MC_RGM)
9.1
9.1.1
Introduction
Overview
The reset generation module (MC_RGM) centralizes the different reset sources and manages the reset
sequence of the device. It provides a register interface and the reset sequencer. The different registers are
available to monitor and control the device reset sequence. The reset sequencer is a state machine that
controls the different phases (PHASE0, PHASE1, PHASE2, PHASE3, and IDLE) of the reset sequence
and control the reset signals generated in the system.
Figure 9-1 shows the MC_RGM block diagram.
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Chapter 9 Reset Generation Module (MC_RGM)
MC_RGM
power-on
MC_ME
Registers
Destructive
Reset Filter
Platform Interface
MC_CGM
peripherals
Reset
State
Machine
RESET
Functional
Reset Filter
core
PA[8] and PA[9]
Boot Mode
Capture
SSCM
Figure 9-1. MC_RGMblock diagram
9.1.2
Features
The MC_RGM contains the functionality for the following features:
• Destructive resets management
• Functional resets management
• Signalling of reset events after each reset sequence (reset status flags)
• Conversion of reset events to SAFE mode or interrupt request eventsChapter 8, Mode Entry
Module (MC_ME)
• Short reset sequence configuration
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Chapter 9 Reset Generation Module (MC_RGM)
•
•
9.1.3
Bidirectional reset behavior configuration
Chapter 8, Mode Entry Module (MC_ME)Boot mode capture on RESET deassertion
Modes of operation
The different reset sources are organized into two families: destructive and functional.
• A destructive reset source is associated with an event related to a critical—usually hardware—error
or dysfunction. When a destructive reset event occurs, the full reset sequence is applied to the
device starting from PHASE0. This resets the full device ensuring a safe start-up state for both
digital and analog modules. Destructive resets are
– Power-on reset
• A functional reset source is associated with an event related to a less-critical—usually
non-hardware—error or dysfunction. When a functional reset event occurs, a partial reset sequence
is applied to the device starting from PHASE1. In this case, most digital modules are reset
normally, while analog modules or specific digital modules’ (e.g. debug modules, flash modules)
state is preserved. Functional resets are
– External reset
When a reset is triggered, the MC_RGM state machine is activated and proceeds through the different
phases (i.e. PHASEn states). Each phase is associated with a particular device reset being provided to the
system. A phase is completed when all corresponding phase completion gates from either the system or
internal to the MC_RGM are acknowledged. The device reset associated with the phase is then released,
and the state machine proceeds to the next phase up to entering the IDLE phase. During this entire process,
the MC_ME state machine is held in RESET mode. Only at the end of the reset sequence, when the IDLE
phase is reached, does the MC_ME enter the DRUN mode.
Alternatively, it is possible for software to configure some reset source events to be converted from a reset
to either a SAFE mode request issued to the MC_ME or to an interrupt issued to the core (see
Section 9.3.1.4, Destructive Event Reset Disable Register (RGM_DERD), and Section 9.3.1.6,
Destructive Event Alternate Request Register (RGM_DEAR), for destructive resets, and Section 9.3.1.3,
Functional Event Reset Disable Register (RGM_FERD), and Section 9.3.1.5, Functional Event Alternate
Request Register (RGM_FEAR), for functional resets).
9.2
External signal description
The MC_RGM interfaces to the reset pin RESET and the boot mode pins PA[8] and PA[9].
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Chapter 9 Reset Generation Module (MC_RGM)
9.3
Memory map and register definition
Table 9-1. MC_RGM register description
Access
Address
Name
Description
Location
Size
Normal Supervisor
1
Test
0xC3FE RGM_FES
_4000
Functional Event Status
half-word
read
read/write1 read/write1 on page 207
0xC3FE RGM_DES
_4002
Destructive Event Status
half-word
read
read/write1 read/write1 on page 208
0xC3FE RGM_FERD
_4004
Functional Event Reset
Disable
half-word
read
read
read
on page 209
0xC3FE RGM_DERD
_4006
Destructive Event Reset
Disable
half-word
read
read
read
on page 211
0xC3FE RGM_FEAR
_4010
Functional Event Alternate half-word
Request
read
read
read
on page 212
0xC3FE RGM_DEAR
_4012
Destructive Event
Alternate Request
half-word
read
read
read
on page 213
0xC3FE RGM_FESS
_4018
Functional Event Short
Sequence
half-word
read
read
read
on page 214
0xC3FE RGM_FBRE
_401C
Functional Bidirectional
Reset Enable
half-word
read
read/write
read/write
on page 216
individual bits cleared on writing 1
NOTE
Any access to unused registers as well as write accesses to read-only
registers will:
•
•
Not change register content
Cause a transfer error
R
0
0
0
0
0
0
0
0
0
0
0
0
CHKSTOP
0xC3FE RGM_
_4000 FES /
RGM_
DES
F_EXR
Table 9-2. MC_RGM Memory Map
R
F_POR
W w1c
0
0
0
0
W w1c
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0
0
0
0
0
0
0
0
0
0
0
0
0
CHKSTOP
0xC3FE RGM_
_4004 FERD /
R
RGM_
DERD
D_EXR
Table 9-2. MC_RGM Memory Map (continued)
W
R
0
0
0
0
0
0
0
W
0xC3FE
_4008
…
0xC3FE
_400C
0
0
0
0
0
0
0
0
0
0
0
0
0
CHKSTOP
0xC3FE RGM_
_4010 FEAR /
R
RGM_
DEAR
AR_EXR
reserved
W
R
0
W
0xC3FE
_4014
SS_EXR
0
0
0
0
0
0
CHKSTOP
0
0
0
0
0
0
CHKSTOP
R
BE_EXR
0xC3FE RGM_
_4018 FESS
reserved
W
0xC3FE RGM_
_401C FBRE
R
W
0xC3FE
_4020
…
0xC3FE
_7FFC
9.3.1
reserved
Register descriptions
Unless otherwise noted, all registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes.
The bytes are ordered according to big endian. For example, the RGM_STDBY register may be accessed
as a word at address 0xC3FE_4018, as a half-word at address 0xC3FE_401A, or as a byte at address
0xC3FE_401B.
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Chapter 9 Reset Generation Module (MC_RGM)
Functional Event Status Register (RGM_FES)
R
F_EXR
Address 0xC3FE_4000
Access: User read, Supervisor read/write, Test read/write
0
0
0
0
0
0
0
0
0
0
0
0
CHKSTOP
9.3.1.1
W w1c
POR
0
0
0
0
0
0
0
0
0
0
Figure 9-2. Functional Event Status Register (RGM_FES)
This register contains the status of the last asserted functional reset sources. It can be accessed in read/write
on either supervisor mode or test mode. Register bits are cleared on write 1.
Table 9-3. Functional Event Status Register (RGM_FES) field descriptions
Field
Description
F_EXR
9.3.1.2
Flag for External Reset
0 No external reset event has occurred since either the last clear or the last destructive reset
assertion
1 An external reset event has occurred
Destructive Event Status Register (RGM_DES)
R
F_POR
Address 0xC3FE_4002
Access: User read, Supervisor read/write, Test read/write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W w1c
POR
1
0
0
0
0
0
Figure 9-3. Destructive Event Status Register (RGM_DES)
This register contains the status of the last asserted destructive reset sources. It can be accessed in
read/write on either supervisor mode or test mode. Register bits are cleared on write 1.
Table 9-4. Destructive Event Status Register (RGM_DES) field descriptions
Field
Description
F_POR
Flag for Power-On reset
0 No power-on event has occurred since the last clear (due to either a software clear or a
low-voltage detection)
1 A power-on event has occurred
NOTE
The F_POR flag is also set when a low-voltage is detected on the 1.2 V
supply, even if the low voltage is detected after power-on has completed.
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The F_LVD27 flag may still have the value 0 after a dip has occurred on the
2.7 V supply during a non-monotonic power-on sequence. The F_POR flag
will, however, still be set in this case as expected after each power-on
sequence.
In contrast to all other reset sources, the 1.2 V low-voltage detected (power
domain #0) event is captured on its deassertion. Therefore, the status bit
F_LVD12_PD0 is also asserted on the reset’s deassertion. In case an
alternate event is selected, the SAFE mode or interrupt request are similarly
asserted on the reset’s deassertion.
9.3.1.3
Functional Event Reset Disable Register (RGM_FERD)
Access: User read, Supervisor read, Test read
CHKSTOP
Address 0xC3FE_4004
D_EXR
R
0
0
0
0
0
0
0
0
0
0
0
0
0
W
POR
0
0
0
0
0
0
0
0
0
Figure 9-4. Functional Event Reset Disable Register (RGM_FERD)
This register provides dedicated bits to disable functional reset sources.When a functional reset source is
disabled, the associated functional event will trigger either a SAFE mode request or an interrupt request
(see Section 9.3.1.5, Functional Event Alternate Request Register (RGM_FEAR)). It can be accessed in
read/write in either supervisor mode or test mode. It can be accessed in read only in user mode. Each byte
can be written only once after power-on reset.
Table 9-5. Functional Event Reset Disable Register (RGM_FERD) field descriptions
Field
D_EXR
9.3.1.4
Description
Disable External Reset
0 An external reset event triggers a reset sequence
1 An external reset event generates a SAFE mode request
Destructive Event Reset Disable Register (RGM_DERD)
Address 0xC3FE_4006
R
Access: Read
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
POR
0
0
0
0
0
Figure 9-5. Destructive Event Reset Disable Register (RGM_DERD)
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Chapter 9 Reset Generation Module (MC_RGM)
This register provides dedicated bits to disable particular destructive reset sources. When a destructive
reset source is disabled, the associated destructive event will trigger either a safe mode request or an
interrupt request (see Section 9.3.1.6, Destructive Event Alternate Request Register (RGM_DEAR)).
9.3.1.5
Functional Event Alternate Request Register (RGM_FEAR)
0
0
0
0
0
0
0
0
0
0
0
0
0
CHKSTOP
R
Access: User read, Supervisor read, Test read
AR_EXR
Address 0xC3FE_4010
W
POR
0
0
0
0
0
0
0
0
0
Figure 9-6. Functional Event Alternate Request Register (RGM_FEAR)
This register defines an alternate request to be generated when a reset on a functional event has been
disabled. The alternate request can be either a SAFE mode request to MC_ME or an interrupt request to
the system. It can be accessed in read/write in either supervisor mode or test mode. It can be accessed in
read only in user mode.
Table 9-7. Functional Event Alternate Request Register (RGM_FEAR) field descriptions
Field
Description
AR_EXR
9.3.1.6
Alternate Request for External Reset
0 Generate a SAFE mode request on an external reset event if the reset is disabled
1 Generate an interrupt request on an external reset event if the reset is disabled
Destructive Event Alternate Request Register (RGM_DEAR)
Address: 0xC3FE_4012
R
Access: Read
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
POR
0
0
0
0
0
Figure 9-7. Destructive Event Alternate Request Register (RGM_DEAR)
This register defines an alternate request to be generated when a reset on a destructive event has been
disabled. The alternate request can be either a SAFE mode request to MC_ME or an interrupt request to
the system.
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9.3.1.7
Functional Event Short Sequence Register (RGM_FESS)
0
0
0
0
0
0
0
0
0
0
0
0
0
CHKSTOP
R
Access: User read, Supervisor read, Test read
SS_EXR
Address 0xC3FE_4018
W
POR
0
0
0
0
0
0
0
0
0
Figure 9-8. Functional Event Short Sequence Register (RGM_FESS)
This register defines which reset sequence will be done when a functional reset sequence is triggered. The
functional reset sequence can either start from PHASE1 or from PHASE3, skipping PHASE1 and
PHASE2.
NOTE
This could be useful for fast reset sequence, for example to skip flash reset.
It can be accessed in read/write in either supervisor mode or test mode. It can be accessed in read in user
mode.
Table 9-9. Functional Event Short Sequence Register (RGM_FESS) field descriptions
Field
Description
SS_EXR
Short Sequence for External Reset
0 The reset sequence triggered by an external reset event will start from PHASE1
1 The reset sequence triggered by an external reset event will start from PHASE3, skipping
PHASE1 and PHASE2
NOTE
This register is reset on any enabled destructive or functional reset event.
Functional Bidirectional Reset Enable Register (RGM_FBRE)
R
Access: User read, Supervisor read/write, Test read/write
BE_EXR
Address 0xC3FE_401C
0
0
0
0
0
0
0
0
0
0
0
0
0
CHKSTOP
9.3.1.8
W
POR
0
0
0
0
0
0
0
0
0
Figure 9-9. Functional Bidirectional Reset Enable Register (RGM_FBRE)
This register enables the generation of an external reset on functional reset. It can be accessed in read/write
in either supervisor mode or test mode. It can be accessed in read in user mode.
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Chapter 9 Reset Generation Module (MC_RGM)
Table 9-10. Functional Bidirectional Reset Enable Register (RGM_FBRE) field descriptions
Field
Description
BE_EXR
9.4
Bidirectional Reset Enable for External Reset
0 RESET is asserted on an external reset event if the reset is enabled
1 RESET is not asserted on an external reset event
Functional description
9.4.1
Reset state machine
The main role of MC_RGM is the generation of the reset sequence, which ensures that the correct parts of
the device are reset based on the reset source event. This is summarized in Table 9-11
Table 9-11. MC_RGM Reset Implications
Source
What Gets Reset
External Reset
Assertion
Boot Mode
Capture
Power-on Reset
All
Yes
Yes
Destructive reset
All except some clock/reset management
Yes
Yes
External reset
All except some clock/reset management and
debug
Yes
Yes
Functional resets
All except some clock/reset management and
debug
Shortened functional resets3 Flip-flops except some clock/reset management
Programmable1 Programmable2
Programmable1 Programmable2
1
the assertion of the external reset is controlled via the RGM_FBRE register
the boot mode is captured if the external reset is asserted
3 the short sequence is enabled via the RGM_FESS register
2
NOTE
JTAG logic has its own independent reset control and is not controlled by
the MC_RGM in any way.
The reset sequence is comprised of five phases managed by a state machine, which ensures that all phases
are correctly processed through waiting for a minimum duration and until all processes that need to occur
during that phase have been completed before proceeding to the next phase.
The state machine used to produce the reset sequence is shown in Figure 9-10.
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Chapter 9 Reset Generation Module (MC_RGM)
x
power-on
reset
PHASE0
power-up has completed
fast internal RC oscillator (16 MHz) clock is running
duration  3 fast internal RC oscillator (16 MHz) clock cycles
FIRC stable, VREG voltage okay done
enabled
non-shortened
externalreset1
PHASE1
duration  10 fast internal RC oscillator (16 MHz) clock cycles
PHASE2
durationfast internal RC oscillator (16 MHz) clock cycles
code and data flash initialization done
PHASE3
enabled
shortened
externalfunctio
nal reset
duration 40fast internal RC oscillator (16 MHz) clock cycles
code and data flash initialization done
RESET released
IDLE
Figure 9-10. MC_RGM State Machine
Figure 9-11 describes how the device behaves during the startup.
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Chapter 9 Reset Generation Module (MC_RGM)
Figure 9-11. Reset configuration timing
9.4.1.1
PHASE0 phase
This phase is entered immediately from any phase on a power-on or enabled destructive reset event. The
reset state machine exits PHASE0 and enters PHASE1 on verification of the following:
• Power-up has completed
• Fast internal RC oscillator (16 MHz) clock is running
• All enabled destructive resets have been processed
• All processes that need to be done in PHASE0 are completed
• A minimum of 3 fast internal RC oscillator (16 MHz) clock cycles have elapsed since power-up
completion and the last enabled destructive reset event
9.4.1.2
PHASE1 phase
This phase is entered either on exit from PHASE0 or immediately from PHASE2, PHASE3, or IDLE on
a non-masked external or functional reset event if it has not been configured to trigger a short sequence.
The reset state machine exits PHASE1 and enters PHASE2 on verification of the following:
• All enabled, non-shortened functional resets have been processed
• A minimum of 10 fast internal RC oscillator (16 MHz) clock cycles have elapsed since the last
enabled external or non-shortened functional reset event
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9.4.1.3
PHASE2 phase
This phase is entered on exit from PHASE1. The reset state machine exits PHASE2 and enters PHASE3
on verification of the following:
• All processes that need to be done in PHASE2 are completed
• A minimum of 8 fast internal RC oscillator (16 MHz) clock cycles have elapsed since entering
PHASE2
9.4.1.4
PHASE3 phase
This phase is a entered either on exit from PHASE2 or immediately from IDLE on an enabled, shortened
functional reset event. The reset state machine exits PHASE3 and enters IDLE on verification of the
following:
• All processes that need to be done in PHASE3 are completed
• A minimum of 40 fast internal RC oscillator (16 MHz) clock cycles have elapsed since the last
enabled, shortened functional reset event
9.4.1.5
IDLE phase
This is the final phase, and is entered on exit from PHASE3. When this phase is reached, the MC_RGM
releases control of the system to the platform and waits for new reset events that can trigger a reset
sequence.
9.4.2
Destructive resets
A destructive reset indicates that an event has occurred, after which critical register or memory content can
no longer be guaranteed.
The status flag associated with a given destructive reset event (RGM_DES.F_<destructive reset> bit) is
set when the destructive reset is asserted and the power-on reset is not asserted. It is possible for multiple
status bits to be set simultaneously, and it is software’s responsibility to determine which reset source is
the most critical for the application.
The destructive reset can be optionally disabled by writing bit RGM_DERD.D_<destructive reset>.
NOTE
The RGM_DERD register can be written only once between two power-on
reset events.
The device’s low-voltage detector threshold ensures that, when 1.2 V low-voltage detected (power domain
#0) is enabled, the supply is sufficient to have the destructive event correctly propagated through the digital
logic. Therefore, if a given destructive reset is enabled, the MC_RGM ensures that the associated reset
event will be correctly triggered to the full system. However, if the given destructive reset is disabled and
the voltage goes below the digital functional threshold, functionality can no longer be ensured, and the
reset may or may not be asserted.
An enabled destructive reset will trigger a reset sequence starting from the beginning of PHASE0.
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Chapter 9 Reset Generation Module (MC_RGM)
9.4.3
External reset
The MC_RGM manages the external reset coming from RESET. The detection of a falling edge on RESET
will start the reset sequence from the beginning of PHASE1.
The status flag associated with the external reset falling edge event (RGM_FES.F_EXR bit) is set when
the external reset is asserted and the power-on reset is not asserted.
The external reset can optionally be disabled by writing bit RGM_FERD.D_EXR.
NOTE
The RGM_FERD register can be written only once between two power-on
reset events.
An enabled external reset will normally trigger a reset sequence starting from the beginning of PHASE1.
Nevertheless, the RGM_FESS register enables the further configuring of the reset sequence triggered by
the external reset. When RGM_FESS.SS_EXR is set, the external reset will trigger a reset sequence
starting directly from the beginning of PHASE3, skipping PHASE1 and PHASE2. This can be useful
especially when an external reset should not reset the flash.
9.4.4
Functional resets
A functional reset indicates that an event has occurred, after which it can be guaranteed that critical register
and memory content is still intact.
The status flag associated with a given functional reset event (RGM_FES.F_<functional reset> bit) is set
when the functional reset is asserted and the power-on reset is not asserted. It is possible for multiple status
bits to be set simultaneously, and it is software’s responsibility to determine which reset source is the most
critical for the application.
The functional reset can be optionally disabled by software writing bit
RGM_FERD.D_<functional reset>.
NOTE
The RGM_FERD register can be written only once between two power-on
reset events.
An enabled functional reset will normally trigger a reset sequence starting from the beginning of PHASE1.
Nevertheless, the RGM_FESS register enables the further configuring of the reset sequence triggered by
a functional reset. When RGM_FESS.SS_<functional reset> is set, the associated functional reset will
trigger a reset sequence starting directly from the beginning of PHASE3, skipping PHASE1 and PHASE2.
This can be useful especially in case a functional reset should not reset the flash module.
See Chapter 8, Mode Entry Module (MC_ME), for details on the STANDBY and DRUN modes.
9.4.5
Alternate event generation
The MC_RGM provides alternative events to be generated on reset source assertion. When a reset source
is asserted, the MC_RGM normally enters the reset sequence. Alternatively, it is possible for each reset
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Chapter 9 Reset Generation Module (MC_RGM)
source event (except the power-on reset event) to be converted from a reset to either a SAFE mode request
issued to the MC_ME or to an interrupt request issued to the core.
Alternate event selection for a given reset source is made via the RGM_F/DERD and RGM_F/DEAR
registers, as shown in Table 9-12.
Table 9-12. MC_RGM alternate event selection
RGM_F/DERD
bit value
RGM_F/DEAR
bit value
0
X
Reset
1
0
SAFE mode request
1
1
Interrupt request
Generated event
The alternate event is cleared by deasserting the source of the request (that is, at the reset source that caused
the alternate request) and also clearing the appropriate RGM_F/DES status bit.
NOTE
Alternate requests (SAFE mode as well as interrupt requests) are generated
asynchronously.
NOTE
If a masked destructive reset event that is configured to generate a SAFE
mode/interrupt request occurs during PHASE0, it is ignored, and the
MC_RGM will not send any safe mode/interrupt request to the MC_ME.
The same is true for masked functional reset events during PHASE1.
9.4.6
Boot mode capturing
The MC_RGM samples PA[9:8] whenever RESET is asserted until five FIRC (16 MHz internal RC
oscillator) clock cycles before its deassertion edge. The result of the sampling is used at the beginning of
reset PHASE3 for boot mode selection and is retained after RESET has been deasserted for subsequent
boots after reset sequences during which RESET is not asserted.
NOTE
In order to ensure that the boot mode is correctly captured, the application
needs to apply the valid boot mode value the entire time that RESET is
asserted.
RESET can be asserted as a consequence of the internal reset generation.
This will force re-sampling of the boot mode pins. (See Table 9-11 for
details.)
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Chapter 10 Power Control Unit (MC_PCU)
Chapter 10
Power Control Unit (MC_PCU)
10.1
10.1.1
Introduction
Overview
The power control unit (MC_PCU) is used to reduce the overall SoC power consumption. Power can be
saved by disconnecting parts of the SoC from the power supply via a power switching device. The SoC is
grouped into multiple parts having this capability, which are called power domains.
When a power domain is disconnected from the supply, the power consumption is reduced to zero in that
domain. Any status information of such a power domain is lost. When reconnecting a power domain to the
supply voltage, the domain draws an increased current until the power domain reaches its operational
voltage.
Power domains are controlled on a device mode basis. For each mode, software can configure whether a
power domain is connected to the supply voltage (power-up state) or disconnected (power-down state).
Maximum power saving is reached by entering the STANDBY mode.
On each mode change request, the MC_PCU evaluates the power domain settings in the power domain
configuration registers and initiates a power-down or a power-up sequence for each individual power
domain. The power-up/down sequences are handled by finite state machines to ensure a smooth and safe
transition from one power state to the other.
Exiting the STANDBY mode can only be done via a system wakeup event as all power domains other than
power domain #0 are in the power-down state.
In addition, the MC_PCU acts as a bridge for mapping the VREG peripheral to the MC_PCU address
space.
Figure 10-1 shows the MC_PCU block diagram.
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Chapter 10 Power Control Unit (MC_PCU)
MC_PCU
MC_ME
FIRC
Registers
Platform Interface
VREG
core
Power Domain
State Machines
power
domains
WKPU
Figure 10-1. MC_PCU Block Diagram
10.1.2
Features
The MC_PCU includes the following features:
• Support for 1012345789 power domains
• Support for device modes RESET, DRUN, SAFE, TEST, RUN0…3, HALT, STOP, and
STANDBY (for further mode details, please see)
• Power states updating on each mode change and on system wakeup
• A handshake mechanism for power state changes thus guaranteeing operable voltage
10.1.3
Modes of operation
The MC_PCU is available in all device modes.
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Chapter 10 Power Control Unit (MC_PCU)
10.2
External signal description
The MC_PCU has no connections to any external pins.
10.3
Memory map and register definition
Table 10-1. MC_PCU register description
Access
Address
Name
Description
Size
Location
Normal Supervisor
Test
0xC3FE PCU_PCONF0
_8000
Power Domain #0
Configuration
word
read
read
read
on page 199
0xC3FE PCU_PCONF1
_8004
Power Domain #1
Configuration
word
read
read
read
on page 200
0xC3FE PCU_PCONF2
_8008
Power Domain #2
Configuration
word
read
read/write
read/write
on page
201on page
201
0xC3FE PCU_PCONF3
_800C
Power Domain #3
Configuration
word
read
read/write
read/write on page 201
0xC3FE PCU_PCONF4
_8010
Power Domain #4
Configuration
word
read
read/write
read/write on page 201
0xC3FE PCU_PCONF5
_8014
Power Domain #5
Configuration
word
read
read/write
read/write on page 201
0xC3FE PCU_PCONF6
_8018
Power Domain #6
Configuration
word
read
read/write
read/write on page 201
0xC3FE PCU_PCONF7
_801C
Power Domain #7
Configuration
word
read
read/write
read/write on page 201
0xC3FE PCU_PCONF8
_8020
Power Domain #8
Configuration
word
read
read/write
read/write on page 201
0xC3FE PCU_PCONF9
_8024
Power Domain #9
Configuration
word
read
read/write
read/write on page 201
0xC3FE PCU_PCONF10 Power Domain #10
_8028
Configuration
word
read
read/write
read/write on page 201
0xC3FE PCU_PCONF11 Power Domain #11
_802C
Configuration
word
read
read/write
read/write on page 201
0xC3FE PCU_PCONF12 Power Domain #12
_8030
Configuration
word
read
read/write
read/write on page 201
0xC3FE PCU_PSTAT
_8040
word
read
read
Power Domain Status
Register
read
on page 202
NOTE
Any access to unused registers as well as write accesses to read-only
registers will:
•
Not change register content
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Chapter 10 Power Control Unit (MC_PCU)
•
Cause a transfer error
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
STBY0
0
0
STOP
0
HALT
RUN3
RUN2
RUN1
RUN0
DRUN
SAFE
TEST
RST
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
STBY0
0
0
STOP
0
HALT
RUN3
RUN2
RUN1
RUN0
DRUN
SAFE
TEST
RST
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
STOP
0
HALT
RUN3
RUN2
RUN1
RUN0
DRUN
SAFE
TEST
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
STOP
R
STBY0
0xC3FE PCU_PCONF0
_8000
STBY0
Table 10-2. MC_PCU memory map
0
W
R
W
0xC3FE PCU_PCONF1
_8004
R
W
R
W
R
R
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RST
0
0
0
0
PD0
0
TEST
0
PD1
PD2
0
SAFE
DRUN
RUN1
0
RUN2
0
RUN3
R
PD3
W
HALT
0xC3FE PCU_PCONF1012
_800C 3456789
RST
W
RUN0
0xC3FE PCU_PCONF2101
_8008 2456789
W
0xC3FE
_800123
048C
…
0xC3FE
_803C
0xC3FE PCU_PSTAT
_8040
reserved
R
W
R
W
0x044
…
0x07C
reserved
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Chapter 10 Power Control Unit (MC_PCU)
Table 10-2. MC_PCU memory map (continued)
0xC3FE
_8080
…
0xC3FE
_80FC
0xC3FE
_8100
…
0xC3FE
_BFFC
10.3.1
reserved
Register descriptions
All registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes. The bytes are ordered
according to big endian. For example, the PD0 field of the PCU_PSTAT register may be accessed as a word
at address 0xC3FE_8040, as a half-word at address 0xC3FE_8042, or as a byte at address 0xC3FE_8043.
10.3.1.1
Power Domain #0 Configuration Register (PCU_PCONF0)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
STOP
0
HALT
RUN3
RUN2
RUN1
RUN0
DRUN
SAFE
TEST
RST
R
Access: User read, Supervisor read, Test read
STBY0
Address 0xC3FE_8000
0
0
1
0
0
1
0
1
1
1
1
1
1
1
1
1
W
Reset
R
W
Reset
Figure 10-2. Power Domain #0 Configuration Register (PCU_PCONF0)
This register defines for power domain #0 whether it is on or off in each device mode. As power domain
#0 is the always-on power domain (and includes the MC_PCU), none of its bits are programmable. This
register is available for completeness reasons.
Table 10-3. Power Domain Configuration Register field descriptions
Field
Description
RST
Power domain control during RESET mode
0 Power domain off
1 Power domain on
TEST
Power domain control during TEST mode
0 Power domain off
1 Power domain on
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Chapter 10 Power Control Unit (MC_PCU)
Table 10-3. Power Domain Configuration Register field descriptions (continued)
Field
Description
SAFE
Power domain control during SAFE mode
0 Power domain off
1 Power domain on
DRUN
Power domain control during DRUN mode
0 Power domain off
1 Power domain on
RUN0
Power domain control during RUN0 mode
0 Power domain off
1 Power domain on
RUN1
Power domain control during RUN1 mode
0 Power domain off
1 Power domain on
RUN2
Power domain control during RUN2 mode
0 Power domain off
1 Power domain on
RUN3
Power domain control during RUN3 mode
0 Power domain off
1 Power domain on
HALT
Power domain control during HALT mode
0 Power domain off
1 Power domain on
STOP
Power domain control during STOP mode
0 Power domain off
1 Power domain on
STBY0
Power domain control during STANDBY mode
0 Power domain off
1 Power domain on
10.3.1.2
Power Domain #1 Configuration Register (PCU_PCONF1)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
HALT
RUN3
RUN2
RUN1
RUN0
DRUN
SAFE
TEST
RST
Access: User read, Supervisor read, Test read
0
STOP
R
STBY0
Address 0xC3FE_8004
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
W
Reset
R
W
Reset
Figure 10-3. Power Domain #1 Configuration Register (PCU_PCONF1)
This register defines for power domain #1 whether it is on or off in each device mode. The bit field
description is the same as in Table 10-3. As the platform, clock generation, and mode control reside in
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Chapter 10 Power Control Unit (MC_PCU)
power domain #1, this power domain is only powered down during the STANDBY mode. Therefore, none
of the bits is programmable. This register is available for completeness reasons.
The difference between PCU_PCONF0 and PCU_PCONF1 is the reset value of the STBY0 bit: During
the STANDBY mode, power domain #1 is disconnected from the power supply, and therefore
PCU_PCONF1.STBY0 is always 0. Power domain #0 is always on, and therefore PCU_PCONF0.STBY0
is 1.
For further details about STANDBY mode, please see Section 10.4.4.2, STANDBY mode transition.
10.3.1.3
Power Domain #2 Configuration Register (PCU_PCONF2)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
0
0
0
0
STOP0
0
HALT0
RUN3
RUN2
RUN1
RUN0
DRUN
SAFE
TEST
R
Access: User read/write, Supervisor read/write, Test read/write
STBY0
Address 0xC3FE_8008
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
W
Reset
RST
W
1
Figure 10-4. Power Domain #2 Configuration Register (PCU_PCONF2)
This register defines for power domain #2 whether it is on or off in each device mode. The bit field
description is the same as in Table 10-3.
10.3.1.4
Power Domain #2…10123456789 Configuration Registers
(PCU_PCONF2…10123456789)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
0
0
0
0
STOP
0
HALT
RUN3
RUN2
RUN1
RUN0
DRUN
SAFE
TEST
R
Access: User read/write, Supervisor read/write, Test read/write
STBY0
Address 0xC3FE_8008
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
W
Reset
RST
W
1
Figure 10-5. Power Domain #2 Configuration Register (PCU_PCONF2)
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Chapter 10 Power Control Unit (MC_PCU)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
STOP
0
HALT
RUN3
RUN2
RUN1
RUN0
DRUN
SAFE
TEST
R
Access: User read/write, Supervisor read/write, Test read/write
STBY0
Address 0xC3FE_800C
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
Reset
R
W
Reset
RST
W
1
Figure 10-6. Power Domain #3 Configuration Register (PCU_PCONF3)
These registers define for each power domain #2 through #10123456789 whether it is on or off in each
device mode. The bit field description is the same as in Table 10-3.
10.3.1.5
Power Domain Status Register (PCU_PSTAT)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PD2
PD1
PD0
R
Access: User read, Supervisor read, Test read
PD3
Address 0xC3FE_8040
0
0
0
10
10
10
10
10
10
10
10
10
10
10
1
1
W
Reset
R
W
Reset
Figure 10-7. Power Domain Status Register (PCU_PSTAT)
This register reflects the power status of all available power domains.
Table 10-4. Power Domain Status Register (PCU_PSTAT) field descriptions
Field
PDn
10.4
10.4.1
Description
Power status for power domain #n
0 Power domain is inoperable
1 Power domain is operable
Functional description
General
The MC_PCU controls all available power domains on a device mode basis. The PCU_PCONFn registers
specify during which system/user modes a power domain is powered up. The power state for each
individual power domain is reflected by the bits in the PCU_PSTAT register.
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Chapter 10 Power Control Unit (MC_PCU)
On a mode change, the MC_PCU evaluates which power domain(s) must change power state. The power
state is controlled by a state machine (FSM) for each individual power domain (see Figure 10-8), which
ensures a clean and safe state transition.
10.4.2
Reset / Power-On Reset
After any reset, the SoC will transition to the RESET mode during which all power domains are powered
up (see Chapter 8, Mode Entry Module (MC_ME)). Once the reset sequence has been completed, the
DRUN mode is entered and software can begin the MC_PCU configuration.
10.4.3
MC_PCU configuration
Per default, all power domains are powered in all modes other than STANDBY. Software can change the
configuration for each power domain on a mode basis by programming the PCU_PCONFn registers.
Each power domain that is powered down is held in a reset state. Read/write accesses to peripherals in
those power domains will result in a transfer error.
10.4.4
Mode transitions
On a mode change requested by the MC_ME, the MC_PCU evaluates the power configurations for all
power domains. It compares the settings in the PCU_PCONFn registers for the new mode with the settings
for the current mode. If the configuration for a power domain differs between the modes, a power state
change request is generated. These requests are handled by a finite state machine to ensure a smooth and
safe transition from one power state to another.
10.4.4.1
DRUN, SAFE, TEST, RUN0…3, HALT, and STOP mode transition
The DRUN, SAFE, TEST, RUN0…3, HALT, and STOP modes allow an increased power saving. The
level of power saving is software-controllable via the settings in the PCU_PCONFn registers for power
domain #2 onwards. The settings for power domains #0 and #1 cannot be changed. Therefore, power
domains #0 and #1 remain connected to the power supply for all modes beside STANDBY.
Figure 10-8 shows an example for a mode transition from RUN0 to HALT and back, which will result in
power domain #2 being powered down during the HALT mode. In this case, PCU_PCONF2. HALT is
programmed to be 0.
When the MC_PCU receives the mode change request to HALT mode, it starts its power-down phase.
During the power-down phase, clocks are disabled and the reset is asserted, resulting in a loss of all
information for this power domain.
Then the power domain is disconnected from the power supply (power-down state).
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Chapter 10 Power Control Unit (MC_PCU)
new mode
requested by ME
RUN0
HALT
RUN0
PSTAT.PD2
voltage in
power domain #2
current mode
RUN0
power-up state
Notes:
power-down
phase
HALT
power-down state
RUN0
power-up phase
power-up state
Not drawn to scale; PCONF2.RUN0 = 1; PCONF2.HALT = 0
Figure 10-8. MC_PCU Events During Power Sequences (non-STANDBY mode)
When the MC_PCU receives a mode change request to RUN0, it starts its power-up phase if
PCU_PCONF2.RUN0 is 1. The power domain is reconnected to the power supply, and the voltage in
power domain #2 will increase slowly. Once the voltage of power domain #2 is within an operable range,
its clocks are enabled, and its resets are deasserted (power-up state).
NOTE
It is possible that, due to a mode change, power-up is requested before a
power domain completed its power-down sequence. In this case, the
information in that power domain is lost.
10.4.4.2
STANDBY mode transition
STANDBY offers the maximum power saving. The level of power saving is software-controllable via the
settings in the PCU_PCONFn registers for power domain #2 onwards. Power domain #0 stays connected
to the power supply while power domain #1 is disconnected from the power supply. Among others, power
domain #1 contains the platform and the MC_ME. Therefore this mode differs from all other user/system
modes.
Once STANDBY is entered it can only be left via a system wakeup. On exiting the STANDBY mode, all
power domains are powered up according to the settings in the PCU_PCONFn registers, and the DRUN
mode is entered. In DRUN mode, at least power domains #0 and #1 are powered.
Figure 10-9 shows an example for a mode transition from RUN0 to STANDBY to DRUN. All power
domains that have PCU_PCONFn.STBY0 cleared will enter power-down phase. In this example only
power domain #1 will be disabled during STANDBY mode.
When the MC_PCU receives the mode change request to STANDBY mode it starts the power down phase
for power domain #1. During the power down phase, clocks are disabled and reset is asserted resulting in
a loss of all information for this power domain. Then the power domain is disconnected from the power
supply (power-down state).
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Chapter 10 Power Control Unit (MC_PCU)
new mode
requested by ME
RUN0
STANDBY
Mode set due to reset being asserted to power domain #1
PSTAT.PD1
voltage in
power domain #1
wakeup request
current mode
RUN0
power-up state
power-down
phase
STANDBY
power-down state
DRUN
power-up phase
power-up state
Notes:
Not drawn to scale; PCONF1.RUN0 = 1; PCONF1.STBY0 = 0
Figure 10-9. MC_PCU Events During Power Sequences (STANDBY mode)
When the MC_PCU receives a system wakeup request, it starts the power-up phase. The power domain is
reconnected to the power supply and the voltage in power domain #1 will increase slowly. Once the
voltage is in an operable range, clocks are enabled and the reset is deasserted (power-up state).
NOTE
It is possible that due to a wakeup request, power-up is requested before a
power domain completed its power-down sequence. In this case, the
information in that power domain is lost.
10.4.4.3
Power saving for memories during STANDBY mode
All memories that are not powered down during STANDBY mode automatically enter a power saving
state. No software configuration is required to enable this power saving state. While a memory is residing
in this state an increased power saving is achieved. Data in the memories is retained.
10.5
Initialization information
To initialize the MC_PCU, the registers PCU_PCONF2…3 should be programmed. After programming
is done, those registers should no longer be changed.
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Chapter 10 Power Control Unit (MC_PCU)
10.6
10.6.1
Application information
STANDBY Mode Considerations
STANDBY offers maximum power saving possibility. But power is only saved during the time a power
domain is disconnected from the supply. Increased power is required when a power domain is reconnected
to the power supply. Additional power is required during restoring the information (for example, in the
platform).
Care should be taken that the time during which the SoC is operating in STANDBY mode is significantly
longer than the required time for restoring the information.
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Chapter 11 Voltage Regulators and Power Supplies
Chapter 11
Voltage Regulators and Power Supplies
11.1
Voltage regulators
The power blocks provide a 1.2 V digital supply to the internal logic of the device. The main supply is
3.3 V–5 V ±10% and digital/regulated output supply is 1.2 V ±10%. The voltage regulator used in
MPC5606BK comprises three regulators.
• High power regulator (HPREG)
• Low power regulator (LPREG)
• Ultra low power regulator (ULPREG)
The HPREG and LPREG regulators are switched off during STANDBY mode to save consumption from
the regulator itself. In STANDBY mode, the supply is provided by the ULPREG regulator.
In STOP mode, the user can configure the HPREG regulator to switch off (see Chapter 8, Mode Entry
Module (MC_ME)). In this case, when current is low enough to be handled by LPREG alone, the HPREG
regulator is switched off and the supply is provided by the LPREG regulator.
The internal voltage regulator requires an external capacitance (CREG) to be connected to the device in
order to provide a stable low voltage digital supply to the device. Capacitances should be placed on the
board as near as possible to the associated pins.
The regulator has two digital domains, one for the high power regulator (HPREG) and the low power
regulator (LPREG) called “High Power domain” and another one for the ultra low power regulator
(ULPREG) called “Standby domain.” For each domain there is a low voltage detector for the 1.2 V output
voltage. Additionally there are two low voltage detectors for the main/input supply with different
thresholds, one at the 3.3 V level and the other one at the 5 V level.
11.1.1
High power regulator (HPREG)
The HPREG converts the 3.3 V–5 V input supply to a 1.2 V digital supply. For more information, see the
voltage regulator electrical characteristics section of the data sheet.
The regulator can be switched off by software. Refer to the main voltage regulator control bit (MVRON)
of the mode configuration registers in Chapter 8, Mode Entry Module (MC_ME).
11.1.2
Low power regulator (LPREG)
The LPREG generates power for the device in the STOP mode, providing the output supply of 1.2 V. It
always sees the minimum external capacitance. The control part of the regulator can be used to disable the
low power regulator. It is managed by MC_ME.
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Chapter 11 Voltage Regulators and Power Supplies
11.1.3
Ultra low power regulator (ULPREG)
The ULPREG generates power for the standby domain as well as a part of the main domain and might or
might not see the external capacitance. The control circuit of ULPREG can be used to disable the ultra low
power regulator by software: This action is managed by MC_ME.
11.1.4
LVDs and POR
There are three kinds of LVD available:
1. LVD_MAIN for the 3.3 V–5 V input supply with thresholds at approximately 3 V level1
2. LVD_MAIN5 for the 3.3 V–5 V input supply with threshold at approximately 4.5 V level1
3. LVD_DIG for the 1.2 V output voltage
The LVD_MAIN and LVD_MAIN5 sense the 3.3 V–5 V power supply for CORE, shared with IO ring
supply and indicate when the 3.3 V–5 V supply is stabilized.
Two LVD_DIGs are provided in the design. One LVD_DIG is placed in the high power domain and senses
the HPREG/LPREG output notifying that the 1.2 V output is stable. The other LVD_DIG is placed in the
standby domain and senses the standby 1.2 V supply level notifying that the 1.2 V output is stable. The
reference voltage used for all LVDs is generated by the low power reference generator and is trimmed for
LVD_DIG, using the bits LP[4:7]. Therefore, during the pre-trimming period, LVD_DIG exhibits higher
thresholds, whereas during post trimming, the thresholds come in the desired range. Power-down pins are
provided for LVDs. When LVDs are power-down, their outputs are pulled high.
POR is required to initialize the device during supply rise. POR works only on the rising edge of the main
supply. To ensure its functioning during the following rising edge of the supply, it is reset by the output of
the LVD_MAIN block when main supply reaches below the lower voltage threshold of the LVD_MAIN.
POR is asserted on power-up when Vdd supply is above VPORUP min (refer to data sheet for details). It
will be released only after Vdd supply is above VPORH (refer to data sheet for details). Vdd above VPORH
ensures power management module including internal LVDs modules are fully functional.
11.1.5
VREG digital interface
The voltage regulator digital interface provides the temporization delay at initial power-up and at exit from
low-power modes. A signal, indicating that Ultra Low Power domain is powered, is used at power-up to
release reset to temporization counter. At exit from low-power modes, the power-down for high power
regulator request signal is monitored by the digital interface and used to release reset to the temporization
counter. In both cases, on completion of the delay counter, a end-of-count signal is released, it is gated with
an other signal indicating main domain voltage fine in order to release the VREGOK signal. This is used
by MC_RGM to release the reset to the device. It manages other specific requirements, like the transition
between high power/low power mode to ultra low power mode avoiding a voltage drop below the
permissible threshold limit of 1.08 V.
The VREG digital interface also holds control register to mask 5 V LVD status coming from the voltage
regulator at the power-up.
1. See section “Voltage monitor electrical characteristics” of the data sheet for detailed information about this voltage value.
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Chapter 11 Voltage Regulators and Power Supplies
11.1.6
Register description
The VREG_CTL register is mapped to the MC_PCU address space as described in Chapter 10, Power
Control Unit (MC_PCU).
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5V_LVD_MASK
Address: 0xC3FE_8080
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
W
Reset
R
W
Reset
Figure 11-1. Voltage Regulator Control Register (VREG_CTL)
Table 11-1. VREG_CTL field descriptions
Field
Description
5V_LVD_MASK Mask bit for 5 V LVD from regulator
This is a read/write bit and must be unmasked by writing a 1 by software to generate LVD functional
reset request to MC_RGM for 5 V trip.
1: 5 V LVD is masked
0: 5 V LVD is not masked.
11.2
Power supply strategy
From a power-routing perspective, the device is organized as follows.
The device provides four dedicated supply domains at package level:
1. HV (high voltage external power supply for I/Os and most analog module) — This must be
provided externally through VDD_HV/VSS_HV power pins. Voltage values should be aligned
with VDD/VSS. Refer to data sheet for details.
2. ADC (high voltage external power supply for ADC module) — This must be provided externally
through VDD_HV_ADC/VSS_HV_ADC power pins. Voltage values should be aligned with
VDD_HV_ADC/VSS_HV_ADC. Refer to data sheet for details.
3. BV (high voltage external power supply for voltage regulator module) — This must be provided
externally through VDD_BV_/VSS_BV power pins. Voltage values should be aligned with
VDD/VSS. Refer to data sheet for details.
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Chapter 11 Voltage Regulators and Power Supplies
4. LV (low voltage internal power supply for core, FMPLL and Flash digital logic) — This is
generated internally by embedded voltage regulator and provided to the core, FMPLL and Flash.
Three VDD_LV/VSS_LV pins pairs are provided to connect the three decoupling capacitances.
This is generated internally by internal voltage regulator but provided outside to connect stability
capacitor. Refer to data sheet for details.
The four dedicated supply domains are further divided within the package in order to reduce as much as
possible EMC and noise issues.
• HV_IO: High voltage pad supply
• HV_FLAn: High voltage flash memory supply
• HV_OSC0REG1: High voltage external oscillator and regulator supply
• HV_ADR: High voltage reference for ADC module. Supplies are further star routed to reduce
impact of ADC resistive reference on ADC capacitive reference accuracy.
• HV_ADV: High voltage supply for ADC module
• BV: High voltage supply for voltage regulator ballast. These two ballast pads are used to supply
the core and the flash memory. Each pad contains two ballasts to supply 80 mA and 20 mA,
respectively. Core is hence supplied through two ballasts of 80 mA capability and CFlash and
DFlash through two 20 mA ballasts. The HV supply for both ballasts is shorted through double
bonding.
• LV_COR: Low voltage supply for the core. It is also used to provide supply for FMPLL through
double bonding.
• LV_FLAn: Low voltage supply for flash memory module n. It is supplied with dedicated ballast
and shorted to LV_COR through double bonding.
• LV_PLL2: Low voltage supply for FMPLL
11.3
Power domain organization
Based on stringent requirements for current consumption in different operational modes, the device is
partitioned into different power domains. Organization into these power domains primarily means separate
power supplies that are separated from each other by use of power switches (switch SW1 for power domain
No. 1 and switch SW2 for power domain No. 2 as shown in Figure 11-2). These different separated power
supplies are hence enabling to switch off power to certain regions of the device to avoid even leakage
current consumption in logic supplied by the corresponding power supply.
This device employs three primary power domains, namely PD0, PD1, and PD2. As PCU supports
dynamic power down of domains based on different device mode, such a possible domain is depicted
below in dotted periphery.
Power domain organization and connections to the internal regulator are depicted in Figure 11-2.
1. Regulator ground is separated from oscillator ground and shorted to the LV ground through star routing
2. During production test, it is also possible to provide the VDD_LV externally through pins by configuring regulator in bypass
mode.
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Freescale Semiconductor
Chapter 11 Voltage Regulators and Power Supplies
PD0
RGM
ipe_iso0
ipe_pd
PCU
VDD_LV_BKP
RC Dig
HPPD
LPPD
WKPU
VREG
OSC Dig
CAN
sampler
SSCM
8 KB RAM
RTC/
API
SIRC
FIRC
SXOSC
nbypass
POR2HV
POR1HV
ULPVDD
SW20
HPVDD
LPVDD
24 KB RAM
VGATE
Vss
SW1
WKP FIL
HV
RC Dig
PD2
e200z0h
CGM
PE11
Reset
PE9
PE0
Wakeup Pads
CGL
VDD5B
platform
ME
Vdd5_cfla
CFLASH
Vdd
330nF
330nF
DFLASH
48 KB RAM
Vdd5_dlf
(PD2)
Vss
Peripheral
Set
SIUL
PA0
Peripheral
Set
PA1
PA2
PJ4
VDD12
PLL
330nF
PD1
ADC0 /
ADC1
VDD_LV_COR
VDD_LV_FLA0
VDD_LV_BKP
VDD_LV_FLA1
VDD_LV_BKP domain
AVSSref
AVSSsupply
AVDDsupply
AVDDref
Figure 11-2. Power domain organization
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Chapter 11 Voltage Regulators and Power Supplies
This page is intentionally left blank.
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Chapter 12 Wakeup Unit (WKPU)
Chapter 12
Wakeup Unit (WKPU)
12.1
Overview
The Wakeup Unit supports two internal sources and as many as 27 external sources that can generate
interrupts or wakeup events, of which one can cause non-maskable interrupt requests or wakeup events.
Figure 12-1 is the block diagram of the Wakeup Unit and its interfaces to other system components.
The wakeup vector mapping is shown in Table 12-1. All unused WKPU pins must use a pull resistor —
either pullup (internal or external) or pulldown (external) — to ensure no leakage from floating inputs.
Table 12-1. Wakeup vector mapping
API
n/a3
—
WKPU1
RTC
n/a3
WKPU2
PA1
WKPU3
bit
position
176-pin QFP
WKPU0
WISR
144-pin QFP
SIU
PCR#
100-pin QFP
Port
Package
Register2
IRQ#
Wakeup
number
Port input
function1 (can be
used in
conjunction with
WKPU function)
46
EIF0
31
3
3
3
—
EIF1
30
3
3
3
PCR1
NMI
EIF2
29



PA2
PCR2
—
EIF3
28



WKPU4
PB1
PCR17
CAN0RX, LIN0RX
EIF4
27



WKPU5
PC11
PCR43
CAN1RX, CAN4RX
EIF5
26



WKPU6
PE0
PCR64
CAN5RX
EIF6
25



WKPU7
PE9
PCR73
CAN2RX, CAN3RX
EIF7
24



WKPU8
PB10
PCR26
—
EIF8
23



WKPU9
PA4
PCR4
LIN5RX
EIF9
22



WKPU10
PA15
PCR15
—
EIF10
21



WKPU11
PB3
PCR19
LIN0RX
EIF11
20



WKPU12
PC7
PCR39
LIN1RX
EIF12
19



WKPU13
PC9
PCR41
LIN2RX
EIF13
18



WKPU14
PE11
PCR75
LIN3RX
EIF14
17



WKPU15
PF11
PCR91
LIN4RX
EIF15
16
x4


WKPU IRQ to
INTC
WakeUpIRQ0
WakeUpIRQ1
47
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Chapter 12 Wakeup Unit (WKPU)
Table 12-1. Wakeup vector mapping (continued)
PF13
PCR93
LIN5RX
WKPU17
PG3
PCR99
—
176-pin QFP
WKPU16
WISR
Register2
bit
position
144-pin QFP
WakeUpIRQ2
Port
SIU
PCR#
100-pin QFP
WKPU IRQ to
INTC
Wakeup
number
IRQ#
Package
Port input
function1 (can be
used in
conjunction with
WKPU function)
48
EIF16
15
x4


EIF17
14
x4


4
WKPU18
PG5
PCR101
—
EIF18
13
x


WKPU19
PA0
PCR0
—
EIF19
12



4
WKPU20
PG7
PCR103
LIN6RX
EIF20
11
x


WKPU21
PG9
PCR105
LIN7RX
EIF21
10
x4


4
WKPU22
PF9
PCR89
CAN2RX, CAN3RX
EIF22
9
x


WKPU23
PI3
PCR131
—
EIF23
8
x4
x4

EIF24
7
4
x
4
x

WKPU24
PI1
PCR129
—
49
WKPU25
PB8
PCR24
—
EIF25
6



WKPU26
PB9
PCR25
—
EIF26
5



WKPU27
PD0
PCR48
—
EIF27
4



WKPU28
PD1
PCR49
—
EIF28
3



1
This column does not contain an exhaustive list of functions on that pin. Rather, it includes peripheral communication functions
(such as CAN and LINFlex Rx) that could be used to wake up the microcontroller. DSPI pins are not included because DSPI
would typically be used in master mode.
2 WISR, IRER, WRER, WIFEER, WIFEEF, WIFER, WIPUER
3 Port not required to use timer functions.
4 Unavailable WKPU pins must use internal pullup enabled using WIPUER.
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Chapter 12 Wakeup Unit (WKPU)
Wakeup Unit
NMI / Wakeup
- Configuration
PLATFORM
NMI enable
filter bypass
PBRIDGE
wakeup
filter
IRQ / Wakeup
- Configuration
PADS
IOMUX
0-27
filter
filter bypass
Mode /
Power Ctl
sys wakeup
IPS
BUS
0-3
IRQs
2
Interrupt
Controller
RTC & API
Figure 12-1. WKPU block diagram
12.2
Features
The Wakeup Unit supports these distinctive features:
• Non-maskable interrupt support with
— One NMI source with bypassable glitch filter
— Independent interrupt destination: non-maskable interrupt, critical interrupt, or machine check
request
— Edge detection
• External wakeup/interrupt support with
— Four system interrupt vectors for as many as 29 interrupt sources
— Analog glitch filter per each wakeup line
— Independent interrupt mask
— Edge detection
— Configurable system wakeup triggering from all interrupt sources
— Configurable pullup
• On-chip wakeup support
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Chapter 12 Wakeup Unit (WKPU)
— Two wakeup sources
— Wakeup status mapped to same register as external wakeup/interrupt status
12.3
External signal description
The Wakeup Unit has 29 signal inputs that can be used as external interrupt sources in normal RUN mode
or as system wakeup sources in all power down modes.
The 27 external signal inputs include one signal input that can be used as a non-maskable interrupt source
in normal RUN, HALT or STOP modes or a system wakeup source in STOP or STANDBY modes. The
exception is with ports PB[8] and PB[9], which have wakeup functionality in all modes except STANDBY.
NOTE
The user should be aware that the Wake-up pins are enabled in ALL modes,
therefore, the Wake-up pins should be correctly terminated to ensure
minimal current consumption. Any unused Wake-up signal input should be
terminated by using an external pullup or pulldown, or by internal pullup
enabled at WKPU_WIPUER. Also, care has to be taken on packages where
the Wake-up signal inputs are not bonded. For these packages the user must
ensure the internal pullup are enabled for those signals not bonded.
12.4
Memory map and register description
This section provides a detailed description of all registers accessible in the WKPU module.
12.4.1
Memory map
Table 12-2 shows the WKPU memory map.
Table 12-2. WKPU memory map
Base address: 0xC3F9_4000
Address offset
0x00
0x04 – 0x07
0x08
0x0C – 0x13
Register name
NMI Status Flag Register (NSR)
Location
on page 217
Reserved
NMI Configuration Register (NCR)
on page 218
Reserved
0x14
Wakeup/Interrupt Status Flag Register (WISR)
on page 219
0x18
Interrupt Request Enable Register (IRER)
on page 219
0x1C
Wakeup Request Enable Register (WRER)
on page 220
0x20 – 0x27
Reserved
0x28
Wakeup/Interrupt Rising-Edge Event Enable Register (WIREER)
on page 220
0x2C
Wakeup/Interrupt Falling-Edge Event Enable Register (WIFEER)
on page 221
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Chapter 12 Wakeup Unit (WKPU)
Table 12-2. WKPU memory map (continued)
Base address: 0xC3F9_4000
Address offset
Register name
Location
0x30
Wakeup/Interrupt Filter Enable Register (WIFER)
on page 221
0x34
Wakeup/Interrupt Pullup Enable Register (WIPUER)
on page 222
NOTE
Reserved registers will read as 0, writes will have no effect. If
SSCM_ERROR[RAE] is enabled, a transfer error will be issued when
trying to access completely reserved register space.
12.4.2
NMI Status Flag Register (NSR)
This register holds the non-maskable interrupt status flags.
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
NIF0
NOVF0
Offset: 0x00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W w1c
Reset
w1c
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 12-2. NMI Status Flag Register (NSR)
Table 12-3. NSR field descriptions
Field
NIF0
NOVF0
Description
NMI Status Flag
If enabled (NREE0 or NFEE0 set), NIF0 causes an interrupt request.
1 An event as defined by NREE0 and NFEE0 has occurred
0 No event has occurred on the pad
NMI Overrun Status Flag
It will be a copy of the current NIF0 value whenever an NMI event occurs, thereby indicating to the
software that an NMI occurred while the last one was not yet serviced. If enabled (NREE0 or NFEE0
set), NOVF0 causes an interrupt request.
1 An overrun has occurred on NMI input
0 No overrun has occurred on NMI input
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Chapter 12 Wakeup Unit (WKPU)
12.4.3
NMI Configuration Register (NCR)
This register holds the configuration bits for the non-maskable interrupt settings.
5
6
7
0
NDSS0
0
0
0
0
0
0
16
17
18
19
20
21
0
0
0
0
0
0
0
0
0
0
Reset
R
0
1
2
8
9
10
11
12
13
14
15
NFEE0
4
NREE0
W
3
NWRE0
R
Access: User read/write
NLOCK0
Offset: 0x08
0
0
0
0
0
0
0
0
NFE0
0
0
0
0
0
0
0
0
0
0
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Figure 12-3. NMI Configuration Register (NCR)
Table 12-4. NCR field descriptions
Field
Description
NLOCK0
NMI Configuration Lock Register
Writing a 1 to this bit locks the configuration for the NMI until it is unlocked by a system reset. Writing
a 0 has no effect.
NDSS0
NMI Destination Source Select
00 Non-maskable interrupt
01 Critical interrupt
10 Machine check request
11 Reserved—no NMI, critical interrupt, or machine check request generated
NWRE0
NMI Wakeup Request Enable
1 A set NIF0 bit or set NOVF0 bit causes a system wakeup request
0 System wakeup requests from the corresponding NIF0 bit are disabled
Note: Software should only enable the NMI after the IVPR/IVOR registers have been configured. This
should be noted when booting from RESET or STANDBY mode as all registers will have been
cleared to their reset state.
NREE0
NMI Rising-edge Events Enable
1 Rising-edge event is enabled
0 Rising-edge event is disabled
NFEE0
NMI Falling-edge Events Enable
1 Falling-edge event is enabled
0 Falling-edge event is disabled
NFE0
NMI Filter Enable
Enable analog glitch filter on the NMI pad input.
1 Filter is enabled
0 Filter is disabled
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Chapter 12 Wakeup Unit (WKPU)
NOTE
Writing a 0 to both NREE0 and NFEE0 disables the NMI functionality
completely (that is, no system wakeup or interrupt will be generated on any
pad activity)!
12.4.4
Wakeup/Interrupt Status Flag Register (WISR)
This register holds the wakeup/interrupt flags.
Offset: 0x14
0
1
Access: User read/write
2
3
R 0 0 0
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
EIF[28:0]1
w1c
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 12-4. Wakeup/Interrupt Status Flag Register (WISR)
1
EIF[24:20] and EIF[18:15] not available in 100-pin LQFP; EIF[24:23] not available in 144-pin LQFP
Table 12-5. WISR field descriptions
Field
EIF[x]
Description
External Wakeup/Interrupt WKPU[x] Status Flag
This flag can be cleared only by writing a 1. Writing a 0 has no effect. If enabled (IRER[x]), EIF[x]
causes an interrupt request.
1 An event as defined by WIREER and WIFEER has occurred
0 No event has occurred on the pad
NOTE
Status bits associated with on-chip wakeup sources are located to the left of
the external wakeup/interrupt status bits and are read only. The wakeup for
these sources must be configured and cleared at the on-chip wakeup source.
Also, the configuration registers for the external interrupts/wakeups do not
have corresponding bits.
12.4.5
Interrupt Request Enable Register (IRER)
This register is used to enable the interrupt messaging from the wakeup/interrupt pads to the interrupt
controller.
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Chapter 12 Wakeup Unit (WKPU)
Offset: 0x18
0
1
Access: User read/write
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
EIRE[28:0]1
R 0 0 0
w1c
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 12-5. Interrupt Request Enable Register (IRER)
1
EIRE[24:20] and EIRE[18:15] not available in 100-pin LQFP; EIRE[24:23] not available in 144-pin LQFP
Table 12-6. IRER field descriptions
Field
Description
EIRE[x]
12.4.6
External Interrupt Request Enable x
1 A set EIF[x] bit causes an interrupt request
0 Interrupt requests from the corresponding EIF[x] bit are disabled
Wakeup Request Enable Register (WRER)
This register is used to enable the system wakeup messaging from the wakeup/interrupt pads to the mode
entry and power control modules.
Offset: 0x1C
0
1
Access: User read/write
2
R 0 0 0
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
WRE[28:0]1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 12-6. Wakeup Request Enable Register (WRER)
1
WRE[24:20] and WRE[18:15] not available in 100-pin LQFP; WRE[24:23] not available in 144-pin LQFP
Table 12-7. WRER field descriptions
Field
WRE[x]
12.4.7
Description
External Wakeup Request Enable x
1 A set EIF[x] bit causes a system wakeup request
0 System wakeup requests from the corresponding EIF[x] bit are disabled
Wakeup/Interrupt Rising-Edge Event Enable Register (WIREER)
This register is used to enable rising-edge triggered events on the corresponding wakeup/interrupt pads.
NOTE
The RTC_API can only be configured on the rising edge.
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Chapter 12 Wakeup Unit (WKPU)
.
Offset: 0x28
0
Access: User read/write
1
2
3
4
5
6
7
8
9
R 0 0 0
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
IREE[28:0]1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 12-7. Wakeup/Interrupt Rising-Edge Event Enable Register (WIREER)
1
IREE[24:20] and IREE[18:15] not available in 100-pin LQFP; IREE[24:23] not available in 144-pin LQFP
Table 12-8. WIREER field descriptions
Field
Description
IREE[x]
12.4.8
External Interrupt Rising-edge Events Enable x
1 Rising-edge event is enabled
0 Rising-edge event is disabled
Wakeup/Interrupt Falling-Edge Event Enable Register (WIFEER)
This register is used to enable falling-edge triggered events on the corresponding wakeup/interrupt pads.
Offset: 0x2C
0
1
Access: User read/write
2
3
R 0 0 0
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
IFEE[28:0]1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 12-8. Wakeup/Interrupt Falling-Edge Event Enable Register (WIFEER)
1
IFEE[24:20] and IFEE[18:15] not available in 100-pin LQFP; IFEE[24:23] not available in 144-pin LQFP
Table 12-9. WIFEER field descriptions
Field
IFEEx
12.4.9
Description
External Interrupt Falling-edge Events Enable x
1 Falling-edge event is enabled
0 Falling-edge event is disabled
Wakeup/Interrupt Filter Enable Register (WIFER)
This register is used to enable an analog filter on the corresponding interrupt pads to filter out glitches on
the inputs.
NOTE
There is no analog filter for the RTC_API.
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Chapter 12 Wakeup Unit (WKPU)
Offset: 0x30
0
1
Access: User read/write
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0
IFE[28:0]1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 12-9. Wakeup/Interrupt Filter Enable Register (WIFER)
1
IFE[24:20] and IFE[18:15] not available in 100-pin LQFP; IFE[24:23] not available in 144-pin LQFP
Table 12-10. WIFER field descriptions
Field
Description
IFE[x]
External Interrupt Filter Enable x
Enable analog glitch filter on the external interrupt pad input.
1 Filter is enabled
0 Filter is disabled
12.4.10 Wakeup/Interrupt Pullup Enable Register (WIPUER)
This register is used to enable a pullup on the corresponding interrupt pads to pull an unconnected
wakeup/interrupt input to a value of 1.
Offset: 0x34
0
1
Access: User read/write
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0
IPUE[28:0]1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 12-10. Wakeup/Interrupt Pullup Enable Register (WIPUER)
1
IPUE[24:20] and IPUE[18:15] not available in 100-pin LQFP; IPUE[24:23] not available in 144-pin LQFP
Table 12-11. WIPUER field descriptions
Field
IPUE[x]
12.5
12.5.1
Description
External Interrupt Pullup Enable x
1 Pullup is enabled
0 Pullup is disabled
Functional description
General
This section provides a complete functional description of the Wakeup Unit.
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Chapter 12 Wakeup Unit (WKPU)
12.5.2
Non-maskable interrupts
The Wakeup Unit supports one non-maskable interrupt that is allocated to the following pins:
• 100-pin LQFP: Pin 7
• 144-pin LQFP: Pin 11
• 176-pin LQFP: Pin 19
The Wakeup Unit supports the generation of three types of interrupts from the NMI. The Wakeup Unit
supports the capturing of a second event per NMI input before the interrupt is cleared, thus reducing the
chance of losing an NMI event.
Each NMI passes through a bypassable analog glitch filter.
NOTE
Glitch filter control and pad configuration should be done while the NMI is
disabled in order to avoid erroneous triggering by glitches caused by the
configuration process itself.
machine check
critical IRQ
NMI
CPU
Mode/
Pwr Ctl
Destination
Wakeup Enable
Flag
Overrun
Edge Detect
NFE0
NFEE0
NREE0
NWRE0
NDSS0
Glitch Filter
NMI Configuration Register (NCR)
Figure 12-11. NMI pad diagram
12.5.2.1
NMI management
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Chapter 12 Wakeup Unit (WKPU)
The NMI can be enabled or disabled using the single NCR register laid out to contain all configuration bits
for an NMI in a single byte (see Figure 12-3). The pad defined as an NMI can be configured by the user
to recognize interrupts with an active rising edge, an active falling edge or both edges being active. A
setting of having both edge events disabled results in no interrupt being detected, and should not be
configured.
The active NMI edge is controlled by the user through the configuration of the NREE0 and NFEE0 bits.
NOTE
After reset, NREE0 and NFEE0 are set to 0. Therefore, the NMI
functionality is disabled after reset and must be enabled explicitly by
software.
Once the pad’s NMI functionality has been enabled, the pad cannot be reconfigured in the IOMUX to
override or disable the NMI.
The NMI destination interrupt is controlled by the user through the configuration of the NDSS0 field. See
Table 12-4 for details.
An NMI supports a status flag and an overrun flag, which are located in the NSR register (see Figure 12-2).
The NIF0 and NOVF0 fields in this register are cleared by writing a 1 to them; this prevents inadvertent
overwriting of other flags in the register. The status flag is set whenever an NMI event is detected. The
overrun flag is set whenever an NMI event is detected and the status flag is set (that is, has not yet been
cleared).
NOTE
The overrun flag is cleared by writing a 1 to the appropriate overrun bit in
the NSR register. If the status bit is cleared and the overrun bit is still set, the
pending interrupt will not be cleared.
12.5.3
External wakeups/interrupts
The Wakeup Unit supports as many as 27 external wakeup/interrupts that can be allocated to any pad
necessary at the SoC level. This allocation is fixed per SoC.
The Wakeup Unit supports as many as four interrupt vectors to the interrupt controller of the SoC. Each
interrupt vector can support up to the number of external interrupt sources from the device pads with the
total across all vectors being equal to the number of external interrupt sources. Each external interrupt
source is assigned to exactly one interrupt vector. The interrupt vector assignment is sequential so that one
interrupt vector is for external interrupt sources 0 through N – 1, the next is for N through N + M – 1, and
so forth.
See Figure 12-12 for an overview of the external interrupt implementation for the example of four interrupt
vectors with as many as eight external interrupt sources each.
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Chapter 12 Wakeup Unit (WKPU)
Interrupt
Controller
Interrupt
Vectors
Mode/
Power Ctl
IRQ_07_00
IRQ_15_08
IRQ_16_23
IRQ_24_28
Wakeup enable
WRER[28:0]
OR
OR
OR
Flag[15:8]
Flag[7:0]
Interrupt enable
IRER[28:0]
Flag[24:20]
Flag[19:16]
Rising
WIREER[28:0]
Edge detection
Glitch filter enable
WIFER[28:0]
WISR[28:0]
Falling
WIFEER[28:0]
Analog glitch filter
Interrupt edge enable
Pads
RTC API
Figure 12-12. External interrupt pad diagram
All of the external interrupt pads within a single group have equal priority. It is the responsibility of the
user software to search through the group of sources in the most appropriate way for their application.
NOTE
Glitch filter control and pad configuration should be done while the external
interrupt line is disabled in order to avoid erroneous triggering by glitches
caused by the configuration process itself.
12.5.3.1
External interrupt management
Each external interrupt can be enabled or disabled independently. This can be performed using a single
rolled up register (Figure 12-5). A pad defined as an external interrupt can be configured by the user to
recognize external interrupts with an active rising edge, an active falling edge or both edges being active.
NOTE
Writing a 0 to both IREE[x] and IFEE[x] disables the external interrupt
functionality for that pad completely (that is, no system wakeup or interrupt
will be generated on any activity on that pad)!
The active IRQ edge is controlled by the users through the configuration of the registers WIREER and
WIFEER.
Each external interrupt supports an individual flag that is held in the flag register (WISR). The bits in the
WISR[EIF] field are cleared by writing a 1 to them; this prevents inadvertent overwriting of other flags in
the register.
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Chapter 12 Wakeup Unit (WKPU)
12.5.4
On-chip wakeups
The Wakeup Unit supports two on-chip wakeup sources. It combines the on-chip wakeups with the
external ones to generate a single wakeup to the system.
12.5.4.1
On-chip wakeup management
In order to allow software to determine the wakeup source at one location, on-chip wakeups are reported
along with external wakeups in the WISR register (see Figure 12-4 for details). Enabling and clearing of
these wakeups are done via the on-chip wakeup source’s own registers.
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Chapter 13 Real Time Clock / Autonomous Periodic Interrupt (RTC/API)
Chapter 13
Real Time Clock / Autonomous Periodic Interrupt (RTC/API)
13.1
Overview
The RTC/API is a free running counter used for time keeping applications. The RTC may be configured
to generate an interrupt at a predefined interval independent of the mode of operation (run mode or low
power mode). If in a low power mode when the RTC interval is reached, the RTC first generates a wakeup,
and then asserts the interrupt request. The RTC also supports an autonomous periodic interrupt (API)
function used to generate a periodic wakeup request to exit a low power mode or an interrupt request.
13.2
Features
Features of the RTC/API include:
• Three selectable counter clock sources
— SIRC (128 kHz)
— SXOSC (32 KHz)
— FIRC (16 MHz)
• Optional 512 prescaler and optional 32 prescaler
• 32-bit counter
— Supports times as long as 1.5 months with 1 ms resolution
— Runs in all modes of operation
— Reset when disabled by software and by POR
• 12-bit compare value to support interrupt intervals from 1 second to longer than 1 hour, with
1 second resolution
• RTC compare value changeable while counter is running
• RTC status and control register are reset only by POR
• Autonomous periodic interrupt (API)
— 10-bit compare value to support wakeup intervals of 1.0 ms to 1 second
— Compare value changeable while counter is running
• Configurable interrupt for RTC match, API match, and RTC rollover
• Configurable wakeup event for RTC match, API match, and RTC rollover
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Chapter 13 Real Time Clock / Autonomous Periodic Interrupt (RTC/API)
RTCCNT
APIVAL
sync
22:31
+
APIEN
reset
load
offset reg
22:31
API wakeup
APIF
32-bit counter
div32
2
SIRC
SXOSC
sync
div512
3
FIRC
0
Reserved
1
==
reset
CNTEN
div32en
div512en
==
CLKSEL[0:1]
APIIE
10:21
API
interrupt
RTCVAL
RTC wakeup
sync
sync
RTCF
RTCIE
RTC interrupt
ROVRF
RTCIE
ROVREN
Figure 13-1. RTC/API block diagram
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Chapter 13 Real Time Clock / Autonomous Periodic Interrupt (RTC/API)
(cnten & clksel== 11)
en
Reserved
C.G.
CELL
3
(cnten & clksel== 10)
en
FIRC
2
C.G.
CELL
0
(cnten & clksel== 01)
0
1
C.G.
CELL
en
SIRC
1
32-bit counter
C.G.
CELL
en
0
C.G.
CELL
div 512
1
div 32
div512en
(cnten & clksel== 00)
div32en
CNTEN
en
en
SXOSC
CLKSEL[0:1]
C.G.
CELL
Figure 13-2. Clock gating for RTC clocks
13.3
Device-specific information
For MPC5606BK, the device specific information is the following:
• SXOSC, FIRC, and SIRC clocks are provided as counter clocks for the RTC. Default clock on reset
is SIRC divided by 4.
• The RTC will be reset on destructive reset, with the exception of software watchdog reset.
• The RTC provides a configurable divider by 512 to be optionally used when FIRC source is
selected.
13.4
13.4.1
Modes of operation
Functional mode
There are two functional modes of operation for the RTC: normal operation and low power mode. In
normal operation, all RTC registers can read or written and the input isolation is disabled. The RTC/API
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Chapter 13 Real Time Clock / Autonomous Periodic Interrupt (RTC/API)
and associated interrupts are optionally enabled. In low power mode, the bus interface is disabled and the
input isolation is enabled. The RTC/API is enabled if enabled prior to entry into low power mode.
13.4.2
Debug mode
On entering into the debug mode the RTC counter freezes on the last valid count if the RTCC[FRZEN] is
set. On exit from debug mode counter continues from the frozen value.
13.5
Register descriptions
Table 13-1 lists the RTC/API registers.
Table 13-1. RTC/API register map
Base address: 0xC3FE_C000
13.5.1
Address offset
Register
Location
0x0
RTC Supervisor Control Register (RTCSUPV)
on page 230
0x4
RTC Control Register (RTCC)
on page 231
0x8
RTC Status Register (RTCS)
on page 233
0xC
RTC Counter Register (RTCCNT)
on page 234
RTC Supervisor Control Register (RTCSUPV)
The RTCSUPV register contains the SUPV bit, which determines whether other registers are accessible in
supervisor mode or user mode.
NOTE
RTCSUPV register is accessible only in supervisor mode.
Offset: 0x0
R
W
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SUPV
0
Access: Read/write
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 13-3. RTC Supervisor Control Register (RTCSUPV)
Table 13-2. RTCSUPV field descriptions
Field
SUPV
Description
RTC Supervisor Bit
0 All registers are accessible in both user as well as supervisor mode.
1 All other registers are accessible in supervisor mode only.
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Chapter 13 Real Time Clock / Autonomous Periodic Interrupt (RTC/API)
13.5.2
RTC Control Register (RTCC)
The RTCC register contains:
• RTC counter enable
• RTC interrupt enable
• RTC clock source select
• RTC compare value
• API enable
• API interrupt enable
• API compare value
Offset: 0x4
Access: User read/write
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
W
CLKSEL
DIV32EN
7
DIV512EN
6
ROVREN
5
FRZEN
4
RTCIE
3
APIIE
2
CNTEN
1
APIEN
0
Reset
0
0
0
0
0
0
0
0
0
R
W
Reset
R
0
RTCVAL
APIVAL
0
0
0
0
0
0
Figure 13-4. RTC Control Register (RTCC)
Table 13-3. RTCC field descriptions
Field
Description
CNTEN
Counter Enable
The CNTEN field enables the RTC counter. Making CNTEN bit 0 has the effect of asynchronously
resetting (synchronous reset negation) all the RTC and API logic. This allows for the RTC
configuration and clock source selection to be updated without causing synchronization issues.
1 Counter enabled
0 Counter disabled
RTCIE
RTC Interrupt Enable
The RTCIE field enables interrupts requests to the system if RTCF is asserted.
1 RTC interrupts enabled
0 RTC interrupts disabled
FRZEN
Freeze Enable
The counter freezes on entering the debug mode on the last valid count value if the FRZEN bit is
set. After coming out of the debug mode, the counter starts from the frozen value.
0 Counter does not freeze in debug mode.
1 Counter freezes in debug mode.
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Chapter 13 Real Time Clock / Autonomous Periodic Interrupt (RTC/API)
Table 13-3. RTCC field descriptions (continued)
Field
Description
ROVREN
Counter Roll Over Wakeup/Interrupt Enable
The ROVREN bit enables wakeup and interrupt requests when the RTC has rolled over from
0xFFFF_FFFF to 0x0000_0000. The RTCIE bit must also be set in order to generate an interrupt
from a counter rollover.
1 RTC rollover wakeup/interrupt enabled
0 RTC rollover wakeup/interrupt disabled
RTCVAL
Note: RTC Compare Value
The RTCVAL bits are compared to bits 10:21 of the RTC counter and if match sets RTCF.
RTCVAL can be updated when the counter is running.
APIEN
Autonomous Periodic Interrupt Enable
The APIEN bit enables the autonomous periodic interrupt function.
1 API enabled
0 API disabled
APIIE
API Interrupt Enable
The APIIE bit enables interrupts requests to the system if APIF is asserted.
1 API interrupts enabled
0 API interrupts disabled
CLKSEL
Clock Select
This field selects the clock source for the RTC. CLKSEL may only be updated when CNTEN is 0.
The user should ensure that oscillator is enabled before selecting it as a clock source for RTC.
00
SXOSC
01
SIRC
10
FIRC
11
Reserved
DIV512EN
Divide by 512 enable
The DIV512EN bit enables the 512 clock divider. DIV512EN may only be updated when CNTEN is
0.
0 Divide by 512 is disabled.
1 Divide by 512 is enabled.
DIV32EN
Divide by 32 enable
The DIV32EN bit enables the 32 clock divider. DIV32EN may only be updated when CNTEN is 0.
0 Divide by 32 is disabled.
1 Divide by 32 is enabled.
APIVAL
API Compare Value
The APIVAL field is compared with bits 22:31 of the RTC counter and if match asserts an
interrupt/wakeup request. APIVAL may only be updated when APIEN is 0 or API function is
undefined.
Note: API functionality starts only when APIVAL is nonzero. The first API interrupt takes two more
cycles because of synchronization of APIVAL to the RTC clock, and APIVAL + 1 cycles for
subsequent occurrences. After that, interrupts are periodic in nature. The minimum supported
value of APIVAL is 4.
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Chapter 13 Real Time Clock / Autonomous Periodic Interrupt (RTC/API)
13.5.3
RTC Status Register (RTCS)
The RTCS register contains:
• RTC interrupt flag
• API interrupt flag
• ROLLOVR flag
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
RTCF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
ROVRF
R
Access: User read/write
APIF
Offset: 0x8
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
Figure 13-5. RTC Status Register (RTCS)
Table 13-4. RTCS field descriptions
Field
Description
RTCF
RTC Interrupt Flag
The RTCF bit indicates that the RTC counter has reached the counter value matching RTCVAL.
RTCF is cleared by writing a 1 to RTCF. Writing a 0 to RTCF has no effect.
1 RTC counter matches RTCVAL
0 RTC counter is not equal to RTCVAL
APIF
API Interrupt Flag
The APIF bit indicates that the RTC counter has reached the counter value matching API offset
value. APIF is cleared by writing a 1 to APIF. Writing a 0 to APIF has no effect.
1 API interrupt
0 No API interrupt
Note: The periodic interrupt comes after APIVAL[0:9] + 1 RTC counts
ROVRF
Counter Roll Over Interrupt Flag
The ROVRF bit indicates that the RTC has rolled over from 0xffff_ffff to 0x0000_0000. ROVRF is
cleared by writing a 1 to ROVRF.
1 RTC has rolled over
0 RTC has not rolled over
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Chapter 13 Real Time Clock / Autonomous Periodic Interrupt (RTC/API)
13.5.4
RTC Counter Register (RTCCNT)
The RTCCNT register contains the current value of the RTC counter.
Offset: 0xC
0
Access: Read
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
RTCCNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 13-6. RTC Counter Register (RTCCNT)
Table 13-5. RTCCNT field descriptions
Field
RTCCNT
13.6
Description
RTC Counter Value
Due to the clock synchronization, the RTCCNT value may actually represent a previous counter
value.
RTC functional description
The RTC consists of a 32-bit free running counter enabled with the RTCC[CNTEN] bit (CNTEN when
negated asynchronously resets the counter and synchronously enables the counter when enabled). The
value of the counter may be read via the RTCCNT register. Note that due to the clock synchronization, the
RTCCNT value may actually represent a previous counter value. The difference between the counter and
the read value depends on ratio of counter clock and system clock. Maximum possible difference between
the two is 6 count values.
The clock source to the counter is selected with the RTCC[CLKSEL] field, which gives the options for
clocking the RTC/API. The output of the clock mux can be optionally divided by combination of 512 and
32 to give a 1 ms RTC/API count period for different clock sources. Note that the RTCC[CNTEN] bit must
be disabled when the RTC/API clock source is switched.
When the counter value for counter bits 10:21 match the 12-bit value in the RTCC[RTCVAL] field, then
the RTCS[RTCF] interrupt flag bit is set (after proper clock synchronization). If the RTCC[RTCIE]
interrupt enable bit is set, then the RTC interrupt request is generated. The RTC supports interrupt requests
in the range of 1 s to 4096 s (> 1 hr) with a 1 s resolution. If there is a match while in low power mode then
the RTC will first generate a wakeup request to force a wakeup to run mode, then the RTCF flag will be set.
A rollover wakeup and/or interrupt can be generated when the RTC transitions from a count of
0xFFFF_FFFF to 0x0000_0000. The rollover flag is enabled by setting the RTCC[ROVREN] bit. An RTC
counter rollover with this bit will cause a wakeup from low power mode. An interrupt request is generated
for an RTC counter rollover when both the RTCC[ROVREN] and RTCC[RTCIE] bits are set.
All the flags and counter values are synchronized with the system clock. It is assumed that the system clock
frequency is always more than or equal to the rtc_clk used to run the counter.
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Chapter 13 Real Time Clock / Autonomous Periodic Interrupt (RTC/API)
13.7
API functional description
Setting the RTCC[APIEN] bit enables the autonomous interrupt function. The 10-bit RTCC[APIVAL]
field selects the time interval for triggering an interrupt and/or wakeup event. Since the RTC is a free
running counter, the APIVAL is added to the current count to calculate an offset. When the counter reaches
the offset count, a interrupt and/or wakeup request is generated. Then the offset value is recalculated and
again re-triggers a new request when the new value is reached. APIVAL may only be updated when APIEN
is disabled. When a compare is reached, the RTCS[APIF] interrupt flag bit is set (after proper clock
synchronization). If the RTCC[APIIE] interrupt enable bit is set, then the API interrupt request is
generated. If there is a match while in low power mode, then the API will first generate a wakeup request
to force a wakeup into normal operation, then the APIF flag will be set.
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Chapter 13 Real Time Clock / Autonomous Periodic Interrupt (RTC/API)
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Chapter 14 CAN Sampler
Chapter 14
CAN Sampler
14.1
Introduction
The CAN Sampler peripheral has been designed to store the first identifier of CAN message detected on
the CAN bus while no precise clock (Crystal) is running at that time on the device, typically in Low Power
modes (STOP, HALT or STANBY) or in RUN mode with crystal switched off.
Depending on both CAN baud rate and Low Power mode used, it is possible to catch either the first or the
second CAN frame by sampling one CAN Rx port among 6 and storing all samples in internal registers.
After selection of the mode (first or second frame), the CAN Sampler stores samples of the 48 bits or skips
the first frame and stores samples of the 48 bits of second frame using the 16 MHz fast internal RC
oscillator and the 5-bit clock prescaler.
After completion, software must process the sampled data in order to rebuild the 48 minimal bits.
Base Identifier (11-bit)
Extended Identifier (18-bit)
Data
Length
Code
RTR bit
r1
IDE bit
SPR
SOF
r0
Figure 14-1. Extended CAN data frame
14.2
•
•
•
•
•
•
•
•
Main features
Store 384 samples, equivalent to 48 CAN bit at 8 samples/bit
Sample frequency from 500 kHz to 16 MHz, equivalent at 8 samples/bit to CAN baud rates of
62.5 Kbit/s to 2 Mbit/s
User selectable CAN Rx sample port [CAN0RX–CAN5RX]
16 MHz fast internal RC oscillator clock
5-bit clock prescaler
Configurable trigger mode (immediate, next frame)
Flexible samples processing by software
Very low power consumption
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Chapter 14 CAN Sampler
14.3
Memory map and register description
The CAN Sampler registers are listed in Table 14-1.
Table 14-1. CAN Sampler memory map
Base address: 0xFFE7_0000
Address offset
14.3.1
Register
Location
0x00
Control Register (CR)
on page 238
0x04–0x30
Sample registers 0–11
on page 239
Control Register (CR)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
BUSY
ACTIVE_CK
0
0
0
MODE
Access: Read/write
RX_COMPLETE
Offset: 0x00
CAN_RX_SEL
0
0
0
0
0
0
0
0
R
Reset
R
CAN_SMPLR_EN
W
BRP
W
Reset
0
0
0
0
0
0
0
0
Figure 14-2. Control Register (CR)
Table 14-2. CR field descriptions
Field
RX_COMPLETE
BUSY
ACTIVE_CK
MODE
Description
0: CAN frame has not been stored in the sample registers
1: CAN frame is stored in the sample registers
This bit indicates the status of sampling
0: Sampling is complete or has not started
1: Sampling is ongoing
This bit indicates the current clock (xmem_ck) for sample registers
0: ipg_clk_s is currently xmem_ck
1: RC_CLK is currently xmem_ck
0:Skip the first frame and sample and store the second frame (SF_MODE)
1:Sample and store the first frame (FF_MODE)
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Chapter 14 CAN Sampler
Table 14-2. CR field descriptions (continued)
Field
Description
CAN_RX_SEL
These bits determine which RX bit is sampled.
000: Rx0 is selected
001: Rx1 is selected
010: Rx2 is selected
011: Rx3 is selected
100: Rx4 is selected
101: Rx5 is selected
110: Rx6 is selected
111: Rx7 is selected
BRP
Baud Rate Prescaler
These bits are used to set the baud rate before going into standby mode
00000: Prescaler has 1
11111: Prescaler has 32
CAN_SMPLR_EN CAN SAMPLER Enable
This bit enables the CAN Sampler before going into standby or stop mode.
0: CAN Sampler is disabled
1: Can Sampler is enabled
14.3.2
CAN Sampler Sample Registers 0–11
Offsets: 0x04–0x30 (12 registers)
0
1
2
3
Access: Read/write
4
5
6
R
7
8
9
10
11
12
13
14
15
30
31
SR[0:15]
W
Reset
The reset values are unknown. They will be filled only after the first CAN sampling.
16
17
18
19
20
21
R
23
24
25
26
27
28
29
SR[16:31]
W
Reset
22
The reset values are unknown. They will be filled only after the first CAN sampling.
Figure 14-3. CAN Sampler Sample Registers 0–11
14.4
Functional description
As the CAN Sampler is driven by the 16 MHz fast internal RC oscillator to sample properly the CAN
identifier, two modes are possible depending on both CAN baud rate and low power mode used:
• Immediate sampling on falling edge detection (first CAN frame): this mode is used when the fast
internal RC oscillator 16 MHz is available in LP mode, for example, STOP or HALT.
• Sampling on next frame (second CAN frame): this mode is used when the fast internal RC
oscillator 16 MHz is switched off in low power mode, such as STANDBY. Due to the start-up times
of both the voltage regulator and the fast internal RC oscillator 16 MHz (~10 µs), the CAN sampler
would miss the first bits of a CAN identifier sent at 500 kbit/s. Therefore the first identifier is
ignored and the sampling is performed on the first falling edge of after interframe space.
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Chapter 14 CAN Sampler
The CAN sampler performs sampling on a user selected CAN Rx port among six Rx ports available,
normally when the device is in standby or stop mode storing the samples in internal registers. The user is
required to configure the baud rate to achieve eight samples per CAN nominal bit. It does not perform any
sort of filtering on input samples. Thereafter the software must enable the sampler by setting
CAN_SMPLR_EN bit in CR register. It then becomes the master controller for accessing the internal
registers implemented for storing samples.
When enabled, the CAN sampler waits for a low pulse on the selected Rx line, taking it as a valid bit of
the first CAN frame, and generates the RC wakeup request, which can be used to start the RC oscillator.
Depending upon the mode, it stores the first 8 samples of the 48 bits on selected Rx line or skips the first
frame and stores 8 bits for first 48 bits of second frame. In FF_MODE, it samples the CAN Rx line on RC
clock and stores the 8 samples of first 48 bits (384 samples). In SF_MODE, it samples the Rx and waits
for 11 consecutive dominant bits (11 × 8 samples), taking it as the end of first frame. It then waits for first
low pulse on the Rx, taking it as a valid Start of Frame (SOF) of the second frame. The sampler takes 384
samples (48 bytes × 8) using the RC clock (configuring 8 samples per nominal bit) of the second frame,
including the SOF bit. These samples are stored in consecutive addresses of the (12 × 32) internal
registers. RX_COMPLETE bit is set to 1, indicating that sampling is complete.
Software should now process the sampled data by first becoming master for accessing samples internal
registers by resetting CAN_SMPLR_EN bit.The sampler will need to be enabled again to start waiting for
a new sampling routine.
14.4.1
Enabling/disabling the CAN sampler
The CAN sampler is disabled on reset and the CPU is able to access the 12 registers used for storing
samples. The CAN Sampler must be enabled before going into standby or stop mode by setting
CAN_SMPLR_EN bit in the Control Register (CR) by writing 1 to this bit.
Any activity on selected Rx line, the sampler enables the 16 MHz fast internal RC oscillator. When
CAN_SMPLR_EN is reset to 0, the sampler should at least receive three RC clock pulses to reset itself,
after which the RC can be switched off.
When the software wishes to access the sample registers contents it must first reset the CAN_SMPLR_EN
bit by writing a 0. Before accessing the register contents it must monitor Active_CK bit for 0.When this
bit is reset it can safely access the (12 × 32) sample registers. While shifting from normal to sample mode
and vice versa, the sample register signals must be static and inactive to ensure the data is not corrupt.
14.4.2
Selecting the Rx port
One Rx port can be selected per sampling routine. The port to be sampled is selected by CAN_RX_SEL.
Table 14-3. Internal multiplexer correspondence
CAN_RX_SEL
Rx selected
000
CAN0RX on PB[1]
001
CAN1RX on PC[11]
010
CAN2RX on PE[9]
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Chapter 14 CAN Sampler
Table 14-3. Internal multiplexer correspondence (continued)
CAN_RX_SEL
14.4.3
Rx selected
011
CAN3RX on PE[9]
100
CAN4RX on PC[11]
101
CAN5RX on PE[0]
110
Rx6
111
Rx7
Baud rate generation
Sampling is performed at a baud rate that is set by the software as a multiple of RC oscillator frequency of
62.5 ns (assuming RC is configured for high frequency mode, that is, 16 MHz). User must set the baud
rate prescaler (BRP) such that 8 samples per bit are achieved.
Baud rate setting must be made by software before going into standby or stop mode. This is done by setting
BRP bits 5:1 in Control register. The reset value of BRP is 00000 and can be set to maximum value of
11111, which gives a prescale value of BRP + 1 thus providing a BRP range of 1 to 32.
• Maximum bit rate supported for sampling is 2 Mbit/s using BRP as 1
• Minimum bit rate supported for sampling is 62.5 kbit/s using BRP as 32
For example, suppose the system is transmitting at 125 kbit/s. In this case, nominal bit period:
T=1/(125 × 103)s = 8 × 10–3 × 10–3s = 8 µs
Eqn. 14-1
To achieve 8 samples per bit
Sample period= 8/8 µs = 1 µs
BRP = 1 µs/62.5 ns = 16. Thus in this case BRP = 01111
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——— Core platform modules ———
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Chapter 15 e200z0h Core
Chapter 15
e200z0h Core
15.1
Overview
The e200 processor family is a set of CPU cores that implement cost-efficient versions of the
Power Architecture. e200 processors are designed for deeply embedded control applications that require
low cost solutions rather than maximum performance.
The e200z0h processors integrate an integer execution unit, branch control unit, instruction fetch and
load/store units, and a multi-ported register file capable of sustaining three read and two write operations
per clock. Most integer instructions execute in a single clock cycle. Branch target prefetching is performed
by the branch unit to allow single-cycle branches in some cases.
The e200z0h core is a single-issue, 32-bit Power Architecture technology VLE-only design with 32-bit
general purpose registers (GPRs). All arithmetic instructions that execute in the core operate on data in the
general purpose registers (GPRs).
Instead of the base Power Architecture technology support, the e200z0h core only implements the VLE
(variable-length encoding) APU, providing improved code density.
15.2
Microarchitecture summary
The e200z0h processor utilizes a four stage pipeline for instruction execution. The Instruction Fetch (stage
1), Instruction Decode/Register file Read/Effective Address Calculation (stage 2), Execute/Memory
Access (stage 3), and Register Writeback (stage 4) stages operate in an overlapped fashion, allowing single
clock instruction execution for most instructions.
The integer execution unit consists of a 32-bit Arithmetic Unit (AU), a Logic Unit (LU), a 32-bit Barrel
shifter (Shifter), a Mask-Insertion Unit (MIU), a Condition Register manipulation Unit (CRU), a
Count-Leading-Zeros unit (CLZ), an 8x32 Hardware Multiplier array, result feed-forward hardware, and
a hardware divider.
Arithmetic and logical operations are executed in a single cycle with the exception of the divide and
multiply instructions. A Count-Leading-Zeros unit operates in a single clock cycle.
The Instruction Unit contains a PC incrementer and a dedicated Branch Address adder to minimize delays
during change of flow operations. Sequential prefetching is performed to ensure a supply of instructions
into the execution pipeline. Branch target prefetching from the BTB is performed to accelerate certain
taken branches in the e200z0h. Prefetched instructions are placed into an instruction buffer with 4entries
in e200z0h, each capable of holding a single 32-bit instruction or a pair of 16-bit instructions.
Conditional branches that are not taken execute in a single clock. Branches with successful target
prefetching have an effective execution time of one clock on e200z0h. All other taken branches have an
execution time of two clocks.
Memory load and store operations are provided for byte, halfword, and word (32-bit) data with automatic
zero or sign extension of byte and halfword load data as well as optional byte reversal of data. These
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Chapter 15 e200z0h Core
instructions can be pipelined to allow effective single cycle throughput. Load and store multiple word
instructions allow low overhead context save and restore operations. The load/store unit contains a
dedicated effective address adder to allow effective address generation to be optimized. Also, a load-to-use
dependency does not incur any pipeline bubbles for most cases.
The Condition Register unit supports the condition register (CR) and condition register operations defined
by the Power Architecture platform. The condition register consists of eight 4-bit fields that reflect the
results of certain operations, such as move, integer and floating-point compare, arithmetic, and logical
instructions, and provide a mechanism for testing and branching.
Vectored and autovectored interrupts are supported by the CPU. Vectored interrupt support is provided to
allow multiple interrupt sources to have unique interrupt handlers invoked with no software overhead.
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Chapter 15 e200z0h Core
15.3
Block diagram
OnCE
CPU
CONTROL LOGIC
CONTROL LOGIC
LR
INSTRUCTION BUS INTERFACE UNIT
N
CONTROL
32
DATA
32
ADDRESS
SPR
CR
INTEGER
EXECUTION
UNIT
GPR
CTR
XER
MULTIPLY
UNIT
INSTRUCTION UNIT
INSTRUCTION BUFFER
CONTROL
EXTERNAL
SPR
INTERFACE
DATA
(MTSPR/MFSPR)
PC
UNIT
BRANCH
UNIT
LOAD/
STORE
UNIT
DATA BUS INTERFACE UNIT
32
ADDRESS
32
DATA
N
CONTROL
Figure 15-1. e200z0h block diagram
15.4
Features
The following is a list of some of the key features of the e200z0h core:
• 32-bit Power Architecture VLE-only programmer’s model
• Single issue, 32-bit CPU
• Implements the VLE APU for reduced code footprint
• In-order execution and retirement
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Chapter 15 e200z0h Core
•
•
•
•
•
•
Precise exception handling
Branch processing unit
— Dedicated branch address calculation adder
— Branch acceleration using Branch Target Buffer
Supports independent instruction and data accesses to different memory subsystems, such as
SRAM and Flash memory via independent Instruction and Data bus interface units (BIUs)
(e200z0h only).
Load/store unit
— 1 cycle load latency
— Fully pipelined
— Big-endian support only
— Misaligned access support
— Zero load-to-use pipeline bubbles for aligned transfers
Power management
— Low power design
— Power saving modes: nap, sleep, and wait
— Dynamic power management of execution units
Testability
— Synthesizeable, full MuxD scan design
— ABIST/MBIST for optional memory arrays
15.4.1
Instruction unit features
The features of the e200 Instruction unit are:
• 32-bit instruction fetch path supports fetching of one 32-bit instruction per clock, or as many as
two 16-bit VLE instructions per clock
• Instruction buffer with 4 entries in e200z0h, each holding a single 32-bit instruction, or a pair of
16-bit instructions
• Dedicated PC incrementer supporting instruction prefetches
• Branch unit with dedicated branch address adder supporting single cycle of execution of certain
branches, two cycles for all others
15.4.2
Integer unit features
The e200 integer unit supports single cycle execution of most integer instructions:
• 32-bit AU for arithmetic and comparison operations
• 32-bit LU for logical operations
• 32-bit priority encoder for count leading zeros function
• 32-bit single cycle barrel shifter for shifts and rotates
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Chapter 15 e200z0h Core
•
•
•
32-bit mask unit for data masking and insertion
Divider logic for signed and unsigned divide in 5 to 34 clocks with minimized execution timing
8 × 32 hardware multiplier array supports 1 to 4 cycle 32 × 32  32 multiply (early out)
15.4.3
Load/Store unit features
The e200 load/store unit supports load, store, and the load multiple / store multiple instructions:
• 32-bit effective address adder for data memory address calculations
• Pipelined operation supports throughput of one load or store operation per cycle
• 32-bit interface to memory (dedicated memory interface on e200z0h)
15.4.4
e200z0h system bus features
The features of the e200z0h system bus interface are as follows:
• Independent instruction and data buses
• AMBA1 AHB2 Lite Rev 2.0 specification with support for ARM v6 AMBA extensions
— Exclusive access monitor
— Byte lane strobes
— Cache allocate support
• 32-bit address bus plus attributes and control on each bus
• 32-bit read data bus for instruction interface
• Separate uni-directional 32-bit read data bus and 32-bit write data bus for data interface
• Overlapped, in-order accesses
15.5
Core registers and programmer’s model
This section describes the registers implemented in the e200z0h cores. It includes an overview of registers
defined by the Power Architecture platform, highlighting differences in how these registers are
implemented in the e200 core, and provides a detailed description of e200-specific registers. Full
descriptions of the architecture-defined register set are provided in the Power Architecture specification.
The Power Architecture defines register-to-register operations for all computational instructions. Source
data for these instructions are accessed from the on-chip registers or are provided as immediate values
embedded in the opcode. The three-register instruction format allows specification of a target register
distinct from the two source registers, thus preserving the original data for use by other instructions. Data
is transferred between memory and registers with explicit load and store instructions only.
Figure 15-2, and Figure 15-1 show the e200 register set, including the registers that are accessible while
in supervisor mode, and the registers that are accessible in user mode. The number to the right of the
special-purpose registers (SPRs) is the decimal number used in the instruction syntax to access the register
(for example, the integer exception register (XER) is SPR 1).
1. Advanced Microcontroller Bus Architecture
2. Advanced High Performance Bus
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Chapter 15 e200z0h Core
NOTE
e200z0h is a 32-bit implementation of the Power Architecture specification.
In this document, register bits are sometimes numbered from bit 0 (Most
Significant Bit) to 31 (Least Significant Bit), rather than the Book E
numbering scheme of 32:63, thus register bit numbers for some registers in
Book E are 32 higher.
Where appropriate, the Book E defined bit numbers are shown in
parentheses.
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SUPERVISOR Mode Program Model SPRs
Exception Handling/Control Registers
General Registers
Condition Register
General-Purpose
Registers
CR
GPR0
Count Register
CTR
SPR General
Save and Restore
SPR 272
SRR0
SPR 26
SPRG1
SPR 273
SRR1
SPR 27
CSRR0
SPR 58
CSRR1
SPR 59
DSRR01
SPR 574
DSRR11
SPR 575
GPR1
SPR 9
Link Register
LR
SPR 8
Interrupt Vector Prefix
SPRG0
GPR31
IVPR
SPR 63
Exception Syndrome
XER
ESR
XER
SPR 1
MCSR
Processor Control Registers
Hardware Implementation
Dependent1
HID0
SPR 1008
Machine State
MSR
Processor Version
PVR
SPR 287
HID1
SPR 1009
Instruction Address
Compare
SPR 308
IAC1
SPR 312
DBCR1
SPR 309
IAC2
SPR 313
DBCR2
SPR 310
IAC3
SPR 314
DBCR31
SPR 561
IAC4
SPR 315
SPR 304
BTB Register
SPR 1013
PID0
DBCR0
DBSR
SPR 61
Process ID
Debug Registers2
Debug Status
DEAR
Memory Management Registers
SPR 1023
Debug Control
Data Exception Address
BUCSR
SPR 286
System Version1
SVR
SPR 572
BTB Control1
Processor ID
PIR
SPR 62
Machine Check
Syndrome Register
Data Address Compare
DAC1
SPR 316
DAC2
SPR 317
DVC1
SPR 318
DVC2
SPR 319
SPR 48
Configuration (read only)
MMUCFG
SPR 1015
Cache Registers
Cache Configuration
(Read-only)
L1CFG0
SPR 515
1 - These e200-specific registers may not be
supported by other Power Architecture
processors.
2 - Optional registers defined by the Power
Architecture technology
3 - Read-only registers
Figure 15-2. e200z0 SUPERVISOR Mode Program Model SPRs
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Chapter 16 Enhanced Direct Memory Access (eDMA)
Chapter 16
Enhanced Direct Memory Access (eDMA)
16.1
•
•
•
•
•
•
•
•
•
•
16.2
Device-specific features
16 programmable channels to support independent 8-, 16-, or 32-bit single value or block transfers
Support of variable sized queues and circular queues
Source and destination address registers independently configured to post-incrementor remain
constant
Each transfer initiated by peripheral, CPU, periodic timer interrupt or eDMA channel request
Peripheral eDMA request sources possible from DSPI, I2C, 10-bit ADC, 12-bit ADC, LINFlexD,
and eMIOS
Each eDMA channel able to optionally send interrupt request to CPU on completion of single value
or block transfer
DMA transfers possible between system memories and all accessible memory mapped locations
including peripheral and registers
Programmable eDMA channel mux allows assignment of any eDMA source to any available
eDMA channel with total of as many as 32 request sources
DMA supports the following functionality:
— Scatter Gather
— Channel Linking
— Inner Loop Offset
— Arbitration
– Fixed Group, fixed channel
– Round Robin Group, fixed channel
– Round Robin Group, Round Robin Channel
– Fixed Group, Round Robin Channel
— Channel preemption
— Cancel channel transfer
Interrupts – The eDMA has a single interrupt request for each implemented channel and a
combined eDMA Error interrupt to flag transfer errors to the system. Each channel eDMA interrupt
can be enabled or disabled and provides notification of a completed transfer. Refer to the Interrupt
Vector in Chapter 18, Interrupt Controller (INTC), for the allocation of these interrupts.
Introduction
The enhanced direct memory access controller (eDMA) is a second-generation platform block capable of
performing complex data movements through 16 programmable channels, with minimal intervention from
the host processor. The hardware microarchitecture includes a DMA engine that performs source and
destination address calculations, and the actual data movement operations, along with an SRAM-based
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Chapter 16 Enhanced Direct Memory Access (eDMA)
memory containing the transfer control descriptors (TCD) for the channels. This implementation
minimizes the overall block size.
Figure 16-1 is a block diagram of the eDMA module.
eDMA
SRAM
transfer control descriptor
(TCD)
Slave write address
Slave write data
TCD0
TCDn – 1
Slave interface
System bus
SRAM
eDMA engine
Bus read data
Program model/
channel arbitration
Data path
Address
path
Control
Slave read data
Bus write data
Bus address
n = 16 channels
eDMA Peripheral
Request
eDMA Done
Figure 16-1. eDMA block diagram
16.2.1
Features
The eDMA module supports the following features:
• All data movement via dual-address transfers: read from source, write to destination
— Programmable source, destination addresses, transfer size, plus support for enhanced
addressing modes
• Transfer control descriptor organized to support two-deep, nested transfer operations
— An inner data transfer loop defined by a minor byte transfer count
— An outer data transfer loop defined by a major iteration count
• Channel service request via one of three methods:
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Chapter 16 Enhanced Direct Memory Access (eDMA)
— Explicit software initiation
— Initiation via a channel-to-channel linking mechanism for continuous transfers
– Independent channel linking at end of minor loop and/or major loop
— Peripheral-paced hardware requests (one per channel)
— For all three methods, one service request per execution of the minor loop is required
Support for fixed-priority and round-robin channel arbitration
Channel completion reported via optional interrupt requests
— One interrupt per channel, optionally asserted at completion of major iteration count
— Error terminations are optionally enabled per channel, and logically summed together to form
a small number of error interrupt outputs
Support for scatter/gather eDMA processing
Support for complex data structures
Support to cancel transfers via software or hardware
•
•
•
•
•
16.3
16.3.1
Memory map and register definition
Memory map
The eDMA memory map is shown in Table 16-1. The eDMA base address is 0xFFF4_4000. The address
of each register is given as an offset to the eDMA base address. Registers are listed in address order,
identified by complete name and mnemonic, and list the type of accesses allowed.
The eDMA’s programming model is partitioned into two regions—the first region defines a number of
registers providing control functions; the second region corresponds to the local transfer control descriptor
memory.
Table 16-1. eDMA memory map
Base address: 0xFFF4_4000
Address offset
Register
Location
0x0000
EDMA_CR — eDMA control register
on page 257
0x0004
EDMA_ESR — eDMA error status register
on page 259
0x0008
Reserved
0x000C
EDMA_ERQRL — eDMA enable request low register (channels 15–00)
0x0010
Reserved
0x0014
EDMA_EEIRL — eDMA enable error interrupt low register (channels 15–00)
on page 262
0x0018
EDMA_SERQR — eDMA set enable request register
on page 263
0x0019
EDMA_CERQR — eDMA clear enable request register
on page 264
0x001A
EDMA_SEEIR — eDMA set enable error interrupt register
on page 264
0x001B
EDMA_CEEIR — eDMA clear enable error interrupt register
on page 265
on page 261
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Chapter 16 Enhanced Direct Memory Access (eDMA)
Table 16-1. eDMA memory map (continued)
Base address: 0xFFF4_4000
Address offset
Register
Location
0x001C
EDMA_CIRQR — eDMA clear interrupt request register
on page 265
0x001D
EDMA_CER — eDMA clear error register
on page 266
0x001E
EDMA_SSBR — eDMA set start bit register
on page 266
0x001F
EDMA_CDSBR — eDMA clear done status bit register
on page 267
0x0020
Reserved
0x0024
EDMA_IRQRL — eDMA interrupt request low register
0x0028
Reserved
0x002C
EDMA_ERL — eDMA error low register
0x0030
Reserved
0x0034
EDMA_HRSL — eDMA hardware request status register
on page 267
on page 268
on page 269
0x0038 – 0x01FC Reserved
0x0100
EDMA_CPR0 — eDMA channel 0 priority register
on page 269
0x0101
EDMA_CPR1 — eDMA channel 1 priority register
on page 269
0x0102
EDMA_CPR2 — eDMA channel 2 priority register
on page 269
0x0103
EDMA_CPR3 — eDMA channel 3 priority register
on page 269
0x0104
EDMA_CPR4 — eDMA channel 4 priority register
on page 269
0x0105
EDMA_CPR5 — eDMA channel 5 priority register
on page 269
0x0106
EDMA_CPR6 — eDMA channel 6 priority register
on page 269
0x0107
EDMA_CPR7 — eDMA channel 7 priority register
on page 269
0x0108
EDMA_CPR8 — eDMA channel 8 priority register
on page 269
0x0109
EDMA_CPR9 — eDMA channel 9 priority register
on page 269
0x010A
EDMA_CPR10 — eDMA channel 10 priority register
on page 269
0x010B
EDMA_CPR11 — eDMA channel 11 priority register
on page 269
0x010C
EDMA_CPR12 — eDMA channel 12 priority register
on page 269
0x010D
EDMA_CPR13 — eDMA channel 13 priority register
on page 269
0x010E
EDMA_CPR14 — eDMA channel 14 priority register
on page 269
0x010F
EDMA_CPR15 — eDMA channel 15 priority register
on page 269
0x0110
Reserved
0x1000
TCD00 — eDMA transfer control descriptor 00
on page 271
0x1020
TCD01 — eDMA transfer control descriptor 01
on page 271
0x1040
TCD02 — eDMA transfer control descriptor 02
on page 271
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Chapter 16 Enhanced Direct Memory Access (eDMA)
Table 16-1. eDMA memory map (continued)
Base address: 0xFFF4_4000
Address offset
Register
Location
0x1060
TCD03 — eDMA transfer control descriptor 03
on page 271
0x1080
TCD04 — eDMA transfer control descriptor 04
on page 271
0x10A0
TCD05 — eDMA transfer control descriptor 05
on page 271
0x10C0
TCD06 — eDMA transfer control descriptor 06
on page 271
0x10E0
TCD07 — eDMA transfer control descriptor 07
on page 271
0x1100
TCD08 — eDMA transfer control descriptor 08
on page 271
0x1120
TCD09 — eDMA transfer control descriptor 09
on page 271
0x1140
TCD10 — eDMA transfer control descriptor 10
on page 271
0x1160
TCD11 — eDMA transfer control descriptor 11
on page 271
0x1180
TCD12 — eDMA transfer control descriptor 12
on page 271
0x11A0
TCD13 — eDMA transfer control descriptor 13
on page 271
0x11C0
TCD14 — eDMA transfer control descriptor 14
on page 271
0x11E0
TCD15 — eDMA transfer control descriptor 15
on page 271
0x1200
Reserved
16.3.2
16.3.2.1
Register descriptions
DMA Control Register (EDMA_CR)
The 32-bit EDMA_CR defines the basic operating configuration of the eDMA.
Arbitration among the channels can be configured to use a fixed priority or a round robin. In fixed-priority
arbitration, the highest priority channel requesting service is selected to execute. The priorities are
assigned by the channel priority registers (see Section 16.3.2.16, DMA Channel n Priority
(EDMA_CPRn))). In round-robin arbitration mode, the channel priorities are ignored and the channels are
cycled through, from channel 15 down to channel 0, without regard to priority.
See Figure 16-2 and Table 16-2 for the EDMA_CR definition.
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Chapter 16 Enhanced Direct Memory Access (eDMA)
Offset: 0x0000
R
Access: Read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
0
0
0
0
0
0
0
0
0
0
0
0
0
0
14
15
CX
ECX
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
HALT
HOE
ERGA
ERCA
EDBG
EBW
R
0
CLM
RESET:
EMLM
W
0
0
0
0
0
0
0
0
GRP0PRI
W
RESET:
0
0
0
0
0
0
0
0
Figure 16-2. DMA Control Register (EDMA_CR)
Table 16-2. EDMA_CR field descriptions
Field
Description
CX
Cancel Transfer
0 Normal operation.
1 Cancel the remaining data transfer. Stop the executing channel and force the minor loop
to be finished. The cancel takes effect after the last write of the current read/write
sequence. The CXFR bit clears itself after the cancel has been honored. This cancel
retires the channel normally as if the minor loop was completed.
ECX
Error Cancel Transfer
0 Normal operation.
1 Cancel the remaining data transfer in the same fashion as the CX cancel transfer. Stop
the executing channel and force the minor loop to be finished. The cancel takes effect
after the last write of the current read/write sequence. The ECX bit clears itself after the
cancel has been honored. In addition to cancelling the transfer, the ECX treats the cancel
as an error condition; thus updating the EDMA_ESR register and generating an optional
error interrupt (see Section 16.3.2.2, DMA Error Status (EDMA_ESR)).
GRP0PRI
Channel Group 0 Priority
Group 0 priority level when fixed priority group arbitration is enabled.
EMLM
Enable Minor Loop Mapping
0 Minor loop mapping disabled. TCDn.word2 is defined as a 32-bit nbytes field.
1 Minor loop mapping enabled. When set,
TCDn.word2 is redefined to include individual enable fields, an offset field and the nbytes
field. The individual enable fields allow the minor loop offset to be applied to the source
address, the destination address, or both. The nbytes field is reduced when either offset
is enabled.
CLM
Continuous Link Mode
0 A minor loop channel link made to itself will go through channel arbitration before being
activated again.
1 A minor loop channel link made to itself will not go through channel arbitration before
being activated again. Upon minor loop completion the channel will active again if that
channel has a minor loop channel link enabled and the link channel is itself. This
effectively applies the minor loop offsets and restarts the next minor loop.
HALT
Halt DMA Operations
0 Normal operation.
1 Stall the start of any new channels. Executing channels are allowed to complete. Channel
execution will resume when the HALT bit is cleared.
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Chapter 16 Enhanced Direct Memory Access (eDMA)
Table 16-2. EDMA_CR field descriptions (continued)
Field
HOE
16.3.2.2
Description
Halt On Error
0 Normal operation.
1 Any error will cause the HALT bit to be set. Subsequently, all service requests will be
ignored until the HALT bit is cleared.
ERGA
Enable Round Robin Group Arbitration
0 Fixed priority arbitration is used for selection among the groups.
1 Round robin arbitration is used for selection among the groups.
ERCA
Enable Round Robin Channel Arbitration
0 Fixed priority arbitration is used for channel selection within each group.
1 Round robin arbitration is used for channel selection within each group.
EDBG
Enable Debug
0 The assertion of the device debug mode is ignored.
1 The assertion of the device debug mode causes the eDMA to stall the start of a new
channel. Executing channels are allowed to complete. Channel execution will resume
when either the device comes out of debug mode or the EDBG bit is cleared.
EBW
0
1
The bufferable write signal (hprot[2]) is not asserted during AMBA AHB writes.
The bufferable write signal (hprot[2]) is asserted on all AMBA AHB writes except for the
last write sequence.
DMA Error Status (EDMA_ESR)
The EDMA_ESR provides information about the last recorded channel error. Channel errors can be caused
by a configuration error (an illegal setting in the transfer control descriptor or an illegal priority register
setting in fixed-arbitration mode) or an error termination to a bus master read or write cycle.
A configuration error is caused when the starting source or destination address, source or destination
offsets, minor loop byte count, and the transfer size represent an inconsistent state. The addresses and
offsets must be aligned on 0-modulo-transfer_size boundaries, and the minor loop byte count must be a
multiple of the source and destination transfer sizes. All source reads and destination writes must be
configured to the natural boundary of the programmed transfer size respectively.
In fixed-arbitration mode, a configuration error is generated when any two channel priority levels are equal
and any channel is activated. The ERRCHN field is undefined for this type of error. All channel priority
levels must be unique before any service requests are made.
If a scatter-gather operation is enabled on channel completion, a configuration error is reported if the
scatter-gather address (DLAST_SGA) is not aligned on a 32-byte boundary. If minor loop channel linking
is enabled on channel completion, a configuration error is reported when the link is attempted if the
TCD.CITER.E_LINK bit is not equal to the TCD.BITER.E_LINK bit. All configuration error conditions
except scatter-gather and minor loop link error are reported as the channel is activated and assert an error
interrupt request if enabled. When properly enabled, a scatter-gather configuration error is reported when
the scatter-gather operation begins at major loop completion. A minor loop channel link configuration
error is reported when the link operation is serviced at minor loop completion.
If a system bus read or write is terminated with an error, the data transfer is immediately stopped and the
appropriate bus error flag is set. In this case, the state of the channel’s transfer control descriptor is updated
by the DMA engine with the current source address, destination address, and minor loop byte count at the
point of the fault. If a bus error occurs on the last read prior to beginning the write sequence, the write will
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execute using the data captured during the bus error. If a bus error occurs on the last write prior to switching
to the next read sequence, the read sequence will execute before the channel is terminated due to the
destination bus error.
The occurrence of any type of error causes the DMA engine to stop the active channel and the appropriate
channel bit in the eDMA error register to be asserted. At the same time, the details of the error condition
are loaded into the EDMA_ESR. The major loop complete indicators, setting the transfer control
descriptor DONE flag and the possible assertion of an interrupt request, are not affected when an error is
detected. After the error status has been updated, the DMA engine continues to operate by servicing the
next appropriate channel. A channel that experiences an error condition is not automatically disabled. If a
channel is terminated by an error and then issues another service request before the error is fixed, that
channel will execute and terminate with the same error condition.
Offset: 0x0004
Access: Read
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
CPE
0
0
R VLD
W
RESET:
R
ERRCHN[0:5]
SAE SOE DAE DOE NCE SGE SBE DBE
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 16-3. DMA Error Status (EDMA_ESR) Register
Table 16-3. EDMA_ESR field descriptions
Field
Description
VLD
Logical OR of all EDMA_ERL status bits.
0 No EDMA_ERL bits are set.
1 At least one EDMA_ERL bit is set indicating a valid error exists that has not been cleared.
CPE
Channel Priority Error
0 No channel priority error.
1 The last recorded error was a configuration error in the channel priorities within a group.
All channel priorities within a group are not unique.
ERRCHN[0:5]
Error Channel Number or Cancelled Channel Number
The channel number of the last recorded error (excluding GPE and CPE errors) or last
recorded transfer that was error cancelled.
SAE
Source Address Error
0 No source address configuration error.
1 The last recorded error was a configuration error detected in the TCD.saddr field.
TCD.saddr is inconsistent with TCD.ssize.
SOE
Source Offset Error
0 No source offset configuration error.
1 The last recorded error was a configuration error detected in the TCD.soff field. TCD.soff
is inconsistent with TCD.ssize.
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Table 16-3. EDMA_ESR field descriptions (continued)
Field
16.3.2.3
Description
DAE
Destination Address Error
0 No destination address configuration error.
1 The last recorded error was a configuration error detected in the TCD.daddr field.
TCD.daddr is inconsistent with TCD.dsize.
DOE
Destination Offset Error
0 No destination offset configuration error.
1 The last recorded error was a configuration error detected in the TCD.doff field. TCD.doff
is inconsistent with TCD.dsize.
NCE
Nbytes/Citer Configuration Error
0 No nbytes/citer configuration error.
1 The last recorded error was a configuration error detected in the TCD.nbytes or TCD.citer
fields. TCD.nbytes is not a multiple of TCD.ssize and TCD.dsize, or TCD.citer is equal to
zero, or TCD.citer.e_link is not equal to TCD.biter.e_link.
SGE
Scatter/Gather Configuration Error
0 No scatter/gather configuration error.
1 The last recorded error was a configuration error detected in the TCD.dlast_sga field.
This field is checked at the beginning of a scatter/gather operation after major loop
completion if TCD.e_sg is enabled. TCD.dlast_sga is not on a 32 byte boundary.
SBE
Source Bus Error
0 No source bus error.
1 The last recorded error was a bus error on a source read.
DBE
Destination Bus Error
0 No destination bus error.
1 The last recorded error was a bus error on a destination write.
DMA Enable Request (EDMA_ERQRL)
The EDMA_ERQRL provides a bit map for the 16 channels to enable the request signal for each channel.
EDMA_ERQRL maps to channels 15–0.
The state of any given channel enable is directly affected by writes to this register; the state is also affected
by writes to the EDMA_SERQR, and EDMA_CERQR registers. The EDMA_CERQR and
EDMA_SERQR registers are provided so the request enable for a single channel can be modified without
performing a read-modify-write sequence to the EDMA_ERQRL register.
Both the eDMA request input signal and this enable request flag must be asserted before a channel’s
hardware service request is accepted. The state of the eDMA enable request flag does not affect a channel
service request made through software or a linked channel request.
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0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
W
ERQ14
ERQ13
ERQ12
ERQ11
ERQ10
ERQ09
ERQ08
ERQ07
ERQ06
ERQ05
ERQ04
ERQ03
ERQ02
ERQ01
ERQ00
Access: Read/write
ERQ15
Offset: 0x000C
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
RESET:
R
Figure 16-4. DMA Enable Request (EDMA_ERQRL) Registers
Table 16-4. EDMA_ERQRL field descriptions
Field
ERQn
Description
Enable eDMA Request n
0 The eDMA request signal for channel n is disabled.
1 The eDMA request signal for channel n is enabled.
As a given channel completes the processing of its major iteration count, there is a flag in the transfer
control descriptor that may affect the ending state of the EDMA_ERQRL bit for that channel. If the
TCD.d_req bit is set, then the corresponding EDMA_ERQRL bit is cleared, disabling the eDMA request;
else if the d_req bit is cleared, the state of the EDMA_ERQRL bit is unaffected.
16.3.2.4
DMA Enable Error Interrupt (EDMA_EEIRL)
The EDMA_EEIRL provides a bit map for the 16 channels to enable the error interrupt signal for each
channel. EDMA_EEIRL maps to channels 15–0.
The state of any given channel’s error interrupt enable is directly affected by writes to these registers; it is
also affected by writes to the EDMA_SEEIR and EDMA_CEEIR registers. The EDMA_SEEIR and
EDMA_CEEIR registers are provided so that the error interrupt enable for a single channel can be
modified without the performing a read-modify-write sequence to the EDMA_EEIRL register.
Both the eDMA error indicator and this error interrupt enable flag must be asserted before an error
interrupt request for a given channel is asserted. See Figure 16-5 and Table 16-5 for the EDMA_EEIRL
definition.
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0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
W
EEI14
EEI13
EEI12
EEI11
EEI10
EEI09
EEI08
EEI07
EEI06
EEI05
EEI04
EEI03
EEI02
EEI01
EEI00
Access: Read/write
EEI15
Offset: 0x0014
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
RESET:
R
Figure 16-5. DMA Enable Error Interrupt (EDMA_EEIRL) Register
Table 16-5. EDMA_EEIRL field descriptions
Field
Description
EEIn
16.3.2.5
Enable Error Interrupt n
0 The error signal for channel n does not generate an error interrupt.
1 The assertion of the error signal for channel n generate an error interrupt request.
DMA Set Enable Request (EDMA_SERQR)
The EDMA_SERQR provides a simple memory-mapped mechanism to set a given bit in the
EDMA_ERQRL to enable the eDMA request for a given channel. The data value on a register write causes
the corresponding bit in the EDMA_ERQRL to be set. Setting bit 1 (SERQ[0]) provides a global set
function, forcing the entire contents of EDMA_ERQRL to be asserted. Reads of this register return all
zeroes.
Offset: 0x0018
Access: Write
R
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
0
0
0
SERQ
W
RESET:
0
0
0
0
0
Figure 16-6. DMA Set Enable Request (EDMA_SERQR) Register
Table 16-6. EDMA_SERQR field descriptions
Field
SERQ
Description
Set Enable Request
0–15 Set the corresponding bit in EDMA_ERQRL
64–127 Set all bits in EDMA_ERQRL
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16.3.2.6
DMA Clear Enable Request (EDMA_CERQR)
The EDMA_CERQR provides a simple memory-mapped mechanism to clear a given bit in the
EDMA_ERQRL to disable the eDMA request for a given channel. The data value on a register write
causes the corresponding bit in the EDMA_ERQRL to be cleared. Setting bit 1 (CERQ[0]) provides a
global clear function, forcing the entire contents of the EDMA_ERQRL to be zeroed, disabling all eDMA
request inputs. Reads of this register return all zeroes. See Figure 16-7 and Table 16-7 for the
EDMA_CERQR definition.
Offset: 0x0019
Access: Write
R
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
0
0
0
W
RESET:
CERQ
0
0
0
0
0
Figure 16-7. DMA Clear Enable Request (EDMA_CERQR) Register
Table 16-7. EDMA_CERQR field descriptions
Field
Description
CERQ
16.3.2.7
Clear Enable Request
0–63
Clear corresponding bit in EDMA_ERQRL
64–127 Clear all bits in EDMA_ERQRL
DMA Set Enable Error Interrupt (EDMA_SEEIR)
The EDMA_SEEIR provides a memory-mapped mechanism to set a given bit in the EDMA_EEIRL to
enable the error interrupt for a given channel. The data value on a register write causes the corresponding
bit in the EDMA_EEIRL to be set. Setting bit 1 (SEEI[0]) provides a global set function, forcing the entire
contents of EDMA_EEIRL to be asserted. Reads of this register return all zeroes. See Figure 16-8 and
Table 16-8 for the EDMA_SEEIR definition.
Offset: 0x001A
Access: Write
R
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
0
0
0
W
RESET:
SEEI
0
0
0
0
0
Figure 16-8. DMA Set Enable Error Interrupt (EDMA_SEEIR) Register
Table 16-8. EDMA_SEEIR field descriptions
Name
Description
SEEI
Set Enable Error Interrupt
0–63
Set the corresponding bit in EDMA_EEIRL
64–127 Set all bits in EDMA_EEIRL
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16.3.2.8
DMA Clear Enable Error Interrupt (EDMA_CEEIR)
The EDMA_CEEIR provides a memory-mapped mechanism to clear a given bit in the EDMA_EEIRL to
disable the error interrupt for a given channel. The data value on a register write causes the corresponding
bit in the EDMA_EEIRL to be cleared. Setting bit 1 (CEEI[0]) provides a global clear function, forcing
the entire contents of the EDMA_EEIRL to be zeroed, disabling error interrupts for all channels. Reads of
this register returns all zeroes. See Figure 16-9 and Table 16-9 for the EDMA_CEEIR definition.
Offset: 0x001B
Access: Write
R
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
0
0
0
W
CEEI[0:6]
RESET:
0
0
0
0
0
Figure 16-9. DMA Clear Enable Error Interrupt (EDMA_CEEIR) Register
Table 16-9. EDMA_CEEIR field descriptions
Field
Description
CEEI
16.3.2.9
Clear Enable Error Interrupt
0–63
Clear corresponding bit in EDMA_EEIRL
64–127 Clear all bits in EDMA_EEIRL
DMA Clear Interrupt Request (EDMA_CIRQR)
The EDMA_CIRQR provides a memory-mapped mechanism to clear a given bit in the EDMA_IRQRL to
disable the interrupt request for a given channel. The given value on a register write causes the
corresponding bit in the EDMA_IRQRL to be cleared. Setting bit 1 (CINT[0]) provides a global clear
function, forcing the entire contents of the EDMA_IRQRL to be zeroed, disabling all eDMA interrupt
requests. Reads of this register return all zeroes. See Figure 16-10 and Table 16-10 for the EDMA_CIRQR
definition.
Offset: 0x001C
Access: Write
R
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
0
0
0
W
CINT
RESET:
0
0
0
0
0
Figure 16-10. DMA Clear Interrupt Request (EDMA_CIRQR) Fields
Table 16-10. EDMA_CIRQR field descriptions
Field
CINT[0:6]
Description
Clear Interrupt Request
0–63
Clear the corresponding bit in EDMA_IRQRL
64–127 Clear all bits in EDMA_IRQRL
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16.3.2.10 DMA Clear Error (EDMA_CER)
The EDMA_CER provides a memory-mapped mechanism to clear a given bit in the EDMA_ERL to
disable the error condition flag for a given channel. The given value on a register write causes the
corresponding bit in the EDMA_ERL to be cleared. Setting bit 1 (CERR[0]) provides a global clear
function, forcing the entire contents of the EDMA_ERL to be zeroed, clearing all channel error indicators.
Reads of this register return all zeroes. See Figure 16-11 and Table 16-11 for the EDMA_CER definition.
Offset: 0x001D
Access: Write
R
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
0
0
0
W
RESET:
CERR
0
0
0
0
0
Figure 16-11. DMA Clear Error (EDMA_CER) Register
Table 16-11. EDMA_CER field descriptions
Field
Description
CERR
Clear Error Indicator
0–63
Clear corresponding bit in EDMA_ERL
64–127 Clear all bits in EDMA_ERL
16.3.2.11 DMA Set START Bit (EDMA_SSBR)
The EDMA_SSBR provides a memory-mapped mechanism to set the START bit in the TCD of the given
channel. The data value on a register write causes the START bit in the corresponding transfer control
descriptor to be set. Setting bit 1 (SSB[0]) provides a global set function, forcing all START bits to be set.
Reads of this register return all zeroes. See Table 16-19 for the TCD START bit definition.
Offset: 0x001E
Access: Write
R
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
0
0
0
W
RESET:
SSRT
0
0
0
0
0
Figure 16-12. DMA Set START Bit (EDMA_SSBR) Register
Table 16-12. EDMA_SSBR field descriptions
Field
Description
SSRT
Set START Bit (Channel Service Request)
0–63
Set the corresponding channel’s TCD.start
64–127 Set all TCD.start bits
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16.3.2.12 DMA Clear DONE Status (EDMA_CDSBR)
The EDMA_CDSBR provides a memory-mapped mechanism to clear the DONE bit in the TCD of the
given channel. The data value on a register write causes the DONE bit in the corresponding transfer control
descriptor to be cleared. Setting bit 1 (CDSB[0]) provides a global clear function, forcing all DONE bits
to be cleared. See Table 16-19 for the TCD DONE bit definition.
Offset: 0x001F
Access: Write
R
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
0
0
0
W
CDNE[0:6]
RESET:
0
0
0
0
0
Figure 16-13. DMA Clear DONE Status (EDMA_CDSBR) Register
Table 16-13. EDMA_CDSBR field descriptions
Field
CDNE[0:6]
Description
Clear DONE Status Bit
0–63 Clear the corresponding channel’s DONE bit
64–127 Clear all TCD DONE bits
16.3.2.13 DMA Interrupt Request (EDMA_IRQRL)
The EDMA_IRQRL provides a bit map for the 16 channels signaling the presence of an interrupt request
for each channel. EDMA_IRQRL maps to channels 15–0.
The DMA engine signals the occurrence of a programmed interrupt on the completion of a data transfer
as defined in the transfer control descriptor by setting the appropriate bit in this register. The outputs of
this register are directly routed to the interrupt controller (INTC). During the execution of the interrupt
service routine associated with any given channel, software must clear the appropriate bit, negating the
interrupt request. Typically, a write to the EDMA_CIRQR in the interrupt service routine is used for this
purpose.
The state of any given channel’s interrupt request is directly affected by writes to this register; it is also
affected by writes to the EDMA_CIRQR. On writes to the EDMA_IRQRL, a 1 in any bit position clears
the corresponding channel’s interrupt request. A 0 in any bit position has no affect on the corresponding
channel’s current interrupt status. The EDMA_CIRQR is provided so the interrupt request for a single
channel can be cleared without performing a read-modify-write sequence to the EDMA_IRQRL. See
Figure 16-14 and Table 16-14 for the EDMA_IRQL definition.
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0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
W
INT14
INT13
INT12
INT11
INT10
INT09
INT08
INT07
INT06
INT05
INT04
INT03
INT02
INT01
INT00
Access: Read/write
INT15
Offset: 0x0024
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
RESET:
R
Figure 16-14. DMA Interrupt Request (EDMA_IRQRL) Registers
Table 16-14. EDMA_IRQRL field descriptions
Field
INTn
Description
DMA Interrupt Request n
0 The interrupt request for channel n is cleared.
1 The interrupt request for channel n is active.
16.3.2.14 DMA Error (EDMA_ERL)
The EDMA_ERL provides a bit map for the 16 channels signaling the presence of an error for each
channel. EDMA_ERL maps to channels 15–0.
The DMA engine signals the occurrence of a error condition by setting the appropriate bit in this register.
The outputs of this register are enabled by the contents of the EDMA_EEIR, then logically summed across
16 channels to form an error interrupt request, which is then routed to the interrupt controller. During the
execution of the interrupt service routine associated with any eDMA errors, it is software’s responsibility
to clear the appropriate bit, negating the error interrupt request. Typically, a write to the EDMA_CER in
the interrupt service routine is used for this purpose. The normal eDMA channel completion indicators,
setting the transfer control descriptor DONE flag and the possible assertion of an interrupt request, are not
affected when an error is detected.
The contents of this register can also be polled. A non-zero value indicates the presence of a channel error,
regardless of the state of the EDMA_EEIR. The EDMA_ESR[VLD] bit is a logical OR of all bits in this
register, and it provides a single bit indication of any errors. The state of any given channel’s error
indicators is affected by writes to this register; it is also affected by writes to the EDMA_CER. On writes
to EDMA_ERL, a 1 in any bit position clears the corresponding channel’s error status. A 0 in any bit
position has no affect on the corresponding channel’s current error status. The EDMA_CER is provided
so the error indicator for a single channel can be cleared. See Figure 16-15 and Table 16-15 for the
EDMA_ERL definition.
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0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
W
ERR14
ERR13
ERR12
ERR11
ERR10
ERR09
ERR08
ERR07
ERR06
ERR05
ERR04
ERR03
ERR02
ERR01
ERR00
Access: Read/write
ERR15
Offset: 0x002C
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
RESET:
R
Figure 16-15. DMA Error (EDMA_ERL) Registers
Table 16-15. EDMA_ERL field descriptions
Field
Description
ERRn
DMA Error n
0 An error in channel n has not occurred.
1 An error in channel n has occurred.
16.3.2.15 DMA Hardware Request Status (EDMA_HRSL)
The EDMA_HRSL register provides a bit map for the implemented channels to show the current hardware
request status for each channel. This view into the hardware request signals may be used for debug
purposes.
See Figure 16-16 and Figure 16-16 for the EDMA_HRSL definition.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
W
HRS14
HRS13
HRS12
HRS11
HRS10
HRS09
HRS08
HRS07
HRS06
HRS05
HRS04
HRS03
HRS02
HRS01
HRS00
Access: Read/write
HRS15
Offset: 0x0034
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
RESET:
R
Figure 16-16. DMA Hardware Request Status (EDMA_HRSL) Register
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Table 16-16. EDMA_HRSL field descriptions
Field
Description
HRSn
DMA Hardware Request Status n
0 A hardware service request for channel n is not present.
1 A hardware service request for channel n is present.
Note: The hardware request status reflects the state of the request as seen by the arbitration
logic. Therefore, this status is affected by the EDMA_ERQRL[n] bit.
16.3.2.16 DMA Channel n Priority (EDMA_CPRn)
When the fixed-priority channel arbitration mode is enabled (EDMA_CR[ERCA] = 0), the contents of
these registers define the unique priorities associated with each channel. The channel priorities are
evaluated by numeric value; that is, 0 is the lowest priority, 1 is the next higher priority, then 2, 3, etc. If
software modifies channel priority values, then the software must ensure that the channel priorities contain
unique values, otherwise a configuration error will be reported. The range of the priority value is limited
to the values of 0 through 15.
Channel preemption is enabled on a per-channel basis by setting the ECP bit in the EDMA_CPRn register.
Channel preemption allows the executing channel’s data transfers to be temporarily suspended in favor of
starting a higher priority channel. After the preempting channel has completed all its minor loop data
transfers, the preempted channel is restored and resumes execution. After the restored channel completes
one read/write sequence, it is again eligible for preemption. If any higher priority channel requests service,
the restored channel will be suspended and the higher priority channel will be serviced. Nested preemption
(attempting to preempt a preempting channel) is not supported. After a preempting channel begins
execution, it cannot be preempted. Preemption is available only when fixed arbitration is selected for
channel arbitration mode
A channel’s ability to preempt another channel can be disabled by setting the DPA bit in the EDMA_CPRn
register. When a channel’s preempt ability is disabled, that channel cannot suspend a lower priority
channel’s data transfer; regardless of the lower priority channel’s ECP setting. This allows for a pool of
low priority, large data moving channels to be defined. These low priority channels can be configured to
not preempt each other, thus preventing a low priority channel from consuming the preempt slot normally
available a true, high priority channel. See Figure 16-17 and Table 16-17 for the EDMA_CPRn definition.
Offset: 0x0100 + n
Access: Read/write
0
1
ECP
DPA
0
0
2
R
3
4
5
6
7
*
*
GRPPRI
CHPRI
W
RESET:
*
*
*
*
*
= defaults to channel number (n) after reset
Figure 16-17. DMA Channel n Priority (EDMA_CPRn) Register
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Table 16-17. EDMA_CPRn field descriptions
Field
Description
ECP
Enable Channel Preemption
0 Channel n cannot be suspended by a higher priority channel’s service request.
1 Channel n can be temporarily suspended by the service request of a higher priority
channel.
DPA
Disable Preempt Ability
0 Channel n can suspend a lower priority channel.
1 Channel n cannot suspend any channel, regardless of channel priority.
CHPRI[0:3]
Channel n Arbitration Priority
Channel priority when fixed-priority arbitration is enabled.
16.3.2.17 Transfer Control Descriptor (TCD)
Each channel requires a 32-byte transfer control descriptor for defining the desired data movement
operation. The channel descriptors are stored in the local memory in sequential order: channel 0, channel
1,... channel 15. The definitions of the TCD are presented as eight 32-bit values. Table 16-18 is a field list
of the basic TCD structure.
Table 16-18. TCDn 32-bit memory structure
eDMA offset
TCDn field
0x1000+(32 × n)+0x0000
Source address (saddr)
0x1000+(32 × n)+0x0004
Transfer attributes
Signed source address offset (soff)
0x1000+(32 × n)+0x0008
Inner minor byte count (nbytes)
0x1000+(32 × n)+0x000C
Last source address adjustment (slast)
0x1000+(32 × n)+0x0010
Destination address (daddr)
0x1000+(32 × n)+0x0014
0x1000 (32 × n) 0x0018
0x1000+(32 × n)+0x001C
Current major iteration count (citer)
Signed destination address offset (doff)
Last destination address adjustment / scatter-gather address (dlast_sga)
Beginning major iteration count (biter)
Channel control/status
Figure 16-18 and Table 16-19 define the fields of the TCDn structure.
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0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0x0000
SADDR
0x0004
SMOD
SSIZE
DMOD
SOFF
NBYTES1
SMLOE1
DMLOE1
0x0008
0x8
DSIZE
MLOFF or NBYTES 1
NBYTES1
SLAST
0x0010
DADDR
0x0014
CITER.E_ LINK
0x000C
CITER or
CITER.LINKCH
CITER
0x001C
DLAST_SGA
BITER.E_ LINK
0x0018
DOFF
0
BITER or
BITER.LINKCH
1
2
3
4
5
6
BITER
7
8
9
BWC MAJOR LINKCH
DONE
ACTIVE
MAJOR.E_LINK
E_SG
D_REQ
INT_HALF
INT_MAJ
START
Word
Offset
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Figure 16-18. TCD structure
1
The fields implemented in Word 2 depend on whether EDMA_CR(EMLM) is set to 0 or 1. See Table 16-2.
NOTE
The TCD structures for the eDMA channels shown in Figure 16-18 are
implemented in internal SRAM. These structures are not initialized at reset;
therefore, all channel TCD parameters must be initialized by the application
code before activating that channel.
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Table 16-19. TCDn field descriptions
Bits /
Word Offset
[n:n]
Name
0–31 /
0x0 [0:31]
SADDR
[0:31]
Source address. Memory address pointing to the source data.
Word 0x0, bits 0–31.
32–36 /
0x4 [0:4]
SMOD
[0:4]
Source address modulo.
0
Source address modulo feature is disabled.
non-0 This value defines a specific address range that is specified to be the
value after SADDR + SOFF calculation is performed or the original
register value. The setting of this field provides the ability to easily
implement a circular data queue. For data queues requiring
power-of-2 size bytes, the queue should start at a 0-modulo-size
address and the SMOD field should be set to the appropriate value
for the queue, freezing the desired number of upper address bits.
The value programmed into this field specifies the number of lower
address bits that are allowed to change. For this circular queue
application, the SOFF is typically set to the transfer size to implement
post-increment addressing with the SMOD function constraining the
addresses to a 0-modulo-size range.
37–39 /
0x4 [5:7]
SSIZE
[0:2]
Source data transfer size.
000 8-bit
001 16-bit
010 32-bit
011 Reserved
100 16-byte (32-bit, 4-beat, WRAP4 burst)
101 32-byte (32-bit, 8-beat, WRAP8 burst)
110 Reserved
111 Reserved
The attempted specification of a reserved encoding causes a configuration
error.
40–44 /
0x4 [8:12]
DMOD
[0:4]
Destination address modulo. See the SMOD[0:5] definition.
45–47 /
0x4 [13:15]
DSIZE
[0:2]
Destination data transfer size. See the SSIZE[0:2] definition.
48–63 /
0x4 [16:31]
SOFF
[0:15]
Source address signed offset. Sign-extended offset applied to the current
source address to form the next-state value as each source read is
completed.
64–95 /
0x8 [0:31]
NBYTES
[0:31]
Inner minor byte transfer count. Number of bytes to be transferred in each
service request of the channel. As a channel is activated, the contents of
the appropriate TCD is loaded into the DMA engine, and the appropriate
reads and writes performed until the complete byte transfer count has been
transferred. This is an indivisible operation and cannot be stalled or halted.
After the minor count is exhausted, the current values of the SADDR and
DADDR are written back into the local memory, the major iteration count is
decremented and restored to the local memory. If the major iteration count
is completed, additional processing is performed.
Note: The NBYTES value of 0x0000_0000 is interpreted as
0x1_0000_0000, thus specifying a 4 GB transfer.
Description
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Table 16-19. TCDn field descriptions (continued)
Bits /
Word Offset
[n:n]
Name
Description
64–95 /
0x8 [0:31]
NBYTES1
[0:31]
Inner minor byte transfer count. Number of bytes to be transferred in each
service request of the channel. As a channel is activated, the contents of
the appropriate TCD is loaded into the eDMA engine, and the appropriate
reads and writes performed until the complete byte transfer count has been
transferred. This is an indivisible operation and cannot be stalled or halted.
Once the minor count is exhausted, the current values of the SADDR and
DADDR are written back into the local memory, the major iteration count is
decremented and restored to the local memory. If the major iteration count
is completed, additional processing is performed.
Note: The NBYTES value of 0x0000_0000 is interpreted as
0x1_0000_0000, thus specifying a 4 Gbyte transfer.
64
0x8 [0]
SMLOE 1
0
Source minor loop offset enable
This flag selects whether the minor loop offset is applied to the source
address upon minor loop completion.
0
1
65
0x8 [1]
DMLOE 1
1
Destination minor loop offset enable
This flag selects whether the minor loop offset is applied to the destination
address upon minor loop completion.
0
1
66–85
0x8 [2:21]
MLOFF or
NBYTES 1
[0:19]
The minor loop offset is not applied to the saddr.
The minor loop offset is applied to the saddr.
The minor loop offset is not applied to the daddr.
The minor loop offset is applied to the daddr.
Inner minor byte transfer count or Minor loop offset
If both SMLOE and DMLOE are cleared, this field is part of the byte transfer
count.
If either SMLOE or DMLOE are set, this field represents a sign-extended
offset applied to the source or destination address to form the next-state
value after the minor loop is completed.
86–95 /
0x8 [22:31]
NBYTES 1
Inner minor byte transfer count. Number of bytes to be transferred in each
service request of the channel. As a channel is activated, the contents of
the appropriate TCD is loaded into the eDMA engine, and the appropriate
reads and writes performed until the complete byte transfer count has been
transferred. This is an indivisible operation and cannot be stalled or halted.
Once the minor count is exhausted, the current values of the SADDR and
DADDR are written back into the local memory, the major iteration count is
decremented and restored to the local memory. If the major iteration count
is completed, additional processing is performed.
Note: The NBYTES value of 0x0000_0000 is interpreted as
0x1_0000_0000, thus specifying a 4 GByte transfer.
96–127 /
0xC [0:31]
SLAST
[0:31]
Last source address adjustment. Adjustment value added to the source
address at the completion of the outer major iteration count. This value can
be applied to restore the source address to the initial value, or adjust the
address to reference the next data structure.
128–159 /
0x10 [0:31]
DADDR
[0:31]
Destination address. Memory address pointing to the destination data.
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Table 16-19. TCDn field descriptions (continued)
Bits /
Word Offset
[n:n]
160 /
0x14 [0]
Name
Description
CITER.E_LINK
Enable channel-to-channel linking on minor loop completion. As the
channel completes the inner minor loop, this flag enables the linking to
another channel, defined by CITER.LINKCH[0:5]. The link target channel
initiates a channel service request via an internal mechanism that sets the
TCD.START bit of the specified channel. If channel linking is disabled, the
CITER value is extended to 15 bits in place of a link channel number. If the
major loop is exhausted, this link mechanism is suppressed in favor of the
MAJOR.E_LINK channel linking.
0 The channel-to-channel linking is disabled.
1 The channel-to-channel linking is enabled.
Note: This bit must be equal to the BITER.E_LINK bit otherwise a
configuration error will be reported.
161–166 /
0x14 [1:6]
CITER
[0:5]
or
CITER.LINKCH
[0:5]
Current major iteration count or link channel number.
If channel-to-channel linking is disabled (TCD.CITER.E_LINK = 0), then
• No channel-to-channel linking (or chaining) is performed after the inner
minor loop is exhausted. TCD bits [161:175] are used to form a 15-bit
CITER field.
Otherwise,
• After the minor loop is exhausted, the DMA engine initiates a channel
service request at the channel defined by CITER.LINKCH[0:5] by setting
that channel’s TCD.START bit.
167–175 /
0x14 [7:15]
CITER
[6:14]
Current major iteration count. This 9- or 15-bit count represents the current
major loop count for the channel. It is decremented each time the minor
loop is completed and updated in the transfer control descriptor memory.
After the major iteration count is exhausted, the channel performs a number
of operations (for example, final source and destination address
calculations), optionally generating an interrupt to signal channel
completion before reloading the CITER field from the beginning iteration
count (BITER) field.
Note: When the CITER field is initially loaded by software, it must be set
to the same value as that contained in the BITER field.
Note: If the channel is configured to execute a single service request, the
initial values of BITER and CITER should be 0x0001.
176–191 /
0x14 [16:31]
DOFF
[0:15]
Destination address signed Offset. Sign-extended offset applied to the
current destination address to form the next-state value as each destination
write is completed.
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Table 16-19. TCDn field descriptions (continued)
Bits /
Word Offset
[n:n]
Name
Description
192–223 /
0x18 [0:31]
DLAST_SGA
[0:31]
Last destination address adjustment or the memory address for the next
transfer control descriptor to be loaded into this channel (scatter-gather).
If scatter-gather processing for the channel is disabled (TCD.E_SG = 0)
then
• Adjustment value added to the destination address at the completion of
the outer major iteration count.
This value can be applied to restore the destination address to the initial
value, or adjust the address to reference the next data structure.
Otherwise,
• This address points to the beginning of a 0-modulo-32 byte region
containing the next transfer control descriptor to be loaded into this
channel. This channel reload is performed as the major iteration count
completes. The scatter-gather address must be 0-modulo-32 byte,
otherwise a configuration error is reported.
224 /
0x1C [0]
BITER.E_LINK
Enables channel-to-channel linking on minor loop complete. As the channel
completes the inner minor loop, this flag enables the linking to another
channel, defined by BITER.LINKCH[0:5]. The link target channel initiates a
channel service request via an internal mechanism that sets the
TCD.START bit of the specified channel. If channel linking is disabled, the
BITER value is extended to 15 bits in place of a link channel number. If the
major loop is exhausted, this link mechanism is suppressed in favor of the
MAJOR.E_LINK channel linking.
0 The channel-to-channel linking is disabled.
1 The channel-to-channel linking is enabled.
Note: When the TCD is first loaded by software, this field must be set equal
to the corresponding CITER field, otherwise a configuration error will be
reported. As the major iteration count is exhausted, the contents of this field
is reloaded into the CITER field.
225–230 /
0x1C [1:6]
BITER
[0:5]
or
BITER.LINKCH[0:5]
Starting major iteration count or link channel number.
If channel-to-channel linking is disabled (TCD.BITER.E_LINK = 0), then
• No channel-to-channel linking (or chaining) is performed after the inner
minor loop is exhausted. TCD bits [225:239] are used to form a 15-bit
BITER field.
Otherwise,
• After the minor loop is exhausted, the DMA engine initiates a channel
service request at the channel, defined by BITER.LINKCH[0:5], by
setting that channel’s TCD.START bit.
Note: When the TCD is first loaded by software, this field must be set equal
to the corresponding CITER field, otherwise a configuration error will be
reported. As the major iteration count is exhausted, the contents of this field
is reloaded into the CITER field.
231–239 /
0x1C [7:15]
BITER
[6:14]
Starting major iteration count. As the transfer control descriptor is first
loaded by software, this field must be equal to the value in the CITER field.
As the major iteration count is exhausted, the contents of this field are
reloaded into the CITER field.
Note: If the channel is configured to execute a single service request, the
initial values of BITER and CITER should be 0x0001.
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Table 16-19. TCDn field descriptions (continued)
Bits /
Word Offset
[n:n]
Name
Description
240–241 /
0x1C [16:17]
BWC
[0:1]
Bandwidth control. This 2-bit field provides a mechanism to effectively
throttle the amount of bus bandwidth consumed by the eDMA. In general,
as the eDMA processes the inner minor loop, it continuously generates
read/write sequences until the minor count is exhausted. This field forces
the eDMA to stall after the completion of each read/write access to control
the bus request bandwidth seen by the system bus crossbar switch
(XBAR).
00 No DMA engine stalls
01 Reserved
10 DMA engine stalls for 4 cycles after each r/w
11 DMA engine stalls for 8 cycles after each r/w
242–247 /
0x1C [18:23]
MAJOR.LINKCH
[0:5]
Link channel number.
If channel-to-channel linking on major loop complete is disabled
(TCD.MAJOR.E_LINK = 0) then,
• No channel-to-channel linking (or chaining) is performed after the outer
major loop counter is exhausted.
Otherwise
• After the major loop counter is exhausted, the DMA engine initiates a
channel service request at the channel defined by MAJOR.LINKCH[0:5]
by setting that channel’s TCD.START bit.
248 /
0x1C [24]
DONE
Channel done. This flag indicates the eDMA has completed the outer major
loop. It is set by the DMA engine as the CITER count reaches zero; it is
cleared by software or hardware when the channel is activated (when the
DMA engine has begun processing the channel, not when the first data
transfer occurs).
Note: This bit must be cleared to write the MAJOR.E_LINK or E_SG bits.
249 /
0x1C [25]
ACTIVE
Channel active. This flag signals the channel is currently in execution. It is
set when channel service begins, and is cleared by the DMA engine as the
inner minor loop completes or if any error condition is detected.
250 /
0x1C [26]
MAJOR.E_LINK
Enable channel-to-channel linking on major loop completion. As the
channel completes the outer major loop, this flag enables the linking to
another channel, defined by MAJOR.LINKCH[0:5]. The link target channel
initiates a channel service request via an internal mechanism that sets the
TCD.START bit of the specified channel.
NOTE: To support the dynamic linking coherency model, this field is forced
to zero when written to while the TCD.DONE bit is set.
0 The channel-to-channel linking is disabled.
1 The channel-to-channel linking is enabled.
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Table 16-19. TCDn field descriptions (continued)
Bits /
Word Offset
[n:n]
1
16.4
Name
Description
251 /
0x1C [27]
E_SG
Enable scatter-gather processing. As the channel completes the outer
major loop, this flag enables scatter-gather processing in the current
channel. If enabled, the DMA engine uses DLAST_SGA as a memory
pointer to a 0-modulo-32 address containing a 32-byte data structure that
is loaded as the transfer control descriptor into the local memory.
NOTE: To support the dynamic scatter-gather coherency model, this field
is forced to zero when written to while the TCD.DONE bit is set.
0 The current channel’s TCD is normal format.
1 The current channel’s TCD specifies a scatter gather format. The
DLAST_SGA field provides a memory pointer to the next TCD to be
loaded into this channel after the outer major loop completes its
execution.
252 /
0x1C [28]
D_REQ
Disable hardware request. If this flag is set, the eDMA hardware
automatically clears the corresponding EDMA_ERQRL bit when the
current major iteration count reaches zero.
0 The channel’s EDMA_ERQRL bit is not affected.
1 The channel’s EDMA_ERQRL bit is cleared when the outer major loop
is complete.
253 /
0x1C [29]
INT_HALF
Enable an interrupt when major counter is half complete. If this flag is set,
the channel generates an interrupt request by setting the appropriate bit in
the EDMA_ERQRL when the current major iteration count reaches the
halfway point. Specifically, the comparison performed by the eDMA engine
is (CITER == (BITER >> 1)). This halfway point interrupt request is provided
to support double-buffered (also known as ping-pong) schemes, or other
types of data movement where the processor needs an early indication of
the transfer’s progress. CITER = BITER = 1 with INT_HALF enabled will
generate an interrupt as it satisfies the equation (CITER == (BITER >> 1))
after a single activation.
0 The half-point interrupt is disabled.
1 The half-point interrupt is enabled.
254 /
0x1C [30]
INT_MAJ
Enable an interrupt when major iteration count completes. If this flag is set,
the channel generates an interrupt request by setting the appropriate bit in
the EDMA_ERQRL when the current major iteration count reaches zero.
0 The end-of-major loop interrupt is disabled.
1 The end-of-major loop interrupt is enabled.
255 /
0x1C [31]
START
Channel start. If this flag is set the channel is requesting service. The
eDMA hardware automatically clears this flag after the channel begins
execution.
0 The channel is not explicitly started.
1 The channel is explicitly started via a software initiated service request.
The fields implemented at 0x8 depend on whether EDMA_CR(EMLM) is set to 0 or 1. Refer to Table 16-2.
Functional description
This section provides an overview of the microarchitecture and functional operation of the eDMA block.
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The eDMA module is partitioned into two major modules: the DMA engine and the transfer control
descriptor local memory. The DMA engine is further partitioned into four submodules, which are detailed
below.
• DMA engine
— Address path: This module implements registered versions of two channel transfer control
descriptors: channel x and channel y, and is responsible for all the master bus address
calculations. All the implemented channels provide the same functionality. This hardware
structure allows the data transfers associated with one channel to be preempted after the
completion of a read/write sequence if a higher priority channel service request is asserted
while the first channel is active. After a channel is activated, it runs until the minor loop is
completed unless preempted by a higher priority channel. This capability provides a
mechanism (optionally enabled by EDMA_CPRn[ECP]) where a large data move operation
can be preempted to minimize the time another channel is blocked from execution.
When another channel is activated, the contents of its transfer control descriptor is read from
the local memory and loaded into the registers of the other address path channel{x,y}. After
the inner minor loop completes execution, the address path hardware writes the new values for
the TCDn.{SADDR, DADDR, CITER} back into the local memory. If the major iteration
count is exhausted, additional processing is performed, including the final address pointer
updates, reloading the TCDn.CITER field, and a possible fetch of the next TCDn from memory
as part of a scatter-gather operation.
— Data path: This module implements the actual bus master read/write datapath. It includes 32
bytes of register storage (matching the maximum transfer size) and the necessary mux logic to
support any required data alignment. The system read data bus is the primary input, and the
system write data bus is the primary output.
The address and data path modules directly support the two-stage pipelined system bus. The
address path module represents the 1st stage of the bus pipeline (the address phase), while the
data path module implements the second stage of the pipeline (the data phase).
— Program model/channel arbitration: This module implements the first section of eDMA’s
programming model and also the channel arbitration logic. The programming model registers
are connected to the slave bus (not shown). The eDMA peripheral request inputs and eDMA
interrupt request outputs are also connected to this module (via the control logic).
— Control: This module provides all the control functions for the DMA engine. For data transfers
where the source and destination sizes are equal, the DMA engine performs a series of source
read, destination write operations until the number of bytes specified in the inner minor loop
byte count has been moved.
A minor loop interaction is defined as the number of bytes to transfer (nbytes) divided by the
transfer size. Transfer size is defined as:
if (SSIZE < DSIZE)
transfer size = destination transfer size (# of bytes)
else
transfer size = source transfer size (# of bytes)
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Chapter 16 Enhanced Direct Memory Access (eDMA)
•
Minor loop TCD variables are SOFF, SMOD, DOFF, DMOD, NBYTES, SADDR, DADDR,
BWC, ACTIVE, and START. Major loop TCD variables are DLAST, SLAST, CITER, BITER,
DONE, D_REQ, INT_MAJ, MAJOR_LNKCH, and INT_HALF.
For descriptors where the sizes are not equal, multiple access of the smaller size data are
required for each reference of the larger size. For example, if the source size references 16-bit
data and the destination is 32-bit data, two reads are performed, then one 32-bit write.
TCD local memory
— Memory controller: This logic implements the required dual-ported controller, handling
accesses from both the DMA engine as well as references from the slave bus. As noted earlier,
in the event of simultaneous accesses, the DMA engine is given priority and the slave
transaction is stalled. The hooks to a BIST controller for the local TCD memory are included
in this module.
— Memory array: The TCD is implemented using a single-ported, synchronous compiled RAM
memory array.
16.4.1
eDMA basic data flow
The eDMA transfers data based on a two-deep, nested flow. The basic flow of a data transfer can be
partitioned into three segments. As shown in Figure 16-19, the first segment involves the channel service
request. In the diagram, this example uses the assertion of the eDMA peripheral request signal to request
service for channel n. Channel service request via software and the TCDn.START bit follows the same
basic flow as an eDMA peripheral request. The eDMA peripheral request input signal is registered
internally and then routed to through the DMA engine, first through the control module, then into the
program model/channel arbitration module. In the next cycle, the channel arbitration is performed using
the fixed-priority or round-robin algorithm. After the arbitration is complete, the activated channel number
is sent through the address path and converted into the required address to access the TCD local memory.
Next, the TCD memory is accessed and the required descriptor read from the local memory and loaded
into the DMA engine address path channel{x,y} registers. The TCD memory is organized 64 bits in width
to minimize the time needed to fetch the activated channel’s descriptor and load it into the eDMA engine
address path channel{x,y} registers.
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eDMA
SRAM
Transfer control descriptor
(TCD)
Slave write address
Slave write data
TCD0
TCDn – 1
Slave interface
System bus
SRAM
eDMA engine
Bus read data
Program model/
channel arbitration
Data path
Address
path
Control
Slave read data
Bus write data
Bus address
n = 16 channels
eDMA interrupt request
eDMA done handshake
eDMA peripheral request
Figure 16-19. eDMA operation, part 1
In the second part of the basic data flow as shown in Figure 16-20, the modules associated with the data
transfer (address path, data path, and control) sequence through the required source reads and destination
writes to perform the actual data movement. The source reads are initiated and the fetched data is
temporarily stored in the data path module until it is gated onto the system bus during the destination write.
This source read/destination write processing continues until the inner minor byte count has been
transferred. The eDMA done handshake signal is asserted at the end of the minor byte count transfer.
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SRAM
Transfer control descriptor
(TCD)
eDMA
Slave write address
Slave write data
TCD0
TCDn – 1
Slave interface
System bus
SRAM
eDMA engine
Bus read data
Program model/
channel arbitration
Data path
Address
path
Control
Slave read data
Bus write data
Bus address
n = 16 channels
eDMA peripheral
request
eDMA interrupt request
eDMA done handshake
Figure 16-20. eDMA operation, part 2
After the inner minor byte count has been moved, the final phase of the basic data flow is performed. In
this segment, the address path logic performs the required updates to certain fields in the channel’s TCD;
for example, SADDR, DADDR, CITER. If the outer major iteration count is exhausted, then there are
additional operations performed. These include the final address adjustments and reloading of the BITER
field into the CITER. Additionally, assertion of an optional interrupt request occurs at this time, as does a
possible fetch of a new TCD from memory using the scatter-gather address pointer included in the
descriptor. The updates to the TCD memory and the assertion of an interrupt request are shown in
Figure 16-21.
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eDMA
SRAM
Transfer control descriptor
(TCD)
Slave write address
Slave write data
TCD0
TCDn – 1
Slave interface
System bus
SRAM
eDMA engine
Bus read data
Program model/
channel arbitration
Address
path
Data path
Control
Slave read data
Bus write data
Bus address
n = 16 channels
eDMA peripheral
request
eDMA done
Figure 16-21. eDMA operation, part 3
16.5
16.5.1
Initialization / application information
eDMA initialization
A typical initialization of the eDMA has the following sequence:
1. Write the EDMA_CR if a configuration other than the default is desired.
2. Write the channel priority levels into the EDMA_CPRn registers if a configuration other than the
default is desired.
3. Enable error interrupts in the EDMA_EEIRL and/or EDMA_EEIRH registers if desired.
4. Write the 32-byte TCD for each channel that may request service.
5. Enable any hardware service requests via the EDMA_ERQRH and/or EDMA_ERQRL registers.
6. Request channel service by software (setting the TCD.START bit) or by hardware (slave device
asserting its DMA peripheral request signal).
After any channel requests service, a channel is selected for execution based on the arbitration and priority
levels written into the programmer's model. The DMA engine will read the entire TCD, including the
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primary transfer control parameter shown in Table 16-20, for the selected channel into its internal address
path module. As the TCD is being read, the first transfer is initiated on the system bus unless a
configuration error is detected. Transfers from the source (as defined by the source address, TCD.SADDR)
to the destination (as defined by the destination address, TCD.DADDR) continue until the specified
number of bytes (TCD.NBYTES) have been transferred. When the transfer is complete, the DMA engine's
local TCD.SADDR, TCD.DADDR, and TCD.CITER are written back to the main TCD memory and any
minor loop channel linking is performed, if enabled. If the major loop is exhausted, further post processing
is executed; for example, interrupts, major loop channel linking, and scatter-gather operations, if enabled.
Table 16-20. TCD primary control and status fields
TCD field name
Description
START
Control bit to start channel when using a software initiated DMA service
(Automatically cleared by hardware)
ACTIVE
Status bit indicating the channel is currently in execution
DONE
Status bit indicating major loop completion (cleared by software when using a
software initiated DMA service)
D_REQ
Control bit to disable DMA request at end of major loop completion when using
a hardware-initiated DMA service
BWC
Control bits for throttling bandwidth control of a channel
E_SG
Control bit to enable scatter-gather feature
INT_HALF
Control bit to enable interrupt when major loop is half complete
INT_MAJ
Control bit to enable interrupt when major loop completes
Figure 16-22 shows how each DMA request initiates one minor loop transfer (iteration) without CPU
intervention. DMA arbitration can occur after each minor loop, and one level of minor loop DMA
preemption is allowed. The number of minor loops in a major loop is specified by the beginning iteration
count (biter).
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Current major loop
iteration count
(CITER)
Example memory array
DMA request
•
•
•
Minor loop
•
•
•
Minor loop
•
•
•
Minor loop
3
DMA request
Major loop
2
DMA request
1
Figure 16-22. Example of multiple loop iterations
Figure 16-23 lists the memory array terms and how the TCD settings interrelate.
xADDR:
(Starting address)
xSIZE:
(Size of one data
transfer)
•
•
•
Minor loop
(NBYTES in
minor loop, often
the same value
as xSIZE)
•
•
•
•
•
•
Minor loop
xLAST: Number of bytes
added to current address
after major loop
(typically used to
loop back)
•
•
•
Last minor loop
Offset (xOFF): Number of
bytes added to current
address after each transfer
(Often the same value
as xSIZE)
Each DMA source (S) and
destination (D) has its own:
• Address (xADDR)
• Size (xSIZE)
• Offset (xOFF)
• Modulo (xMOD)
• Last address adjustment
(xLAST) where x = S or D
Peripheral queues typically
have size and offset
equal to NBYTES
Figure 16-23. Memory array terms
16.5.2
DMA programming errors
The DMA performs various tests on the transfer control descriptor to verify consistency in the descriptor
data. Most programming errors are reported on a per-channel basis with the exception of channel-priority
error, or EDMA_ESR[CPE].
For all error types other than channel-priority errors, the channel number causing the error is recorded in
the EDMA_ESR. If the error source is not removed before the next activation of the problem channel, the
error will be detected and recorded again.
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If priority levels are not unique, the highest (channel) priority that has an active request is selected, but the
lowest numbered (channel) with that priority is selected by arbitration and executed by the DMA engine.
The hardware service request handshake signals, error interrupts, and error reporting are associated with
the selected channel.
16.5.3
DMA request assignments
The assignments between the DMA requests from the modules to the channels of the eDMA are shown in
Table 16-21. The source column is written in C language syntax. The syntax is
module_instance.register[bit].
Table 16-21. DMA request summary for eDMA
DMA Request
Channel
Source
Description
DMA_MUX_CHCONFIG0_SOURCE
0
DMA_MUX.CHCONFIG0[SOURCE]
DMA MUX channel 0 source
DMA_MUX_CHCONFIG1_SOURCE
1
DMA_MUX.CHCONFIG1[SOURCE]
DMA MUX channel 1 source
DMA_MUX_CHCONFIG2_SOURCE
2
DMA_MUX.CHCONFIG2[SOURCE]
DMA MUX channel 2 source
DMA_MUX_CHCONFIG3_SOURCE
3
DMA_MUX.CHCONFIG3[SOURCE]
DMA MUX channel 3 source
DMA_MUX_CHCONFIG4_SOURCE
4
DMA_MUX.CHCONFIG4[SOURCE]
DMA MUX channel 4 source
DMA_MUX_CHCONFIG5_SOURCE
5
DMA_MUX.CHCONFIG5[SOURCE]
DMA MUX channel 5 source
DMA_MUX_CHCONFIG6_SOURCE
6
DMA_MUX.CHCONFIG6[SOURCE]
DMA MUX channel 6 source
DMA_MUX_CHCONFIG7_SOURCE
7
DMA_MUX.CHCONFIG7[SOURCE]
DMA MUX channel 7 source
DMA_MUX_CHCONFIG8_SOURCE
8
DMA_MUX.CHCONFIG8[SOURCE]
DMA MUX channel 8 source
DMA_MUX_CHCONFIG9_SOURCE
9
DMA_MUX.CHCONFIG9[SOURCE]
DMA MUX channel 9 source
DMA_MUX_CHCONFIG10_SOURCE
10
DMA_MUX.CHCONFIG10[SOURCE]
DMA MUX channel 10 source
DMA_MUX_CHCONFIG11_SOURCE
11
DMA_MUX.CHCONFIG11[SOURCE]
DMA MUX channel 11 source
DMA_MUX_CHCONFIG12_SOURCE
12
DMA_MUX.CHCONFIG12[SOURCE]
DMA MUX channel 12 source
DMA_MUX_CHCONFIG13_SOURCE
13
DMA_MUX.CHCONFIG13[SOURCE]
DMA MUX channel 13 source
DMA_MUX_CHCONFIG14_SOURCE
14
DMA_MUX.CHCONFIG14[SOURCE]
DMA MUX channel 14 source
DMA_MUX_CHCONFIG15_SOURCE
15
DMA_MUX.CHCONFIG15[SOURCE]
DMA MUX channel 15 source
16.5.4
16.5.4.1
DMA arbitration mode considerations
Fixed-channel arbitration
In this mode, the channel service request from the highest priority channel is selected to execute.
Preemption is available in this scenario only.
16.5.4.2
Round-robin channel arbitration
In this mode, channels are serviced starting with the highest channel number and rotating through to the
lowest channel number without regard to the assigned channel priority levels.
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16.5.5
16.5.5.1
DMA transfer
Single request
To perform a simple transfer of n bytes of data with one activation, set the major loop to 1
(TCD.CITER = TCD.BITER = 1). The data transfer will begin after the channel service request is
acknowledged and the channel is selected to execute. After the transfer is complete, the TCD.DONE bit
will be set and an interrupt will be generated if properly enabled.
For example, the following TCD entry is configured to transfer 16 bytes of data. The eDMA is
programmed for one iteration of the major loop transferring 16 bytes per iteration. The source memory has
a byte-wide memory port located at 0x1000. The destination memory has a word wide port located at
0x2000. The address offsets are programmed in increments to match the size of the transfer; 1 byte for the
source and 4 bytes for the destination. The final source and destination addresses are adjusted to return to
their beginning values.
TCD.CITER = TCD.BITER = 1
TCD.NBYTES = 16
TCD.SADDR = 0x1000
TCD.SOFF = 1
TCD.SSIZE = 0
TCD.SLAST = –16
TCD.DADDR = 0x2000
TCD.DOFF = 4
TCD.DSIZE = 2
TCD.DLAST_SGA= –16
TCD.INT_MAJ = 1
TCD.START = 1 (Must be written last after all other fields have been initialized)
All other TCD fields = 0
This would generate the following sequence of events:
1. Slave write to the TCD.START bit requests channel service.
2. The channel is selected by arbitration for servicing.
3. eDMA engine writes: TCD.DONE = 0, TCD.START = 0, TCD.ACTIVE = 1.
4. eDMA engine reads: channel TCD data from local memory to internal register file.
5. The source to destination transfers are executed as follows:
a) read_byte(0x1000), read_byte(0x1001), read_byte(0x1002), read_byte(0x1003)
b) write_word(0x2000)  first iteration of the minor loop
c) read_byte(0x1004), read_byte(0x1005), read_byte(0x1006), read_byte(0x1007)
d) write_word(0x2004)  second iteration of the minor loop
e) read_byte(0x1008), read_byte(0x1009), read_byte(0x100a), read_byte(0x100b)
f) write_word(0x2008)  third iteration of the minor loop
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g) read_byte(0x100c), read_byte(0x100d), read_byte(0x100e), read_byte(0x100f)
h) write_word(0x200c)  last iteration of the minor loop  major loop complete
6. eDMA engine writes: TCD.SADDR = 0x1000, TCD.DADDR = 0x2000, TCD.CITER = 1
(TCD.BITER).
7. eDMA engine writes: TCD.ACTIVE = 0, TCD.DONE = 1, EDMA_IRQRn = 1.
8. The channel retires.
The eDMA goes idle or services the next channel.
16.5.5.2
Multiple requests
The next example is the same as previous, excepting transferring 32 bytes via two hardware requests. The
only fields that change are the major loop iteration count and the final address offsets. The eDMA is
programmed for two iterations of the major loop transferring 16 bytes per iteration. After the channel’s
hardware requests are enabled in the EDMA_ERQR, channel service requests are initiated by the slave
device (ERQR should be set after TCD). Note that TCD.START = 0.
TCD.CITER = TCD.BITER = 2
TCD.NBYTES = 16
TCD.SADDR = 0x1000
TCD.SOFF = 1
TCD.SSIZE = 0
TCD.SLAST = –32
TCD.DADDR = 0x2000
TCD.DOFF = 4
TCD.DSIZE = 2
TCD.DLAST_SGA= –32
TCD.INT_MAJ = 1
TCD.START = 0 (Must be written last after all other fields have been initialized)
All other TCD fields = 0
This generates the following sequence of events:
1. First hardware (eDMA peripheral request) request for channel service.
2. The channel is selected by arbitration for servicing.
3. eDMA engine writes: TCD.DONE = 0, TCD.START = 0, TCD.ACTIVE = 1.
4. eDMA engine reads: channel TCD data from local memory to internal register file.
5. The source to destination transfers are executed as follows:
a) read_byte(0x1000), read_byte(0x1001), read_byte(0x1002), read_byte(0x1003)
b) write_word(0x2000)  first iteration of the minor loop
c) read_byte(0x1004), read_byte(0x1005), read_byte(0x1006), read_byte(0x1007)
d) write_word(0x2004)  second iteration of the minor loop
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e) read_byte(0x1008), read_byte(0x1009), read_byte(0x100a), read_byte(0x100b)
f) write_word(0x2008)  third iteration of the minor loop
g) read_byte(0x100c), read_byte(0x100d), read_byte(0x100e), read_byte(0x100f)
h) write_word(0x200c)  last iteration of the minor loop
6. eDMA engine writes: TCD.SADDR = 0x1010, TCD.DADDR = 0x2010, TCD.CITER = 1.
7. eDMA engine writes: TCD.ACTIVE = 0.
8. The channel retires  one iteration of the major loop.
The eDMA goes idle or services the next channel.
9. Second hardware (eDMA peripheral request) requests channel service.
10. The channel is selected by arbitration for servicing.
11. eDMA engine writes: TCD.DONE = 0, TCD.START = 0, TCD.ACTIVE = 1.
12. eDMA engine reads: channel TCD data from local memory to internal register file.
13. The source to destination transfers are executed as follows:
a) read_byte(0x1010), read_byte(0x1011), read_byte(0x1012), read_byte(0x1013)
b) write_word(0x2010)  first iteration of the minor loop
c) read_byte(0x1014), read_byte(0x1015), read_byte(0x1016), read_byte(0x1017)
d) write_word(0x2014)  second iteration of the minor loop
e) read_byte(0x1018), read_byte(0x1019), read_byte(0x101a), read_byte(0x101b)
f) write_word(0x2018)  third iteration of the minor loop
g) read_byte(0x101c), read_byte(0x101d), read_byte(0x101e), read_byte(0x101f)
h) write_word(0x201c)  last iteration of the minor loop  major loop complete
14. eDMA engine writes: TCD.SADDR = 0x1000, TCD.DADDR = 0x2000, TCD.CITER = 2
(TCD.BITER).
15. eDMA engine writes: TCD.ACTIVE = 0, TCD.DONE = 1, EDMA_IRQRn = 1.
16. The channel retires  major loop complete.
The eDMA goes idle or services the next channel.
16.5.5.3
Modulo feature
The modulo feature of the eDMA provides the ability to implement a circular data queue in which the size
of the queue is a power of two. MOD is a 5-bit field for both the source and destination in the TCD and
specifies which lower address bits are allowed to increment from their original value after the
address + offset calculation. All upper address bits remain the same as in the original value. A setting of 0
for this field disables the modulo feature.
Table 16-22 shows how the transfer addresses are specified based on the setting of the MOD field. Here a
circular buffer is created where the address wraps to the original value while the 28 upper address bits
(0x1234567x) retain their original value. In this example the source address is set to 0x12345670, the
offset is set to 4 bytes and the mod field is set to 4, allowing for a 24 byte (16-byte) size queue.
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Table 16-22. Modulo Feature Example
16.5.6
16.5.6.1
Transfer
Number
Address
1
0x12345670
2
0x12345674
3
0x12345678
4
0x1234567C
5
0x12345670
6
0x12345674
TCD status
Minor loop complete
There are two methods to test for minor loop completion when using software initiated service requests.
The first method is to read the TCD.CITER field and test for a change. Another method may be extracted
from the sequence below. The second method is to test the TCD.START bit AND the TCD.ACTIVE bit.
The minor loop complete condition is indicated by both bits reading zero after the TCD.START was
written to a 1. Polling the TCD.ACTIVE bit may be inconclusive because the active status may be missed
if the channel execution is short in duration.
The TCD status bits execute the following sequence for a software activated channel:
1. TCD.START = 1, TCD.ACTIVE = 0, TCD.DONE = 0 (channel service request via software).
2. TCD.START = 0, TCD.ACTIVE = 1, TCD.DONE = 0 (channel is executing).
3. TCD.START = 0, TCD.ACTIVE = 0, TCD.DONE = 0 (channel has completed the minor loop and
is idle), or
4. TCD.START = 0, TCD.ACTIVE = 0, TCD.DONE = 1 (channel has completed the major loop and
is idle).
The best method to test for minor loop completion when using hardware initiated service requests is to
read the TCD.CITER field and test for a change. The hardware request and acknowledge handshakes
signals are not visible in the programmer’s model.
The TCD status bits execute the following sequence for a hardware activated channel:
1. eDMA peripheral request asserts (channel service request via hardware).
2. TCD.START = 0, TCD.ACTIVE = 1, TCD.DONE = 0 (channel is executing).
3. TCD.START = 0, TCD.ACTIVE = 0, TCD.DONE = 0 (channel has completed the minor loop and
is idle), or
4. TCD.START = 0, TCD.ACTIVE = 0, TCD.DONE = 1 (channel has completed the major loop and
is idle).
For both activation types, the major loop complete status is explicitly indicated via the TCD.DONE bit.
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The TCD.START bit is cleared automatically when the channel begins execution, regardless of how the
channel was activated.
16.5.6.2
Active channel TCD reads
The eDMA will read back the true TCD.SADDR, TCD.DADDR, and TCD.NBYTES values if read while
a channel is executing. The true values of the SADDR, DADDR, and NBYTES are the values the eDMA
engine is currently using in its internal register file and not the values in the TCD local memory for that
channel. The addresses (SADDR and DADDR) and NBYTES (decrements to 0 as the transfer progresses)
can give an indication of the progress of the transfer. All other values are read back from the TCD local
memory.
16.5.6.3
Preemption status
Preemption is available only when fixed arbitration is selected for channel-arbitration mode. A
preemptable situation is one in which a preempt-enabled channel is running and a higher priority request
becomes active. When the eDMA engine is not operating in fixed-channel arbitration mode, the
determination of the relative priority of the actively running and the outstanding requests become
undefined. Channel priorities are treated as equal (or more exactly, constantly rotating) when round-robin
arbitration mode is selected.
The TCD.ACTIVE bit for the preempted channel remains asserted throughout the preemption. The
preempted channel is temporarily suspended while the preempting channel executes one iteration of the
major loop. Two TCD.ACTIVE bits set at the same time in the overall TCD map indicates a higher priority
channel is actively preempting a lower priority channel.
16.5.7
Channel linking
Channel linking (or chaining) is a mechanism in which one channel sets the TCD.START bit of another
channel (or itself), thus initiating a service request for that channel. This operation is automatically
performed by the eDMA engine at the conclusion of the major or minor loop when properly enabled.
The minor loop channel linking occurs at the completion of the minor loop (or one iteration of the major
loop). The TCD.CITER.E_LINK field are used to determine whether a minor loop link is requested. When
enabled, the channel link is made after each iteration of the minor loop except for the last. When the major
loop is exhausted, only the major loop channel link fields are used to determine if a channel link should be
made. For example, with the initial fields of:
TCD.CITER.E_LINK = 1
TCD.CITER.LINKCH = 0xC
TCD.CITER value = 0x4
TCD.MAJOR.E_LINK = 1
TCD.MAJOR.LINKCH = 0x7
will execute as:
1. Minor loop done  set channel 12 TCD.START bit
2. Minor loop done  set channel 12 TCD.START bit
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3. Minor loop done  set channel 12 TCD.START bit
4. Minor loop done, major loop done  set channel 7 TCD.START bit
When minor loop linking is enabled (TCD.CITER.E_LINK = 1), the TCD.CITER field uses a nine bit
vector to form the current iteration count.
When minor loop linking is disabled (TCD.CITER.E_LINK = 0), the TCD.CITER field uses a 15-bit
vector to form the current iteration count. The bits associated with the TCD.CITER.LINKCH field are
concatenated onto the CITER value to increase the range of the CITER.
NOTE
After configuration, the TCD.CITER.E_LINK bit and the
TCD.BITER.E_LINK bit must be equal or a configuration error will be
reported. The CITER and BITER vector widths must be equal to calculate
the major loop, halfway done interrupt point.
Table 16-23 summarizes how a DMA channel can link to another DMA channel, i.e, use another channel’s
TCD, at the end of a loop.
Table 16-23. Channel linking parameters
Desired Link
Behavior
Link at end of
minor loop
Link at end of
major loop
16.5.8
16.5.8.1
TCD Control Field Name
Description
citer.e_link
Enable channel-to-channel linking on minor loop
completion (current iteration).
citer.linkch
Link channel number when linking at end of minor loop
(current iteration).
major.e_link
Enable channel-to-channel linking on major loop
completion.
major.linkch
Link channel number when linking at end of major loop.
Dynamic programming
Dynamic channel linking
Dynamic channel linking is the process of setting the TCD.major.e_link bit during channel execution. This
bit is read from the TCD local memory at the end of channel execution, thus allowing the user to enable
the feature during channel execution.
Because the user is allowed to change the configuration during execution, a coherency model is needed.
Consider the scenario where the user attempts to execute a dynamic channel link by enabling the
TCD.major.e_link bit at the same time the eDMA engine is retiring the channel. The TCD.major.e_link
would be set in the programmer’s model, but it would be unclear whether the actual link was made before
the channel retired.
The coherency model in Table 16-24 is recommended when executing a dynamic channel link request.
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Table 16-24. Coherency model for a dynamic channel link request
Step
Action
1
Write 1b to the TCD.major.e_link bit.
2
Read back the TCD.major.e_link bit.
3
Test the TCD.major.e_link request status:
• If TCD.major.e_link = 1b, the dynamic link attempt was successful.
• If TCD.major.e_link = 0b, the attempted dynamic link did not succeed (the channel was
already retiring).
For this request, the TCD local memory controller forces the TCD.major.e_link bit to zero on any writes
to a channel’s TCD.word7 after that channel’s TCD.done bit is set, indicating the major loop is complete.
NOTE
The user must clear the TCD.done bit before writing the TCD.major.e_link
bit. The TCD.done bit is cleared automatically by the eDMA engine after a
channel begins execution.
16.5.8.2
Dynamic scatter/gather
Dynamic scatter/gather is the process of setting the TCD.e_sg bit during channel execution. This bit is read
from the TCD local memory at the end of channel execution, thus allowing the user to enable the feature
during channel execution.
Because the user is allowed to change the configuration during execution, a coherency model is needed.
Consider the scenario where the user attempts to execute a dynamic scatter/gather operation by enabling
the TCD.e_sg bit at the same time the eDMA engine is retiring the channel. The TCD.e_sg would be set
in the programmer’s model, but it would be unclear whether the actual scatter/gather request was honored
before the channel retired.
Two methods for this coherency model are shown in the following subsections. Method 1 has the
advantage of reading the major.linkch field and the e_sg bit with a single read. For both dynamic channel
linking and scatter/gather requests, the TCD local memory controller forces the TCD.major.e_link and
TCD.e_sg bits to zero on any writes to a channel’s TCD.word7 if that channel’s TCD.done bit is set
indicating the major loop is complete.
NOTE
The user must clear the TCD.done bit before writing the TCD.major.e_link
or TCD.e_sg bits. The TCD.done bit is cleared automatically by the eDMA
engine after a channel begins execution.
16.5.8.2.1
Method 1 (channel not using major loop channel linking)
For a channel not using major loop channel linking, the coherency model in Table 16-25 may be used for
a dynamic scatter/gather request.
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When the TCD.major.e_link bit is zero, the TCD.major.linkch field is not used by the eDMA. In this case,
the TCD.major.linkch bits may be used for other purposes. This method uses the TCD.major.linkch field
as a TCD identification (ID).
Table 16-25. Coherency model for method 1
16.5.8.2.2
Step
Action
1
When the descriptors are built, write a unique TCD ID in the TCD.major.linkch field for each
TCD associated with a channel using dynamic scatter/gather.
2
Write 1b to theTCD.d_req bit.
Note: Should a dynamic scatter/gather attempt fail, setting the d_req bit will prevent a future
hardware activation of this channel. This stops the channel from executing with a
destination address (daddr) that was calculated using a scatter/gather address
(written in the next step) instead of a dlast final offset value.
3
Write theTCD.dlast_sga field with the scatter/gather address.
4
Write 1b to the TCD.e_sg bit.
5
Read back the 16 bit TCD control/status field.
6
Test the TCD.e_sg request status and TCD.major.linkch value:
• If e_sg = 1b, the dynamic link attempt was successful.
• If e_sg = 0b and the major.linkch (ID) did not change, the attempted dynamic link did not
succeed (the channel was already retiring).
• If e_sg = 0b and the major.linkch (ID) changed, the dynamic link attempt was successful
(the new TCD’s e_sg value cleared the e_sg bit).
Method 2 (channel using major loop linking)
For a channel using major loop channel linking, the coherency model in Table 16-26 may be used for a
dynamic scatter/gather request. This method uses the TCD.dlast_sga field as a TCD identification (ID).
Table 16-26. Coherency model for method 2
Step
Action
1
Write 1b to theTCD.d_req bit.
Note: Should a dynamic scatter/gather attempt fail, setting the d_req bit will prevent a future
hardware activation of this channel. This stops the channel from executing with a
destination address (daddr) that was calculated using a scatter/gather address
(written in the next step) instead of a dlast final offset value.
2
Write theTCD.dlast_sga field with the scatter/gather address.
3
Write 1b to the TCD.e_sg bit.
4
Read back the TCD.e_sg bit.
5
Test the TCD.e_sg request status:
• If e_sg = 1b, the dynamic link attempt was successful.
• If e_sg = 0b, read the 32 bit TCD dlast_sga field.
• If e_sg = 0b and the dlast_sga did not change, the attempted dynamic link did not
succeed (the channel was already retiring).
• If e_sg = 0b and the dlast_sga changed, the dynamic link attempt was successful (the
new TCD’s e_sg value cleared the e_sg bit).
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Chapter 17 eDMA Channel Multiplexer (DMA_MUX)
Chapter 17
eDMA Channel Multiplexer (DMA_MUX)
17.1
Introduction
The eDMA channel multiplexer (DMA_MUX) allows the routing of 59 DMA sources (slots) to 16 eDMA
channels. This is illustrated in Figure 17-1.
Source #1
DMA_MUX
eDMA Channel #0
eDMA Channel #1
Source #2
Source #3
Source #59
Always enabled
Always enabled
Trigger #1
eDMA Channel #15
Trigger #4
Figure 17-1. DMA_MUX block diagram
17.2
Features
The DMA_MUX has these major features:
• 16 independently selectable eDMA channel routers
— Four channels with normal or periodic triggering capability
— 12 channels with normal capability
• Capability to assign each channel router to one of 59 possible peripheral DMA sources, four always
enabled sources, or one always disabled source
• Three modes of operation:
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— Disabled
— Normal
— Periodic Trigger
17.3
Modes of operation
The following operation modes are available:
• Disabled Mode — In this mode, the eDMA channel is disabled. Since disabling and enabling of
eDMA channels is done primarily via the eDMA configuration registers, this mode is used mainly
as the reset state for an eDMA channel in the DMA_MUX. It may also be used to temporarily
suspend an eDMA channel while reconfiguration of the system takes place (for example, changing
the period of an eDMA trigger).
• Normal Mode — In this mode, an eDMA source (such as DSPI_0_TX or DSPI_0_RX example)
is routed directly to the specified eDMA channel. The operation of the DMA_MUX in this mode
is completely transparent to the system.
• Periodic Trigger Mode — In this mode, an eDMA source may only request an eDMA transfer
(such as when a transmit buffer becomes empty or a receive buffer becomes full) periodically. The
period is configured in the registers of the Periodic Interrupt Timer (PIT).
eDMA channels 0–3 may be used in all three modes, but channels 4–15 may only be configured to disabled
or normal mode.
17.4
External signal description
The DMA_MUX has no external pins.
17.5
Memory map and register definition
Table 17-1 shows the memory map for the DMA_MUX. Note that all addresses are offsets; the absolute
address may be computed by adding the specified offset to the base address of the DMA_MUX.
Table 17-1. DMA_MUX memory map
Base address: 0xFFFD_C000
Address offset
Register
Location
0x0
Channel #0 Configuration (CHCONFIG0)
on page 297
0x1
Channel #1 Configuration (CHCONFIG1)
on page 297
...
...
0xF
Channel #15 Configuration (CHCONFIG15)
...
on page 297
All registers are accessible via 8-, 16-, or 32-bit accesses. However, 16-bit accesses must be aligned to
16-bit boundaries, and 32-bit accesses must be aligned to 32-bit boundaries. As an example, CHCONFIG0
through CHCONFIG3 are accessible by a 32-bit read/write to address Base + 0x00, but performing a
32-bit access to address Base + 0x01 is illegal.
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17.5.1
Channel configuration registers (CHCONFIGn)
Each of the total of 16 eDMA channels can be independently enabled/disabled and associated with 1 of
the 28 peripheral eDMA sources + 1 of the four always enabled eDMA sources in the system.
Offset: 0x0 + n (16 registers)
Access: User read/write
0
1
ENBL
TRIG
0
0
2
3
4
5
6
7
0
0
0
R
SOURCE
W
Reset
0
0
0
Figure 17-2. Channel Configuration Registers (CHCONFIGn)
Table 17-2. CHCONFIGn field descriptions
Field
Description
ENBL
eDMA Channel Enable
ENBL enables the eDMA channel.
0 eDMA channel is disabled. This mode is primarily used during configuration of the DMA_MUX.
The eDMA has separate channel enables/disables, which should be used to disable or reconfigure
an eDMA channel.
1 eDMA channel is enabled
TRIG
eDMA Channel Trigger Enable (for triggered channels only)
TRIG enables the periodic trigger capability for the eDMA channel.
0 Periodic triggering is disabled. If periodic triggering is disabled, and the ENBL bit is set, the
DMA_MUX will simply route the specified source to the eDMA channel.
1 Triggering is enabled
SOURCE
eDMA Channel Source (slot)
SOURCE specifies which eDMA source, if any, is routed to a particular eDMA channel. Please see
Table 17-4 for DMA_MUX inputs mapping.
Table 17-3. Channel and trigger enabling
ENBL
TRIG
Function
0
X
eDMA channel is disabled
1
0
eDMA channel is enabled with no triggering
(transparent)
1
1
eDMA channel is enabled with triggering
Mode
Disabled Mode
Normal Mode
Periodic Trigger Mode
NOTE
Setting multiple CHCONFIG registers with the same Source value results
in unpredictable behavior.
NOTE
Before changing the trigger or source settings an eDMA channel must be
disabled via the CHCONFIGn[ENBL] bit.
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17.6
17.6.1
DMA_MUX inputs
DMA_MUX peripheral sources
Table 17-4. eDMA channel mapping
DMA_MUX channel
Module
eDMA requesting module
DMA_MUX input #
0
—
Always disabled
—
1
DSPI 0
DSPI_0 TX
DMA_MUX Source #1
2
DSPI 0
DSPI_0 RX
DMA_MUX Source #2
3
DSPI 1
DSPI_1 TX
DMA_MUX Source #3
4
DSPI 1
DSPI_1 RX
DMA_MUX Source #4
5
DSPI 2
DSPI_2 TX
DMA_MUX Source #5
6
DSPI 2
DSPI_2 RX
DMA_MUX Source #6
7
DSPI 3
DSPI_3 TX
DMA_MUX Source #7
8
DSPI 3
DSPI_3 RX
DMA_MUX Source #8
9
DSPI 4
DSPI_4 TX
DMA_MUX Source #9
10
DSPI 4
DSPI_4 RX
DMA_MUX Source #10
11
DSPI 5
DSPI_5 TX
DMA_MUX Source #11
12
DSPI 5
DSPI_5 RX
DMA_MUX Source #12
13
—
—
DMA_MUX Source #13
14
—
—
DMA_MUX Source #14
15
—
—
DMA_MUX Source #15
16
—
—
DMA_MUX Source #16
17
eMIOS 0
EMIOS0_CH0
DMA_MUX Source #17
18
eMIOS 0
EMIOS0_CH1
DMA_MUX Source #18
19
eMIOS 0
EMIOS0_CH9
DMA_MUX Source #19
20
eMIOS 0
EMIOS0_CH18
DMA_MUX Source #20
21
eMIOS 0
EMIOS0_CH25
DMA_MUX Source #21
22
eMIOS 0
EMIOS0_CH26
DMA_MUX Source #22
23
eMIOS 1
EMIOS1_CH0
DMA_MUX Source #23
24
eMIOS 1
EMIOS1_CH9
DMA_MUX Source #24
25
eMIOS 1
EMIOS1_CH17
DMA_MUX Source #25
26
eMIOS 1
EMIOS1_CH18
DMA_MUX Source #26
27
eMIOS 1
EMIOS1_CH25
DMA_MUX Source #27
28
eMIOS 1
EMIOS1_CH26
DMA_MUX Source #28
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Table 17-4. eDMA channel mapping (continued)
DMA_MUX channel
Module
eDMA requesting module
DMA_MUX input #
29
ADC 0
ADC0_EOC
DMA_MUX Source #29
30
ADC 1
ADC1_EOC
DMA_MUX Source #30
31
I2C
IIC_RX
DMA_MUX Source #31
32
I2C
IIC_TX
DMA_MUX Source #32
33
LINFLEX
0
LINFLEX0_RX
DMA_MUX Source #33
34
LINFLEX
0
LINFLEX0_TX
DMA_MUX Source #34
35
LINFLEX
1
LINFLEX1_RX
DMA_MUX Source #35
36
LINFLEX
1
LINFLEX1_TX
DMA_MUX Source #36
37
—
—
DMA_MUX Source #37
38
—
—
DMA_MUX Source #38
39
—
—
DMA_MUX Source #39
40
—
—
DMA_MUX Source #40
41
—
—
DMA_MUX Source #41
42
—
—
DMA_MUX Source #42
43
—
—
DMA_MUX Source #43
44
—
—
DMA_MUX Source #44
45
—
—
DMA_MUX Source #45
46
—
—
DMA_MUX Source #46
47
—
—
DMA_MUX Source #47
48
—
—
DMA_MUX Source #48
49
—
—
DMA_MUX Source #49
50
—
—
DMA_MUX Source #50
51
—
—
DMA_MUX Source #51
52
—
—
DMA_MUX Source #52
53
—
—
DMA_MUX Source #53
54
—
—
DMA_MUX Source #54
55
—
—
DMA_MUX Source #55
56
—
—
DMA_MUX Source #56
57
—
—
DMA_MUX Source #57
58
—
—
DMA_MUX Source #58
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Table 17-4. eDMA channel mapping (continued)
DMA_MUX channel
17.6.2
Module
eDMA requesting module
DMA_MUX input #
59
—
—
DMA_MUX Source #59
60
—
ALWAYS ENABLED
DMA_MUX Source #60
61
—
ALWAYS ENABLED
DMA_MUX Source #61
62
—
ALWAYS ENABLED
DMA_MUX Source #62
63
—
ALWAYS ENABLED
DMA_MUX Source #63
DMA_MUX periodic trigger inputs
Table 17-5. DMA_MUX periodic trigger inputs
17.7
DMA_MUX trigger input
PIT channel
Trigger #1
PIT0
Trigger #2
PIT1
Trigger #3
PIT4
Trigger #4
PIT5
Functional description
The primary purpose of the DMA_MUX is to provide flexibility in the system’s use of the available eDMA
channels. As such, configuration of the DMA_MUX is intended to be a static procedure done during
execution of the system boot code. However, if the procedure outlined in Section 17.8.2, Enabling and
configuring sources, is followed, the configuration of the DMA_MUX may be changed during the normal
operation of the system.
Functionally, the DMA_MUX channels may be divided into two classes: Channels that implement the
normal routing functionality plus periodic triggering capability, and channels, that implement only the
normal routing functionality.
17.7.1
eDMA channels with periodic triggering capability
Besides the normal routing functionality, the first four channels of the DMA_MUX provide a special
periodic triggering capability that can be used to provide an automatic mechanism to transmit bytes,
frames or packets at fixed intervals without the need for processor intervention. The trigger is generated
by the periodic interrupt timer (PIT); as such, the configuration of the periodic triggering interval is done
via configuration registers in the PIT. Please see Section 27.5, Periodic Interrupt Timer (PIT), for more
information on this topic.
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NOTE
Because of the dynamic nature of the system (such as eDMA channel
priorities, bus arbitration, or interrupt service routine lengths), the number
of clock cycles between a trigger and the actual eDMA transfer cannot be
guaranteed.
Source #1
Source #2
Source #3
Trigger #1
DMA Channel #0
Trigger #2
Source #28
Always enabled
Trigger #4
DMA Channel #3
Always enabled
Figure 17-3. DMA_MUX channel 0–3 block diagram
The eDMA channel triggering capability allows the system to schedule regular eDMA transfers, usually
on the transmit side of certain peripherals, without the intervention of the processor. This trigger works by
gating the request from the peripheral to the eDMA until a trigger event has been seen. This is illustrated
in Figure 17-4.
Periph Request
Trigger
DMA Request
Figure 17-4. DMA_MUX channel triggering: Normal operation
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Once the eDMA request has been serviced, the peripheral will negate its request, effectively resetting the
gating mechanism until the peripheral reasserts its request AND the next trigger event is seen. This means
that if a trigger is seen, but the peripheral is not requesting a transfer, that triggered will be ignored. This
situation is illustrated in Figure 17-5.
Periph Request
Trigger
DMA Request
Figure 17-5. DMA_MUX channel triggering: Ignored trigger
This triggering capability may be used with any peripheral that supports eDMA transfers, and is most
useful for periodically polling external devices on a particular bus.
As an example, the transmit side of a DSPI is assigned to an eDMA channel with a trigger, as described
above. Once set up, the SPI will request eDMA transfers (presumably from memory) as long as its transmit
buffer is empty. By using a trigger on this channel, the DSPI transfers can be automatically performed
every 5µs (as an example). On the receive side of the SPI, the SPI and eDMA can be configured to transfer
receive data into memory, effectively implementing a method to periodically read data from external
devices and transfer the results into memory without processor intervention.
A more detailed description of the capability of each trigger (such as resolution, or range of values) may
be found in Chapter 27, Timers.
17.7.2
eDMA channels with no triggering capability
Channels 4–15 of the DMA_MUX provide the normal routing functionality as described in Section 17.3,
Modes of operation.
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Source #1
Source #2
Source #3
DMA Channel #4
Source #28
DMA Channel #15
Always enabled
Always enabled
Figure 17-6. DMA_MUX channel 4–15 block diagram
17.8
Initialization/Application information
17.8.1
Reset
The reset state of each individual bit is shown in Section 17.5, Memory map and register definition. In
summary, after reset, all channels are disabled and must be explicitly enabled before use.
17.8.2
17.8.2.1
Enabling and configuring sources
Enabling a source with periodic triggering
The following describes how to enable a source with periodic triggering:
1. Determine with which eDMA channel the source will be associated. Remember that only the first
four eDMA channels have periodic triggering capability.
2. Clear the ENBL and TRIG bits of the eDMA channel.
3. Ensure that the eDMA channel is properly configured in the eDMA. The eDMA channel may be
enabled at this point.
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4. In the PIT, configure the corresponding timer.
5. Select the source to be routed to the eDMA channel. Write to the corresponding CHCONFIG
register, ensuring that the ENBL and TRIG bits are set.
Example 17-1. Configure source #3 Transmit for use with eDMA Channel 2, with periodic triggering
capability
1.
2.
3.
4.
Write 0x00 to CHCONFIG2 (Base Address + 0x02)
Configure Channel 2 in the eDMA, including enabling the channel
Configure Timer 4 in the Periodic Interrupt Timer (PIT) for the desired trigger interval
Write 0xC3 to CHCONFIG2 (Base Address + 0x02)
The following code example illustrates steps #1 and #4 above:
In File registers.h:
#define DMAMUX_BASE_ADDR
0xFC084000/* Example only ! */
/* Following example assumes char is 8 bits */
volatile unsigned char *CHCONFIG2 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0002);
In File main.c:
#include "registers.h"
:
:
*CHCONFIG2 = 0x00;
*CHCONFIG2 = 0xC3;
17.8.2.2
Enabling a source without periodic triggering
The following describes how to enable a source without periodic triggering:
1. Determine with which eDMA channel the source will be associated. Remember that only eDMA
channels 0–3 have periodic triggering capability.
2. Clear the ENBL and TRIG bits of the eDMA channel.
3. Ensure that the eDMA channel is properly configured in the eDMA. The eDMA channel may be
enabled at this point.
4. Select the source to be routed to the eDMA channel. Write to the corresponding CHCONFIG
register, ensuring that the ENBL is set and the TRIG bit is cleared.
Example 17-2. Configure source #5 Transmit for use with eDMA Channel 2, without periodic triggering
capability
1. Write 0x00 to CHCONFIG2 (Base Address + 0x02)
2. Configure Channel 2 in the eDMA, including enabling the channel
3. Write 0x85 to CHCONFIG2 (Base Address + 0x02)
The following code example illustrates steps #1 and #3 above:
In File registers.h:
#define DMAMUX_BASE_ADDR
0xFC084000/* Example only ! */
/* Following example assumes char is 8 bits */
volatile unsigned char *CHCONFIG2 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0002);
In File main.c:
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#include "registers.h"
:
:
*CHCONFIG2 = 0x00;
*CHCONFIG2 = 0x85;
17.8.2.3
Disabling a source
A particular eDMA source may be disabled by not writing the corresponding source value into any of the
CHCONFIG registers. Additionally, some module specific configuration may be necessary. Please refer
to the appropriate section for more details.
17.8.2.4
Switching the source of an eDMA channel
The following describes how to switch the source of an eDMA channel:
1. Disable the eDMA channel in the eDMA and reconfigure the channel for the new source.
2. Clear the ENBL and TRIG bits of the eDMA channel.
3. Select the source to be routed to the eDMA channel. Write to the corresponding CHCONFIG
register, ensuring that the ENBL and TRIG bits are set.
Example 17-3. Switch eDMA Channel 8 from source #5 transmit to source #7 transmit
1. In the eDMA configuration registers, disable eDMA channel 8 and reconfigure it to handle the
transfers to peripheral slot 7. This example assumes channel 8 doesn’t have triggering capability.
2. Write 0x00 to CHCONFIG8 (Base Address + 0x08)
3. Write 0x87 to CHCONFIG8 (Base Address + 0x08).
The following code example illustrates steps #2 and #3 above:
In File registers.h:
#define DMAMUX_BASE_ADDR
0xFC084000/* Example only ! */
/* Following example assumes char is 8 bits */
volatile unsigned char *CHCONFIG8 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0008);
In File main.c:
#include "registers.h"
:
:
*CHCONFIG8 = 0x00;
*CHCONFIG8 = 0x87;
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Chapter 18 Interrupt Controller (INTC)
Chapter 18
Interrupt Controller (INTC)
18.1
Introduction
The INTC provides priority-based preemptive scheduling of interrupt service requests (ISRs). This
scheduling scheme is suitable for statically scheduled hard real-time systems. The INTC supports 204
interrupt requests. It is targeted to work with a Power Architecture technology processor and automotive
powertrain applications where the ISRs nest to multiple levels, but it also can be used with other processors
and applications.
For high priority interrupt requests in these target applications, the time from the assertion of the
peripheral’s interrupt request from the peripheral to when the processor is performing useful work to
service the interrupt request needs to be minimized. The INTC supports this goal by providing a unique
vector for each interrupt request source. It also provides 16 priorities so that lower priority ISRs do not
delay the execution of higher priority ISRs. Since each individual application will have different priorities
for each source of interrupt request, the priority of each interrupt request is configurable.
When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC
supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the
priority can be raised temporarily so that all tasks that share the resource cannot preempt each other.
Multiple processors can assert interrupt requests to each other through software configurable interrupt
requests. These same software configurable interrupt requests also can be used to break the work involved
in servicing an interrupt request into a high priority portion and a low priority portion. The high priority
portion is initiated by a peripheral interrupt request, but then the ISR can assert a software configurable
interrupt request to finish the servicing in a lower priority ISR. Therefore these software configurable
interrupt requests can be used instead of the peripheral ISR scheduling a task through the RTOS.
18.2
•
•
•
•
•
Features
Supports 196 peripheral and 8 software-configurable interrupt request sources
Unique 9-bit vector per interrupt source
Each interrupt source can be programmed to one of 16 priorities
Preemption
— Preemptive prioritized interrupt requests to processor
— ISR at a higher priority preempts ISRs or tasks at lower priorities
— Automatic pushing or popping of preempted priority to or from a LIFO
— Ability to modify the ISR or task priority; modifying the priority can be used to implement the
priority ceiling protocol for accessing shared resources.
Low latency – 3 clocks from receipt of interrupt request from peripheral to interrupt request to
processor
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Table 18-1. Interrupt sources available
Interrupt sources (204)
Number available
Software
8
ECSM
1
eDMA
17
Software Watchdog (SWT)
1
STM
4
Flash/SRAM ECC (SEC-DED)
2
Real Time Counter (RTC/API)
2
System Integration Unit Lite (SIUL)
3
WKPU
4
MC_ME
4
MC_RGM
1
FXOSC
1
SXOSC
1
PIT
8
ADC_0
2
ADC_1
2
FlexCAN_0
8
FlexCAN_1
8
FlexCAN_2
8
FlexCAN_3
8
FlexCAN_4
8
FlexCAN_5
8
LINFlex_0
3
LINFlex_1
3
LINFlex_2
3
LINFlex_3
3
LINFlex_4
3
LINFlex_5
3
LINFlex_6
3
LINFlex_7
3
DSPI_0
5
DSPI_1
5
DSPI_2
5
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Table 18-1. Interrupt sources available (continued)
Interrupt sources (204)
18.3
Number available
DSPI_3
5
DSPI_4
5
DSPI_5
5
I2C_0
1
Enhanced Modular I/O Subsystem 0 (eMIOS_0)
16
eMIOS_1
16
Block diagram
Figure 18-1 provides a block diagram of the INTC.
Software
Set/Clear
Interrupt
Registers
n1 x
4-bits
Flag Bits
Peripheral
Interrupt
Requests
8
n
1
Priority
Arbitrator
4
Popped
Priority
4
Highest
Priority
Interrupt
Requests
n1
Request
Selector
Lowest
Vector
Interrupt
Request
n1
End of
Interrupt
Register
Vector
Encoder
Processor 0
Current
Priority
Register
Interrupt
Vector
9
Processor 0
Interrupt
Acknowledge
Register
Highest Priority
Update Interrupt Vector
Current
Priority
4
Hardware
Vector Enable
1
Vector Table
Entry Size 1
New
Priority
4
Pushed
Priority
4
Processor 0
Priority
LIFO
Module
Configuration
Register
Priority
Select
Registers
Interrupt
Vector
9
Interrupt
Request to
Processor
1
Priority
Comparator
1
Interrupt Acknowledge
1
Push/Update/Acknowledge
1
Pop
1
Slave
Interface
for Reads
& Writes
Peripheral
Bus
Memory Mapped Registers
Non-Memory Mapped Logic
Figure 18-1. INTC block diagram
18.4
18.4.1
Modes of operation
Normal mode
In normal mode, the INTC has two handshaking modes with the processor: software vector mode and
hardware vector mode.
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Chapter 18 Interrupt Controller (INTC)
18.4.1.1
Software vector mode
In software vector mode, software, that is the interrupt exception handler, must read a register in the INTC
to obtain the vector associated with the interrupt request to the processor. The INTC will use software
vector mode for a given processor when its associated HVEN bit in INTC_MCR is negated. The hardware
vector enable signal to processor 0 or processor 1 is driven as negated when its associated HVEN bit is
negated. The vector is read from INC_IACKR. Reading the INTC_IACKR negates the interrupt request
to the associated processor. Even if a higher priority interrupt request arrived while waiting for this
interrupt acknowledge, the interrupt request to the processor will negate for at least one clock. The reading
also pushes the PRI value in INTC_CPR onto the associated LIFO and updates PRI in the associated
INTC_CPR with the new priority.
Furthermore, the interrupt vector to the processor is driven as all 0s. The interrupt acknowledge signal
from the associated processor is ignored.
18.4.1.2
Hardware vector mode
In hardware vector mode, the hardware is the interrupt vector signal from the INTC in conjunction with a
processor with the capability use that vector. In hardware vector mode, this hardware causes the first
instruction to be executed in handling the interrupt request to the processor to be specific to that vector.
Therefore the interrupt exception handler is specific to a peripheral or software configurable interrupt
request rather than being common to all of them. The INTC uses hardware vector mode for a given
processor when the associated HVEN bit in the INTC_MCR is asserted. The hardware vector enable signal
to the associated processor is driven as asserted. When the interrupt request to the associated processor
asserts, the interrupt vector signal is updated. The value of that interrupt vector is the unique vector
associated with the preempting peripheral or software configurable interrupt request. The vector value
matches the value of the INTVEC field in the INTC_IACKR field in the INTC_IACKR, depending on
which processor was assigned to handle a given interrupt source.
The processor negates the interrupt request to the processor driven by the INTC by asserting the interrupt
acknowledge signal for one clock. Even if a higher priority interrupt request arrived while waiting for the
interrupt acknowledge, the interrupt request to the processor will negate for at least one clock.
The assertion of the interrupt acknowledge signal for a given processor pushes the associated PRI value in
the associated INTC_CPR register onto the associated LIFO and updates the associated PRI in the
associated INTC_CPR register with the new priority. This pushing of the PRI value onto the associated
LIFO and updating PRI in the associated INTC_CPR does not occur when the associated interrupt
acknowledge signal asserts and INTC_SSCIR0_3–INTC_SSCIR4_7 is written at a time such that the PRI
value in the associated INTC_CPR register would need to be pushed and the previously last pushed PRI
value would need to be popped simultaneously. In this case, PRI in the associated INTC_CPR is updated
with the new priority, and the associated LIFO is neither pushed or popped.
18.4.1.3
Debug mode
The INTC operation in debug mode is identical to its operation in normal mode.
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Chapter 18 Interrupt Controller (INTC)
18.4.1.4
Stop mode
The INTC supports STOP mode. The INTC can have its clock input disabled at any time by the clock
driver on the device. While its clocks are disabled, the INTC registers are not accessible.
The INTC requires clocking in order for a peripheral interrupt request to generate an interrupt request to
the processor. Since the INTC is not clocked in STOP mode, peripheral interrupt requests cannot be used
as a wakeup source, unless the device supports that interrupt request as a wakeup source.
18.5
Memory map and register description
18.5.1
Module memory map
Table 18-2 shows the INTC memory map.
Table 18-2. INTC memory map
Base address: 0xFFF4_8000
Address offset
1
Register
0x0000
INTC Module Configuration Register (INTC_MCR)
0x0004
Reserved
0x0008
INTC Current Priority Register for Processor (INTC_CPR)
0x000C
Reserved
0x0010
INTC Interrupt Acknowledge Register (INTC_IACKR)
0x0014
Reserved
0x0018
INTC End-of-Interrupt Register (INTC_EOIR)
0x001C
Reserved
0x0020–0x0027
INTC Software Set/Clear Interrupt Registers
(INTC_SSCIR0_3–INTC_SSCIR4_7)
0x0028–0x003C
Reserved
0x0040–0x00D0
INTC Priority Select Registers
(INTC_PSR0_3–INTC_PSR232_233)1
Location
on page 312
on page 312
on page 314
on page 315
on page 316
on page 317
The PRI fields are reserved for peripheral interrupt requests whose vectors are labeled Reserved in Figure 18-3.
18.5.2
Register description
With exception of the INTC_SSCIn and INTC_PSRn, all registers are 32 bits in width. Any combination
of accessing the 4 bytes of a register with a single access is supported, provided that the access does not
cross a register boundary. These supported accesses include types and sizes of 8 bits, aligned 16 bits,
misaligned 16 bits to the middle 2 bytes, and aligned 32 bits.
Although INTC_SSCIn and INTC_PSRn are 8 bits wide, they can be accessed with a single 16-bit or
32-bit access, provided that the access does not cross a 32-bit boundary.
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Chapter 18 Interrupt Controller (INTC)
In software vector mode, the side effects of a read of INTC_IACKR are the same regardless of the size of
the read. In either software or hardware vector mode, the size of a write to either
INTC_SSCIR0_3–INTC_SSCIR4_7 or INTC_EOIR does not affect the operation of the write.
18.5.2.1
INTC Module Configuration Register (INTC_MCR)
The module configuration register is used to configure options of the INTC.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
HVEN
Access: User read/write
VTES
Offset: 0x0000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
Reset
R
W
Reset
Figure 18-2. INTC Module Configuration Register (INTC_MCR)
Table 18-3. INTC_MCR field descriptions
Field
Description
VTES
Vector table entry size.
Controls the number of 0s to the right of INTVEC in Section 18.5.2.3, INTC Interrupt Acknowledge
Register (INTC_IACKR). If the contents of INTC_IACKR are used as an address of an entry in a vector
table as in software vector mode, then the number of rightmost 0s will determine the size of each
vector table entry. VTES impacts software vector mode operation but also affects
INTC_IACKR[INTVEC] position in both hardware vector mode and software vector mode.
0 4 bytes
1 8 bytes
HVEN
Hardware vector enable.
Controls whether the INTC is in hardware vector mode or software vector mode. Refer to Section 18.4,
Modes of operation, for the details of the handshaking with the processor in each mode.
0 Software vector mode
1 Hardware vector mode
18.5.2.2
INTC Current Priority Register for Processor (INTC_CPR)
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Offset: 0x0008
0
1
Access: User read/write
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PRI
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
Figure 18-3. INTC Current Priority Register (INTC_CPR)
Table 18-4. INTC_CPR field descriptions
Field
PRI
Description
Priority
PRI is the priority of the currently executing ISR according to the field values defined in Table 18-5.
The INTC_CPR masks any peripheral or software configurable interrupt request set at the same or lower
priority as the current value of the INTC_CPR[PRI] field from generating an interrupt request to the
processor. When the INTC interrupt acknowledge register (INTC_IACKR) is read in software vector
mode or the interrupt acknowledge signal from the processor is asserted in hardware vector mode, the
value of PRI is pushed onto the LIFO, and PRI is updated with the priority of the preempting interrupt
request. When the INTC end-of-interrupt register (INTC_EOIR) is written, the LIFO is popped into the
INTC_CPR’s PRI field.
The masking priority can be raised or lowered by writing to the PRI field, supporting the PCP. Refer to
Section 18.7.5, Priority ceiling protocol.
NOTE
A store to modify the PRI field that closely precedes or follows an access to
a shared resource can result in a non-coherent access to that resource. Refer
to Section 18.7.5.2, Ensuring coherency, for example code to ensure
coherency.
Table 18-5. PRI values
PRI
Meaning
1111
Priority 15—highest priority
1110
Priority 14
1101
Priority 13
1100
Priority 12
1011
Priority 11
1010
Priority 10
1001
Priority 9
1000
Priority 8
0111
Priority 7
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Chapter 18 Interrupt Controller (INTC)
Table 18-5. PRI values (continued)
18.5.2.3
PRI
Meaning
0110
Priority 6
0101
Priority 5
0100
Priority 4
0011
Priority 3
0010
Priority 2
0001
Priority 1
0000
Priority 0—lowest priority
INTC Interrupt Acknowledge Register (INTC_IACKR)
Offset: 0x0010
0
Access: User read/write
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
VTBA[20:5]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
R
INTVEC
VTBA[4:0]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 18-4. INTC Interrupt Acknowledge Register (INTC_IACKR) when INTC_MCR[VTES] = 0
Offset: 0x0010
0
Access: User read/write
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
VTBA[19:4]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
R
INTVEC
VTBA[3:0]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 18-5. INTC Interrupt Acknowledge Register (INTC_IACKR) when INTC_MCR[VTES] = 1
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Table 18-6. INTC_IACKR field descriptions
Field
Description
VTBA
Vector Table Base Address
Can be the base address of a vector table of addresses of ISRs.
INTVEC
Interrupt Vector
It is the vector of the peripheral or software configurable interrupt request that caused the interrupt
request to the processor. When the interrupt request to the processor asserts, the INTVEC is updated,
whether the INTC is in software or hardware vector mode.
The interrupt acknowledge register provides a value that can be used to load the address of an ISR from a
vector table. The vector table can be composed of addresses of the ISRs specific to their respective
interrupt vectors.
In software vector mode, the INTC_IACKR has side effects from reads. Therefore, it must not be
speculatively read while in this mode. The side effects are the same regardless of the size of the read.
Reading the INTC_IACKR does not have side effects in hardware vector mode.
18.5.2.4
INTC End-of-Interrupt Register (INTC_EOIR)
Offset: 0x0018
0
1
Access: Write only
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0
See text
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 18-6. INTC End-of-Interrupt Register (INTC_EOIR)
Writing to the end-of-interrupt register signals the end of the servicing of the interrupt request. When the
INTC_EOIR is written, the priority last pushed on the LIFO is popped into INTC_CPR. An exception to
this behavior is described in Section 18.4.1.2, Hardware vector mode. The values and size of data written
to the INTC_EOIR are ignored. The values and sizes written to this register neither update the
INTC_EOIR contents or affect whether the LIFO pops. For possible future compatibility, write four bytes
of all 0s to the INTC_EOIR.
Reading the INTC_EOIR has no effect on the LIFO.
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18.5.2.5
INTC Software Set/Clear Interrupt Registers
(INTC_SSCIR0_3–INTC_SSCIR4_7)
2
3
4
5
6
0
0
0
0
0
0
0
R
9
10
11
12
13
14
15
0
0
0
0
0
0
SET0
SET1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SET2
SET3
0
0
0
0
0
W
Reset
8
0
W
Reset
7
CLR3
1
CLR0
0
CLR2
R
Access: User read/write
CLR1
Offset: 0x0020
0
0
0
0
0
0
0
0
0
0
0
Figure 18-7. INTC Software Set/Clear Interrupt Register 0–3 (INTC_SSCIR[0:3])
2
3
4
5
6
0
0
0
0
0
0
0
R
9
10
11
12
13
14
15
0
0
0
0
0
0
SET4
SET5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SET6
SET7
0
0
0
0
0
W
Reset
8
0
W
Reset
7
CLR7
1
CLR4
0
CLR6
R
Access: User read/write
CLR5
Offset: 0x0024
0
0
0
0
0
0
0
0
0
0
0
Figure 18-8. INTC Software Set/Clear Interrupt Register 4–7 (INTC_SSCIR[4:7])
Table 18-7. INTC_SSCIR[0:7] field descriptions
Field
Description
SETx
Set Flag Bits
Writing a 1 sets the corresponding CLRx bit. Writing a 0 has no effect. Each SETx always will be read
as a 0.
CLRx
Clear Flag Bits
CLRx is the flag bit. Writing a 1 to CLRx clears it provided that a 1 is not written simultaneously to its
corresponding SETx bit. Writing a 0 to CLRx has no effect.
0 Interrupt request not pending within INTC
1 Interrupt request pending within INTC
The software set/clear interrupt registers support the setting or clearing of software configurable interrupt
request. These registers contain eight independent sets of bits to set and clear a corresponding flag bit by
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Chapter 18 Interrupt Controller (INTC)
software. Excepting being set by software, this flag bit behaves the same as a flag bit set within a
peripheral. This flag bit generates an interrupt request within the INTC like a peripheral interrupt request.
Writing a 1 to SETx will leave SETx unchanged at 0 but sets CLRx. Writing a 0 to SETx has no effect.
CLRx is the flag bit. Writing a 1 to CLRx clears it. Writing a 0 to CLRx has no effect. If a 1 is written
simultaneously to a pair of SETx and CLRx bits, CLRx will be asserted, regardless of whether CLRx was
asserted before the write.
18.5.2.6
INTC Priority Select Registers (INTC_PSR0_3–INTC_PSR232_233)
Offset: 0x0040
R
Access: User read/write
0
1
2
3
4
5
6
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
0
0
0
0
0
0
0
0
7
8
9
10
11
0
0
0
0
0
0
0
0
0
0
23
24
25
26
27
28
0
0
0
0
0
0
0
0
PRI0
12
13
14
15
0
0
0
29
30
31
0
0
PRI1
W
Reset
R
PRI2
PRI3
W
Reset
0
0
0
0
0
0
Figure 18-9. INTC Priority Select Register 0–3 (INTC_PSR[0:3])
Offset: 0x0128
R
Access: User read/write
0
1
2
3
0
0
0
0
4
5
6
7
8
9
10
11
0
0
0
0
12
PRI232
13
14
15
PRI233
W
Reset
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Figure 18-10. INTC Priority Select Register 232–233 (INTC_PSR[232:233])
Table 18-8. INTC_PSR0_3–INTC_PSR232_233 field descriptions
Field
PRI
Description
Priority Select
PRIx selects the priority for interrupt requests. See Section 18.6, Functional description.
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Chapter 18 Interrupt Controller (INTC)
Table 18-9. INTC Priority Select Register address offsets
INTC_PSRx_x
Offset address
INTC_PSRx_x
Offset address
INTC_PSR0_3
0x0040
INTC_PSR120_123
0x00B8
INTC_PSR4_7
0x0044
INTC_PSR124_127
0x00BC
INTC_PSR8_11
0x0048
INTC_PSR128_131
0x00C0
INTC_PSR12_15
0x004C
INTC_PSR132_135
0x00C4
INTC_PSR16_19
0x0050
INTC_PSR136_139
0x00C8
INTC_PSR20_23
0x0054
INTC_PSR140_143
0x00CC
INTC_PSR24_27
0x0058
INTC_PSR144_147
0x00D0
INTC_PSR28_31
0x005C
INTC_PSR148_151
0x00D4
INTC_PSR32_35
0x0060
INTC_PSR152_155
0x00D8
INTC_PSR36_39
0x0064
INTC_PSR156_159
0x00DC
INTC_PSR40_43
0x0068
INTC_PSR160_163
0x00E0
INTC_PSR44_47
0x006C
INTC_PSR164_167
0x00E4
INTC_PSR48_51
0x0070
INTC_PSR168_171
0x00E8
INTC_PSR52_55
0x0074
INTC_PSR172_175
0x00EC
INTC_PSR56_59
0x0078
INTC_PSR176_179
0x00F0
INTC_PSR60_63
0x007C
INTC_PSR180_183
0x00F4
INTC_PSR64_67
0x0080
INTC_PSR184_187
0x00F8
INTC_PSR68_71
0x0084
INTC_PSR188_191
0x00FC
INTC_PSR72_75
0x0088
INTC_PSR192_195
0x0100
INTC_PSR76_79
0x008C
INTC_PSR196_199
0x0104
INTC_PSR80_83
0x0090
INTC_PSR200_203
0x0108
INTC_PSR84_87
0x0094
INTC_PSR204_207
0x010C
INTC_PSR88_91
0x0098
INTC_PSR208_211
0x0110
INTC_PSR92_95
0x009C
INTC_PSR212_215
0x0114
INTC_PSR96_99
0x00A0
INTC_PSR216_219
0x0118
INTC_PSR100_103
0x00A4
INTC_PSR220_223
0x011C
INTC_PSR104_107
0x00A8
INTC_PSR224_227
0x0120
INTC_PSR108_111
0x00AC
INTC_PSR228_231
0x0124
INTC_PSR112_115
0x00B0
INTC_PSR232_233
0x0128
INTC_PSR116_119
0x00B4
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Chapter 18 Interrupt Controller (INTC)
18.6
Functional description
The functional description involves the areas of interrupt request sources, priority management, and
handshaking with the processor.
NOTE
The INTC has no spurious vector support. Therefore, if an asserted
peripheral or software settable interrupt request, whose PRIn value in
INTC_PSR0–INTC_PSR233 is higher than the PRI value in INTC_CPR,
negates before the interrupt request to the processor for that peripheral or
software settable interrupt request is acknowledged, the interrupt request to
the processor still can assert or will remain asserted for that peripheral or
software settable interrupt request. In this case, the interrupt vector will
correspond to that peripheral or software settable interrupt request. Also, the
PRI value in the INTC_CPR will be updated with the corresponding PRIn
value in INTC_PSRn. Furthermore, clearing the peripheral interrupt
request’s enable bit in the peripheral or, alternatively, setting its mask bit has
the same consequences as clearing its flag bit. Setting its enable bit or
clearing its mask bit while its flag bit is asserted has the same effect on the
INTC as an interrupt event setting the flag bit.
Table 18-10. Interrupt vector table
IRQ #
Offset
Size
(bytes)
Interrupt
Module
Section A (Core Section)
—
0x0000
16
Critical Input
(INTC software vector mode) / NMI
Core
—
0x0010
16
Machine check / NMI
Core
—
0x0020
16
Data Storage
Core
—
0x0030
16
Instruction Storage
Core
—
0x0040
16
External Input
(INTC software vector mode)
Core
—
0x0050
16
Alignment
Core
—
0x0060
16
Program
Core
—
0x0070
16
Reserved
Core
—
0x0080
16
System call
Core
—
0x0090
96
Unused
Core
—
0x00F0
16
Debug
Core
—
0x0100
1792
Unused
Core
Section B (On-Platform Peripherals)
0
0x0800
4
Software configurable flag 0
Software
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Chapter 18 Interrupt Controller (INTC)
Table 18-10. Interrupt vector table (continued)
IRQ #
Offset
Size
(bytes)
1
0x0804
4
Software configurable flag 1
Software
2
0x0808
4
Software configurable flag 2
Software
3
0x080C
4
Software configurable flag 3
Software
4
0x0810
4
Software configurable flag 4
Software
5
0x0814
4
Software configurable flag 5
Software
6
0x0818
4
Software configurable flag 6
Software
7
0x081C
4
Software configurable flag 7
Software
8
0x0820
4
9
0x0824
4
Platform Flash Bank 0 Abort |
Platform Flash Bank 0 Stall |
Platform Flash Bank 1 Abort |
Platform Flash Bank 1 Stall |
ECSM
10
0x0828
4
Combined Error
eDMA
11
0x082C
4
Channel 0
eDMA
12
0x0830
4
Channel 1
eDMA
13
0x0834
4
Channel 2
eDMA
14
0x0838
4
Channel 3
eDMA
15
0x083C
4
Channel 4
eDMA
16
0x0840
4
Channel 5
eDMA
17
0x0844
4
Channel 6
eDMA
18
0x0848
4
Channel 7
eDMA
19
0x084C
4
Channel 8
eDMA
20
0x0850
4
Channel 9
eDMA
21
0x0854
4
Channel 10
eDMA
22
0x0858
4
Channel 11
eDMA
23
0x085C
4
Channel 12
eDMA
24
0x0860
4
Channel 13
eDMA
25
0x0864
4
Channel 14
eDMA
26
0x0868
4
Channel 15
eDMA
27
0x086C
4
28
0x0870
4
29
0x0874
4
30
0x0878
4
Interrupt
Module
Reserved
Reserved
Timeout
SWT
Reserved
Match on channel 0
STM
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Chapter 18 Interrupt Controller (INTC)
Table 18-10. Interrupt vector table (continued)
IRQ #
Offset
Size
(bytes)
31
0x087C
4
Match on channel 1
STM
32
0x0880
4
Match on channel 2
STM
33
0x0884
4
Match on channel 3
STM
34
0x0888
4
35
0x088C
4
ECC_DBD_PlatformFlash |
ECC_DBD_PlatformRAM
Platform ECC Double Bit Detection
36
0x0890
4
ECC_SBC_PlatformFlash |
ECC_SBC_PlatformRAM
Platform ECC Single Bit Correction
37
0x0894
4
Interrupt
Module
Reserved
Reserved
Section C
38
0x0898
4
RTC
RTC/API
39
0x089C
4
API
RTC/API
40
0x08A0
4
41
0x08A4
4
SIU External IRQ_0
SIUL
42
0x08A8
4
SIU External IRQ_1
SIUL
43
0x08AC
4
SIU External IRQ_2
SIUL
44
0x08B0
4
Reserved
45
0x08B4
4
Reserved
46
0x08B8
4
WakeUp_IRQ_0
WKPU
47
0x08BC
4
WakeUp_IRQ_1
WKPU
48
0x08C0
4
WakeUp_IRQ_2
WKPU
49
0x08C4
4
WakeUp_IRQ_3
WKPU
50
0x08C8
4
51
0x08CC
4
Safe Mode Interrupt
MC_ME
52
0x08D0
4
Mode Transition Interrupt
MC_ME
53
0x08D4
4
Invalid Mode Interrupt
MC_ME
54
0x08D8
4
Invalid Mode Config
MC_ME
55
0x08DC
4
56
0x08E0
4
Functional and destructive reset alternate MC_RGM
event interrupt (ipi_int)
57
0x08E4
4
FXOSC counter expired (ipi_int_osc)
58
0x08E8
4
59
0x08EC
4
Reserved
Reserved
Reserved
FXOSC
Reserved
PITimer Channel 0
PIT
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Chapter 18 Interrupt Controller (INTC)
Table 18-10. Interrupt vector table (continued)
IRQ #
Offset
Size
(bytes)
60
0x08F0
4
PITimer Channel 1
PIT
61
0x08F4
4
PITimer Channel 2
PIT
62
0x08F8
4
ADC_EOC
ADC_0
64
0x0900
4
ADC_WD
ADC_0
63
0x08FC
4
65
0x0904
4
FlexCAN_ESR[ERR_INT]
FlexCAN_0
66
0x0908
4
FlexCAN_ESR_BOFF |
FlexCAN_Transmit_Warning |
FlexCAN_Receive_Warning
FlexCAN_0
67
0x090C
4
68
0x0910
4
FlexCAN_BUF_00_03
FlexCAN_0
69
0x0914
4
FlexCAN_BUF_04_07
FlexCAN_0
70
0x0918
4
FlexCAN_BUF_08_11
FlexCAN_0
71
0x091C
4
FlexCAN_BUF_12_15
FlexCAN_0
72
0x0920
4
FlexCAN_BUF_16_31
FlexCAN_0
73
0x0924
4
FlexCAN_BUF_32_63
FlexCAN_0
74
0x0928
4
DSPI_SR[TFUF]
DSPI_SR[RFOF]
DSPI_0
75
0x092C
4
DSPI_SR[EOQF]
DSPI_0
76
0x0930
4
DSPI_SR[TFFF]
DSPI_0
77
0x0934
4
DSPI_SR[TCF]
DSPI_0
78
0x0938
4
DSPI_SR[RFDF]
DSPI_0
79
0x093C
4
LINFlex_RXI
LINFlex_0
80
0x0940
4
LINFlex_TXI
LINFlex_0
81
0x0944
4
LINFlex_ERR
LINFlex_0
82
0x0948
4
ADC_EOC
ADC_1
83
0x094C
4
84
0x0950
4
ADC_WD
ADC_1
85
0x0954
4
FlexCAN_ESR[ERR_INT]
FlexCAN_1
86
0x0958
4
FlexCAN_ESR_BOFF |
FlexCAN_Transmit_Warning |
FlexCAN_Receive_Warning
FlexCAN_1
87
0x095C
4
88
0x0960
4
Interrupt
Module
Reserved
Reserved
Reserved
Reserved
FlexCAN_BUF_00_03
FlexCAN_1
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Chapter 18 Interrupt Controller (INTC)
Table 18-10. Interrupt vector table (continued)
IRQ #
Offset
Size
(bytes)
89
0x0964
4
FlexCAN_BUF_04_07
FlexCAN_1
90
0x0968
4
FlexCAN_BUF_08_11
FlexCAN_1
91
0x096C
4
FlexCAN_BUF_12_15
FlexCAN_1
92
0x0970
4
FlexCAN_BUF_16_31
FlexCAN_1
93
0x0974
4
FlexCAN_BUF_32_63
FlexCAN_1
94
0x0978
4
DSPI_SR[TFUF]
DSPI_SR[RFOF]
DSPI_1
95
0x097C
4
DSPI_SR[EOQF]
DSPI_1
96
0x0980
4
DSPI_SR[TFFF]
DSPI_1
97
0x0984
4
DSPI_SR[TCF]
DSPI_1
98
0x0988
4
DSPI_SR[RFDF]
DSPI_1
99
0x098C
4
LINFlex_RXI
LINFlex_1
100
0x0990
4
LINFlex_TXI
LINFlex_1
101
0x0994
4
LINFlex_ERR
LINFlex_1
102
0x0998
4
Reserved
103
0x099C
4
Reserved
104
0x09A0
4
Reserved
105
0x09A4
4
FlexCAN_[ERR_INT]
FlexCAN_2
106
0x09A8
4
FlexCAN_ESR_BOFF |
FlexCAN_Transmit_Warning |
FlexCAN_Receive_Warning
FlexCAN_2
107
0x09AC
4
108
0x09B0
4
FlexCAN_BUF_00_03
FlexCAN_2
109
0x09B4
4
FlexCAN_BUF_04_07
FlexCAN_2
110
0x09B8
4
FlexCAN_BUF_08_11
FlexCAN_2
111
0x09BC
4
FlexCAN_BUF_12_15
FlexCAN_2
112
0x09C0
4
FlexCAN_BUF_16_31
FlexCAN_2
113
0x09C4
4
FlexCAN_BUF_32_63
FlexCAN_2
114
0x09C8
4
DSPI_SR[TFUF]
DSPI_SR[RFOF]
DSPI_2
115
0x09CC
4
DSPI_SR[EOQF]
DSPI_2
116
0x09D0
4
DSPI_SR[TFFF]
DSPI_2
117
0x09D4
4
DSPI_SR[TCF]
DSPI_2
118
0x09D8
4
DSPI_SR[RFDF]
DSPI_2
Interrupt
Module
Reserved
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Chapter 18 Interrupt Controller (INTC)
Table 18-10. Interrupt vector table (continued)
IRQ #
Offset
Size
(bytes)
119
0x09DC
4
LINFlex_RXI
LINFlex_2
120
0x09E0
4
LINFlex_TXI
LINFlex_2
121
0x09E4
4
LINFlex_ERR
LINFlex_2
122
0x09E8
4
LINFlex_RXI
LINFlex_3
123
0x09EC
4
LINFlex_TXI
LINFlex_3
124
0x09F0
4
LINFlex_ERR
LINFlex_3
125
0x09F4
4
I2C_SR[IBAL]
I2C_SR[TCF]
I2C_SR[IAAS]
I2C_0
126
0x09F8
4
127
0x09FC
4
PITimer Channel 3
PIT
128
0x0A00
4
PITimer Channel 4
PIT
129
0x0A04
4
PITimer Channel 5
PIT
130
0x0A08
4
PITimer Channel 6
PIT
131
0x0A0C
4
PITimer Channel 7
PIT
132
0x0A10
4
Reserved
133
0x0A14
4
Reserved
134
0x0A18
4
Reserved
135
0x0A1C
4
Reserved
136
0x0A20
4
Reserved
137
0x0A24
4
Reserved
138
0x0A28
4
Reserved
139
0x0A2C
4
Reserved
140
0x0A30
4
Reserved
141
0x0A34
4
EMIOS_GFR[F0,F1]
eMIOS_0
142
0x0A38
4
EMIOS_GFR[F2,F3]
eMIOS_0
143
0x0A3C
4
EMIOS_GFR[F4,F5]
eMIOS_0
144
0x0A40
4
EMIOS_GFR[F6,F7]
eMIOS_0
145
0x0A44
4
EMIOS_GFR[F8,F9]
eMIOS_0
146
0x0A48
4
EMIOS_GFR[F10,F11]
eMIOS_0
147
0x0A4C
4
EMIOS_GFR[F12,F13]
eMIOS_0
148
0x0A50
4
EMIOS_GFR[F14,F15]
eMIOS_0
149
0x0A54
4
EMIOS_GFR[F16,F17]
eMIOS_0
Interrupt
Module
Reserved
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Chapter 18 Interrupt Controller (INTC)
Table 18-10. Interrupt vector table (continued)
IRQ #
Offset
Size
(bytes)
150
0x0A58
4
EMIOS_GFR[F18,F19]
eMIOS_0
151
0x0A5C
4
EMIOS_GFR[F20,F21]
eMIOS_0
152
0x0A60
4
EMIOS_GFR[F22,F23]
eMIOS_0
153
0x0A64
4
EMIOS_GFR[F24,F25]
eMIOS_0
154
0x0A68
4
EMIOS_GFR[F26,F27]
eMIOS_0
155
0x0A6C
4
EMIOS_GFR[F28,F29]
eMIOS_0
156
0x0A70
4
EMIOS_GFR[F30,F31]
eMIOS_0
Interrupt
Module
Section D (Device specific vectors)
157
0x0A74
4
EMIOS_GFR[F0,F1]
eMIOS_1
158
0x0A78
4
EMIOS_GFR[F2,F3]
eMIOS_1
159
0x0A7C
4
EMIOS_GFR[F4,F5]
eMIOS_1
160
0x0A80
4
EMIOS_GFR[F6,F7]
eMIOS_1
161
0x0A84
4
EMIOS_GFR[F8,F9]
eMIOS_1
162
0x0A88
4
EMIOS_GFR[F10,F11]
eMIOS_1
163
0x0A8C
4
EMIOS_GFR[F12,F13]
eMIOS_1
164
0x0A90
4
EMIOS_GFR[F14,F15]
eMIOS_1
165
0x0A94
4
EMIOS_GFR[F16,F17]
eMIOS_1
166
0x0A98
4
EMIOS_GFR[F18,F19]
eMIOS_1
167
0x0A9C
4
EMIOS_GFR[F20,F21]
eMIOS_1
168
0x0AA0
4
EMIOS_GFR[F22,F23]
eMIOS_1
169
0x0AA4
4
EMIOS_GFR[F24,F25]
eMIOS_1
170
0x0AA8
4
EMIOS_GFR[F26,F27]
eMIOS_1
171
0x0AAC
4
EMIOS_GFR[F28,F29]
eMIOS_1
172
0x0AB0
4
EMIOS_GFR[F30,F31]
eMIOS_1
173
0x0AB4
4
FlexCAN_ESR
FlexCAN_3
174
0x0AB8
4
FlexCAN_ESR_BOFF |
FlexCAN_Transmit_Warning |
FlexCAN_Receive_Warning
FlexCAN_3
175
0x0ABC
4
176
0x0AC0
4
FlexCAN_BUF_0_3
FlexCAN_3
177
0x0AC4
4
FlexCAN_BUF_4_7
FlexCAN_3
178
0x0AC8
4
FlexCAN_BUF_8_11
FlexCAN_3
179
0x0ACC
4
FlexCAN_BUF_12_15
FlexCAN_3
Reserved
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Chapter 18 Interrupt Controller (INTC)
Table 18-10. Interrupt vector table (continued)
IRQ #
Offset
Size
(bytes)
180
0x0AD0
4
FlexCAN_BUF_16_31
FlexCAN_3
181
0x0AD4
4
FlexCAN_BUF_32_63
FlexCAN_3
182
0x0AD8
4
DSPI_SR[TFUF]
DSPI_SR[RFOF]
DSPI_3
183
0x0ADC
4
DSPI_SR[EOQF]
DSPI_3
184
0x0AE0
4
DSPI_SR[TFFF]
DSPI_3
185
0x0AE4
4
DSPI_SR[TCF]
DSPI_3
186
0x0AE8
4
DSPI_SR[RFDF]
DSPI_3
187
0x0AEC
4
LINFlex_RXI
LINFlex_4
188
0x0AF0
4
LINFlex_TXI
LINFlex_4
189
0x0AF4
4
LINFlex_ERR
LINFlex_4
190
0x0AF8
4
FlexCAN_ESR
FlexCAN_4
191
0x0AFC
4
FlexCAN_ESR_BOFF |
FlexCAN_Transmit_Warning |
FlexCAN_Receive_Warning
FlexCAN_4
192
0x0B00
4
193
0x0B04
4
FlexCAN_BUF_0_3
FlexCAN_4
194
0x0B08
4
FlexCAN_BUF_4_7
FlexCAN_4
195
0x0B0C
4
FlexCAN_BUF_8_11
FlexCAN_4
196
0x0B10
4
FlexCAN_BUF_12_15
FlexCAN_4
197
0x0B14
4
FlexCAN_BUF_16_31
FlexCAN_4
198
0x0B18
4
FlexCAN_BUF_32_63
FlexCAN_4
199
0x0B1C
4
LINFlex_RXI
LINFlex_5
200
0x0B20
4
LINFlex_TXI
LINFlex_5
201
0x0B24
4
LINFlex_ERR
LINFlex_5
202
0x0B28
4
FlexCAN_ESR
FlexCAN_5
203
0x0B2C
4
FlexCAN_ESR_BOFF |
FlexCAN_Transmit_Warning |
FlexCAN_Receive_Warning
FlexCAN_5
204
0x0B30
4
205
0x0B34
4
FlexCAN_BUF_0_3
FlexCAN_5
206
0x0B38
4
FlexCAN_BUF_4_7
FlexCAN_5
207
0x0B3C
4
FlexCAN_BUF_8_11
FlexCAN_5
208
0x0B40
4
FlexCAN_BUF_12_15
FlexCAN_5
Interrupt
Module
Reserved
Reserved
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Chapter 18 Interrupt Controller (INTC)
Table 18-10. Interrupt vector table (continued)
IRQ #
Offset
Size
(bytes)
209
0x0B44
4
FlexCAN_BUF_16_31
FlexCAN_5
210
0x0B48
4
FlexCAN_BUF_32_63
FlexCAN_5
211
0x0B4C
4
DSPI_SR[TFUF]
DSPI_SR[RFOF]
DSPI_4
212
0x0B50
4
DSPI_SR[EOQF]
DSPI_4
213
0x0B54
4
DSPI_SR[TFFF]
DSPI_4
214
0x0B58
4
DSPI_SR[TCF]
DSPI_4
215
0x0B5C
4
DSPI_SR[RFDF]
DSPI_4
216
0x0B60
4
LINFlex_RXI
LINFlex_6
217
0x0B64
4
LINFlex_TXI
LINFlex_6
218
0x0B68
4
LINFlex_ERR
LINFlex_6
219
0x0B6C
4
DSPI_SR[TFUF]
DSPI_SR[RFOF]
DSPI_5
220
0x0B70
4
DSPI_SR[EOQF]
DSPI_5
221
0x0B74
4
DSPI_SR[TFFF]
DSPI_5
222
0x0B78
4
DSPI_SR[TCF]
DSPI_5
223
0x0B7C
4
DSPI_SR[RFDF]
DSPI_5
224
0x0B80
4
LINFlex_RXI
LINFlex_7
225
0x0B84
4
LINFlex_TXI
LINFlex_7
226
0x0B88
4
LINFlex_ERR
LINFlex_7
227
0x0B8C
4
Reserved
228
0x0B90
4
Reserved
229
0x0B94
4
Reserved
230
0x0B98
4
Reserved
231
0x0B9C
4
Reserved
232
0x0BA0
4
Reserved
233
0x0BA4
4
18.6.1
Interrupt
32KXOSC counter expired
Module
SXOSC
Interrupt request sources
The INTC has two types of interrupt requests, peripheral and software configurable. These interrupt
requests can assert on any clock cycle.
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Chapter 18 Interrupt Controller (INTC)
18.6.1.1
Peripheral interrupt requests
An interrupt event in a peripheral’s hardware sets a flag bit that resides in the peripheral. The interrupt
request from the peripheral is driven by that flag bit.
The time from when the peripheral starts to drive its peripheral interrupt request to the INTC to the time
that the INTC starts to drive the interrupt request to the processor is three clocks.
External interrupts are handled by the SIU (see Section 20.6.3, External interrupts).
18.6.1.2
Software configurable interrupt requests
An interrupt request is triggered by software by writing a 1 to a SETx bit in
INTC_SSCIR0_3–INTC_SSCIR4_7. This write sets the corresponding flag bit, CLRx, resulting in the
interrupt request. The interrupt request is cleared by writing a 1 to the CLRx bit.
The time from the write to the SETx bit to the time that the INTC starts to drive the interrupt request to the
processor is four clocks.
18.6.1.3
Unique vector for each interrupt request source
Each peripheral and software configurable interrupt request is assigned a hardwired unique 9-bit vector.
Software configurable interrupts 0–7 are assigned vectors 0–7 respectively. The peripheral interrupt
requests are assigned vectors 8 to as high as needed to include all the peripheral interrupt requests. The
peripheral interrupt request input ports at the boundary of the INTC block are assigned specific hardwired
vectors within the INTC (see Table 18-1).
18.6.2
Priority management
The asserted interrupt requests are compared to each other based on their PRIx values set in the INTC
Priority Select Registers (INTC_PSR0_3–INTC_PSR232_233). The result is compared to PRI in the
associated INTC_CPR. The results of those comparisons manage the priority of the ISR executed by the
associated processor. The associated LIFO also assists in managing that priority.
18.6.2.1
Current priority and preemption
The priority arbitrator, selector, encoder, and comparator subblocks shown in Figure 18-1 compare the
priority of the asserted interrupt requests to the current priority. If the priority of any asserted peripheral or
software configurable interrupt request is higher than the current priority for a given processor, then the
interrupt request to the processor is asserted. Also, a unique vector for the preempting peripheral or
software configurable interrupt request is generated for INTC interrupt acknowledge register
(INTC_IACKR), and if in hardware vector mode, for the interrupt vector provided to the processor.
18.6.2.1.1
Priority arbitrator subblock
The priority arbitrator subblock for each processor compares all the priorities of all of the asserted interrupt
requests assigned to that processor, both peripheral and software configurable. The output of the priority
arbitrator subblock is the highest of those priorities assigned to a given processor. Also, any interrupt
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Chapter 18 Interrupt Controller (INTC)
requests that have this highest priority are output as asserted interrupt requests to the associated request
selector subblock.
18.6.2.1.2
Request selector subblock
If only one interrupt request from the associated priority arbitrator subblock is asserted, then it is passed
as asserted to the associated vector encoder subblock. If multiple interrupt requests from the associated
priority arbitrator subblock are asserted, the only the one with the lowest vector is passed as asserted to the
associated vector encoder subblock. The lower vector is chosen regardless of the time order of the
assertions of the peripheral or software configurable interrupt requests.
18.6.2.1.3
Vector encoder subblock
The vector encoder subblock generates the unique 9-bit vector for the asserted interrupt request from the
request selector subblock for the associated processor.
18.6.2.1.4
Priority Comparator subblock
The priority comparator subblock compares the highest priority output from the priority arbitrator
subblock with PRI in INTC_CPR. If the priority comparator subblock detects that this highest priority is
higher than the current priority, then it asserts the interrupt request to the associated processor. This
interrupt request to the processor asserts whether this highest priority is raised above the value of PRI in
INTC_CPR or the PRI value in INTC_CPR is lowered below this highest priority. This highest priority
then becomes the new priority, which will be written to PRI in INTC_CPR when the interrupt request to
the processor is acknowledged. Interrupt requests whose PRIn in INTC_PSRn are zero will not cause a
preemption because their PRIn will not be higher than PRI in INTC_CPR.
18.6.2.2
Last-In First-Out (LIFO)
The LIFO stores the preempted PRI values from the INTC_CPR. Therefore, because these priorities are
stacked within the INTC, if interrupts need to be enabled during the ISR, at the beginning of the interrupt
exception handler the PRI value in the INTC_CPR does not need to be loaded from the INTC_CPR and
stored onto the context stack. Likewise at the end of the interrupt exception handler, the priority does not
need to be loaded from the context stack and stored into the INTC_CPR.
The PRI value in the INTC_CPR is pushed onto the LIFO when the INTC_IACKR is read in software
vector mode or the interrupt acknowledge signal from the processor is asserted in hardware vector mode.
The priority is popped into PRI in the INTC_CPR whenever the INTC_EOIR is written.
Although the INTC supports 16 priorities, an ISR executing with PRI in the INTC_CPR equal to 15 will
not be preempted. Therefore, the LIFO supports the stacking of 15 priorities. However, the LIFO is only
14 entries deep. An entry for a priority of 0 is not needed because of how pushing onto a full LIFO and
popping an empty LIFO are treated. If the LIFO is pushed 15 or more times than it is popped, the priorities
first pushed are overwritten. A priority of 0 would be an overwritten priority. However, the LIFO will pop
0s if it is popped more times than it is pushed. Therefore, although a priority of 0 was overwritten, it is
regenerated with the popping of an empty LIFO.
The LIFO is not memory mapped.
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18.6.3
18.6.3.1
Handshaking with processor
Software vector mode handshaking
This section describes handshaking in software vector mode.
18.6.3.1.1
Acknowledging interrupt request to processor
A timing diagram of the interrupt request and acknowledge handshaking in software vector mode, along
with the handshaking near the end of the interrupt exception handler, is shown in Figure 18-11. The INTC
examines the peripheral and software configurable interrupt requests. When it finds an asserted peripheral
or software configurable interrupt request with a higher priority than PRI in the associated INTC_CPR, it
asserts the interrupt request to the processor. The INTVEC field in the associated INTC_IACKR is updated
with the preempting interrupt request’s vector when the interrupt request to the processor is asserted. The
INTVEC field retains that value until the next time the interrupt request to the processor is asserted. The
rest of the handshaking is described in Section 18.4.1.1, Software vector mode.
18.6.3.1.2
End of interrupt exception handler
Before the interrupt exception handling completes, INTC end-of-interrupt register (INTC_EOIR) must be
written.When written, the associated LIFO is popped so the preempted priority is restored into PRI of the
INTC_CPR. Before it is written, the peripheral or software configurable flag bit must be cleared so that
the peripheral or software configurable interrupt request is negated.
NOTE
To ensure proper operation across all Power Architecture MCUs, execute an
MBAR or MSYNC instruction between the access to clear the flag bit and the
write to the INTC_EOIR.
When returning from the preemption, the INTC does not search for the peripheral or software settable
interrupt request whose ISR was preempted. Depending on how much the ISR progressed, that interrupt
request may no longer even be asserted. When PRI in INTC_CPR is lowered to the priority of the
preempted ISR, the interrupt request for the preempted ISR or any other asserted peripheral or software
settable interrupt request at or below that priority will not cause a preemption. Instead, after the restoration
of the preempted context, the processor will return to the instruction address that it was to next execute
before it was preempted. This next instruction is part of the preempted ISR or the interrupt exception
handler’s prolog or epilog.
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Clock
Interrupt request to processor
Hardware vector enable
Interrupt vector
0
Interrupt acknowledge
Read INTC_IACKR
Write INTC_EOIR
INTVEC in INTC_IACKR
0
PRI in INTC_CPR
0
108
1
0
Peripheral interrupt request 100
Figure 18-11. Software vector mode handshaking timing diagram
18.6.3.2
Hardware vector mode handshaking
A timing diagram of the interrupt request and acknowledge handshaking in hardware vector mode, along
with the handshaking near the end of the interrupt exception handler, is shown in Figure 18-12. As in
software vector mode, the INTC examines the peripheral and software settable interrupt requests, and
when it finds an asserted one with a higher priority than PRI in INTC_CPR, it asserts the interrupt request
to the processor. The INTVEC field in the INTC_IACKR is updated with the preempting peripheral or
software settable interrupt request’s vector when the interrupt request to the processor is asserted. The
INTVEC field retains that value until the next time the interrupt request to the processor is asserted. In
addition, the value of the interrupt vector to the processor matches the value of the INTVEC field in the
INTC_IACKR. The rest of the handshaking is described in Section 18.7.2.2, Hardware vector mode.
The handshaking near the end of the interrupt exception handler, that is the writing to the INTC_EOIR, is
the same as in software vector mode. Refer to Section 18.6.3.1.2, End of interrupt exception handler.
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Clock
Interrupt request to processor
Hardware vector enable
Interrupt vector
0
108
INTVEC in INTC_IACKR
0
108
PRI in INTC_CPR
0
Interrupt acknowledge
Read INTC_IACKR
Write INTC_EOIR
1
0
Peripheral interrupt request 100
Figure 18-12. Hardware vector mode handshaking timing diagram
18.7
Initialization/application information
18.7.1
Initialization flow
After exiting reset, all of the PRIn fields in INTC priority select registers (INTC_PSR0–INTC_PSR233)
will be zero, and PRI in INTC current priority register (INTC_CPR) will be 15. These reset values will
prevent the INTC from asserting the interrupt request to the processor. The enable or mask bits in the
peripherals are reset such that the peripheral interrupt requests are negated. An initialization sequence for
allowing the peripheral and software settable interrupt requests to cause an interrupt request to the
processor is:
interrupt_request_initialization:
configure VTES and HVEN in INTC_MCR
configure VTBA in INTC_IACKR
raise the PRIn fields in INTC_PSRn
set the enable bits or clear the mask bits for the peripheral interrupt requests
lower PRI in INTC_CPR to zero
enable processor recognition of interrupts
18.7.2
Interrupt exception handler
These example interrupt exception handlers use Power Architecture assembly code.
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18.7.2.1
Software vector mode
interrupt_exception_handler:
code to create stack frame, save working register, and save SRR0 and SRR1
lis
r3,[email protected]
# form adjusted upper half of INTC_IACKR address
lwz
r3,[email protected](r3)
# load INTC_IACKR, which clears request to processor
lwz
r3,0x0(r3)
# load address of ISR from vector table
wrteei 1
# enable processor recognition of interrupts
code to save rest of context required by e500 EABI
mtlr
blrl
r3
# move INTC_IACKR contents into link register
# branch to ISR; link register updated with epilog
# address
epilog:
code to restore most of context required by e500 EABI
# Popping the LIFO after the restoration of most of the context and the disabling of processor
# recognition of interrupts eases the calculation of the maximum stack depth at the cost of
# postponing the servicing of the next interrupt request.
mbar
# ensure store to clear flag bit has completed
lis
r3,[email protected]
# form adjusted upper half of INTC_EOIR address
li
r4,0x0
# form 0 to write to INTC_EOIR
wrteei
0
# disable processor recognition of interrupts
stw
r4,[email protected](r3)
# store to INTC_EOIR, informing INTC to lower priority
code to restore SRR0 and SRR1, restore working registers, and delete stack frame
rfi
vector_table_base_address:
address of ISR for interrupt
address of ISR for interrupt
.
.
.
address of ISR for interrupt
address of ISR for interrupt
with vector 0
with vector 1
with vector 510
with vector 511
ISRx:
code to service the interrupt event
code to clear flag bit which drives interrupt request to INTC
blr # return to epilog
18.7.2.2
Hardware vector mode
This interrupt exception handler is useful with processor and system bus implementations that support a
hardware vector. This example assumes that each interrupt_exception_handlerx only has space for four
instructions, and therefore a branch to interrupt_exception_handler_continuedx is needed.
interrupt_exception_handlerx:
b interrupt_exception_handler_continuedx# 4 instructions available, branch to continue
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interrupt_exception_handler_continuedx:
code to create stack frame, save working register, and save SRR0 and SRR1
wrteei
1
# enable processor recognition of interrupts
code to save rest of context required by e500 EABI
bl
ISRx
# branch to ISR for interrupt with vector x
epilog:
code to restore most of context required by e500 EABI
# Popping the LIFO after the restoration of most of the context and the disabling of processor
# recognition of interrupts eases the calculation of the maximum stack depth at the cost of
# postponing the servicing of the next interrupt request.
mbar
# ensure store to clear flag bit has completed
lis
r3,[email protected]
# form adjusted upper half of INTC_EOIR address
li
r4,0x0
# form 0 to write to INTC_EOIR
wrteei
0
# disable processor recognition of interrupts
stw
r4,[email protected](r3) # store to INTC_EOIR, informing INTC to lower priority
code to restore SRR0 and SRR1, restore working registers, and delete stack frame
rfi
ISRx:
code to service the interrupt event
code to clear flag bit which drives interrupt request to INTC
blr
# branch to epilog
18.7.3
ISR, RTOS, and task hierarchy
The RTOS and all of the tasks under its control typically execute with PRI in INTC current priority register
(INTC_CPR) having a value of 0. The RTOS will execute the tasks according to whatever priority scheme
that it may have, but that priority scheme is independent and has a lower priority of execution than the
priority scheme of the INTC. In other words, the ISRs execute above INTC_CPR priority 0 and outside
the control of the RTOS, the RTOS executes at INTC_CPR priority 0, and while the tasks execute at
different priorities under the control of the RTOS, they also execute at INTC_CPR priority 0.
If a task shares a resource with an ISR and the PCP is being used to manage that shared resource, then the
task’s priority can be elevated in the INTC_CPR while the shared resource is being accessed.
An ISR whose PRIn in INTC priority select registers (INTC_PSR0–INTC_PSR233) has a value of 0 will
not cause an interrupt request to the processor, even if its peripheral or software settable interrupt request
is asserted. For a peripheral interrupt request, not setting its enable bit or disabling the mask bit will cause
it to remain negated, which consequently also will not cause an interrupt request to the processor. Since
the ISRs are outside the control of the RTOS, this ISR will not run unless called by another ISR or the
interrupt exception handler, perhaps after executing another ISR.
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18.7.4
Order of execution
An ISR with a higher priority can preempt an ISR with a lower priority, regardless of the unique vectors
associated with each of their peripheral or software configurable interrupt requests. However, if multiple
peripheral or software configurable interrupt requests are asserted, more than one has the highest priority,
and that priority is high enough to cause preemption, the INTC selects the one with the lowest unique
vector regardless of the order in time that they asserted. However, the ability to meet deadlines with this
scheduling scheme is no less than if the ISRs execute in the time order that their peripheral or software
configurable interrupt requests asserted.
The example in Table 18-11 shows the order of execution of both ISRs with different priorities and the
same priority.
Table 18-11. Order of ISR execution example
Code Executing at End of Step
Step
No.
1
Step description
RTOS
ISR1081
ISR208
ISR308
ISR408
Interrupt
exception
handler
X
PRI in
INTC_CPR
at End of
Step
1
RTOS at priority 0 is executing.
0
2
Peripheral interrupt request 100 at
priority 1 asserts. Interrupt taken.
3
Peripheral interrupt request 400 at
priority 4 is asserts. Interrupt taken.
X
4
4
Peripheral interrupt request 300 at
priority 3 is asserts.
X
4
5
Peripheral interrupt request 200 at
priority 3 is asserts.
X
4
6
ISR408 completes. Interrupt exception
handler writes to INTC_EOIR.
7
Interrupt taken. ISR208 starts to execute,
even though peripheral interrupt request
300 asserted first.
8
ISR208 completes. Interrupt exception
handler writes to INTC_EOIR.
9
Interrupt taken. ISR308 starts to execute.
10
ISR308 completes. Interrupt exception
handler writes to INTC_EOIR.
X
1
11
ISR108 completes. Interrupt exception
handler writes to INTC_EOIR.
X
0
12
RTOS continues execution.
X
1
X
X
1
3
X
X
X
1
3
0
ISR108 executes for peripheral interrupt request 100 because the first eight ISRs are for software configurable interrupt
requests.
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18.7.5
18.7.5.1
Priority ceiling protocol
Elevating priority
The PRI field in INTC_CPR is elevated in the OSEK PCP to the ceiling of all of the priorities of the ISRs
that share a resource. This protocol allows coherent accesses of the ISRs to that shared resource.
For example, ISR1 has a priority of 1, ISR2 has a priority of 2, and ISR3 has a priority of 3. They share
the same resource. Before ISR1 or ISR2 can access that resource, they must raise the PRI value in
INTC_CPR to 3, the ceiling of all of the ISR priorities. After they release the resource, the PRI value in
INTC_CPR can be lowered. If they do not raise their priority, ISR2 can preempt ISR1, and ISR3 can
preempt ISR1 or ISR2, possibly corrupting the shared resource. Another possible failure mechanism is
deadlock if the higher priority ISR needs the lower priority ISR to release the resource before it can
continue, but the lower priority ISR cannot release the resource until the higher priority ISR completes and
execution returns to the lower priority ISR.
Using the PCP instead of disabling processor recognition of all interrupts eliminates the time when
accessing a shared resource that all higher priority interrupts are blocked. For example, while ISR3 cannot
preempt ISR1 while it is accessing the shared resource, all of the ISRs with a priority higher than 3 can
preempt ISR1.
18.7.5.2
Ensuring coherency
A scenario can cause non-coherent accesses to the shared resource. For example, ISR1 and ISR2 are both
running on the same core and both share a resource. ISR1 has a lower priority than ISR2. ISR1 is executing
and writes to the INTC_CPR. The instruction following this store is a store to a value in a shared coherent
data block. Either immediately before or at the same time as the first store, the INTC asserts the interrupt
request to the processor because the peripheral interrupt request for ISR2 has asserted. As the processor is
responding to the interrupt request from the INTC, and as it is aborting transactions and flushing its
pipeline, it is possible that both stores will be executed. ISR2 thereby thinks that it can access the data
block coherently, but the data block has been corrupted.
OSEK uses the GetResource and ReleaseResource system services to manage access to a shared resource.
To prevent corruption of a coherent data block, modifications to PRI in INTC_CPR can be made by those
system services with the code sequence:
disable processor recognition of interrupts
PRI modification
enable processor recognition of interrupts
18.7.6
Selecting priorities according to request rates and deadlines
The selection of the priorities for the ISRs can be made using rate monotonic scheduling (RMS) or a
superset of it, deadline monotonic scheduling (DMS). In RMS, the ISRs that have higher request rates have
higher priorities. In DMS, if the deadline is before the next time the ISR is requested, then the ISR is
assigned a priority according to the time from the request for the ISR to the deadline, not from the time of
the request for the ISR to the next request for it.
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For example, ISR1 executes every 100 µs, ISR2 executes every 200 µs, and ISR3 executes every 300 µs.
ISR1 has a higher priority than ISR, 2 which has a higher priority than ISR3; however, if ISR3 has a
deadline of 150 µs, then it has a higher priority than ISR2.
The INTC has 16 priorities, which may be less than the number of ISRs. In this case, the ISRs should be
grouped with other ISRs that have similar deadlines. For example, a priority could be allocated for every
time the request rate doubles. ISRs with request rates around 1 ms would share a priority, ISRs with request
rates around 500 µs would share a priority, ISRs with request rates around 250 µs would share a priority,
etc. With this approach, a range of ISR request rates of 216 could be included, regardless of the number of
ISRs.
Reducing the number of priorities reduces the processor’s ability to meet its deadlines. However, reducing
the number of priorities can reduce the size and latency through the interrupt controller. It also allows
easier management of ISRs with similar deadlines that share a resource. They do not need to use the PCP
to access the shared resource.
18.7.7
Software configurable interrupt requests
The software configurable interrupt requests can be used in two ways. They can be used to schedule a
lower priority portion of an ISR, and they may also be used by processors to interrupt other processors in
a multiple processor system.
18.7.7.1
Scheduling a lower priority portion of an ISR
A portion of an ISR needs to be executed at the PRIx value in the INTC Priority Select Registers
(INTC_PSR0_3–INTC_PSR232_233), which becomes the PRI value in INTC_CPR with the interrupt
acknowledge. The ISR, however, can have a portion that does not need to be executed at this higher
priority. Therefore, executing the later portion that does not need to be executed at this higher priority can
prevent the execution of ISRs that do not have a higher priority than the earlier portion of the ISR, but do
have a higher priority than what the later portion of the ISR needs. This preemptive scheduling inefficiency
reduces the processor’s ability to meet its deadlines.
One option is for the ISR to complete the earlier higher priority portion, but then schedule through the
RTOS a task to execute the later lower priority portion. However, some RTOSs can require a large amount
of time for an ISR to schedule a task. Therefore, a second option is for the ISR, after completing the higher
priority portion, to set a SETx bit in INTC_SSCIR0_3–INTC_SSCIR4_7. Writing a 1 to SETx causes a
software configurable interrupt request. This software configurable interrupt request will usually have a
lower PRIx value in the INTC_PSRx_x and will not cause preemptive scheduling inefficiencies. After
generating a software settable interrupt request, the higher priority ISR completes. The lower priority ISR
is scheduled according to its priority. Execution of the higher priority ISR is not resumed after the
completion of the lower priority ISR.
18.7.7.2
Scheduling an ISR on another processor
Because the SETx bits in the INTC_SSCIRx_x are memory mapped, processors in multiple-processor
systems can schedule ISRs on the other processors. One application is that one processor wants to
command another processor to perform a piece of work and the initiating processor does not need to use
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the results of that work. If the initiating processor is concerned that the processor executing the software
configurable ISR has not completed the work before asking it to again execute the ISR, it can check if the
corresponding CLRx bit in INTC_SSCIRx_x is asserted before again writing a 1 to the SETx bit.
Another application is the sharing of a block of data. For example, a first processor has completed
accessing a block of data and wants a second processor to then access it. Furthermore, after the second
processor has completed accessing the block of data, the first processor again wants to access it. The
accesses to the block of data must be done coherently. To do this, the first processor writes a 1 to a SETx
bit on the second processor. After accessing the block of data, the second processor clears the
corresponding CLRx bit and then writes 1 to a SETx bit on the first processor, informing it that it can now
access the block of data.
18.7.8
Lowering priority within an ISR
A common method for avoiding preemptive scheduling inefficiencies with an ISR whose work spans
multiple priorities (see Section 18.7.7.1, Scheduling a lower priority portion of an ISR) is to lower the
current priority. However, the INTC has a LIFO whose depth is determined by the number of priorities.
NOTE
Lowering the PRI value in INTC_CPR within an ISR to below the ISR’s
corresponding PRI value in the INTC Priority Select Registers
(INTC_PSR0_3–INTC_PSR232_233) allows more preemptions than the
LIFO depth can support.
Therefore, the INTC does not support lowering the current priority within an ISR as a way to avoid
preemptive scheduling inefficiencies.
18.7.9
18.7.9.1
Negating an interrupt request outside of its ISR
Negating an interrupt request as a side effect of an ISR
Some peripherals have flag bits that can be cleared as a side effect of servicing a peripheral interrupt
request. For example, reading a specific register can clear the flag bits and their corresponding interrupt
requests. This clearing as a side effect of servicing a peripheral interrupt request can cause the negation of
other peripheral interrupt requests besides the peripheral interrupt request whose ISR presently is
executing. This negating of a peripheral interrupt request outside of its ISR can be a desired effect.
18.7.9.2
Negating multiple interrupt requests in one ISR
An ISR can clear other flag bits besides its own. One reason that an ISR clears multiple flag bits is because
it serviced those flag bits, and therefore the ISRs for these flag bits do not need to be executed.
18.7.9.3
Proper setting of interrupt request priority
Whether an interrupt request negates outside its own ISR due to the side effect of an ISR execution or the
intentional clearing a flag bit, the priorities of the peripheral or software configurable interrupt requests for
these other flag bits must be selected properly. Their PRIx values in the INTC Priority Select Registers
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(INTC_PSR0_3–INTC_PSR232_233) must be selected to be at or lower than the priority of the ISR that
cleared their flag bits. Otherwise, those flag bits can cause the interrupt request to the processor to assert.
Furthermore, the clearing of these other flag bits also has the same timing relationship to the writing to
INTC_SSCIR0_3–INTC_SSCIR4_7 as the clearing of the flag bit that caused the present ISR to be
executed (see Section 18.6.3.1.2, End of interrupt exception handler).
A flag bit whose enable bit or mask bit negates its peripheral interrupt request can be cleared at any time,
regardless of the peripheral interrupt request’s PRIx value in INTC_PSRx_x.
18.7.10 Examining LIFO contents
In normal mode, the user does not need to know the contents of the LIFO. He may not even know how
deeply the LIFO is nested. However, if he wants to read the contents, such as in debug mode, they are not
memory mapped. The contents can be read by popping the LIFO and reading the PRI field in either
INTC_CPR. The code sequence is:
pop_lifo:
store to INTC_EOIR
load INTC_CPR, examine PRI, and store onto stack
if PRI is not zero or value when interrupts were enabled, branch to pop_lifo
When the examination is complete, the LIFO can be restored using this code sequence:
push_lifo:
load stacked PRI value and store to INTC_CPR
load INTC_IACKR
if stacked PRI values are not depleted, branch to push_lifo
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Chapter 19 Crossbar Switch (XBAR)
Chapter 19
Crossbar Switch (XBAR)
19.1
Introduction
This chapter describes the multi-port crossbar switch (XBAR), which supports simultaneous connections
between three master ports and three slave ports. XBAR supports a 32-bit address bus width and a 32-bit
data bus width at all master and slave ports.
The crossbar of MPC5606BK is the same as the one of all other PPC55xx and PPC56xx products except
that it cannot be configured by software and that it has a hard-wired configuration.
19.2
Block diagram
Figure 19-1 shows a block diagram of the crossbar switch.
CPU
instructions
CPU data
eDMA
Master modules
Crossbar Switch
Slave modules
Flash
memory
Peripheral
bridges
Internal
SRAM
Figure 19-1. XBAR block diagram
Table 19-1 gives the crossbar switch port for each master and slave, and the assigned and fixed ID number
for each master. The table shows the master ID numbers as they relate to the master port numbers.
Table 19-1. XBAR switch ports for MPC5606BK
Port
Module
Physical master ID
Type
Logical number
e200z0 core–CPU instructions
Master
0
0
e200z0 core–CPU data
Master
1
0
eDMA
Master
2
1
Flash memory
Slave
0
—
Internal SRAM
Slave
2
—
Peripheral bridges
Slave
7
—
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19.3
Overview
The XBAR allows for concurrent transactions to occur from any master port to any slave port. It is possible
for all master ports and slave ports to be in use at the same time as a result of independent master requests.
If a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher
priority master and grants it ownership of the slave port. All other masters requesting that slave port are
stalled until the higher priority master completes its transactions.
Requesting masters are granted access based on a fixed priority.
19.4
•
•
•
•
•
Features
Three master ports:
— Core: e200z0 core instructions
— Core: e200z0 core data
— eDMA
Three slave ports
— Flash (refer to Chapter 30, Flash Memory, for information on accessing flash memory)
— Internal SRAM
— Peripheral bridges
32-bit address, 32-bit data paths
Fully concurrent transfers between independent master and slave ports
Fixed priority scheme and fixed parking strategy
19.5
19.5.1
Modes of operation
Normal mode
In normal mode, the XBAR provides the logic that controls crossbar switch configuration.
19.5.2
Debug mode
The XBAR operation in debug mode is identical to operation in normal mode.
19.6
Functional description
This section describes the functionality of the XBAR in more detail.
19.6.1
Overview
The main goal of the XBAR is to increase overall system performance by allowing multiple masters to
communicate concurrently with multiple slaves. To maximize data throughput, it is essential to keep
arbitration delays to a minimum.
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This section examines data throughput from the point of view of masters and slaves, detailing when the
XBAR stalls masters, or inserts bubbles on the slave side.
19.6.2
General operation
When a master makes an access to the XBAR from an idle master state, the access is taken immediately
by the XBAR. If the targeted slave port of the access is available (that is, the requesting master is currently
granted ownership of the slave port), the access is immediately presented on the slave port. It is possible
to make single clock (zero wait state) accesses through the XBAR by a granted master. If the targeted slave
port of the access is busy or parked on a different master port, the requesting master receives wait states
until the targeted slave port can service the master request. The latency in servicing the request depends
on each master’s priority level and the responding slave’s access time.
Because the XBAR appears to be simply another slave to the master device, the master device has no
indication that it owns the slave port it is targeting. While the master does not have control of the slave port
it is targeting, it is wait-stated.
A master is given control of a targeted slave port only after a previous access to a different slave port has
completed, regardless of its priority on the newly targeted slave port. This prevents deadlock from
occurring when a master has the following conditions:
•
•
•
Outstanding request to slave port A that has a long response time
Pending access to a different slave port B
Lower priority master also makes a request to the different slave port B.
In this case, the lower priority master is granted bus ownership of slave port B after a cycle of arbitration,
assuming the higher priority master slave port A access is not terminated.
After a master has control of the slave port it is targeting, the master remains in control of that slave port
until it gives up the slave port by running an IDLE cycle, leaves that slave port for its next access, or loses
control of the slave port to a higher priority master with a request to the same slave port. However, because
all masters run a fixed-length burst transfer to a slave port, it retains control of the slave port until that
transfer sequence is completed.
When a slave bus is idled by the XBAR, it is parked on the master that did the last transfer.
19.6.3
Master ports
A master access is taken if the slave port to which the access decodes is either currently servicing the
master or is parked on the master. In this case, the XBAR is completely transparent and the master access
is immediately transmitted on the slave bus and no arbitration delays are incurred. A master access stall if
the access decodes to a slave port that is busy serving another master, parked on another master.
If the slave port is currently parked on another master, and no other master is requesting access to the slave
port, then only one clock of arbitration is incurred. If the slave port is currently serving another master of
a lower priority and the master has a higher priority than all other requesting masters, then the master gains
control over the slave port as soon as the data phase of the current access is completed. If the slave port is
currently servicing another master of a higher priority, then the master gains control of the slave port after
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Chapter 19 Crossbar Switch (XBAR)
the other master releases control of the slave port if no other higher priority master is also waiting for the
slave port.
A master access is responded to with an error if the access decodes to a location not occupied by a slave
port. This is the only time the XBAR directly responds with an error response. All other error responses
received by the master are the result of error responses on the slave ports being passed through the XBAR.
19.6.4
Slave ports
The goal of the XBAR with respect to the slave ports is to keep them 100% saturated when masters are
actively making requests. To do this the XBAR must not insert any bubbles onto the slave bus unless
absolutely necessary.
There is only one instance when the XBAR forces a bubble onto the slave bus when a master is actively
making a request. This occurs when a handoff of bus ownership occurs and there are no wait states from
the slave port. A requesting master that does not own the slave port is granted access after a one clock
delay.
19.6.5
Priority assignment
Each master port is assigned a fixed 3-bit priority level (hard-wired priority). The following table shows
the priority levels assigned to each master (the lowest has highest priority).
Table 19-2. Hardwired bus master priorities
Port
Module
19.6.6
Priority level
Type
Master #
e200z0 core–CPU instructions
Master
0
7
e200z0 core–CPU data
Master
1
6
eDMA
Master
2
5
Arbitration
XBAR supports only a fixed-priority comparison algorithm.
19.6.6.1
Fixed priority operation
When operating in fixed-priority arbitration mode, each master is assigned a unique priority level in the
XBAR_MPR. If two masters both request access to a slave port, the master with the higher priority in the
selected priority register gains control over the slave port.
Any time a master makes a request to a slave port, the slave port checks to see if the new requesting
master’s priority level is higher than that of the master that currently has control over the slave port (if any).
The slave port does an arbitration check at every clock edge to ensure that the proper master (if any) has
control of the slave port.
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Chapter 19 Crossbar Switch (XBAR)
If the new requesting master’s priority level is higher than that of the master that currently has control of
the slave port, the higher priority master is granted control at the termination of any currently pending
access, assuming the pending transfer is not part of a burst transfer.
A new requesting master must wait until the end of the fixed-length burst transfer, before it is granted
control of the slave port. But if the new requesting master’s priority level is lower than that of the master
that currently has control of the slave port, the new requesting master is forced to wait until the master that
currently has control of the slave port is finished accessing the current slave port.
19.6.6.1.1
Parking
If no master is currently requesting the slave port, the slave port is parked. The slave port parks always to
the last master (park-on-last). When parked on the last master, the slave port is passing that master’s signals
through to the slave bus. When the master accesses the slave port again, no other arbitration penalties are
incurred except that a one clock arbitration penalty is incurred for each access request to the slave port
made by another master port. All other masters pay a one clock penalty.
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Chapter 20 System Integration Unit Lite (SIUL)
Chapter 20
System Integration Unit Lite (SIUL)
20.1
Introduction
This chapter describes the System Integration Unit Lite (SIUL), which manages the pads and their
configuration. It controls the multiplexing of the alternate functions used on all pads and is responsible for
the management of the external interrupts to the device.
20.2
Overview
The System Integration Unit Lite (SIUL) controls the MCU pad configuration, ports, general-purpose
input and output (GPIO) signals, and external interrupts with trigger event configuration. Figure 20-1
provides a block diagram of the SIUL and its interfaces to other system components.
The module provides the capability to configure, read, and write to the device’s general-purpose I/O pads
that can be configured as either inputs or outputs.
• When a pad is configured as an input, the state of the pad (logic high or low) is obtained by reading
an associated data input register.
• When a pad is configured as an output, the value driven onto the pad is determined by writing to
an associated data output register. Enabling the input buffers when a pad is configured as an output
allows the actual state of the pad to be read.
• To enable monitoring of an output pad value, the pad can be configured as both output and input
so the actual pad value can be read back and compared with the expected value.
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Chapter 20 System Integration Unit Lite (SIUL)
SIUL Module
Pad Config (IOMUXC)
149(1)
Pad Cfg (PCRs)
GPIO Functionality
149(1)
Data
149(1)
Pad Input
IO
MUX
149(1)
PADS
IPS
Master
Interrupt Functionality
24(2)
Interrupt
– Configuration
– Glitch Filter
3
Interrupt
Controller
IPS
BUS
Notes:
1
149 GPIOs in 176-pin LQFP and 208 BGA, as many as 121 GPIOs in 144-pin LQFP and as many as 77 GPIOs in 100-pin LQFP
2
24 EIRQs in 144-pin LQFP, 176-pin LQFP and 208 BGA; as many as 20 EIRQs in 100-pin LQFP
Figure 20-1. System Integration Unit Lite block diagram
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Chapter 20 System Integration Unit Lite (SIUL)
20.3
Features
The System Integration Unit Lite supports these distinctive features:
• GPIO
— GPIO function on as many as 149 I/O pins
— Dedicated input and output registers for most GPIO pins1
• External interrupts
— Three interrupt vectors dedicated to 24 external interrupts
— 24 programmable digital glitch filters
— Independent interrupt mask
— Edge detection
• System configuration
— Pad configuration control
20.4
External signal description
Most device pads support multiple device functions. Pad configuration registers are provided to enable
selection between GPIO and other signals. These other signals, also referred to as alternate functions, are
typically peripheral functions.
GPIO pads are grouped in ports, with each port containing as many as 16 pads. With appropriate
configuration, all pins in a port can be read or written to in parallel with a single R/W access.
NOTE
In order to use GPIO port functionality, all pads in the port must be
configured as GPIO rather than as alternate functions.
Table 20-1 lists the external pins configurable via the SIUL.
(
Table 20-1. SIUL signal properties
GPIO[0:148]
category
Name
I/O
direction
Function
System configuration
GPIO[0:148]1
I/O2
General-purpose input/output
External interrupt
PA[3], PA[6:8], PA[11:12],
PA[14], PC[2:5], PC[12],
PC[14:15], PE[2], PE[4],
PE[6:7], PE[10], PE[12],
PE[14], PF[15], PG[1],
PG[8]3
Input
Pins with External Interrupt Request
functionality. Please see Chapter 4, Signal
description, for details.
1
GPIO[0–26], GPIO[28–59], and GPIO[61–122] in 144-pin LQFP; GPIO[0–26], GPIO[28–59], GPIO[61–76], and
GPIO[121–122] in 100-pin LQFP
2
Most, but not all GPIO pads can be configured as inputs or outputs but some, e.g., analog pins with GPIO function,
are only configurable as inputs.
3 PE[14], PF[15], PG[1], and PG[8] not available in 100-pin LQFP
1.Some device pins, e.g., analog pins, do not have both input and output functionality.
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Chapter 20 System Integration Unit Lite (SIUL)
20.4.1
20.4.1.1
Detailed signal descriptions
General-purpose I/O pins (GPIO[0:148])1
The GPIO pins provide general-purpose input and output functions. The GPIO pins are generally
multiplexed with other I/O pin functions. Each GPIO input and output is separately controlled by an input
(GPDIn_n) or output (GPDOn_n) register.
20.4.1.2
External interrupt request input pins (EIRQ[0:23])2
The EIRQ[0:23] pins are connected to the SIUL inputs. Rising- or falling-edge events are enabled by
setting the corresponding bits in the SIUL_IREER or the SIUL_IFEER register.
1. GPIO[0–26], GPIO[28–59], and GPIO[61–122] in 144-pin LQFP; GPIO[0–26], GPIO[28–59], GPIO[61–76], and
GPIO[121–122] in 100-pin LQFP
2. EIRQ[0:11] plus EIRQ[16:23] in 100-pin LQFP
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Chapter 20 System Integration Unit Lite (SIUL)
20.5
Memory map and register description
This section provides a detailed description of all registers accessible in the SIUL module.
20.5.1
SIUL memory map
Table 20-2 gives an overview of the SIUL registers implemented.
Table 20-2. SIUL memory map
Base address: 0xC3F9_0000
Address offset
Register
Location
0x0000
Reserved
0x0004
MCU ID Register #1 (MIDR1)
on page 353
0x0008
MCU ID Register #2 (MIDR2)
on page 354
0x000C–0x0013
Reserved
0x0014
Interrupt Status Flag Register (ISR)
on page 355
0x0018
Interrupt Request Enable Register (IRER)
on page 356
0x001C–0x00
Reserved
0x0028
Interrupt Rising-Edge Event Enable Register (IREER)
on page 356
0x002C
Interrupt Falling-Edge Event Enable Register (IFEER)
on page 357
0x0030
Interrupt Filter Enable Register (IFER)
on page 358
0x0034–0x003F
Reserved
0x0040–0x0168
Pad Configuration Registers (PCR0–PCR148)1
0x016A–0x04FF
Reserved
0x0500–0x053C
Pad Selection for Multiplexed Inputs Registers
(PSMI0_3–PSMI60_63)
0x0540–0x05FF
Reserved
0x0600–0x06A0
GPIO Pad Data Output Registers (GPDO0_3–GPDO148_151)2
0x06A4–0x07FF
Reserved
0x0800–0x08A0
GPIO Pad Data Input Registers (GPDI0_3–GPDI148_151)3
0x08A4–0x0BFF
Reserved
0x0C00–0x0C10
Parallel GPIO Pad Data Out Registers (PGPDO0 – PGPDO4)
0x0C14–0x0C3F
Reserved
0x0C40–0x0C50
Parallel GPIO Pad Data In Registers (PGPDI0 – PGPDI4)
0x0C54–0x0C7F
Reserved
0x0C80–0x0CA4
Masked Parallel GPIO Pad Data Out Register
(MPGPDO0–MPGPDO9)
0x0CA8–0x0FFF
Reserved
on page 359
on page 361
on page 366
on page 367
on page 367
on page 368
on page 369
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Chapter 20 System Integration Unit Lite (SIUL)
Table 20-2. SIUL memory map (continued)
Base address: 0xC3F9_0000
Address offset
Register
Location
0x1000–0x105C
Interrupt Filter Maximum Counter Registers (IFMC0–IFMC23)4
on page 371
0x1060–0x107C
Reserved
0x1080
Interrupt Filter Clock Prescaler Register (IFCPR)
0x1084–0x3FFF
Reserved
on page 371
1
PCR0–26, PCR28–59, and PCR61–122 in 144-pin LQFP; PCR0–26, PCR28–59, PCR61–76, and PCR121–122 in
100-pin LQFP—all remaining registers are reserved.
2
GPDO0–26, GPDO28–59, and GPDO61–122 in 144-pin LQFP; GPDO0–26, GPDO28–59, GPDO61–76, and
GPDO121–122 in 100-pin LQFP—all remaining registers are reserved.
3 GPDI0–26, GPDI28–59, and GPDI61–122 in 144-pin LQFP; GPDI0–26, GPDI28–59, GPDI61–76, and
GPDI121–122 in 100-pin LQFP—all remaining registers are reserved.
4 IFMC0–11 plus IFMC16–23 in 100-pin LQFP—all remaining registers are reserved.
NOTE
A transfer error will be issued when trying to access completely reserved
register space.
20.5.2
Register protection
Individual registers in System Integration Unit Lite can be protected from accidental writes using the
Register Protection module. The following registers can be protected:
• Interrupt Request Enable Register (IRER)
• Interrupt Rising-Edge Event Enable Register (IREER)
• Interrupt Falling-Edge Event Enable Register (IFEER)
• Interrupt Filter Enable Register (IFER),
• Pad Configuration Registers (PCR0–PCR148). Note that only the following registers can be
protected:
— PCR[0:15] (Port A)
— PCR[16:19] (Port B[0:3])
— PCR[34:47] (Port C[2:15])
• Pad Selection for Multiplexed Inputs Registers (PSMI0_3–PSMI60_63)
• Interrupt Filter Maximum Counter Registers (IFMC0–IFMC23). Note that only IFMC[0:15] can
be protected.
• Interrupt Filter Clock Prescaler Register (IFCPR)
See Chapter 32, Register Protection, for more details.
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Chapter 20 System Integration Unit Lite (SIUL)
20.5.3
Register descriptions
20.5.3.1
MCU ID Register #1 (MIDR1)
This register holds identification information about the device.
Offset: 0x0004
0
Access: Read
1
2
3
4
5
6
R
7
8
9
10
11
12
13
14
15
PARTNUM[15:0]
W
Reset
0
1
0
1
0
1
1
0
0
0
0
0
0
1
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
R CSP
PKG
MAJOR_MASK
MINOR_MASK
W
Reset
0
0
1
1
0
1
0
0
0
0
0
0
0
0
Figure 20-2. MCU ID Register #1 (MIDR1)
Table 20-3. MIDR1 field descriptions
Field
PARTNUM[15:0]
Description
MCU Part Number, lower 16 bits
Device part number of the MCU.
0101_0110_0000_0001:128 KB
0101_0110_0000_0010: 256 KB
0101_0110_0000_0011: 320/384 KB
0101_0110_0000_0100: 512 KB
0101_0110_0000_0101: 768 KB
0101_0110_0000_0110: 1 MB
0101_0110_0000_0111: 1.5 MB
For the full part number this field needs to be combined with MIDR2[PARTNUM[23:16]].
CSP
Always reads back 0
PKG
Package Settings
Can be read by software to determine the package type that is used for the particular device
as described below. Any values not explicitly specified are reserved.
0b01001: 100-pin LQFP
0b01101: 144-pin LQFP
0b10000: 208 BGA
0b10001: 176-pin LQFP
MAJOR_MASK
Major Mask Revision
Counter starting at 0x0. Incremented each time there is a resynthesis.
MINOR_MASK
Minor Mask Revision
Counter starting at 0x0. Incremented each time a mask change is done.
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20.5.3.2
MCU ID Register #2 (MIDR2)
Offset: 0x0008
0
R
Access: Read
1
SF
2
3
4
5
FLASH_SIZE_1
6
7
8
FLASH_SIZE_2
9
10
11
12
13
14
15
0
0
0
0
0
0
0
W
Reset
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
EE
0
0
0
0
0
0
0
1
01
01
01
0
R
PARTNUM[23:16]
W
Reset
0
1
0
0
0
0
1
0/1
Figure 20-3. MCU ID Register #2 (MIDR2)
1
Static bit fixed in hardware
Table 20-4. MIDR2 field descriptions
Field
SF
Description
Manufacturer
0 Freescale
1 Reserved
FLASH_SIZE_1 Coarse granularity for Flash memory size
Total flash memory size = FLASH_SIZE_1 + FLASH_SIZE_2
0011 128 KB
0100 256 KB
0101 512 KB
0110 1 MB
FLASH_SIZE_2 Fine granularity for Flash memory size
Total flash memory size = FLASH_SIZE_1 + FLASH_SIZE_2
0000 0 × (FLASH_SIZE_1 / 8)
0010 2 × (FLASH_SIZE_1 / 8)
0100 4 × (FLASH_SIZE_1 / 8)
PARTNUM
[23:16]
MCU Part Number, upper 8 bits containing the ASCII character within the MCU part number
0x42: Character B (Body controller)
0x43: Character C (Gateway)
For the full part number this field needs to be combined with MIDR1[PARTNUM[15:0]].
EE
20.5.3.3
Data Flash present
0 No Data Flash is present
1 Data Flash is present
Interrupt Status Flag Register (ISR)
This register holds the interrupt flags.
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Offset: 0x0014
0
R
0
Access: User read/write
1
2
0
0
3
0
4
5
0
0
6
0
7
8
9
10
0
11
EIF[23:16]
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
R
EIF[15:0]
W
w1c
Reset
13
14
15
1
w1c
W
Reset
12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
25
26
27
28
29
30
31
0
0
0
0
0
0
0
1
Figure 20-4. Interrupt Status Flag Register (ISR)
1
20 flags in 100-pin LQFP: EIF[23:16] plus EIF[11:0] (register bits 16–19 reserved).
Table 20-5. ISR field descriptions
Field
Description
EIF[x]
External Interrupt Status Flag x
This flag can be cleared only by writing a 1. Writing a 0 has no effect. If enabled (IRER[x]), EIF[x]
causes an interrupt request.
0 No interrupt event has occurred on the pad
1 An interrupt event as defined by IREER[x] and IFEER[x] has occurred
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Chapter 20 System Integration Unit Lite (SIUL)
20.5.3.4
Interrupt Request Enable Register (IRER)
This register is used to enable the interrupt messaging to the interrupt controller.
Offset: 0x0018
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
0
0
12
13
14
15
0
0
0
0
27
28
29
30
31
0
0
0
0
0
IRE[23:16]1
W
Reset
R
IRE[15:0]1
W
Reset
0
0
0
0
0
0
0
0
0
Figure 20-5. Interrupt Request Enable Register (IRER)
1
20 enable requests in 100-pin LQFP: IRE[23:16] plus IRE[11:0] (register bits 16–19 reserved).
Table 20-6. IRER field descriptions
Field
Description
IRE[x]
20.5.3.5
External Interrupt Request Enable x
0 Interrupt requests from the corresponding ISR[EIF[x]] bit are disabled.
1 Interrupt requests from the corresponding ISR[EIF[x]] bit are enabled.
Interrupt Rising-Edge Event Enable Register (IREER)
This register is used to enable rising-edge triggered events on the corresponding interrupt pads.
Offset:0x0028
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
0
0
12
13
14
15
0
0
0
0
27
28
29
30
31
0
0
0
0
0
IREE[23:16]1
W
Reset
R
IREE[15:0]1
W
Reset
0
0
0
0
0
0
0
0
0
Figure 20-6. Interrupt Rising-Edge Event Enable Register (IREER)
1
20 enable events in 100-pin LQFP: IREE[23:16] plus IREE[11:0] (register bits 16–19 reserved).
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Table 20-7. IREER field descriptions
Field
Description
IREE[x]
20.5.3.6
Enable rising-edge events to cause the ISR[EIF[x]] bit to be set.
0 Rising-edge event is disabled
1 Rising-edge event is enabled
Interrupt Falling-Edge Event Enable Register (IFEER)
This register is used to enable falling-edge triggered events on the corresponding interrupt pads.
Offset:0x002C
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
0
0
12
13
14
15
0
0
0
0
27
28
29
30
31
0
0
0
0
0
IFEE[23:16]1
W
Reset
R
IFEE[15:0]1
W
Reset
0
0
0
0
0
0
0
0
0
Figure 20-7. Interrupt Falling-Edge Event Enable Register (IFEER)
1
20 enabling events in 100-pin LQFP: IFEE[23:16] plus IFEE[11:0] (register bits 16–19 reserved).
Table 20-8. IFEER field descriptions
Field
Description
IFEE[x]
Enable falling-edge events to cause the ISR[EIF[x]] bit to be set.
0 Falling-edge event is disabled
1 Falling-edge event is enabled
NOTE
If both the IREER[IREE] and IFEER[IFEE] bits are cleared for the same
interrupt source, the interrupt status flag for the corresponding external
interrupt will never be set. If IREER[IREE] and IFEER[IFEE] bits are set
for the same source the interrupts are triggered by both rising edge events
and falling edge events.
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Chapter 20 System Integration Unit Lite (SIUL)
20.5.3.7
Interrupt Filter Enable Register (IFER)
This register is used to enable a digital filter counter on the corresponding interrupt pads to filter out
glitches on the inputs.
Offset:0x0030
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
0
0
12
13
14
15
0
0
0
0
27
28
29
30
31
0
0
0
0
0
IFE[23:16]1
W
Reset
R
IFE[15:0]1
W
Reset
0
0
0
0
0
0
0
0
0
Figure 20-8. Interrupt Filter Enable Register (IFER)
1
20 bits in 100-pin LQFP: IFE[23:16] plus IFE[11:0] (register bits 16–19 reserved).
Table 20-9. IFER field descriptions
Field
IFE[x]
20.5.3.8
Description
Enable digital glitch filter on the interrupt pad input
0 Filter is disabled
1 Filter is enabled
See the IFMC field descriptions in Table 20-20 for details on how the filter works.
Pad Configuration Registers (PCR0–PCR148)
The Pad Configuration Registers allow configuration of the static electrical and functional characteristics
associated with I/O pads. Each PCR controls the characteristics of a single pad.
Please note that input and output peripheral muxing are separate.
• For output pads:
— Select the appropriate alternate function in Pad Config Register (PCR)
— OBE is not required for functions other than GPIO
• For input pads:
— Select the feature location from PSMI register
— Set the IBE bit in the appropriate PCR
• For normal GPIO (not alternate function):
— Configure PCR
— Read from GPDI or write to GPDO
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Offsets: Base + 0x0040 (PCR0)(149 registers)
Base + 0x0042 (PCR1)
...
Base + 0x0168 (PCR148)
0
R
1
2
3
4
5
Access: User read/write
6
7
OBE
IBE
02
03
0
SMC APC
PA[1:0]
8
9
0
0
10
11
12
0
0
ODE
13
14
15
SRC WPE WPS
W
Reset
01
0
0
0
01
0
0
0
0
0
0
0
03
14
Figure 20-9. Pad Configuration Registers (PCRx)
1
SMC and PA[1] are 1 for JTAG pads
2 OBE is 1 for TDO
3
IBE and WPE are 1 for TCK, TMS, TDI, FAB, and ABS
4
WPS is 0 for input only pad with analog feature and FAB
NOTE
16- and 32-bit accesses to the PCRx registers are supported.
In addition to the bit map above, the following Table 20-11 describes the PCR depending on the pad type
(pad types are defined in the “Pad types” section of this reference manual). The bits in shaded fields are
not implemented for the particular I/O type. The PA field selecting the number of alternate functions may
or may not be present depending on the number of alternate functions actually mapped on the pad.
Table 20-10. PCR bit implementation by pad type
PCR bit No.
Pad type
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
S, M, F (Pad with
GPIO and digital
alternate
function)
SMC APC
PA[1:0]
OBE
IBE
ODE
SRC WPE WPS
Pad with slew rate
control
SMC APC
PA[1:0]
OBE
IBE
ODE
SRC WPE WPS
J (Pad with GPIO
and analog
functionality)
SMC APC
PA[1:0]
OBE
IBE
ODE
SRC WPE WPS
I (Pad dedicated
to ADC)
SMC APC
PA[1:0]
OBE
IBE
ODE
SRC WPE WPS
Table 20-11. PCRx field descriptions
Field
Description
SMC
Safe Mode Control.
This bit supports the overriding of the automatic deactivation of the output buffer of the associated
pad upon entering SAFE mode of the device.
0 In SAFE mode, the output buffer of the pad is disabled.
1 In SAFE mode, the output buffer remains functional.
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Table 20-11. PCRx field descriptions (continued)
Field
APC
PA[1:0]
Description
Analog Pad Control.
This bit enables the usage of the pad as analog input.
0 Analog input path from the pad is gated and cannot be used
1 Analog input path switch can be enabled by the ADC
Pad Output Assignment
This field is used to select the function that is allowed to drive the output of a multiplexed pad.
00 Alternative Mode 0 — GPIO
01 Alternative Mode 1 — See Chapter 4, Signal description
10 Alternative Mode 2 — See Chapter 4, Signal description
11 Alternative Mode 3 — See Chapter 4, Signal description
Note: Number of bits depends on the actual number of actual alternate functions. Please see data
sheet.
20.5.3.9
OBE
Output Buffer Enable
This bit enables the output buffer of the pad in case the pad is in GPIO mode.
0 Output buffer of the pad is disabled when PA[1:0] = 00
1 Output buffer of the pad is enabled when PA[1:0] = 00
IBE
Input Buffer Enable
This bit enables the input buffer of the pad.
0 Input buffer of the pad is disabled
1 Input buffer of the pad is enabled
ODE
Open Drain Output Enable
This bit controls output driver configuration for the pads connected to this signal. Either open drain
or push/pull driver configurations can be selected. This feature applies to output pads only.
0 Pad configured for push/pull output
1 Pad configured for open drain
SRC
Slew Rate Control
This field controls the slew rate of the associated pad when it is slew rate selectable. Its usage is
the following:
0 Pad configured as slow (default)
1 Pad is configured as medium or fast (depending on the pad)
Note: PC[1] (TDO pad) is medium only. By default SRC = 0, and writing 1 has no effect.
WPE
Weak Pull Up/Down Enable
This bit controls whether the weak pull up/down devices are enabled/disabled for the pad
connected to this signal.
0 Weak pull device disabled for the pad
1 Weak pull device enabled for the pad
WPS
Weak Pull Up/Down Select
This bit controls whether weak pull up or weak pull down devices are used for the pads connected
to this signal when weak pull up/down devices are enabled.
0 Weak pulldown selected
1 Weak pullup selected
Pad Selection for Multiplexed Inputs Registers (PSMI0_3–PSMI60_63)
In some cases, a peripheral input signal can be selected from more than one pin. For example, the
CAN1_RXD signal can be selected on three different pins: PC[3], PC[11], and PF[15]. Only one can be
active at a time. To select the pad to be used as input to the peripheral:
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•
•
Select the signal via the pad’s PCR register using the PA field.
Specify the pad to be used via the appropriate PSMI field.
Offsets:0x0500–0x053C (16 registers)
R
0
1
2
3
0
0
0
0
4
Access: User read/write
5
6
7
8
9
10
11
0
0
0
0
12
PADSEL0
13
14
15
PADSEL1
W
Reset
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
PADSEL2
PADSEL3
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 20-10. Pad Selection for Multiplexed Inputs Register (PSMI0_3)
Table 20-12. PSMI0_3 field descriptions
Field
Description
PADSEL0–3, Pad Selection Bits
PADSEL4–7, Each PADSEL field selects the pad currently used for a certain input function. See Table 20-13.
...
PADSEL60–63
In order to multiplex different pads to the same peripheral input, the SIUL provides a register that controls
the selection between the different sources.
Table 20-13. Peripheral input pin selection
PSMI registers PADSEL fields SIUL address offset
Function / Peripheral
Mapping1
PSMI0_3
PADSEL0
0x500
CAN1RX / FlexCAN_1
00: PCR[35]
01: PCR[43]
10: PCR[95]2
PADSEL1
0x501
CAN2RX / FlexCAN_2
00: PCR[73]
01: PCR[89]2
PADSEL2
0x502
CAN3RX / FlexCAN_3
00: PCR[36]
01: PCR[73]
10: PCR[89]2
PADSEL3
0x503
CAN4RX / FlexCAN_4
00: PCR[35]
01: PCR[43]
10: PCR[95]2
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Table 20-13. Peripheral input pin selection (continued)
PSMI registers PADSEL fields SIUL address offset
Function / Peripheral
Mapping1
PSMI4_7
PSMI8_11
PSMI12_15
PSMI16_19
PADSEL4
0x504
CAN5RX / FlexCAN_5
00: PCR[64]
01: PCR[97]2
PADSEL5
0x505
SCK_0 / DSPI_0
00: PCR[14]
01: PCR[15]
PADSEL6
0x506
CS0_0 / DSPI_0
00: PCR[14]
01: PCR[15]
10: PCR[27]3
PADSEL7
0x507
SCK_1 / DSPI_1
00: PCR[34]
01: PCR[68]
10: PCR[114]2
PADSEL8
0x508
SIN_1 / DSPI_1
00: PCR[36]
01: PCR[66]
10: PCR[112]2
PADSEL9
0x509
CS0_1 / DSPI_1
00: PCR[]
01: PCR[61]
10: PCR[69]
11: PCR[115]2
PADSEL10
0x50A
SCK_2 / DSPI_2
00: PCR[46]
01: PCR[78]2
10: PCR[105]2
PADSEL11
0x50B
SIN_2 / DSPI_2
00: PCR[44]
01: PCR[76]
PADSEL12
0x50C
CS0_2 / DSPI_2
00: PCR[47]
01: PCR[79]2
10: PCR[82]2
11: PCR[104]2
PADSEL13
0x50D
E1UC[3] / eMIOS_0
00: PCR[3]
01: PCR[27]3
10: PCR[40]
PADSEL14
0x50E
E0UC[4] / eMIOS_0
00: PCR[4]
01: PCR[28]
PADSEL15
0x50F
E0UC[5] / eMIOS_0
00: PCR[5]
01: PCR[29]
PADSEL16
0x510
E0UC[6] / eMIOS_0
00: PCR[6]
01: PCR[30]
PADSEL17
0x511
E0UC[7] / eMIOS_0
00: PCR[7]
01: PCR[31]
10: PCR[41]
PADSEL18
0x512
E0UC[10] / eMIOS_0
00: PCR[10]
01: PCR[80]2
PADSEL19
0x513
E0UC[11] / eMIOS_0
00: PCR[11]
01: PCR[81]2
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Table 20-13. Peripheral input pin selection (continued)
PSMI registers PADSEL fields SIUL address offset
Function / Peripheral
Mapping1
PSMI20_23
PSMI24_27
PSMI28_31
PSMI32_35
PADSEL20
0x514
E0UC[12] / eMIOS_0
00: PCR[44]
01: PCR[82]2
PADSEL21
0x515
E0UC[13] / eMIOS_0
00: PCR[45]
01: PCR[83]2
10: PCR[0]
PADSEL22
0x516
E0UC[14] / eMIOS_0
00: PCR[46]
01: PCR[84]2
10: PCR[8]
PADSEL23
0x517
E0UC[22] / eMIOS_0
00: PCR[70]
01: PCR[72]
10: PCR[85]2
PADSEL24
0x518
E0UC[23] / eMIOS_0
00: PCR[71]
01: PCR[73]
10: PCR[86]2
PADSEL25
0x519
E0UC[24] / eMIOS_0
00: PCR[60]
01: PCR[106]2
10: PCR[75]
PADSEL26
0x51A
E0UC[25] / eMIOS_0
00: PCR[61]
01: PCR[107]2
PADSEL27
0x51B
E0UC[26] / eMIOS_0
00: PCR[62]
01: PCR[108]2
PADSEL28
0x51C
E0UC[27] / eMIOS_0
00: PCR[63]
01: PCR[109]2
PADSEL29
0x51D
SCL / f_0
00: PCR[11]
01: PCR[19]
PADSEL30
0x51E
SDA / I2C__0
00: PCR[10]
01: PCR[18]
PADSEL31
0x51F
LIN3RX / LINFlex_3
00: PCR[8]
01: PCR[75]
PADSEL32
0x520
SCK_3 / DSPI_3
00: PCR[100]2
01: PCR[124]3
PADSEL33
0x521
SIN_3 / DSPI_3
00: PCR[101]2
01: PCR[139]3
PADSEL34
0x522
CS0_3 / DSPI_3
00: PCR[99]2
01: PCR[125]3
10: PCR[140]3
PADSEL35
0x523
SCK_4 / DSPI_4
00: PCR[109]2
01: PCR[126]3
10: PCR[133]3
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Table 20-13. Peripheral input pin selection (continued)
PSMI registers PADSEL fields SIUL address offset
Function / Peripheral
Mapping1
PSMI36_39
PSMI40_43
PSMI44_47
PSMI48_51
PADSEL36
0x524
SIN_4 /
DSPI_4Reserved
00: PCR[106]2
01:
PCR[142]3—
PADSEL37
0x525
CS0_4 /
DSPI_4Reserved
00: PCR[107]2
01: PCR[123]3
10: PCR[134]3
11:
PCR[143]3—
PADSEL38
0x526
E0UC[0] / eMIOS_0
00: PCR[0]
01: PCR[14]
PADSEL39
0x527
E0UC[1] / eMIOS_0
00: PCR[1]
01: PCR[15]
PADSEL40
0x528
E0UC[28] / eMIOS_0
00: PCR[12]
01: PCR[128]3
PADSEL41
0x529
E0UC[29] / eMIOS_0
00: PCR[13]
01: PCR[129]3
PADSEL42
0x52A
E0UC[30] / eMIOS_0
00: PCR[16]
01: PCR[18]
10: PCR[130]3
PADSEL43
0x52B
E0UC[31] / eMIOS0
00: PCR[17]
01: PCR[19]
10: PCR[131]3
PADSEL44
0x52C
E1UC[1] / eMIOS_1
00: PCR[111]2
01: PCR[89]2
PADSEL45
0x52D
E1UC[2] / eMIOS_1
00: PCR[112]2
01: PCR[90]2
PADSEL46
0x52E
E1UC[3] / eMIOS_1
00: PCR[113]2
01: PCR[91]2
PADSEL47
0x52F
E1UC[4] / eMIOS_1
00: PCR[114]2
01: PCR[95]2
PADSEL48
0x530
E1UC[5] / eMIOS_1
00: PCR[115]2
01: PCR[123]3
PADSEL49
0x531
E1UC[17] / eMIOS_1
00: PCR[104]2
01: PCR[127]3
PADSEL50
0x532
E1UC[18] / eMIOS_1
00: PCR[105]2
01: PCR[148]
PADSEL51
0x533
E1UC[25] / eMIOS_1
00: PCR[92]2
01: PCR[124]3
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Table 20-13. Peripheral input pin selection (continued)
PSMI registers PADSEL fields SIUL address offset
Function / Peripheral
Mapping1
PSMI52_55
PSMI56_59
PSMI60_634
PADSEL52
0x534
E1UC[26] / eMIOS_1
00: PCR[93]2
01: PCR[125]3
PADSEL53
0x535
E1UC[27] / eMIOS_1
00: PCR[94]2
01: PCR[126]3
PADSEL54
0x536
E1UC[28] / eMIOS_1
00: PCR[38]
01: PCR[132]3
PADSEL55
0x537
E1UC[29] / eMIOS_1
00: PCR[39]
01: PCR[133]3
PADSEL56
0x538
E1UC[30] /
eMIOS_1Reserved
00: PCR[74]
01: PCR[103]2
10:
PCR[134]3—
PADSEL57
0x539
E1UC[31] /
eMIOS_1Reserved
00: PCR[36]
01: PCR[106]2
10:
PCR[135]3—
PADSEL58
0x53A
LIN2RX / LINFlex _2
00: PCR[41]
01: PCR[11]
PADSEL59
0x53B
LIN4RX / LINFlex
_4Reserved
00: PCR[6]
01: PCR[91]2—
PADSEL60
0x53C
LIN5RX / LINFlex _5
00: PCR[4]
01: PCR[93]2
PADSEL61
0x53D
Reserved
PADSEL62
0x53E
LIN0RX/LINFlexD_0
00: PCR[19]
01: PCR[17]
1
See Chapter 4, Signal description, for correspondence between PCR and pinout
Not available in 100-pin LQFP
3 Available only in 176-pin LQFP and 208 BGA packages
4 PADSEL63 not implemented
2
20.5.3.10 GPIO Pad Data Output Registers (GPDO0_3–GPDO148_151)
These registers are used to set or clear GPIO pads. Each pad data out bit can be controlled separately with
a byte access.
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0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
PDO[0]
0
0
0
0
0
0
0
PDO[1]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PDO[3]
R
Access: User read/write
PDO[2]
Offsets: 0x0600–0x06A0 (38 registers)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
Figure 20-11. Port GPIO Pad Data Output Register 0–3 (GPDO0_3)
Table 20-14. GPDO0_3 field descriptions
Field
PDO[x]
Description
Pad Data Out
This bit stores the data to be driven out on the external GPIO pad controlled by this register.
0 Logic low value is driven on the corresponding GPIO pad when the pad is configured as an
output
1 Logic high value is driven on the corresponding GPIO pad when the pad is configured as an
output
CAUTION
Toggling several IOs at the same time can significantly increase the current in a pad group. Caution must
be taken to avoid exceeding maximum current thresholds. Please see data sheet.
20.5.3.11 GPIO Pad Data Input Registers (GPDI0_3–GPDI148_151)
These registers are used to read the GPIO pad data with a byte access.
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0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
PDI[0]
0
0
0
0
0
0
0
PDI[1]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PDI[3]
R
Access: User read
PDI[2]
Offsets: 0x0800–0x08A0 (38 registers)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
Figure 20-12. Port GPIO Pad Data Input Register 0–3 (GPDI0_3)
Table 20-15. GPDI0_3 field descriptions
Field
PDI[x]
Description
Pad Data In
This bit stores the value of the external GPIO pad associated with this register.
0 Value of the data in signal for the corresponding GPIO pad is logic low
1 Value of the data in signal for the corresponding GPIO pad is logic high
20.5.3.12 Parallel GPIO Pad Data Out Registers (PGPDO0 – PGPDO4)
MPC5606BK devices ports are constructed such that they contain 16 GPIO pins, for example
PortA[0..15]. Parallel port registers for input (PGPDI) and output (PGPDO) are provided to allow a
complete port to be written or read in one operation, dependent on the individual pad configuration.
Writing a parallel PGPDO register directly sets the associated GPDO register bits. There is also a masked
parallel port output register allowing the user to determine which pins within a port are written.
While very convenient and fast, this approach does have implications regarding current consumption for
the device power segment containing the port GPIO pads. Toggling several GPIO pins simultaneously can
significantly increase current consumption.
CAUTION
Caution must be taken to avoid exceeding maximum current thresholds
when toggling multiple GPIO pins simultaneously. Please see data sheet.
Table 20-16 shows the locations and structure of the PGPDOx registers.
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Table 20-16. PGPDO0 – PGPDO4 register map
Field
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Offset1 Register
0x0C00 PGPDO0
Port A
Port B
0x0C04 PGPDO1
Port C
Port D
0x0C08 PGPDO2
Port E
Port F
0x0C0C PGPDO3
Port G
Port H
0x0C10 PGPDO4
Port I
1
Port J
Reserved
SIU base address is 0xC3F9_0000. To calculate register address add offset to base address
It is important to note the bit ordering of the ports in the parallel port registers. The most significant bit of
the parallel port register corresponds to the least significant pin in the port.
For example in Table 20-16, the PGPDO0 register contains fields for Port A and Port B.
• Bit 0 is mapped to Port A[0], bit 1 is mapped to Port A[1] and so on, through bit 15, which is
mapped to Port A[15]
• Bit 16 is mapped to Port B[0], bit 17 is mapped to Port B[1] and so on, through bit 31, which is
mapped to Port B[15].
20.5.3.13 Parallel GPIO Pad Data In Registers (PGPDI0 – PGPDI4)
The SIU_PGPDI registers are similar in operation to the PGPDIO registers, described in the previous
section (Section 20.5.3.12, Parallel GPIO Pad Data Out Registers (PGPDO0 – PGPDO4)) but they are
used to read port pins simultaneously.
NOTE
The port pins to be read need to be configured as inputs but even if a single
pin within a port has IBE set, then you can still read that pin using the
parallel port register. However, this does mean you need to be very careful.
Reads of PGPDI registers are equivalent to reading the corresponding GPDI registers but significantly
faster since as many as two ports can be read simultaneously with a single 32-bit read operation.
Table 20-17 shows the locations and structure of the PGPDIx registers. Each 32-bit PGPDIx register
contains two 16-bit fields, each field containing the values for a separate port.
Table 20-17. PGPDI0 – PGPDI4 register map
Field
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Offset1 Register
0x0C40
PGPDI0
Port A
Port B
0x0C44
PGPDI1
Port C
Port D
0x0C48
PGPDI2
Port E
Port F
0x0C4C
PGPDI3
Port G
Port H
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Table 20-17. PGPDI0 – PGPDI4 register map (continued)
Field
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Offset1 Register
0x0C50
1
PGPDI4
Port I
Port J
Reserved
SIU base address is 0xC3F9_0000. To calculate register address add offset to base address
It is important to note the bit ordering of the ports in the parallel port registers. The most significant bit of
the parallel port register corresponds to the least significant pin in the port.
For example in Table 20-17, the PGPDI0 register contains fields for Port A and Port B.
• Bit 0 is mapped to Port A[0], bit 1 is mapped to Port A[1] and so on, through bit 15, which is
mapped to Port A[15]
• Bit 16 is mapped to Port B[0], bit 17 is mapped to Port B[1] and so on, through bit 31, which is
mapped to Port B[15].
20.5.3.14 Masked Parallel GPIO Pad Data Out Register (MPGPDO0–MPGPDO9)
The MPGPDOx registers are similar in operation to the PGPDOx ports described in Section 20.5.3.12,
Parallel GPIO Pad Data Out Registers (PGPDO0 – PGPDO4), but with two significant differences:
• The MPGPDOx registers support masked port-wide changes to the data out on the pads of the
respective port. Masking effectively allows selective bitwise writes to the full 16-bit port.
• Each 32-bit MPGPDOx register is associated to only one port.
NOTE
The MPGPDOx registers may only be accessed with 32-bit writes. 8-bit or
16-bit writes will not modify any bits in the register and will cause a transfer
error response by the module. Read accesses return 0.
Table 20-18 shows the locations and structure of the MPGPDOx registers. Each 32-bit MPGPDOx register
contains two 16-bit fields (MASKx and MPPDOx). The MASK field is a bitwise mask for its associated
port. The MPPDO0 field contains the data to be written to the port.
Table 20-18. MPGPDO0 – MPGPDO9 register map
Field
Register
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Offset1
0x0C80 MPGPDO0
MASK0 (Port A)
MPPDO0 (Port A)
0x0C84 MPGPDO1
MASK1 (Port B)
MPPDO1 (Port B)
0x0C88 MPGPDO2
MASK2 (Port C)
MPPDO2 (Port C)
0x0C8C MPGPDO3
MASK3 (Port D)
MPPDO3 (Port D)
0x0C90 MPGPDO4
MASK4 (Port E)
MPPDO4 (Port E)
0x0C94 MPGPDO5
MASK5 (Port F)
MPPDO5 (Port F)
0x0C98 MPGPDO6
MASK6 (Port G)
MPPDO6 (Port G)
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Chapter 20 System Integration Unit Lite (SIUL)
Table 20-18. MPGPDO0 – MPGPDO9 register map (continued)
Field
Register
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Offset1
0x0C9C MPGPDO7
MASK7 (Port H)
MPPDO7 (Port H)
0x0CA0 MPGPDO8
MASK8 (Port I)
MPPDO8 (Port I)
0x0CAF MPGPDO9
1
MASK9
(Port J)
Reserved
MPPDO9
(Port J)
Reserved
SIU base address is 0xC3F9_0000. To calculate register address add offset to base address
It is important to note the bit ordering of the ports in the parallel port registers. The most significant bit of
the parallel port register corresponds to the least significant pin in the port.
For example in Table 20-18, the MPGPDO0 register contains field MASK0, which is the bitwise mask for
Port A and field MPPDO0, which contains data to be written to Port A.
• MPGPDO0[0] is the mask bit for Port A[0], MPGPDO0[1] is the mask bit for Port A[1] and so on,
through MPGPDO0[15], which is the mask bit for Port A[15]
• MPGPDO0[16] is the data bit mapped to Port A[0], MPGPDO0[17] is mapped to Port A[1] and so
on, through MPGPDO0[31], which is mapped to Port A[15].
Table 20-19. MPGPDO0..MPGPDO9 field descriptions
Field
Description
Mask Field
Each bit corresponds to one data bit in the MPPDOx register at the same bit location.
0 Associated bit value in the MPPDOxfield is ignored
1 Associated bit value in the MPPDOx field is written
MASKx
[15:0]
MPPDOx
[15:0]
Masked Parallel Pad Data Out
Write the data register that stores the value to be driven on the pad in output mode.
Accesses to this register location are coherent with accesses to the bitwise GPIO Pad Data Output
Registers (GPDO0_3–GPDO148_151).
The x and bit index define which MPPDO register bit is equivalent to which PDO register bit
according to the following equation:
MPPDO[x][y] = PDO[(x * 16) + y]
CAUTION
Toggling several IOs at the same time can significantly increase the current
in a pad group. Caution must be taken to avoid exceeding maximum current
thresholds. Please see data sheet.
20.5.3.15 Interrupt Filter Maximum Counter Registers (IFMC0–IFMC23)
These registers are used to configure the filter counter associated with each digital glitch filter.
NOTE
For the pad transition to trigger an interrupt it must be steady for at least the
filter period.
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Chapter 20 System Integration Unit Lite (SIUL)
Offset: 0x1000–0x105C) (24 registers)
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
MAXCNTx
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 20-13. Interrupt Filter Maximum Counter Registers (IFMC0–IFMC23)
Table 20-20. IFMC field descriptions
Field
Description
MAXCNTx
Maximum Interrupt Filter Counter setting
Filter Period = T(CK) × MAXCNTx + n × T(CK)
Where (n can be 1 to 3)
MAXCNTx can be 0 to 15
T(CK): Prescaled Filter Clock Period, which is the FIRC clock prescaled to IFCP value
T(FIRC): Basic Filter Clock Period: 62.5 ns (fFIRC = 16 MHz)
20.5.3.16 Interrupt Filter Clock Prescaler Register (IFCPR)
This register is used to configure a clock prescaler that selects the clock for all digital filter counters in the
SIUL.
Offsets:0x1080
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
IFCP
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 20-14. Interrupt Filter Clock Prescaler Register (IFCPR)
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Chapter 20 System Integration Unit Lite (SIUL)
Table 20-21. IFCPR field descriptions
Field
IFCP
20.6
20.6.1
Description
Interrupt Filter Clock Prescaler setting
Prescaled Filter Clock Period = T(FIRC) × (IFCP + 1)
T(FIRC) is the fast internal RC oscillator period.
IFCP can be 0 to 15.
Functional description
Pad control
The SIUL controls the configuration and electrical characteristic of the device pads. It provides a
consistent interface for all pads, both on a by-port and a by-bit basis. The pad configuration registers
(PCRn, see Section 20.5.3.8, Pad Configuration Registers (PCR0–PCR148)) allow software control of the
static electrical characteristics of external pins with a single write. These are used to configure the
following pad features:
• Open drain output enable
• Slew rate control
• Pull control
• Pad assignment
• Control of analog path switches
• Safe mode behavior configuration
20.6.2
General purpose input and output pads (GPIO)
The SIUL manages as many as 149 GPIO pads organized as ports that can be accessed for data reads and
writes as 32-, 16-, or 8-bit1.
NOTE
Ports are organized as groups of 16 GPIO pads, with the exception of Port J,
which has 5. A 32-bit R/W operation accesses two ports simultaneously. A
16-bit operation accesses a full port and an 8-bit access either the upper or
lower byte of a port.
As shown in Figure 20-15, all port accesses are identical with each read or write being performed only at
a different location to access a different port width.
1.There are exceptions. Some pads, e.g., precision analog pads, are input only.
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Chapter 20 System Integration Unit Lite (SIUL)
23
31
SIUL Base+ 0x0C00
SIUL Base+
0x0C02
SIUL Base+
0x0C03
15
7
7
0
32-bit Access (2 ports)
7
15
0
SIUL Base+
0x0C00
16-bit Access (full port)
0
8-bit Access
(half port)
15
SIUL Base+
0x0C02
7
0
8-bit Access
(half port)
SIUL Base+
0x0C01
7
0
16-bit Access (full port)
7
0
8-bit Access
(half port)
SIUL Base+
0x0C00
7
0
8-bit Access
(half port)
Figure 20-15. Data Port example arrangement showing configuration for different port width accesses
The SIUL has separate data input (GPDIn_n, see Section 20.5.3.11, GPIO Pad Data Input Registers
(GPDI0_3–GPDI148_151)) and data output (GPDOn_n, see Section 20.5.3.10, GPIO Pad Data Output
Registers (GPDO0_3–GPDO148_151)) registers for all pads, allowing the possibility of reading back an
input or output value of a pad directly. This supports the ability to validate what is present on the pad rather
than simply confirming the value that was written to the data register by accessing the data input registers.
Data output registers allow an output pad to be driven high or low (with the option of push-pull or open
drain drive). Input registers are read-only and reflect the respective pad value.
When the pad is configured to use one of its alternate functions, the data input value reflects the respective
value of the pad. If a write operation is performed to the data output register for a pad configured as an
alternate function (non-GPIO), this write will not be reflected by the pad value until reconfigured to GPIO.
The allocation of what input function is connected to the pin is defined by the PSMI registers (PCRn, see
Section 20.5.3.9, Pad Selection for Multiplexed Inputs Registers (PSMI0_3–PSMI60_63)).
20.6.3
External interrupts
The SIUL supports 24 external interrupts, EIRQ0–EIRQ23. Mapping is shown for external interrupts to
pads in Chapter 4, Signal description.
The SIUL supports three interrupt vectors to the interrupt controller. Each vector interrupt has eight
external interrupts combined together with the presence of flag generating an interrupt for that vector if
enabled. All of the external interrupt pads within a single group have equal priority.
See Figure 20-16 for an overview of the external interrupt implementation.
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Chapter 20 System Integration Unit Lite (SIUL)
Interrupt
Controller
Interrupt
Vectors
IRQ_23_16
IRQ_15_08
OR
IRQ_07_00
OR
OR
IRE[23:0](1)
Interrupt enable
Glitch filter Prescaler
EIF[23:16]
EIF[15:8]
EIF[7:0]
IFCP[3:0]
Glitch filter Counter_n
Edge Detection
MAXCOUNT[x]
IRQ Glitch Filter enable
IFE[23:0]
Glitch Filter
Interrupt Edge Enable
Rising
IREE[23:0](1)
Falling
IFEE[23:0](1)
Pads
Figure 20-16. External interrupt pad diagram
3
20 interrupts in 100-pin LQFP.
Each interrupt can be enabled or disabled independently. This can be performed using the IRER. A pad
defined as an external interrupt can be configured to recognize interrupts with an active rising edge, an
active falling edge or both edges being active. A setting of having both edge events disabled is reserved
and should not be configured.
The active EIRQ edge is controlled through the configuration of the registers IREER and IFEER.
Each external interrupt supports an individual flag in the Interrupt Status Flag Register (ISR). The bits in
the ISR[EIF] field are cleared by writing a 1 to them; this prevents inadvertent overwriting of other flags
in the register.
20.7
Pin muxing
For pin muxing, please see Chapter 4, Signal description.
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Chapter 21 Memory Protection Unit (MPU)
Chapter 21
Memory Protection Unit (MPU)
21.1
Introduction
The Memory Protection Unit (MPU) provides hardware access control for all memory references
generated in the device. Using preprogrammed region descriptors that define memory spaces and their
associated access rights, the MPU concurrently monitors all system bus transactions and evaluates the
appropriateness of each transfer. Memory references that have sufficient access control rights are allowed
to complete, while references that are not mapped to any region descriptor or have insufficient rights are
terminated with a protection error response.
The MPU module provides the following capabilities:
• Support for 8 program-visible 128-bit (4-word) region descriptors
— Each region descriptor defines a modulo-32 byte space, aligned anywhere in memory
– Region sizes can vary from a minimum of 32 bytes to a maximum of 4 Gbytes
— Two types of access control permissions defined in single descriptor word
– Processors have separate {read, write, execute} attributes for supervisor and user accesses
– Non-processor masters have {read, write} attributes
— Hardware-assisted maintenance of the descriptor valid bit minimizes coherency issues
— Alternate programming model view of the access control permissions word
• Memory-mapped platform device
— Interface to three slave XBAR ports: flash controller, system SRAM controller and peripherals
bus
– Connections to the address phase address and attributes
– Typical location is immediately downstream of the platform’s crossbar switch
A simplified block diagram of the MPU module is shown in Figure 21-1.
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Chapter 21 Memory Protection Unit (MPU)
Platform
Core (z0hn2p)
s0
PFlash
m0
m1
m2
XBAR
MPU
s2
PRAM
s7
PBRIDGE0
eDMA
Figure 21-1. MPU block diagram
21.2
Features
The Memory Protection Unit implements a two-dimensional hardware array of memory region descriptors
and the crossbar slave XBAR ports to continuously monitor the legality of every memory reference
generated by each bus master in the system. The feature set includes:
• Support for eight memory region descriptors, each 128 bits in size
— Specification of start and end addresses provide granularity for region sizes from 32 bytes to
4 GB
— Access control definitions: two bus masters (processor cores) support the traditional {read,
write, execute} permissions with independent definitions for supervisor and user mode
accesses
— Automatic hardware maintenance of the region descriptor valid bit removes issues associated
with maintaining a coherent image of the descriptor
— Alternate memory view of the access control word for each descriptor provides an efficient
mechanism to dynamically alter only the access rights of a descriptor
— For overlapping region descriptors, priority is given to permission granting over access
denying as this approach provides more flexibility to system software. See Section 21.6.2,
Putting it all together and AHB error terminations, for details and Section 21.8, Application
information, for an example.
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Chapter 21 Memory Protection Unit (MPU)
•
•
21.3
Support for three XBAR slave port connections: flash controller, system SRAM controller and
peripherals bus:
— MPU hardware continuously monitors every XBAR slave port access using the
preprogrammed memory region descriptors.
— An access protection error is detected if a memory reference does not hit in any memory region
or the reference is flagged as illegal in all memory regions where it does hit. In the event of an
access error, the XBAR reference is terminated with an error response and the MPU inhibits
the bus cycle being sent to the targeted slave device.
— 64-bit error registers, one for each XBAR slave port, capture the last faulting address,
attributes, and detail information.
Global MPU enable/disable control bit provides a mechanism to easily load region descriptors
during system startup or allow complete access rights during debug with the module disabled.
Modes of operation
The MPU module does not support any special modes of operation. As a memory-mapped device located
on the platform’s high-speed system bus, it responds based strictly on the memory addresses of the
connected system buses. The peripheral bus is used to access the MPU’s programming model and the
memory protection functions are evaluated on a reference-by-reference basis using the addresses from the
XBAR system bus port(s).
Power dissipation is minimized when the MPU’s global enable/disable bit is cleared
(MPU_CESR[VLD] = 0).
21.4
External signal description
The MPU module does not include any external interface. The MPU’s internal interfaces include a
peripheral bus connection for accessing the programming model and multiple connections to the address
phase signals of the platform crossbar’s slave AHB ports. From a platform topology viewpoint, the MPU
module appears to be directly connected downstream from the crossbar switch with interfaces to the
XBAR slave ports.
21.5
Memory map and register description
The MPU module provides an IPS programming model mapped to an SPP-standard on-platform 16 KB
space. The programming model is partitioned into three groups: control/status registers, the data structure
containing the region descriptors and the alternate view of the region descriptor access control values.
The programming model can only be referenced using 32-bit (word) accesses. Attempted references using
different access sizes, to undefined (reserved) addresses, or with a non-supported access type (for example,
a write to a read-only register or a read of a write-only register) generate an IPS error termination.
Finally, the programming model allocates space for an MPU definition with 8 region descriptors and as
many as three XBAR slave ports, like flash controller, system SRAM controller and peripheral bus.
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Chapter 21 Memory Protection Unit (MPU)
21.5.1
Memory map
The MPU programming model map is shown in Table 21-1.
Table 21-1. MPU memory map
Base address: 0xFFF1_1000
Address offset
0x000
0x004–0x00F
Register
MPU Control/Error Status Register (MPU_CESR)
Location
on page 379
Reserved
0x010
MPU Error Address Register, Slave Port 0 (MPU_EAR0)
on page 380
0x014
MPU Error Detail Register, Slave Port 0 (MPU_EDR0)
on page 381
0x018
MPU Error Address Register, Slave Port 1 (MPU_EAR1)
on page 380
0x01C
MPU Error Detail Register, Slave Port 1 (MPU_EDR1)
on page 381
0x020
MPU Error Address Register, Slave Port 2 (MPU_EAR2)
on page 380
0x024
MPU Error Detail Register, Slave Port 2 (MPU_EDR2)
on page 381
0x028–0x3FF
Reserved
0x400
MPU Region Descriptor 0 (MPU_RGD0)
on page 382
0x410
MPU Region Descriptor 1 (MPU_RGD1)
on page 382
0x420
MPU Region Descriptor 2 (MPU_RGD2)
on page 382
0x430
MPU Region Descriptor 3 (MPU_RGD3)
on page 382
0x440
MPU Region Descriptor 4 (MPU_RGD4)
on page 382
0x450
MPU Region Descriptor 5 (MPU_RGD5)
on page 382
0x460
MPU Region Descriptor 6 (MPU_RGD6)
on page 382
0x470
MPU Region Descriptor 7 (MPU_RGD7)
on page 382
0x480–0x7FF
Reserved
0x800
MPU RGD Alternate Access Control 0 (MPU_RGDAAC0)
on page 387
0x804
MPU RGD Alternate Access Control 1 (MPU_RGDAAC1)
on page 387
0x808
MPU RGD Alternate Access Control 2 (MPU_RGDAAC2)
on page 387
0x80C
MPU RGD Alternate Access Control 3 (MPU_RGDAAC3)
on page 387
0x810
MPU RGD Alternate Access Control 4 (MPU_RGDAAC4)
on page 387
0x814
MPU RGD Alternate Access Control 5 (MPU_RGDAAC5)
on page 387
0x818
MPU RGD Alternate Access Control 6 (MPU_RGDAAC6)
on page 387
0x81C
MPU RGD Alternate Access Control 7 (MPU_RGDAAC7)
on page 387
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Chapter 21 Memory Protection Unit (MPU)
21.5.2
Register description
21.5.2.1
MPU Control/Error Status Register (MPU_CESR)
The MPU_CESR provides one byte of error status plus three bytes of configuration information. A global
MPU enable/disable bit is also included in this register.
Offset: 0x000
Access: Read/Partial Write
0
R
2
SPERR[0:2]
W w1c
Reset
1
3
4
5
6
7
8
9
10
11
0
0
0
0
0
1
0
0
0
12
13
14
15
HRL
w1c
w1c
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
NSP
NRGD
VLD
W
Reset
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
Figure 21-2. MPU Control/Error Status Register (MPU_CESR)
Table 21-2. MPU_CESR field descriptions
Field
Description
SPERRn
Slave Port n Error, where the slave port number matches the bit number. See Table 21-3.
Each bit in this field represents a flag maintained by the MPU for signaling the presence of a captured
error contained in the MPU_EARn and MPU_EDRn registers. The individual bit is set when the
hardware detects an error and records the faulting address and attributes. It is cleared when the
corresponding bit is written as a logical one. If another error is captured at the exact same cycle as a
write of a logical one, this flag remains set. A “find first one” instruction (or equivalent) can be used to
detect the presence of a captured error.
0 The corresponding MPU_EARn/MPU_EDRn registers do not contain a captured error.
1 The corresponding MPU_EARn/MPU_EDRn registers do contain a captured error.
HRL
Hardware Revision Level
This field specifies the MPU’s hardware and definition revision level. It can be read by software to
determine the functional definition of the module.
NSP
Number of Slave Ports
This field specifies the number of slave ports [1–8] connected to the MPU.
NRGD
Number of Region Descriptors
This field specifies the number of region descriptors implemented in the MPU. The defined encodings
include:
0000 8 region descriptors
0001 12 region descriptors
0010 16 region descriptors
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Chapter 21 Memory Protection Unit (MPU)
Table 21-2. MPU_CESR field descriptions (continued)
Field
Description
VLD
Valid
This bit provides a global enable/disable for the MPU.
0 The MPU is disabled.
1 The MPU is enabled.
While the MPU is disabled, all accesses from all bus masters are allowed.
Table 21-3. SPERR implementation
SPERR bit
Corresponding port
SPERR[0]
Flash memory controller slave port
SPERR[1]
System RAM controller slave port
SPERR[2]
IPS peripheral bus slave port
21.5.2.2
MPU Error Address Register, Slave Port n (MPU_EARn)
When the MPU detects an access error on slave port n, the 32-bit reference address is captured in this
read-only register and the corresponding bit in the MPU_CESR[SPERR] field set. Additional information
about the faulting access is captured in the corresponding MPU_EDRn register at the same time. Note this
register and the corresponding MPU_EDRn register contain the most recent access error; there are no
hardware interlocks with the MPU_CESR[SPERR] field as the error registers are always loaded upon the
occurrence of each protection violation.
Offsets: 0x010–0x020 (3 registers)
0
1
2
3
Access: Read
4
5
6
R
7
8
9
10
11
12
13
14
15
EADDR [31:16]
W
Reset
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
–
–
–
–
–
–
–
R
EADDR [15:0]
W
Reset
–
–
–
–
–
–
–
–
–
Figure 21-3. MPU Error Address Register, Slave Port n (MPU_EARn)
Table 21-4. MPU_EARn field descriptions
Field
EADDR
Description
Error Address
This field is the reference address from slave port n that generated the access error.
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Chapter 21 Memory Protection Unit (MPU)
21.5.2.3
MPU Error Detail Register, Slave Port n (MPU_EDRn)
When the MPU detects an access error on slave port n, 32 bits of error detail are captured in this read-only
register and the corresponding bit in the MPU_CESR[SPERR] field set. Information on the faulting
address is captured in the corresponding MPU_EARn register at the same time. Note that this register and
the corresponding MPU_EARn register contain the most recent access error; there are no hardware
interlocks with the MPU_CESR[SPERR] field as the error registers are always loaded upon the occurrence
of each protection violation.
Offsets: 0x014–0x024 (3 registers)
0
1
2
R
Access: Read
3
4
5
6
7
EACD
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
W
Reset
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
EPID
EMN
EATTR
ERW
W
Reset
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Figure 21-4. MPU Error Detail Register, Slave Port n (MPU_EDRn)
Table 21-5. MPU_EDRn field descriptions
Field
EACD
Description
Error Access Control Detail
This field implements one bit per region descriptor and is an indication of the region descriptor hit
logically ANDed with the access error indication. The MPU performs a reference-by-reference
evaluation to determine the presence/absence of an access error. When an error is detected, the
hit-qualified access control vector is captured in this field.
If the MPU_EDRn register contains a captured error and the EACD field is all zeroes, this signals an
access that did not hit in any region descriptor. All non-zero EACD values signal references that hit in
a region descriptor(s), but failed due to a protection error as defined by the specific set bits. If only a
single EACD bit is set, then the protection error was caused by a single non-overlapping region
descriptor. If two or more EACD bits are set, then the protection error was caused in an overlapping set
of region descriptors.
EPID
Error Process Identification
This field records the process identifier of the faulting reference. The process identifier is typically driven
only by processor cores; for other bus masters, this field is cleared.
EMN
Error Master Number
This field records the logical master number of the faulting reference. This field is used to determine
the bus master that generated the access error.
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Table 21-5. MPU_EDRn field descriptions (continued)
Field
Description
EATTR
Error Attributes
This field records attribute information about the faulting reference. The supported encodings are
defined as:
000 User mode, instruction access
001 User mode, data access
010 Supervisor mode, instruction access
011 Supervisor mode, data access
All other encodings are reserved. For non-core bus masters, the access attribute information is typically
wired to supervisor, data (0b011).
ERW
21.5.2.4
Error Read/Write
This field signals the access type (read, write) of the faulting reference.
0 Read
1 Write
MPU Region Descriptor n (MPU_RGDn)
Each 128-bit (16-byte) region descriptor specifies a given memory space and the access attributes
associated with that space. The descriptor definition is the very essence of the operation of the Memory
Protection Unit.
The region descriptors are organized sequentially in the MPU’s programming model and each of the four
32-bit words are detailed in the subsequent sections.
21.5.2.4.1
MPU Region Descriptor n, Word 0 (MPU_RGDn.Word0)
The first word of the MPU region descriptor defines the 0-modulo-32 byte start address of the memory
region. Writes to this word clear the region descriptor’s valid bit (see Section 21.5.2.4.4, MPU Region
Descriptor n, Word 3 (MPU_RGDn.Word3) for more information).
Offset: 0x400 + (16 × n) + 0x0 (MPU_RGDn.Word0)
0
1
2
3
4
5
6
R
Access: Read/write
7
8
9
10
11
12
13
14
15
SRTADDR[26:11]
W
Reset
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
R
SRTADDR[10:0]
W
Reset
–
–
–
–
–
–
–
–
–
–
–
Figure 21-5. MPU Region Descriptor, Word 0 Register (MPU_RGDn.Word0)
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Table 21-6. MPU_RGDn.Word0 field descriptions
Field
Description
SRTADDR
Start Address
This field defines the most significant bits of the 0-modulo-32 byte start address of the memory
region.
21.5.2.4.2
MPU Region Descriptor n, Word 1 (MPU_RGDn.Word1)
The second word of the MPU region descriptor defines the 31-modulo-32 byte end address of the memory
region. Writes to this word clear the region descriptor’s valid bit (see Section 21.5.2.4.4, MPU Region
Descriptor n, Word 3 (MPU_RGDn.Word3) for more information).
Offset: 0x400 + (16 × n) + 0x4 (MPU_RGDn.Word1)
0
1
2
3
4
5
6
Access: Read/write
7
8
9
10
11
12
13
14
15
R
ENDADDR[26:11]
W
Reset
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1
1
1
1
1
1
1
1
1
1
R
ENDADDR[10:0]
W
Reset
–
–
–
–
–
–
–
–
–
–
–
Figure 21-6. MPU Region Descriptor, Word 1 Register (MPU_RGDn.Word1)
Table 21-7. MPU_RGDn.Word1 field descriptions
Field
Description
ENDADDR
End Address
This field defines the most significant bits of the 31-modulo-32 byte end address of the memory
region. There are no hardware checks to verify that ENDADDR  SRTADDR; it is software’s
responsibility to properly load these region descriptor fields.
21.5.2.4.3
MPU Region Descriptor n, Word 2 (MPU_RGDn.Word2)
The third word of the MPU region descriptor defines the access control rights of the memory region. The
access control privileges are dependent on two broad classifications of bus masters. Bus masters 0–3 are
typically reserved for processor cores and the corresponding access control is a 6-bit field defining
separate privilege rights for user and supervisor mode accesses as well as the optional inclusion of a
process identification field within the definition. Bus masters 4–7 are typically reserved for data movement
engines, and their capabilities are limited to separate read and write permissions. For these fields, the bus
master number refers to the logical master number defined as the XBAR hmaster[3:0] signal.
For the processor privilege rights, there are three flags associated with this function: {read, write, execute}.
In this context, these flags follow the traditional definition:
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•
•
•
Read (r) permission refers to the ability to access the referenced memory address using an operand
(data) fetch.
Write (w) permission refers to the ability to update the referenced memory address using a store
(data) instruction.
Execute (x) permission refers to the ability to read the referenced memory address using an
instruction fetch.
The evaluation logic defines the processor access type based on multiple AHB signals, as hwrite and
hprot[1:0].
For non-processor data movement engines (bus masters 4–7), the evaluation logic simply uses hwrite to
determine if the access is a read or write.
Writes to this word clear the region descriptor’s valid bit (see Section 21.5.2.4.4, MPU Region Descriptor
n, Word 3 (MPU_RGDn.Word3) for more information). Since it is also expected that system software may
adjust only the access controls within a region descriptor (MPU_RGDn.Word2) as different tasks execute,
an alternate programming view of this 32-bit entity is provided. If only the access controls are being
updated, this operation should be performed by writing to MPU_RGDAACn (Alternate Access Control n)
as stores to these locations do not affect the descriptor’s valid bit.
3
4
5
6
7
8
W
M6RE
M6WE
M5RE
M5WE
M4RE
M4WE
M3PE
Reset
–
–
–
–
–
–
–
–
–
–
–
–
–
–
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
M0PE
R
W
Reset
M2UM
–
–
–
0
0
0
0
0
10
11
M3SM
0
0
–
12
13
M3UM
M0SM
–
–
14
15
M2SM[1]
2
R
9
M2PE
1
M2SM[0]
0
M7WE
Access: R/W
M7RE
Offset: 0x400 + (16 × n) + 0x8 (MPU_RGDn.Word2)
–
–
M0UM
–
–
–
Figure 21-7. MPU Region Descriptor, Word 2 Register (MPU_RGDn.Word2)
Table 21-8. MPU_RGDn.Word2 field descriptions
Field
Description
M7RE
Bus master 7 read enable
If set, this flag allows bus master 7 to perform read operations. If cleared, any attempted read by bus
master 7 terminates with an access error and the read is not performed.
M7WE
Bus master 7 write enable
If set, this flag allows bus master 7 to perform write operations. If cleared, any attempted write by bus
master 7 terminates with an access error and the write is not performed.
M6RE
Bus master 6 read enable
If set, this flag allows bus master 6 to perform read operations. If cleared, any attempted read by bus
master 6 terminates with an access error and the read is not performed.
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Table 21-8. MPU_RGDn.Word2 field descriptions (continued)
Field
Description
M6WE
Bus master 6 write enable
If set, this flag allows bus master 6 to perform write operations. If cleared, any attempted write by bus
master 6 terminates with an access error and the write is not performed.
M5RE
Bus master 5 read enable
If set, this flag allows bus master 5 to perform read operations. If cleared, any attempted read by bus
master 5 terminates with an access error and the read is not performed.
M5WE
Bus master 5 write enable
If set, this flag allows bus master 5 to perform write operations. If cleared, any attempted write by bus
master 5 terminates with an access error and the write is not performed.
M4RE
Bus master 4 read enable
If set, this flag allows bus master 4 to perform read operations. If cleared, any attempted read by bus
master 4 terminates with an access error and the read is not performed.
M4WE
Bus master 4 write enable
If set, this flag allows bus master 4 to perform write operations. If cleared, any attempted write by bus
master 4 terminates with an access error and the write is not performed.
M3PE
Bus master 3 process identifier enable
If set, this flag specifies that the process identifier and mask (defined in MPU_RGDn.Word3) are to be
included in the region hit evaluation. If cleared, then the region hit evaluation does not include the
process identifier.
M3SM
Bus master 3 supervisor mode access control
This field defines the access controls for bus master 3 when operating in supervisor mode. The M3SM
field is defined as:
00 r, w, x = read, write and execute allowed
01 r, –, x = read and execute allowed, but no write
10 r, w, – = read and write allowed, but no execute
11 Same access controls as that defined by M3UM for user mode
M3UM
Bus master 3 user mode access control
This field defines the access controls for bus master 3 when operating in user mode. The M3UM field
consists of three independent bits, enabling read, write and execute permissions: {r,w,x}. If set, the bit
allows the given access type to occur; if cleared, an attempted access of that mode may be terminated
with an access error (if not allowed by any other descriptor) and the access not performed.
M2PE
Bus master 2 process identifier enable
If set, this flag specifies that the process identifier and mask (defined in MPU_RGDn.Word3) are to be
included in the region hit evaluation. If cleared, then the region hit evaluation does not include the
process identifier.
M2SM
Bus master 2 supervisor mode access control
This field defines the access controls for bus master 2 when operating in supervisor mode. The M2SM
field is defined as:
00 r, w, = read and write allowed
01 r = read allowed, but no write
10 r, w = read and write allowed
11 Same access controls as that defined by M2UM for user mode
M2UM
Bus master 2 user mode access control
This field defines the access controls for bus master 2 when operating in user mode. The M2UM field
consists of two independent bits, enabling read and write permissions: {r,w}. If set, the bit allows the
given access type to occur; if cleared, an attempted access of that mode may be terminated with an
access error (if not allowed by any other descriptor) and the access not performed.
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Table 21-8. MPU_RGDn.Word2 field descriptions (continued)
Field
Description
M0PE
Bus master 0 process identifier enable
If set, this flag specifies that the process identifier and mask (defined in MPU_RGDn.Word3) are to be
included in the region hit evaluation. If cleared, then the region hit evaluation does not include the
process identifier.
M0SM
Bus master 0 supervisor mode access control
This field defines the access controls for bus master 0 when operating in supervisor mode. The M0SM
field is defined as:
00 r, w, x = read, write and execute allowed
01 r, –, x = read and execute allowed, but no write
10 r, w, – = read and write allowed, but no execute
11 Same access controls as that defined by M0UM for user mode
M0UM
Bus master 0 user mode access control
This field defines the access controls for bus master 0 when operating in user mode. The M0UM field
consists of three independent bits, enabling read, write and execute permissions: {r,w,x}. If set, the bit
allows the given access type to occur; if cleared, an attempted access of that mode may be terminated
with an access error (if not allowed by any other descriptor) and the access not performed.
21.5.2.4.4
MPU Region Descriptor n, Word 3 (MPU_RGDn.Word3)
The fourth word of the MPU region descriptor contains the optional process identifier and mask, plus the
region descriptor’s valid bit.
Since the region descriptor is a 128-bit entity, there are potential coherency issues as this structure is being
updated since multiple writes are required to update the entire descriptor. Accordingly, the MPU hardware
assists in the operation of the descriptor valid bit to prevent incoherent region descriptors from generating
spurious access errors. In particular, it is expected that a complete update of a region descriptor is typically
done with sequential writes to MPU_RGDn.Word0, then MPU_RGDn.Word1,... and finally
MPU_RGDn.Word3. The MPU hardware automatically clears the valid bit on any writes to words {0,1,2}
of the descriptor. Writes to this word set/clear the valid bit in a normal manner.
Since it is also expected that system software may adjust only the access controls within a region descriptor
(MPU_RGDn.Word2) as different tasks execute, an alternate programming view of this 32-bit entity is
provided. If only the access controls are being updated, this operation should be performed by writing to
MPU_RGDAACn (Alternate Access Control n) as stores to these locations do not affect the descriptor’s
valid bit.
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Offset: 0x400 + (16 × n) + 0xC (MPU_RGDn.Word3)
0
1
2
3
4
5
6
Access: Read/write
7
8
9
10
11
12
13
14
15
R
PID
PIDMASK
W
Reset
R
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VLD
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 21-8. MPU Region Descriptor, Word 3 Register (MPU_RGDn.Word3)
Table 21-9. MPU_RGDn.Word3 field descriptions
Field
Description
PID
Process Identifier
This field specifies that the optional process identifier is to be included in the determination of whether
the current access hits in the region descriptor. This field is combined with the PIDMASK and included
in the region hit determination if MPU_RGDn.Word2[MxPE] is set.
PIDMASK
Process Identifier Mask
This field provides a masking capability so that multiple process identifiers can be included as part of
the region hit determination. If a bit in the PIDMASK is set, then the corresponding bit of the PID is
ignored in the comparison. This field is combined with the PID and included in the region hit
determination if MPU_RGDn.Word2[MxPE] is set. For more information on the handling of the PID
and PIDMASK, see Section 21.6.1.1, Access evaluation – Hit determination.
VLD
Valid
This bit signals the region descriptor is valid. Any write to MPU_RGDn.Word{0,1,2} clears this bit,
while a write to MPU_RGDn.Word3 sets or clears this bit depending on bit 31 of the write operand.
0 Region descriptor is invalid
1 Region descriptor is valid
21.5.2.5
MPU Region Descriptor Alternate Access Control n (MPU_RGDAACn)
As noted in Section 21.5.2.4.3, MPU Region Descriptor n, Word 2 (MPU_RGDn.Word2), it is expected
that since system software may adjust only the access controls within a region descriptor
(MPU_RGDn.Word2) as different tasks execute, an alternate programming view of this 32-bit entity is
desired. If only the access controls are being updated, this operation should be performed by writing to
MPU_RGDAACn (Alternate Access Control n) as stores to these locations do not affect the descriptor’s
valid bit.
The memory address therefore provides an alternate location for updating MPU_RGDn.Word2.
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3
4
5
6
7
8
W
M6RE
M6WE
M5RE
M5WE
M4RE
M4WE
M3PE
Reset
–
–
–
–
–
–
–
–
–
–
–
–
–
–
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
M0PE
R
W
Reset
–
–
0
0
0
0
0
0
11
M3SM
M2UM
–
10
0
–
12
13
M3UM
M0SM
–
–
14
15
M2SM[1]
2
R
9
M2PE
1
M2SM[0]
0
M7WE
Access: Read/write
M7RE
Offset: 0x800 + (4 × n) (MPU_RGDAACn)
–
–
M0UM
–
–
–
Figure 21-9. MPU RGD Alternate Access Control n (MPU_RGDAACn)
Since the MPU_RGDAACn register is simply another memory mapping for MPU_RGDn.Word2, the field
definitions shown in Table 21-10 are identical to those presented in Table 21-8.
Table 21-10. MPU_RGDAACn field descriptions
Field
Description
M7RE
Bus master 7 read enable.
If set, this flag allows bus master 7 to perform read operations. If cleared, any attempted read by bus
master 7 terminates with an access error and the read is not performed.
M7WE
Bus master 7 write enable
If set, this flag allows bus master 7 to perform write operations. If cleared, any attempted write by bus
master 7 terminates with an access error and the write is not performed.
M6RE
Bus master 6 read enable
If set, this flag allows bus master 6 to perform read operations. If cleared, any attempted read by bus
master 6 terminates with an access error and the read is not performed.
M6WE
Bus master 6 write enable
If set, this flag allows bus master 6 to perform write operations. If cleared, any attempted write by bus
master 6 terminates with an access error and the write is not performed.
M5RE
Bus master 5 read enable
If set, this flag allows bus master 5 to perform read operations. If cleared, any attempted read by bus
master 5 terminates with an access error and the read is not performed.
M5WE
Bus master 5 write enable
If set, this flag allows bus master 5 to perform write operations. If cleared, any attempted write by bus
master 5 terminates with an access error and the write is not performed.
M4RE
Bus master 4 read enable
If set, this flag allows bus master 4 to perform read operations. If cleared, any attempted read by bus
master 4 terminates with an access error and the read is not performed.
M4WE
Bus master 4 write enable
If set, this flag allows bus master 4 to perform write operations. If cleared, any attempted write by bus
master 4 terminates with an access error and the write is not performed.
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Table 21-10. MPU_RGDAACn field descriptions (continued)
Field
Description
M3PE
Bus master 3 process identifier enable
If set, this flag specifies that the process identifier and mask (defined in MPU_RGDn.Word3) are to be
included in the region hit evaluation. If cleared, then the region hit evaluation does not include the
process identifier.
M3SM
Bus master 3 supervisor mode access control
This field defines the access controls for bus master 3 when operating in supervisor mode. The M3SM
field is defined as:
00 r, w, x = read, write and execute allowed
01 r, –, x = read and execute allowed, but no write
10 r, w, – = read and write allowed, but no execute
11 Same access controls as that defined by M3UM for user mode
M3UM
Bus master 3 user mode access control
This field defines the access controls for bus master 3 when operating in user mode. The M3UM field
consists of three independent bits, enabling read, write and execute permissions: {r,w,x}. If set, the bit
allows the given access type to occur; if cleared, an attempted access of that mode may be terminated
with an access error (if not allowed by any other descriptor) and the access not performed.
M2PE
Bus master 2 process identifier enable
If set, this flag specifies that the process identifier and mask (defined in MPU_RGDn.Word3) are to be
included in the region hit evaluation. If cleared, then the region hit evaluation does not include the
process identifier.
M2SM
Bus master 2 supervisor mode access control
This field defines the access controls for bus master 2 when operating in supervisor mode. The M2SM
field is defined as:
00 r, w, = read and write allowed
01 r = read allowed, but no write
10 r, w = read and write allowed
11 Same access controls as that defined by M2UM for user mode
M2UM
Bus master 2 user mode access control
This field defines the access controls for bus master 2 when operating in user mode. The M2UM field
consists of three independent bits, enabling read, write and execute permissions: {r,w,x}. If set, the bit
allows the given access type to occur; if cleared, an attempted access of that mode may be terminated
with an access error (if not allowed by any other descriptor) and the access not performed.
M0PE
Bus master 0 process identifier enable
If set, this flag specifies that the process identifier and mask (defined in MPU_RGDn.Word3) are to be
included in the region hit evaluation. If cleared, then the region hit evaluation does not include the
process identifier.
M0SM
Bus master 0 supervisor mode access control
This field defines the access controls for bus master 0 when operating in supervisor mode. The M0SM
field is defined as:
00 r, w, x = read, write and execute allowed
01 r, –, x = read and execute allowed, but no write
10 r, w, – = read and write allowed, but no execute
11 Same access controls as that defined by M0UM for user mode
M0UM
Bus master 0 user mode access control
This field defines the access controls for bus master 0 when operating in user mode. The M0UM field
consists of three independent bits, enabling read, write and execute permissions: {r,w,x}. If set, the bit
allows the given access type to occur; if cleared, an attempted access of that mode may be terminated
with an access error (if not allowed by any other descriptor) and the access not performed.
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Chapter 21 Memory Protection Unit (MPU)
21.6
Functional description
In this section, the functional operation of the MPU is detailed. In particular, subsequent sections discuss
the operation of the access evaluation macro as well as the handling of error-terminated bus cycles.
21.6.1
Access evaluation macro
As previously discussed, the basic operation of the MPU is performed in the access evaluation macro, a
hardware structure replicated in the two-dimensional connection matrix. As shown in Figure 21-10, the
access evaluation macro inputs the system bus address phase signals and the contents of a region descriptor
(RGDn) and performs two major functions: region hit determination (hit_b) and detection of an access
protection violation (error).
System bus
address phase
RGDn
start
end
r,w,x


error
hit_b
>
hit & error
>
hit_b | error
Figure 21-10. MPU access evaluation macro
Figure 21-10 is not intended to be a schematic of the actual access evaluation macro, but rather a
generalized block diagram showing the major functions included in this logic block.
21.6.1.1
Access evaluation – Hit determination
To evaluate the region hit determination, the MPU uses two magnitude comparators in conjunction with
the contents of a region descriptor: the current access must be included between the region's start and end
addresses and simultaneously the region's valid bit must be active.
Recall there are no hardware checks to verify that region's end address is greater then region's start address,
and it is software’s responsibility to properly load appropriate values into these fields of the region
descriptor.
In addition to this, the optional process identifier is examined against the region descriptor’s PID and
PIDMASK fields. In order to generate the pid_hit indication: the current PID with its PIDMASK must be
equal to the region's PID with its PIDMASK. Also the process identifier enable is take into account in this
comparison so that the MPU forces the pid_hit term to be asserted in the case of AHB bus master doesn't
provide its process identifier.
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21.6.1.2
Access evaluation – Privilege violation determination
While the access evaluation macro is making the region hit determination, the logic is also evaluating if
the current access is allowed by the permissions defined in the region descriptor. The protection violation
logic then evaluates the access against the effective permissions using the specification shown in
Table 21-11.
Table 21-11. Protection violation definition
Inputs
Output
Description
eff_rgd[r]
eff_rgd[w]
eff_rgd[x]
Protection violation?
inst fetch read
—
—
0
yes, no x permission
inst fetch read
—
—
1
no, access is allowed
data read
0
—
—
yes, no r permission
data read
1
—
—
no, access is allowed
data write
—
0
—
yes, no w permission
data write
—
1
—
no, access is allowed
As shown in Figure 21-10, the output of the protection violation logic is the error signal.
The access evaluation macro then uses the hit_b and error signals to form two outputs. The combined
(hit_b | error) signal is used to signal the current access is not allowed and (~hit_b & error) is used as the
input to MPU_EDRn (error detail register) in the event of an error.
21.6.2
Putting it all together and AHB error terminations
For each XBAR slave port being monitored, the MPU performs a reduction-AND of all the individual
(hit_b | error) terms from each access evaluation macro. This expression then terminates the bus cycle with
an error and reports a protection error for three conditions:
• If the access does not hit in any region descriptor, a protection error is reported.
• If the access hits in a single region descriptor and that region signals a protection violation, then a
protection error is reported.
• If the access hits in multiple (overlapping) regions and all regions signal protection violations, then
a protection error is reported.
The third condition reflects that priority is given to permission granting over access denying for
overlapping regions as this approach provides more flexibility to system software in region descriptor
assignments. For an example of the use of overlapping region descriptors, see Section 21.8, Application
information.
In event of a protection error, the MPU requires two distinct actions:
• Intercepting the error during the address phase (first cycle out of two) and cancelling the
transaction before it is seen by the slave device
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Chapter 21 Memory Protection Unit (MPU)
•
Performing the required logic functions to force the standard 2-cycle AHB error response to
properly terminate the bus transaction and then providing the right values to the crossbar switch to
commit the transaction to other portions of the platform.
If, instead, the access is allowed, then the MPU simply passes all original signals to the slave device. In
this case, from a functionality point of view, the MPU is fully transparent.
21.7
Initialization information
The reset state of MPU_CESR[VLD] disables the entire module. Recall that while the MPU is disabled,
all accesses from all bus masters are allowed. This state also minimizes the power dissipation of the MPU.
The power dissipation of each access evaluation macro is minimized when the associated region descriptor
is marked as invalid or when MPU_CESR[VLD] = 0.
Typically the appropriate number of region descriptors (MPU_RGDn) is loaded at system startup,
including the setting of the MPU_RGDn.Word3[VLD] bits, before MPU_CESR[VLD] is set, enabling the
module. This approach allows all the loaded region descriptors to be enabled simultaneously. Recall if a
memory reference does not hit in any region descriptor, the attempted access is terminated with an error.
21.8
Application information
In an operational system, interfacing with the MPU can generally be classified into the following activities:
• Creation of a new memory region requires loading the appropriate region descriptor into an
available register location. When a new descriptor is loaded into a RGDn, it would typically be
performed using four 32-bit word writes. As discussed in Section 21.5.2.4.4, MPU Region
Descriptor n, Word 3 (MPU_RGDn.Word3), the hardware assists in the maintenance of the valid
bit, so if this approach is followed, there are no coherency issues associated with the multi-cycle
descriptor writes. Deletion/removal of an existing memory region is performed simply by clearing
MPU_RGDn.Word3[VLD].
• If only the access rights for an existing region descriptor need to change, a 32-bit write to the
alternate version of the access control word (MPU_RGDAACn) would typically be performed.
Recall writes to the region descriptor using this alternate access control location do not affect the
valid bit, so there are, by definition, no coherency issues involved with the update. The access
rights associated with the memory region switch instantaneously to the new value as the IPS write
completes.
• If the region’s start and end addresses are to be changed, this would typically be performed by
writing a minimum of three words of the region descriptor: MPU_RGDn.Word{0,1,3}, where the
writes to Word0 and Word1 redefine the start and end addresses, respectively, and the write to
Word3 re-enables the region descriptor valid bit. In many situations, all four words of the region
descriptor would be rewritten.
• Typically, references to the MPU’s programming model would be restricted to supervisor mode
accesses from a specific processor(s), so a region descriptor would be specifically allocated for this
purpose with attempted accesses from other masters or while in user mode terminated with an error.
When the MPU detects an access error, the current bus cycle is terminated with an error response, and
information on the faulting reference is captured in the MPU_EARn and MPU_EDRn registers. The
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Chapter 21 Memory Protection Unit (MPU)
error-terminated bus cycle typically initiates some type of error response in the originating bus master. For
example, the CPU errors generate a core exception, whereas the DMA errors generate a MPU (external)
interrupt. It is important to highlight that in case of DMA access violations, the core continues to run, but
if a core violation occurs, the system stops. In any event, the processor can retrieve the captured error
address and detail information by reading the MPU_E{A,D}Rn registers. Information on that error
registers contain captured fault data is signaled by MPU_CESR[SPERR].
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——— Communication modules ———
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Chapter 22 Inter-Integrated Circuit Bus Controller Module (I2C)
Chapter 22
Inter-Integrated Circuit Bus Controller Module (I2C)
22.1
22.1.1
Introduction
Overview
The Inter-Integrated Circuit (I2C or IIC) bus is a two wire bidirectional serial bus that provides a simple
and efficient method of data exchange between devices. It minimizes the number of external connections
to devices and does not require an external address decoder.
This bus is suitable for applications requiring occasional communications over a short distance between a
number of devices. It also provides flexibility, allowing additional devices to be connected to the bus for
further expansion and system development.
The interface is designed to operate as fast as 100 kbit/s in Standard Mode and 400 kbit/s in Fast Mode.
The device is capable of operating at higher baud rates, up to a maximum of module clock/20 with reduced
bus loading. Actual baud rate can be less than the programmed baud rate and is dependent on the SCL rise
time. SCL rise time is dependent on the external pullup resistor value and bus loading. The maximum
communication length and the number of devices that can be connected are limited by a maximum bus
capacitance of 400 pF.
22.1.2
Features
The I2C module has the following key features:
• Compatible with I2C Bus standard
• Multi-master operation
• Software programmable for one of 256 different serial clock frequencies
• Software selectable acknowledge bit
• Interrupt driven byte-by-byte data transfer
• Arbitration lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
• Start and stop signal generation/detection
• Repeated start signal generation
• Acknowledge bit generation/detection
• Bus busy detection
• Direct memory access
Features currently not supported:
• No support for general call address
• Not compliant to 10-bit addressing
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Chapter 22 Inter-Integrated Circuit Bus Controller Module (I2C)
22.1.3
Block diagram
The block diagram of the I2C module is shown in Figure 22-1.
I2C
Registers
Start
Stop
Arbitration
Control
Clock
Control
In/Out
Data
Shift
Register
Interrupt
bus_clock
SCL
SDA
Address
Compare
Figure 22-1. I2C block diagram
22.2
External signal description
The Inter-Integrated Circuit (I2C) module has two external pins, SCL and SDA.
22.2.1
SCL
This is the bidirectional Serial Clock Line (SCL) of the module, compatible with the I2C-Bus specification.
22.2.2
SDA
This is the bidirectional Serial Data line (SDA) of the module, compatible with the I2C-Bus specification.
22.3
22.3.1
Memory map and register description
Module memory map
The memory map for the I2C module is given below in Table 22-1. The total address for each register is
the sum of the base address for the I2C module and the address offset for each register.
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Chapter 22 Inter-Integrated Circuit Bus Controller Module (I2C)
Table 22-1. I2C memory map
Base address: 0xFFE3_0000
Address offset
Register
Location
0x0
I2C Bus Address Register (IBAD)
on page 399
0x1
I2C Bus Frequency Divider Register (IBFD)
on page 400
0x2
I2C Bus Control Register (IBCR)
on page 406
0x3
I2C Bus Status Register (IBSR)
on page 407
0x4
I2C Bus Data I/O Register (IBDR)
on page 408
0x5
I2C Bus Interrupt Config Register (IBIC)
on page 409
All registers are accessible via 8-, 16-, or 32-bit accesses. However, 16-bit accesses must be aligned to
16-bit boundaries, and 32-bit accesses must be aligned to 32-bit boundaries. As an example, the IBDF
register for the frequency divider is accessible by a 16-bit read/write to address Base + 0x000, but
performing a 16-bit access to Base + 0x001 is illegal.
I2C Bus Address Register (IBAD)
22.3.2
This register contains the address the I2C bus will respond to when addressed as a slave; note that it is not
the address sent on the bus during the address transfer.
Offset 0x0
Access: Read/write any time
7
6
5
4
3
2
1
R
0
0
ADR
W
Reset
0
0
0
0
0
0
0
0
Figure 22-2. I2C Bus Address Register (IBAD)
Table 22-2. IBAD field descriptions
Field
ADR
Description
Slave Address. Specific slave address to be used by the I2C Bus module.
Note: The default mode of I2C Bus is slave mode for an address match on the bus.
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Chapter 22 Inter-Integrated Circuit Bus Controller Module (I2C)
I2C Bus Frequency Divider Register (IBFD)
22.3.3
Offset 0x1
Access: Read/write any time
7
6
5
4
3
2
1
0
0
0
0
0
R
IBC
W
Reset
0
0
0
0
Figure 22-3. I2C Bus Frequency Divider Register (IBFD)
Table 22-3. IBFD field descriptions
Field
Description
IBC
I-Bus Clock Rate. This field is used to prescale the clock for bit rate selection. The bit clock generator is
implemented as a prescale divider. The IBC bits are decoded to give the Tap and Prescale values as
follows:
7–6 select the prescaled shift register (see Table 22-4)
5–3 select the prescaler divider (see Table 22-5)
2–0 select the shift register tap point (see Table 22-6)
Table 22-4. I-Bus multiplier factor
IBC7–6
MUL
00
01
01
02
10
04
11
RESERVED
Table 22-5. I-Bus prescaler divider values
IBC5–3
scl2start
(clocks)
scl2stop
(clocks)
scl2tap
(clocks)
tap2tap
(clocks)
000
2
7
4
1
001
2
7
4
2
010
2
9
6
4
011
6
9
6
8
100
14
17
14
16
101
30
33
30
32
110
62
65
62
64
111
126
129
126
128
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Chapter 22 Inter-Integrated Circuit Bus Controller Module (I2C)
Table 22-6. I-Bus tap and prescale values
IBC2–0
SCL Tap
(clocks)
SDA Tap
(clocks)
000
5
1
001
6
1
010
7
2
011
8
2
100
9
3
101
10
3
110
12
4
111
15
4
The number of clocks from the falling edge of SCL to the first tap (Tap[1]) is defined by the values shown
in the scl2tap column of Table 22-5. All subsequent tap points are separated by 2IBC5-3 as shown in the
tap2tap column in Table 22-5. The SCL Tap is used to generate the SCL period and the SDA Tap is used
to determine the delay from the falling edge of SCL to the change of state of SDA i.e. the SDA hold time.
SCL Divider
SCL
SDA
SDA Hold
Figure 22-4. SDA hold time
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Chapter 22 Inter-Integrated Circuit Bus Controller Module (I2C)
SDA
SCL Hold(stop)
SCL Hold(start)
SCL
START condition
STOP condition
Figure 22-5. SCL divider and SDA hold
The equation used to generate the divider values from the IBFD bits is:
SCL Divider = MUL × {2 × (scl2tap + [(SCL_Tap –1) × tap2tap] + 2)}
Eqn. 22-1
The SDA hold delay is equal to the CPU clock period multiplied by the SDA Hold value shown in
Table 22-7. The equation used to generate the SDA Hold value from the IBFD bits is:
SDA Hold = MUL × {scl2tap + [(SDA_Tap – 1) × tap2tap] + 3}
Eqn. 22-2
The equation for SCL Hold values to generate the start and stop conditions from the IBFD bits is:
SCL Hold(start) = MUL × [scl2start + (SCL_Tap – 1) × tap2tap]
Eqn. 22-3
SCL Hold(stop) = MUL × [scl2stop + (SCL_Tap – 1) × tap2tap]
Eqn. 22-4
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Chapter 22 Inter-Integrated Circuit Bus Controller Module (I2C)
MUL = 1
Table 22-7. I2C divider and hold values
IBC7–0
(hex)
SCL divider
(clocks)
SDA hold
(clocks)
SCL hold
(start)
SCL hold
(stop)
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
20
22
24
26
28
30
34
40
28
32
36
40
44
48
56
68
48
56
64
72
80
88
104
128
80
96
112
128
144
160
192
240
160
192
224
256
288
320
384
480
320
384
448
512
576
640
768
960
640
768
896
1024
1152
1280
1536
1920
1280
1536
1792
2048
2304
2560
3072
3840
7
7
8
8
9
9
10
10
7
7
9
9
11
11
13
13
9
9
13
13
17
17
21
21
9
9
17
17
25
25
33
33
17
17
33
33
49
49
65
65
33
33
65
65
97
97
129
129
65
65
129
129
193
193
257
257
129
129
257
257
385
385
513
513
6
7
8
9
10
11
13
16
10
12
14
16
18
20
24
30
18
22
26
30
34
38
46
58
38
46
54
62
70
78
94
118
78
94
110
126
142
158
190
238
158
190
222
254
286
318
382
478
318
382
446
510
574
638
766
958
638
766
894
1022
1150
1278
1534
1918
11
12
13
14
15
16
18
21
15
17
19
21
23
25
29
35
25
29
33
37
41
45
53
65
41
49
57
65
73
81
97
121
81
97
113
129
145
161
193
241
161
193
225
257
289
321
385
481
321
385
449
513
577
641
769
961
641
769
897
1025
1153
1281
1537
1921
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Chapter 22 Inter-Integrated Circuit Bus Controller Module (I2C)
MUL = 2
Table 22-7. I2C divider and hold values (continued)
IBC7–0
(hex)
SCL divider
(clocks)
SDA hold
(clocks)
SCL hold
(start)
SCL hold
(stop)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
40
44
48
52
56
60
68
80
56
64
72
80
88
96
112
136
96
112
128
144
160
176
208
256
160
192
224
256
288
320
384
480
320
384
448
512
576
640
768
960
640
768
896
1024
1152
1280
1536
1920
1280
1536
1792
2048
2304
2560
3072
3840
2560
3072
3584
4096
4608
5120
6144
7680
14
14
16
16
18
18
20
20
14
14
18
18
22
22
26
26
18
18
26
26
34
34
42
42
18
18
34
34
50
50
66
66
28
28
32
32
36
36
40
40
28
28
36
36
44
44
52
52
36
36
52
52
68
68
84
84
36
36
68
68
100
100
132
132
12
14
16
18
20
22
26
32
20
24
28
32
36
40
48
60
36
44
52
60
68
76
92
116
76
92
108
124
140
156
188
236
156
188
220
252
284
316
380
476
316
380
444
508
572
636
764
956
636
764
892
1020
1148
1276
1532
1916
1276
1532
1788
2044
2300
2556
3068
3836
22
24
26
28
30
32
36
42
30
34
38
42
46
50
58
70
50
58
66
74
82
90
106
130
82
98
114
130
146
162
194
242
162
194
226
258
290
322
386
482
322
386
450
514
578
642
770
962
642
770
898
1026
1154
1282
1538
1922
1282
1538
1794
2050
2306
2562
3074
3842
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Chapter 22 Inter-Integrated Circuit Bus Controller Module (I2C)
MUL = 4
Table 22-7. I2C divider and hold values (continued)
IBC7–0
(hex)
SCL divider
(clocks)
SDA hold
(clocks)
SCL hold
(start)
SCL hold
(stop)
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
30
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
80
88
96
104
112
120
136
160
112
128
144
160
176
192
224
272
192
224
256
288
320
352
416
512
320
384
448
512
576
640
768
960
640
768
896
1024
1152
1280
1536
1920
1280
1536
1792
2048
2304
2560
3072
3840
2560
3072
3584
4096
4608
5120
6144
7680
5120
6144
7168
8192
9216
10240
12288
15360
28
28
32
32
36
36
40
40
28
28
36
36
44
44
52
52
36
36
52
52
68
68
84
84
36
36
68
68
100
100
132
132
68
68
132
132
196
196
260
260
132
132
260
260
388
388
516
516
260
260
516
516
772
772
1028
1028
516
516
1028
1028
1540
1540
2052
2052
24
28
32
36
40
44
52
64
40
48
56
64
72
80
96
120
72
88
104
120
136
152
184
232
152
184
216
248
280
312
376
472
312
376
440
504
568
632
760
952
632
760
888
1016
1144
1272
1528
1912
1272
1528
1784
2040
2296
2552
3064
3832
2552
3064
3576
4088
4600
5112
6136
7672
44
48
52
56
60
64
72
84
60
68
76
84
92
100
116
140
100
116
132
148
164
180
212
260
164
196
228
260
292
324
388
484
324
388
452
516
580
644
772
964
644
772
900
1028
1156
1284
1540
1924
1284
1540
1796
2052
2308
2564
3076
3844
2564
3076
3588
4100
4612
5124
6148
7684
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Chapter 22 Inter-Integrated Circuit Bus Controller Module (I2C)
I2C Bus Control Register (IBCR)
22.3.4
Offset 0x2
Access: Read/write any time
7
6
5
4
3
MDIS
IBIE
MSSL
TXRX
NOACK
R
1
0
W
Reset
2
0
0
DMAEN
RSTA
1
0
0
0
0
0
0
0
Figure 22-6. I2C Bus Control Register (IBCR)
Table 22-8. IBCR field descriptions
Field
Description
MDIS
Module disable. This bit controls the software reset of the entire I2C Bus module.
1 The module is reset and disabled. This is the power-on reset situation. When high, the interface is
held in reset, but registers can still be accessed. Status register bits (IBSR) are not valid when
module is disabled.
0 The I2C Bus module is enabled. This bit must be cleared before any other IBCR bits have any effect
Note: If the I2C Bus module is enabled in the middle of a byte transfer, the interface behaves as follows:
slave mode ignores the current transfer on the bus and starts operating whenever a subsequent
start condition is detected. Master mode will not be aware that the bus is busy, hence if a start
cycle is initiated then the current bus cycle may become corrupt. This would ultimately result in
either the current bus master or the I2C Bus module losing arbitration, after which, bus operation
would return to normal.
IBIE
I-Bus Interrupt Enable.
1 Interrupts from the I2C Bus module are enabled. An I2C Bus interrupt occurs provided the IBIF bit in
the status register is also set.
0 Interrupts from the I2C Bus module are disabled. Note that this does not clear any currently pending
interrupt condition
MSSL
Master/Slave mode select. Upon reset, this bit is cleared. When this bit is changed from 0 to 1, a START
signal is generated on the bus and the master mode is selected. When this bit is changed from 1 to 0,
a STOP signal is generated and the operation mode changes from master to slave. A STOP signal
should be generated only if the IBIF flag is set. MSSL is cleared without generating a STOP signal when
the master loses arbitration.
1 Master Mode
0 Slave Mode
TXRX
Transmit/Receive mode select. This bit selects the direction of master and slave transfers. When
addressed as a slave this bit should be set by software according to the SRW bit in the status register.
In master mode this bit should be set according to the type of transfer required. Therefore, for address
cycles, this bit will always be high.
1 Transmit
0 Receive
NOACK
Data Acknowledge disable. This bit specifies the value driven onto SDA during data acknowledge cycles
for both master and slave receivers. The I2C module will always acknowledge address matches,
provided it is enabled, regardless of the value of NOACK. Note that values written to this bit are only
used when the I2C Bus is a receiver, not a transmitter.
1 No acknowledge signal response is sent (i.e., acknowledge bit = 1)
0 An acknowledge signal will be sent out to the bus at the 9th clock bit after receiving one byte of data
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Chapter 22 Inter-Integrated Circuit Bus Controller Module (I2C)
Table 22-8. IBCR field descriptions (continued)
Field
Description
RSTA
Repeat Start. Writing a 1 to this bit will generate a repeated START condition on the bus, provided it is
the current bus master. This bit will always be read as a low. Attempting a repeated start at the wrong
time, if the bus is owned by another master, will result in loss of arbitration.
1 Generate repeat start cycle
0 No effect
DMAEN
DMA Enable. When this bit is set, the DMA TX and RX lines will be asserted when the I2C module
requires data to be read or written to the data register. No Transfer Done interrupts will be generated
when this bit is set, however an interrupt will be generated if the loss of arbitration or addressed as slave
conditions occur. The DMA mode is only valid when the I2C module is configured as a Master and the
DMA transfer still requires CPU intervention at the start and the end of each frame of data. See the DMA
Application Information section for more details.
1 Enable the DMA TX/RX request signals
0 Disable the DMA TX/RX request signals
I2C Bus Status Register (IBSR)
22.3.5
Offset 0x3
R
Access: Read-write
7
6
5
4
3
2
1
0
TCF
IAAS
IBB
IBAL
0
SRW
IBIF
RXAK
W
Reset
w1c
1
0
0
0
w1c
0
0
0
0
Figure 22-7. I2C Bus Status Register (IBSR)
Table 22-9. IBSR Field Descriptions
Field
Description
TCF
Transfer complete. While one byte of data is being transferred, this bit is cleared. It is set by the falling
edge of the 9th clock of a byte transfer. Note that this bit is only valid during or immediately following a
transfer to the I2C module or from the I2C module.
1 Transfer complete
0 Transfer in progress
IAAS
Addressed as a slave. When its own specific address (I-Bus Address Register) is matched with the
calling address, this bit is set. The CPU is interrupted provided the IBIE is set. Then the CPU needs to
check the SRW bit and set its Tx/Rx mode accordingly. Writing to the I-Bus Control Register clears this
bit.
1 Addressed as a slave
0 Not addressed
IBB
Bus busy. This bit indicates the status of the bus. When a START signal is detected, the IBB is set. If a
STOP signal is detected, IBB is cleared and the bus enters idle state.
1 Bus is busy
0 Bus is Idle
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Table 22-9. IBSR Field Descriptions (continued)
Field
Description
IBAL
Arbitration Lost. The arbitration lost bit (IBAL) is set by hardware when the arbitration procedure is lost.
Arbitration is lost in the following circumstances:
• SDA is sampled low when the master drives a high during an address or data transmit cycle.
• SDA is sampled low when the master drives a high during the acknowledge bit of a data receive cycle.
• A start cycle is attempted when the bus is busy.
• A repeated start cycle is requested in slave mode.
• A stop condition is detected when the master did not request it.
SRW
Slave Read/Write. When IAAS is set, this bit indicates the value of the R/W command bit of the calling
address sent from the master. This bit is only valid when the I-Bus is in slave mode, a complete address
transfer has occurred with an address match and no other transfers have been initiated. By
programming this bit, the CPU can select slave transmit/receive mode according to the command of the
master.
1 Slave transmit, master reading from slave
0 Slave receive, master writing to slave
IBIF
I-Bus Interrupt Flag. The IBIF bit is set when one of the following conditions occurs:
• Arbitration lost (IBAL bit set)
• Byte transfer complete (TCF bit set)
• Addressed as slave (IAAS bit set)
• NoAck from Slave (MS & Tx bits set)
• I2C Bus going idle (IBB high-low transition and enabled by BIIE)
A processor interrupt request will be caused if the IBIE bit is set.
RXAK
Received Acknowledge. This is the value of SDA during the acknowledge bit of a bus cycle. If the
received acknowledge bit (RXAK) is low, it indicates an acknowledge signal has been received after the
completion of 8 bits data transmission on the bus. If RXAK is high, it means no acknowledge signal is
detected at the 9th clock. This bit is valid only after transfer is complete.
1 No acknowledge received
0 Acknowledge received
I2C Bus Data I/O Register (IBDR)
22.3.6
Offset 0x4
Access: Read/write any time
7
6
5
4
3
2
1
0
0
0
0
0
R
DATA
W
Reset
0
0
0
0
Figure 22-8. I2C Bus Data I/O Register (IBDR)
In master transmit mode, when data is written to IBDR, a data transfer is initiated. The most significant bit
is sent first. In master receive mode, reading this register initiates next byte data receiving. In slave mode,
the same functions are available after an address match has occurred. Note that the IBCR[TXRX] field
must correctly reflect the desired direction of transfer in master and slave modes for the transmission to
begin. For instance, if the I2C is configured for master transmit but a master receive is desired, then reading
the IBDR will not initiate the receive.
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Reading the IBDR will return the last byte received while the I2C is configured in either master receive or
slave receive modes. The IBDR does not reflect every byte that is transmitted on the I2C bus, nor can
software verify that a byte has been written to the IBDR correctly by reading it back.
In master transmit mode, the first byte of data written to IBDR following assertion of MS/SL is used for
the address transfer and should comprise the calling address (in position D7–D1) concatenated with the
required R/W bit (in position D0).
I2C Bus Interrupt Configuration Register (IBIC)
22.3.7
Offset 0x5
R
Access: Read/write any time
7
6
5
4
3
2
1
0
BIIE1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Figure 22-9. I2C Bus Interrupt Configuration Register (IBIC)
1
This bit cannot be set in reset state, when I2C is in slave mode. It can be set to 1 only when I2C is in Master mode.
This information is missing from the spec.
Table 22-10. IBIC field descriptions
22.4
Field
Description
BIIE
Bus Idle Interrupt Enable bit. This configuration bit can be used to enable the generation of an interrupt
once the I2C bus becomes idle. Once this bit is set, an IBB high-low transition will set the IBIF bit. This
feature can be used to signal to the CPU the completion of a STOP on the I2C bus.
1 Bus Idle Interrupts enabled
0 Bus Idle Interrupts disabled
Note:
DMA Interface
A simple DMA interface is implemented so that the I2C can request data transfers with minimal support
from the CPU. DMA mode is enabled by setting bit 1 in the Control Register.
The DMA interface is only valid when the I2C module is configured for Master Mode.
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Address
DMA request
IRQ
Data bus
ADDR_DECODE
DATA_MUX
CTRL_REG FREQ_REG ADDR_REG
Input
Sync
Start
Stop
Arbitration
Control
STATUS_REG
DATA_REG
In/Out
Data
Shift
Register
Clock
Address
Control
Compare
SCL
Figure 22-10.
I2C
SDA
module DMA interface block diagram
At least 3 bytes of data per frame must be transferred from/to the slave when using DMA mode, although
in practice it will only be worthwhile using the DMA mode when there is a large number of data bytes to
transfer per frame.
Two internal signals, TX request and RX request, are used to signal to a DMA controller when the I2C
module requires data to be written or read from the data register.
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22.5
Functional description
22.5.1
I-Bus protocol
The I2C Bus system uses a Serial Data line (SDA) and a Serial Clock Line (SCL) for data transfer. All
devices connected to it must have open drain or open collector outputs. A logical AND function is
exercised on both lines with external pullup resistors. The value of these resistors is system dependent.
Normally, a standard communication is composed of four parts: START signal, slave address transmission,
data transfer and STOP signal. They are described briefly in the following sections and illustrated in
Figure 22-11.
MSB
SCL
SDA
1
LSB
2
3
4
5
6
7
Calling Address
Read/
Write
MSB
SDA
MSB
9
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
Start
Signal
SCL
8
1
XXX
3
4
5
6
7
8
Calling Address
Read/
Write
3
4
5
6
7
8
D7
D6
D5
D4
D3
D2
D1
D0
Data Byte
1
XX
Ack
Bit
9
No
Ack
Bit
MSB
9
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
Start
Signal
2
Ack
Bit
LSB
2
LSB
1
Stop
Signal
LSB
2
3
4
5
6
7
8
9
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
Repeated
Start
Signal
New Calling Address
Read/
Write
No
Ack
Bit
Stop
Signal
Figure 22-11. I2C bus transmission signals
22.5.1.1
START signal
When the bus is free, that is, no master device is engaging the bus (both SCL and SDA lines are at logical
high), a master may initiate communication by sending a START signal. As shown in Figure 22-11, a
START signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the
beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves
out of their idle states.
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SDA
SCL
START condition
STOP condition
Figure 22-12. Start and stop conditions
22.5.1.2
Slave address transmission
The first byte of data transfer immediately after the START signal is the slave address transmitted by the
master. This is a 7-bit calling address followed by a R/W bit. The R/W bit tells the slave the desired
direction of data transfer.
1 = Read transfer—the slave transmits data to the master
0 = Write transfer—the master transmits data to the slave
Only the slave with a calling address that matches the one transmitted by the master will respond by
sending back an acknowledge bit. This is done by pulling the SDA low at the 9th clock (see Figure 22-11).
No two slaves in the system may have the same address. If the I2C bus is master, it must not transmit an
address that is equal to its own slave address. The I2C bus cannot be master and slave at the same time.
However, if arbitration is lost during an address cycle the I2C bus will revert to slave mode and operate
correctly, even if it is being addressed by another master.
22.5.1.3
Data transfer
Once successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a direction
specified by the R/W bit sent by the calling master.
All transfers that come after an address cycle are referred to as data transfers, even if they carry sub-address
information for the slave device.
Each data byte is 8 bits long. Data may be changed only while SCL is low and must be held stable while
SCL is high as shown in Figure 22-11. There is one clock pulse on SCL for each data bit, the MSB being
transferred first. Each data byte must be followed by an acknowledge bit, which is signaled from the
receiving device by pulling the SDA low at the ninth clock. Therefore, one complete data byte transfer
needs 9 clock pulses.
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If the slave receiver does not acknowledge the master, the SDA line must be left high by the slave. The
master can then generate a stop signal to abort the data transfer or a start signal (repeated start) to
commence a new calling.
If the master receiver does not acknowledge the slave transmitter after a byte transmission, it means 'end
of data' to the slave, so the slave releases the SDA line for the master to generate a STOP or START signal.
22.5.1.4
STOP signal
The master can terminate the communication by generating a STOP signal to free the bus. However, the
master may generate a START signal followed by a calling command without generating a STOP signal
first. This is called repeated START. A STOP signal is defined as a low-to-high transition of SDA while
SCL is at logical 1 (see Figure 22-11).
The master can generate a STOP even if the slave has generated an acknowledge, at which point the slave
must release the bus.
22.5.1.5
Repeated START signal
As shown in Figure 22-11, a repeated START signal is a START signal generated without first generating
a STOP signal to terminate the communication. This is used by the master to communicate with another
slave or with the same slave in different mode (transmit/receive mode) without releasing the bus.
22.5.1.6
Arbitration procedure
The Inter-IC bus is a true multi-master bus that allows more than one master to be connected on it. If two
or more masters try to control the bus at the same time, a clock synchronization procedure determines the
bus clock, for which the low period is equal to the longest clock low period and the high is equal to the
shortest one among the masters. The relative priority of the contending masters is determined by a data
arbitration procedure. A bus master loses arbitration if it transmits logic 1 while another master transmits
logic 0. The losing masters immediately switch over to slave receive mode and stop driving the SDA
output. In this case, the transition from master to slave mode does not generate a STOP condition.
Meanwhile, a status bit is set by hardware to indicate loss of arbitration.
22.5.1.7
Clock synchronization
Since wire-AND logic is performed on the SCL line, a high-to-low transition on the SCL line affects all
the devices connected on the bus. The devices start counting their low period and once a device's clock has
gone low, it holds the SCL line low until the clock high state is reached. However, the change of low to
high in this device clock may not change the state of the SCL line if another device clock is still within its
low period. Therefore, synchronized clock SCL is held low by the device with the longest low period.
Devices with shorter low periods enter a high wait state during this time (see Figure 22-13). When all
devices concerned have counted off their low period, the synchronized clock SCL line is released and
pulled high. There is then no difference between the device clocks and the state of the SCL line and all the
devices start counting their high periods. The first device to complete its high period pulls the SCL line
low again.
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WAIT
Start Counting High Period
SCL1
SCL2
SCL
Internal Counter Reset
Figure 22-13. I2C bus clock synchronization
22.5.1.8
Handshaking
The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold
the SCL low after completion of one byte transfer (9 bits). In such cases, it halts the bus clock and forces
the master clock into wait state until the slave releases the SCL line.
22.5.1.9
Clock stretching
The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. After
the master has driven SCL low, the slave can drive SCL low for the required period and then release it. If
the slave SCL low period is greater than the master SCL low period then the resulting SCL bus signal low
period is stretched.
22.5.2
Interrupts
22.5.2.1
General
The I2C uses only one interrupt vector.
Table 22-11. Interrupt summary
Interrupt
Offset
I2C
Interrupt
—
Vector Priority
—
—
Source
Description
IBAL, TCF,
When any of IBAL, TCF or IAAS bits is set an interrupt may
IAAS, IBB bits in be caused based on Arbitration lost, Transfer Complete or
IBSR register Address Detect conditions. If enabled by BIIE, the
deassertion of IBB can also cause an interrupt, indicating
that the bus is idle.
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22.5.2.2
Interrupt description
There are five types of internal interrupts in the I2C. The interrupt service routine can determine the
interrupt type by reading the Status Register.
The I2C interrupt can be generated on
• Arbitration Lost condition (IBAL bit set)
• Byte Transfer condition (TCF bit set and DMAEN bit not set)
• Address Detect condition (IAAS bit set)
• No Acknowledge from slave received when expected
• Bus Going Idle (IBB bit not set)
The I2C interrupt is enabled by the IBIE bit in the I2C Control Register. It must be cleared by writing 1 to
the IBIF bit in the interrupt service routine. The Bus Going Idle interrupt needs to be additionally enabled
by the BIIE bit in the IBIC register.
22.6
Initialization/application information
22.6.1
22.6.1.1
I2C programming examples
Initialization sequence
Reset will put the I2C Bus Control Register to its default state. Before the interface can be used to transfer
serial data, an initialization procedure must be carried out, as follows:
1. Update the Frequency Divider Register (IBFD) and select the required division ratio to obtain SCL
frequency from system clock.
2. Update the I2C Bus Address Register (IBAD) to define its slave address.
3. Clear the IBCR[MDIS] field to enable the I2C interface system.
4. Modify the bits of the I2C Bus Control Register (IBCR) to select Master/Slave mode,
Transmit/Receive mode and interrupt enable or not. Optionally also modify the bits of the I2C Bus
Interrupt Configuration Register (IBIC) to further refine the interrupt behavior.
22.6.1.2
Generation of START
After completion of the initialization procedure, serial data can be transmitted by selecting the 'master
transmitter' mode. If the device is connected to a multi-master bus system, the state of the I2C Bus Busy
bit (IBB) must be tested to check whether the serial bus is free.
If the bus is free (IBB=0), the start condition and the first byte (the slave address) can be sent. The data
written to the data register comprises the slave calling address and the LSB, which is set to indicate the
direction of transfer required from the slave.
The bus free time (i.e., the time between a STOP condition and the following START condition) is built
into the hardware that generates the START cycle. Depending on the relative frequencies of the system
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clock and the SCL period, it may be necessary to wait until the I2C is busy after writing the calling address
to the IBDR before proceeding with the following instructions. This is illustrated in the following example.
An example of the sequence of events that generates the START signal and transmits the first byte of data
(slave address) is shown below:
while (bit 5, IBSR ==1)// wait in loop for IBB flag to clear
bit4 and bit 5, IBCR = 1// set transmit and master mode, i.e. generate start condition
IBDR = calling_address// send the calling address to the data register
while (bit 5, IBSR ==0)// wait in loop for IBB flag to be set
22.6.1.3
Post-transfer software response
Transmission or reception of a byte will set the data transferring bit (TCF) to 1, which indicates one byte
communication is finished. The I2C Bus interrupt bit (IBIF) is set also; an interrupt will be generated if the
interrupt function is enabled during initialization by setting the IBIE bit. The IBIF (interrupt flag) can be
cleared by writing 1 (in the interrupt service routine, if interrupts are used).
The TCF bit will be cleared to indicate data transfer in progress whenever data register is written to in
transmit mode, or during reading out from data register in receive mode. The TCF bit should not be used
as a data transfer complete flag as the flag timing is dependent on a number of factors including the I2C
bus frequency. This bit may not conclusively provide an indication of a transfer complete situation. It is
recommended that transfer complete situations are detected using the IBIF flag
Software may service the I2C I/O in the main program by monitoring the IBIF bit if the interrupt function
is disabled. Note that polling should monitor the IBIF bit rather than the TCF bit since their operation is
different when arbitration is lost.
Note that when a Transfer Complete interrupt occurs at the end of the address cycle, the master will always
be in transmit mode, i.e. the address is transmitted. If master receive mode is required, indicated by R/W
bit sent with slave calling address, then the Tx/Rx bit at Master side should be toggled at this stage. If
Master does not receive an ACK from Slave, then transmission must be re-initiated or terminated.
In slave mode, IAAS bit will get set in IBSR if Slave address (IBAD) matches the Master calling address.
This is an indication that Master-Slave data communication can now start. During address cycles
(IAAS=1), the SRW bit in the status register is read to determine the direction of the subsequent transfer
and the Tx/Rx bit is programmed accordingly. For slave mode data cycles (IAAS=0), the SRW bit is not
valid. The Tx/Rx bit in the control register should be read to determine the direction of the current transfer.
22.6.1.4
Transmit/receive sequence
Follow this sequence in case of Master Transmit (Address/Data):
1. Clear IBSR[IBIF].
2. Write data in Data Register (IBDR).
3. IBSR[TCF] bit will get cleared when transfer is in progress.
4. IBSR[TCF] bit will get set when transfer is complete.
5. Wait for IBSR[IBIF] to get set, then read IBSR register to determine its source:
— TCF = 1, transfer is complete.
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— No Acknowledge condition (RXAK = 1) is found.
— IBB = 0, Bus has transitioned from Busy to Idle state.
— If IBB = 1, ignore check of Arbitration Loss (IBAL = 1).
— Ignore Address Detect (IAAS = 1) for Master mode (valid only for Slave mode).
6. f) Check RXAK in IBSR for an acknowledge from slave.
Follow this sequence in case of Slave Receive (Address/Data):
1. Clear IBSR[IBIF].
2. IBSR[TCF] will get cleared when transfer is in progress for address transfer.
3. IBSR[TCF] will get set when transfer is complete.
4. Wait for IBSR[IBIF] to get set. Then read IBSR register to determine its source:
— Address Detect has occurred (IAAS = 1)—determination of Slave mode.
5. Clear IBIF.
6. Wait until IBSR[TCF] bit gets cleared (that is, “Transfer under Progress” condition is reached for
data transfer).
7. Wait until IBSR[TCF] bit gets cleared (proof that transfer completes from “Transfer under
Progress” state).
8. Wait until IBSR[IBIF] bit gets set. To find its source, check if:
— TCF = 1 i.e. reception is complete
— IBSR[IBB] = 0, that is, bus has transitioned from Busy to Idle state
— Ignore Arbitration Loss (IBAL = 1) for IBB = 1
— Ignore No Acknowledge condition (RXAK = 1) for receiver
9. Read the Data Register (IBDR) to determine data received from Master.
Sequence followed in case of Slave Transmit (Steps 1–4 of Slave Receive for Address Detect, followed by
1–6 of Master Transmit for Data Transmit).
Sequence followed in case of Master Receive (Steps 1–6 of Master Transmit for Address dispatch,
followed by 5–8 of Slave Receive for Data Receive).
22.6.1.5
Generation of STOP
A data transfer ends with a STOP signal generated by the 'master' device. A master transmitter can simply
generate a STOP signal after all the data has been transmitted. The following is an example showing how
a stop condition is generated by a master transmitter.
if (tx_count == 0) or// check to see if all data bytes have been transmitted
(bit 0, IBSR == 1) {// or if no ACK generated
clear bit 5, IBCR// generate stop condition
}
else {
IBDR = data_to_transmit// write byte of data to DATA register
tx_count --// decrement counter
}// return from interrupt
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If a master receiver wants to terminate a data transfer, it must inform the slave transmitter by not
acknowledging the last byte of data, which can be done by setting the transmit acknowledge bit (TXAK)
before reading the 2nd last byte of data. Before reading the last byte of data, a STOP signal must first be
generated. The following is an example showing how a STOP signal is generated by a master receiver.
rx_count --// decrease the rx counter
if (rx_count ==1)// 2nd last byte to be read ?
bit 3, IBCR = 1// disable ACK
if (rx_count == 0)// last byte to be read ?
bit 5, IBCR = 0// generate stop signal
else
data_received = IBDR// read RX data and store
22.6.1.6
Generation of repeated START
At the end of data transfer, if the master still wants to communicate on the bus, it can generate another
START signal followed by another slave address without first generating a STOP signal. A program
example is as shown.
bit 2, IBCR = 1// generate another start ( restart)
IBDR == calling_address// transmit the calling address
22.6.1.7
Slave mode
In the slave interrupt service routine, the module addressed as slave bit (IAAS) should be tested to check
if a calling of its own address has just been received. If IAAS is set, software should set the
transmit/receive mode select bit (Tx/Rx bit of IBCR) according to the R/W command bit (SRW). Writing
to the IBCR clears IAAS automatically. Note that the only time IAAS is read as set is from the interrupt
at the end of the address cycle where an address match occurred. Interrupts resulting from subsequent data
transfers will have IAAS cleared. A data transfer may now be initiated by writing information to IBDR for
slave transmits or dummy reading from IBDR in slave receive mode. The slave will drive SCL low
in-between byte transfers SCL is released when the IBDR is accessed in the required mode.
In slave transmitter routine, the received acknowledge bit (RXAK) must be tested before transmitting the
next byte of data. Setting RXAK means an 'end of data' signal from the master receiver, after which it must
be switched from transmitter mode to receiver mode by software. A dummy read then releases the SCL
line so that the master can generate a STOP signal.
22.6.1.8
Arbitration lost
If several masters try to engage the bus simultaneously, only one master wins and the others lose
arbitration. The devices that lost arbitration are immediately switched to slave receive mode by the
hardware. Their data output to the SDA line is stopped, but SCL is still generated until the end of the byte
during which arbitration was lost. An interrupt occurs at the falling edge of the ninth clock of this transfer
with IBAL=1 and MS/SL=0. If one master attempts to start transmission, while the bus is being engaged
by another master, the hardware will inhibit the transmission, switch the MS/SL bit from 1 to 0 without
generating a STOP condition, generate an interrupt to CPU and set the IBAL to indicate that the attempt
to engage the bus is failed. When considering these cases, the slave service routine should test the IBAL
first and the software should clear the IBAL bit if it is set.
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Clear
IBIF
Master
Mode
?
Y
TX
N
Y
RX
Tx/Rx
?
Arbitration
Lost
?
N
Last Byte
Transmitted
?
N
RXAK=0
?
Clear IBAL
Y
Last
Byte To Be Read
?
N
N
Y
N
Y
Y
IAAS=1
?
Y
N
Address Transfer
Y
End Of
Addr Cycle
(Master Rx)
?
N
Y
Y
(Read)
2nd Last
Byte To Be Read
?
Write Next
Byte To IBDR
Generate
Stop Signal
Set TXAK =1
SRW=1
?
Data Transfer
TX/RX
?
Y
Set TX
Mode
RX
TX
N (Write)
N
IAAS=1
?
ACK From
Receiver
?
N
Switch To
Rx Mode
Dummy Read
From IBDR
Generate
Stop Signal
Read Data
From IBDR
And Store
Read Data
From IBDR
And Store
Tx Next
Byte
Write Data
To IBDR
Set RX
Mode
Switch To
Rx Mode
Dummy Read
From IBDR
Dummy Read
From IBDR
RTI
Figure 22-14. Flow chart of typical I2C interrupt routine
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Chapter 23 LIN Controller (LINFlex)
Chapter 23
LIN Controller (LINFlex)
23.1
Introduction
The LINFlex (Local Interconnect Network Flexible) controller interfaces the LIN network and supports
the LIN protocol versions 1.3; 2.0 and 2.1; and J2602 in both Master and Slave modes. LINFlex includes
a LIN mode that provides additional features (compared to standard UART) to ease LIN implementation,
improve system robustness, minimize CPU load and allow slave node resynchronization.
23.2
Main features
23.2.1
•
•
•
•
•
•
•
•
•
•
•
•
•
Supports LIN protocol versions 1.3, 2.0, 2.1, and J2602
Master mode with autonomous message handling
Classic and enhanced checksum calculation and check
Single 8-byte buffer for transmission/reception
Extended frame mode for In-Application Programming (IAP) purposes
Wake-up event on dominant bit detection
True LIN field state machine
Advanced LIN error detection
Header, response, and frame timeout
Slave mode
— Autonomous header handling
— Autonomous transmit/receive data handling
LIN automatic resynchronization, allowing operation with 16 MHz fast internal RC oscillator as
clock source
16 identifier filters for autonomous message handling in Slave mode
Peripheral DMA request sources possible from LINFlex
23.2.2
•
•
•
•
UART mode features
Full duplex communication
8- or 9-bit with parity
4-byte buffer for reception, 4-byte buffer for transmission
8-bit counter for timeout management
23.2.3
•
LIN mode features
Features common to LIN and UART
Fractional baud rate generator
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Chapter 23 LIN Controller (LINFlex)
•
•
•
23.3
Three operating modes for power saving and configuration registers lock:
— Initialization
— Normal
— Sleep
Two test modes:
— Loop Back
— Self Test
Maskable interrupts
General description
The increasing number of communication peripherals embedded on microcontrollers, for example CAN,
LIN, and SPI, requires more and more CPU resources for communication management. Even a 32-bit
microcontroller is overloaded if its peripherals do not provide high-level features to autonomously handle
the communication.
Even though the LIN protocol with a maximum baud rate of 20 kbit/s is relatively slow, it still generates
a non-negligible load on the CPU if the LIN is implemented on a standard UART, as usually the case.
To minimize the CPU load in Master mode, LINFlex handles the LIN messages autonomously.
In Master mode, once the software has triggered the header transmission, LINFlex does not request any
software intervention until the next header transmission request in transmission mode or until the
checksum reception in reception mode.
To minimize the CPU load in Slave mode, LINFlex requires software intervention only to:
• Trigger transmission or reception or data discard depending on the identifier
• Write data into the buffer (transmission mode) or read data from the buffer (reception mode) after
checksum reception
If filter mode is activated for Slave mode, LINFlex requires software intervention only to write data into
the buffer (transmission mode) or read data from the buffer (reception mode)
The software uses the control, status, and configuration registers to:
• Configure LIN parameters (for example, baud rate or mode)
• Request transmissions
• Handle receptions
• Manage interrupts
• Configure LIN error and timeout detection
• Process diagnostic information
The message buffer stores transmitted or received LIN frames.
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MCU
Application
LINFlex
Controller
LIN
Rx
LIN slave node n
LIN slave node 1
LIN master node
Chapter 23 LIN Controller (LINFlex)
LIN
Tx
LIN
Transceiver
LIN
LIN Bus
Figure 23-1. LIN topology network
REGISTER MODEL / APPLICATION INTERFACE
Message
Buffer
Interface
CONFIGURATION
CONTROL STATUS
LIN control
LIN status
Baud rate
SLAVE
MESSAGE HANDLER
Filter configuration
MASTER
MESSAGE HANDLER
Identifier Filters(1)
LIN PROTOCOL HANDLER
1. Filter activation optional
Figure 23-2. LINFlex block diagram
23.4
Fractional baud rate generation
The baud rates for the receiver and transmitter are both set to the same value as programmed in the
Mantissa (LINIBRR) and Fraction (LINFBRR) registers.
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Chapter 23 LIN Controller (LINFlex)
Eqn. 23-1
Tx/ Rx baud =
fperiph_set_1_clk
(16 × LFDIV)
LFDIV is an unsigned fixed point number. The 12-bit mantissa is coded in the LINIBRR and the fraction
is coded in the LINFBRR.
The following examples show how to derive LFDIV from LINIBRR and LINFBRR register values:
Example 23-1. Deriving LFDIV from LINIBRR and LINFBRR register values
If LINIBRR = 27d and LINFBRR = 12d, then
Mantissa (LFDIV) = 27d
Fraction (LFDIV) = 12/16 = 0.75d
Therefore LFDIV = 27.75d
Example 23-2. Programming LFDIV from LINIBRR and LINFBRR register values
To program LFDIV = 25.62d,
LINFBRR = 16 × 0.62 = 9.92, nearest real number 10d = 0xA
LINIBRR = mantissa (25.620d) = 25d = 0x19
NOTE
The baud counters are updated with the new value of the baud registers after
a write to LINIBRR. Hence the baud register value must not be changed
during a transaction. The LINFBRR (containing the Fraction bits) must be
programmed before the LINIBRR.
NOTE
LFDIV must be greater than or equal to 1.5d, i.e. LINIBRR = 1 and
LINFBRR = 8. Therefore, the maximum possible baudrate is
fperiph_set_1_clk / 24.
Table 23-1. Error calculation for programmed baud rates
fperiph_set_1_clk
Baud
rate
Actual
= 64 MHz
fperiph_set_1_clk
Value programmed
in
the baud rate
register
LINIBRR
% Error =
(Calculated –
Desired)
baud rate
/ Desired
baud rate
LINFBRR
Actual
= 16 MHz
% Error =
Value programmed in (Calculated –
the baud rate register
Desired)
baud rate
/ Desired
LINIBRR
LINFBRR
baud rate
2400
2399.97
1666
11
–0.001
2399.88
416
11
–0.005
9600
9599.52
416
11
–0.005
9598.08
104
3
–0.02
10417
10416.7
384
0
–0.003
10416.7
96
0
–0.003
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Chapter 23 LIN Controller (LINFlex)
Table 23-1. Error calculation for programmed baud rates (continued)
fperiph_set_1_clk
Baud
rate
Actual
= 64 MHz
fperiph_set_1_clk
Value programmed
in
the baud rate
register
LINIBRR
% Error =
(Calculated –
Desired)
baud rate
/ Desired
baud rate
LINFBRR
Actual
= 16 MHz
% Error =
Value programmed in (Calculated –
the baud rate register
Desired)
baud rate
/ Desired
LINIBRR
LINFBRR
baud rate
19200
19201.9
208
5
0.01
19207.7
52
1
0.04
57600
57605.8
69
7
0.01
57554
17
6
–0.08
115200
115108
34
12
–0.08
115108
8
11
–0.08
230400
230216
17
6
–0.08
231884
4
5
0.644
460800
460432
8
11
–0.08
457143
2
3
–0.794
921600
927536
4
5
0.644
941176
1
1
2.124
23.5
Operating modes
LINFlex has three main operating modes: Initialization, Normal, and Sleep. After a hardware reset,
LINFlex is in Sleep mode to reduce power consumption. The software instructs LINFlex to enter
Initialization mode or Sleep mode by setting the INIT bit or SLEEP bit in the LINCR1.
RESET
SL
EE
SL
SLEEP
LINRX DOMINANT
SLEEP
P*
EE
INI
T
P
INITIALIZATION
SL
P
EE
IT
* IN
P*
EE
SL
T
I NI
NORMAL
Figure 23-3. LINFlex operating modes
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Chapter 23 LIN Controller (LINFlex)
23.5.1
Initialization mode
The software can be initialized while the hardware is in Initialization mode. To enter this mode the
software sets the INIT bit in the LINCR1.
To exit Initialization mode, the software clears the INIT bit.
While in Initialization mode, all message transfers to and from the LIN bus are stopped and the status of
the LIN bus output LINTX is recessive (high).
Entering Initialization mode does not change any of the configuration registers.
To initialize the LINFlex controller, the software selects the mode (LIN Master, LIN Slave or UART), sets
up the baud rate register and, if LIN Slave mode with filter activation is selected, initializes the identifier
list.
23.5.2
Normal mode
Once initilization is complete, software clears the INIT bit in the LINCR1 to put the hardware into Normal
mode.
23.5.3
Low power mode (Sleep)
To reduce power consumption, LINFlex has a low power mode called Sleep mode. To enter Sleep mode,
software sets the SLEEP bit in the LINCR1. In this mode, the LINFlex clock is stopped. Consequently, the
LINFlex will not update the status bits but software can still access the LINFlex registers.
LINFlex can be awakened (exit Sleep mode) either by software clearing the SLEEP bit or on detection of
LIN bus activity if automatic wake-up mode is enabled (AWUM bit is set).
On LIN bus activity detection, hardware automatically performs the wake-up sequence by clearing the
SLEEP bit if the AWUM bit in the LINCR1 is set. To exit from Sleep mode if the AWUM bit is cleared,
software clears the SLEEP bit when a wake-up event occurs.
23.6
Test modes
Two test modes are available to the user: Loop Back mode and Self Test mode. They can be selected by
the LBKM and SFTM bits in the LINCR1. These bits must be configured while LINFlex is in Initialization
mode. Once one of the two test modes has been selected, LINFlex must be started in Normal mode.
23.6.1
Loop Back mode
LINFlex can be put in Loop Back mode by setting the LBKM bit in the LINCR. In Loop Back mode, the
LINFlex treats its own transmitted messages as received messages.
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Chapter 23 LIN Controller (LINFlex)
LINFlex
Tx
Rx
LINTX
LINRX
Figure 23-4. LINFlex in loop back mode
This mode is provided for self test functions. To be independent of external events, the LIN core ignores
the LINRX signal. In this mode, the LINFlex performs an internal feedback from its Tx output to its Rx
input. The actual value of the LINRX input pin is disregarded by the LINFlex. The transmitted messages
can be monitored on the LINTX pin.
23.6.2
Self Test mode
LINFlex can be put in Self Test mode by setting the LBKM and SFTM bits in the LINCR. This mode can
be used for a Hot Self Test, meaning the LINFlex can be tested as in Loop Back mode but without affecting
a running LIN system connected to the LINTX and LINRX pins. In this mode, the LINRX pin is
disconnected from the LINFlex and the LINTX pin is held recessive.
LINFlex
Tx
Rx
=1
LINTX
LINRX
Figure 23-5. LINFlex in self test mode
23.7
23.7.1
Memory map and registers description
Memory map
See Chapter 3, Memory Map, of this reference manual for the base addresses for the LINFlex modules.
Table 23-2 shows the LINFlex memory map.
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Chapter 23 LIN Controller (LINFlex)
Table 23-2. LINFlex memory map
Address offset
Register
Location
0x0000
LIN control register 1 (LINCR1)
on page 429
0x0004
LIN interrupt enable register (LINIER)
on page 432
0x0008
LIN status register (LINSR)
on page 433
0x000C
LIN error status register (LINESR)
on page 436
0x0010
UART mode control register (UARTCR)
on page 437
0x0014
UART mode status register (UARTSR)
on page 438
0x0018
LIN timeout control status register (LINTCSR)
on page 440
0x001C
LIN output compare register (LINOCR)
on page 441
0x0020
LIN timeout control register (LINTOCR)
on page 442
0x0024
LIN fractional baud rate register (LINFBRR)
on page 442
0x0028
LIN integer baud rate register (LINIBRR)
on page 443
0x002C
LIN checksum field register (LINCFR)
on page 444
0x0030
LIN control register 2 (LINCR2)
on page 444
0x0034
Buffer identifier register (BIDR)
on page 445
0x0038
Buffer data register LSB (BDRL)1
on page 446
0x003C
Buffer data register MSB (BDRM)2
on page 447
0x0040
Identifier filter enable register (IFER)
on page 448
0x0044
Identifier filter match index (IFMI)
on page 449
0x0048
Identifier filter mode register (IFMR)
on page 450
0x004C
Identifier filter control register 0 (IFCR0)
on page 451
0x0050
Identifier filter control register 1 (IFCR1)
on page 452
0x0054
Identifier filter control register 2 (IFCR2)
on page 452
0x0058
Identifier filter control register 3 (IFCR3)
on page 452
0x005C
Identifier filter control register 4 (IFCR4)
on page 452
0x0060
Identifier filter control register 5 (IFCR5)
on page 452
0x0064
Identifier filter control register 6 (IFCR6)
on page 452
0x0068
Identifier filter control register 7 (IFCR7)
on page 452
0x006C
Identifier filter control register 8 (IFCR8)
on page 452
0x0070
Identifier filter control register 9 (IFCR9)
on page 452
0x0074
Identifier filter control register 10 (IFCR10)
on page 452
0x0078
Identifier filter control register 11 (IFCR11)
on page 452
0x007C
Identifier filter control register 12 (IFCR12)
on page 452
0x0080
Identifier filter control register 13 (IFCR13)
on page 452
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Chapter 23 LIN Controller (LINFlex)
Table 23-2. LINFlex memory map (continued)
Address offset
2
23.7.1.1
Location
0x0084
Identifier filter control register 14 (IFCR14)
on page 452
0x0088
Identifier filter control register 15 (IFCR15)
on page 452
0x008C–0x000F
1
Register
Reserved
LSB: Least significant byte
MSB: Most significant byte
LIN control register 1 (LINCR1)
Offset: 0x0000
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
W
Reset
R
CCD CFD LASE AWUM
MBL
BF
SFTM LBKM MME SBDT RBLM SLEEP INIT
W
Reset
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
Figure 23-6. LIN control register 1 (LINCR1)
Table 23-3. LINCR1 field descriptions
Field
Description
CCD
Checksum calculation disable
This bit disables the checksum calculation (see Table 23-4).
0 Checksum calculation is done by hardware. When this bit is 0, the LINCFR is read-only.
1 Checksum calculation is disabled. When this bit is set the LINCFR is read/write. User can
program this register to send a software-calculated CRC (provided CFD is 0).
Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
CFD
Checksum field disable
This bit disables the checksum field transmission (see Table 23-4).
0 Checksum field is sent after the required number of data bytes is sent.
1 No checksum field is sent.
Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
LASE
LIN Slave Automatic Resynchronization Enable
0 Automatic resynchronization disable.
1 Automatic resynchronization enable.
Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
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Chapter 23 LIN Controller (LINFlex)
Table 23-3. LINCR1 field descriptions (continued)
Field
Description
AWUM
Automatic Wake-Up Mode
This bit controls the behavior of the LINFlex hardware during Sleep mode.
0 The Sleep mode is exited on software request by clearing the SLEEP bit of the LINCR.
1 The Sleep mode is exited automatically by hardware on LINRX dominant state detection. The
SLEEP bit of the LINCR is cleared by hardware whenever WUF bit in the LINSR is set.
Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
MBL
LIN Master Break Length
This field indicates the Break length in Master mode (see Table 23-5).
Note: This field can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
BF
Bypass filter
0 No interrupt if identifier does not match any filter.
1 An RX interrupt is generated on identifier not matching any filter.
Note:
• If no filter is activated, this bit is reserved and always reads 1.
• This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
SFTM
Self Test Mode
This bit controls the Self Test mode. For more details, see Section 23.6.2, Self Test mode.
0 Self Test mode disable.
1 Self Test mode enable.
Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
LBKM
Loop Back Mode
This bit controls the Loop Back mode. For more details see Section 23.6.1, Loop Back mode.
0 Loop Back mode disable.
1 Loop Back mode enable.
Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode
MME
Master Mode Enable
0 Slave mode enable.
1 Master mode enable.
Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
SBDT
Slave Mode Break Detection Threshold
0 11-bit break.
1 10-bit break.
Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
RBLM
Receive Buffer Locked Mode
0 Receive Buffer not locked on overrun. Once the Slave Receive Buffer is full the next incoming
message overwrites the previous one.
1 Receive Buffer locked against overrun. Once the Receive Buffer is full the next incoming
message is discarded.
Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
SLEEP
Sleep Mode Request
This bit is set by software to request LINFlex to enter Sleep mode.
This bit is cleared by software to exit Sleep mode or by hardware if the AWUM bit in LINCR1 and
the WUF bit in LINSR are set (see Table 23-6).
INIT
Initialization Request
The software sets this bit to switch hardware into Initialization mode. If the SLEEP bit is reset,
LINFlex enters Normal mode when clearing the INIT bit (see Table 23-6).
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Chapter 23 LIN Controller (LINFlex)
Table 23-4. Checksum bits configuration
CFD
CCD
LINCFR
Checksum sent
1
1
Read/Write
None
1
0
Read-only
None
0
1
Read/Write
Programmed in LINCFR by bits CF[0:7]
0
0
Read-only
Hardware calculated
Table 23-5. LIN master break length selection
MBL
Length
0000
10-bit
0001
11-bit
0010
12-bit
0011
13-bit
0100
14-bit
0101
15-bit
0110
16-bit
0111
17-bit
1000
18-bit
1001
19-bit
1010
20-bit
1011
21-bit
1100
22-bit
1101
23-bit
1110
36-bit
1111
50-bit
Table 23-6. Operating mode selection
SLEEP
INIT
Operating mode
1
0
Sleep (reset value)
x
1
Initialization
0
0
Normal
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Chapter 23 LIN Controller (LINFlex)
23.7.1.2
LIN interrupt enable register (LINIER)
Offset: 0x0004
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
W
Reset
R
SZIE OCIE BEIE CEIE HEIE
FEIE BOIE LSIE WUIE DBFIE DBEIE DRIE DTIE HRIE
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 23-7. LIN interrupt enable register (LINIER)
Table 23-7. LINIER field descriptions
Field
Description
SZIE
Stuck at Zero Interrupt Enable
0 No interrupt when SZF bit in LINESR or UARTSR is set.
1 Interrupt generated when SZF bit in LINESR or UARTSR is set.
OCIE
Output Compare Interrupt Enable
0 No interrupt when OCF bit in LINESR or UARTSR is set.
1 Interrupt generated when OCF bit in LINESR or UARTSR is set.
BEIE
Bit Error Interrupt Enable
0 No interrupt when BEF bit in LINESR is set.
1 Interrupt generated when BEF bit in LINESR is set.
CEIE
Checksum Error Interrupt Enable
0 No interrupt on Checksum error.
1 Interrupt generated when checksum error flag (CEF) in LINESR is set.
HEIE
Header Error Interrupt Enable
0 No interrupt on Break Delimiter error, Synch Field error, Identifier field error.
1 Interrupt generated on Break Delimiter error, Synch Field error, Identifier field error.
FEIE
Framing Error Interrupt Enable
0 No interrupt on Framing error.
1 Interrupt generated on Framing error.
BOIE
Buffer Overrun Interrupt Enable
0 No interrupt on Buffer overrun.
1 Interrupt generated on Buffer overrun.
LSIE
LIN State Interrupt Enable
0 No interrupt on LIN state change.
1 Interrupt generated on LIN state change.
This interrupt can be used for debugging purposes. It has no status flag but is reset when writing
1111 into LINS[0:3] in the LINSR.
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Chapter 23 LIN Controller (LINFlex)
Table 23-7. LINIER field descriptions (continued)
Field
Description
WUIE
Wake-up Interrupt Enable
0 No interrupt when WUF bit in LINSR or UARTSR is set.
1 Interrupt generated when WUF bit in LINSR or UARTSR is set.
DBFIE
Data Buffer Full Interrupt Enable
0 No interrupt when buffer data register is full.
1 Interrupt generated when data buffer register is full.
DBEIE
Data Buffer Empty Interrupt Enable
0 No interrupt when buffer data register is empty.
1 Interrupt generated when data buffer register is empty.
DRIE
Data Reception Complete Interrupt Enable
0 No interrupt when data reception is completed.
1 Interrupt generated when data received flag (DRF) in LINSR or UARTSR is set.
DTIE
Data Transmitted Interrupt Enable
0 No interrupt when data transmission is completed.
1 Interrupt generated when data transmitted flag (DTF) is set in LINSR or UARTSR.
HRIE
Header Received Interrupt Enable
0 No interrupt when a valid LIN header has been received.
1 Interrupt generated when a valid LIN header has been received, that is, HRF bit in LINSR is set.
23.7.1.3
LIN status register (LINSR)
Offset: 0x0008
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
RMB
0
DTF
HRF
W
Reset
R
LINS
W
w1c
Reset
0
0
w1c
0
0
0
0
0
RBSY RPS WUF DBFF DBEF DRF
w1c
0
0
1
w1c
w1c
w1c
w1c
w1c
w1c
0
0
0
0
0
0
Figure 23-8. LIN status register (LINSR)
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Chapter 23 LIN Controller (LINFlex)
t
Table 23-8. LINSR field descriptions
Field
LINS
Description
LIN modes / normal mode states
0000: Sleep mode
LINFlex is in Sleep mode to save power consumption.
0001: Initialization mode
LINFlex is in Initialization mode.
Normal mode states
0010: Idle
This state is entered on several events:
• SLEEP bit and INIT bit in LINCR1 have been cleared by software,
• A falling edge has been received on RX pin and AWUM bit is set,
• The previous frame reception or transmission has been completed or aborted.
0011: Break
In Slave mode, a falling edge followed by a dominant state has been detected. Receiving Break.
Note: In Slave mode, in case of error new LIN state can be either Idle or Break depending on
last bit state. If last bit is dominant new LIN state is Break, otherwise Idle.
In Master mode, Break transmission ongoing.
0100: Break Delimiter
In Slave mode, a valid Break has been detected. See Section 23.7.1.1, LIN control register 1
(LINCR1) for break length configuration (10-bit or 11-bit). Waiting for a rising edge.
In Master mode, Break transmission has been completed. Break Delimiter transmission is
ongoing.
0101: Synch Field
In Slave mode, a valid Break Delimiter has been detected (recessive state for at least one bit
time). Receiving Synch Field.
In Master mode, Synch Field transmission is ongoing.
0110: Identifier Field
In Slave mode, a valid Synch Field has been received. Receiving Identifier Field.
In Master mode, identifier transmission is ongoing.
0111: Header reception/transmission completed
In Slave mode, a valid header has been received and identifier field is available in the BIDR.
In Master mode, header transmission is completed.
1000: Data reception/transmission
Response reception/transmission is ongoing.
1001: Checksum
Data reception/transmission completed. Checksum reception/transmission ongoing.
In UART mode, only the following states are flagged by the LIN state bits:
• Init
• Sleep
• Idle
• Data transmission/reception
RMB
Release Message Buffer
0 Buffer is free.
1 Buffer ready to be read by software. This bit must be cleared by software after reading data
received in the buffer.
This bit is cleared by hardware in Initialization mode.
RBSY
Receiver Busy Flag
0 Receiver is idle
1 Reception ongoing
Note: In Slave mode, after header reception, if BIDR[DIR] = 0 and reception starts then this bit
is set. In this case, user cannot program LINCR2[DTRQ] = 1.
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Chapter 23 LIN Controller (LINFlex)
Table 23-8. LINSR field descriptions (continued)
Field
Description
RPS
LIN receive pin state
This bit reflects the current status of LINRX pin for diagnostic purposes.
WUF
Wake-up Flag
This bit is set by hardware and indicates to the software that LINFlex has detected a falling edge
on the LINRX pin when:
• Slave is in Sleep mode
• Master is in Sleep mode or idle state
This bit must be cleared by software. It is reset by hardware in Initialization mode. An interrupt is
generated if WUIE bit in LINIER is set.
DBFF
Data Buffer Full Flag
This bit is set by hardware and indicates the buffer is full. It is set only when receiving extended
frames (DFL > 7).
This bit must be cleared by software.
It is reset by hardware in Initialization mode.
DBEF
Data Buffer Empty Flag
This bit is set by hardware and indicates the buffer is empty. It is set only when transmitting
extended frames (DFL > 7).
This bit must be cleared by software, once buffer has been filled again, in order to start
transmission.
This bit is reset by hardware in Initialization mode.
DRF
Data Reception Completed Flag
This bit is set by hardware and indicates the data reception is completed.
This bit must be cleared by software.
It is reset by hardware in Initialization mode.
Note: This flag is not set in case of bit error or framing error.
DTF
Data Transmission Completed Flag
This bit is set by hardware and indicates the data transmission is completed.
This bit must be cleared by software.
It is reset by hardware in Initialization mode.
Note: This flag is not set in case of bit error if IOBE bit is reset.
HRF
Header Reception Flag
This bit is set by hardware and indicates a valid header reception is completed.
This bit must be cleared by software.
This bit is reset by hardware in Initialization mode and at end of completed or aborted frame.
Note: If filters are enabled, this bit is set only when identifier software filtering is required, that is
to say:
• All filters are inactive and BF bit in LINCR1 is set
• No match in any filter and BF bit in LINCR1 is set
• TX filter match
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Chapter 23 LIN Controller (LINFlex)
23.7.1.4
LIN error status register (LINESR)
Offset: 0x000C
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
NF
W
Reset
R SZF OCF BEF CEF SFEF BDEF IDPEF FEF BOF
W w1c
Reset
0
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
0
0
0
0
0
0
0
0
w1c
0
0
0
0
0
0
0
Figure 23-9. LIN error status register (LINESR)
Table 23-9. LINESR field descriptions
Field
Description
SZF
Stuck at Zero Flag
This bit is set by hardware when the bus is dominant for more than a 100-bit time. If the dominant
state continues, SZF flag is set again after 87-bit time. It is cleared by software.
OCF
Output Compare Flag
0 No output compare event occurred
1 The content of the counter has matched the content of OC1[0:7] or OC2[0:7] in LINOCR. If this
bit is set and IOT bit in LINTCSR is set, LINFlex moves to Idle state.
If LTOM bit in LINTCSR is set, then OCF is cleared by hardware in Initialization mode. If LTOM bit is
cleared, then OCF maintains its status whatever the mode is.
BEF
Bit Error Flag
This bit is set by hardware and indicates to the software that LINFlex has detected a bit error. This
error can occur during response field transmission (Slave and Master modes) or during header
transmission (in Master mode).
This bit is cleared by software.
CEF
Checksum Error Flag
This bit is set by hardware and indicates that the received checksum does not match the hardware
calculated checksum.
This bit is cleared by software.
Note: This bit is never set if CCD or CFD bit in LINCR1 is set.
SFEF
Synch Field Error Flag
This bit is set by hardware and indicates that a Synch Field error occurred (inconsistent Synch Field).
BDEF
Break Delimiter Error Flag
This bit is set by hardware and indicates that the received Break Delimiter is too short (less than one
bit time).
IDPEF
Identifier Parity Error Flag
This bit is set by hardware and indicates that a Identifier Parity error occurred.
Note: Header interrupt is triggered when SFEF or BDEF or IDPEF bit is set and HEIE bit in LINIER
is set.
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Chapter 23 LIN Controller (LINFlex)
Table 23-9. LINESR field descriptions (continued)
Field
Description
FEF
Framing Error Flag
This bit is set by hardware and indicates to the software that LINFlex has detected a framing error
(invalid stop bit). This error can occur during reception of any data in the response field (Master or
Slave mode) or during reception of Synch Field or Identifier Field in Slave mode.
BOF
Buffer Overrun Flag
This bit is set by hardware when a new data byte is received and the buffer full flag is not cleared. If
RBLM in LINCR1 is set then the new byte received is discarded. If RBLM is reset then the new byte
overwrites the buffer. It can be cleared by software.
NF
23.7.1.5
Noise Flag
This bit is set by hardware when noise is detected on a received character. This bit is cleared by
software.
UART mode control register (UARTCR)
Offset: 0x0010
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
OP
PCE
0
0
W
Reset
R
0
0
TDFL
RDFL
RXEN TXEN
WL UART
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 23-10. UART mode control register (UARTCR)
Table 23-10. UARTCR field descriptions
Field
Description
TDFL
Transmitter Data Field length
This field sets the number of bytes to be transmitted in UART mode. It can be programmed only
when the UART bit is set. TDFL[0:1] = Transmit buffer size – 1.
00 Transmit buffer size = 1.
01 Transmit buffer size = 2.
10 Transmit buffer size = 3.
11 Transmit buffer size = 4.
RDFL
Receiver Data Field length
This field sets the number of bytes to be received in UART mode. It can be programmed only
when the UART bit is set. RDFL[0:1] = Receive buffer size – 1.
00 Receive buffer size = 1.
01 Receive buffer size = 2.
10 Receive buffer size = 3.
11 Receive buffer size = 4.
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Chapter 23 LIN Controller (LINFlex)
Table 23-10. UARTCR field descriptions (continued)
Field
Description
RXEN
Receiver Enable
0 Receiver disable.
1 Receiver enable.
This bit can be programmed only when the UART bit is set.
TXEN
Transmitter Enable
0 Transmitter disable.
1 Transmitter enable.
This bit can be programmed only when the UART bit is set.
Note: Transmission starts when this bit is set and when writing DATA0 in the BDRL register.
OP
Odd Parity
0 Sent parity is even.
1 Sent parity is odd.
This bit can be programmed in Initialization mode only when the UART bit is set.
PCE
Parity Control Enable
0 Parity transmit/check disable.
1 Parity transmit/check enable.
This bit can be programmed in Initialization mode only when the UART bit is set.
WL
Word Length in UART mode
0 7-bit data + parity bit.
1 8-bit data (or 9-bit if PCE is set).
This bit can be programmed in Initialization mode only when the UART bit is set.
UART
23.7.1.6
UART mode enable
0 LIN mode.
1 UART mode.
This bit can be programmed in Initialization mode only.
UART mode status register (UARTSR)
Offset: 0x0014
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R SZF OCF PE3
PE2
PE1
PE0 RMB FEF BOF RPS WUF
0
0
W w1c
R
W
Reset
Reset
0
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
0
0
0
0
0
0
0
0
0
0
0
0
DRF DTF
NF
w1c
w1c
w1c
0
0
0
Figure 23-11. UART mode status register (UARTSR)
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Chapter 23 LIN Controller (LINFlex)
Table 23-11. UARTSR field descriptions
Field
Description
SZF
Stuck at Zero Flag
This bit is set by hardware when the bus is dominant for more than a 100-bit time. It is cleared by
software.
OCF
OCF Output Compare Flag
0 No output compare event occurred.
1 The content of the counter has matched the content of OC1[0:7] or OC2[0:7] in LINOCR.
An interrupt is generated if the OCIE bit in LINIER register is set.
PE3
Parity Error Flag Rx3
This bit indicates if there is a parity error in the corresponding received byte (Rx3). See
Section 23.8.1.1, Buffer in UART mode. No interrupt is generated if this error occurs.
0 No parity error.
1 Parity error.
PE2
Parity Error Flag Rx2
This bit indicates if there is a parity error in the corresponding received byte (Rx2). See
Section 23.8.1.1, Buffer in UART mode. No interrupt is generated if this error occurs.
0 No parity error.
1 Parity error.
PE1
Parity Error Flag Rx1
This bit indicates if there is a parity error in the corresponding received byte (Rx1). See
Section 23.8.1.1, Buffer in UART mode. No interrupt is generated if this error occurs.
0 No parity error.
1 Parity error.
PE0
Parity Error Flag Rx0
This bit indicates if there is a parity error in the corresponding received byte (Rx0). See
Section 23.8.1.1, Buffer in UART mode. No interrupt is generated if this error occurs.
0 No parity error.
1 Parity error.
RMB
Release Message Buffer
0 Buffer is free.
1 Buffer ready to be read by software. This bit must be cleared by software after reading data
received in the buffer.
This bit is cleared by hardware in Initialization mode.
FEF
Framing Error Flag
This bit is set by hardware and indicates to the software that LINFlex has detected a framing error
(invalid stop bit).
BOF
Buffer Overrun Flag
This bit is set by hardware when a new data byte is received and the buffer full flag is not cleared.
If RBLM in LINCR1 is set then the new byte received is discarded. If RBLM is reset then the new
byte overwrites buffer. it can be cleared by software.
RPS
LIN Receive Pin State
This bit reflects the current status of LINRX pin for diagnostic purposes.
WUF
Wake-up Flag
This bit is set by hardware and indicates to the software that LINFlex has detected a falling edge
on the LINRX pin in Sleep mode.
This bit must be cleared by software. It is reset by hardware in Initialization mode.
An interrupt i generated if WUIE bit in LINIER is set.
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Chapter 23 LIN Controller (LINFlex)
Table 23-11. UARTSR field descriptions (continued)
Field
Description
DRF
Data Reception Completed Flag
This bit is set by hardware and indicates the data reception is completed, that is, the number of
bytes programmed in RDFL[0:1] in UARTCR have been received.
This bit must be cleared by software.
It is reset by hardware in Initialization mode.
An interrupt is generated if DRIE bit in LINIER is set.
Note: In UART mode, this flag is set in case of framing error, parity error or overrun.
DTF
Data Transmission Completed Flag
This bit is set by hardware and indicates the data transmission is completed, that is, the number of
bytes programmed in TDFL[0:1] have been transmitted.
This bit must be cleared by software.
It is reset by hardware in Initialization mode.
An interrupt is generated if DTIE bit in LINIER is set.
NF
Noise Flag
This bit is set by hardware when noise is detected on a received character. This bit is cleared by
software.
23.7.1.7
LIN timeout control status register (LINTCSR)
Offset: 0x0018
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
LTOM
IOT
TOCE
0
0
0
0
0
0
0
W
Reset
R
CNT
W
Reset
0
0
0
0
0
0
0
1
0
Figure 23-12. LIN timeout control status register (LINTCSR)
Table 23-12. LINTCSR field descriptions
Field
LTOM
IOT
Description
LIN timeout mode
0 LIN timeout mode (header, response and frame timeout detection).
1 Output compare mode.
This bit can be set/cleared in Initialization mode only.
Idle on Timeout
0 LIN state machine not reset to Idle on timeout event.
1 LIN state machine reset to Idle on timeout event.
This bit can be set/cleared in Initialization mode only.
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Chapter 23 LIN Controller (LINFlex)
Table 23-12. LINTCSR field descriptions (continued)
Field
Description
TOCE
Timeout counter enable
0 Timeout counter disable. OCF bit in LINESR or UARTSR is not set on an output compare
event.
1 Timeout counter enable. OCF bit is set if an output compare event occurs.
TOCE bit is configurable by software in Initialization mode. If LIN state is not Init and if timer is in
LIN timeout mode, then hardware takes control of TOCE bit.
CNT
23.7.1.8
Counter Value
This field indicates the LIN timeout counter value.
LIN output compare register (LINOCR)
Offset: 0x001C
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1
1
1
W
Reset
R
OC21
OC11
W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
If LINTCSR[LTOM] = 0, this field is read-only.
Figure 23-13. LIN output compare register (LINOCR)
Table 23-13. LINOCR field descriptions
Field
Description
OC2
Output compare 2 value
These bits contain the value to be compared to the value of bits CNT[0:7] in LINTCSR.
OC1
Output compare 1 value
These bits contain the value to be compared to the value of bits CNT[0:7] in LINTCSR.
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Chapter 23 LIN Controller (LINFlex)
23.7.1.9
LIN timeout control register (LINTOCR)
Offset: 0x0020
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
1
0
0
W
Reset
R
0
RTO
HTO
W
Reset
0
0
0
0
1
1
1
0
0
0
1
0
1
Figure 23-14. LIN timeout control register (LINTOCR)
Table 23-14. LINTOCR field descriptions
Field
Description
RTO
Response timeout value
This field contains the response timeout duration (in bit time) for 1 byte.
The reset value is 0xE = 14, corresponding to TResponse_Maximum = 1.4 × TResponse_Nominal
HTO
Header timeout value
This field contains the header timeout duration (in bit time). This value does not include the Break
and the Break Delimiter. The reset value is the 0x2C = 44, corresponding to THeader_Maximum.
Programming LINSR[MME] = 1 changes the HTO value to 0x1C = 28.
This field can be written only in Slave mode.
23.7.1.10 LIN fractional baud rate register (LINFBRR)
Offset: 0x0024
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
DIV_F
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 23-15. LIN fractional baud rate register (LINFBRR)
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Chapter 23 LIN Controller (LINFlex)
Table 23-15. LINFBRR field descriptions
Field
Description
DIV_F
Fraction bits of LFDIV
The 4 fraction bits define the value of the fraction of the LINFlex divider (LFDIV).
Fraction (LFDIV) = Decimal value of DIV_F / 16.
This field can be written in Initialization mode only.
23.7.1.11 LIN integer baud rate register (LINIBRR)
Offset: 0x0028
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
R
W
Reset
R
DIV_M
W
Reset
0
0
0
0
0
0
0
0
0
0
Figure 23-16. LIN integer baud rate register (LINIBRR)
Table 23-16. LINIBRR field descriptions
Field
Description
DIV_M
LFDIV mantissa
This field defines the LINFlex divider (LFDIV) mantissa value (see Table 23-17). This field can be
written in Initialization mode only.
Table 23-17. Integer baud rate selection
DIV_M[0:12]
Mantissa
0x0000
LIN clock disabled
0x0001
1
...
...
0x1FFE
8190
ox1FFF
8191
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Chapter 23 LIN Controller (LINFlex)
23.7.1.12 LIN checksum field register (LINCFR)
Offset: 0x002C
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
R
W
Reset
R
CF
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Figure 23-17. LIN checksum field register (LINCFR)
Table 23-18. LINCFR field descriptions
Field
Description
CF
Checksum bits
When LINCR1[CCD] = 0, this field is read-only. When LINCR1[CCD] = 1, this field is read/write.
See Table 23-4.
23.7.1.13 LIN control register 2 (LINCR2)
Offset: 0x0030
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
0
IOBE IOPE
W
Reset
WURQ DDRQ DTRQ ABRQ HTRQ
0
1
1
0
0
0
0
0
Figure 23-18. LIN control register 2 (LINCR2)
Table 23-19. LINCR2 field descriptions
Field
IOBE
Description
Idle on Bit Error
0 Bit error does not reset LIN state machine.
1 Bit error reset LIN state machine.
This bit can be set/cleared in Initialization mode only.
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Chapter 23 LIN Controller (LINFlex)
Table 23-19. LINCR2 field descriptions (continued)
Field
Description
IOPE
Idle on Identifier Parity Error
0 Identifier Parity error does not reset LIN state machine.
1 Identifier Parity error reset LIN state machine.
This bit can be set/cleared in Initialization mode only.
WURQ
Wake-up Generation Request
Setting this bit generates a wake-up pulse. It is reset by hardware when the wake-up character
has been transmitted. The character sent is copied from DATA0 in BDRL buffer. Note that this bit
cannot be set in Sleep mode. Software has to exit Sleep mode before requesting a wake-up. Bit
error is not checked when transmitting the wake-up request.
DDRQ
Data Discard Request
Set by software to stop data reception if the frame does not concern the node. This bit is reset by
hardware once LINFlex has moved to idle state. In Slave mode, this bit can be set only when HRF
bit in LINSR is set and identifier did not match any filter.
DTRQ
Data Transmission Request
Set by software in Slave mode to request the transmission of the LIN Data field stored in the Buffer
data register. This bit can be set only when HRF bit in LINSR is set.
Cleared by hardware when the request has been completed or aborted or on an error condition.
In Master mode, this bit is set by hardware when BIDR[DIR] = 1 and header transmission is
completed.
ABRQ
Abort Request
Set by software to abort the current transmission.
Cleared by hardware when the transmission has been aborted. LINFlex aborts the transmission
at the end of the current bit.
This bit can also abort a wake-up request.
It can also be used in UART mode.
HTRQ
Header Transmission Request
Set by software to request the transmission of the LIN header.
Cleared by hardware when the request has been completed or aborted.
This bit has no effect in UART mode.
23.7.1.14 Buffer identifier register (BIDR)
Offset: 0x0034
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
DIR
CCS
0
0
0
0
0
W
Reset
R
DFL
ID
W
Reset
0
0
0
0
0
0
0
0
0
0
0
Figure 23-19. Buffer identifier register (BIDR)
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Table 23-20. BIDR field descriptions
Field
Description
DFL
Data Field Length
This field defines the number of data bytes in the response part of the frame.
DFL = Number of data bytes – 1.
Normally, LIN uses only DFL[2:0] to manage frames with a maximum of 8 bytes of data. Identifier
filters are compatible with DFL[2:0] only. DFL[5:3] are provided to manage extended frames.
DIR
Direction
This bit controls the direction of the data field.
0 LINFlex receives the data and copies them in the BDR registers.
1 LINFlex transmits the data from the BDR registers.
CCS
Classic Checksum
This bit controls the type of checksum applied on the current message.
0 Enhanced Checksum covering Identifier and Data fields. This is compatible with LIN
specification 2.0 and higher.
1 Classic Checksum covering Data fields only. This is compatible with LIN specification 1.3 and
earlier.
In LIN slave mode (MME bit cleared in LINCR1), this bit must be configured before the header
reception. If the slave has to manage frames with 2 types of checksum, filters must be configured.
ID
Identifier
Identifier part of the identifier field without the identifier parity.
23.7.1.15 Buffer data register LSB (BDRL)
Offset: 0x0038
0
Access: User read/write
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
DATA3
DATA2
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
R
DATA1
DATA0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 23-20. Buffer data register LSB (BDRL)
Table 23-21. BDRL field descriptions
Field
Description
DATA3
Data Byte 3
Data byte 3 of the data field.
DATA2
Data Byte 2
Data byte 2 of the data field.
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Table 23-21. BDRL field descriptions (continued)
Field
Description
DATA1
Data Byte 1
Data byte 1 of the data field.
DATA0
Data Byte 0
Data byte 0 of the data field.
23.7.1.16 Buffer data register MSB (BDRM)
Offset: 0x003C
0
Access: User read/write
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
DATA7
DATA6
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
R
DATA5
DATA4
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 23-21. Buffer data register MSB (BDRM)
Table 23-22. BDRM field descriptions
Field
Description
DATA7
Data Byte 7
Data byte 7 of the data field.
DATA6
Data Byte 6
Data byte 6 of the data field.
DATA5
Data Byte 5
Data byte 5 of the data field.
DATA4
Data Byte 4
Data byte 4 of the data field.
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23.7.1.17 Identifier filter enable register (IFER)
Offset: 0x0040
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
FACT
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 23-22. Identifier filter enable register (IFER)
Table 23-23. IFER field descriptions
Field
Description
FACT
Filter activation (see Table 23-24)
0 Filters 2n and 2n + 1 are deactivated.
1 Filters 2n and 2n + 1 are activated.
This field can be set/cleared in Initialization mode only.
Table 23-24. IFER[FACT] configuration
Bit
Value
FACT[0]
0
Filters 0 and 1 are deactivated.
1
Filters 0 and 1 are activated.
0
Filters 2 and 3 are deactivated.
1
Filters 2 and 3 are activated.
0
Filters 4 and 5 are deactivated.
1
Filters 4 and 5 are activated.
0
Filters 6 and 7 are deactivated.
1
Filters 6 and 7 are activated.
0
Filters 8 and 9 are deactivated.
1
Filters 8 and 9 are activated.
0
Filters 10 and 11 are deactivated.
1
Filters 10 and 11 are activated.
0
Filters 12 and 13 are deactivated.
1
Filters 12 and 13 are activated.
FACT[1]
FACT[2]
FACT[3]
FACT[4]
FACT[5]
FACT[6]
Result
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Table 23-24. IFER[FACT] configuration (continued)
Bit
Value
Result
FACT[7]
0
Filters 14 and 15 are deactivated.
1
Filters 14 and 15 are activated.
23.7.1.18 Identifier filter match index (IFMI)
Address: Base + 0x0044
R
Access: User read-only
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
IFMI[0:4]
W
Reset
0
0
0
Figure 23-23. Identifier filter match index (IFMI)
Table 23-25. IFMI field descriptions
Field
0:26
IFMI[0:4]
27:31
Description
Reserved
Filter match index
This register contains the index corresponding to the received identifier. It can be used to directly
write or read the data in SRAM (see Section 23.8.2.2, Slave mode for more details).
When no filter matches, IFMI[0:4] = 0. When Filter n is matching, IFMI[0:4] = n + 1.
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23.7.1.19 Identifier filter mode register (IFMR)
Offset: 0x0048
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
IFM
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Figure 23-24. Identifier filter mode register (IFMR)
Table 23-26. IFMR field descriptions
Field
IFM
Description
Filter mode (see Table 23-27).
0 Filters 2n and 2n + 1 are in identifier list mode.
1 Filters 2n and 2n + 1 are in mask mode (filter 2n + 1 is the mask for the filter 2n).
Table 23-27. IFMR[IFM] configuration
Bit
Value
IFM[0]
0
Filters 0 and 1 are in identifier list mode.
1
Filters 0 and 1 are in mask mode (filter 1 is the mask for the filter 0).
0
Filters 2 and 3 are in identifier list mode.
1
Filters 2 and 3 are in mask mode (filter 3 is the mask for the filter 2).
0
Filters 4 and 5 are in identifier list mode.
1
Filters 4 and 5 are in mask mode (filter 5 is the mask for the filter 4).
0
Filters 6 and 7 are in identifier list mode.
1
Filters 6 and 7 are in mask mode (filter 7 is the mask for the filter 6).
0
Filters 8 and 9 are in identifier list mode.
1
Filters 8 and 9 are in mask mode (filter 9 is the mask for the filter 8).
0
Filters 10 and 11 are in identifier list mode.
1
Filters 10 and 11 are in mask mode (filter 11 is the mask for the filter 10).
0
Filters 12 and 13 are in identifier list mode.
1
Filters 12 and 13 are in mask mode (filter 13 is the mask for the filter 12).
IFM[1]
IFM[2]
IFM[3]
IFM[4]
IFM[5]
IFM[6]
Result
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Table 23-27. IFMR[IFM] configuration (continued)
Bit
Value
Result
IFM[7]
0
Filters 14 and 15 are in identifier list mode.
1
Filters 14 and 15 are in mask mode (filter 15 is the mask for the filter 14).
23.7.1.20 Identifier filter control register (IFCR2n)
Offsets: 0x004C–0x0084 (8 registers)
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
DIR
CCS
0
0
0
W
Reset
R
DFL
ID
W
w1c
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 23-25. Identifier filter control register (IFCR2n)
NOTE
This register can be written in Initialization mode only.
Table 23-28. IFCR2n field descriptions
Field
Description
DFL
Data Field Length
This field defines the number of data bytes in the response part of the frame.
DIR
Direction
This bit controls the direction of the data field.
0 LINFlex receives the data and copies them in the BDRL and BDRM registers.
1 LINFlex transmits the data from the BDRL and BDRM registers.
CCS
Classic Checksum
This bit controls the type of checksum applied on the current message.
0 Enhanced Checksum covering Identifier and Data fields. This is compatible with LIN specification
2.0 and higher.
1 Classic Checksum covering Data fields only. This is compatible with LIN specification 1.3 and
earlier.
ID
Identifier
Identifier part of the identifier field without the identifier parity.
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23.7.1.21 Identifier filter control register (IFCR2n + 1)
Offsets: 0x0050–0x0088 (8 registers)
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
DIR
CCS
0
0
0
W
Reset
R
DFL
ID
W
w1c
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 23-26. Identifier filter control register (IFCR2n + 1)
NOTE
This register can be written in Initialization mode only.
Table 23-29. IFCR2n + 1 field descriptions
Field
Description
DFL
Data Field Length
This field defines the number of data bytes in the response part of the frame.
DFL = Number of data bytes – 1.
DIR
Direction
This bit controls the direction of the data field.
0 LINFlex receives the data and copies them in the BDRL and BDRM registers.
1 LINFlex transmits the data from the BDRL and BDRM registers.
CCS
Classic Checksum
This bit controls the type of checksum applied on the current message.
0 Enhanced Checksum covering Identifier and Data fields. This is compatible with LIN
specification 2.0 and higher.
1 Classic Checksum covering Data field only. This is compatible with LIN specification 1.3 and
earlier.
ID
Identifier
Identifier part of the identifier field without the identifier parity
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Chapter 23 LIN Controller (LINFlex)
23.8
Functional description
23.8.1
UART mode
The main features in the UART mode are
• Full duplex communication
• 8- or 9-bit data with parity
• 4-byte buffer for reception, 4-byte buffer for transmission
• 8-bit counter for timeout management
8-bit data frames: The 8th bit can be a data or a parity bit. Even/Odd Parity can be selected by the Odd
Parity bit in the UARTCR. An even parity is set if the modulo-2 sum of the 7 data bits is 1. An odd parity
is cleared in this case.
Byte Field
Start
bit
D0
D1
D2
D3
D4
D5
D6
Stop
bit
D7
— Data bit
— Parity bit
Figure 23-27. UART mode 8-bit data frame
9-bit frames: The 9th bit is a parity bit. Even/Odd Parity can be selected by the Odd Parity bit in the
UARTCR. An even parity is set if the modulo-2 sum of the 8 data bits is 1. An odd parity is cleared in this
case.
Byte Field
Start
bit
D0
D1
D2
D3
D4
D5
D6
D7
D8
Stop
bit
— Parity bit
Figure 23-28. UART mode 9-bit data frame
23.8.1.1
Buffer in UART mode
The 8-byte buffer is divided into two parts: one for receiver and one for transmitter, as shown in
Table 23-30.
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Table 23-30. Message buffer
Buffer data
register
BDRL[0:31]
LIN mode
Transmit/Receive
buffer
BDRM[0:31]
23.8.1.2
DATA0[0:7]
UART mode
Transmit buffer
Tx0
DATA1[0:7]
Tx1
DATA2[0:7]
Tx2
DATA3[0:7]
Tx3
DATA4[0:7]
Receive buffer
Rx0
DATA5[0:7]
Rx1
DATA6[0:7]
Rx2
DATA7[0:7]
Rx3
UART transmitter
In order to start transmission in UART mode, you must program the UART bit and the transmitter enable
(TXEN) bit in the UARTCR to 1. Transmission starts when DATA0 (least significant data byte) is
programmed. The number of bytes transmitted is equal to the value configured by UARTCR[TDFL] (see
Table 23-10).
The Transmit buffer is 4 bytes, hence a 4-byte maximum transmission can be triggered. Once the
programmed number of bytes has been transmitted, the UARTSR[DTF] bit is set. If UARTCR[TXEN] is
reset during a transmission then the current transmission is completed and no further transmission can be
invoked.
23.8.1.3
UART receiver
The UART receiver is active as soon as the user exits Initialization mode and programs
UARTCR[RXEN] = 1. There is a dedicated 4-byte data buffer for received data bytes. Once the
programmed number (RDFL bits) of bytes has been received, the UARTSR[DRF] bit is set. If the RXEN
bit is reset during a reception then the current reception is completed and no further reception can be
invoked until RXEN is set.
If a parity error occurs during reception of any byte, then the corresponding PEx bit in the UARTSR is set.
No interrupt is generated in this case. If a framing error occurs in any byte (UARTSR[FE] = 1) then an
interrupt is generated if the LINIER[FEIE] bit is set.
If the last received frame has not been read from the buffer (that is, RMB bit is not reset by the user) then
upon reception of the next byte an overrun error occurs (UARTSR[BOF] = 1) and one message will be
lost. Which message is lost depends on the configuration of LINCR1[RBLM].
• If the buffer lock function is disabled (LINCR1[RBLM] = 0), the last message stored in the buffer
is overwritten by the new incoming message. In this case the latest message is always available to
the application.
• If the buffer lock function is enabled (LINCR1[RBLM] = 1), the most recent message is discarded
and the previous message is available in the buffer.
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Chapter 23 LIN Controller (LINFlex)
An interrupt is generated if the LINIER[BOIE] bit is set.
23.8.1.4
Clock gating
The LINFlex clock can be gated from the Mode Entry module (MC_ME). In UART mode, the LINFlex
controller acknowledges a clock gating request once the data transmission and data reception are
completed, that is, once the Transmit buffer is empty and the Receive buffer is full.
23.8.2
LIN mode
LIN mode comprises four submodes:
• Master mode
• Slave mode
• Slave mode with identifier filtering
• Slave mode with automatic resynchronization
These submodes are described in the following pages.
23.8.2.1
Master mode
In Master mode the application uses the message buffer to handle the LIN messages. Master mode is
selected when the LINCR1[MME] bit is set.
23.8.2.1.1
LIN header transmission
According to the LIN protocol any communication on the LIN bus is triggered by the Master sending a
header. The header is transmitted by the Master task while the data is transmitted by the Slave task of a
node.
To transmit a header with LINFlex, the application must set up the identifier and the data field length, and
configure the message (direction and checksum type) in the BIDR before requesting the header
transmission by setting LINCR2[HTRQ].
23.8.2.1.2
Data transmission (transceiver as publisher)
When the master node is publisher of the data corresponding to the identifier sent in the header, then the
slave task of the master has to send the data in the Response part of the LIN frame. Therefore, the
application must provide the data to LINFlex before requesting the header transmission. The application
stores the data in the message buffer BDR. According to the data field length, LINFlex transmits the data
and the checksum. The application uses the BDR[CCS] bit to configure the checksum type (classic or
enhanced) for each message.
If the response has been sent successfully, the LINSR[DTF] bit is set. In case of error, the DTF flag is not
set and the corresponding error flag is set in the LINESR (see Section 23.8.2.1.6, Error handling).
It is possible to handle frames with a Response size larger than 8 bytes of data (extended frames). If the
data field length in the BIDR is configured with a value higher than 8 data bytes, the LINSR[DBEF] bit is
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Chapter 23 LIN Controller (LINFlex)
set after the first 8 bytes have been transmitted. The application has to update the buffer BDR before
resetting the DBEF bit. The transmission of the next bytes starts when the DBEF bit is reset.
After the last data byte (or the checksum byte) has been sent, the DTF flag is set.
The direction of the message buffer is controlled by the BIDR[DIR] bit. When the application sets this bit
the response is sent by LINFlex (publisher). Resetting this bit configures the message buffer as subscriber.
23.8.2.1.3
Data reception (transceiver as subscriber)
To receive data from a slave node, the master sends a header with the corresponding identifier. LINFlex
stores the data received from the slave in the message buffer and stores the message status in the LINSR.
If the response has been received successfully, the LINSR[DRF] is set. In case of error, the DRF flag is not
set and the corresponding error flag is set in the LINESR (see Section 23.8.2.1.6, Error handling).
It is possible to handle frames with a Response size larger than 8 bytes of data (extended frames). If the
data field length in the BIDR is configured with a value higher than 8 data bytes, the LINSR[DBFF] bit is
set once the first 8 bytes have been received. The application has to read the buffer BDR before resetting
the DBFF bit. Once the last data byte (or the checksum byte) has been received, the DRF flag is set.
23.8.2.1.4
Data discard
To discard data from a slave, the BIDR[DIR] bit must be reset and the LINCR2[DDRQ] bit must be set
before starting the header transmission.
23.8.2.1.5
Error detection
LINFlex is able to detect and handle LIN communication errors. A code stored in the LIN error status
register (LINESR) signals the errors to the software.
In Master mode, the following errors are detected:
• Bit error: During transmission, the value read back from the bus differs from the transmitted value.
• Framing error: A dominant state has been sampled on the stop bit of the currently received
character (synch field, identifier field or data field).
• Checksum error: The computed checksum does not match the received one.
• Response and Frame timeout: See Section 23.8.3, 8-bit timeout counter, for more details.
23.8.2.1.6
Error handling
In case of Bit Error detection during transmission, LINFlex stops the transmission of the frame after the
corrupted bit. LINFlex returns to idle state and an interrupt is generated if LINIER[BEIE] = 1.
During reception, a Framing Error leads LINFlex to discard the current frame. LINFlex returns
immediately to idle state. An interrupt is generated if LINIER[FEIE] = 1.
During reception, a Checksum Error leads LINFlex to discard the received frame. LINFlex returns to idle
state. An interrupt is generated if LINIER[CEIE] = 1.
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Chapter 23 LIN Controller (LINFlex)
23.8.2.1.7
Overrun
After the message buffer is full, the next valid message reception causes an overrun and a message is lost.
The LINFlexD controller sets LINSR[BOF] to signal the overrun condition. Which message is lost
depends on the configuration of the RX message buffer:
• If the buffer lock function is disabled (LINCR1[RBLM] cleared), the last message stored in the
buffer is overwritten by the new incoming message. In this case, the latest message is always
available to the software.
• If the buffer lock function is enabled (LINCR1[RBLM] set), the most recent message is discarded
and the previous message is available in the buffer.
23.8.2.2
Slave mode
In Slave mode the application uses the message buffer to handle the LIN messages. Slave mode is selected
when LINCR1[MME] = 0.
23.8.2.2.1
Data transmission (transceiver as publisher)
When LINFlex receives the identifier, the LINSR[HRF] is set and, if LINIER[HRIE] = 1, an RX interrupt
is generated. The software must read the received identifier in the BIDR, fill the BDR registers, specify
the data field length using the BIDR[DFL], and trigger the data transmission by setting the
LINCR2[DTRQ] bit.
One or several identifier filters can be configured for transmission by setting the IFCRx[DIR] bit and
activated by setting one or several bits in the IFER.
When at least one identifier filter is configured in transmission and activated, and if the received identifier
matches the filter, a specific TX interrupt (instead of an RX interrupt) is generated.
Typically, the application has to copy the data from SRAM locations to the BDAR. To copy the data to the
right location, the application has to identify the data by means of the identifier. To avoid this and to ease
the access to the SRAM locations, the LINFlex controller provides a Filter Match Index. This index value
is the number of the filter that matched the received identifier.
The software can use the index in the IFMI register to directly access the pointer that points to the right
data array in the SRAM area and copy this data to the BDAR (see Figure 23-30).
Using a filter avoids the software having to configure the direction, the data field length and the checksum
type in the BIDR. The software fills the BDAR and triggers the data transmission by programming
LINCR2[DTRQ] = 1.
If LINFlex cannot provide enough TX identifier filters to handle all identifiers the software has to transmit
data for, then a filter can be configured in mask mode (see Section 23.8.2.3, Slave mode with identifier
filtering) in order to manage several identifiers with one filter only.
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Chapter 23 LIN Controller (LINFlex)
23.8.2.2.2
Data reception (transceiver as subscriber)
When LINFlex receives the identifier, the LINSR[HRF] bit is set and, if LINIER[HRIE] = 1, an RX
interrupt is generated. The software must read the received identifier in the BIDR and specify the data field
length using the BIDR[DFL] field before receiving the stop bit of the first byte of data field.
When the checksum reception is completed, an RX interrupt is generated to allow the software to read the
received data in the BDR registers.
One or several identifier filters can be configured for reception by programming IFCRx[DIR] = 0 and
activated by setting one or several bits in the IFER.
When at least one identifier filter is configured in reception and activated, and if the received identifier
matches the filter, an RX interrupt is generated after the checksum reception only.
Typically, the application has to copy the data from the BDAR to SRAM locations. To copy the data to the
right location, the application has to identify the data by means of the identifier. To avoid this and to ease
the access to the SRAM locations, the LINFlex controller provides a Filter Match Index. This index value
is the number of the filter that matched the received identifier.
The software can use the index in the IFMI register to directly access the pointer that points to the right
data array in the SRAM area and copy this data from the BDAR to the SRAM (see Figure 23-30).
Using a filter avoids the software reading the ID value in the BIDR and configuring the direction, the data
field length, and the checksum type in the BIDR.
If LINFlex cannot provide enough RX identifier filters to handle all identifiers the software has to receive
the data for, then a filter can be configured in mask mode (see Section 23.8.2.3, Slave mode with identifier
filtering) in order to manage several identifiers with one filter only.
23.8.2.2.3
Data discard
When LINFlex receives the identifier, the LINSR[HRF] bit is set and, if LINIER[HRIE] = 1, an RX
interrupt is generated. If the received identifier does not concern the node, you must program
LINCR2[DDRQ] = 1. LINFlex returns to idle state after bit DDRQ is set.
23.8.2.2.4
Error detection
In Slave mode, the following errors are detected:
• Header error: An error occurred during header reception (Break Delimiter error, Inconsistent
Synch Field, Header Timeout).
• Bit error: During transmission, the value read back from the bus differs from the transmitted value.
• Framing error: A dominant state has been sampled on the stop bit of the currently received
character (synch field, identifier field or data field).
• Checksum error: The computed checksum does not match the received one.
23.8.2.2.5
Error handling
In case of Bit Error detection during transmission, LINFlex stops the transmission of the frame after the
corrupted bit. LINFlex returns to idle state and an interrupt is generated if the BEIE bit in the LINIER is set.
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During reception, a Framing Error leads LINFlex to discard the current frame. LINFlex returns
immediately to idle state. An interrupt is generated if LINIER[FEIE] = 1.
During reception, a Checksum Error leads LINFlex to discard the received frame. LINFlex returns to idle
state. An interrupt is generated if LINIER[CEIE] = 1.
During header reception, a Break Delimiter error, an Inconsistent Synch Field or a Timeout error leads
LINFlex to discard the header. An interrupt is generated if LINIER[HEIE] = 1. LINFlex returns to idle
state.
23.8.2.2.6
Valid header
A received header is considered as valid when it has been received correctly according to the LIN protocol.
If a valid Break Field and Break Delimiter come before the end of the current header or at any time during
a data field, the current header or data is discarded and the state machine synchronizes on this new break.
23.8.2.2.7
Valid message
A received or transmitted message is considered as valid when the data has been received or transmitted
without error according to the LIN protocol.
23.8.2.2.8
Overrun
Once the message buffer is full, the next valid message reception leads to an overrun and a message is lost.
The hardware sets the BOF bit in the LINSR to signal the overrun condition. Which message is lost
depends on the configuration of the RX message buffer:
• If the buffer lock function is disabled (LINCR1[RBLM] = 0), the last message stored in the buffer
is overwritten by the new incoming message. In this case the latest message is always available to
the application.
• If the buffer lock function is enabled (LINCR1[RBLM] = 0), the most recent message is discarded
and the previous message is available in the buffer.
23.8.2.3
Slave mode with identifier filtering
In the LIN protocol the identifier of a message is not associated with the address of a node but related to
the content of the message. Consequently a transmitter broadcasts its message to all receivers. On header
reception a slave node decides—depending on the identifier value—whether the software needs to receive
or send a response. If the message does not target the node, it must be discarded without software
intervention.
To fulfill this requirement, the LINFlex controller provides configurable filters in order to request software
intervention only if needed. This hardware filtering saves CPU resources that would otherwise be needed
by software for filtering.
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23.8.2.3.1
Filter mode
Usually each of the eight IFCR registers filters one dedicated identifier, but this limits the number of
identifiers LINFlex can handle to the number of IFCR registers implemented in the device. Therefore, in
order to be able to handle more identifiers, the filters can be configured in mask mode.
In identifier list mode (the default mode), both filter registers are used as identifier registers. All bits of the
incoming identifier must match the bits specified in the filter register.
In mask mode, the identifier registers are associated with mask registers specifying which bits of the
identifier are handled as “must match” or as “don’t care”. For the bit mapping and registers organization,
please see Figure 23-29.
Identifier Filter Register Organization
0
15
Identifier
Bit Mapping
IFCRn
DFL
DIR CCS
Identifier Filter Configuration
ID
Identifier Filter Mode
Identifier List Mode
Identifier
Identifier
IFCR2n
IFCR2n + 1
IFM = 0
Mask Mode
Identifier
Mask
IFCR2n
IFCR2n + 1
IFM = 1
Figure 23-29. Filter configuration—register organization
23.8.2.3.2
Identifier filter mode configuration
The identifier filters are configured in the IFCRx registers. To configure an identifier filter the filter must
first be deactivated by programming IFER[FACT] = 0. The identifier list or identifier mask mode for the
corresponding IFCRx registers is configured by the IFMR[IFM] bit. For each filter, the IFCRx register
configures the ID (or the mask), the direction (TX or RX), the data field length, and the checksum type.
If no filter is active, an RX interrupt is generated on any received identifier event.
If at least one active filter is configured as TX, all received identifiers matching this filter generate a TX
interrupt.
If at least one active filter is configured as RX, all received identifiers matching this filter generate an RX
interrupt.
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If no active filter is configured as RX, all received identifiers not matching TX filter(s) generate an RX
interrupt.
Table 23-31. Filter to interrupt vector correlation
Number of Number of active filters Number of active filters
active filters
configured as TX
configured as RX
Interrupt vector
0
0
0
RX interrupt on all identifiers
a
(a > 0)
a
0
— TX interrupt on identifiers
matching the filters,
— RX interrupt on all other
identifiers if BF bit is set, no RX
interrupt if BF bit is reset
n
(n = a + b)
a
(a > 0)
b
(b > 0)
— TX interrupt on identifiers
matching the TX filters,
— RX interrupt on identifiers
matching the RX filters,
— all other identifiers discarded
(no interrupt)
b
(b > 0)
0
b
— RX interrupt on identifiers
matching the filters,
— TX interrupt on all other
identifiers if BF bit is set, no TX
interrupt if BF bit is reset
MESSAGE0
@
MESSAGE1
+
IFMI
DATA
pointers
table
MESSAGE2
SRAM
Figure 23-30. Identifier match index
23.8.2.4
Slave mode with automatic resynchronization
Automatic resynchronization must be enabled in Slave mode if fperiph_set_1_clk tolerance is greater than
1.5%. This feature compensates a fperiph_set_1_clk deviation up to 14%, as specified in LIN standard.
This mode is similar to Slave mode as described in Section 23.8.2.2, Slave mode, with the addition of
automatic resynchronization enabled by the LASE bit. In this mode LINFlex adjusts the fractional baud
rate generator after each Synch Field reception.
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23.8.2.4.1
Automatic resynchronization method
When automatic resynchronization is enabled, after each LIN Break, the time duration between five falling
edges on RDI is sampled on fperiph_set_1_clk and the result of this measurement is stored in an internal 19-bit
register called SM (not user accessible) (see Figure 23-31). Then the LFDIV value (and its associated
registers LINIBRR and LINFBRR) is automatically updated at the end of the fifth falling edge. During
LIN Synch Field measurement, the LINFlex state machine is stopped and no data is transferred to the data
register.
Tperiph_set_1_clk = Clock period
TBR = baud rate period
TBR = 16.LFDIV.Tperiph_set_1_clk
SM = Synch Measurement Register (19 bits)
TBR
LIN Synch Field
LIN Break
Break
delim.
Start
Bit
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Stop
Bit
Next
Start
Bit
Measurement = 8.TBR = SM.Tperiph_set_1_clk
LFDIV(n+1)
LFDIV(n)
LFDIV = TBR / (16.Tperiph_set_1_clk) = Rounding (SM / 128)
Figure 23-31. LIN synch field measurement
LFDIV is an unsigned fixed point number. The mantissa is coded on 12 bits in the LINIBRR and the
fraction is coded on 4 bits in the LINFBRR.
If LASE bit = 1 then LFDIV is automatically updated at the end of each LIN Synch Field.
Three internal registers (not user-accessible) manage the auto-update of the LINFlex divider (LFDIV):
• LFDIV_NOM (nominal value written by software at LINIBRR and LINFBRR addresses)
• LFDIV_MEAS (results of the Field Synch measurement)
• LFDIV (used to generate the local baud rate)
On transition to idle, break or break delimiter state due to any error or on reception of a complete frame,
hardware reloads LFDIV with LFDIV_NOM.
23.8.2.4.2
Deviation error on the Synch Field
The deviation error is checked by comparing the current baud rate (relative to the slave oscillator) with the
received LIN Synch Field (relative to the master oscillator). Two checks are performed in parallel.
The first check is based on a measurement between the first falling edge and the last falling edge of the
Synch Field:
• If D1 > 14.84%, LHE is set.
• If D1 < 14.06%, LHE is not set.
• If 14.06% < D1 < 14.84%, LHE can be either set or reset depending on the dephasing between the
signal on LINFlex_RX pin the fperiph_set_1_clk clock.
The second check is based on a measurement of time between each falling edge of the Synch Field:
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•
If D2 > 18.75%, LHE is set.
If D2 < 15.62%, LHE is not set.
If 15.62% < D2 < 18.75%, LHE can be either set or reset depending on the dephasing between the
signal on LINFlex_RX pin the fperiph_set_1_clk clock.
Note that the LINFlex does not need to check if the next edge occurs slower than expected. This is covered
by the check for deviation error on the full synch byte.
23.8.2.5
Clock gating
The LINFlex clock can be gated from the Mode Entry module (MC_ME). In LIN mode, the LINFlex
controller acknowledges a clock gating request once the frame transmission or reception is completed.
23.8.3
23.8.3.1
8-bit timeout counter
LIN timeout mode
Clearing the LTOM bit (setting its value to 0) in the LINTCSR enables the LIN timeout mode. The
LINOCR becomes read-only, and OC1 and OC2 output compare values in the LINOCR are automatically
updated by hardware.
This configuration detects header timeout, response timeout, and frame timeout.
Depending on the LIN mode (selected by the LINCR1[MME] bit), the 8-bit timeout counter will behave
differently.
LIN timeout mode must not be enabled during LIN extended frames transmission or reception (that is, if
the data field length in the BIDR is configured with a value higher than 8 data bytes).
23.8.3.1.1
LIN Master mode
The LINTOCR[RTO] field can be used to tune response timeout and frame timeout values. Header timeout
value is fixed to HTO = 28-bit time.
Field OC1 checks THeader and TResponse and field OC2 checks TFrame (see Figure 23-32).
When LINFlex moves from Break delimiter state to Synch Field state (see Section 23.7.1.3, LIN status
register (LINSR)):
• OC1 is updated with the value of OCHeader (OCHeader = CNT + 28),
• OC2 is updated with the value of OCFrame (OCFrame = CNT + 28 + RTO × 9 (frame timeout value
for an 8-byte frame),
• The TOCE bit is set.
On the start bit of the first response data byte (and if no error occurred during the header reception), OC1
is updated with the value of OCResponse (OCResponse = CNT + RTO × 9 (response timeout value for an
8-byte frame)).
On the first response byte is received, OC1 and OC2 are automatically updated to check TResponse and
TFrame according to RTO (tolerance) and DFL.
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On the checksum reception or in case of error in the header or response, the TOCE bit is reset.
If there is no response, frame timeout value does not take into account the DFL value, and an 8-byte
response (DFL = 7) is always assumed.
23.8.3.1.2
LIN Slave mode
The LINTOCR[RTO] field can be used to tune response timeout and frame timeout values. Header timeout
value is fixed to HTO.
OC1 checks THeader and TResponse and OC2 checks TFrame (see Figure 23-32).
When LINFlex moves from Break state to Break Delimiter state (see Section 23.7.1.3, LIN status register
(LINSR)):
• OC1 is updated with the value of OCHeader (OCHeader = CNT + HTO),
• OC2 is updated with the value of OCFrame (OCFrame = CNT + HTO + RTO × 9 (frame timeout
value for an 8-byte frame)),
• The TOCE bit is set.
On the start bit of the first response data byte (and if no error occurred during the header reception), OC1
is updated with the value of OCResponse (OCResponse = CNT + RTO × 9 (response timeout value for an
8-byte frame)).
Once the first response byte is received, OC1 and OC2 are automatically updated to check TResponse and
TFrame according to RTO (tolerance) and DFL.
On the checksum reception or in case of error in the header or data field, the TOCE bit is reset.
Frame
Header
Response
Response
space
OC1
OC2
OCHeader
Break
OCResponse
OCFrame
Figure 23-32. Header and response timeout
23.8.3.2
Output compare mode
Setting LINTCSR[LTOM] = 1 enables the output compare mode. This mode allows the user to fully
customize the use of the counter.
OC1 and OC2 output compare values can be updated in the LINTOCR by software.
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23.8.4
Interrupts
Table 23-32. LINFlex interrupt control
Interrupt event
Event flag bit
Enable control bit
Interrupt vector
Header Received interrupt
HRF
HRIE
RXI 1
Data Transmitted interrupt
DTF
DTIE
TXI
Data Received interrupt
DRF
DRIE
RXI
Data Buffer Empty interrupt
DBEF
DBEIE
TXI
Data Buffer Full interrupt
DBFF
DBFIE
RXI
Wake-up interrupt
WUPF
WUPIE
RXI
LIN State interrupt 2
LSF
LSIE
RXI
Buffer Overrun interrupt
BOF
BOIE
ERR
Framing Error interrupt
FEF
FEIE
ERR
Header Error interrupt
HEF
HEIE
ERR
Checksum Error interrupt
CEF
CEIE
ERR
Bit Error interrupt
BEF
BEIE
ERR
Output Compare interrupt
OCF
OCIE
ERR
Stuck at Zero interrupt
SZF
SZIE
ERR
1
In Slave mode, if at least one filter is configured as TX and enabled, header received interrupt vector
is RXI or TXI depending on the value of identifier received.
2
For debug and validation purposes
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Chapter 24 LIN Controller (LINFlexD)
Chapter 24
LIN Controller (LINFlexD)
24.1
Introduction
The LINFlexD (Local Interconnect Network Flexible with DMA support) controller interfaces the LIN
network and supports the LIN protocol versions 1.3, 2.0, 2.1 and J2602 in both Master and Slave modes.
LINFlexD includes a LIN mode that provides additional features (compared to standard UART) to ease
LIN implementation, improve system robustness, minimize CPU load, and allow slave node
resynchronization.
Figure 24-1 shows the LINFlexD block diagram.
REGISTER MODEL / APPLICATION INTERFACE
Message
Buffer
Interface
CONFIG
CONTROL
STATUS
LIN Control
LIN Status
Baud rate
SLAVE
MESSAGE HANDLER
Filter Config.
MASTER
MESSAGE HANDLER
ID Filters(1)
LIN PROTOCOL HANDLER
1
Filter activation optional
Figure 24-1. LINFlexD block diagram
24.2
Main features
The LINFlexD controller can operate in several modes, each of which has a distinct set of features. These
distinct features are described in the following sections.
In addition, the LINFlexD controller has several features common to all modes:
• Fractional baud rate generator
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•
•
•
Three operating modes for power saving and configuration registers lock
— Initialization
— Normal
— Sleep
Two test modes
— Loop Back
— Self Test
Maskable interrupts
24.2.1
•
•
•
•
•
•
•
•
•
•
•
•
Supports LIN protocol versions 1.3, 2.0, 2.1, and J2602
Master mode with autonomous message handling
Classic and enhanced checksum calculation and check
Single 8-byte buffer for transmission/reception
Extended frame mode for In-application Programming purposes
Wake-up event on dominant bit detection
True LIN field state machine
Advanced LIN error detection
Header, response, and frame timeout
Slave mode
— Autonomous header handling
— Autonomous transmit/receive data handling
LIN automatic resynchronization, allowing operation with as clock source
Identifier filters for autonomous message handling in Slave mode
24.2.2
•
•
•
LIN mode features
UART mode features
Full-duplex communication
Selectable frame size:
— 8-bit frame
— 9-bit frame
— 16-bit frame
— 17-bit frame
Selectable parity:
— Even
— Odd
— 0
— 1
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•
4-byte buffer for reception, 4-byte buffer for transmission
12-bit counter for timeout management
24.3
The LIN protocol
The LIN (Local Interconnect Network) is a serial communication protocol. The topology of a LIN network
is shown in Figure 24-2. A LIN network consists of:
• One master
• Several slave
• The LIN bus
A master node contains the master task as well as a slave task, all other nodes contain a slave task only.
The master node decides when and which frame shall be transferred on the bus. The slave task provides
the data to be transported by the frame.
LIN master node
LIN slave node 1
LIN slave node n
MCU
Application
LINFlexD
Controller
LIN
Rx
LIN
Tx
LIN
Transceiver
LIN
LIN Bus
Figure 24-2. LIN network topology
24.3.1
Dominant and recessive logic levels
The LIN bus defines two logic levels, dominant and recessive, as follows:
• Dominant: logical low level (0)
• Recessive: logical high level (1)
24.3.2
LIN frames
A frame consists of a header provided by the master task and a response provided by the slave task, as
shown in Figure 24-3.
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Master Task
Slave Task 1
Header
Header
Response
Slave Task 2
Response
Frame slot
Frame
Header
Response
space
Response
Figure 24-3. LIN frame structure
24.3.3
LIN header
The header consists of:
• A break field (described in Section 24.3.3.1, Break field)
• A sync (described in Section 24.3.3.2, Sync)
• An identifier (described in Section 24.3.4.2, Identifier)
The slave task associated with the identifier provides the response.
24.3.3.1
Break field
The break field, shown in Figure 24-4, is used to signal the beginning of a new frame. It is always
generated by the master and consists of:
• At least 13 dominant bits including the start bit
• At least one recessive bit that functions as break delimiter
Break
Delimiter
Start
bit
Figure 24-4. Break field
24.3.3.2
Sync
The sync pattern is a byte consisting of alternating dominant and recessive bits as shown in Figure 24-5.
It forms a data value of 0x55.
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Stop
Start
bit
bit
Figure 24-5. Sync pattern
24.3.4
Response
The response consists of:
• A data field (described in Section 24.3.4.1, Data field)
• A checksum (described in Section 24.3.4.3, Checksum)
The slave task interested in the data associated with the identifier receives the response and verifies the
checksum.
24.3.4.1
Data field
The structure of the data field transmitted on the LIN bus is shown in Figure 24-6. The LSB of the data is
sent first and the MSB last. The start bit is encoded as a dominant bit and the stop bit is encoded as a
recessive bit.
Byte Field
Start
bit
MSB
LSB
Stop
bit
Figure 24-6. Structure of the data field
24.3.4.2
Identifier
The identifier, shown in Figure 24-7, consists of two subfields:
• The identifier value (in bits 0–5)
• The identifier parity (in bits 6–7)
The parity bits P0 and P1 are defined as follows:
• P0 = ID0 xor ID1 xor ID2 xor ID4
• P1 = not(ID1 xor ID3 xor ID4 xor ID5)
Start
bit
ID0
ID1
ID2
ID3
ID4
ID5
P0
P1
Stop
bit
Figure 24-7. Identifier
24.3.4.3
Checksum
The checksum contains the inverted 8-bit sum (with carry) over one of two possible groups:
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24.4
The classic checksum sums all data bytes, and is used for communication with LIN 1.3 slaves.
The enhanced checksum sums all data bytes and the identifier, and is used for communication with
LIN 2.0 (or later) slaves.
LINFlexD and software intervention
The increasing number of communication peripherals embedded on microcontrollers (for example, CAN,
LIN, SPI) requires more and more CPU resources for the communication management. Even a 32-bit
microcontroller is overloaded if its peripherals do not provide high level features to autonomously handle
the communication.
Even though the LIN protocol with a maximum baud rate of 20 Kbit/s is relatively slow, it still generates
a non-negligible load on the CPU if the LIN is implemented on a standard UART, as is usually the case.
To minimize the CPU load in Master mode, LINFlexD handles the LIN messages autonomously.
In Master mode, once the software has triggered the header transmission, LINFlexD does not request any
software (that is, application) intervention until the next header transmission request in transmission mode
or until the checksum reception in reception mode.
To minimize the CPU load in Slave mode, LINFlexD requires software intervention only to:
• Trigger transmission or reception or data discard depending on the identifier
• Write data into the buffer (transmission mode) or read data from the buffer (reception mode) after
checksum reception
If filter mode is activated for Slave mode, LINFlexD requires software intervention only to write data into
the buffer (transmission mode) or read data from the buffer (reception mode)
The software uses the control, status, and configuration registers to:
• Configure LIN parameters (for example, baud rate or mode)
• Request transmissions
• Handle receptions
• Manage interrupts
• Configure LIN error and timeout detection
• Process diagnostic information
The message buffer stores transmitted or received LIN frames.
24.5
Summary of operating modes
The LINFlexD controller has three operating modes:
• Normal
• Initialization
• Sleep
After a hardware reset, the LINFlexD controller is in Sleep mode to reduce power consumption.
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The transitions between these modes are shown in Figure 24-8. The software instructs LINFlexD to enter
Initialization mode or Sleep mode by setting LINCR1[INIT] or LINCR1[SLEEP], respectively.
RESET
SL
EE
SL
SLEEP
LINRX DOMINANT
SLEEP
P*
EE
INI
T
P
INITIALIZATION
T
INI
P*
EE
T
L
S
I NI
P*
E
E
SL
NORMAL
Figure 24-8. LINFlexD controller operating modes
In addition to these controller-level operating modes, the LINFlexD controller also supports several
protocol-level modes:
• LIN mode:
— Master mode
— Slave mode
— Slave mode with identifier filtering
— Slave mode with automatic resynchronization
• UART mode
• Test modes:
— Loop Back mode
— Self Test mode
These modes are discussed in detail in subsequent sections.
24.6
24.6.1
Controller-level operating modes
Initialization mode
The software initialization can be done while the hardware is in Initialization mode. To enter or exit this
mode, the software sets or clears LINCR1[INIT], respectively.
In Initialization mode, all message transfers to and from the LIN bus are stopped and the LIN bus output
(LINTX) is recessive.
Entering Initialization mode does not change any of the configuration registers.
To initialize the LINFlexD controller, the software must:
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•
Select the desired mode (Master, Slave or UART)
Set up the baud rate register
If LIN Slave mode with filter activation is selected, initialize the identifier list
24.6.2
Normal mode
After initialization is complete, the software must clear LINCR1[INIT] to put the LINFlexD controller into
Normal mode.
24.6.3
Sleep (low-power) mode
To reduce power consumption, LINFlexD has a low-power mode called Sleep mode. In this mode, the
LINFlexD clock is stopped. Consequently, the LINFlexD will not update the status bits, but software can
still access the LINFlexD registers.
To enter this mode, the software must set LINCR1[SLEEP].
LINFlexD can be awakened (exit Sleep mode) in one of two ways:
• The software clears LINCR1[SLEEP]
• Automatic wake-up is enabled (LINCR1[AWUM] is set) and LINFlexD detects LIN bus activity
(that is, if a wakeup pulse of 150 s is detected on the LIN bus)
On LIN bus activity detection, hardware automatically performs the wake-up sequence by clearing
LINCR1[SLEEP] if LINCR1[AWUM] is set. To exit from Sleep mode if LINCR1[AWUM] is cleared, the
software must clear LINCR1[SLEEP] when a wake-up event occurs.
24.7
LIN modes
24.7.1
Master mode
In Master mode, the software uses the message buffer to handle the LIN messages.
Master mode is selected when LINCR1[MME] is set.
24.7.1.1
LIN header transmission
According to the LIN protocol, any communication on the LIN bus is triggered by the master sending a
header. The header is transmitted by the master task while the data is transmitted by the slave task of a
node.
To transmit a header with LINFlexD the application must set up the identifier and the data field length, and
configure the message (direction and checksum type) in the BIDR register before requesting the header
transmission by setting LINCR2[HTRQ].
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24.7.1.2
Data transmission (transceiver as publisher)
When the master node is publisher of the data corresponding to the identifier sent in the header, then the
slave task of the master has to send the data in the Response part of the LIN frame. Therefore, the software
must provide the data to LINFlexD before requesting the header transmission. The software stores the data
in the message buffer BDR. According to the data field length LINFlexD transmits the data and the
checksum. The software uses the BIDR[CCS] bit to configure the checksum type (classic or enhanced) for
each message.
The direction of the message buffer is controlled by the BIDR[DIR] bit. When the software sets this bit
the response is sent by LINFlexD (publisher). Clearing this bit configures the message buffer as subscriber.
24.7.1.3
Data reception (transceiver as subscriber)
To receive data from a slave node, the master sends a header with the corresponding identifier. LINFlexD
stores the data received from the slave in the message buffer and stores the message status in the LINSR.
24.7.1.4
Error detection and handling
LINFlexD is able to detect and handle LIN communication errors. A code stored in the LIN error status
register (LINESR) signals the errors to the software.
Table 24-1 lists the errors detected in Master mode and the LINFlexD controller’s response to these errors.
Table 24-1. Errors in Master mode
Error
Description
LINFlexD response to error
Bit error
During transmission, the value read back
from the bus differs from the transmitted
value
• Stops the transmission of the frame after
the corrupted bit
• Generates an interrupt if LINIER[BEIE] is
set
• Returns to idle state
Framing error
A dominant state has been sampled on the
stop bit of the currently received character
(sync field, identifier, or data field)
If encountered during reception:
• Discards the current frame
• Generates an interrupt if LINIER[FEIE] is
set
• Returns immediately to idle state
Checksum error
The computed checksum does not match the If encountered during reception:
received checksum
• Discards the current frame
• Generates an interrupt if LINIER[CEIE] is
set
• Returns to idle state
Response and frame
timeout
Refer to Section 24.12.1, 8-bit timeout counter, for more details
24.7.1.5
Overrun
After the message buffer is full, the next valid message reception causes an overrun and a message is lost.
The LINFlexD controller sets LINSR[BOF] to signal the overrun condition. Which message is lost
depends on the configuration of the RX message buffer:
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Chapter 24 LIN Controller (LINFlexD)
•
•
If the buffer lock function is disabled (LINCR1[RBLM] cleared), the last message stored in the
buffer is overwritten by the new incoming message. In this case, the latest message is always
available to the software.
If the buffer lock function is enabled (LINCR1[RBLM] set), the most recent message is discarded
and the previous message is available in the buffer.
24.7.2
Slave mode
In Slave mode the software uses the message buffer to handle the LIN messages.
Slave mode is selected when the LINCR1[MME] is cleared.
24.7.2.1
Data transmission (transceiver as publisher)
When LINFlexD receives the identifier, an RX interrupt is generated. The software must:
• Read the received ID in the BIDR register
• Fill the BDR registers
• Specify the data field length using the BIDR[DFL] field
• Trigger the data transmission by setting LINCR2[DTRQ]
One or several identifier filters can be configured for transmission by setting the DIR bits in the
corresponding IFCR registers and activated by setting one or several bits in the IFER register.
When at least one identifier filter is configured in transmission and activated. If the received ID matches
the filter, a specific TX interrupt is generated.
Typically, the software has to copy the data from RAM locations to the BDRL and BDRM registers. To
copy the data to the right location, the software has to identify the data by means of the identifier. To avoid
this and to ease the access to the RAM locations, the LINFlexD controller provides a Filter Match Index.
This index value is the number of the filter that matched the received identifier.
The software can use the index in the IFMI register to directly access the pointer that points to the right
data array in the RAM area and copy this data to the BDRL and BDRM registers (see Figure 24-10).
Using a filter avoids the software having to configure the direction, the data field length and the checksum
type in the BDIR register. The software fills the BDRL and BDRM registers and triggers the data
transmission by setting LINCR2[DTRQ].
If LINFlexD cannot provide enough TX identifier filters to handle all identifiers the software has to
transmit data for, then a filter can be configured in mask mode (refer to Section 24.7.3, Slave mode with
identifier filtering) in order to manage several identifiers with one filter only.
24.7.2.2
Data reception (transceiver as subscriber)
When LINFlexD receives the identifier, an RX interrupt is generated. The software must:
• Read the received ID in the BIDR register
• Specify the data field length using the BIDR[DFL] field before the reception of the stop bit of the
first byte of data field
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When the checksum reception is completed, an RX interrupt is generated to allow the software to read the
received data in the BDR registers.
One or several identifier filters can be configured for reception by clearing the DIR bit in the corresponding
IFCR registers and activated by clearing one or several bits in the IFER register.
When at least one identifier filter is configured in reception and activated. If the received ID matches the
filter, an RX interrupt is generated after the checksum reception only.
Typically, the software has to copy the data from the BDRL and BDRM registers to RAM locations. To
copy the data to the right location, the software has to identify the data by means of the identifier. To avoid
this and to ease the access to the RAM locations, the LINFlexD controller provides a Filter Match Index.
This index value is the number of the filter that matched the received identifier.
The software can use the index in the IFMI register to directly access the pointer that points to the right
data array in the RAM area and copy this data from the BDRL and BDRM registers to the RAM (see
Figure 24-10).
Using a filter avoids the software reading the ID value in the BIDR register and configuring the direction,
the data field length, and the checksum type in the BIDR register.
If LINFlexD cannot provide enough RX identifier filters to handle all identifiers the software has to
receive the data for, then a filter can be configured in mask mode (refer to Section 24.7.3, Slave mode with
identifier filtering) in order to manage several identifiers with one filter only.
24.7.2.3
Data discard
When LINFlexD receives the identifier, an RX interrupt is generated. If the received identifier does not
concern the node, the software must set LINCR2[DDRQ]. LINFlexD returns to idle state.
24.7.2.4
Error detection and handling
Table 24-2 lists the errors detected in Slave mode and the LINFlexD controller’s response to these errors.
Table 24-2. Errors in Slave mode
Error
Description
LINFlexD response to error
Bit error
During transmission, the value read back
from the bus differs from the transmitted
value
• Stops the transmission of the frame after
the corrupted bit
• Generates an interrupt if LINIER[BEIE] is
set
• Returns to idle state
Framing error
A dominant state has been sampled on the
stop bit of the currently received character
(sync field, identifier, or data field)
If encountered during reception:
• Discards the current frame
• Generates an interrupt if LINIER[FEIE] is
set
• Returns immediately to idle state
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Table 24-2. Errors in Slave mode (continued)
Error
Description
LINFlexD response to error
Checksum error
The computed checksum does not match the If encountered during reception:
received checksum
• Discards the received frame
• Generates an interrupt if LINIER[CEIE] is
set
• Returns to idle state
Header error
An error occurred during header reception
If encountered during header reception, a
(break delimiter error, inconsistent sync field, break field error, an inconsistent sync field, or
header timeout)
a timeout:
• Discards the header
• Generates an interrupt if LINIER[HEIE] is
set
• Returns to idle state
24.7.2.5
Valid header
A received header is considered as valid when it has been received correctly according to the LIN protocol.
If a valid break field and break delimiter come before the end of the current header, or at any time during
a data field, the current header or data is discarded and the state machine synchronizes on this new break.
24.7.2.6
Valid message
A received or transmitted message is considered as valid when the data has been received or transmitted
without error according to the LIN protocol.
24.7.2.7
Overrun
After the message buffer is full, the next valid message reception causes an overrun and a message is lost.
The LINFlexD controller sets LINSR[BOF] to signal the overrun condition. Which message is lost
depends on the configuration of the RX message buffer:
• If the buffer lock function is disabled (LINCR1[RBLM] cleared), the last message stored in the
buffer is overwritten by the new incoming message. In this case, the latest message is always
available to the software.
• If the buffer lock function is enabled (LINCR1[RBLM] set), the most recent message is discarded
and the previous message is available in the buffer.
24.7.3
Slave mode with identifier filtering
In the LIN protocol, the identifier of a message is not associated with the address of a node but related to
the content of the message. Consequently a transmitter broadcasts its message to all receivers. When a
slave node receives a header, it decides—depending on the identifier value—whether the software needs
to receive or send a response. If the message does not target the node, it must be discarded without software
intervention.
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To fulfill this requirement, the LINFlexD controller provides configurable filters in order to request
software intervention only if needed. This hardware filtering saves CPU resources, which would otherwise
be needed by software for filtering.
The filtering is accomplished through the use of IFCR registers. These registers have the names IFCR0
through IFCR. This section also uses the nomenclature IFCR2n and IFCR2n+1; in this nomenclature, n is
an integer, and the corresponding IFCR register is calculated using the formula in the subscript.
24.7.3.1
Filter submodes
Usually each of the 16 IFCRs is used to filter one dedicated identifier, but this means that the LINFlexD
controller could filter a maximum of 16 identifiers. In order to be able to handle more identifiers, the filters
can be configured to operate as masks.
Table 24-3 describes the two available filter submodes.
Table 24-3. Filter submodes
Submode
Description
Identifier list
Both filter registers are used as identifier registers. All bits of the incoming identifier must match
the bits specified in the filter register. This is the default submode for the LINFlexD controller.
Mask
The identifier registers are associated with mask registers specifying which bits of the identifier
are handled as “must match” or as “don’t care”.
The bit mapping and register organization in these two submodes is shown in Figure 24-9.
Identifier filter register organization
Identifier
Bit Mapping
IFCRx
DFL
DIR CCS
Identifier filter configuration
ID
Identifier filter submode
Identifier list submode
Identifier
Identifier
IFCR2n
IFCR2n+1
IFM = 0
Mask submode
Identifier
Mask
IFCR2n
IFCR2n+1
IFM = 1
Figure 24-9. Filter configuration—register organization
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24.7.3.2
Identifier filter submode configuration
The identifier filters are configured in the IFCR registers. To configure an identifier filter the filter must
first be activated by setting the corresponding bit in the IFER[FACT] field. The submode (identifier list or
mask) for the corresponding IFCR register is configured by the IFMR[IFM] field. For each filter, the IFCR
register is used to configure:
• The ID or mask
• The direction (TX or RX)
• The data field length
• The checksum type
If no filter is active, an RX interrupt is generated on any received identifier event.
If at least one active filter is configured as TX, all received identifiers matching this filter generate a TX
interrupt.
If at least one active filter is configured as RX, all received identifiers matching this filter generate an RX
interrupt.
If no active filter is configured as RX, all received identifiers not matching TX filter(s) generate an RX
interrupt.
Further details are provided in Table 24-4 and Figure 24-10.
Table 24-4. Filter to interrupt vector correlation
Number of active
filters
Number of active
Number of active
filters configured as filters configured as
TX
RX
Interrupt vector
0
0
0
RX interrupt on all IDs
a
(a > 0)
a
0
• TX interrupt on IDs matching
the filters
• RX interrupt on all other IDs
if BF bit is set, no RX
interrupt if BF bit is reset
n
(n = a + b)
a
(a > 0)
b
(b > 0)
• TX interrupt on IDs matching
the TX filters
• RX interrupt on IDs
matching the RX filters
• All other IDs discarded (no
interrupt)
b
(b > 0)
0
b
• RX interrupt on IDs
matching the filters
• TX interrupt on all other IDs
if BF bit is set, no TX
interrupt if BF bit is reset
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Chapter 24 LIN Controller (LINFlexD)
MESSAGE0
@
+
MESSAGE1
IFMI
DATA
Pointers
Table
MESSAGE2
RAM
Figure 24-10. Identifier match index
24.7.4
Slave mode with automatic resynchronization
Automatic resynchronization must be enabled in Slave mode if fipg_clock_lin tolerance is greater than 1.5%.
This feature compensates a deviation up to 14%, as specified in the LIN standard.
This mode is similar to Slave mode as described in Section 24.7.2, Slave mode, with the addition of
automatic resynchronization enabled by the LINCR1[LASE] bit. In this mode LINFlexD adjusts the
fractional baud rate generator after each synch field reception.
24.7.4.1
Automatic resynchronization method
When automatic resynchronization is enabled, after each LIN break, the time duration between five falling
edges on RDI is sampled on as shown in Figure 24-11. Then the LFDIV value (and its associated
LINIBRR and LINFBRR registers) is automatically updated at the end of the fifth falling edge. During
LIN sync field measurement, the LINFlexD state machine is stopped and no data is transferred to the data
register.
T = Clock period
TBR = 16.LFDIV.T
TBR = Baud rate period
TBR
LIN sync field
LIN Break
Break
delim.
Start
Bit
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Stop
Bit
Next
Start
Bit
Measurement = 8.TBR
LFDIV(n+1)
LFDIV(n)
LFDIV = TBR/(16.T)
Figure 24-11. LIN sync field measurement
LFDIV is an unsigned fixed point number. The mantissa is coded on 20 bits in the LINIBRR register and
the fraction is coded on 4 bits in the LINFBRR register.
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If LINCR1[LASE] is set, LFDIV is automatically updated at the end of each LIN sync field.
Three registers are used internally to manage the auto-update of the LINFlexD divider (LFDIV):
• LFDIV_NOM (nominal value written by software at LINIBRR and LINFBRR addresses)
• LFDIV_MEAS (results of the Field Synch measurement)
• LFDIV (used to generate the local baud rate)
On transition to idle, break or break delimiter state due to any error or on reception of a complete frame,
hardware reloads LFDIV with LFDIV_NOM.
24.7.4.2
Deviation error on the sync field
The deviation error is checked by comparing the current baud rate (relative to the slave oscillator) with the
received LIN sync field (relative to the master oscillator). Two checks are performed in parallel.
The first check is based on a measurement between the first falling edge and the last falling edge of the
sync field:
• If D1 > 14.84%, LHE is set.
• If D1 < 14.06%, LHE is not set.
• If 14.06% < D1 < 14.84%, LHE can be either set or reset depending on the dephasing between the
signal on LINFlexD_RX pin the fipg_clock_lin clock.
The second check is based on a measurement of time between each falling edge of the sync field:
• If D2 > 18.75%, LHE is set.
• If D2 < 15.62%, LHE is not set.
• If 15.62% < D2 < 18.75%, LHE can be either set or reset depending on the dephasing between the
signal on LINFlexD_RX pin the fipg_clock_lin clock.
Note that the LINFlexD does not need to check if the next edge occurs slower than expected. This is
covered by the check for deviation error on the full synch byte.
24.8
Test modes
The LINFlexD controller includes two test modes, Loop Back mode and Self Test mode. They can be
selected by the LBKM and SFTM bits in the LINCR1 register. These bits must be configured while
LINFlexD is in Initialization mode. After one of the two test modes has been selected, LINFlexD must be
started in Normal mode.
24.8.1
Loop Back mode
LINFlexD can be put in Loop Back mode by setting LINCR1[LBKM]. In Loop Back mode, the LINFlexD
treats its own transmitted messages as received messages. This is illustrated in Figure 24-12.
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LINFlexD
Tx
Rx
LINTX
LINRX
Figure 24-12. LINFlexD in Loop Back mode
This mode is provided for self-test functions. To be independent of external events, the LIN core ignores
the LINRX signal. In this mode, the LINFlexD performs an internal feedback from its Tx output to its Rx
input. The actual value of the LINRX input pin is disregarded by the LINFlexD. The transmitted messages
can be monitored on the LINTX pin.
24.8.2
Self Test mode
LINFlexD can be put in Self Test mode by setting LINCR1[LBKM] and LINCR1[SFTM]. This mode can
be used for a Hot Self Test, meaning the LINFlexD can be tested as in Loop Back mode but without
affecting a running LIN system connected to the LINTX and LINRX pins. In this mode, the LINRX pin is
disconnected from the LINFlexD and the LINTX pin is held recessive. This is illustrated in Figure 24-13.
LINFlexD
Tx
Rx
=1
LINTX
LINRX
Figure 24-13. LINFlexD in Self Test mode
24.9
UART mode
The main features of UART mode are presented in Section 24.2.2, UART mode features.
24.9.1
24.9.1.1
Data frame structure
8-bit data frame
The 8-bit UART data frame is shown in Figure 24-14. The 8th bit can be a data or a parity bit. Parity (even,
odd, 0, or 1) can be selected by the UARTCR[PC] field. An even parity is set if the modulo-2 sum of the
7 data bits is 1. An odd parity is cleared in this case.
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Byte Field
Start
bit
D0
D1
D2
D3
D4
D5
D6
Stop
bit
D7
– Data bit
– Parity bit
Figure 24-14. UART mode 8-bit data frame
24.9.1.2
9-bit data frame
The 9-bit UART data frame is shown in Figure 24-15. The 9th bit is a parity bit. Parity (even, odd, 0, or 1)
can be selected by the by the UARTCR[PC] field. An even parity is set if the modulo-2 sum of the 8 data
bits is 1. An odd parity is cleared in this case. Parity 0 forces a zero logical value. Parity 1 forces a high
logical value.
Byte Field
Start
bit
D0
D1
D2
D3
D4
D5
D6
Stop
bit
D8
D7
– Parity bit
Figure 24-15. UART mode 9-bit data frame
24.9.1.3
16-bit data frame
The 16-bit UART data frame is shown in Figure 24-16. The 16th bit can be a data or a parity bit. Parity
(even, odd, 0, or 1) can be selected by the UARTCR[PC] field. Parity 0 forces a zero logical value. Parity
1 forces a high logical value.
Byte Field
Start
bit
D0
D1
D2
...
...
D13
D14
D15
Stop
bit
– Data bit
– Parity bit
Figure 24-16. UART mode 16-bit data frame
24.9.1.4
17-bit data frame
The 17-bit UART data frame is shown in Figure 24-17. The 17th bit is the parity bit. Parity (even, odd, 0,
or 1) can be selected by the UARTCR[PC] field. Parity 0 forces a zero logical value. Parity 1 forces a high
logical value.
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Byte Field
Start
bit
D0
D1
D2
...
D13
D14
D15
Stop
bit
D16
– Parity bit
Figure 24-17. UART mode 17-bit data frame
24.9.2
Buffer
The 8-byte buffer is divided into two parts—one for receiver and one for transmitter—as shown in
Table 24-5.
Table 24-5. UART buffer structure
BDR
UART mode
0
Tx0
1
Tx1
2
Tx2
3
Tx3
4
Rx0
5
Rx1
6
Rx2
7
Rx3
For 16-bit frames, the lower 8 bits will be written in BDR0 and the upper 8 bits will be written in BDR1.
24.9.3
UART transmitter
In order to start transmission in UART mode, the UARTCR[UART] and UARTCR[TXEN] bits must be
set. Transmission starts when BDR0 (least significant data byte) is programmed. The number of bytes
transmitted is equal to the value configured by the UARTCR[TDFLTFC] field (see Table 24-16).
The Transmit buffer size is as follows:
• 4 bytes when UARTCR[WL1] = 0
• 2 half-words when UARTCR[WL1] = 1
Therefore, the maximum transmission that can be triggered is 4 bytes (2 half-words). After the
programmed number of bytes has been transmitted, the UARTSR[DTFTFF] flag is set. If the
UARTCR[TXEN] field is cleared during a transmission, the current transmission is completed, but no
further transmission can be invoked. The buffer can be configured in FIFO mode (mandatory when DMA
Tx is enabled) by setting UARTCR[TFBM].
The access to the BDRL register is shown in Table 24-6.
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Table 24-6. BDRL access in UART mode
Mode1
Access
Word length2
IPS operation result
Write Byte0
FIFO
Byte
OK
Write Byte1-2-3
FIFO
Byte
IPS transfer error
Write Half-word0-1
FIFO
Byte
IPS transfer error
Write Word
FIFO
Byte
IPS transfer error
Write Byte0-1-2-3
FIFO
Half-word
IPS transfer error
Write Half-word0
FIFO
Half-word
OK
Write Half-word1
FIFO
Half-word
IPS transfer error
Write Word
FIFO
Half-word
IPS transfer error
Read Byte0-1-2-3
FIFO
Byte/Half-word
IPS transfer error
Read Half-word0-1
FIFO
Byte/Half-word
IPS transfer error
Read Word
FIFO
Byte/Half-word
IPS transfer error
Write Byte0-1-2-3
BUFFER
Byte/Half-word
OK
Write Half-word0-1
BUFFER
Byte/Half-word
OK
Write Word
BUFFER
Byte/Half-word
OK
Read Byte0-1-2-3
BUFFER
Byte/Half-word
OK
Read Half-word0-1
BUFFER
Byte/Half-word
OK
Read Word
BUFFER
Byte/Half-word
OK
1
2
As specified by UARTCR[TFBM]
As specified by the WL1 and WL0 bits of the UARTCR register. In UART FIFO mode (UARTCR[TFBM] = 1),any
read operation causes an IPS transfer error.
24.9.4
UART receiver
Reception of a data byte is started as soon as the software completes the following tasks in order:
1. Exits Initialization mode
2. Sets the UARTCR[RXEN] field
3. Detects the start bit
There is a dedicated data buffer for received data bytes. Its size is as follows:
• 4 bytes when UARTCR[WL1] = 0
• 2 half-words when UARTCR[WL1] = 1
After the programmed number (RDFL bits) of bytes has been received, the UARTSR[DRFRFE] field is
set. If the UARTCR[RXEN] field is cleared during a reception, the current reception is completed, but no
further reception can be invoked until UARTCR[RXEN] is set again.
The buffer can be configured in FIFO mode (required when DMA Rx is enabled) by setting
UARTCR[RFBM].
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The access to the BDRM register is shown in Table 24-7.
Table 24-7. BDRM access in UART mode
Mode1
Access
Word length2
IPS operation result
Read Byte4
FIFO
Byte
OK
Read Byte5-6-7
FIFO
Byte
IPS transfer error
Read Half-word2-3
FIFO
Byte
IPS transfer error
Read Word
FIFO
Byte
IPS transfer error
Read Byte4-5-6-7
FIFO
Half-word
IPS transfer error
Read Half-word2
FIFO
Half-word
OK
Read Half-word3
FIFO
Half-word
IPS transfer error
Read Word
FIFO
Half-word
IPS transfer error
Write Byte4-5-6-7
FIFO
Byte/Half-word
IPS transfer error
Write Half-word2-3
FIFO
Byte/Half-word
IPS transfer error
Write Word
FIFO
Byte/Half-word
IPS transfer error
Read Byte4-5-6-7
BUFFER
Byte/Half-word
OK
Read Half-word2-3
BUFFER
Byte/Half-word
OK
Read Word
BUFFER
Byte/Half-word
OK
Write Byte4-5-6-7
BUFFER
Byte/Half-word
IPS transfer error
Write Half-word2-3
BUFFER
Byte/Half-word
IPS transfer error
Write Word
BUFFER
Byte/Half-word
IPS transfer error
1
2
As specified by UARTCR[RFBM]
As specified by the WL1 and WL0 bits of the UARTCR register
Table 24-8 lists some common scenarios, controller responses, and suggestions when the LINFlexD
controller is acting as a UART receiver.
Table 24-8. UART receiver scenarios
Scenario
The software does not know (in advance) how many
bytes will be received.
Responses and suggestions
Do not program UARTCR[RDFLRFC] in advance. When
this field is zero (as it is after reset), reception occurs on
a byte-by-byte basis. Therefore, the state machine will
move to IDLE state after each byte is received.
UARTCR[RDFLRFC] is programmed for a certain
The reception will hang. In this case, the software must
number of bytes received, but the actual number of bytes monitor the UARTSR[TO] field, and move to IDLE state
received is smaller.
by setting LINCR1[SLEEP].
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Chapter 24 LIN Controller (LINFlexD)
Table 24-8. UART receiver scenarios (continued)
Scenario
Responses and suggestions
A STOP request arrives before the reception is
completed.
The request is acknowledged only after the programmed
number of data bytes are received. In other words, the
STOP request is not serviced immediately. In this case,
the software must monitor the UARTSR[TO] field and
move the state machine to IDLE state as appropriate. The
stop request will be serviced only after this is complete.
A parity error occurs during the reception of a byte.
The corresponding UARTSR[PEn] field is set. No
interrupt is generated.
A framing error occurs during the reception of a byte.
• UARTSR[FE] is set.
• If LINIER[FEIE] = 1, an interrupt is generated. This
interrupt is helpful in identifying which byte has the
framing error, since there is only one register bit for
framing errors.
A new byte has been received, but the last received frame
has not been read from the buffer (UARTSR[RMB] has
not yet been cleared by the software)
• An overrun error will occur (UARTSR[BOF] will be set).
• One message will be lost (depending on the setting of
LINCR[RBLM]).
• An interrupt is generated if LINIER[BOIE] is set.
24.10 Memory map and register description
24.10.1 LIN control register 1 (LINCR1)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
BF1
SFT
M1
MME1
SBDT1
RBLM1
SLEEP
R
Access: User read/write
LBKM1
Offset:0x00
INIT
1
0
0
0/12
0
0
1
0
1
1
AWUM1
Reset
LASE1
W
0
0
0
0
R CCD CFD
W
Reset
1
2
MBL1
0
0
0
0
These fields are writable only in Initialization mode (LINCR1[INIT] = 1).
Resets to 0 in Slave mode and to 1 in Master mode
Figure 24-18. LIN control register 1 (LINCR1)
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Chapter 24 LIN Controller (LINFlexD)
Table 24-9. LINCR1 field descriptions
Field
Description
CCD
Checksum Calculation disable
This bit is used to disable the checksum calculation (see Table 24-10).
0: Checksum calculation is done by hardware. When this bit is reset the LINCFR register is read-only.
1: Checksum calculation is disabled. When this bit is set the LINCFR register is read/write. User can
program this register to send a software calculated CRC (provided CFD is reset).
Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
CFD
Checksum field disable
This bit is used to disable the checksum field transmission (see Table 24-10).
0: Checksum field is sent after the required number of data bytes is sent.
1: No checksum field is sent.
Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
LASE
LIN Slave Automatic Resynchronization Enable
0: Automatic resynchronization disable
1: Automatic resynchronization enable
Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
AWUM
Automatic Wake-Up Mode
This bit controls the behavior of the LINFlexD hardware during Sleep mode.
0: The Sleep mode is exited on software request by clearing the SLEEP bit of the LINCR register.
1: The Sleep mode is exited automatically by hardware on RX dominant state detection. The SLEEP
bit of the LINCR register is cleared by hardware whenever WUF bit in LINSR is set.
Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
MBL
BF
LIN Master Break Length
These bits indicate the Break length in Master mode (see Table 24-11).
Note: These bits can be written in Initialization mode only. They are read-only in Normal or Sleep
mode.
Bypass filter
0: No interrupt if ID does not match any filter
1: An RX interrupt is generated on ID not matching any filter
Notes:
• If no filter is activated, this bit is reserved.
• This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
SFTM
Self Test Mode
This bit controls the Self Test mode. For more details please refer to Section 24.8.2, Self Test mode.
0: Self Test mode disable
1: Self Test mode enable
Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
LBKM
Loop Back Mode
This bit controls the Loop Back mode. For more details please refer to Section 24.8.1, Loop Back
mode.
0: Loop Back mode disable
1: Loop Back mode enable
Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode
MME
Master Mode Enable
0: Slave mode enable
1: Master mode enable
Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
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Chapter 24 LIN Controller (LINFlexD)
Table 24-9. LINCR1 field descriptions (continued)
Field
Description
SBDT
Slave Mode Break Detection Threshold
0: 11-bit break
1: 10-bit break
Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
RBLM
Receive Buffer Locked Mode
0: Receive Buffer not locked on overrun. Once the Slave Receive Buffer is full the next incoming
message overwrites the previous one.
1: Receive Buffer locked against overrun. Once the Receive Buffer is full the next incoming message
is discarded.
Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode.
SLEEP
Sleep Mode Request
This bit is set by software to request LINFlexD to enter Sleep mode.
This bit is cleared by software to exit Sleep mode or by hardware if the AWUM bit in LINCR1 and the
WUF bit in LINSR are set (see Table 24-12).
INIT
Initialization Request
The software sets this bit to switch hardware into Initialization mode. If the SLEEP bit is reset,
LINFlexD enters Normal mode when clearing the INIT bit (see Table 24-12).
Table 24-10. Checksum bits configuration
CFD
CCD
LINCFR
Checksum sent
1
1
Read/Write
None
1
0
Read-only
None
0
1
Read/Write
Programmed in LINCFR by bits CF[0:7]
0
0
Read-only
Hardware calculated
Table 24-11. LIN master break length selection
MBL
Length
0000
10-bit
0001
11-bit
0010
12-bit
0011
13-bit
0100
14-bit
0101
15-bit
0110
16-bit
0111
17-bit
1000
18-bit
1001
19-bit
1010
20-bit
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Chapter 24 LIN Controller (LINFlexD)
Table 24-11. LIN master break length selection (continued)
MBL
Length
1011
21-bit
1100
22-bit
1101
23-bit
1110
36-bit
1111
50-bit
Table 24-12. Operating mode selection
SLEEP
INIT
Operating mode
1
0
Sleep (reset value)
x
1
Initialization
0
0
Normal
24.10.2 LIN interrupt enable register (LINIER)
Offset: 0x04
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
DBFIE
DBEIETOIE
Reset
WUIE
W
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
0
0
0
0
0
0
0
0
0
R
SZIE OCIE BEIE CEIE HEIE
W w1c
Reset
0
w1c
w1c
w1c
w1c
0
0
0
0
0
0
FEIE BOIE LSIE
DRIE DTIE HRIE
Figure 24-19. LIN interrupt enable register (LINIER)
Table 24-13. LINIER field descriptions
Field
SZIE
Description
Stuck at Zero Interrupt Enable
0: No interrupt when SZF bit in LINESR or UARTSR is set
1: Interrupt generated when SZF bit in LINESR or UARTSR is set
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Chapter 24 LIN Controller (LINFlexD)
Table 24-13. LINIER field descriptions (continued)
Field
Description
OCIE
Output Compare Interrupt Enable
0: No interrupt when OCF bit in LINESR or UARTSR is set
1: Interrupt generated when OCF bit in LINESR or UARTSR is set
BEIE
Bit Error Interrupt Enable
0: No interrupt when BEF bit in LINESR is set
1: Interrupt generated when BEF bit in LINESR is set
CEIE
Checksum Error Interrupt Enable
0: No interrupt on Checksum error
1: Interrupt generated when checksum error flag (CEF) is set in LINESR
HEIE
Header Error Interrupt Enable
0: No interrupt on Break Delimiter error, Synch Field error, ID field error
1: Interrupt generated on Break Delimiter error, Synch Field error, ID field error
FEIE
Framing Error Interrupt Enable
0: No interrupt on Framing error
1: Interrupt generated on Framing error
BOIE
Buffer Overrun Interrupt Enable
0: No interrupt on Buffer overrun
1: Interrupt generated on Buffer overrun
LSIE
LIN State Interrupt Enable
0: No interrupt on LIN state change
1: Interrupt generated on LIN state change
This interrupt can be used for debugging purposes. It has no status flag but is reset when writing 1111
into the LIN state bits in the LINSR register.
WUIE
Wake-up Interrupt Enable
0: No interrupt when WUF bit in LINSR or UARTSR is set
1: Interrupt generated when WUF bit in LINSR or UARTSR is set
DBFIE
Data Buffer Full Interrupt Enable
0: No interrupt when buffer data register is full
1: Interrupt generated when data buffer register is full
DBEIETOIE Data Buffer Empty Interrupt Enable / Timeout Interrupt Enable
0: No interrupt when buffer data register is empty
1: Interrupt generated when data buffer register is empty
Note: An interrupt is generated if this bit is set and one of the following is true:
LINFlexD is in LIN mode and LINSR[DBEF] is set
LINFlexD is in UART mode and UARTSR[TO] is set
DRIE
Data Reception Complete Interrupt Enable
0: No interrupt when data reception is completed
1: Interrupt generated when data received flag (DRF) in LINSR or UARTSR is set
DTIE
Data Transmitted Interrupt Enable
0: No interrupt when data transmission is completed
1: Interrupt generated when data transmitted flag (DTF) is set in LINSR or UARTSR register
HRIE
Header Received Interrupt Enable
0: No interrupt when a valid LIN header has been received
1: Interrupt generated when a valid LIN header has been received, that is, HRF bit in LINSR register
is set
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Chapter 24 LIN Controller (LINFlexD)
24.10.3 LIN status register (LINSR)
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
RMB
0
RBSY
Offset: 0x08
R
LINS
W
Reset
w1c
w1c
0
0
0
0
0
0
0
0
DBEF
Reset
DBFF
W
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
0
1
0
0
0
0
0
0
RPS WUF
DRF DTF HRF
Figure 24-20. LIN status register (LINSR)
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Chapter 24 LIN Controller (LINFlexD)
Table 24-14. LINSR field descriptions
Field
Description
LINS
LIN state
LIN mode states description
0000: Sleep mode
LINFlexD is in Sleep mode to save power consumption.
0001: Initialization mode
LINFlexD is in Initialization mode.
0010: Idle
This state is entered on several events:
• SLEEP bit and INIT in LINCR1 register have been cleared by software,
• A falling edge has been received on RX pin and AWUM bit is set,
• The previous frame reception or transmission has been completed or aborted.
0011: Break
In Slave mode, a falling edge followed by a dominant state has been detected. Receiving Break.
Note: In Slave mode, in case of error new LIN state can be either Idle or Break depending on last bit
state. If last bit is dominant new LIN state is Break, otherwise Idle.
In Master mode, Break transmission ongoing.
0100: Break Delimiter
In Slave mode, a valid Break has been detected. Refer to LINCR1 register for break length
configuration (10-bit or 11-bit). Waiting for a rising edge.
In Master mode, Break transmission has been completed. Break Delimiter transmission is ongoing.
0101: Synch Field
In Slave mode, a valid Break Delimiter has been detected (recessive state for at least one bit time).
Receiving Synch Field.
In Master mode, Synch Field transmission is ongoing.
0110: Identifier Field
In Slave mode, a valid Synch Field has been received. Receiving ID Field.
In Master mode, identifier transmission is ongoing.
0111: Header reception/transmission completed
In Slave mode, a valid header has been received and identifier field is available in the BIDR register.
In Master mode, header transmission is completed.
1000: Data reception/transmission
Response reception/transmission is ongoing.
1001: Checksum
Data reception/transmission completed. Checksum reception/transmission ongoing.
In UART mode, only the following states are flagged by the LIN state bits:
• Init
• Sleep
• Idle
• Data transmission/reception
RMB
Release Message Buffer
0: Buffer is free
1: Buffer ready to be read by software. This bit must be cleared by software after reading data received
in the buffer.
This bit is cleared by hardware in Initialization mode.
RBSY
Receiver Busy Flag
0: Receiver is Idle
1: Reception ongoing
Note: In Slave mode, after header reception, if DIR bit in BIDR is reset and reception starts then this
bit is set. In this case, user cannot set DTRQ bit in LINCR2.
RPS
LIN receive pin state
This bit reflects the current status of LINRX pin for diagnostic purposes.
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Chapter 24 LIN Controller (LINFlexD)
Table 24-14. LINSR field descriptions (continued)
Field
Description
WUF
Wake-up Flag
This bit is set by hardware and indicates to the software that LINFlexD has detected a falling edge on
the LINRX pin when
• slave is in Sleep mode,
• master is in Sleep mode or idle state.
This bit must be cleared by software. It is reset by hardware in Initialization mode. An interrupt is
generated if WUIE bit in LINIER is set.
DBFF
Data Buffer Full Flag
This bit is set by hardware and indicates the buffer is full. It is set only when receiving extended frames
(DFL > 7).
This bit must be cleared by software.
It is reset by hardware in Initialization mode.
DBEF
Data Buffer Empty Flag
This bit is set by hardware and indicates the buffer is empty. It is set only when transmitting extended
frames (DFL > 7).
This bit must be cleared by software, once buffer has been filled again, in order to start transmission.
This bit is reset by hardware in Initialization mode.
DRF
Data Reception Completed Flag
This bit is set by hardware and indicates the data reception is completed.
This bit must be cleared by software.
It is reset by hardware in Initialization mode.
Note: This flag is not set in case of bit error or framing error.
DTF
Data Transmission Completed Flag
This bit is set by hardware and indicates the data transmission is completed.
This bit must be cleared by software.
It is reset by hardware in Initialization mode.
Note: This flag is not set in case of bit error if IOBE bit is reset.
HRF
Header Reception Flag
This bit is set by hardware and indicates a valid header reception is completed.
This bit must be cleared by software.
This bit is reset by hardware in Initialization mode and at end of completed or aborted frame.
Note: If filters are enabled, this bit is set only when identifier software filtering is required, that is to say:
• all filters are inactive and BF bit in LINCR1 is set
• no match in any filter and BF bit in LINCR1 is set
• TX filter match
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Chapter 24 LIN Controller (LINFlexD)
24.10.4 LIN error status register (LINESR)
Offset: 0x0C
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
NF
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
0
0
0
0
0
0
0
0
SZF OCF BEF CEF
W w1c
Reset
IDPEF
R
BDEF
Reset
SFEF
W
0
FEF BOF
w1c
0
0
0
0
0
0
0
Figure 24-21. LIN error status register (LINESR)
Table 24-15. LINESR field descriptions
Field
Description
SZF
Stuck at zero Flag
This bit is set by hardware when the bus is dominant for more than a 100-bit time. It is cleared by
software.
OCF
Output Compare Flag
0: No output compare event occurred
1: The content of the counter has matched the content of OC1[0:7] or OC2[0:7] in LINOCR. If this bit
is set and IOT bit in LINTCSR is set, LINFlexD moves to Idle state.
If LTOM bit in LINTCSR register is set then OCF is reset by hardware in Initialization mode. If LTOM
bit is reset, then OCF maintains its status whatever the mode is.
BEF
Bit Error Flag
This bit is set by hardware and indicates to the software that LINFlexD has detected a bit error. This
error can occur during response field transmission (Slave and Master modes) or during header
transmission (in Master mode).
This bit is cleared by software.
CEF
Checksum error Flag
This bit is set by hardware and indicates that the received checksum does not match the hardware
calculated checksum.
This bit is cleared by software.
Note: This bit is never set if CCD or CFD bit in LINCR1 register is set.
SFEF
Synch Field Error Flag
This bit is set by hardware and indicates that a Synch Field error occurred (inconsistent Synch Field).
BDEF
Break Delimiter Error Flag
This bit is set by hardware and indicates that the received Break Delimiter is too short (less than one
bit time).
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Chapter 24 LIN Controller (LINFlexD)
Table 24-15. LINESR field descriptions (continued)
Field
Description
IDPEF
Identifier Parity Error Flag
This bit is set by hardware and indicates that a Identifier Parity error occurred.
Note: Header interrupt is triggered when SFEF or BDEF or IDPEF bit is set and HEIE bit in LINIER is
set.
FEF
Framing Error Flag
This bit is set by hardware and indicates to the software that LINFlexD has detected a framing error
(invalid stop bit). This error can occur during reception of any data in the response field (Master or
Slave mode) or during reception of Synch Field or Identifier Field in Slave mode.
BOF
Buffer Overrun Flag
This bit is set by hardware when a new data byte is received and the buffer full flag is not cleared. If
RBLM in LINCR1 is set then the new byte received is discarded. If RBLM is reset then the new byte
overwrites the buffer. It can be cleared by software.
NF
Noise Flag
This bit is set by hardware when noise is detected on a received character. This bit is cleared by
software.
24.10.5 UART mode control register (UARTCR)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
TFBM2
WL[1]2
PC12
RXEN
TXEN
PC02
PCE2
WL[0]2
UART2
R
Access: User read/write
RFBM
Offset: 0x10
0
0
0
0
0
0
0
0
0
0
W
Reset
R
TDFLTFC1
RDFLRFC1
W
Reset
0
1
2
0
0
0
0
0
These fields are read/write in UART buffer mode and read-only in other modes.
These fields are writable only in Initialization mode (LINCR1[INIT] = 1).
Figure 24-22. UART mode control register (UARTCR)
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Chapter 24 LIN Controller (LINFlexD)
Table 24-16. UARTCR field descriptions
Field
Description
TDFLTFC
Transmitter data field length / Tx FIFO counter
This field has one of two functions depending on the mode of operation as follows:
• When LINFlexD is in UART buffer mode (TFBM = 0), TDFLTFC defines the number of bytes to be
transmitted. The field is read/write in this configuration. The first bit is reserved and not
implemented.
The permissible values are as follows (with X representing the unimplemented first bit):
0bX00: 1 byte
0bX01: 2 bytes
0bX10: 3 bytes
0bX11: 4 bytes
When the UART data length is configured as half-word (WL = 0b10 or 0b11), the only valid values
for TDFLTFC are 0b001 and 0b011.
• When LINFlexD is in UART FIFO mode (TFBM = 1), TDFLTFC contains the number of entries
(bytes) of the Tx FIFO. The field is read-only in this configuration.
The permissible values are as follows:
0b000: Empty
0b001: 1 byte
0b010: 2 bytes
0b011: 3 bytes
0b100: 4 bytes
All other values are reserved.
This field is meaningful and can be programmed only when the UART bit is set.
RDFLRFC
Receiver data field length / Rx FIFO counter
This field has one of two functions depending on the mode of operation as follows:
• When LINFlexD is in UART buffer mode (RFBM = 0), RDFLRFC defines the number of bytes to be
received. The field is read/write in this configuration. The first bit is reserved and not implemented.
The permissible values are as follows (with X representing the unimplemented first bit):
0bX00: 1 byte
0bX01: 2 bytes
0bX10: 3 bytes
0bX11: 4 bytes
When the UART data length is configured as half-word (WL = 0b10 or 0b11), the only valid values
for RDFLRFC are 0b001 and 0b011.
• When LINFlexD is in UART FIFO mode (RFBM = 1), RDFLRFC contains the number of entries
(bytes) of the Rx FIFO. The field is read-only in this configuration.
The permissible values are as follows:
0b000: Empty
0b001: 1 byte
0b010: 2 bytes
0b011: 3 bytes
0b100: 4 bytes
All other values are reserved.
This field is meaningful and can be programmed only when the UART bit is set.
RFBM
Rx FIFO/buffer mode
0 Rx buffer mode enabled
1 Rx FIFO mode enabled (mandatory in DMA Rx mode)
This field can be programmed in initialization mode only when the UART bit is set.
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Chapter 24 LIN Controller (LINFlexD)
Table 24-16. UARTCR field descriptions (continued)
Field
Description
TFBM
Tx FIFO/buffer mode
0 Tx buffer mode enabled
1 Tx FIFO mode enabled (mandatory in DMA Tx mode)
This field can be programmed in initialization mode only when the UART bit is set.
RXEN
Receiver Enable
0: Receiver disabled
1: Receiver enabled
This field can be programmed only when the UART bit is set.
TXEN
Transmitter Enable
0: Transmitter disabled
1: Transmitter enabled
This field can be programmed only when the UART bit is set.
Note: Transmission starts when this bit is set and when writing DATA0 in the BDRL register.
PC
Parity control
00 Parity sent is even
01 Parity sent is odd
10 A logical 0 is always transmitted/checked as parity bit
11 A logical 1 is always transmitted/checked as parity bit
This field can be programmed in initialization mode only when the UART bit is set.
PCE
Parity Control Enable
0: Parity transmit/check disabled
1: Parity transmit/check enabled
This field can be programmed in Initialization mode only when the UART bit is set.
WL
Word length in UART mode
00 7 bits data + parity
01 8 bits data when PCE = 0 or 8 bits data + parity when PCE = 1
10 15 bits data + parity
11 16 bits data when PCE = 0 or 16 bits data + parity when PCE = 1
This field can be programmed in Initialization mode only when the UART bit is set.
UART
UART mode enable
0: LIN mode
1: UART mode
This field can be programmed in Initialization mode only.
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Chapter 24 LIN Controller (LINFlexD)
24.10.6 UART mode status register (UARTSR)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
PE2
PE1
PE0 RMB FEF BOF RPS WUF
0
TO
DTFTFF
R
Access: User read/write
DRFRFE
Offset: 0x14
NF
w1c
w1c
w1c
w1c
0
0
0
0
W
Reset
R
SZF OCF PE3
W w1c
Reset
0
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
0
0
0
0
0
0
0
0
0
0
0
Figure 24-23. UART mode status register (UARTSR)
Table 24-17. UARTSR field descriptions
Field
Description
SZF
Stuck at zero Flag
This bit is set by hardware when the bus is dominant for more than a 100-bit time. It is cleared by
software.
OCF
OCF Output Compare Flag
0: No output compare event occurred
1: The content of the counter has matched the content of OC1[0:7] or OC2[0:7] in LINOCR.
An interrupt is generated if the OCIE bit in LINIER register is set.
PE3
Parity Error Flag Rx3
This bit indicates if there is a parity error in the corresponding received byte (Rx3). No interrupt is
generated if this error occurs.
0: No parity error
1: Parity error
PE2
Parity Error Flag Rx2
This bit indicates if there is a parity error in the corresponding received byte (Rx2). No interrupt is
generated if this error occurs.
0: No parity error
1: Parity error
PE1
Parity Error Flag Rx1
This bit indicates if there is a parity error in the corresponding received byte (Rx1). No interrupt is
generated if this error occurs.
0: No parity error
1: Parity error
PE0
Parity Error Flag Rx0
This bit indicates if there is a parity error in the corresponding received byte (Rx0). No interrupt is
generated if this error occurs.
0: No parity error
1: Parity error
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Chapter 24 LIN Controller (LINFlexD)
Table 24-17. UARTSR field descriptions (continued)
Field
Description
RMB
Release Message Buffer
0: Buffer is free
1: Buffer ready to be read by software. This bit must be cleared by software after reading data received
in the buffer.
This bit is cleared by hardware in Initialization mode.
FEF
Framing Error Flag
This bit is set by hardware and indicates to the software that LINFlexD has detected a framing error
(invalid stop bit).
BOF
FIFO/buffer overrun flag
This bit is set by hardware when a new data byte is received and the RMB bit is not cleared in UART
buffer mode. In UART FIFO mode, this bit is set when there is a new byte and the Rx FIFO is full. In
UART FIFO mode, once Rx FIFO is full, the new received message is discarded regardless of the
value of LINCR1[RBLM].
If LINCR1[RBLM] = 1, the new byte received is discarded.
If LINCR1[RBLM] = 0, the new byte overwrites buffer.
This field can be cleared by writing a 1 to it. An interrupt is generated if LINIER[BOIE] is set.
RPS
LIN Receive Pin State
This bit reflects the current status of LINRX pin for diagnostic purposes.
WUF
Wake-up Flag
This bit is set by hardware and indicates to the software that LINFlexD has detected a falling edge on
the LINRX pin in Sleep mode.
This bit must be cleared by software. It is reset by hardware in Initialization mode.
An interrupt i generated if WUIE bit in LINIER is set.
TO
Timeout
The LINFlexD controller sets this field when a UART timeout occurs — that is, when the value of
UARTCTO becomes equal to the preset value of the timeout (UARTPTO register setting). This field
should be cleared by software. The GCR[SR] field should be used to reset the receiver FSM to idle
state in case of UART timeout for UART reception depending on the application both in buffer and
FIFO mode.
An interrupt is generated when LINIER[DBEIETOIE] is set on the Error interrupt line in UART mode.
DRFRFE
Data reception completed flag / Rx FIFO empty flag
The LINFlexD controller sets this field as follows:
• In UART buffer mode (RFBM = 0), it indicates that the number of bytes programmed in RDFL has
been received. This field should be cleared by software. An interrupt is generated if LINIER[DRIE]
is set. This field is set in case of framing error, parity error, or overrun. This field reflects the same
value as in LINESR when in Initialization mode and UART bit is set.
• In UART FIFO mode (RFBM = 1), it indicates that the Rx FIFO is empty. This field is a read-only
field used internally by the DMA Rx interface.
DTFTFF
Data transmission completed flag / Tx FIFO full flag
The LINFlexD controller sets this field as follows:
• In UART buffer mode (TFBM = 0), it indicates that the data transmission is completed. This field
should be cleared by software. An interrupt is generated if LINIER[DTIE] is set. This field reflects
the same value as in LINESR when in Initialization mode and UART bit is set.
• In UART FIFO mode (TFBM = 1), it indicates that the Tx FIFO is full. This field is a read-only field
used internally by the DMA Tx interface.
NF
Noise Flag
This bit is set by hardware when noise is detected on a received character. This bit is cleared by
software.
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Chapter 24 LIN Controller (LINFlexD)
24.10.7 LIN timeout control status register (LINTCSR)
Offset: 0x18
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
W
Reset
Reset
1
These fields are writable only in Initialization mode (LINCR1[INIT] = 1).
Figure 24-24. LIN timeout control status register (LINTCSR)
Table 24-18. LINTCSR field descriptions
Name
LTOM
IOT
TOCE
CNT
Description
LIN timeout mode
0: LIN timeout mode (header, response and frame timeout detection)
1: Output compare mode
This bit can be set/cleared in Initialization mode only.
Idle on Timeout
0: LIN state machine not reset to Idle on timeout event
1: LIN state machine reset to Idle on timeout event
This bit can be set/cleared in Initialization mode only.
Timeout counter enable
0: Timeout counter disable. OCF bit in LINESR or UARTSR is not set on an output compare event.
1: Timeout counter enable. OCF bit is set if an output compare event occurs.
TOCE bit is configurable by software in Initialization mode. If LIN state is not Init and if timer is in LIN
timeout mode, then hardware takes control of TOCE bit.
Counter Value
These bits indicate the LIN Timeout counter value.
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Chapter 24 LIN Controller (LINFlexD)
24.10.8 LIN output compare register (LINOCR)
Offset: 0x1C
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1
1
1
W
Reset
R
1
OC1
1
w1c1
OC2
W
w1c
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
If LINTCSR[LTOM] = 0, these fields are read-only.
Figure 24-25. LIN output compare register (LINOCR)
Table 24-19. LINOCR field descriptions
Field
Description
OC2
Output compare 2 value
These bits contain the value to be compared to the value of LINTCSR[CNT].
OC1
Output compare 1 value
These bits contain the value to be compared to the value of LINTCSR[CNT].
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Chapter 24 LIN Controller (LINFlexD)
24.10.9 LIN timeout control register (LINTOCR)
Offset: 0x20
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
1
0
0
W
Reset
R
0
HTO3
RTO
W
Reset
0
0
0
0
1
1
1
0
0
0
0/11
0/12
1
1
Resets to 1 in Slave mode and to 0 in Master mode
Resets to 0 in Slave mode and to 1 in Master mode
3 HTO field can only be written in slave mode, LINCR1[MME] = 0.
2
Figure 24-26. LIN timeout control register (LINTOCR)
Table 24-20. LINTOCR field descriptions
Field
Description
RTO
Response timeout value
This register contains the response timeout duration (in bit time) for 1 byte.
The reset value is 0xE = 14, corresponding to TResponse_Maximum = 1.4 x TResponse_Nominal
HTO
Header timeout value
This register contains the header timeout duration (in bit time). This value does not include the first 11
dominant bits of the Break. The reset value depends on which mode LINFlexD is in.
HTO can be written only for Slave mode.
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Chapter 24 LIN Controller (LINFlexD)
24.10.10 LIN fractional baud rate register (LINFBRR)
Offset: 0x24
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
DIV_F1
W
Reset
1
0
0
0
0
This field is writable only in Initialization mode, LINCR1[INIT] = 1.
Figure 24-27. LIN timeout control register (LINTOCR)
Table 24-21. LINFBRR field descriptions
Field
Description
DIV_F
Fraction bits of LFDIV
The 4 fraction bits define the value of the fraction of the LINFlexD divider (LFDIV).
Fraction (LFDIV) = Decimal value of DIV_F / 16.
This register can be written in Initialization mode only, LINCR1[INIT] = 1.
24.10.11 LIN integer baud rate register (LINIBRR)
Offset: 0x28
0
Access: User read/write
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0
DIV_M1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1
This field is writable only in Initialization mode (LINCR1[INIT] = 1).
Figure 24-28. LIN integer baud rate register (LINIBRR)
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Chapter 24 LIN Controller (LINFlexD)
Table 24-22. LINIBRR field descriptions
Field
Description
DIV_M
LFDIV mantissa
These bits define the LINFlexD divider (LFDIV) mantissa value (see Table 24-23).
This register can be written in Initialization mode only.
Table 24-23. Integer baud rate selection
DIV_M
Mantissa
0x0
LIN clock disabled
0x1
1
...
...
0xFFFFE
1048574
0xFFFFF
1048575
24.10.12 LIN checksum field register (LINCFR)
Offset: 0x2C
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
CF
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Figure 24-29. LIN checksum field register (LINCFR)
Table 24-24. LINCFR field descriptions
Field
CF
Description
Checksum bits
When LINCR1[CCD] is cleared, these bits are read-only. When LINCR1[CCD] is set, these bits are
read/write. See Table 24-10.
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Chapter 24 LIN Controller (LINFlexD)
24.10.13 LIN control register 2 (LINCR2)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
IOPE1
R
Access: User read/write
IOBE1
Offset: 0x30
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
2
1
0/12
HTRQ
Reset
ABRQ
W
DTRQ
R
DDRQ
Reset
WURQ
W
w1c
w1c
w1c
w1c
w1c
0
0
0
0
0
These fields are writable only in Initialization mode (LINCR1[INIT] = 1.
Resets to 1 in Slave mode and to 0 in Master mode
Figure 24-30. LIN control register 2 (LINCR2)
Table 24-25. LINCR2 field descriptions
Field
Description
IOBE
Idle on Bit Error
0: Bit error does not reset LIN state machine
1: Bit error reset LIN state machine
This bit can be set/cleared in Initialization mode only (LINCR1[INIT]) = 1.
IOPE
Idle on Identifier Parity Error
0: Identifier Parity error does not reset LIN state machine.
1: Identifier Parity error reset LIN state machine.
This bit can be set/cleared in Initialization mode only (LINCR1[INIT]) = 1.
WURQ
Wake-up Generation Request
Setting this bit generates a wake-up pulse. It is reset by hardware when the wake-up character has
been transmitted. The character sent is copied from DATA0 in BDRL buffer. Note that this bit cannot
be set in Sleep mode. Software has to exit Sleep mode before requesting a wake-up. Bit error is not
checked when transmitting the wake-up request.
DDRQ
Data Discard Request
Set by software to stop data reception if the frame does not concern the node. This bit is reset by
hardware once LINFlexD has moved to idle state. In Slave mode, this bit can be set only when HRF
bit in LINSR is set and identifier did not match any filter.
DTRQ
Data Transmission Request
Set by software in Slave mode to request the transmission of the LIN Data field stored in the Buffer
data register. This bit can be set only when HRF bit in LINSR is set.
Cleared by hardware when the request has been completed or aborted or on an error condition.
In Master mode, this bit is set by hardware when DIR bit in BIDR is set and header transmission is
completed.
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Chapter 24 LIN Controller (LINFlexD)
Table 24-25. LINCR2 field descriptions (continued)
Field
Description
ABRQ
Abort Request
Set by software to abort the current transmission.
Cleared by hardware when the transmission has been aborted. LINFlexD aborts the transmission at
the end of the current bit.
This bit can also abort a wake-up request.
It can also be used in UART mode.
HTRQ
Header Transmission Request
Set by software to request the transmission of the LIN header.
Cleared by hardware when the request has been completed or aborted.
This bit has no effect in UART mode.
24.10.14 Buffer identifier register (BIDR)
This register contains the fields that identify a transaction and provide other information related to it.
All the fields in this register must be updated when an ID filter (enabled) in slave mode (Tx or Rx) matches
the ID received.
Offset: 0x34
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Reset
Figure 24-31. Buffer identifier register (BIDR)
Table 24-26. BIDR field descriptions
Field
Description
DFL
Data Field Length
These bits define the number of data bytes in the response part of the frame.
DFL = Number of data bytes – 1.
Normally, LIN uses only DFL[0:2] to manage frames with a maximum of 8 bytes of data. Identifier filters
are compatible with DFL[0:2] and DFL[0:5] . DFL[3:5] are provided to manage extended frames.
DIR
Direction
This bit controls the direction of the data field.
0: LINFlexD receives the data and copy them in the BDR registers.
1: LINFlexD transmits the data from the BDR registers.
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Chapter 24 LIN Controller (LINFlexD)
Table 24-26. BIDR field descriptions (continued)
Field
Description
CCS
Classic Checksum
This bit controls the type of checksum applied on the current message.
0: Enhanced Checksum covering Identifier and Data fields. This is compatible with LIN specification
2.0 and higher.
1: Classic Checksum covering Data fields only. This is compatible with LIN specification 1.3 and below.
ID
Identifier
Identifier part of the identifier field without the identifier parity.
24.10.15 Buffer data register least significant (BDRL)
Offset: 0x38
0
Access: User read/write
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
DATA3
DATA2
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
R
DATA1
DATA0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 24-32. Buffer data register least significant (BDRL)
Table 24-27. BDRL field descriptions
Field
Description
DATA3
Data Byte 3
Data byte 3 of the data field
DATA2
Data Byte 2
Data byte 2 of the data field
DATA1
Data Byte 1
Data byte 1 of the data field
DATA0
Data Byte 0
Data byte 0 of the data field
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Chapter 24 LIN Controller (LINFlexD)
24.10.16 Buffer data register most significant (BDRM)
Offset: 0x3C
0
Access: User read/write
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
DATA7
DATA6
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
R
DATA5
DATA4
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 24-33. Buffer data register most significant (BDRM)
Table 24-28. BDRM field descriptions
Field
Description
DATA7
Data Byte 7
Data byte 7 of the data field
DATA6
Data Byte 6
Data byte 6 of the data field
DATA5
Data Byte 5
Data byte 5 of the data field
DATA4
Data Byte 4
Data byte 4 of the data field
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Chapter 24 LIN Controller (LINFlexD)
24.10.17 Identifier filter enable register (IFER)
Offset: 0x40
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
FACT1
W
Reset
1
0
0
0
0
0
This field is writable only in Initialization mode (LINCR1[INIT] = 1).
Figure 24-34. Identifier filter enable register (IFER)
Table 24-29. IFER field descriptions
Field
FACT
Description
Filter activation (see Table 24-30)
The software sets the bit FACT[x] to activate the filters x in identifier list mode.
In identifier mask mode bits FACT(2n + 1) have no effect on the corresponding filters as they act as
masks for the Identifiers 2n.
0 Filters 2n and 2n + 1 are deactivated.
1 Filters 2n and 2n + 1 are activated.
Table 24-30. IFER[FACT] configuration
Bit
Value
FACT[0]
0
Filters 0 and 1 are deactivated.
1
Filters 0 and 1 are activated.
0
Filters 2 and 3 are deactivated.
1
Filters 2 and 3 are activated.
0
Filters 4 and 5 are deactivated.
1
Filters 4 and 5 are activated.
0
Filters 6 and 7 are deactivated.
1
Filters 6 and 7 are activated.
0
Filters 8 and 9 are deactivated.
1
Filters 8 and 9 are activated.
FACT[1]
FACT[2]
FACT[3]
FACT[4]
Result
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Chapter 24 LIN Controller (LINFlexD)
Table 24-30. IFER[FACT] configuration (continued)
Bit
Value
FACT[5]
0
Filters 10 and 11 are deactivated.
1
Filters 10 and 11 are activated.
0
Filters 12 and 13 are deactivated.
1
Filters 12 and 13 are activated.
0
Filters 14 and 15 are deactivated.
1
Filters 14 and 15 are activated.
FACT[6]
FACT[7]
Result
24.10.18 Identifier filter match index (IFMI)
Offset: 0x44
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Reset
Figure 24-35. Identifier filter match index (IFMI)
Table 24-31. IFMI field descriptions
Field
IFMI
Description
Filter match index
This register contains the index corresponding to the received ID. It can be used to directly write or
read the data in RAM (refer to Section 24.7.2, Slave mode, for more details).
When no filter matches, IFMI = 0. When Filter n is matching, IFMI = n + 1.
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Chapter 24 LIN Controller (LINFlexD)
24.10.19 Identifier filter mode register (IFMR)
Offset:0x48
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Reset
Figure 24-36. Identifier filter mode register (IFMR)
Table 24-32. IFMR field descriptions
Field
IFM
Description
Filter mode
0 Filters 2n and 2n + 1 are in identifier list mode.
1 Filters 2n and 2n + 1 are in mask mode (filter 2n + 1 is the mask for the filter 2n).
24.10.20 Identifier filter control registers (IFCR0–IFCR15)
The function of these registers is different depending on which mode the LINFlexD controller is in, as
described in Table 24-33.
Table 24-33. IFCR functionality based on mode
Mode
IFCR functionality
Identifier list
Each IFCR register acts as a filter.
Identifier mask
If a = (number of filters) / 2, and n = 0 to (a – 1),
then IFCR[2n] acts as a filter and IFCR[2n + 1] acts as the mask for IFCR[2n].
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0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
CCS1
R
Access: User read/write
DIR1
Offsets: 0x4C–0x88 (16 registers)
0
0
0
0
0
0
0
0
0
W
Reset
R
DFL1
W
Reset
0
1
0
0
0
0
0
ID1
0
0
0
These fields are writable only in Initialization mode (LINCR1[INIT] = 1).
Figure 24-37. Identifier filter control registers (IFCR0–IFCR15)
Table 24-34. IFCR field descriptions
Field
Description
DFL
Data Field Length
This field defines the number of data bytes in the response part of the frame.
DIR
Direction
This bit controls the direction of the data field.
0: LINFlexD receives the data and copy them in the BDRL and BDRM registers.
1: LINFlexD transmits the data from the BDRL and BDRM registers.
CCS
Classic Checksum
This bit controls the type of checksum applied on the current message.
0: Enhanced Checksum covering Identifier and Data fields. This is compatible with LIN specification
2.0 and higher.
1: Classic Checksum covering Data fields only. This is compatible with LIN specification 1.3 and below.
ID
Identifier
Identifier part of the identifier field without the identifier parity.
24.10.21 Global control register (GCR)
This register can be programmed only in Initialization mode. The configuration specified in this register
applies in both LIN and UART modes.
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0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
RDFBM1
TDLIS1
RDLIS1
STOP1
R
Access: User read/write
TDFBM1
Offset: 0x8C
0
SR1
0
0
0
0
0
0
W
Reset
R
W
Reset
0
1
0
0
0
0
0
0
0
0
0
This field is writable only in Initialization mode (LINCR1[INIT] = 1).
Figure 24-38. Global control register (GCR)
Table 24-35. GCR field descriptions
Field
Description
TDFBM
Transmit data first bit MSB
This field controls the first bit of transmitted data (payload only) as MSB/LSB in both UART and LIN
modes.
0 The first bit of transmitted data is LSB – that is, the first bit transmitted is mapped on the LSB bit
(BDR(0), BDR(8), BDR(16), BDR(24)).
1 The first bit of transmitted data is MSB – that is, the first bit transmitted is mapped on the MSB bit
(BDR(7), BDR(15), BDR(23), BDR(31)).
RDFBM
Received data first bit MSB
This field controls the first bit of received data (payload only) as MSB/LSB in both UART and LIN
modes.
0 The first bit of received data is LSB – that is, the first bit received is mapped on the LSB bit (BDR(0),
BDR(8), BDR(16), BDR(24)).
1 The first bit of received data is MSB – that is, the first bit received is mapped on the MSB bit
(BDR(7), BDR(15), BDR(23), BDR(31)).
TDLIS
Transmit data level inversion selection
This field controls the data inversion of transmitted data (payload only) in both UART and LIN modes.
0 Transmitted data is not inverted.
1 Transmitted data is inverted.
RDLIS
Received data level inversion selection
This field controls the data inversion of received data (payload only) in both UART and LIN modes.
0 Received data is not inverted.
1 Received data is inverted.
STOP
Stop bit configuration
This field controls the number of stop bits in transmitted data in both UART and LIN modes. The stop
bit is configured for all the fields (delimiter, sync, ID, checksum, and payload).
0 One stop bit
1 Two stop bits
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Chapter 24 LIN Controller (LINFlexD)
Table 24-35. GCR field descriptions (continued)
Field
Description
SR
Soft reset
If the software writes a 1 to this field, the LINFlexD controller executes a soft reset in which the FSMs,
FIFO pointers, counters, timers, status registers, and error registers are reset but the configuration
registers are unaffected.
This field always reads 0.
24.10.22 UART preset timeout register (UARTPTO)
This register contains the preset timeout value in UART mode, and is used to monitor the IDLE state of
the reception line. The timeout detection uses this register and the UARTCTO register described in
Section 24.10.23, UART current timeout register (UARTCTO).
Offset: 0x90
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
1
1
1
1
1
1
W
Reset
R
PTO
W
Reset
0
0
0
0
1
1
1
1
1
1
Figure 24-39. UART preset timeout register (UARTPTO)
Table 24-36. UARTPTO field descriptions
Field
PTO
Description
Preset value of the timeout counter
Do not set PTO = 0 (otherwise, UARTSR[TO] would immediately be set).
24.10.23 UART current timeout register (UARTCTO)
This register contains the current timeout value in UART mode, and is used in conjunction with the
UARTPTO register (see Section 24.10.22, UART preset timeout register (UARTPTO)) to monitor the
IDLE state of the reception line. UART timeout works in both CPU and DMA modes.
The timeout counter:
• Starts at 0 and counts upward
• Is clocked with the baud rate clock prescaled by a hard-wired scaling factor of 16
• Is automatically enabled when UARTCR[RXEN] = 1
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Offset: 0x94
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
CTO
W
Reset
0
0
0
0
0
0
Figure 24-40. UART current timeout register (UARTCTO)
Table 24-37. UARTCTO field descriptions
Field
Description
CTO
Current value of the timeout counter
This field is reset whenever one of the following occurs:
•
•
•
•
A new value is written to the UARTPTO register
The value of this field matches the value of UARTPTO[PTO]
A hard or soft reset occurs
New incoming data is received
When CTO matches the value of UARTPTO[PTO], UARTSR[TO] is set.
24.10.24 DMA Tx enable register (DMATXE)
This register enables the DMA Tx interface.
Offset: 0x98
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Reset
Figure 24-41. DMA Tx enable register (DMATXE)
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Table 24-38. DMATXE field descriptions
Field
Description
DTEn
DMA Tx channel n enable
0 DMA Tx channel n disabled
1 DMA Tx channel n enabled
Note: When DMATXE = 0x0, the DMA Tx interface FSM is forced (soft reset) into the IDLE state.
24.10.25 DMA Rx enable register (DMARXE)
This register enables the DMA Rx interface.
Offset: 0x9C
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Reset
Figure 24-42. DMA Rx enable register (DMARXE)
Table 24-39. DMARXE field descriptions
Field
DREn
Description
DMA Rx channel n enable
0 DMA Rx channel n disabled
1 DMA Rx channel n enabled
Note: When DMARXE = 0x0, the DMA Rx interface FSM is forced (soft reset) into the IDLE state.
24.11 DMA interface
The LINFlexD DMA interface offers a parametric and programmable solution with the following features:
• LIN Master node, TX mode: single DMA channel
• LIN Master node, RX mode: single DMA channel
• LIN Slave node, TX mode: 1 to N DMA channels where N = max number of ID filters
• LIN Slave node, RX mode: 1 to N DMA channels where N = max number of ID filters
• UART node, TX mode: single DMA channel
• UART node, RX mode: single DMA channel + timeout
The LINFlexD controller interacts with an enhanced direct memory access (eDMA) controller; see the
description of that controller for details on its operation and the transfer control descriptors (TCDs)
referenced in this section.
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24.11.1 Master node, TX mode
On a master node in TX mode, the DMA interface requires a single TX channel. Each TCD controls a
single frame, except for the extended frames (multiple TCDs). The memory map associated with the TCD
chain (RAM area and LINFlexD registers) is shown in Figure 24-43.
RAM area
LINFlex2 registers
LINCR2 (4 bytes)
TCD (n)
TCD (n+1)
TCD (n+2)
Linked
chain
TCD (n+3)
DMA transfer
LINCR2 (4 bytes)
BIDR (4 bytes)
BIDR (4 bytes)
BDRL + BDRM
(4/8 bytes)
BDRL + BDRM
(4/8 bytes)
LINCR2 (4 bytes)
LINCR2 (4 bytes)
BIDR (4 bytes)
BIDR (4 bytes)
LINCR2 (4 bytes)
LINCR2 (4 bytes)
BIDR (4 bytes)
BIDR (4 bytes)
BDRL + BDRM
(8 bytes)
BDRL + BDRM
(8 bytes)
BDRL + BDRM
(4/8 bytes)
BDRL + BDRM
(4/8 bytes)
Frame (n)
Master  Slave
Frame (n+1)
Slave  Master
or
Slave  Slave
Extended
Frame (n+2)
Master  Slave
Extended
Frame (n+3)
Master  Slave
1 DMA TX channel (TCD single and/or linked chain)
Figure 24-43. TCD chain memory map (master node, TX mode)
The TCD chain of the DMA Tx channel on a master node supports:
• Master to Slave: transmission of the entire frame (header + data)
• Slave to Master: transmission of the header. The data reception is controlled by the Rx channel on
the master node.
• Slave to Slave: transmission of the header.
The register settings for the LINCR2 and BIDR registers for each class of LIN frame are shown in
Table 24-40.
Table 24-40. Register settings (master node, TX mode)
LIN frame
Master to Slave
LINCR2
DDRQ=1
DTRQ=0
HTRQ=0
BIDR
DFL = payload size
ID = address
CCS = checksum
DIR = 1 (TX)
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Table 24-40. Register settings (master node, TX mode) (continued)
LIN frame
LINCR2
BIDR
Slave to Master
DDRQ=0
DTRQ=0
HTRQ=0
DFL = payload size
ID = address
CCS = checksum
DIR = 0 (RX)
Slave to Slave
DDRQ=1
DTRQ=0
HTRQ=0
DFL = payload size
ID = address
CCS = checksum
DIR = 0 (RX)
The concept FSM to control the DMA TX interface is shown in Figure 24-44. The DMA TX FSM will
move to IDLE state immediately at next clock edge if DMATXE[0] = 0.
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Chapter 24 LIN Controller (LINFlexD)
Enables DMA TX
channel request
(DMAERQH, DMAERQL)
!DTF &
!DRF & (LIN idle |
DBEF) & DMA_TEN &
!Token_DMA_RX
?
False
True
DMA TX transfer (Req/Ack
minor/major loop) from
RAM area to LINFlex registers
DMA TX
transfer is completed
?
False
True
DBEF
?
True
False
Set HTRQ to transmit the
LIN frame (header + [data])
True (RX mode)
Clear DBEF to transmit the LIN
frame (data for extended frame)
!DIR & !DDRQ
?
False (TX mode)
Set Token_DMA_RX to enable
the DMA RX interface
DTF
?
False
True (end of frame)
Clear DTF
DBEF
?
False
True
(extended frame,
size > 8 bytes)
Figure 24-44. FSM to control the DMA TX interface (master node)
The TCD settings (word transfer) are shown in Table 24-41. All other TCD fields are equal to 0. TCD
settings based on half-word or byte transfers are allowed.
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Chapter 24 LIN Controller (LINFlexD)
Table 24-41. TCD settings (master node, TX mode)
TCD field
Value
Description
CITER[14:0]
1
Single iteration for the major loop
BITER[14:0]
1
Single iteration for the major loop
NBYTES[31:0]
SADDR[31:0]
[4 + 4] + 0/4/8 = N Data buffer is stuffed with dummy bytes if the length is
not word aligned.
LINCR2 + BIDR + BDRL + BDRM
RAM address
SOFF[15:0]
4
Word increment
SSIZE[2:0]
2
Word transfer
SLAST[31:0]
–N
DADDR[31:0]
LINCR2 address
DOFF[15:0]
4
Word increment
DSIZE[2:0]
2
Word transfer
DLAST_SGA[31:0]
–N
No scatter/gather processing
INT_MAJ
0/1
Interrupt disabled/enabled
D_REQ
1
Only on the last TCD of the chain.
START
0
No software request
24.11.2 Master node, RX mode
On a master node in RX mode, the DMA interface requires a single RX channel. Each TCD controls a
single frame, except for the extended frames (multiple TCDs). The memory map associated to the TCD
chain (RAM area and LINFlexD registers) is shown in Figure 24-45.
LINFlex2 registers
Frame (n)
Slave  Master
Extended
Frame (n+1)
BIDR (4 bytes)
BDRL + BDRM
(4/8 bytes)
RAM area
DMA transfer
BIDR (4 bytes)
BDRL + BDRM
(4/8 bytes)
BIDR (4 bytes)
BIDR (4 bytes)
BDRL + BDRM
(8 bytes)
BDRL + BDRM
(8 bytes)
TCD (n)
TCD (n+1)
Linked
Extended
Frame (n+2)
BDRL + BDRM
(4/8 bytes)
BDRL + BDRM
(4/8 bytes)
chain
TCD (n+2)
1 DMA RX channel (TCD single and/or linked chain)
Figure 24-45. TCD chain memory map (master node, RX mode)
The TCD chain of the DMA Rx channel on a master node supports Slave-to-Master reception of the data
field.
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Chapter 24 LIN Controller (LINFlexD)
The BIDR register is optionally copied into the RAM area. This BIDR field (part of FIFO data) contains
the ID of each message to allow the CPU to figure out which ID was received by the LINFlexD DMA if
only the “one DMA channel” setup is used.
The concept FSM to control the DMA RX interface is shown in Figure 24-46. The DMA RX FSM will
move to IDLE state immediately at next clock edge if DMARXE[0]=0.
Enables DMA RX
channel request
(DMAERQH, DMAERQL)
(DRF |
(DBFF & RMB))
& Token_DMA_RX &
DMA_REN
?
False
True
DMA RX transfer (Req/Ack
minor/major loop) from
LINFlex registers to RAM area
DMA RX
transfer done
?
False
True
False
DRF
?
True
DBFF & RMB
?
False
True
(extended frame,
size > 8 bytes)
Clear Token_DMA_RX
Clear DBFF, RMB
(for extended frame)
Clear DRF
Figure 24-46. FSM to control the DMA RX interface (master node)
The TCD settings (word transfer) are shown in Table 24-42. All other TCD fields are equal to 0. TCD
settings based on half-word or byte transfer are allowed.
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Chapter 24 LIN Controller (LINFlexD)
Table 24-42. TCD settings (master node, RX mode)
TCD field
Value
Description
CITER[14:0]
1
Single iteration for the major loop
BITER[14:0]
1
Single iteration for the major loop
NBYTES[31:0]
[4] + 4/8 = N
Data buffer is stuffed with dummy bytes if the length is not
word aligned.
BIDR + BDRL + BDRM
SADDR[31:0]
BIDR address
SOFF[15:0]
4
Word increment
SSIZE[2:0]
2
Word transfer
SLAST[31:0]
–N
DADDR[31:0]
RAM address
DOFF[15:0]
4
Word increment
DSIZE[2:0]
2
Word transfer
DLAST_SGA[31:0]
–N
No scatter/gather processing
INT_MAJ
0/1
Interrupt disabled/enabled
D_REQ
1
Only on the last TCD of the chain.
START
0
No software request
24.11.3 Slave node, TX mode
On a slave node in TX mode, the DMA interface requires a DMA TX channel for each ID filter
programmed in TX mode. In case a single DMA TX channel is available, a single ID field filter must be
programmed in TX mode. Each TCD controls a single frame, except for the extended frames (multiple
TCDs). The memory map associated to the TCD chain (RAM area and LINFlexD registers) is shown in
Figure 24-47.
LINFlex2 registers
RAM area
DMA transfer
TCD (n)
BDRL + BDRM
(4/8 bytes)
BDRL + BDRM
(4/8 bytes)
Frame (n)
Slave  Master
Slave  Slave
TCD (n+1)
BDRL + BDRM
(8 bytes)
BDRL + BDRM
(8 bytes)
Extended
Frame (n+1)
BDRL + BDRM
(4/8 bytes)
BDRL + BDRM
(4/8 bytes)
Extended
Frame (n+2)
Linked
chain
TCD (n+2)
1 DMA TX channel/filter (TCD single and/or linked chain)
Figure 24-47. TCD chain memory map (slave node, TX mode)
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The TCD chain of the DMA Tx channel on a slave node supports:
• Slave to Master: transmission of the data field
• Slave to Slave: transmission of the data field
The register settings of the LINCR2, IFER, IFMR, and IFCR registers are shown in Table 24-43.
Table 24-43. Register settings (slave node, TX mode)
LIN frame
LINCR2
IFER
Slave to Master
DDRQ = 0 To enable an ID filter
or Slave to Slave DTRQ = 0 (Tx mode) for each
HTRQ = 0 DMA TX channel
IFMR
Identifier list mode
Identifier mask mode
IFCR
DFL = payload size
ID = address
CCS = checksum
DIR = 1(TX)
The concept FSM to control the DMA Tx interface is shown in Figure 24-48. DMA TX FSM will move
to idle state if DMATXE[x] = 0, where x = IFMI – 1.
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Chapter 24 LIN Controller (LINFlexD)
Enables DMA TX
channel/filter request
(DMAERQH, DMAERQL)
!DTF &
!DRF & (DBEF |
HRF) & (IFMI != 0) &
DMA_TEN
?
False
True
DMA TX transfer (Req/Ack) from
RAM area to LINFlex registers
(channel/filter mapping)
DMA TX
transfer done
?
False
True
DBEF
?
True
False
False
Set DTRQ to transmit the
LIN frame (data)
Clear DBEF to transmit the LIN
frame (data for extended frame)
DTF
?
DBEF
?
True
False
True
(extended frame,
size > 8 bytes)
Clear DTF
Figure 24-48. FSM to control the DMA TX interface (slave node)
The TCD settings (word transfer) are shown in Table 24-44. All other TCD fields are equal to 0. TCD
settings based on half-word or byte transfer are allowed.
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Table 24-44. TCD settings (slave node, TX mode)
TCD field
Value
Description
CITER[14:0]
1
Single iteration for the major loop
BITER[14:0]
1
Single iteration for the major loop
NBYTES[31:0]
4/8 = N
SADDR[31:0]
RAM address
Data buffer is stuffed with dummy bytes if the length is not
word aligned.
BDRL + BDRM
SOFF[15:0]
4
Word increment
SSIZE[2:0]
2
Word transfer
SLAST[31:0]
–N
DADDR[31:0]
BDRL address
DOFF[15:0]
4
Word increment
DSIZE[2:0]
2
Word transfer
DLAST_SGA[31:0]
–N
No scatter/gather processing
INT_MAJ
0/1
Interrupt disabled/enabled
D_REQ
1
Only on the last TCD of the chain.
START
0
No software request
24.11.4 Slave node, RX mode
On a slave node in RX mode, the DMA interface requires a DMA RX channel for each ID filter
programmed in RX mode. In case a single DMA RX channel is available, a single ID field filter must be
programmed in RX mode. Each TCD controls a single frame, except for the extended frames (multiple
TCDs). The memory map associated to the TCD chain (RAM area and LINFlexD registers) is shown in
Figure 24-49.
RAM area
LINFlex2 registers
Frame (n)
Master  Slave
Slave  Slave
Extended
Frame (n+1)
BIDR (4 bytes)
BDRL + BDRM
(4/8 bytes)
DMA transfer
BIDR (4 bytes)
BDRL + BDRM
(4/8 bytes)
BIDR (4 bytes)
BIDR (4 bytes)
BDRL + BDRM
(8 bytes)
BDRL + BDRM
(8 bytes)
TCD (n)
TCD (n+1)
Linked
Extended
Frame (n+2)
BDRL + BDRM
(4/8 bytes)
BDRL + BDRM
(4/8 bytes)
chain
TCD (n+2)
1 DMA RX channel/filter (TCD single and/or linked chain)
Figure 24-49. TCD chain memory map (slave node, RX mode)
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Chapter 24 LIN Controller (LINFlexD)
The TCD chain of the DMA RX channel on a slave node supports:
• Master to Slave: reception of the data field.
• Slave to Slave: reception of the data field.
The register setting of the LINCR2, IFER, IFMR, and IFCR registers are given in Table 24-45.
Table 24-45. Register settings (slave node, RX mode)
LIN frame
LINCR2
IFER
Master to Slave DDRQ = 0 To enable an ID filter
or Slave to Slave DTRQ = 0 (Rx mode) for each
HTRQ = 0 DMA RX channel
IFMR
Identifier list mode
Identifier mask mode
IFCR
DFL = payload size
ID = address
CCS = checksum
DIR = 0 (RX)
The concept FSM to control the DMA Rx interface is shown in Figure 24-50. DMA RX FSM will move
to idle state if DMARXE[x] = 0 where x = IFMI – 1.
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Chapter 24 LIN Controller (LINFlexD)
Enables DMA RX
channel/filter request
(DMAERQH, DMAERQL)
!DTF &
(DRF | (DBFF &
RMB)) & (IFMI != 0) &
DMA_REN
?
False
True
DMA RX transfer (Req/Ack) from
LINFlex registers to RAM area
(channel/filter mapping)
DMA RX
transfer done
?
False
True
False
DRF
?
True
Clear DRF
DBFF & RMB
?
False
True
(extended frame,
size > 8 bytes)
Clear DBFF, RMB
(for extended frame)
Figure 24-50. FSM to control the DMA RX interface (slave node)
The TCD settings (word transfer) are shown in Table 24-46. All other TCD fields = 0. TCD settings based
on half-word or byte transfer are allowed.
Table 24-46. TCD settings (slave node, RX mode)
TCD Field
Value
Description
CITER[14:0]
1
Single iteration for the major loop
BITER[14:0]
1
Single iteration for the major loop
NBYTES[31:0]
[4] + 4/8 = N
SADDR[31:0]
BDRL address
Data buffer is stuffed with dummy bytes if the length
is not word aligned.
BIDR + BDRL + BDRM
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Table 24-46. TCD settings (slave node, RX mode) (continued)
TCD Field
Value
Description
SOFF[15:0]
4
Word increment
SSIZE[2:0]
2
Word transfer
SLAST[31:0]
–N
DADDR[31:0]
RAM address
DOFF[15:0]
4
Word increment
DSIZE[2:0]
2
Word transfer
DLAST_SGA[31:0]
–N
No scatter/gather processing
INT_MAJ
0/1
Interrupt disabled/enabled
D_REQ
1
Only on the last TCD of the chain.
START
0
No software request
24.11.5 UART node, TX mode
In UART TX mode, the DMA interface requires a DMA TX channel. A single TCD can control the
transmission of an entire Tx buffer. The memory map associated with the TCD chain (RAM area and
LINFlexD registers) is shown in Figure 24-51.
RAM area
LINFlex2 registers
DMA transfer (8/16-bit data format)
BDRL
(M bytes)
BDRL
(4 bytes FIFO mode)
BDRL
(M half-words)
BDRL
(2 half-words FIFO mode)
BDRL
(M bytes)
BDRL
(4 bytes FIFO mode)
BDRL
(M half-words)
BDRL
(2 half-words FIFO mode)
Buffer (n)
TCD (n)
TCD (n+1)
Buffer (n+1)
1 DMA TX channel (TCD single and/or linked chain)
Figure 24-51. TCD chain memory map (UART node, TX mode)
The UART TX buffer must be configured in FIFO mode in order to:
• Allow the transfer of large data buffer by a single TCD
• Adsorb the latency, following a DMA request (due to the DMA arbitration), to move data from the
RAM to the FIFO
• Use low priority DMA channels
• Support the UART baud rate (2 Mb/s) without underrun events
The Tx FIFO size is:
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•
•
4 bytes in 8-bit data format
2 half-words in 16-bit data format
A DMA request is triggered by FIFO not full (TX) status signals.
The concept FSM to control the DMA TX interface is shown in Figure 24-52. DMA TX FSM will move
to idle state if DMATXE[0] = 0.
UART TX buffer (FIFO mode)
Set TXEN
Enables DMA TX
channel request
(DMAERQH, DMAERQL)
!TFF & DMA_TEN
?
False
True
DMA TX transfer (Req/Ack) from
RAM area to UART TX FIFO
True
DMA TX
(major loop) done
?
False
DMA TX
(minor loop) done
?
False
True
False
!TFF
?
True
Figure 24-52. FSM to control the DMA TX interface (UART node)
The TCD settings (typical case) are shown in Table 24-47. All other TCD fields = 0. The minor loop
transfers a single byte/half-word as soon a free entry is available in the Tx FIFO.
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Table 24-47. TCD settings (UART node, TX mode)
Value
TCD Field
Description
8-bit data
16-bit data
CITER[14:0]
M
Multiple iterations for the major loop
BITER[14:0]
M
Multiple iterations for the major loop
NBYTES[31:0]
1
SADDR[31:0]
2
Minor loop transfer = 1 or 2 bytes
RAM address
SOFF[15:0]
1
2
Byte/half-word increment
SSIZE[2:0]
0
1
Byte/half-word transfer
–M
–M × 2
SLAST[31:0]
DADDR[31:0]
BDRL address
DOFF[15:0]
DADDR = BDRL + 0x3 for byte transfer
DADDR = BDRL + 0x2 for half-word
transfer
0
DSIZE[2:0]
0
No increment (FIFO)
1
DLAST_SGA[31:0]
0
INT_MAJ
0/1
Byte/Half-word transfer
No scatter/gather processing
Interrupt disabled/enabled
D_REQ
1
Only on the last TCD of the chain.
START
0
No software request
24.11.6 UART node, RX mode
In UART RX mode, the DMA interface requires a DMA RX channel. A single TCD can control the
reception of an entire Rx buffer. The memory map associated with the TCD chain (RAM area and
LINFlexD registers) is shown in Figure 24-53.
LINFlex2 registers
RAM area
DMA transfer (8/16-bit data format)
BDRM
(4 bytes FIFO mode)
BDRM
(M bytes)
BDRM
(2 half-words FIFO mode)
BDRM
(M half-words)
BDRM
(4 bytes FIFO mode)
BDRM
(M bytes)
BDRM
(2 half-words FIFO mode)
BDRM
(M half-words)
Buffer (n)
TCD (n)
Buffer (n+1)
TCD (n+1)
1 DMA RX channel (TCD single and/or linked chain)
Figure 24-53. TCD chain memory map (UART node, RX mode)
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The UART RX buffer must be configured in FIFO mode in order to:
• Allow the transfer of large data buffer by a single TCD
• Adsorb the latency, following a DMA request (due to the DMA arbitration), to move data from the
FIFO to the RAM
• Use low priority DMA channels
• Support high UART baud rate (at least 2 Mb/s) without overrun events
The Rx FIFO size is:
• 4 bytes in 8-bit data format
• 2 half-words in 16-bit data format
This is sufficient because just one byte allows a reaction time of about 3.8 s (at 2 Mbit/s), corresponding
to about 450 clock cycles at 120 MHz, before the transmission is affected. A DMA request is triggered by
FIFO not empty (RX) status signals.
The concept FSM to control the DMA Rx interface is shown in Figure 24-54. DMA Rx FSM will move
to idle state if DMARXE[0] = 0.
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Chapter 24 LIN Controller (LINFlexD)
UART RX buffer (FIFO mode)
TIMEOUT config
Set RXEN
Enables DMA RX
channel request
(DMAERQH, DMAERQL)
!RFE & DMA_REN
?
False
True
TIMEOUT restart
DMA RX transfer (Req/Ack) from
UART RX FIFO to RAM area
True
DMA RX
(major loop) done
?
False
DMA RX
(minor loop) done
?
False
True
!RFE
?
True
False
False
TIMEOUT
?
True
Set TIMEOUT flag
Figure 24-54. FSM to control the DMA RX interface (UART node)
The TCD settings (typical case) are shown in Table 24-48. All other TCD fields = 0. The minor loop
transfers a single byte/half-word as soon an entry is available in the Rx FIFO. A new software reset bit is
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Chapter 24 LIN Controller (LINFlexD)
required that allows the LINFlexD FSMs to be reset in case this timeout state is reached or in any other
case. Timeout counter can be rewritten by software at any time to extend timeout period.
Table 24-48. TCD settings (UART node, RX mode)
Value
TCD Field
Description
8 bits data
16 bits data
CITER[14:0]
M
Multiple iterations for the major loop
BITER[14:0]
M
Multiple iterations for the major loop
NBYTES[31:0]
1
SADDR[31:0]
2
BDRM address
SOFF[15:0]
SSIZE[2:0]
Minor loop transfer = 1 or 2 bytes
SADDR = BDRM + 0x3 for byte transfer
SADDR = BDRM + 0x2 for half-word transfer
0
No increment (FIFO)
0
SLAST[31:0]
0
DADDR[31:0]
RAM address
1
Byte/half-word transfer
DOFF[15:0]
1
2
Byte/half-word increment
DSIZE[2:0]
0
1
Byte/half-word transfer
–M
–M × 2
DLAST_SGA[31:0]
INT_MAJ
0/1
No scatter/gather processing
Interrupt disabled/enabled
D_REQ
1
Only on the last TCD of the chain.
START
0
No software request
24.11.7 Use cases and limitations
•
•
•
•
•
•
In LIN slave mode, the DMA capability can be used only if the ID filtering mode is activated. The
number of ID filters enabled must be equal to the number of DMA channels enabled. The
correspondence between channel # and ID filter is based on IFMI (identifier filter match index).
In LIN master mode, both the DMA channels (TX and RX) must be enabled in case the DMA
capability is required.
In UART mode, the DMA capability can be used only if the UART Tx/Rx buffers are configured
as FIFOs.
DMA and CPU operating modes are mutually exclusive for the data/frame transfer on a UART or
LIN node. Once a DMA transfer is finished, the CPU can handle subsequent accesses.
Error management must be always executed via CPU enabling the related error interrupt sources.
The DMA capability does not provide support for the error management. Error management means
checking status bits, handling IRQs, and potentially canceling DMA transfers.
The DMA programming model must be coherent with the TCD setting defined in this document.
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Chapter 24 LIN Controller (LINFlexD)
24.12 Functional description
24.12.1 8-bit timeout counter
24.12.1.1 LIN timeout mode
Clearing the LTOM bit (setting its value to 0) in the LINTCSR enables the LIN timeout mode. The
LINOCR becomes read-only, and OC1 and OC2 output compare values in the LINOCR are automatically
updated by hardware.
This configuration detects header timeout, response timeout, and frame timeout.
Depending on the LIN mode (selected by the MME bit in LINCR1), the 8-bit timeout counter will behave
differently.
LIN timeout mode must not be enabled during LIN extended frames transmission or reception (that is, if
the data field length in the BIDR is configured with a value higher than 8 data bytes).
24.12.1.1.1 LIN Master mode
Field RTO in the LINTOCR can be used to tune response timeout and frame timeout values. Header
timeout value is fixed to HTO = 28-bit time.
Field OC1 checks THeader and TResponse and field OC2 checks TFrame (refer to Figure 24-55 (Header
and response timeout)).
When LINFlexD moves from Break delimiter state to Synch Field state (refer to Section 24.10.3, LIN
status register (LINSR)):
• OC1 is updated with the value of OCHeader (OCHeader = CNT + 28),
• OC2 is updated with the value of OCFrame (OCFrame = CNT + 28 + RTO × 9 (frame timeout
value for an 8-byte frame)
• the TOCE bit is set.
On the start bit of the first response data byte (and if no error occurred during the header reception), OC1
is updated with the value of OCResponse (OCResponse = CNT + RTO × 9 (response timeout value for an
8-byte frame)).
On the first response byte is received, OC1 and OC2 are automatically updated to check TResponse and
TFrame according to RTO (tolerance) and DFL.
On the checksum reception or in case of error in the header or response, the TOCE bit is reset.
If there is no response, frame timeout value does not take into account the DFL value, and an 8-byte
response (DFL = 7) is always assumed.
24.12.1.1.2 LIN Slave mode
Field RTO in the LINTOCR can be used to tune response timeout and frame timeout values. Header
timeout value is fixed to HTO.
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OC1 checks THeader and TResponse and OC2 checks TFrame (refer to Figure 24-55 (Header and
response timeout)).
When LINFlexD moves from Break state to Break Delimiter state (refer to Section 24.10.3, LIN status
register (LINSR)):
• OC1 is updated with the value of OCHeader (OCHeader = CNT + HTO),
• OC2 is updated with the value of OCFrame (OCFrame = CNT + HTO + RTO × 9 (frame timeout
value for an 8-byte frame)),
• The TOCE bit is set.
On the start bit of the first response data byte (and if no error occurred during the header reception), OC1
is updated with the value of OCResponse (OCResponse = CNT + RTO × 9 (response timeout value for an
8-byte frame)).
Once the first response byte is received, OC1 and OC2 are automatically updated to check TResponse and
TFrame according to RTO (tolerance) and DFL.
On the checksum reception or in case of error in the header or data field, the TOCE bit is reset.
Frame
Header
Response
Response
space
OC1
OCHeader
OCResponse
Break
OC2
OCFrame
Figure 24-55. Header and response timeout
24.12.1.2 Output compare mode
Setting LINTCSR[LTOM] = 1 enables the output compare mode. This mode allows the user to fully
customize the use of the counter.
OC1 and OC2 output compare values can be updated in the LINTOCR by software.
24.12.2 Interrupts
Table 24-49. LINFlexD interrupt control
Interrupt event
Event flag bit
Enable control bit
Interrupt vector
Header Received interrupt
HRF
HRIE
RXI 1
Data Transmitted interrupt
DTF
DTIE
TXI
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Table 24-49. LINFlexD interrupt control (continued)
Interrupt event
Event flag bit
Enable control bit
Interrupt vector
Data Received interrupt
DRF
DRIE
RXI
Data Buffer Empty interrupt
DBEF
DBEIE
TXI
Data Buffer Full interrupt
DBFF
DBFIE
RXI
Wake-up interrupt
WUPF
WUPIE
RXI
LIN State interrupt 2
LSF
LSIE
RXI
Buffer Overrun interrupt
BOF
BOIE
ERR
Framing Error interrupt
FEF
FEIE
ERR
Header Error interrupt
HEF
HEIE
ERR
Checksum Error interrupt
CEF
CEIE
ERR
Bit Error interrupt
BEF
BEIE
ERR
Output Compare interrupt
OCF
OCIE
ERR
Stuck at Zero interrupt
SZF
SZIE
ERR
1
In Slave mode, if at least one filter is configured as TX and enabled, header received interrupt vector
is RXI or TXI depending on the value of identifier received.
2 For debug and validation purposes.
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DTIE
DTF
DBEIE
DBEF
Tx
HRIE
HRF
LSIE
States
WUIE
WUF
DBFIE
DBFF
Rx
DRIE
DRF
HRIE
HRF
BOIE
BOF
FEIE
FEF
HEIE
SFEF,SDEF,IDPEF
Error
CEIE
CEF
BEIE
BEF
OCIE
OCF
SZIE
SZF
TOIE
TO
Figure 24-56. Interrupt diagram
24.12.3 Fractional baud rate generation
The baud rates for the receiver and transmitter are both set to the same value as programmed in the
Mantissa (LINIBRR) and Fraction (LINFBRR) registers.
Tx/Rx baud =
fipg_clock_lin
(16 × LFDIV)
LFDIV is an unsigned fixed point number. The 20-bit mantissa is coded in the LINIBRR register and the
fraction is coded in the LINFBRR register.
The following examples show how to derive LFDIV from LINIBRR and LINFBRR register values:
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Chapter 24 LIN Controller (LINFlexD)
Example 24-1.
If LINIBRR = 27d and LINFBRR = 12d, then
Mantissa (LFDIV) = 27d
Fraction (LFDIV) = 12/16 = 0.75d
Therefore LFDIV = 27.75d
Example 24-2.
To program LFDIV = 25.62d,
LINFBRR = 16 × 0.62 = 9.92, nearest real number 10d = Ah
LINIBRR = mantissa(25.620d) = 25d = 19h
NOTE
The Baud Counters are updated with the new value of the Baud Registers
after a write to LINIBRR. Hence the Baud Register value must not be
changed during a transaction. The LINFBRR (containing the Fraction bits)
must be programmed before LINIBRR.
NOTE
LFDIV must be greater than or equal to 1.5d, for example, LINIBRR = 1
and LINFBRR = 8. Therefore, the maximum possible baud rate is
fperiph_set_1_clk / 24.
24.13 Programming considerations
This section describes the various configurations in which the LINFlexD can be used.
24.13.1 Master node
Header
Data TX
Checksum TX
DIR = 1
Configure ID
DTF set
DFL, Data buffer
TXI Interrupt
Set HTRQ
Figure 24-57. Programming consideration: master node, transmitter
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Header
Data RX
Checksum RX
DIR = 0
and
DDRQ = 0
Configure ID, DFL
Set HTRQ
DRF set
RXI Interrupt
Figure 24-58. Programming consideration: master node, receiver
Header
Data TX
DIR = 1
IOBE = 1
Configure ID
BEF set
DFL, Data buffer
ERRI Interrupt
Set HTRQ
Header
Data TX
DIR = 1
Checksum TX
IOBE = 0
Configure ID
BEF set
DTF set
DFL, Data buffer
ERR Interrupt
TX Interrupt
Set HTRQ
Figure 24-59. Programming consideration: master node, transmitter, bit error
Header
Data RX
DIR = 0
and
DDRQ = 0
Configure ID, DFL
Set HTRQ
Checksum RX
CEF set
ERR Interrupt
Figure 24-60. Programming consideration: master node, receiver, checksum error
24.13.2 Slave node
Header
HRF set
RX Interrupt
Data TX
Configure CCS, DIR, DFL,
Data Buffers
Checksum TX
DTF set
TX Interrupt
Set DTRQ
Figure 24-61. Programming consideration: slave node, transmitter, no filters
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DDRQ = 0
Header
Data RX
HRF set
RX Interrupt
Checksum RX
Configure CCS, DIR, DFL
DRF set
RX Interrupt
Header
HRF set
RX Interrupt
DDRQ = 1
Figure 24-62. Programming consideration: slave node, receiver, no filters
Header
HRF set
RX Interrupt
Data TX
Configure DIR, DFL,
Data Buffers
Set DTRQ
BEF set
ERR Interrupt
IOBE = 1
Figure 24-63. Programming consideration: slave node, transmitter, no filters, bit error
Header
HRF set
RX Interrupt
Data RX
Checksum RX
Configure DIR, DFL
CEF set
DDRQ = 0
ERR Interrupt
Figure 24-64. Programming consideration: slave node, receiver, no filters, checksum error
Header
HRF set
TX Interrupt
(ID matched)
Data TX
Checksum TX
Write Data Buffers
DTF set
Set DTRQ
TX Interrupt
Note: This configuration can be used in case the slave never receives data (for
example, as with a sensor).
Figure 24-65. Programming consideration: slave node, at least one TX filter, BF is reset, ID matches filter
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Header
Data RX
Checksum RX
IFMI = ID matched+1
DRF set
RXI Interrupt
Figure 24-66. Programming consideration: slave node, at least one RX filter, BF is reset, ID matches filter
Header
ID not matching any filter
Figure 24-67. Programming consideration: slave node, RX only, TX only, RX and TX filters, ID not matching
filter, BF is reset
Header
HRF set
TX Interrupt
(ID has matched)
Data TX
Checksum TX
Write Data Buffers
DTF set
Set DTRQ
TX Interrupt
DDRQ = 0
Header
HRF set
RX Interrupt
(ID not matched)
Data RX
Configure CCS, DIR, DFL
Checksum RX
DRF set
RX Interrupt
Note: This configuration is used when:
a) All TX IDs are managed by filters
b) The number of other filters is not enough to manage all reception IDs
Figure 24-68. Programming consideration: slave node, TX filter, BF is set
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Header
Data receive
Checksum receive
IFMI = ID matched
DRF set
Receive interrupt
DDRQ = 0
Header
Data receive
HRF set
Receive interrupt
(ID not matched)
Configure CCS, DIR, DFL
(ID is receive)
Header
Data transmit
HRF set
Receive interrupt
Configure CCS, DIR, DFL,
data buffers
Checksum receive
DRF set
Receive interrupt
Checksum transmit
DTF set
Transmit interrupt
Set DTRQ
(ID is transmit)
Figure 24-69. Programming consideration: slave node, RX filter, BF is set
Header
Data transmit
HRF set
Transmit interrupt
(IFMI = ID matched+1)
Checksum transmit
Write data buffers
DTF set
Set DTRQ
Transmit interrupt
Header
Data receive
Checksum receive
IFMI = ID matched+1
DRF set
RXI interrupt
Header
Data receive/transmit
HRF set
Receive interrupt
(ID not matched)
Checksum receive/transmit
Configure CCS, DIR, DFL
DRF/DTF set
DDRQ = 0
Receive/transmit interrupt
Note: This configuration is used when:
a) The number of filters is not enough
b) Filters are used for most frequently used IDs to reduce CPU usage
Figure 24-70. Programming consideration: slave node, TX filter, RX filter, BF is set
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24.13.3 Extended frames
Header
8 bytes transmit
8 bytes transmit
HRF set Configure DIR, DFL,
DBEF
Receive interrupt CCS
set
(ID not matched) DTRQ =1
Refill buffer
Reset DBEF
Header
8 bytes receive
8 bytes receive
HRF set
Receive interrupt
(ID not matched)
Configure DIR, DFL, RMB,
CCS
DBFF
DDRQ = 0
set
Read buffer
Reset RMB
Checksum transmit
DTF set
Transmit interrupt
Checksum receive
DRF set
Receive interrupt
Figure 24-71. Programming consideration: extended frames
24.13.4 Timeout
Tresponse_max
OC1
Header receive/transmit
Data receive
OCF is set
ERR interrupt
Figure 24-72. Programming consideration: response timeout
Tframe_max
OC2
Header
transmit/receive
Data receive/transmit
OCF is set
ERR interrupt
Figure 24-73. Programming consideration: frame timeout
Theader_max
Header receive
Break
OC1
OCF is set
ERR interrupt
Figure 24-74. Programming consideration: header timeout
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Chapter 24 LIN Controller (LINFlexD)
24.13.5 UART mode
Data receive/transmit
Set TXen/RXen
Write buffer for transmit
DTF/DRF is set
Transmit/receive interrupt
Figure 24-75. Programming consideration: UART mode
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Chapter 24 LIN Controller (LINFlexD)
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Chapter 25 FlexCAN
Chapter 25
FlexCAN
25.1
Information specific to this device
This section presents device-specific parameterization and customization information not specifically
referenced in the remainder of this chapter.
25.1.1
Device-specific features
The device has six Controller Area Network (FlexCAN) blocks.
• Each block supports 64 Message Buffers (MB).
• DMA support is not provided.
• It is possible to operate the FlexCAN bit timing logic with either system clock or 4–40 MHz fast
external crystal oscillator clock (FXOSC).
• In the case of safe mode entry, the pad associated with CANTX can optionally be put into a
high-impedance state (not recessive state)
• Modes of operation:
— Four functional modes: Normal (User and Supervisor), Freeze, Listen-Only, and Loop-Back
— One low-power mode (Disable mode)
• 1056 bytes (64 MBs) of RAM used for MB storage
• 256 bytes (64 MBs) of RAM used for individual Rx Mask registers
• Hardware cancellation on Tx message buffers
• Module Configuration Register (MCR): Bits 5, 9, 12, and 13 are reserved
• Error and Status Register (ESR): Bit 31 is reserved
25.2
Introduction
The FlexCAN module is a communication controller implementing the CAN protocol according to the
CAN 2.0B protocol specification. A general block diagram is shown in Figure 25-1, which describes the
main sub-blocks implemented in the FlexCAN module, including two embedded memories, one for
storing Message Buffers (MB) and another one for storing Rx Individual Mask registers. Support for as
many as 64 Message Buffers is provided. The functions of the sub-modules are described in subsequent
sections.
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Chapter 25 FlexCAN
MB31
RXIMR63
RXIMR62
Message
Buffer
Management
CAN
Protocol
Interface
MB30
max MB #
CAN Tx
(0–31)
ID Mask
Storage
Message
Buffer
Storage
64/128/256byte RAM
288/544/1056byte RAM
RXIMR1
RXIMR0
CAN Rx
MB1
Bus Interface Unit
MB0
IP Bus Interface
Clocks, Address & Data buses,
Interrupt and Test Signals
Figure 25-1. FlexCAN block diagram
25.2.1
Overview
The CAN protocol was primarily, but not only, designed to be used as a vehicle serial data bus, meeting
the specific requirements of this field: real-time processing, reliable operation in the EMI environment of
a vehicle, cost-effectiveness, and required bandwidth. The FlexCAN module is a full implementation of
the CAN protocol specification, Version 2.0 B, which supports both standard and extended message
frames. A flexible number of Message Buffers (16, 32 or 64) is also supported. The Message Buffers are
stored in an embedded RAM dedicated to the FlexCAN module.
The CAN Protocol Interface (CPI) submodule manages the serial communication on the CAN bus,
requesting RAM access for receiving and transmitting message frames, validating received messages, and
performing error handling. The Message Buffer Management (MBM) submodule handles Message Buffer
selection for reception and transmission, taking care of arbitration and ID matching algorithms. The Bus
Interface Unit (BIU) submodule controls the access to and from the internal interface bus in order to
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Chapter 25 FlexCAN
establish connection to the CPU and to other blocks. Clocks, address and data buses, interrupt outputs, and
test signals are accessed through the Bus Interface Unit.
25.2.2
FlexCAN module features
The FlexCAN module includes these distinctive features:
• Full Implementation of the CAN protocol specification, Version 2.0B
— Standard data and remote frames
— Extended data and remote frames
— 0 to 8 bytes data length
— Programmable bit rate as fast as 1 Mbit/s
— Content-related addressing
• Flexible Message Buffers (as many as 64) of 0 to 8 bytes data length
• Each MB configurable as Rx or Tx, all supporting standard and extended messages
• Individual Rx Mask registers per Message Buffer (MB)
• Includes either 1056 bytes (64 MBs), 544 bytes (32 MBs), or 288 bytes (16 MBs) of RAM used
for MB storage
• Includes either 256 bytes (64 MBs), 128 bytes (32 MBs), or 64 bytes (16 MBs) of RAM used for
individual Rx Mask registers
• Full featured Rx FIFO with storage capacity for 6 frames and internal pointer handling
• Powerful Rx FIFO ID filtering, capable of matching incoming IDs against either 8 extended, 16
standard, or 32 partial (8 bits) IDs, with individual masking capability
• Selectable backwards compatibility with previous FlexCAN version
• Programmable clock source to the CAN Protocol Interface, either bus clock or crystal oscillator
• Unused MB and Rx Mask register space can be used as general purpose RAM space
• Listen only mode capability
• Programmable loopback mode supporting self-test operation
• Programmable transmission priority scheme: lowest ID, lowest buffer number or highest priority
• Time Stamp based on 16-bit free-running timer
• Global network time, synchronized by a specific message
• Maskable interrupts
• Independent of the transmission medium (an external transceiver is assumed)
• Short latency time due to an arbitration scheme for high-priority messages
• Low power modes, with programmable wake up on bus activity
25.2.3
Modes of operation
The FlexCAN module has four functional modes: Normal mode (User and Supervisor), Freeze mode,
Listen-Only mode, and Loop-Back mode. There is also a low-power mode (Disable mode).
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Chapter 25 FlexCAN
•
•
•
•
•
Normal mode (User or Supervisor):
In Normal Mode, the module operates receiving and/or transmitting message frames, errors are
handled normally and all the CAN Protocol functions are enabled. User and Supervisor Modes
differ in the access to some restricted control registers.
Freeze mode:
It is enabled when the FRZ bit in MCR is asserted. If enabled, Freeze Mode is entered when the
HALT bit in MCR is set or when Debug Mode is requested at MCU level. In this mode, no
transmission or reception of frames is done and synchronicity to the CAN bus is lost. See
Section 25.5.10.1, Freeze mode, for more information.
Listen-Only mode:
The module enters this mode when the LOM bit in CTRL is asserted. In this mode, transmission is
disabled, all error counters are frozen and the module operates in a CAN Error Passive mode. Only
messages acknowledged by another CAN station will be received. If FlexCAN detects a message
that has not been acknowledged, it will flag a BIT0 error (without changing the REC), as if it was
trying to acknowledge the message.
Loop-Back mode:
The module enters this mode when the LPB bit in CTRL is asserted. In this mode, FlexCAN
performs an internal loop back that can be used for self test operation. The bit stream output of the
transmitter is internally fed back to the receiver input. The Rx CAN input pin is ignored and the Tx
CAN output goes to the recessive state (logic 1). FlexCAN behaves as it normally does when
transmitting and treats its own transmitted message as a message received from a remote node. In
this mode, FlexCAN ignores the bit sent during the ACK slot in the CAN frame acknowledge field
to ensure proper reception of its own message. Both transmit and receive interrupts are generated.
Module Disable mode:
This low power mode is entered when the MCR[MDIS] bit is asserted by the CPU. When disabled,
the module requests to disable the clocks to the CAN Protocol Interface and Message Buffer
Management submodules. Exit from this mode is done by negating the MDIS bit in MCR. See
Section 25.5.10.2, Module Disable mode, for more information.
25.3
25.3.1
External signal description
Overview
The FlexCAN module has two I/O signals connected to the external MCU pins. These signals are
summarized in Table 25-1 and described in more detail in the next subsections.
Table 25-1. FlexCAN Signals
Signal Name1
1
Direction
Description
CAN Rx
Input
CAN Receive Pin
CAN Tx
Output
CAN Transmit Pin
The actual MCU pins may have different names.
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Chapter 25 FlexCAN
25.3.2
Signal descriptions
25.3.2.1
CAN Rx
This pin is the receive pin from the CAN bus transceiver. Dominant state is represented by logic level 0.
Recessive state is represented by logic level 1.
25.3.2.2
CAN Tx
This pin is the transmit pin to the CAN bus transceiver. Dominant state is represented by logic level 0.
Recessive state is represented by logic level 1.
25.4
Memory map/register definition
This section describes the registers and data structures in the FlexCAN module. The base address of the
module depends on the particular memory map of the MCU. The addresses presented here are relative to
the base address.
The address space occupied by FlexCAN has 96 bytes for registers starting at the module base address,
followed by MB storage space in embedded RAM starting at address 0x0060, and an extra ID Mask
storage space in a separate embedded RAM starting at address 0x0880.
25.4.1
FlexCAN memory mapping
The complete memory map for a FlexCAN module with 64 MBs capability is shown in Table 25-2.
All registers except for the MCR can be configured to have either supervisor or unrestricted access by
programming the MCR[SUPV] bit.
The IFLAG2 and IMASK2 registers are considered reserved space when FlexCAN is configured with 16
or 32 MBs. The Rx Global Mask (RXGMASK), Rx Buffer 14 Mask (RX14MASK), and the Rx Buffer 15
Mask (RX15MASK) registers are provided for backwards compatibility and are not used when the BCC
bit in MCR is asserted.
The address ranges 0x0060–0x047F and 0x0880–0x097F are occupied by two separate embedded
memories. These two ranges are completely occupied by RAM (1056 and 256 bytes, respectively) only
when FlexCAN is configured with 64 MBs. When it is configured with 16 MBs, the memory sizes are 288
and 64 bytes, so the address ranges 0x0180–0x047F and 0x08C0–0x097F are considered reserved space.
When it is configured with 32 MBs, the memory sizes are 544 and 128 bytes, so the address ranges
0x0280–0x047F and 0x0900–0x097F are considered reserved space. Furthermore, if the BCC bit in MCR
is negated, then the whole Rx Individual Mask registers address range (0x0880–0x097F) is considered
reserved space.
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Chapter 25 FlexCAN
Table 25-2. FlexCAN memory map
Base addresses:
0xFFFC_0000 (FlexCAN_0)
0xFFFC_4000 (FlexCAN_1)
0xFFFC_8000 (FlexCAN_2)
0xFFFC_C000 (FlexCAN_3)
0xFFFD_0000 (FlexCAN_4)
0xFFFD_4000 (FlexCAN_5)
Address offset
Register
Location
0x0000
Module Configuration (MCR)
on page 557
0x0004
Control Register (CTRL)
on page 561
0x0008
Free Running Timer (TIMER)
on page 564
0x000C
Reserved
0x0010
Rx Global Mask (RXGMASK)
on page 565
0x0014
Rx Buffer 14 Mask (RX14MASK)
on page 567
0x0018
Rx Buffer 15 Mask (RX15MASK)
on page 567
0x001C
Error Counter Register (ECR)
on page 567
0x0020
Error and Status Register (ESR)
on page 569
0x0024
Interrupt Masks 2 (IMASK2)
on page 572
0x0028
Interrupt Masks 1 (IMASK1)
on page 573
0x002C
Interrupt Flags 2 (IFLAG2)
on page 573
0x0030
Interrupt Flags 1 (IFLAG1)
on page 574
0x0034–0x007F
Reserved
0x0080–0x017F
Message Buffers MB0–MB15
—
0x0180–0x027F
Message Buffers MB16–MB31
—
0x0280–0x047F
Message Buffers MB32–MB63
—
0x0480–087F
Reserved
0x0880–0x08BC
Rx Individual Mask Registers RXIMR0–RXIMR15
on page 575
0x08C0–0x08FC
Rx Individual Mask Registers RXIMR16–RXIMR31
on page 575
0x0900–0x097C
Rx Individual Mask Registers RXIMR32–RXIMR63
on page 575
The FlexCAN module stores CAN messages for transmission and reception using a Message Buffer
structure. Each individual MB is formed by 16 bytes mapped on memory as described in Table 25-3.
Table 25-3 shows a Standard/Extended Message Buffer (MB0) memory map, using 16 bytes total
(0x80–0x8F space).
Table 25-3. Message Buffer MB0 memory mapping
Address Offset
MB Field
0x80
Control and Status (C/S)
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Chapter 25 FlexCAN
Table 25-3. Message Buffer MB0 memory mapping
25.4.2
0x84
Identifier Field
0x88–0x8F
Data Field 0 – Data Field 7 (1 byte each)
Message Buffer Structure
The Message Buffer structure used by the FlexCAN module is represented in Figure 25-2. Both Extended
and Standard Frames (29-bit Identifier and 11-bit Identifier, respectively) used in the CAN specification
(Version 2.0 Part B) are represented.
3
0x0
4
5
6
7
CODE
0x4
PRIO
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RTR
2
IDE
1
SRR
0
LENGTH
TIME STAMP
ID (Standard/Extended)
ID (Extended)
0x8
Data Byte 0
Data Byte 1
Data Byte 2
Data Byte 3
0xC
Data Byte 4
Data Byte 5
Data Byte 6
Data Byte 7
= Unimplemented or Reserved
Figure 25-2. Message Buffer Structure
Table 25-4. Message Buffer Structure field description
Field
Description
CODE
Message Buffer Code
This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part
of the message buffer matching and arbitration process. The encoding is shown in Table 25-5 and
Table 25-6. See Section 25.5, Functional description, for additional information.
SRR
Substitute Remote Request
Fixed recessive bit, used only in extended format. It must be set to 1 by the user for transmission (Tx
Buffers) and will be stored with the value received on the CAN bus for Rx receiving buffers. It can be
received as either recessive or dominant. If FlexCAN receives this bit as dominant, then it is
interpreted as arbitration loss.
0 Dominant is not a valid value for transmission in Extended Format frames.
1 Recessive value is compulsory for transmission in Extended Format frames.
IDE
ID Extended Bit
This bit identifies whether the frame format is standard or extended.
0 Frame format is standard.
1 Frame format is extended.
RTR
Remote Transmission Request
This bit is used for requesting transmissions of a data frame. If FlexCAN transmits this bit as 1
(recessive) and receives it as 0 (dominant), it is interpreted as arbitration loss. If this bit is transmitted
as 0 (dominant), then if it is received as 1 (recessive), the FlexCAN module treats it as bit error. If the
value received matches the value transmitted, it is considered as a successful bit transmission.
0 Indicates the current MB has a Data Frame to be transmitted.
1 Indicates the current MB has a Remote Frame to be transmitted.
Note: Do not configure the last Message Buffer to be the RTR frame.
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Chapter 25 FlexCAN
Table 25-4. Message Buffer Structure field description (continued)
Field
Description
LENGTH
Length of Data in Bytes
This 4-bit field is the length (in bytes) of the Rx or Tx data, which is located in offset 0x8 through 0xF
of the MB space (see Figure 25-2). In reception, this field is written by the FlexCAN module, copied
from the DLC (Data Length Code) field of the received frame. In transmission, this field is written by
the CPU and corresponds to the DLC field value of the frame to be transmitted. When RTR=1, the
Frame to be transmitted is a Remote Frame and does not include the data field, regardless of the
Length field.
TIME STAMP Free-Running Counter Time Stamp
This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when
the beginning of the Identifier field appears on the CAN bus.
PRIO
Local priority
This 3-bit field is only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers.
These bits are not transmitted. They are appended to the regular ID to define the transmission
priority. See Section 25.5.4, Arbitration process.
ID
Frame Identifier
In Standard Frame format, only the 11 most significant bits (3 to 13) are used for frame identification
in both receive and transmit cases. The 18 least significant bits are ignored. In Extended Frame
format, all bits are used for frame identification in both receive and transmit cases.
DATA
Data Field
As many as 8 bytes can be used for a data frame. For Rx frames, the data is stored as it is received
from the CAN bus. For Tx frames, the CPU prepares the data field to be transmitted within the frame.
Table 25-5. Message Buffer Code for Rx buffers
Rx Code
BEFORE
Rx New Frame
Description
Rx Code
AFTER
Rx New Frame
—
Comment
0000
INACTIVE: MB is not active.
MB does not participate in the matching
process.
0100
EMPTY: MB is active and
empty.
0010
MB participates in the matching process. When
a frame is received successfully, the code is
automatically updated to FULL.
0010
FULL: MB is full.
0010
The act of reading the C/S word followed by
unlocking the MB does not make the code
return to EMPTY. It remains FULL. If a new
frame is written to the MB after the C/S word
was read and the MB was unlocked, the code
still remains FULL.
0110
If the MB is FULL and a new frame is
overwritten to this MB before the CPU had time
to read it, the code is automatically updated to
OVERRUN. See Section 25.5.6, Matching
process, for details about overrun behavior.
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Chapter 25 FlexCAN
Table 25-5. Message Buffer Code for Rx buffers
Rx Code
BEFORE
Rx New Frame
0110
0XY11
1
Description
OVERRUN: a frame was
overwritten into a full buffer.
BUSY: Flexcan is updating the
contents of the MB. The CPU
must not access the MB.
Rx Code
AFTER
Rx New Frame
Comment
0010
If the code indicates OVERRUN but the CPU
reads the C/S word and then unlocks the MB,
when a new frame is written to the MB the code
returns to FULL.
0110
If the code already indicates OVERRUN, and
yet another new frame must be written, the MB
will be overwritten again, and the code will
remain OVERRUN. See Section 25.5.6,
Matching process, for details about overrun
behavior.
0010
An EMPTY buffer was written with a new frame
(XY was 01).
0110
A FULL/OVERRUN buffer was overwritten (XY
was 11).
Note that for Tx MBs (see Table 25-6), the BUSY bit should be ignored upon read, except when AEN bit is set
in the MCR register.
Table 25-6. Message Buffer Code for Tx buffers
RTR
Initial Tx
code
Code after
successful
transmission
X
1000
—
INACTIVE: MB does not participate in the arbitration process.
X
1001
—
ABORT: MB was configured as Tx and CPU aborted the
transmission. This code is only valid when AEN bit in MCR is
asserted. MB does not participate in the arbitration process.
0
1100
1000
Transmit data frame unconditionally once. After transmission, the
MB automatically returns to the INACTIVE state.
1
1100
0100
Transmit remote frame unconditionally once. After transmission,
the MB automatically becomes an Rx MB with the same ID.
0
1010
1010
Transmit a data frame whenever a remote request frame with the
same ID is received. This MB participates simultaneously in both
the matching and arbitration processes. The matching process
compares the ID of the incoming remote request frame with the ID
of the MB. If a match occurs this MB is allowed to participate in the
current arbitration process and the Code field is automatically
updated to 1110 to allow the MB to participate in future arbitration
runs. When the frame is eventually transmitted successfully, the
Code automatically returns to 1010 to restart the process again.
0
1110
1010
This is an intermediate code that is automatically written to the MB
by the MBM as a result of match to a remote request frame. The
data frame will be transmitted unconditionally once and then the
code will automatically return to 1010. The CPU can also write this
code with the same effect.
Description
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Chapter 25 FlexCAN
25.4.3
Rx FIFO structure
When the FEN bit is set in the MCR, the memory area from 0x80 to 0xFC (which is normally occupied by
MBs 0 to 7) is used by the reception FIFO engine. Figure 25-3 shows the Rx FIFO data structure. The
region 0x80–0x8C contains an MB structure, which is the port through which the CPU reads data from the
FIFO (the oldest frame received and not read yet). The region 0x90–0xDC is reserved for internal use of
the FIFO engine. The region 0xE0–0xFC contains an 8-entry ID table that specifies filtering criteria for
accepting frames into the FIFO. Figure 25-4 shows the three different formats that the elements of the ID
table can assume, depending on the IDAM field of the MCR. Note that all elements of the table must have
the same format. See Section 25.5.8, Rx FIFO, for more information.
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0x80
0x84
RTR
2
IDE
1
SRR
0
LENGTH
TIME STAMP
ID (Standard/Extended)
ID (Extended)
0x88
Data Byte 0
Data Byte 1
Data Byte 2
Data Byte 3
0x8C
Data Byte 4
Data Byte 5
Data Byte 6
Data Byte 7
0x90
to
Reserved
0xDC
0xE0
ID Table 0
0xE4
ID Table 1
0xE8
ID Table 2
0xEC
ID Table 3
0xF0
ID Table 4
0xF4
ID Table 5
0xF8
ID Table 6
0xFC
ID Table 7
= Unimplemented or Reserved
Figure 25-3. Rx FIFO structure
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Chapter 25 FlexCAN
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RXIDC_0
(Std/Ext = 0–7)
C
RXIDC_1
(Std/Ext = 8–15)
EXT
RXIDB_0
(Standard = 2–12, Extended = 2–15)
REM
RXIDA
(Standard = 2–12, Extended = 2–30)
EXT
REM
B
1
EXT
A
REM
0
RXIDB_1
(Standard = 18–28, Extended = 18–31)
RXIDC_2
(Std/Ext = 16–23)
RXIDC_3
(Std/Ext = 24–31)
= Unimplemented or Reserved
Figure 25-4. ID Table 0–7
Table 25-7. Rx FIFO Structure field description
Field
Description
REM
Remote Frame
This bit specifies if Remote Frames are accepted into the FIFO if they match the target ID.
0 Remote Frames are rejected and data frames can be accepted
1 Remote Frames can be accepted and data frames are rejected
EXT
Extended Frame
Specifies whether extended or standard frames are accepted into the FIFO if they match the target ID.
0 Extended frames are rejected and standard frames can be accepted
1 Extended frames can be accepted and standard frames are rejected
RXIDA
Rx Frame Identifier (Format A)
Specifies an ID to be used as acceptance criteria for the FIFO. In the standard frame format, only the
11 most significant bits (3 to 13) are used for frame identification. In the extended frame format, all bits
are used.
RXIDB_0,
RXIDB_1
Rx Frame Identifier (Format B)
Specifies an ID to be used as acceptance criteria for the FIFO. In the standard frame format, the 11
most significant bits (a full standard ID) (3 to 13) are used for frame identification. In the extended frame
format, all 14 bits of the field are compared to the 14 most significant bits of the received ID.
RXIDC_0, Rx Frame Identifier (Format C)
RXIDC_1, Specifies an ID to be used as acceptance criteria for the FIFO. In both standard and extended frame
RXIDC_2, formats, all 8 bits of the field are compared to the 8 most significant bits of the received ID.
RXIDC_3
25.4.4
Register descriptions
The FlexCAN registers are described in this section in ascending address order.
25.4.4.1
Module Configuration Register (MCR)
This register defines global system configurations, such as the module operation mode (e.g., low power)
and maximum message buffer configuration. This register can be accessed at any time, however some
fields must be changed only during Freeze Mode. Find more information in the fields descriptions ahead.
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Chapter 25 FlexCAN
1
0
0
16
17
18
19
20
21
22
0
0
0
0
AEN
0
0
MDIS
W
RESET:
0
0
10
11
12
13
0
0
29
30
31
1
1
0
0
1
0
0
0
23
24
25
26
27
28
0
0
IDAM
0
0
0
14
15
BCC
1
9
LPM_ACK
0
8
Note2
1
SOFT_RST
1
FRZ FEN HALT
W
R
7
0
R
RESET:
6
WRN_EN
5
SUPV
4
FRZ_ACK
3
Note1
2
NOT_RDY
1
LPRIO_EN
0
Access: Supervisor read/write
SRX_DIS
Offset: 0x0000
0
0
MAXMB
0
0
0
0
0
1
1
Figure 25-5. Module Configuration Register (MCR)
1
2
Different on various platforms, but it is always the opposite of the MDIS reset value.
Different on various platforms, but it is always the same as the MDIS reset value.
Table 25-8. MCR field descriptions
Field
Description
MDIS
Module Disable
This bit controls whether FlexCAN is enabled or not. When disabled, FlexCAN shuts down the
clocks to the CAN Protocol Interface and Message Buffer Management submodules. This is the only
bit in MCR not affected by soft reset. See Section 25.5.10.2, Module Disable mode, for more
information.
0 Enable the FlexCAN module
1 Disable the FlexCAN module
FRZ
Freeze Enable
The FRZ bit specifies the FlexCAN behavior when the HALT bit in MCR is set or when Debug Mode
is requested at MCU level. When FRZ is asserted, FlexCAN is enabled to enter Freeze Mode.
Negation of this bit field causes FlexCAN to exit from Freeze Mode.
0 Not enabled to enter Freeze Mode
1 Enabled to enter Freeze Mode
FEN
FIFO Enable
This bit controls whether the FIFO feature is enabled or not. When FEN is set, MBs 0 to 7 cannot
be used for normal reception and transmission because the corresponding memory region
(0x80–0xFF) is used by the FIFO engine. See Section 25.4.3, Rx FIFO structure, and
Section 25.5.8, Rx FIFO, for more information. This bit must be written in Freeze mode only.
0 FIFO not enabled
1 FIFO enabled
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Table 25-8. MCR field descriptions (continued)
Field
Description
HALT
Halt FlexCAN
Assertion of this bit puts the FlexCAN module into Freeze Mode. The CPU should clear it after
initializing the Message Buffers and CTRL. No reception or transmission is performed by FlexCAN
before this bit is cleared. While in Freeze Mode, the CPU has write access to ECR, which is
otherwise read-only. Freeze Mode cannot be entered while FlexCAN is in any of the low power
modes. See Section 25.5.10.1, Freeze mode, for more information.
0 No Freeze Mode request.
1 Enters Freeze Mode if the FRZ bit is asserted.
NOT_RDY
FlexCAN Not Ready
This read-only bit indicates that FlexCAN is in Disable Mode or Freeze Mode. It is negated once
FlexCAN has exited these modes.
0 FlexCAN module is in Normal Mode, Listen-Only Mode or Loop-Back Mode
1 FlexCAN module is in Disable Mode or Freeze Mode
SOFT_RST
Soft Reset
When this bit is asserted, FlexCAN resets its internal state machines and some of the memory
mapped registers. The following registers are reset: MCR (except the MDIS bit), TIMER, ECR, ESR,
IMASK1, IMASK2, IFLAG1, IFLAG2. Configuration registers that control the interface to the CAN
bus are not affected by soft reset. The following registers are unaffected:
CTRL
RXIMR0–RXIMR63
RXGMASK, RX14MASK, RX15MASK
all Message Buffers
The SOFT_RST bit can be asserted directly by the CPU when it writes to MCR, but it is also
asserted when global soft reset is requested at MCU level. Since soft reset is synchronous and has
to follow a request/acknowledge procedure across clock domains, it may take some time to fully
propagate its effect. The SOFT_RST bit remains asserted while reset is pending, and is
automatically negated when reset completes. Therefore, software can poll this bit to know when the
soft reset has completed.
Soft reset cannot be applied while clocks are shut down in any of the low power modes. The module
should be first removed from low power mode, and then soft reset can be applied.
0 No reset request
1 Resets the registers marked as affected by soft reset in Table 25-2
FRZ_ACK
Freeze Mode Acknowledge
This read-only bit indicates that FlexCAN is in Freeze Mode and its prescaler is stopped. The Freeze
Mode request cannot be granted until current transmission or reception processes have finished.
Therefore the software can poll the FRZ_ACK bit to know when FlexCAN has actually entered
Freeze Mode. If Freeze Mode request is negated, then this bit is negated once the FlexCAN
prescaler is running again. If Freeze Mode is requested while FlexCAN is in any of the low power
modes, then the FRZ_ACK bit will only be set when the low power mode is exited. See
Section 25.5.10.1, Freeze mode, for more information.
0 FlexCAN not in Freeze Mode, prescaler running
1 FlexCAN in Freeze Mode, prescaler stopped
SUPV
Supervisor Mode
This bit configures some of the FlexCAN registers to be either in Supervisor or Unrestricted memory
space. The registers affected by this bit are marked as S/U in the Access Type column of Table 25-2.
Reset value of this bit is 1, so the affected registers start with Supervisor access restrictions. This
bit should be written in Freeze mode only.
0 Affected registers are in Unrestricted memory space
1 Affected registers are in Supervisor memory space. Any access without supervisor permission
behaves as though the access was done to an unimplemented register location
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Chapter 25 FlexCAN
Table 25-8. MCR field descriptions (continued)
Field
Description
WRN_EN
Warning Interrupt Enable
When asserted, this bit enables the generation of the TWRN_INT and RWRN_INT flags in the Error
and Status Register (ESR). If WRN_EN is negated, the TWRN_INT and RWRN_INT flags will
always be zero, independent of the values of the error counters, and no warning interrupt will ever
be generated. This bit must be written in Freeze mode only.
0 TWRN_INT and RWRN_INT bits are zero, independent of the values in the error counters.
1 TWRN_INT and RWRN_INT bits are set when the respective error counter transition
from < 96 to  96.
LPM_ACK
Low Power Mode Acknowledge
This read-only bit indicates that FlexCAN is in Disable Mode. This mode cannot be entered until all
current transmission or reception processes have finished, so the CPU can poll the LPM_ACK bit
to know when FlexCAN has actually entered low power mode. See Section 25.5.10.2, Module
Disable mode, for more information.
0 FlexCAN not in any low-power mode
1 FlexCAN is in Disable Mode
SRX_DIS
Self Reception Disable
This bit defines whether FlexCAN is allowed to receive frames transmitted by itself. If this bit is
asserted, frames transmitted by the module will not be stored in any MB, regardless if the MB is
programmed with an ID that matches the transmitted frame, and no interrupt flag or interrupt signal
will be generated due to the frame reception. This bit must be written in Freeze mode only.
0 Self reception enabled
1 Self reception disabled
BCC
Backwards Compatibility Configuration
This bit is provided to support Backwards Compatibility with previous FlexCAN versions.
On this device, FlexCAN supports individual Rx ID masking using RXIMR0–63. Setting this bit
enables individual Rx ID masking.
When this bit is cleared. FlexCAN uses a backwards compatible masking scheme with RXGMASK,
RX14MASK, and RX15MASK; and the reception queue feature is disabled. Upon receiving a
message, if the first MB with a matching ID that is found is still occupied by a previous unread
message, FlexCAN will not look for another matching MB. It will override this MB with the new
message and set the CODE field to ‘0110’ (overrun).
This bit is cleared on reset, allowing legacy software to work without modification. This bit must be
written in Freeze mode only.
0 Individual Rx masking and queue feature are disabled.
1 Individual Rx masking and queue feature are enabled.
LPRIO_EN
Local Priority Enable
This bit is provided for backwards compatibility reasons. It controls whether the local priority feature
is enabled or not. It is used to extend the ID used during the arbitration process. With this extended
ID concept, the arbitration process is done based on the full 32-bit word, but the actual transmitted
ID still has 11-bit for standard frames and 29-bit for extended frames. This bit must be written in
Freeze mode only.
0 Local Priority disabled
1 Local Priority enabled
AEN
Abort Enable
This bit is supplied for backwards compatibility reasons. When asserted, it enables the Tx abort
feature. This feature guarantees a safe procedure for aborting a pending transmission, so that no
frame is sent in the CAN bus without notification. This bit must be written in Freeze mode only.
0 Abort disabled
1 Abort enabled
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Table 25-8. MCR field descriptions (continued)
Field
Description
IDAM
ID Acceptance Mode
This 2-bit field identifies the format of the elements of the Rx FIFO filter table, as shown in
Table 25-9. Note that all elements of the table are configured at the same time by this field (they are
all the same format). See Section 25.4.3, Rx FIFO structure. This bit must be written in Freeze
mode only.
MAXMB
Maximum Number of Message Buffers
This 6-bit field defines the maximum number of message buffers that will take part in the matching
and arbitration processes. The reset value (0x0F) is equivalent to 16 MB configuration. This field
must be changed only while the module is in Freeze Mode.
Maximum MBs in use = MAXMB + 1.
Note: MAXMB must be programmed with a value smaller or equal to the number of available
Message Buffers, otherwise FlexCAN can transmit and receive wrong messages.
Table 25-9. IDAM coding
25.4.4.2
IDAM
Format
Explanation
0b00
A
One full ID (standard or extended) per filter element.
0b01
B
Two full standard IDs or two partial 14-bit extended IDs per filter element.
0b10
C
Four partial 8-bit IDs (standard or extended) per filter element.
0b11
D
All frames rejected.
Control (CTRL) register
This register is defined for specific FlexCAN control features related to the CAN bus, such as bit rate,
programmable sampling point within an Rx bit, Loop Back Mode, Listen Only Mode, Bus Off recovery
behavior, and interrupt enabling (Bus-Off, Error, Warning). It also determines the Division Factor for the
clock prescaler. Most of the fields in this register should only be changed while the module is in Disable
Mode or in Freeze Mode. Exceptions are the BOFF_MSK, ERR_MSK, TWRN_MSK, RWRN_MSK, and
BOFF_REC bits, which can be accessed at any time.
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Offset: 0x0004
0
Access: Read/write
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
PRESDIV
RJW
PSEG1
PSEG2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
TWRN_MSK
RWRN_MSK
0
0
SMP
BOFF_REC
TSYN
W
0
0
0
0
0
0
W
BOFF_MSK
ERR_ MSK
CLK_SRC
RESET:
LPB
RESET:
0
0
0
0
R
0
LBUF LOM
0
0
PROPSEG
0
0
0
Figure 25-6. Control (CTRL) register
Table 25-10. CTRL field descriptions
Field
Description
PRESDIV
Prescaler Division Factor
This 8-bit field defines the ratio between the CPI clock frequency and the Serial Clock (Sclock)
frequency. The Sclock period defines the time quantum of the CAN protocol. For the reset value, the
Sclock frequency is equal to the CPI clock frequency. The Maximum value of this register is 0xFF, that
gives a minimum Sclock frequency equal to the CPI clock frequency divided by 256. For more
information refer to Section 25.5.9.4, Protocol timing. This bit must be written in Freeze mode only.
Sclock frequency = CPI clock frequency / (PRESDIV + 1)
RJW
Resync Jump Width
This 2-bit field defines the maximum number of time quanta1 that a bit time can be changed by one
resynchronization. The valid programmable values are 0–3. This bit must be written in Freeze mode
only.
Resync Jump Width = RJW + 1.
PSEG1
Phase Segment 1
This 3-bit field defines the length of Phase Buffer Segment 1 in the bit time. The valid programmable
values are 0–7. This bit must be written in Freeze mode only.
Phase Buffer Segment 1 = (PSEG1 + 1) × Time Quanta.
PSEG2
Phase Segment 2
This 3-bit field defines the length of Phase Buffer Segment 2 in the bit time. The valid programmable
values are 1–7. This bit must be written in Freeze mode only.
Phase Buffer Segment 2 = (PSEG2 + 1) × Time Quanta.
BOFF_MSK Bus Off Mask
This bit provides a mask for the Bus Off Interrupt.
0 Bus Off interrupt disabled
1 Bus Off interrupt enabled
ERR_MSK
Error Mask
This bit provides a mask for the Error Interrupt.
0 Error interrupt disabled
1 Error interrupt enabled
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Table 25-10. CTRL field descriptions (continued)
Field
Description
CLK_SRC
CAN Engine Clock Source
This bit selects the clock source to the CAN Protocol Interface (CPI) to be either the peripheral clock
(driven by the PLL) or the crystal oscillator clock. The selected clock is the one fed to the prescaler to
generate the Serial Clock (Sclock). In order to guarantee reliable operation, this bit must only be
changed while the module is in Disable Mode. See Section 25.5.9.4, Protocol timing, for more
information.
0 The CAN engine clock source is the oscillator clock
1 The CAN engine clock source is the bus clock
TWRN_MSK Tx Warning Interrupt Mask
This bit provides a mask for the Tx Warning Interrupt associated with the TWRN_INT flag in ESR.
This bit has no effect if the WRN_EN bit in MCR is negated and it is read as zero when WRN_EN is
negated.
0 Tx Warning Interrupt disabled
1 Tx Warning Interrupt enabled
RWRN_MSK Rx Warning Interrupt Mask
This bit provides a mask for the Rx Warning Interrupt associated with the RWRN_INT flag in ESR.
This bit has no effect if the WRN_EN bit in MCR is negated and it is read as zero when WRN_EN is
negated.
0 Rx Warning Interrupt disabled
1 Rx Warning Interrupt enabled
LPB
Loop Back
This bit configures FlexCAN to operate in Loop-Back Mode. In this mode, FlexCAN performs an
internal loop back that can be used for self test operation. The bit stream output of the transmitter is
fed back internally to the receiver input. The Rx CAN input pin is ignored and the Tx CAN output goes
to the recessive state (logic 1). FlexCAN behaves as it normally does when transmitting, and treats
its own transmitted message as a message received from a remote node. In this mode, FlexCAN
ignores the bit sent during the ACK slot in the CAN frame acknowledge field, generating an internal
acknowledge bit to ensure proper reception of its own message. Both transmit and receive interrupts
are generated. This bit must be written in Freeze mode only.
0 Loop Back disabled
1 Loop Back enabled
SMP
Sampling Mode
This bit defines the sampling mode of CAN bits at the Rx input. This bit must be written in Freeze
mode only.
0 Just one sample is used to determine the bit value
1 Three samples are used to determine the value of the received bit: the regular one (sample point)
and two preceding samples, a majority rule is used
BOFF_REC Bus Off Recovery Mode
This bit defines how FlexCAN recovers from Bus Off state. If this bit is negated, automatic recovering
from Bus Off state occurs according to the CAN Specification 2.0B. If the bit is asserted, automatic
recovering from Bus Off is disabled and the module remains in Bus Off state until the bit is negated
by the user. If the negation occurs before 128 sequences of 11 recessive bits are detected on the CAN
bus, then Bus Off recovery happens as if the BOFF_REC bit had never been asserted. If the negation
occurs after 128 sequences of 11 recessive bits occurred, then FlexCAN will resynchronize to the bus
by waiting for 11 recessive bits before joining the bus. After negation, the BOFF_REC bit can be
reasserted again during Bus Off, but it will only be effective the next time the module enters Bus Off.
If BOFF_REC was negated when the module entered Bus Off, asserting it during Bus Off will not be
effective for the current Bus Off recovery.
0 Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B
1 Automatic recovering from Bus Off state disabled
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Chapter 25 FlexCAN
Table 25-10. CTRL field descriptions (continued)
1
Field
Description
TSYN
Timer Sync Mode
This bit enables a mechanism that resets the free-running timer each time a message is received in
Message Buffer 0. This feature provides means to synchronize multiple FlexCAN stations with a
special SYNC message (i.e., global network time). If the FEN bit in MCR is set (FIFO enabled), MB8
is used for timer synchronization instead of MB0. This bit must be written in Freeze mode only.
0 Timer Sync feature disabled
1 Timer Sync feature enabled
LBUF
Lowest Buffer Transmitted First
This bit defines the ordering mechanism for Message Buffer transmission. When asserted, the
LPRIO_EN bit does not affect the priority arbitration. This bit must be written in Freeze mode only.
0 Buffer with highest priority is transmitted first
1 Lowest number buffer is transmitted first
LOM
Listen-Only Mode
This bit configures FlexCAN to operate in Listen Only Mode. In this mode, transmission is disabled,
all error counters are frozen and the module operates in a CAN Error Passive mode [Ref. 1]. Only
messages acknowledged by another CAN station will be received. If FlexCAN detects a message that
has not been acknowledged, it will flag a BIT0 error (without changing the REC), as if it was trying to
acknowledge the message. This bit must be written in Freeze mode only.
0 Listen Only Mode is deactivated
1 FlexCAN module operates in Listen Only Mode
PROPSEG
Propagation Segment
This 3-bit field defines the length of the Propagation Segment in the bit time. The valid programmable
values are 0–7. This bit must be written in Freeze mode only.
Propagation Segment Time = (PROPSEG + 1) × Time Quanta.
Time Quantum = one Sclock period.
One time quantum is equal to the Sclock period.
25.4.4.3
Free Running Timer (TIMER) register
This register represents a 16-bit free running counter that can be read and written by the CPU.
The timer is clocked by the FlexCAN bit clock (which defines the baud rate on the CAN bus). During a
message transmission/reception, it increments by one for each bit that is received or transmitted. When
there is no message on the bus, it counts using the previously programmed baud rate. During Freeze Mode,
the timer is not incremented.
The timer value is captured at the beginning of the identifier field of any frame on the CAN bus. This
captured value is written into the Time Stamp entry in a message buffer after a successful reception or
transmission of a message.
Writing to the timer is an indirect operation. The data is first written to an auxiliary register and then an
internal request/acknowledge procedure across clock domains is executed. All this is transparent to the
user, except for the fact that the data will take some time to be actually written to the register. If desired,
software can poll the register to discover when the data was actually written.
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Offset: 0x0008
R
Access: Read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
W
RESET:
R
TIMER
W
RESET:
0
0
0
0
0
0
0
0
0
Figure 25-7. Free Running Timer (TIMER) register
Table 25-11. TIMER field descriptions
Field
Description
TIMER
Free-running timer counter. The timer starts from 0x0000 after reset, counts linearly to 0xFFFF, and
wraps around.
25.4.4.4
Rx Global Mask (RXGMASK) register
This register is provided for legacy support and for MCUs that do not have the individual masking per
Message Buffer feature. Setting the BCC bit in MCR causes the RXGMASK register to have no effect on
the module operation.
RXGMASK is used as acceptance mask for all Rx MBs, excluding MBs 14–15, which have individual
mask registers. When the FEN bit in MCR is set (FIFO enabled), the RXGMASK also applies to all
elements of the ID filter table, except elements 6–7, which have individual masks.
See Section 25.5.8, Rx FIFO, for important details on usage of RXGMASK on filtering process for Rx
FIFO.
The contents of this register must be programmed while the module is in Freeze Mode, and must not be
modified when the module is transmitting or receiving frames.
During CAN messages reception by FlexCAN, the RXGMASK (Rx Global Mask) is used as acceptance
mask for most of the Rx Message Buffers (MB). When the FIFO Enable bit in the FlexCAN Module
Configuration Register (CANx_MCR[FEN], bit 2) is set, the RXGMASK also applies to most of the
elements of the ID filter table. However, there is a misalignment between the position of the ID field in the
Rx MB and in RXIDA, RXIDB, and RXIDC fields of the ID Tables. In fact, the RXIDA filter in the ID
Tables is shifted one bit to the left from Rx MBs ID position as shown below:
• Rx MB ID = bits 3–31 of ID word corresponding to message ID bits 0–28
• RXIDA = bits 2–30 of ID Table corresponding to message ID bits 0–28
The mask bits one-to-one correspondence occurs with the filters bits, not with the incoming message ID
bits. This leads the RXGMASK to affect Rx MB and Rx FIFO filtering in different ways.
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Chapter 25 FlexCAN
For example, if the user intends to mask out the bit 24 of the ID filter of Message Buffers then the
RXGMASK will be configured as 0xffff_ffef. As result, bit 24 of the ID field of the incoming message
will be ignored during filtering process for Message Buffers. This very same configuration of RXGMASK
would lead bit 24 of RXIDA to be “don’t care” and thus bit 25 of the ID field of the incoming message
would be ignored during filtering process for Rx FIFO.
Similarly, both RXIDB and RXIDC filters have multiple misalignments with regards to position of ID field
in Rx MBs, which can lead to erroneous masking during filtering process for either Rx FIFO or MBs.
RX14MASK (Rx 14 Mask) and RX15MASK (Rx 15 Mask) have the same structure as the RXGMASK.
This includes the misalignment problem between the position of the ID field in the Rx MBs, and in
RXIDA, RXIDB, and RXIDC fields of the ID Tables.
Therefore it is recommended that one of the following actions be taken to avoid problems:
• Do not enable the RxFIFO. If CANx_MCR[FEN]=0 then the Rx FIFO is disabled and thus the
masks RXGMASK, RX14MASK, and RX15MASK do not affect it.
• Enable Rx Individual Mask Registers. If the Backwards Compatibility Configuration bit in the
FlexCAN Module Configuration Register (CANx_MCR[BCC], bit 15) is set then the Rx
Individual Mask Registers (RXIMR0–63) are enabled, and thus the masks RXGMASK,
RX14MASK, and RX15MASK are not used.
• Do not use masks RXGMASK, RX14MASK, and RX15MASK (that is, leave them at their reset
value, which is 0xFFFF_FFFF) when CANx_MCR[FEN]=1 and CANx_MCR[BCC]=0. In this
case, filtering processes for both Rx MBs and Rx FIFO are not affected by those masks.
• Do not configure any MB as Rx (i.e., let all MBs as either Tx or inactive) when
CANx_MCR[FEN]=1 and CANx_MCR[BCC]=0. In this case, the masks RXGMASK,
RX14MASK, and RX15MASK can be used to affect ID Tables without affecting filtering process
for Rx MBs.
Offset: 0x0010
0
Access: Read/write
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
MI31 MI30 MI29 MI28 MI27 MI26 MI25 MI24 MI23 MI22 MI21 MI20 MI19 MI18 MI17 MI16
W
RESET:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
MI8
MI7
MI6
MI5
MI4
MI3
MI2
MI1
MI0
1
1
1
1
1
1
1
1
1
R
MI15 MI14 MI13 MI12 MI11 MI10 MI9
W
RESET:
1
1
1
1
1
1
1
Figure 25-8. Rx Global Mask (RXGMASK) register
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Table 25-12. RXGMASK field descriptions
25.4.4.5
Field
Description
MIn
Mask Bits
For normal Rx MBs, the mask bits affect the ID filter programmed on the MB. For the Rx FIFO,
the mask bits affect all bits programmed in the filter table (ID, IDE, RTR).
0 The corresponding bit in the filter is “don’t care”
1 The corresponding bit in the filter is checked against the one received
Rx 14 Mask (RX14MASK) register
This register is provided for legacy support and for MCUs that do not have the individual masking per
Message Buffer feature. Setting the BCC bit in MCR causes the RX14MASK register to have no effect on
the module operation.
RX14MASK is used as acceptance mask for the Identifier in Message Buffer 14. When the FEN bit in
MCR is set (FIFO enabled), the RXG14MASK also applies to element 6 of the ID filter table. This register
has the same structure as the Rx Global Mask register.
See Section 25.5.8, Rx FIFO, for important details on usage of RX14MASK on filtering process for Rx
FIFO.
The contents of this register must be programmed while the module is in Freeze Mode, and must not be
modified when the module is transmitting or receiving frames.
• Address offset: 0x14
• Reset value: 0xFFFF_FFFF
25.4.4.6
Rx 15 Mask (RX15MASK) register
This register is provided for legacy support and for MCUs that do not have the individual masking per
Message Buffer feature. Setting the BCC bit in MCR causes the RX15MASK register to have no effect on
the module operation.
When the BCC bit is negated, RX15MASK is used as acceptance mask for the Identifier in Message Buffer
15. When the FEN bit in MCR is set (FIFO enabled), the RXG15MASK also applies to element 7 of the
ID filter table. This register has the same structure as the Rx Global Mask register.
Refer to Section 25.5.8, Rx FIFO, for important details on usage of RX15MASK on filtering process for
Rx FIFO.
The contents of this register must be programmed while the module is in Freeze Mode, and must not be
modified when the module is transmitting or receiving frames.
• Address offset: 0x18
• Reset value: 0xFFFF_FFFF
25.4.4.7
Error Counter Register (ECR)
This register has two 8-bit fields reflecting the value of two FlexCAN error counters: Transmit Error
Counter (TX_ERR_COUNTER field) and Receive Error Counter (RX_ERR_COUNTER field). The rules
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Chapter 25 FlexCAN
for increasing and decreasing these counters are described in the CAN protocol and are completely
implemented in the FlexCAN module. Both counters are read only except in Freeze Mode, where they can
be written by the CPU.
Writing to the Error Counter Register while in Freeze Mode is an indirect operation. The data is first
written to an auxiliary register and then an internal request/acknowledge procedure across clock domains
is executed. All this is transparent to the user, except for the fact that the data will take some time to be
actually written to the register. If desired, software can poll the register to discover when the data was
actually written.
FlexCAN responds to any bus state as described in the protocol, e.g., transmit Error Active or Error Passive
flag, delay its transmission start time (Error Passive) and avoid any influence on the bus when in Bus Off
state. The following are the basic rules for FlexCAN bus state transitions.
• If the value of TX_ERR_COUNTER or RX_ERR_COUNTER increases to be greater than or
equal to 128, the FLT_CONF field in the Error and Status Register is updated to reflect Error
Passive state.
• If the FlexCAN state is Error Passive, and either TX_ERR_COUNTER or RX_ERR_COUNTER
decrements to a value less than or equal to 127 while the other already satisfies this condition, the
FLT_CONF field in the Error and Status Register is updated to reflect Error Active state.
• If the value of TX_ERR_COUNTER increases to be greater than 255, the FLT_CONF field in the
Error and Status Register is updated to reflect Bus Off state, and an interrupt may be issued. The
value of TX_ERR_COUNTER is then reset to zero.
• If the FlexCAN is in Bus Off state, then Tx_Err_Counter is cascaded together with another internal
counter to count the 128th occurrences of 11 consecutive recessive bits on the bus. Hence,
TX_ERR_COUNTER is reset to 0 and counts in a manner where the internal counter counts 11
such bits and then wraps around while incrementing the TX_ERR_COUNTER. When
TX_ERR_COUNTER reaches the value of 128, the FLT_CONF field in the Error and Status
Register is updated to be Error Active and both error counters are reset to 0. At any instance of
dominant bit following a stream of less than 11 consecutive recessive bits, the internal counter
resets itself to 0 without affecting the TX_ERR_COUNTER value.
• If during system start-up, only one node is operating, then its TX_ERR_COUNTER increases in
each message it is trying to transmit, as a result of acknowledge errors (indicated by the ACK_ERR
bit in the Error and Status Register). After the transition to Error Passive state, the
TX_ERR_COUNTER does not increment anymore by acknowledge errors. Therefore the device
never goes to the Bus Off state.
• If the RX_ERR_COUNTER increases to a value greater than 127, it is not incremented further,
even if more errors are detected while being a receiver. At the next successful message reception,
the counter is set to a value between 119 and 127 to resume to Error Active state.
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Offset: 0x001C
R
Access: Read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
W
RESET:
R
RX_ERR_COUNTER
TX_ERR_COUNTER
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 25-9. Error Counter Register (ECR)
Table 25-13. ECR field descriptions
Field
Description
RX_ERROR_
COUNTER
Receive Error Counter. See the text of this section for a detailed description of this field and
how it interacts with TX_ERROR_COUNTER.
TX_ERROR_
COUNTER
Transmit Error Counter. See the text of this section for a detailed description of this field and
how it interacts with RX_ERROR_COUNTER.
25.4.4.8
Error and Status Register (ESR)
This register reflects various error conditions, some general status of the device and it is the source of four
interrupts to the CPU. The reported error conditions (bits 16–21) are those that occurred since the last time
the CPU read this register. The CPU read action clears bits 16–23. Bits 22–28 are status bits.
Most bits in this register are read-only, except TWRN_INT, RWRN_INT, BOFF_INT, and ERR_INT,
which are interrupt flags that can be cleared by writing 1 to them (writing 0 has no effect). See
Section 25.5.11, Interrupts, for more details.
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
569
Chapter 25 FlexCAN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TWRN_INT
RWRN_INT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
BIT0_ ERR
ACK_ ERR
CRC_ERR
FRM_ERR
STF_ERR
TX_WRN
RX_WRN
IDLE
TXRX
BOFF_INT
ERR_ INT
Access: Read/write
BIT1_ ERR
Offset: 0x0020
0
0
0
0
0
0
0
0
0
0
0
0
R
W
RESET:
R
FLT_CONF
0
W
RESET:
0
0
0
0
0
Figure 25-10. Error and Status Register (ESR)
Table 25-14. ESR field descriptions
Field
Description
TWRN_INT
TWRN_INT — Tx Warning Interrupt Flag
If the WRN_EN bit in MCR is asserted, the TWRN_INT bit is set when the TX_WRN flag transition
from 0 to 1, meaning that the Tx error counter reached 96. If the corresponding mask bit in the
Control Register (TWRN_MSK) is set, an interrupt is generated to the CPU. This bit is cleared by
writing it to 1. Writing 0 has no effect.
0 No such occurrence
1 The Tx error counter transition from < 96 to  96
RWRN_INT
RWRN_INT — Rx Warning Interrupt Flag
If the WRN_EN bit in MCR is asserted, the RWRN_INT bit is set when the RX_WRN flag transition
from 0 to 1, meaning that the Rx error counters reached 96. If the corresponding mask bit in the
Control Register (RWRN_MSK) is set, an interrupt is generated to the CPU. This bit is cleared by
writing i