MCF51MM256 - Reference Manual

MCF51MM256 Reference Manual
An Energy-Efficient Solution from Freescale
Devices Supported:
MCF51MM256
MCF51MM128
Document Number:
MCF51MM256RM
Rev. 3
Freescale Semiconductor
i
MCF51MM256 Series Devices Reference Manual, Rev. 3
ii
Freescale Semiconductor
Contents
Chapter 1
Device Overview
1.1
1.2
1.3
1.4
The MCF51MM256 Series Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1.1 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1.2 Devices in the MCF51MM256 series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
MCF51MM256/128 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2.1 Functional Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.2.2 Functional Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
V1 ColdFire Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.3.1 User Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.3.2 Supervisor Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
System Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.4.1 System Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.4.2 System Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.4.3 Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.4.4 MCG Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.4.5 MCG Mode State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
Chapter 2
Pins and Connections
2.1
2.2
2.3
2.4
2.5
2.6
Device Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
104-Pin MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
100-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
81-Pin MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
80-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.6.1 Pinout Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.6.2 Recommended System Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
2.6.3 Interfacing the SCIs to Off-Chip Opto-Isolators . . . . . . . . . . . . . . . . . . . . . . . 2-23
2.6.4 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
2.6.5 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
2.6.6 PTD1/CMPP2/RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2.6.7 PTE4/CMPP3/TPMCLK/IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2.6.8 Background / Mode Select (PTD0/BKGD/MS) . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2.6.9 ADC Reference Pins (VREFH, VREFL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
2.6.10 Bootloader Mode Select (BLMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
2.6.11 USB Data Pins (USB_DP, USB_DN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
iii
2.6.12 General-Purpose I/O and Peripheral Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
Chapter 3
Modes of Operation
3.1
3.2
3.3
3.4
3.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Secure Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Bootloader Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.5.1 Entering Bootloader Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.5.2 Entering User mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.5.3 Active Background Mode and Bootloader Mode Arbitrage . . . . . . . . . . . . . . . . 3-7
3.5.4 Bootloader Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.5.4.1 Flash Block Checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.5.4.2 SIGNATURE Semaphore Register . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.5.4.3 Flash Partial Erase Semaphore . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.5.4.4 Boot Mode Entry Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.6 Run Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.6.1 Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.6.2 Low-Power Run Mode (LPrun) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.6.2.1 BDM in Low-Power Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.7 Wait Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3.7.2 Low-Power Wait Mode (LPwait) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3.7.2.1 BDM in Low-Power Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3.8 Stop Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.8.1 Stop2 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
3.8.2 Stop3 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
3.8.3 Stop4 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
3.8.3.1 LVD Enabled in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
3.9 On-Chip peripheral Modules in Stop and Low-power Modes . . . . . . . . . . . . . . . . . . . 3-14
3.10 Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
Chapter 4
Memory
4.1
4.2
4.3
MCF51MM256 Series Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1.1 Register Addresses and Bit Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.1.2 Detailed register addresses and bit assignments . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.1.3 Flash Module Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
4.1.4 ColdFire Rapid GPIO Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
4.1.5 ColdFire Interrupt Controller Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
4.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22
4.3.2 Dual Flash Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
MCF51MM256 Series Devices Reference Manual, Rev. 3
iv
Freescale Semiconductor
4.4
4.5
4.3.3 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.3.1 Flash Clock Divider Register (FxCDIV) . . . . . . . . . . . . . . . . . . . . .
4.3.3.2 Flash Options Register (FxOPT and NVxOPT) . . . . . . . . . . . . . . .
4.3.3.3 Flash Configuration Register (FxCNFG) . . . . . . . . . . . . . . . . . . . .
4.3.3.4 Flash Protection Register (FxPROT and NVxPROT) . . . . . . . . . . .
4.3.3.5 Flash Status Register (FxSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.3.6 Flash Command Register (FxCMD) . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.1 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.1.1 Writing the FCDIV Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.1.2 Command Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.2 Flash Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.2.1 Erase Verify Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.2.2 Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.2.3 Burst Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.2.4 Sector Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.2.5 Mass Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.3 Illegal Flash Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.3.1 Flash Access Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.3.2 Flash Protection Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.4 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.4.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.4.2 Stop Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.4.3 Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.5 Flash Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.6 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.6.1 Flash Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.6.2 Reset While Flash Command Active . . . . . . . . . . . . . . . . . . . . . . .
4.4.6.3 Program and Erase Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . .
4-23
4-23
4-24
4-25
4-25
4-27
4-28
4-29
4-29
4-29
4-30
4-31
4-31
4-33
4-34
4-35
4-37
4-38
4-38
4-38
4-39
4-39
4-39
4-39
4-39
4-40
4-40
4-40
4-40
4-40
4-41
Chapter 5
Resets, Interrupts, and General System Control
5.1
5.2
5.3
5.4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microcontroller Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.1 Computer Operating Properly (COP) Watchdog . . . . . . . . . . . . . . . . . . . . . . .
5.3.2 Illegal Opcode Detect (ILOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.3 Illegal Address Detect (ILAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts & Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.1 External Interrupt Request (IRQ) Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.1.1 Pin Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.1.2 Edge and Level Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.2 Interrupt Vectors, Sources, and Local Masks . . . . . . . . . . . . . . . . . . . . . . . . . .
5-1
5-1
5-1
5-2
5-3
5-3
5-3
5-4
5-5
5-5
5-5
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
v
5.5
5.6
5.7
Low-Voltage Detect (LVD) System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.5.1 Power-On Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.5.2 LVD Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.5.3 LVD Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
5.5.4 Low-Voltage Warning (LVW) Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . 5-10
Peripheral Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Reset, Interrupt, and System Control Registers and Control Bits . . . . . . . . . . . . . . . . 5-10
5.7.1 Interrupt Pin Request Status and Control Register (IRQSC) . . . . . . . . . . . . . 5-11
5.7.2 System Reset Status Register (SRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
5.7.3 System Options 1 (SOPT1) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
5.7.4 System Options 2 (SOPT2) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
5.7.5 SIM Clock Set and Select Register (SIMCO) . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
5.7.6 System Device Identification Register (SDIDH, SDIDL) . . . . . . . . . . . . . . . . . 5-16
5.7.7 System Clock Gating Control 1 Register (SCGC1) . . . . . . . . . . . . . . . . . . . . 5-17
5.7.8 System Clock Gating Control 2 Register (SCGC2) . . . . . . . . . . . . . . . . . . . . 5-18
5.7.9 System Clock Gating Control 3 Register (SCGC3) . . . . . . . . . . . . . . . . . . . . 5-18
5.7.10 System Options 3 Register (SOPT3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20
5.7.11 System Options 4 Register (SOPT4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
5.7.12 System Options 5 Register (SOPT5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22
5.7.13 SIM Internal Peripheral Select Register (SIMIPS) . . . . . . . . . . . . . . . . . . . . . 5-22
5.7.14 Signature Register (Signature) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
5.7.15 System Power Management Status and Control 1 Register (SPMSC1) . . . . 5-23
5.7.16 System Power Management Status and Control 2 Register (SPMSC2) . . . . 5-24
5.7.17 System Power Management Status and Control 3 Register (SPMSC3) . . . . 5-26
5.7.18 Flash Protection Disable Register (FPROTD) . . . . . . . . . . . . . . . . . . . . . . . . 5-27
5.7.19 Mini-FlexBus Pin Control 1 (MFBPC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27
5.7.20 Mini-FlexBus Pin Control 2 (MFBPC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28
5.7.21 Mini-FlexBus Pin Control 3 (MFBPC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29
5.7.22 Mini-FlexBus Pin Control 4 (MFBPC4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30
Chapter 6
Parallel Input/Output Control
6.1
6.2
6.3
6.4
6.5
Port Data and Data Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pull-up, Slew Rate, and Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.1 Port Internal Pull-up Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.2 Port Slew Rate Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.3 Port Drive Strength Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.4 Port Input Filter Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ColdFire V1 Rapid GPIO Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Keyboard Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.1 Edge Only Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.2 Edge and Level Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.3 Pull-up/Pull-down Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.4 Keyboard Interrupt Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Behavior in Stop Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-1
6-2
6-2
6-2
6-3
6-3
6-3
6-3
6-4
6-4
6-4
6-4
6-5
MCF51MM256 Series Devices Reference Manual, Rev. 3
vi
Freescale Semiconductor
6.6
Parallel I/O, Keyboard Interrupt, and Pin Control Registers . . . . . . . . . . . . . . . . . . . . . . 6-5
6.6.1 Port A Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.6.1.1 Port A Data Register (PTAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.6.1.2 Port A Data Direction Register (PTADD) . . . . . . . . . . . . . . . . . . . . . 6-6
6.6.1.3 Port A Pull Enable Register (PTAPE) . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6.6.1.4 Port A Slew Rate Enable Register (PTASE) . . . . . . . . . . . . . . . . . . 6-7
6.6.1.5 Port A Drive Strength Selection Register (PTADS) . . . . . . . . . . . . . 6-7
6.6.1.6 Port A Input Filter Enable Register (PTAIFE) . . . . . . . . . . . . . . . . . . 6-8
6.6.2 Port B Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
6.6.2.1 Port B Data Register (PTBD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
6.6.2.2 Port B Data Direction Register (PTBDD) . . . . . . . . . . . . . . . . . . . . . 6-9
6.6.2.3 Port B Pull Enable Register (PTBPE) . . . . . . . . . . . . . . . . . . . . . . . . 6-9
6.6.2.4 Port B Slew Rate Enable Register (PTBSE) . . . . . . . . . . . . . . . . . . 6-9
6.6.2.5 Port B Drive Strength Selection Register (PTBDS) . . . . . . . . . . . . 6-10
6.6.2.6 Port B Input Filter Enable Register (PTBIFE) . . . . . . . . . . . . . . . . . 6-10
6.6.3 Port C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
6.6.3.1 Port C Data Register (PTCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
6.6.3.2 Port C Data Direction Register (PTCDD) . . . . . . . . . . . . . . . . . . . . 6-11
6.6.3.3 Port C Pull Enable Register (PTCPE) . . . . . . . . . . . . . . . . . . . . . . 6-12
6.6.3.4 Port C Slew Rate Enable Register (PTCSE) . . . . . . . . . . . . . . . . . 6-12
6.6.3.5 Port C Drive Strength Selection Register (PTCDS) . . . . . . . . . . . . 6-12
6.6.3.6 Port C Input Filter Enable Register (PTCIFE) . . . . . . . . . . . . . . . . . 6-13
6.6.4 Port D Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
6.6.4.1 Port D Data Register (PTDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
6.6.4.2 Port D Data Direction Register (PTDDD) . . . . . . . . . . . . . . . . . . . . 6-14
6.6.4.3 Port D Pull Enable Register (PTDPE) . . . . . . . . . . . . . . . . . . . . . . 6-14
6.6.4.4 Port D Slew Rate Enable Register (PTDSE) . . . . . . . . . . . . . . . . . 6-15
6.6.4.5 Port D Drive Strength Selection Register (PTDDS) . . . . . . . . . . . . 6-15
6.6.4.6 Port D Input Filter Enable Register (PTDIFE) . . . . . . . . . . . . . . . . . 6-15
6.6.5 Port E Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
6.6.5.1 Port E Data Register (PTED) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
6.6.5.2 Port E Data Direction Register (PTEDD) . . . . . . . . . . . . . . . . . . . . 6-16
6.6.5.3 Port E Pull Enable Register (PTEPE) . . . . . . . . . . . . . . . . . . . . . . . 6-17
6.6.5.4 Port E Slew Rate Enable Register (PTESE) . . . . . . . . . . . . . . . . . 6-17
6.6.5.5 Port E Drive Strength Selection Register (PTEDS) . . . . . . . . . . . . 6-18
6.6.5.6 Port E Input Filter Enable Register (PTEIFE) . . . . . . . . . . . . . . . . . 6-18
6.6.6 Port F Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
6.6.6.1 Port F Data Register (PTFD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
6.6.6.2 Port F Data Direction Register (PTFDD) . . . . . . . . . . . . . . . . . . . . 6-19
6.6.6.3 Port F Pull Enable Register (PTFPE) . . . . . . . . . . . . . . . . . . . . . . . 6-20
6.6.6.4 Port F Slew Rate Enable Register (PTFSE) . . . . . . . . . . . . . . . . . . 6-20
6.6.6.5 Port F Drive Strength Selection Register (PTFDS) . . . . . . . . . . . . 6-20
6.6.6.6 Port F Input Filter Enable Register (PTFIFE) . . . . . . . . . . . . . . . . . 6-21
6.6.7 Port G Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
6.6.7.1 Port G Data Register (PTGD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
vii
6.6.7.2 Port G Data Direction Register (PTGDD) . . . . . . . . . . . . . . . . . . . .
6.6.7.3 Port G Pull Enable Register (PTGPE) . . . . . . . . . . . . . . . . . . . . . .
6.6.7.4 Port G Slew Rate Enable Register (PTGSE) . . . . . . . . . . . . . . . . .
6.6.7.5 Port G Drive Strength Selection Register (PTGDS) . . . . . . . . . . . .
6.6.7.6 Port G Input Filter Enable Register (PTGIFE) . . . . . . . . . . . . . . . .
6.6.8 Port H Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6.8.1 Port H Data Register (PTHD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6.8.2 Port H Data Direction Register (PTHDD) . . . . . . . . . . . . . . . . . . . .
6.6.8.3 Port H Pull Enable Register (PTHPE) . . . . . . . . . . . . . . . . . . . . . .
6.6.8.4 Port H Slew Rate Enable Register (PTHSE) . . . . . . . . . . . . . . . . .
6.6.8.5 Port H Drive Strength Selection Register (PTHDS) . . . . . . . . . . . .
6.6.8.6 Port H Input Filter Enable Register (PTHIFE) . . . . . . . . . . . . . . . . .
6.6.9 Port J Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6.9.1 Port J Data Register (PTJD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6.9.2 Port J Data Direction Register (PTJDD) . . . . . . . . . . . . . . . . . . . . .
6.6.9.3 Port J Pull Enable Register (PTJPE) . . . . . . . . . . . . . . . . . . . . . . .
6.6.9.4 Port J Slew Rate Enable Register (PTJSE) . . . . . . . . . . . . . . . . . .
6.6.9.5 Port J Drive Strength Selection Register (PTJDS) . . . . . . . . . . . . .
6.6.9.6 Port J Input Filter Enable Register (PTJIFE) . . . . . . . . . . . . . . . . .
6.6.10 Keyboard Interrupt 1 (KBI1) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6.10.1 KBI1 Interrupt Status and Control Register (KBI1SC) . . . . . . . . . .
6.6.10.2 KBI1 Interrupt Pin Select Register (KBI1PE) . . . . . . . . . . . . . . . . .
6.6.10.3 KBI1 Interrupt Edge Select Register (KBI1ES) . . . . . . . . . . . . . . . .
6.6.11 Keyboard Interrupt 2 (KBI2) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6.11.1 KBI2 Interrupt Status and Control Register (KBI2SC) . . . . . . . . . .
6.6.11.2 KBI2 Interrupt Pin Select Register (KBI2PE) . . . . . . . . . . . . . . . . .
6.6.11.3 KBI2 Interrupt Edge Select Register (KBI2ES) . . . . . . . . . . . . . . . .
6-22
6-22
6-23
6-23
6-23
6-24
6-24
6-24
6-25
6-25
6-25
6-26
6-26
6-26
6-27
6-27
6-28
6-28
6-28
6-29
6-29
6-30
6-30
6-30
6-31
6-31
6-32
Chapter 7
ColdFire Core
7.1
7.2
7.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
Memory Map/Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
7.2.1 Data Registers (D0–D7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
7.2.2 Address Registers (A0–A6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
7.2.3 Supervisor/User Stack Pointers (A7 and OTHER_A7) . . . . . . . . . . . . . . . . . . . 7-5
7.2.4 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
7.2.5 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
7.2.6 Vector Base Register (VBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
7.2.7 CPU Configuration Register (CPUCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
7.2.8 Status Register (SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
7.3.1 Instruction Set Architecture (ISA_C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
7.3.2 Exception Processing Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
7.3.2.1 Exception Stack Frame Definition . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
MCF51MM256 Series Devices Reference Manual, Rev. 3
viii
Freescale Semiconductor
7.3.3 Processor Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.3.1 Access Error Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.3.2 Address Error Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.3.3 Illegal Instruction Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.3.4 Privilege Violation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.3.5 Trace Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.3.6 Unimplemented Line-A Opcode . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.3.7 Unimplemented Line-F Opcode . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.3.8 Debug Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.3.9 RTE and Format Error Exception . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.3.10 TRAP Instruction Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.3.11 Unsupported Instruction Exception . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.3.12 Interrupt Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.3.13 Fault-on-Fault Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.3.14 Reset Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.4 Instruction Execution Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.4.1 Timing Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.4.2 MOVE Instruction Execution Times . . . . . . . . . . . . . . . . . . . . . . . .
7.3.4.3 Standard One Operand Instruction Execution Times . . . . . . . . . . .
7.3.4.4 Standard Two Operand Instruction Execution Times . . . . . . . . . . .
7.3.4.5 Miscellaneous Instruction Execution Times . . . . . . . . . . . . . . . . . .
7.3.4.6 MAC Instruction Execution Times . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.4.7 Branch Instruction Execution Times . . . . . . . . . . . . . . . . . . . . . . . .
7-14
7-14
7-14
7-15
7-16
7-16
7-17
7-17
7-17
7-17
7-18
7-18
7-18
7-18
7-19
7-22
7-22
7-23
7-24
7-25
7-26
7-27
7-28
Chapter 8
Multiply-Accumulate Unit (MAC)
8.1
8.2
8.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1.1.1 Introduction to the MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2.1 MAC Status Register (MACSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2.2 Mask Register (MASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2.3 Accumulator Register (ACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3.1 Fractional Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3.1.1 Rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3.1.2 Saving and Restoring the MAC Programming Model . . . . . . . . . . . .
8.3.1.3 MULS/MULU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3.1.4 Scale Factor in MAC or MSAC Instructions . . . . . . . . . . . . . . . . . . .
8.3.2 MAC Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3.3 MAC Instruction Execution Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3.4 Data Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3.5 MAC Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-1
8-1
8-1
8-2
8-2
8-4
8-5
8-6
8-7
8-7
8-7
8-8
8-8
8-8
8-9
8-9
8-9
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
ix
Chapter 9
Rapid GPIO (RGPIO)
9.1
9.2
9.3
9.4
9.5
9.6
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
9.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
9.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
9.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
9.2.2 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
9.3.1 RGPIO Data Direction (RGPIO_DIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
9.3.2 RGPIO Data (RGPIO_DATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
9.3.3 RGPIO Pin Enable (RGPIO_ENB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
9.3.4 RGPIO Clear Data (RGPIO_CLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
9.3.5 RGPIO Set Data (RGPIO_SET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
9.3.6 RGPIO Toggle Data (RGPIO_TOG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
Initialization Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
9.6.1 Application 1: Simple Square-Wave Generation . . . . . . . . . . . . . . . . . . . . . . . 9-11
9.6.2 Application 2: 16-bit Message Transmission using SPI Protocol . . . . . . . . . . 9-11
Chapter 10
Interrupt Controller (CF1_INTC)
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.3.1 Force Interrupt Register (INTC_FRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
10.3.2 INTC Programmable Level 6, Priority {7,6} Registers (INTC_PL6P{7,6}) . . . . 10-7
10.3.3 INTC Wakeup Control Register (INTC_WCR) . . . . . . . . . . . . . . . . . . . . . . . . 10-8
10.3.4 INTC Set Interrupt Force Register (INTC_SFRC) . . . . . . . . . . . . . . . . . . . . . 10-9
10.3.5 INTC Clear Interrupt Force Register (INTC_CFRC) . . . . . . . . . . . . . . . . . . . 10-10
10.3.6 INTC Software and Level-n IACK Registers (n = 1,2,3,...,7) . . . . . . . . . . . . . 10-11
10.3.7 Interrupt Request Level and Priority Assignments . . . . . . . . . . . . . . . . . . . . 10-12
10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
10.4.1 Handling of Non-Maskable Level 7 Interrupt Requests . . . . . . . . . . . . . . . . 10-15
10.5 Initialization Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
10.6 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
10.6.1 Emulation of the HCS08’s 1-Level IRQ Handling . . . . . . . . . . . . . . . . . . . . . 10-15
10.6.2 Using INTC_PL6P{7,6} Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16
10.6.3 More on Software IACKs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
MCF51MM256 Series Devices Reference Manual, Rev. 3
x
Freescale Semiconductor
Chapter 11
Programmable Analog Comparator (S08PRACMPV1)
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.1.1 PRACMP Configuration Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.1.2 PRACMP/TPM Configuration Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.1.3 PRACMP/OPAMP Configuration Information . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.1.4 PRACMP Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.1.5 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.1.6 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.1.6.1 Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.1.6.2 Operation in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.1.6.3 Operation in Background Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.1.7 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
11.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
11.3.1 PRACMP Control and Status Register (PRACMPCS) . . . . . . . . . . . . . . . . . . 11-5
11.3.2 PRACMP Control Register 0 (PRACMPC0) . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
11.3.3 PRACMP Control Register 1 (PRACMPC1) . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
11.3.4 PRACMP Control Register 2 (PRACMPC2) . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
11.5 Setup and Operation of PRACMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
11.6 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
11.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10
Chapter 12
Analog-to-Digital Converter (S08ADC16V1)
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1.1 Status and Control and Result Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1.2 ADC and TRIAMP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1.3 Dedicated ADC Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1.4 ADC Reference Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1.5 Module Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1.5.1 Configurations for Stop Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1.5.2 Differential Channel Assignments . . . . . . . . . . . . . . . . . . . . . . . . .
12.1.5.3 Single-Ended Channel Assignments . . . . . . . . . . . . . . . . . . . . . . .
12.1.5.4 Alternate Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1.5.5 Hardware Triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1.5.6 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1.6 ADC Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1.7 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1.8 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.1 Analog Power (VDDAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.2 Analog Ground (VSSAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.3 Voltage Reference Select High (VREFSH) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12-1
12-1
12-1
12-1
12-2
12-2
12-2
12-3
12-3
12-4
12-4
12-5
12-7
12-7
12-7
12-8
12-9
12-9
12-9
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
xi
12.2.4 Voltage Reference Select Low (VREFL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10
12.2.5 Analog Channel Inputs (ADx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10
12.2.6 Differential Analog Channel Inputs (DADx) . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10
12.3 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10
12.3.1 Status and Control Registers 1 (ADCSC1A:ADCSC1n) . . . . . . . . . . . . . . . . 12-11
12.3.2 Configuration Register 1 (ADCCFG1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12
12.3.3 Configuration Register 2 (ADCCFG2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14
12.3.4 Data Result Registers (ADCRHA:ADCRLA to ADCRHn:ADCRLn) . . . . . . . 12-15
12.3.5 Compare Value Registers (ADCCV1H:ADCCV1L and ADCCV2H:ADCCV2L) . . .
12-16
12.3.6 Status and Control Register 2 (ADCSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17
12.3.7 Status and Control Register 3 (ADCSC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18
12.3.8 ADC Offset Correction Register (ADCOFSH:ADCOFSL) . . . . . . . . . . . . . . . 12-19
12.3.9 ADC Plus-Side Gain Register (ADCPGH:ADCPGL) . . . . . . . . . . . . . . . . . . 12-20
12.3.10ADC Minus-Side Gain Register (ADCMGH:ADCMGL) . . . . . . . . . . . . . . . . 12-20
12.3.11ADC Plus-Side General Calibration Value Registers (ADCCLPx) . . . . . . . . 12-21
12.3.12ADC Minus-Side General Calibration Value Registers (ADCCLMx) . . . . . . 12-23
12.3.13Pin Control 1 Register (APCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-24
12.3.14Pin Control 2 Register (APCTL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-25
12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-26
12.4.1 Clock Select and Divide Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-27
12.4.2 Input Select and Pin Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-27
12.4.3 Voltage Reference Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-27
12.4.4 Hardware Trigger and Channel Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-28
12.4.5 Conversion Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-28
12.4.5.1 Initiating Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-28
12.4.5.2 Completing Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-29
12.4.5.3 Aborting Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-30
12.4.5.4 Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-30
12.4.5.5 Sample Time and Total Conversion Time . . . . . . . . . . . . . . . . . . 12-31
12.4.5.6 Conversion Time Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-33
12.4.5.6.1 Typical conversion time configuration . . . . . . . . . . . . . . . 12-33
12.4.5.6.2 Long conversion time configuration . . . . . . . . . . . . . . . . 12-33
12.4.5.7 Hardware Average Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-34
12.4.6 Automatic Compare Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-34
12.4.7 Calibration Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-35
12.4.8 User Defined Offset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-37
12.4.9 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-37
12.4.10MCU Wait Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-38
12.4.11MCU Stop3 Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-38
12.4.11.1 Stop3 Mode With ADACK Disabled . . . . . . . . . . . . . . . . . . . . . . . 12-38
12.4.11.2 Stop3 Mode With ADACK Enabled . . . . . . . . . . . . . . . . . . . . . . . 12-39
12.4.12MCU Stop2 Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-39
12.5 Initialization Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-39
12.5.1 ADC Module Initialization Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-40
MCF51MM256 Series Devices Reference Manual, Rev. 3
xii
Freescale Semiconductor
12.5.1.1 Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.5.1.2 Pseudo-Code Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.6 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.6.1 External Pins and Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.6.1.1 Analog Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.6.1.2 Analog Voltage Reference Pins . . . . . . . . . . . . . . . . . . . . . . . . . .
12.6.1.3 Analog Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.6.2 Sources of Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.6.2.1 Sampling Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.6.2.2 Pin Leakage Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.6.2.3 Noise-Induced Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.6.2.4 Code Width and Quantization Error . . . . . . . . . . . . . . . . . . . . . . .
12.6.2.5 Linearity Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.6.2.6 Code Jitter, Non-Monotonicity, and Missing Codes . . . . . . . . . . .
12-40
12-40
12-41
12-42
12-42
12-42
12-43
12-43
12-43
12-43
12-44
12-44
12-45
12-45
Chapter 13
Cyclic Redundancy Check (CRC)
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
13.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
13.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
13.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.3 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.3.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
13.3.2.1 CRC High Register (CRCH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
13.3.2.2 CRC Low Register (CRCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
13.3.2.3 Transpose Register (TRANSPOSE) . . . . . . . . . . . . . . . . . . . . . . . . 13-6
13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
13.4.1 ITU-T (CCITT) Recommendations and Expected CRC Results . . . . . . . . . . . 13-7
13.4.2 Programming model extension for CF1Core . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
13.4.3 Transpose feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9
13.5 Initialization Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
Chapter 14
Carrier Modulator Timer (CMT)
14.1
14.2
14.3
14.4
14.5
14.6
14.7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IRO Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CMT Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.7.1 Carrier Generator Data Registers (CMTCGH1, CMTCGL1, CMTCGH2, and
CMTCGL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14-1
14-1
14-1
14-3
14-3
14-3
14-4
14-4
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
xiii
14.7.2 CMT Output Control Register (CMTOC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5
14.7.3 CMT Modulator Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . 14-6
14.7.4 CMT Modulator Data Registers (CMTCMD1, CMTCMD2, CMTCMD3 and
CMTCMD4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8
14.8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8
14.8.1 Carrier Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10
14.8.2 Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12
14.8.2.1 Time Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13
14.8.2.2 Baseband Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-14
14.8.2.3 FSK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-14
14.8.2.4 Extended Space Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-15
14.8.2.4.1 EXSPC Operation in Time Mode . . . . . . . . . . . . . . . . . . 14-15
14.8.2.4.2 EXSPC Operation in FSK Mode . . . . . . . . . . . . . . . . . . . 14-16
14.8.3 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-16
14.8.4 CMT Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-16
14.8.5 Low-Power Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-17
14.8.5.1 Wait Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-17
14.8.5.2 Stop3 Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-17
14.8.5.3 Stop2 Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-17
14.8.5.4 Background Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18
Chapter 15
12-bit Digital to Analog Converter (DAC12LVLPv1)
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.1.1 DAC Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.1.2 DAC Vext and Vint Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.1.3 DAC Hardware Trigger Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.1.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.2 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.2.1 DAC Data Register x (DACDATxH:DACDATxL) . . . . . . . . . . . . . . . . . . . . . . .
15.2.2 DAC Status Register (DACS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.2.3 DAC Control Register (DACC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.2.4 DAC Control Register1 (DACC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.2.5 DAC Control Register 2 (DACC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.3.1 DAC Data Buffer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.3.1.1 Buffer Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.3.1.2 Buffer Swing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.3.1.3 Buffer One-time Scan Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.3.2 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.3.3 Low Power Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.3.3.1 Wait Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.3.3.2 Stop Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.3.4 Background Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15-1
15-1
15-1
15-1
15-3
15-3
15-4
15-5
15-5
15-6
15-7
15-8
15-8
15-8
15-8
15-9
15-9
15-9
15-9
15-9
15-9
15-9
MCF51MM256 Series Devices Reference Manual, Rev. 3
xiv
Freescale Semiconductor
Chapter 16
Inter-Integrated Circuit (S08IICV3)
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
16.1.1 Module Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
16.1.2 IIC Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
16.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3
16.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3
16.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4
16.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4
16.2.1 SCL — Serial Clock Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4
16.2.2 SDA — Serial Data Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4
16.3 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5
16.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5
16.3.2 IIC Address Register 1 (IICA1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5
16.3.3 IIC Frequency Divider Register (IICF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6
16.3.4 IIC Control Register (IICC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-9
16.3.5 IIC Status Register (IICS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10
16.3.6 IIC Data I/O Register (IICD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11
16.3.7 IIC Control Register 2 (IICC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13
16.3.8 IIC SMBus Control and Status Register (IICSMB) . . . . . . . . . . . . . . . . . . . . 16-14
16.3.9 IIC Address Register 2 (IICA2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15
16.3.10IIC SCL Low Time Out Register High (IICSLTH) . . . . . . . . . . . . . . . . . . . . . 16-15
16.3.11IIC SCL LowTime Out register Low (IICSLTL) . . . . . . . . . . . . . . . . . . . . . . . 16-15
16.3.12IIC Programmable Input Glitch Filter (IICFLT) . . . . . . . . . . . . . . . . . . . . . . . 16-16
16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-17
16.4.1 IIC Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-17
16.4.1.1 START Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-18
16.4.1.2 Slave Address Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-18
16.4.1.3 Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-18
16.4.1.4 STOP Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-19
16.4.1.5 Repeated START Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-19
16.4.1.6 Arbitration Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-19
16.4.1.7 Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-19
16.4.1.8 Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-20
16.4.1.9 Clock Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-20
16.4.2 10-bit Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-21
16.4.2.1 Master-Transmitter Addresses a Slave-Receiver . . . . . . . . . . . . . 16-21
16.4.2.2 Master-Receiver Addresses a Slave-Transmitter . . . . . . . . . . . . . 16-21
16.4.3 Address Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-22
16.4.4 System Management Bus Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-22
16.4.4.1 Timeouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-22
16.4.4.1.1 SCL Low Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-22
16.4.4.1.2 SCL High (SMBus Free) Timeout . . . . . . . . . . . . . . . . . . 16-23
16.4.4.1.3 CSMBCLK TIMEOUT MEXT . . . . . . . . . . . . . . . . . . . . . 16-23
16.4.4.1.4 CSMBCLK TIMEOUT SEXT . . . . . . . . . . . . . . . . . . . . . . 16-23
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
xv
16.5
16.6
16.7
16.8
16.4.4.2 FAST ACK and NACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.6.1 Byte Transfer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.6.2 Address Detect Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.6.3 Arbitration Lost Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.6.4 Timeouts Interrupt in SMbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.6.5 Programmable input glitch filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SMBALERT# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-24
16-24
16-24
16-25
16-25
16-25
16-25
16-26
16-27
16-30
Chapter 17
Multipurpose Clock Generator (S08MCGV3)
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1
17.1.1 Clock Check & Select Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.1.2 Clock Check & Select Control (CCSCTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.1.3 CCS XOSC1 Timer Register (CCSTMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4
17.1.4 CCS XOSC2 Timer Register (CCSTMR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5
17.1.5 CCS Internal Reference Clock Timer Register (CCSTMRIR) . . . . . . . . . . . . . 17-5
17.1.6 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5
17.1.7 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6
17.1.8 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8
17.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8
17.3 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8
17.3.1 MCG Control Register 1 (MCGC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8
17.3.2 MCG Control Register 2 (MCGC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10
17.3.3 MCG Trim Register (MCGTRM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11
17.3.4 MCG Status and Control Register (MCGSC) . . . . . . . . . . . . . . . . . . . . . . . . 17-12
17.3.5 MCG Control Register 3 (MCGC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13
17.3.6 MCG Control Register 4 (MCGC4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-14
17.3.7 MCG Test Register (MCGT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-15
17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16
17.4.1 MCG Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16
17.4.2 MCG Mode State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-18
17.4.3 Mode Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-18
17.4.4 Bus Frequency Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19
17.4.5 Low Power Bit Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19
17.4.6 Internal Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19
17.4.7 External Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19
17.4.8 Fixed Frequency Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-20
17.4.9 MCGPLLSCLK Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-20
17.5 Initialization / Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-21
17.5.1 MCG Module Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-21
17.5.1.1 Initializing the MCG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-21
17.5.2 Using a 32.768 kHz Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-23
MCF51MM256 Series Devices Reference Manual, Rev. 3
xvi
Freescale Semiconductor
17.5.3 MCG Mode Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-23
17.5.3.1 Example 1: Moving from FEI to PEE Mode: External Crystal = 8 MHz,
Bus Frequency = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-24
17.5.3.2 Example 2: Moving from PEE to BLPI Mode: Bus Frequency =16 kHz .
17-28
17.5.3.3 Example 3: Moving from BLPI to FEE Mode: External Crystal = 8 MHz,
Bus Frequency = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-31
17.5.4 Calibrating the Internal Reference Clock (IRC) . . . . . . . . . . . . . . . . . . . . . . 17-32
17.5.4.1 Example 4: Internal Reference Clock Trim . . . . . . . . . . . . . . . . . . 17-33
Chapter 18
Mini-FlexBus
18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1
18.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1
18.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1
18.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2
18.1.4 Module Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2
18.1.5 Mini-FlexBus Security Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2
18.1.6 Mini-FlexBus Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2
18.2 External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4
18.2.1 Address and Data Buses (FB_A[19:0], FB_D[7:0], FB_AD[:0]) . . . . . . . . . . . 18-4
18.2.1 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4
18.2.2 Chip Selects (FB_CS[1:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4
18.2.3 Output Enable (FB_OE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4
18.2.4 Read/Write (FB_R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4
18.2.5 Address Latch Enable (FB_ALE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5
18.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5
18.3.1 Chip-Select Address Registers (CSAR0 – CSAR1) . . . . . . . . . . . . . . . . . . . . 18-5
18.3.2 Chip-Select Mask Registers (CSMR0 – CSMR1) . . . . . . . . . . . . . . . . . . . . . . 18-6
18.3.3 Chip-Select Control Registers (CSCR0 – CSCR1) . . . . . . . . . . . . . . . . . . . . . 18-7
18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-8
18.4.1 Chip-Select Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-8
18.4.1.1 General Chip-Select Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9
18.4.1.2 8- and 16-Bit Port Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9
18.4.2 Data Transfer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9
18.4.3 Data Byte Alignment and Physical Connections . . . . . . . . . . . . . . . . . . . . . . 18-10
18.4.4 Address/Data Bus Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-10
18.4.5 Bus Cycle Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-10
18.4.5.1 Data Transfer Cycle States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-11
18.4.6 Mini-FlexBus Timing Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-12
18.4.6.1 Basic Read Bus Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-12
18.4.6.2 Basic Write Bus Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-13
18.4.6.3 Bus Cycle Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-14
18.4.6.4 Timing Variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-17
18.4.6.4.1 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-17
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
xvii
18.4.6.4.2 Address Setup and Hold . . . . . . . . . . . . . . . . . . . . . . . . . 18-20
18.4.7 Bus Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-22
Chapter 19
General Purpose Operational Amplifier (OPAMP)
19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1
19.1.1 OPAMP Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1
19.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3
19.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3
19.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4
19.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5
19.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6
19.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6
19.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6
19.3.2.1 GPAMP Control Register 0 (GPAMPxC0) . . . . . . . . . . . . . . . . . . . 19-6
19.3.2.2 GPAMP Control Register 1 (GPAMPxC1) . . . . . . . . . . . . . . . . . . . 19-7
19.3.2.3 GPAMP Control Register 2 (GPAMPxC2) . . . . . . . . . . . . . . . . . . . 19-7
19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-8
19.4.1 OPAMP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-9
19.4.2 Buffer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-10
19.4.3 Inverting PGA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-11
19.4.4 Non-Inverting PGA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-12
Chapter 20
Programmable Delay Block (PDB)
20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1
20.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1
20.1.2 PDB Trigger Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1
20.2 ADC Hardware Triggers and Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2
20.2.1 PDB Trigger Acknowledgement Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2
20.2.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4
20.2.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4
20.2.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6
20.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-11
20.3.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-11
20.3.2 Registers Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-11
20.3.2.1 PDB Status and Control Register (PDBSC) . . . . . . . . . . . . . . . . . 20-11
20.3.2.2 PDB Control Register 1 (PDBC1) . . . . . . . . . . . . . . . . . . . . . . . . . 20-13
20.3.2.3 PDB Control Register 2 (PDBC2) . . . . . . . . . . . . . . . . . . . . . . . . . 20-14
20.3.2.4 PDB Channel Enable Register (PDBCHEN) . . . . . . . . . . . . . . . . 20-15
20.3.2.5 PDB Modulus Registers (PDBMODH:PDBMODL) . . . . . . . . . . . . 20-15
20.3.2.6 PDB Counter Registers (PDBCNTH:PDBCNTL) . . . . . . . . . . . . . 20-16
20.3.2.7 PDB Interrupt Delay Register (PDBIDLYH:PDBIDLYL) . . . . . . . . 20-16
20.3.2.8 DAC Interval Registers (DACINTH:DACINTL) . . . . . . . . . . . . . . . 20-16
20.3.2.9 PDB Delay Registers (PDBDLYnH:PDBDLYnL) . . . . . . . . . . . . . 20-17
MCF51MM256 Series Devices Reference Manual, Rev. 3
xviii
Freescale Semiconductor
20.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.3.3.1 Impact of Using the Prescaler on Timing Resolution . . . . . . . . . .
20.4 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.5 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20-18
20-18
20-18
20-18
20-18
Chapter 21
Serial Communication Interface (S08SCIV4)
21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.1.1 SCIx Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.1.2 Module Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.1.3 Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.1.4 Interfacing the SCIs to Off-Chip Opto-Isolators . . . . . . . . . . . . . . . . . . . . . .
21.1.5 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.1.6 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.1.7 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.2 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.2.1 SCI Baud Rate Registers (SCIxBDH, SCIxBDL) . . . . . . . . . . . . . . . . . . . . .
21.2.2 SCI Control Register 1 (SCIxC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.2.3 SCI Control Register 2 (SCIxC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.2.4 SCI Status Register 1 (SCIxS1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.2.5 SCI Status Register 2 (SCIxS2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.2.6 SCI Control Register 3 (SCIxC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.2.7 SCI Data Register (SCIxD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.3.1 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.3.2 Transmitter Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.3.2.1 Send Break and Queued Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.3.3 Receiver Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.3.3.1 Data Sampling Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.3.3.2 Receiver Wakeup Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.3.3.2.1 Idle-Line Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.3.3.2.2 Address-Mark Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . .
21.3.4 Interrupts and Status Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.3.5 Additional SCI Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.3.5.1 8- and 9-Bit Data Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.3.5.2 Stop Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.3.5.3 Loop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.3.5.4 Single-Wire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21-19
21-19
21-19
21-20
21-21
21-21
21-22
21-23
21-25
21-25
21-26
21-27
21-28
21-30
21-31
21-32
21-32
21-32
21-33
21-34
21-34
21-35
21-35
21-36
21-36
21-36
21-37
21-37
21-37
21-38
21-38
Chapter 22
16-bit Serial Peripheral Interface (S08SPI16V5)
22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1
22.1.1 SPI1 Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1
22.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
xix
22.2
22.3
22.4
22.5
22.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3
22.1.4 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4
22.1.4.1 SPI System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4
22.1.4.2 SPI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4
External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6
22.2.1 SPSCK — SPI Serial Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6
22.2.2 MOSI — Master Data Out, Slave Data In . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6
22.2.3 MISO — Master Data In, Slave Data Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6
22.2.4 SS — Slave Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6
Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6
22.3.1 SPI Control Register 1 (SPIxC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7
22.3.2 SPI Control Register 2 (SPIxC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8
22.3.3 SPI Baud Rate Register (SPIxBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-10
22.3.4 SPI Status Register (SPIxS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11
22.3.5 SPI Data Registers (SPIxDH:SPIxDL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-14
22.3.6 SPI Match Registers (SPIxMH:SPIxML) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-15
22.3.7 SPI Control Register 3 (SPIxC3) — enable FIFO feature . . . . . . . . . . . . . . . 22-15
22.3.8 SPI Clear Interrupt Register (SPIxCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-17
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-18
22.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-18
22.4.2 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-18
22.4.3 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-19
22.4.4 SPI FIFO MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-21
22.4.5 Data Transmission Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-22
22.4.6 SPI Clock Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-22
22.4.7 SPI Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-24
22.4.8 Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-25
22.4.8.1 SS Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-25
22.4.8.2 Bidirectional Mode (MOMI or SISO) . . . . . . . . . . . . . . . . . . . . . . . 22-25
22.4.9 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-26
22.4.9.1 Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-26
22.4.10Low-power Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-27
22.4.10.1 SPI in Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-27
22.4.10.2 SPI in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-27
22.4.10.3 SPI in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-28
22.4.10.4 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-28
22.4.10.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-28
22.4.11SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-28
22.4.11.1 MODF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-29
22.4.11.2 SPRF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-29
22.4.11.3 SPTEF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-29
22.4.11.4 SPMF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-29
22.4.11.5 TNEAREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-29
22.4.11.6 RNFULLF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-30
Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-30
MCF51MM256 Series Devices Reference Manual, Rev. 3
xx
Freescale Semiconductor
22.5.1 SPI Module Initialization Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-30
22.5.1.1 Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-30
22.5.1.2 Pseudo—Code Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-30
Chapter 23
8-bit Serial Peripheral Interface (S08SPIV5)
23.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1
23.1.1 SPI2 Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1
23.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3
23.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3
23.1.4 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3
23.1.4.1 SPI System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4
23.1.4.2 SPI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4
23.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5
23.2.1 SPSCK — SPI Serial Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5
23.2.2 MOSI — Master Data Out, Slave Data In . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6
23.2.3 MISO — Master Data In, Slave Data Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6
23.2.4 SS — Slave Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6
23.3 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6
23.3.1 SPI Control Register 1 (SPIxC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6
23.3.2 SPI Control Register 2 (SPIxC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-8
23.3.3 SPI Baud Rate Register (SPIxBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-9
23.3.4 SPI Status Register (SPIxS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-10
23.3.5 SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-11
23.3.6 SPI Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-12
23.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-12
23.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-12
23.4.2 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-13
23.4.3 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-14
23.4.4 SPI Clock Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-15
23.4.5 SPI Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-17
23.4.6 Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-18
23.4.6.1 SS Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-18
23.4.6.2 Bidirectional Mode (MOMI or SISO) . . . . . . . . . . . . . . . . . . . . . . . 23-18
23.4.7 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-19
23.4.7.1 Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-19
23.4.8 Low-power Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-20
23.4.8.1 SPI in Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-20
23.4.8.2 SPI in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-20
23.4.8.3 SPI in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-21
23.4.8.4 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-21
23.4.8.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-21
23.4.9 SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-21
23.4.9.1 MODF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-22
23.4.9.2 SPRF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-22
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
xxi
23.4.9.3 SPTEF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.4.9.4 SPMF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.5.1 SPI Module Initialization Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.5.1.1 Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.5.1.2 Pseudo—Code Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23-22
23-22
23-22
23-22
23-22
23-23
Chapter 24
Time Of Day Module (S08TODV1)
24.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1
24.1.1 TOD Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1
24.1.2 TOD Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1
24.1.3 TOD Status after Stop2 Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1
24.1.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3
24.1.5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3
24.1.6 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4
24.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5
24.2.1 TOD Clock (TODCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5
24.2.2 TOD Match Signal (TODMTCHS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5
24.3 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5
24.3.1 TOD Control Register (TODC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5
24.3.2 TOD Status and Control Register (TODSC) . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6
24.3.3 TOD Match Register (TODM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-8
24.3.4 TOD Counter Register (TODCNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-8
24.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-8
24.4.1 TOD Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9
24.4.2 TOD Match Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9
24.4.3 Match Write Complete . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-10
24.4.4 TOD Clock Select and Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-11
24.4.4.1 TOD Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-11
24.4.5 Quarter-Second, One-Second, and Match Interrupts . . . . . . . . . . . . . . . . . . 24-12
24.4.5.1 Quarter-Second Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12
24.4.5.2 One-Second Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12
24.4.5.3 Match Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12
24.4.6 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-13
24.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-13
24.5 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-13
24.5.1 Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-13
24.5.2 Initialization Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-14
24.5.2.1 Initialization Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-14
24.5.2.2 Initialization Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-16
24.5.2.3 Initialization Example 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-17
24.6 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-17
MCF51MM256 Series Devices Reference Manual, Rev. 3
xxii
Freescale Semiconductor
Chapter 25
Timer/Pulse-Width Modulator (S08TPMV3)
25.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1
25.1.1 ACMP/TPM Configuration Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1
25.1.2 TPM External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1
25.1.3 TPM Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1
25.1.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3
25.1.5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3
25.1.6 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4
25.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-6
25.2.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-6
25.2.1.1 EXTCLK — External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . 25-6
25.2.1.2 TPMxCHn — TPM Channel n I/O Pins . . . . . . . . . . . . . . . . . . . . . . 25-6
25.3 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-9
25.3.1 TPM Status and Control Register (TPMxSC) . . . . . . . . . . . . . . . . . . . . . . . . . 25-9
25.3.2 TPM-Counter Registers (TPMxCNTH:TPMxCNTL) . . . . . . . . . . . . . . . . . . . 25-10
25.3.3 TPM Counter Modulo Registers (TPMxMODH:TPMxMODL) . . . . . . . . . . . . 25-11
25.3.4 TPM Channel n Status and Control Register (TPMxCnSC) . . . . . . . . . . . . . 25-12
25.3.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL) . . . . . . . . . . . . . . 25-13
25.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-15
25.4.1 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-15
25.4.1.1 Counter Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-15
25.4.1.2 Counter Overflow and Modulo Reset . . . . . . . . . . . . . . . . . . . . . . 25-16
25.4.1.3 Counting Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-16
25.4.1.4 Manual Counter Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-16
25.4.2 Channel Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-16
25.4.2.1 Input Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-16
25.4.2.2 Output Compare Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-17
25.4.2.3 Edge-Aligned PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-17
25.4.2.4 Center-Aligned PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-18
25.5 Reset Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-19
25.5.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-19
25.5.2 Description of Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-20
25.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-20
25.6.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-20
25.6.2 Description of Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-20
25.6.2.1 Timer Overflow Interrupt (TOF) Description . . . . . . . . . . . . . . . . . 25-21
25.6.2.1.1 Normal Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-21
25.6.2.1.2 Center-Aligned PWM Case . . . . . . . . . . . . . . . . . . . . . . . 25-21
25.6.2.2 Channel Event Interrupt Description . . . . . . . . . . . . . . . . . . . . . . . 25-21
25.6.2.2.1 Input Capture Events . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-21
25.6.2.2.2 Output Compare Events . . . . . . . . . . . . . . . . . . . . . . . . . 25-21
25.6.2.2.3 PWM End-of-Duty-Cycle Events . . . . . . . . . . . . . . . . . . . 25-21
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
xxiii
Chapter 26
Trans-Impedance Amplifier (TRIAMP)
26.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26.1.1 TRIAMP Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26.1.5 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26.2 Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26.2.1 TIAMP Control Register 0 (TIAMPxC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26.3.1 Trans-Impedance Amplifier Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26-1
26-1
26-3
26-3
26-3
26-3
26-4
26-4
26-4
26-4
Chapter 27
USB On-the-GO (USBOTG)
27.1
27.2
27.3
27.4
27.5
27.6
27.0.1 Module Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3
27.0.2 USB Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3
27.2.1 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3
27.2.2 USB On-The-Go . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-5
27.2.3 USB-FS Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6
27.2.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6
27.2.4.1 Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6
27.2.4.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6
27.2.4.3 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6
External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6
27.3.1 USB Pull-up/Pull-down Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6
27.3.2 USB OTG Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-7
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8
27.4.1 Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8
Programmers Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-9
27.5.1 Buffer Descriptor Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-9
27.5.2 Rx vs. Tx as a USB Target Device or USB Host . . . . . . . . . . . . . . . . . . . . . 27-10
27.5.3 Addressing Buffer Descriptor Table Entries . . . . . . . . . . . . . . . . . . . . . . . . . 27-10
27.5.4 Buffer Descriptor Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-11
27.5.5 USB Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-12
Memory Map/Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-14
27.6.1 Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-15
27.6.1.1 Peripheral ID Register (PER_ID) . . . . . . . . . . . . . . . . . . . . . . . . . 27-16
27.6.1.2 Peripheral ID Complement Register (ID_COMP) . . . . . . . . . . . . . 27-16
27.6.1.3 Peripheral Revision Register (REV) . . . . . . . . . . . . . . . . . . . . . . . 27-17
27.6.1.4 Peripheral Additional Info Register (ADD_INFO) . . . . . . . . . . . . . 27-17
27.6.1.5 OTG Interrupt Status Register (OTG_INT_STAT) . . . . . . . . . . . . 27-18
27.6.1.6 OTG Interrupt Control Register (OTG_INT_EN) . . . . . . . . . . . . . 27-19
MCF51MM256 Series Devices Reference Manual, Rev. 3
xxiv
Freescale Semiconductor
27.6.1.7 Interrupt Status Register (OTG_STAT) . . . . . . . . . . . . . . . . . . . .
27.6.1.8 OTG Control Register (OTG_CTRL) . . . . . . . . . . . . . . . . . . . . . .
27.6.1.9 Interrupt Status Register (INT_STAT) . . . . . . . . . . . . . . . . . . . . .
27.6.1.10 Interrupt Enable Register (INT_ENB) . . . . . . . . . . . . . . . . . . . . . .
27.6.1.11 Error Interrupt Status Register (ERR_STAT) . . . . . . . . . . . . . . . .
27.6.1.12 Error Interrupt Enable Register (ERR_ENB) . . . . . . . . . . . . . . . .
27.6.1.13 Status Register (STAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.6.1.14 Control Register (CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.6.1.15 Address Register (ADDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.6.1.16 BDT Page Register 1 (BDT_PAGE_01) . . . . . . . . . . . . . . . . . . . .
27.6.1.17 Frame Number Register Low/High (FRM_NUML, FRM_NUMH) .
27.6.1.18 Token Register (TOKEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.6.1.19 SOF Threshold Register (SOF_THLD) . . . . . . . . . . . . . . . . . . . . .
27.6.1.20 BDT Page Register 2 (BDT_PAGE_02) . . . . . . . . . . . . . . . . . . . .
27.6.1.21 BDT Page Register 3 (BDT_PAGE_03) . . . . . . . . . . . . . . . . . . . .
27.6.1.22 Endpoint Control Registers 0 – 15 (ENDPT0–15) . . . . . . . . . . . .
27.6.1.23 USB Control Register (USB_CTRL) . . . . . . . . . . . . . . . . . . . . . . .
27.6.1.24 USB OTG Observe Register (USB_OTG_OBSERVE) . . . . . . . .
27.6.1.25 USB OTG Control Register (USB_OTG_CONTROL) . . . . . . . . .
27.6.1.26 USB Transceiver and Regulator Control Register 0 (USBTRC0) .
27.6.1.27 OTG Pin Control Register (OTGPIN) . . . . . . . . . . . . . . . . . . . . . .
27.7 OTG and Host Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.7.1 Configuration of External Pull-up/Pull-down for USB . . . . . . . . . . . . . . . . . .
27.8 Host Mode Operation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.9 On-The-Go Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.9.1 OTG Dual Role A Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.9.2 OTG Dual Role B Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.9.3 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.9.4 USB Suspend State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27-20
27-21
27-22
27-23
27-24
27-25
27-26
27-27
27-28
27-29
27-30
27-31
27-32
27-33
27-33
27-34
27-36
27-36
27-37
27-38
27-39
27-40
27-40
27-42
27-44
27-44
27-46
27-47
27-47
Chapter 28
Voltage Reference Module (S08VREFV1)
28.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.1.1 VREF Configuration Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.1.2 VREF Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.1.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.1.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.1.5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.1.6 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.2 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.2.1 VREF Trim Register (VREFTRM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.2.2 VREF Status and Control Register (VREFSC) . . . . . . . . . . . . . . . . . . . . . . . .
28.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.3.1 Voltage Reference Disabled, VREFEN=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.3.2 Voltage Reference Enabled, VREFEN=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28-1
28-3
28-3
28-3
28-4
28-5
28-5
28-5
28-5
28-6
28-7
28-7
28-7
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
xxv
28.3.2.1 Mode[1:0]=00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.3.2.2 Mode[1:0]=01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.3.2.3 Mode[1:0]=10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.3.2.4 Mode[1:0]=11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.4 Initialization Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28-7
28-7
28-8
28-8
28-8
Chapter 29
Version 1 ColdFire Debug (CF1_DEBUG)
29.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1
29.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2
29.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3
29.1.3 Modes of Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3
29.2 External Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-5
29.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6
29.3.1 Configuration/Status Register (CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-7
29.3.2 Extended Configuration/Status Register (XCSR) . . . . . . . . . . . . . . . . . . . . . 29-10
29.3.3 Configuration/Status Register 2 (CSR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-13
29.3.4 Configuration/Status Register 3 (CSR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-16
29.3.5 BDM Address Attribute Register (BAAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-17
29.3.6 Address Attribute Trigger Register (AATR) . . . . . . . . . . . . . . . . . . . . . . . . . . 29-18
29.3.7 Trigger Definition Register (TDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-19
29.3.8 Program Counter Breakpoint/Mask Registers (PBR0–3, PBMR) . . . . . . . . . 29-22
29.3.9 Address Breakpoint Registers (ABLR, ABHR) . . . . . . . . . . . . . . . . . . . . . . . 29-24
29.3.10Data Breakpoint and Mask Registers (DBR, DBMR) . . . . . . . . . . . . . . . . . 29-25
29.3.10.1 Resulting Set of Possible Trigger Combinations . . . . . . . . . . . . . 29-26
29.3.11PST Buffer (PSTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-26
29.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-27
29.4.1 Background Debug Mode (BDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-27
29.4.1.1 CPU Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-28
29.4.1.2 Background Debug Serial Interface Controller (BDC) . . . . . . . . . 29-29
29.4.1.3 BDM Communication Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-30
29.4.1.4 BDM Command Set Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 29-33
29.4.1.5 BDM Command Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-36
29.4.1.5.1 SYNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-38
29.4.1.5.2 ACK_DISABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-39
29.4.1.5.3 ACK_ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-39
29.4.1.5.4 BACKGROUND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-40
29.4.1.5.5 DUMP_MEM.sz, DUMP_MEM.sz_WS . . . . . . . . . . . . . . 29-40
29.4.1.5.6 FILL_MEM.sz, FILL_MEM.sz_WS . . . . . . . . . . . . . . . . . 29-42
29.4.1.5.7 GO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-43
29.4.1.5.8 NOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-43
29.4.1.5.9 READ_CREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-44
29.4.1.5.10 READ_DREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-44
29.4.1.5.11 READ_MEM.sz, READ_MEM.sz_WS . . . . . . . . . . . . . . 29-45
29.4.1.5.12 READ_PSTB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-46
MCF51MM256 Series Devices Reference Manual, Rev. 3
xxvi
Freescale Semiconductor
29.4.1.5.13 READ_Rn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.4.1.5.14 READ_XCSR_BYTE . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.4.1.5.15 READ_CSR2_BYTE . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.4.1.5.16 READ_CSR3_BYTE . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.4.1.5.17 SYNC_PC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.4.1.5.18 WRITE_CREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.4.1.5.19 WRITE_DREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.4.1.5.20 WRITE_MEM.sz, WRITE_MEM.sz_WS . . . . . . . . . . . . .
29.4.1.5.21 WRITE_Rn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.4.1.5.22 WRITE_XCSR_BYTE . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.4.1.5.23 WRITE_CSR2_BYTE . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.4.1.5.24 WRITE_CSR3_BYTE . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.4.1.5.25 BDM Accesses of the MAC Registers . . . . . . . . . . . . . .
29.4.1.6 Serial Interface Hardware Handshake Protocol . . . . . . . . . . . . . .
29.4.1.7 Hardware Handshake Abort Procedure . . . . . . . . . . . . . . . . . . . .
29.4.2 Real-Time Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.4.3 Trace Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.4.3.1 Begin Execution of Taken Branch (PST = 0x05) . . . . . . . . . . . . .
29.4.3.2 PST Trace Buffer (PSTB) Entry Format . . . . . . . . . . . . . . . . . . . .
29.4.3.3 PST/DDATA Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.4.3.4 Processor Status, Debug Data Definition . . . . . . . . . . . . . . . . . . .
29.4.3.4.1 User Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.4.3.4.2 Supervisor Instruction Set . . . . . . . . . . . . . . . . . . . . . . . .
29.4.4 Freescale-Recommended BDM Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29-46
29-46
29-47
29-47
29-47
29-48
29-48
29-49
29-50
29-50
29-50
29-50
29-51
29-51
29-53
29-56
29-56
29-58
29-60
29-60
29-62
29-62
29-66
29-67
Appendix A
Revision History
A.1 Changes Between Rev. 0 and Rev. 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
A.2 Changes Between Rev. 1 and Rev. 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
A.3 Changes Between Rev. 2 and Rev. 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
xxvii
MCF51MM256 Series Devices Reference Manual, Rev. 3
xxviii
Freescale Semiconductor
About This Book
The primary objective of this reference manual is to define the processor for software and hardware
developers. The information in this book is subject to change without notice, as described in the
disclaimers on the title page. As with any technical documentation, the reader must use the most recent
version of the documentation.
To locate any published errata or updates for this document, refer to the world-wide web at
http://www.freescale.com/coldfire.
Portions of Chapter 27, “USB On-the-GO (USBOTG) relating to the EHCI specification are Copyright ©
Intel Corporation 1999-2001. The EHCI specification is provided “As Is” with no warranties whatsoever,
including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any
warranty otherwise arising out of any proposal, specification or sample. Intel disclaims all liability,
including liability for infringement of any proprietary rights, relating to use of information in the EHCI
specification. Intel may make changes to the EHCI specifications at any time, without notice.
Audience
This manual is intended for system software and hardware developers and applications programmers who
want to develop products with this ColdFire processor. It is assumed that the reader understands operating
systems, microprocessor system design, basic principles of software and hardware, and basic details of the
ColdFire® architecture.
Suggested Reading
This section lists additional reading that provides background for the information in this manual as well as
general information about ColdFire architecture.
General Information
Useful information about the ColdFire architecture and computer architecture in general:
• ColdFire Programmers Reference Manual (MCF5200PRM/AD)
• Using Microprocessors and Microcomputers: The Motorola Family, William C. Wray, Ross
Bannatyne, Joseph D. Greenfield
• Computer Architecture: A Quantitative Approach, Second Edition, by John L. Hennessy and David
A. Patterson.
• Computer Organization and Design: The Hardware/Software Interface, Second Edition, David A.
Patterson and John L. Hennessy.
Freescale Semiconductor
xxix
ColdFire Documentation
ColdFire documentation is available from the sources listed on the back cover of this manual, as well as
our web site, http://www.freescale.com/coldfire.
• Reference manuals — These books provide details about individual ColdFire implementations and
are intended to be used in conjunction with the ColdFire Programmers Reference Manual.
• Data sheets — Data sheets provide specific data regarding pin-out diagrams, bus timing, signal
behavior, and AC, DC, and thermal characteristics, as well as other design considerations.
• Product briefs — Each device has a product brief that provides an overview of its features. This
document is roughly equivalent to the overview (Chapter 1) of an device’s reference manual.
• Application notes — These short documents address specific design issues useful to programmers
and engineers working with Freescale Semiconductor processors.
Additional literature is published as new processors become available. For a current list of ColdFire
documentation, refer to http://www.freescale.com/coldfire.
Conventions
This document uses the following notational conventions:
cleared/set
When a bit takes the value zero, it is said to be cleared; when it takes a value of
one, it is said to be set.
MNEMONICS
In text, instruction mnemonics are shown in uppercase.
mnemonics
In code and tables, instruction mnemonics are shown in lowercase.
italics
Italics indicate variable command parameters.
Book titles in text are set in italics.
0x0
Prefix to denote hexadecimal number
0b0
Prefix to denote binary number
REG[FIELD]
Abbreviations for registers are shown in uppercase. Specific bits, fields, or ranges
appear in brackets. For example, RAMBAR[BA] identifies the base address field
in the RAM base address register.
nibble
A 4-bit data unit
byte
An 8-bit data unit
word
A 16-bit data unit1
longword
A 32-bit data unit
x
In some contexts, such as signal encodings, x indicates a don’t care.
n
Used to express an undefined numerical value
~
NOT logical operator
&
AND logical operator
|
OR logical operator
1The
only exceptions to this appear in the discussion of serial communication modules that support variable-length data
transmission units. To simplify the discussion these units are referred to as words regardless of length.
xxx
Freescale Semiconductor
||
OVERBAR
Field concatenation operator
An overbar indicates that a signal is active-low.
Register Figure Conventions
This document uses the following conventions for the register reset values:
—
Undefined at reset.
u
Unaffected by reset.
[signal_name]
Reset value is determined by the polarity of the indicated signal.
The following register fields are used:
R
0
Indicates a reserved bit field in a memory-mapped register. These bits are always read as zeros.
1
Indicates a reserved bit field in a memory-mapped register. These bits are always read as ones.
W
R
W
R FIELDNAME
Indicates a read/write bit.
W
R FIELDNAME
Indicates a read-only bit field in a memory-mapped register.
W
R
Indicates a write-only bit field in a memory-mapped register.
W FIELDNAME
R FIELDNAME
W
w1c
R
0
Write 1 to clear: indicates that writing a 1 to this bit field clears it.
Indicates a self-clearing bit.
W FIELDNAME
Freescale Semiconductor
xxxi
xxxii
Freescale Semiconductor
Chapter 1
Device Overview
1.1
The MCF51MM256 Series Microcontroller
1.1.1
Definition
The MCF51MM256 and MCF51MM128 series microcontrollers are systems-on-chip (SoCs) that are
based on the ColdFire® V1 core and:
• Operate at processor core speeds up to 50.33 MHz (peripherals operate at half of this speed).
• Integrate technologies that are important for today’s consumer and industrial applications, such as
USB On-the-Go and high precision analog.
1.1.2
Devices in the MCF51MM256 series
There are two members of the MCF51MM256 series, each available in various packages, as shown in
Table 1-1.
Table 1-1. MCF51MM256 Series Package Availability
MCF51MM256
MCF51MM128
104-pin MAPBGA
Yes
—
100-pin LQFP
Yes
—
81-pin MAPBGA
Yes
Yes
80-pin LQFP
Yes
Yes
The MCF51MM256 series is summarized in the following tables.
Table 1-2. MCF51MM256/128 Features by MCU and Package
Feature
FLASH Size (bytes)
MCF51MM256
MCF51MM128
262144
131072
32K
32K
RAM Size (bytes)
Pin Quantity
104
100
81
80
81
80
Programmable Analog Comparator (PRACMP)
yes
yes
yes
yes
yes
yes
Debug Module (DBG)
yes
yes
yes
yes
yes
yes
Multipurpose Clock Generator (MCG)
yes
yes
yes
yes
yes
yes
Inter-Integrated Communication (IIC)
yes
yes
yes
yes
yes
yes
Interrupt Request Pin (IRQ)
yes
yes
yes
yes
yes
yes
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
1-1
Device Overview
Table 1-2. MCF51MM256/128 Features by MCU and Package
Feature
MCF51MM256
Keyboard Interrupt (KBI)
MCF51MM128
16
16
16
16
16
16
1
Digital General Purpose I/O
69
65
48
47
48
47
Dedicated Analog Input Pins
14
14
14
14
14
14
Power and Ground Pins
8
8
8
8
8
8
Time Of Day (TOD)
yes
yes
yes
yes
yes
yes
Serial Communications (SCI1)
yes
yes
yes
yes
yes
yes
Serial Communications (SCI2)
yes
yes
yes
yes
yes
yes
Serial Peripheral Interface (SPI1(FIFO))
yes
yes
yes
yes
yes
yes
Serial Peripheral Interface(SPI2)
yes
yes
yes
yes
yes
yes
Carrier Modulator Timer Pin (IRO)
yes
yes
yes
yes
yes
yes
TPM Input Clock Pin (TPMCLK)
yes
yes
yes
yes
yes
yes
TPM1 Channels
4
4
4
4
4
4
TPM2 Channels
4
4
4
4
4
4
XOSC1
yes
yes
yes
yes
yes
yes
XOSC2
yes
yes
yes
yes
yes
yes
USB On-the-Go
yes
yes
yes
yes
yes
yes
Mini-FlexBus
yes
yes
DATA2
DATA2
DATA2
DATA2
Rapid GPIO
16
16
9
9
9
9
MEASUREMENT ENGINE
Programmable Delay Block (PDB)
yes
yes
yes
yes
yes
yes
16-Bit SAR ADC Differential Channels3
4
4
4
4
4
4
16-Bit SAR ADC Single-Ended Channels
8
8
8
8
8
8
DAC Ouput Pin (DACO)
yes
yes
yes
yes
yes
yes
Voltage Reference Output Pin (VREFO)
yes
yes
yes
yes
yes
yes
General Purpose Operational Amplifier (OPAMP)
yes
yes
yes
yes
yes
yes
Trans-Impedance Amplifier (TRIAMP)
yes
yes
yes
yes
yes
yes
1
Port I/O count does not include BLMS, BKGD and IRQ. BLMS and BKGD are Output only, IRQ is input only.
The 80/81 pin packages contain the Mini-FlexBus data pins to support an 8-bit data bus interface to external peripherals.
3 Each differential channel is comprised of 2 pin inputs.
2
1.2
MCF51MM256/128 Block Diagram
Figure 1-1 shows the connections between the MCF51MM256/ pins and modules.
MCF51MM256 Series Devices Reference Manual, Rev. 3
1-2
Freescale Semiconductor
Device Overview
Figure 1-1. MCF51MM256 Series Block Diagram
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
1-3
Device Overview
1.2.1
Functional Units
Table 1-3 describes the functional units of the MCF51MM256/128devices.
Table 1-3. MCF51MM256/128 Functional Units
Unit
Function
Measurement Engine
DAC (digital to analog converter) — Used to output voltage levels.
16-BIT SAR ADC (analog-to-digital converter) — Measures analog
voltages at up to 16 bits of resolution. The ADC has up to four
differential and 8 single-ended inputs.
OPAMP — General purpose op amp used for signal filtering or
amplification.
TRIAMP —- Transimpedance amplifier optimized for converting small
currents into voltages.
Measurement Engine PDB — The measurement engine PDB is used
to precisely trigger the DAC and the ADC modules to complete sensor
biasing and measuring.
Mini-FlexBus
Provides expansion capability for off-chip memory and peripherals.
USB On-the-Go
Supports the USB On-the-Go dual-role controller.
CMT (Carrier Modulator Timer)
Infrared output used for the Remote Controller operation.
MCG (Multipurpose Clock Generator)
Provides clocking options for the device, including a phase-locked loop
(PLL) and frequency-locked loop (FLL) for multiplying slower reference
clock sources.
BDM (Background Debug Module)
Provides single pin debugging interface (part of the V1 ColdFire core).
CF1 CORE (V1 ColdFire Core)
Executes programs and interrupt handlers.
PRACMP
Analog comparators for comparing external analog signals against
each other, or a variety of reference levels.
COP (Computer Operating Properly)
Software Watchdog.
IRQ (Interrupt Request)
Single-pin high-priority interrupt (part of the V1 ColdFire core).
CRC (Cyclic Redundancy Check)
High-speed CRC calculation.
DBG (Debug)
Provides debugging and emulation capabilities (part of the V1 ColdFire.
core)
FLASH (Flash Memory)
Provides storage for program code, constants, and variables.
IIC (Inter-integrated Circuits)
Supports standard IIC communications protocol and SMBus.
INTC (Interrupt Controller)
Controls and prioritizes all device interrupts.
KBI1 & KBI2
Keyboard Interfaces 1 and 2.
LVD (Low-voltage Detect)
Provides an interrupt to theColdFire V1 CORE in the event that the
supply voltage drops below a critical value. The LVD can also be
programmed to reset the device upon a low voltage event.
VREF (Voltage Reference)
The Voltage Reference output is available for both on- and off-chip use.
MCF51MM256 Series Devices Reference Manual, Rev. 3
1-4
Freescale Semiconductor
Device Overview
Table 1-3. MCF51MM256/128 Functional Units (Continued)
Unit
Function
RAM (Random-Access Memory)
Provides stack and variable storage.
RGPIO (Rapid General-purpose
Input/output)
Allows for I/O port access at CPU clock speeds. RGPIO is used to
implement GPIO functionality.
SCI1, SCI2 (Serial Communications
Interfaces)
Serial communications UARTs capable of supporting RS-232 and LIN
protocols.
SIM (system integration unit)
SPI1 (FIFO), SPI2 (Serial Peripheral
Interfaces)
SPI1 and SPI2 provide standard master/slave capability. SPI contains
a FIFO buffer in order to increase the throughput for this peripheral.
TPM1, TPM2 (Timer/PWM Module)
Timer/PWM module can be used for a variety of generic timer
operations as well as pulse-width modulation.
VREG (Voltage Regulator)
Controls power management across the device.
XOSC1 and XOSC2 (Crystal Oscillators) These devices incorporate redundant crystal oscillators. One is
intended primarily for use by the TOD, and the other by the CPU and
other peripherals.
1.2.2
Functional Versions
Table 1-4 provides the functional version of the on-chip modules.
Table 1-4. Versions of On-Chip Modules
Module1
Version
Analog-to-Digital Converter (ADC16)
1
General Purpose Operational Amplifier (OPAMP)
1
Trans-Impedance Operational Amplifier (TRIAMP)
1
Digital to Analog Converter (DAC)
1
Programmable Delay Block (PDB)
1
Central Processing Unit — ColdFire V1 (CPU)
2
Inter-Integrated Circuit (IIC)
3
Multi-Purpose Clock Generator (MCG)
3
Low-Power Oscillator (XOSCVLP)
1
Carrier Modulator Timer (CMT)
1
Mini-FlexBus
1
On-Chip In-Circuit Debug/Emulator - ColdFire V1 (DBG)
1
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
1-5
Device Overview
Table 1-4. Versions of On-Chip Modules (Continued)
Module1
Programable Analog Comparator (PRACMP)
1
Serial Communications Interface (SCI)
4
Serial Peripheral Interface (SPI)
5
Time-of-Day (TOD)
1
USB On-the-Go (USBOTG)
1
Timer Pulse-Width Modulator (TPM)
3
System Integration Module (SIM)
1
Cyclic Redundancy Check
3
Keyboard Interrupt
2
Voltage Reference (VREF)
1
Voltage Regulator (VREG)
1
Interrupt Request (IRQ)
3
Flash Wrapper
1
GPIO
0
Port Control
1
1Shaded
1.3
Version
Modules comprise the measurement engine.
V1 ColdFire Core
The MCF51MM256/128 devices contain a version of the V1 ColdFire platform that is optimized for area
and low power. The CPU implements ColdFire instruction set architecture revision C (ISA_C) with added
capabilities:
• Hardware MAC support for 16X16 32 and 32X32  32 bit multiply-accumulate operations
(32-bit accumulator)
• Upward compatibility with all other ColdFire cores (V2–V5)
An integrated multi-master crossbar switch on the ColdFire system busses provides access to system
resources by the CPU.
For more details on the V1 ColdFire core, see Chapter 7, “ColdFire Core.”
A simplified block diagram of the V1 core including the processor and debug module is shown in
Figure 1-2.
MCF51MM256 Series Devices Reference Manual, Rev. 3
1-6
Freescale Semiconductor
Device Overview
RPP_mm256
cf1_core
IFP
External
IA Generation
IAG
AHB
Master
(USB)
Instruction
Fetch Cycle
IC
m1
m0
FIFO
Instruction
Buffer
IB
AHB
Address
Attributes
Crossbar
Lite
Switch
2X3
AHB
Read
Data
OEP
Decode & Select,
Operand Fetch
DSOC
AGEX
s1
Address
Generation,
Execute
MAC
s3
s0
AHB
Write
Data
Debug
Local
Bus Ctlr
Port
Splitter
IPS
Bridge
MiniFlexBus
PRAM
Controller
RGPIO
Controller
Port
Splitter
PROM
Controller
PFLASH
Controller
32
8
External
IPS Bus
32
Off-Platform
IPS Bus
External
Bus
Off-Platform
RAM Array
16
RGPIO
Pins
Off-Platform
ROM Array
32
Off-Platform
Flash Array
Figure 1-2. Simplified CF1Core and Low-Cost Platform Block Diagram
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
1-7
Device Overview
Table 1-5. Acronyms used in Figure 1-2
1.3.1
Acronym
Meaning
IFP
Instruction Fetch Pipeline
OEP
Operand Fetch Pipeline
PST/DDATA
Processor Status / Debug Data
BDC
Background Debug Controller
BDM
Background Debug Module
RTD
Real Time Debug
AXBS
Amba-AHB Crossbar Switch
INTC
Interrupt Controller
IPS
IP Skyblue Bus Controller
User Programming Model
Table 1-6 illustrates the integer portion of the user programming model. It consists of the following
registers:
• 16 general-purpose 32-bit registers (D0–D7, A0–A7)
• 32-bit program counter (PC)
• 8-bit condition code register (CCR)
1.3.2
Supervisor Programming Model
System programmers use the supervisor programming model to implement operating system functions.
All accesses that affect the control features of ColdFire processors must be made in supervisor mode and
can be accessed only by privileged instructions. The supervisor programming model consists of the
registers available in user mode as well as the registers listed in Table 1-6.
Table 1-6. Version 1 ColdFire CPU Programming Model
Width
(bits)
Register
Reset Value
Supervisor/User Registers
Data Register 0 (D0)
32
0xCF1*_**29
Data Register 1 (D1)
32
0x010*0_10*0
Data Register 2–7 (D2–D7)
32
Undefined
Address Register 0–6 (A0–A6)
32
Undefined
Supervisor/User A7 Stack Pointer (A7)
32
Undefined
Program Counter (PC)
32
Contents of memory at
0x00_0004
Condition Code Register (CCR)
8
Undefined
MCF51MM256 Series Devices Reference Manual, Rev. 3
1-8
Freescale Semiconductor
Device Overview
Table 1-6. Version 1 ColdFire CPU Programming Model (Continued)
Width
(bits)
Register
Reset Value
Supervisor Registers
1.4
Status Register (SR)
16
0x27--
User/Supervisor A7 Stack Pointer (OTHER_A7)
32
Contents of memory at
0x00_0000
Vector Base Register (VBR)
32
0x0000_0000
CPU Configuration Register (CPUCR)
32
0x0000_0000
System Clocks
This section discusses on-chip clock generation and distribution for the MCF51MM256 series devices.
1.4.1
System Clock Distribution
Figure 1-3 shows how clocks from the MCG and XOSCx are distributed to the microcontroller’s other
functional units. Some modules in the microcontroller have selectable clock inputs. All memory-mapped
registers associated with the modules (except RGPIO) are clocked with BUSCLK. The RGPIO registers
are clocked with the CPU clock (MCGOUT).
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
1-9
EXTAL1
XTAL1
EXTAL2
XTAL2
Device Overview
TOD
Clock Check
& Select
XOSC2
XOSC1
OSCOUT2
OSCOUT1
MCGIRCLK
TPMCLK
1 kHz
LPO
LPOCLK
COP
TPM1
TPM2
DAC
CMT
VREG
FSPI1
SPI2
KBIx &
GPIO
SCI1
SCI2
oscillator control
div 3
MCGERCLK
MCGFFCLK
MCG
MCGOUT
2
2
FFCLK*
SYNC*
BUSCLK
MCGPLLSCLK
MCGLCLK
CPU
DBG
RGPIO
RAM &
ROM
BDC
USB_FS
Interrupt
Controller
ADC
MiniFlexBus
PDB
FLASH
IIC
PRACMP
TRIAMP &
OPAMP
USB_ALTCLK
Note: The ADC has minimum and maximum frequency requirements. See the ADC chapter and the MCF51MM256 series Data Sheet.
Flash memory has frequency requirements for program and erase operations. Each ADC also has it’s own internal asynchronous clock
source, which is not shown above.
* The fixed frequency clock (FFCLK) is internally synchronized to the bus clock (BUSCLK) and must not exceed one half of the bus clock
frequency.
Figure 1-3. System Clock Distribution Diagram
MCF51MM256 Series Devices Reference Manual, Rev. 3
1-10
Freescale Semiconductor
Device Overview
1.4.2
System Clocks
Table 1-7 describes each of the system clocks.
Table 1-7. System Clocks
Clock
Description
MCGOUT
This clock source is used as the CPU clock and is divided by two to generate the peripheral bus
clock. Control bits in the MCG control registers determine which of three clock sources is connected:
• Internal reference clock
• External reference clock
• Frequency-locked loop (FLL) or phase-locked loop (PLL) output
This clock drives the CPU, debug, RAM, and BDM directly and is divided by two to clock all
peripherals (BUSCLK).
See Chapter 17, “Multipurpose Clock Generator (S08MCGV3),” for details on configuring the
MCGOUT clock.
MCGLCLK
This clock source is derived from the digitally controlled oscillator (DCO) of the MCG. Development
tools can select this internal self-clocked source to speed up BDC communications in systems
where the bus clock is slow.
MCGERCLK
MCG External Reference Clock—This is the external reference clock and can be selected as the
alternate clock for the ADC.
MCGIRCLK
MCG Internal Reference Clock—This is the internal reference clock and can be selected as the
TOD clock source.
MCGFFCLK
MCG Fixed-Frequency Clock—This clock is divided by 2 to generate the fixed frequency clock
(FFCLK) after being synchronized to the bus clock. It can be selected as clock source for the TPM
modules. The frequency of the FFCLK is determined by the settings of the MCG.
LPOCLK
Low-Power Oscillator Clock—This clock is generated from an internal low-power oscillator that is
completely independent of the MCG module. The LPOCLK can be selected as the clock source to
the TOD or COP.
TPMCLK
TPM Clock—An optional external clock source for the TPMs. This clock must be limited to
one-quarter the frequency of the bus clock for synchronization.
MCGPLLSCLK
This clock has a direct connection to the PLL output clock (running at 48 MHz) and thus allows the
user to have the flexibility to run the MCGOUT at lower frequencies to conserve power.
ADACK (not
shown)
The ADC module also has an internally generated asynchronous clock that allows it to run in STOP
mode (ADACK). This signal is not available externally.
OSCOUT1
Low-power crystal oscillator output that can be used as the reference clock to the MCG or the TOD.
OSCOUT2
Low-power crystal oscillator output that can be used as the reference clock to the MCG.
1.4.3
Clock Gating
To save power, peripheral clocks can be shut off by programming the system clock gating registers. For
details, refer to Section 5.7.7, “System Clock Gating Control 1 Register (SCGC1)”.
1.4.4
MCG Modes of Operation
The MCG operates in one of the modes described in Table 1-8.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
1-11
Device Overview
Table 1-8. MCG Modes
Related field values1
Mode
Description
FLL Engaged Internal (FEI)
• MCGC1[IREFS] = 1
• MCGC1[CLKS] = 00
• MCGC3[PLLS] = 0
Default. The MCG supplies a clock derived from one of the
on-chip FLLs, which is sourced by the internal reference
clock. Upon exiting reset, the default FLL is that which
generates the x MHz bus / y MHz CPU clocks.
FLL Engaged External (FEE)
• MCGC1[IREFS] = 0
• MCGC1[CLKS] = 00
• MCGC3[PLLS] = 0
The MCG supplies a clock derived from the FLL, which is
sourced from an external reference clock (or crystal
oscillator).
FLL Bypassed Internal (FBI)
•
•
•
•
MCGC1[IREFS] = 1
The FLL is enabled and sourced by the internal reference
MCGC1[CLKS] = 01
clock but is bypassed. The MCGOUT clock is derived from
MCGC3[PLLS] = 0
the internal reference clock.
XCSM[ENBDM] = 1 or
MCGC2[LP] = 0
FLL Bypassed External (FBE)
•
•
•
•
MCGC1[IREFS] = 0
MCGC1[CLKS] = 10
MCGC3[PLLS] = 0
XCSM[ENBDM] = 1 or
MCGC2[LP] = 0
PLL Engaged External (PEE)
• MCGC1[IREFS] = 0
• MCGC1[CLKS] = 00
• MCGC3[PLLS] = 1
The MCG supplies a clock derived from the PLL, which is
sourced from an external reference clock (or crystal
oscillator).
PLL Bypassed External (PBE)
•
•
•
•
The MCG supplies a clock MCGOUT derived from the
external reference clock (or crystal oscillator). The PLL is
also sourced from the external clock source but is
bypassed.
Bypassed Low Power Internal (BLPI)
• MCGC1[IREFS] = 1
• MCGC1[CLKS] = 01
• XCSM[ENBDM] = 0
and MCGC2[LP] = 1
The FLL and PLL are disabled and bypassed, and the MCG
supplies MCGOUT derived from the internal reference
clock.
Bypassed Low Power External (BLPE) • MCGC1[IREFS] = 0
• MCGC1[CLKS] = 10
• XCSM[ENBDM] = 0
and MCGC2[LP] = 1
The FLL and PLL are disabled and bypassed, and the MCG
supplies MCGOUT derived from the external reference
clock.
STOP
The FLL and PLL are disabled, and the internal or external
reference clocks can be selected to be enabled or disabled.
The microcontroller does not provide a microcontroller
clock source unless BDC[ENBDM] is enabled.
MCGC1[IREFS] = 0
MCGC1[CLKS] = 10
MCGC3[PLLS] = 1
XCSM[ENBDM] = 1 or
MCGC2[LP] = 0
—
1
The FLL is enabled and controlled by an external reference
clock but is bypassed. The MCGOUT clock is derived from
the external reference clock. The external reference clock
can be an external crystal/resonator supplied by an XOSC1
or XOSC2 controlled by the MCG, or it can be another
external clock source.
For descriptions of the MCGC1, MCGC2, and MCGC3 registers, see Chapter 17, “Multipurpose Clock Generator
(S08MCGV3)”. For a description of the XCSM register, see Chapter 29, “Version 1 ColdFire Debug (CF1_DEBUG)”.
1.4.5
MCG Mode State Diagram
Figure 1-4 shows the valid state transitions for the MCG.
MCF51MM256 Series Devices Reference Manual, Rev. 3
1-12
Freescale Semiconductor
Device Overview
The IREFS and CLKS fields are contained within the MCG module definition. The LP bit is part of the
on-chip power management controller (PMC) block.
The clock source for the BDC is controlled by the BDC clksw bit. Choices for the BDC clock are
MCGOUT and the output from DCO.
IREFS = 1
CLKS = 00
PLLS = 0
FLL Engaged
Internal (FEI)
FLL Engaged
External (FEE)
IREFS = 1
CLKS = 01
PLLS = 0
IREFS = 0
CLKS = 10
PLLS = 0
BDM Enabled
or LP = 0
IREFS = 1
CLKS = 01
BDM Disabled
and LP = 1
IREFS = 0
CLKS = 00
PLLS = 0
FLL Bypassed
Internal (FBI)
FLL Bypassed
External (FBE)
BDM Enabled
or LP=0
Bypassed
IREFS = 0
Low Power
CLKS = 10
External (BLPE) BDM Disabled
Bypassed
Low Power
Internal (BLPI)
and LP = 1
PLL Bypassed
External (PBE)
IREFS = 0
CLKS = 10
PLLS = 1
BDM Enabled
or LP = 0
PLL Engaged
External (PEE)
Entered from any state
when MCU enters stop
Stop
IREFS = 0
CLKS = 00
PLLS = 1
Returns to state that was active
before MCU entered stop, unless
RESET occurs while in stop.
Figure 1-4. MCG Mode State Diagram
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
1-13
Device Overview
MCF51MM256 Series Devices Reference Manual, Rev. 3
1-14
Freescale Semiconductor
Chapter 2
Pins and Connections
This section describes signals that connect to package pins. It includes pinout diagrams, recommended
system connections, and detailed discussions of signals.
2.1
Device Pin Assignments
The following figures depict the various device pin assignments.
2.2
104-Pin MAPBGA
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
2-1
Pins and Connections
The following figure shows the 104-pin MAPBGA pinout configuration.
1
2
3
4
5
6
7
8
9
10
11
A
PTF6
PTF7
USB_DP
USB_DM
VUSB33
PTF4
PTF3
FB_AD12
PTJ7
PTJ5
PTJ4
A
B
PTG0
PTA0
PTG3
VBUS
PTF5
PTJ6
PTH0
PTE5
PTF0
PTF1
PTF2
B
C
IRO
PTG4
PTA6
PTG2
PTG6
PTG5
PTG7
PTH1
PTE4
PTE6
PTE7
C
D
PTA5
PTA4
PTB1
VDD1
VDD3
PTA1
PTE3
PTE2
D
E
VSSA
PTA7
PTB0
PTA2
PTJ3
PTE1
E
F
VREFL
INP1-
INP2-
PTJ2
PTJ0
PTJ1
F
TRIOUT1
OUT1
OUT2
PTD5
PTD7
PTE0
G
VINP1
VINN1
PTA3
VSS1
VSS3
PTD4
PTD3
PTD2
H
J
DADP0
DADM0
PTH7
PTH6
PTH4
PTH3
PTH2
PTD6
PTC2
PTC0
PTC1
J
K
VINP2
VINN2
DADP1
PTH5
PTB6
PTB7
PTC3
PTD1
PTC4
PTC5
PTC6
K
L
TRIOUT2
DACO
DADM1
VREFO
VREFH
VDDA
PTB3
PTB2
PTD0
PTB5
PTB4
L
1
2
3
4
5
6
7
8
9
10
11
G
H
VDD2
PTG1
PTC7
VSS2
Figure 2-1. 104-Pin MAPBGA
MCF51MM256 Series Devices Reference Manual, Rev. 3
2-2
Freescale Semiconductor
Pins and Connections
2.3
100-Pin LQFP
PTA0/FB_D2/SS1
IRO
PTG5/FB_RW
PTG6/FB_AD19
PTG7/FB_AD18
PTH0/FB_OE
PTH1/FB_D0
PTA1/KBI1P0/TX1/FB_D1
PTA2/KBI1P1/RX1/ADP4
PTA3/KBI1P2/FB_D6/ADP5
PTA4/INP1+
PTA5
PTA6
PTA7/INP2+
PTB0
PTB1/BLMS
VSSA
VREFL
INP1OUT1
TRIOUT1/DADP2VINP1
VINN1/DADM2
INP2-
PTE7/USB_VBUSVLD/TPM2CH3
PTE6/FB_RW/USB_SESSEND/RX2
PTE5/FB_D7/USB_SESSVLD/TX2
VDD3
VSS3
PTF0/USB_ID/TPM2CH2
PTJ4/RGPIOP15/FB_AD16
PTF2/TX2/USB_DM_DOWN/TPM2CH0
PTF1/RX2/USB_DP_DOWN/TPM2CH1
PTF5/KBI2P7/FB_D3/FB_AD9
PTF4/SDA/FB_D4/FB_AD10
PTF3/SCL/FB_D5/FB_AD11
FB_AD12
PTJ7/FB_AD13
PTJ6/FB_AD14
PTJ5/FB_AD15
VSS1
VBUS
USB_DP
USB_DM
VUSB33
VDD1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 LQFP
PTE4/CMPP3/TPMCLK/IRQ
PTE3/KBI2P6/FB_AD8
PTE2/KBI2P5/RGPIOP14/FB_AD7
PTE1/KBI2P4/RGPIOP13/FB_AD6
PTJ3/RGPIOP12/FB_AD5
PTJ2/FB_AD4
PTJ1/FB_AD3
PTJ0/FB_AD2
PTE0/KBI2P3/FB_ALE/FB_CS1
PTD7/USB_PULLUP(D+)/RX1
PTD6/USB_ALTCLK/TX1
PTD5/SCL/RGPIOP11/TPM1CH3
PTD4/SDA/RGPIOP10/TPM1CH2
PTD3/USB_PULLUP(D+)/RGPIOP9/TPM1CH1
PTD2/USB_ALTCLK/RGPIOP8/TPM1CH0
PTD1/CMPP2/RESET
PTD0/BKGD/MS
PTC7/KBI2P2/CLKOUT/ADP11
PTC6/KBI2P1/PRACMPO/ADP10
PTC5/KBI2P0/CMPP1/ADP9
PTC4/KBI1P7/CMPP0/ADP8
PTC3/KBI1P6/SS2/ADP7
PTC2/KBI1P5/SPSCK2/ADP6
PTC1/MISO2/FB_D0/FB_AD1
PTC0/MOSI2/FB_OE/FB_CS0
PTH7/RGPIOP7/FB_D2
PTH6/RGPIOP6/FB_D3
PTH5/RGPIOP5/FB_D4
PTB5/XTAL2
PTB6/KBI1P3/RGPIOP0/FB_AD17
PTB7/KBI1P4/RGPIOP1/FB_AD0
PTH2/RGPIOP2/FB_D7
PTH3/RGPIOP3/FB_D6
PTH4/RGPIOP4/FB_D5
VDDA
VSS2
PTB2/EXTAL1
PTB3/XTAL1
VDD2
PTB4/EXTAL2
DADP0
DADM0
VREFO
DADP1
DADM1
VREFH
DACO
TRIOUT2/DADP3
VINP2
VINN2/DADM3
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
OUT2
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PTG0/SPSCK1
PTF7/MISO1
PTF6/MOSI1
The following figure shows the 100-pin LQFP pinout configuration.
Figure 2-2. 100-Pin LQFP
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
2-3
Pins and Connections
2.4
81-Pin MAPBGA
The following figure shows the 81-pin MAPBGA pinout configuration.
1
2
3
4
5
6
7
8
9
A
IRO
PTG0
PTF6
USB_DP
VBUS
VUSB33
PTF4
PTF3
PTE4
A
B
PTF7
PTA0
PTG1
USB_DM
PTF5
PTE7
PTF1
PTF0
PTE3
B
C
PTA4
PTA5
PTA6
PTA1
PTF2
PTE6
PTE5
PTE2
PTE1
C
D
INP1-
PTA7
PTB0
PTB1
PTA2
PTA3
PTD5
PTD7
PTE0
D
E
OUT1
VINN1
OUT2
VDD2
VDD3
VDD1
PTD2
PTD3
PTD6
E
F
VINP1
TRIOUT1
INP2-
VSS2
VSS3
VSS1
PTB7
PTC7
PTD4
F
G
DADP0
DACO
TRIOUT2
VINN2
VREFO
PTB6
PTC0
PTC1
PTC2
G
H
DADM0
DADM1
DADP1
VINP2
PTC3
PTC4
PTD0
PTC5
PTC6
H
J
VSSA
VREFL
VREFH
VDDA
PTB2
PTB3
PTD1
PTB4
PTB5
J
1
2
3
4
5
6
7
8
9
Figure 2-3. 81-Pin MAPBGA
MCF51MM256 Series Devices Reference Manual, Rev. 3
2-4
Freescale Semiconductor
Pins and Connections
2.5
80-Pin LQFP
PTB0
PTB1/BLMS
VSSA
VREFL
INP1OUT1
80-Pin LQFP
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PTE4/CMPP3/TPMCLK/IRQ
PTE3/KBI2P6/FB_AD8
PTE2/KBI2P5/RGPIOP14/FB_AD7
PTE1/KBI2P4/RGPIOP13/FB_AD6
PTE0/KBI2P3/FB_ALE/FB_CS1
PTD7/USB_PULLUP(D+)/RX1
PTD6/USB_ALTCLK/TX1
PTD5/SCL/RGPIOP11/TPM1CH3
PTD4/SDA/RGPIOP10/TPM1CH2
PTD3/USB_PULLUP(D+)/RGPIOP9/TPM1CH1
PTD2/USB_ALTCLK/RGPIOP8/TPM1CH0
PTD1/CMPP2/RESET
PTD0/BKGD/MS
PTC7/KBI2P2/CLKOUT/ADP11
PTC6/KBI2P1/PRACMPO/ADP10
PTC5/KBI2P0/CMPP1/ADP9
PTC4/KBI1P7/CMPP0/ADP8
PTC3/KBI1P6/SS2/ADP7
PTC2/KBI1P5/SPSCK2/ADP6
PTC1/MISO2/FB_D0/FB_AD1
DACO
TRIOUT2/DADP3
VINP2
VINN2/DADM3
DADP0
DADM0
VREFO
DADP1
DADM1
VREFH
VDDA
VSS2
PTB2/EXTAL1
PTB3/XTAL1
VDD2
PTB4/EXTAL2
PTB5/XTAL2
PTB6/KBI1P3/RGPIOP0/FB_AD17
PTB7/KBI1P4/RGPIOP1/FB_AD0
PTC0/MOSI2/FB_OE/FB_CS0
TRIOUT1/DADP2VINP1
VINN1DADM2
INP2OUT2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
PTA0/FB_D2/SS1
IRO
PTA1/KBI1P0/TX1/FB_D1
PTA2/KBI1P1/RX1/ADP4
PTA3/KBI1P2/FB_D6/ADP5
PTA4/INP1+
PTA5
PTA6
PTA7/INP2+
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PTG0/SPSCK1
PTF7/MISO1
PTF6/MOSI1
VDD1
VSS1
VBUS
USB_DP
USB_DM
VUSB33
PTF5/KBI2P7/FB_D3/FB_AD9
PTF4/SDA/FB_D4/FB_AD10
PTF3/SCL/FB_D5/FB_AD11
PTF2/TX2/USB_DM_DOWN/TPM2CH0
PTF1/RX2/USB_DP_DOWN/TPM2CH1
PTF0/USB_ID/TPM2CH2
PTE7/USB_VBUSVLD/TPM2CH3
PTE6/FB_RW/USB_SESSEND/RX2
PTE5/FB_D7/USB_SESSVLD/TX2
VDD3
VSS3
The following figure shows the 80-pin LQFP pinout configuration.
Figure 2-4. 80-Pin LQFP
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
2-5
Pins and Connections
2.6
Pin Assignments
MCF51MM256/128 uses the HCS08 style of pin muxing to be Flexis-compatible. The pin defaults as
GPIO and the alternate functions follow a priority where ALT3 has the highest priority. The following
table shows the package pin assignments.
Table 2-1. Package Pin Assignments
104 MAPBGA
100 LQFP
81 MAPBGA
80 LQFP
Package
Default
Function
B2
1
B2
1
PTA0
FB_D2
SS1
—
PTA0/FB_D2/SS1
C1
2
A1
2
IRO
—
—
—
IRO
C6
3
—
—
PTG5
FB_RW
—
—
PTG5/FB_RW
C5
4
—
—
PTG6
FB_AD19
—
—
PTG6/FB_AD19
C7
5
—
—
PTG7
FB_AD18
—
—
PTG7/FB_AD18
B7
6
—
—
PTH0
FB_OE
—
—
PTH0/FB_OE
C8
7
—
—
PTH1
FB_D0
—
—
PTH1/FB_D0
D9
8
C4
3
PTA1
KBI1P0
TX1
FB_D1
PTA1/KBI1P0/TX1/FB_D1
E9
9
D5
4
PTA2
KBI1P1
RX1
ADP4
PTA2/KBI1P1/RX1/ADP4
H3
10
D6
5
PTA3
KBI1P2
FB_D6
ADP5
PTA3/KBI1P2/FB_D6/ADP5
D2
11
C1
6
PTA4
INP1+
—
—
PTA4/INP1+
D1
12
C2
7
PTA5
—
—
—
PTA5
C3
13
C3
8
PTA6
—
—
—
PTA6
E2
14
D2
9
PTA7
INP2+
—
—
PTA7/INP2+
E3
15
D3
10
PTB0
—
—
—
PTB0
D3
16
D4
11
PTB1
BLMS
—
—
PTB1/BLMS
E1
17
J1
12
VSSA
—
—
—
VSSA
F1
18
J2
13
VREFL
—
—
—
VREFL
F2
19
D1
14
INP1-
—
—
—
INP1-
G2
20
E1
15
OUT1
—
—
—
OUT1
G1
21
F2
16
DADP2
TRIOUT1
—
—
DADP2/TRIOUT1
H1
22
F1
17
VINP1
—
—
—
VINP1
H2
23
E2
18
DADM2
VINN1
—
—
DADM2/VINN1
F3
24
F3
19
INP2-
—
—
—
INP2-
G3
25
E3
20
OUT2
—
—
—
OUT2
Alternate
1
Alternate
2
Alternate
3
Composite Pin Name
MCF51MM256 Series Devices Reference Manual, Rev. 3
2-6
Freescale Semiconductor
Pins and Connections
Table 2-1. Package Pin Assignments
104 MAPBGA
100 LQFP
81 MAPBGA
80 LQFP
Package
Default
Function
L2
26
G2
21
DACO
—
—
—
DACO
L1
27
G3
22
DADP3
TRIOUT2
—
—
DADP3/TRIOUT2
K1
28
H4
23
VINP2
—
—
—
VINP2
K2
29
G4
24
DADM3
VINN2
—
—
DADM3/VINN2
J1
30
G1
25
DADP0
—
—
—
DADP0
J2
31
H1
26
DADM0
—
—
—
DADM0
L4
32
G5
27
VREFO
—
—
—
VREFO
K3
33
H3
28
DADP1
—
—
—
DADP1
L3
34
H2
29
DADM1
—
—
—
DADM1
L5
35
J3
30
VREFH
—
—
—
VREFH
L6
36
J4
31
VDDA
—
—
—
VDDA
H6
37
F4
32
VSS2
—
—
—
VSS2
L8
38
J5
33
PTB2
EXTAL1
—
—
PTB2/EXTAL1
L7
39
J6
34
PTB3
XTAL1
—
—
PTB3/XTAL1
D6
40
E4
35
VDD2
—
—
—
VDD2
L11
41
J8
36
PTB4
EXTAL2
—
—
PTB4/EXTAL2
L10
42
J9
37
PTB5
XTAL2
—
—
PTB5/XTAL2
K5
43
G6
38
PTB6
KBI1P3
RGPIOP0
FB_AD17
PTB6/KBI1P3/RGPIOP0/FB_AD17
K6
44
F7
39
PTB7
KBI1P4
RGPIOP1
FB_AD0
PTB7/KBI1P4/RGPIOP1/FB_AD0
J7
45
—
—
PTH2
RGPIOP2
FB_D7
—
PTH2/RGPIOP2/FB_D7
J6
46
—
—
PTH3
RGPIOP3
FB_D6
—
PTH3/RGPIOP3/FB_D6
J5
47
—
—
PTH4
RGPIOP4
FB_D5
—
PTH4/RGPIOP4/FB_D5
K4
48
—
—
PTH5
RGPIOP5
FB_D4
—
PTH5/RGPIOP5/FB_D4
J4
49
—
—
PTH6
RGPIOP6
FB_D3
—
PTH6/RGPIOP6/FB_D3
J3
50
—
—
PTH7
RGPIOP7
FB_D2
—
PTH7/RGPIOP7/FB_D2
J10
51
G7
40
PTC0
MOSI2
FB_OE
FB_CS0
PTC0/MOSI2/FB_OE/FB_CS0
J11
52
G8
41
PTC1
MISO2
FB_D0
FB_AD1
PTC1/MISO2/FB_D0/FB_AD1
J9
53
G9
42
PTC2
KBI1P5
SPSCK2
ADP6
PTC2/KBI1P5/SPSCK2/ADP6
K7
54
H5
43
PTC3
KBI1P6
SS2
ADP7
PTC3/KBI1P6/SS2/ADP7
Alternate
1
Alternate
2
Alternate
3
Composite Pin Name
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
2-7
Pins and Connections
Table 2-1. Package Pin Assignments
104 MAPBGA
100 LQFP
81 MAPBGA
80 LQFP
Package
Default
Function
K9
55
H6
44
PTC4
KBI1P7
CMPP0
ADP8
PTC4/KBI1P7/CMPP0/ADP8
K10
56
H8
45
PTC5
KBI2P0
CMPP1
ADP9
PTC5/KBI2P0/CMPP1/ADP9
K11
57
H9
46
PTC6
KBI2P1
PRACMPO
ADP10
PTC6/KBI2P1/PRACMPO/ADP10
F8
58
F8
47
PTC7
KBI2P2
CLKOUT
ADP11
PTC7/KBI2P2/CLKOUT/ADP11
L9
59
H7
48
PTD0
BKGD
MS
—
PTD0/BKGD/MS
K8
60
J7
49
PTD1
CMPP2
RESET
—
PTD1/CMPP2/RESET
H11
61
E7
50
PTD2
USB_ALTCLK
RGPIOP8
TPM1CH0
PTD2/USB_ALTCLK/RGPIOP8/TPM1CH0
H10
62
E8
51
PTD3
USB_PULLUP
(D+)
RGPIOP9
TPM1CH1 PTD3/USB_PULLUP(D+)/RGPIOP9/TPM1CH1
H9
63
F9
52
PTD4
SDA
RGPIOP10 TPM1CH2
PTD4/SDA/RGPIOP10/TPM1CH2
G9
64
D7
53
PTD5
SCL
RGPIOP11 TPM1CH3
PTD5/SCL/RGPIOP11/TPM1CH3
J8
65
E9
54
PTD6
USB_ALTCLK
TX1
—
PTD6/USB_ALTCLK/TX1
G10
66
D8
55
PTD7
USB_PULLUP
(D+)
RX1
—
PTD7/USB_PULLUP(D+) /RX1
G11
67
D9
56
PTE0
KBI2P3
FB_ALE
FB_CS1
PTE0/KBI2P3/FB_ALE/FB_CS1
F10
68
—
—
PTJ0
FB_AD2
—
—
PTJ0/FB_AD2
F11
69
—
—
PTJ1
FB_AD3
—
—
PTJ1/FB_AD3
F9
70
—
—
PTJ2
FB_AD4
—
—
PTJ2/FB_AD4
E10
71
—
—
PTJ3
RGPIOP12
FB_AD5
—
PTJ3/RGPIOP12/FB_AD5
E11
72
C9
57
PTE1
KBI2P4
RGPIOP13
FB_AD6
PTE1/KBI2P4/RGPIOP13/FB_AD6
D11
73
C8
58
PTE2
KBI2P5
RGPIOP14
FB_AD7
PTE2/KBI2P5/RGPIOP14/FB_AD7
D10
74
B9
59
PTE3
KBI2P6
FB_AD8
—
PTE3/KBI2P6/FB_AD8
C9
75
A9
60
PTE4
CMPP3
TPMCLK
IRQ
PTE4/CMPP3/TPMCLK/IRQ
H8
76
F5
61
VSS3
—
—
—
VSS3
D8
77
E5
62
VDD3
—
—
—
VDD3
B8
78
C7
63
PTE5
FB_D7
USB_
SESSVLD
TX2
PTE5/FB_D7/USB_SESSVLD/TX2
C10
79
C6
64
PTE6
FB_RW
USB_
SESSEND
RX2
PTE6/FB_RW/USB_SESSEND/RX2
C11
80
B6
65
PTE7
USB_
VBUSVLD
TPM2CH3
—
PTE7/USB_VBUSVLD/TPM2CH3
Alternate
1
Alternate
2
Alternate
3
Composite Pin Name
MCF51MM256 Series Devices Reference Manual, Rev. 3
2-8
Freescale Semiconductor
Pins and Connections
Table 2-1. Package Pin Assignments
104 MAPBGA
100 LQFP
81 MAPBGA
80 LQFP
Package
Default
Function
B9
81
B8
66
PTF0
USB_ID
B10
82
B7
67
PTF1
RX2
USB_DP_ TPM2CH1
DOWN
PTF1/RX2/USB_DP_DOWN/TPM2CH1
B11
83
C5
68
PTF2
TX2
USB_DM_ TPM2CH0
DOWN
PTF2/TX2/USB_DM_DOWN/TPM2CH0
A11
84
—
—
PTJ4
RGPIOP15
FB_AD16
—
PTJ4/RGPIOP15/FB_AD16
A10
85
—
—
PTJ5
FB_AD15
—
—
PTJ5/FB_AD15
B6
86
—
—
PTJ6
FB_AD14
—
—
PTJ6/FB_AD14
A9
87
—
—
PTJ7
FB_AD13
—
—
PTJ7/FB_AD13
A8
88
—
—
FB_AD12
—
—
—
FB_AD12
A7
89
A8
69
PTF3
SCL
FB_D5
FB_AD11
PTF3/SCL/FB_D5/FB_AD11
A6
90
A7
70
PTF4
SDA
FB_D4
FB_AD10
PTF4/SDA/FB_D4/FB_AD10
B5
91
B5
71
PTF5
KBI2P7
FB_D3
FB_AD9
PTF5/KBI2P7/FB_D3/FB_AD9
A5
92
A6
72
VUSB33
—
—
—
VUSB33
A4
93
B4
73
USB_DM
—
—
—
USB_DM
A3
94
A4
74
USB_DP
—
—
—
USB_DP
B4
95
A5
75
VBUS
—
—
—
VBUS
H4
96
F6
76
VSS1
—
—
—
VSS1
D4
97
E6
77
VDD1
—
—
—
VDD1
A1
98
A3
78
PTF6
MOSI1
—
—
PTF6/MOSI1
A2
99
B1
79
PTF7
MISO1
—
—
PTF7/MISO1
B1
100
A2
80
PTG0
SPSCK1
—
—
PTG0/SPSCK1
F4
—
A1
—
PTG1
USB_
SESSEND
—
—
PTG1/USB_SESSEND
C4
—
—
—
PTG2
USB_DM_
DOWN
—
—
PTG2/USB_DM_DOWN
B3
—
—
—
PTG3
USB_DP_
DOWN
—
—
PTG3/USB_DP_DOWN
C2
—
—
—
PTG4
USB_SESSVLD
—
—
PTG4/USB_SESSVLD
Alternate
1
Alternate
2
Alternate
3
Composite Pin Name
TPM2CH2
—
PTF0/USB_ID/TPM2CH2
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
2-9
Pins and Connections
Drive strength, pullup enable1, slew rate and input filter settings in the GPIO apply to any digital use of
the associated pin.
2.6.1
Pinout Summary
The following tables identify pin options on a peripheral-by-peripheral basis.
Table 2-2. RGPIO Pinout Summary
104
MAPBGA
100
LQFP
81
MAPBGA
80
LQFP
Default
Function
Composite Pin Name
RGPIO
K5
43
G6
38
PTB6
PTB6/KBI1P3/RGPIOP0/FB_AD17
RGPIOP0
K6
44
F7
39
PTB7
PTB7/KBI1P4/RGPIOP1/FB_AD0
RGPIOP1
H9
63
F9
52
PTD4
PTD4/SDA/RGPIOP10/TPM1CH2
RGPIOP10
G9
64
D7
53
PTD5
PTD5/SCL/RGPIOP11/TPM1CH3
RGPIOP11
E10
71
—
—
PTJ3
PTJ3/RGPIOP12/FB_AD5
RGPIOP12
E11
72
C9
57
PTE1
PTE1/KBI2P4/RGPIOP13/FB_AD6
RGPIOP13
D11
73
C8
58
PTE2
PTE2/KBI2P5/RGPIOP14/FB_AD7
RGPIOP14
A11
84
—
—
PTJ4
PTJ4/RGPIOP15/FB_AD16
RGPIOP15
J7
45
—
—
PTH2
PTH2/RGPIOP2/FB_D7
RGPIOP2
J6
46
—
—
PTH3
PTH3/RGPIOP3/FB_D6
RGPIOP3
J5
47
—
—
PTH4
PTH4/RGPIOP4/FB_D5
RGPIOP4
K4
48
—
—
PTH5
PTH5/RGPIOP5/FB_D4
RGPIOP5
J4
49
—
—
PTH6
PTH6/RGPIOP6/FB_D3
RGPIOP6
J3
50
—
—
PTH7
PTH7/RGPIOP7/FB_D2
RGPIOP7
H11
61
E7
50
PTD2
PTD2/USB_ALTCLK/RGPIOP8/
TPM1CH0
RGPIOP8
H10
62
E8
51
PTD3
PTD3/USB_PULLUP(D+)/RGPIOP9/
TPM1CH1
RGPIOP9
Table 2-3. PTA Pinout Summary
104
MAPBGA
100
LQFP
81
MAPBGA
80
LQFP
Default
Function
Composite Pin Name
PTA
B2
1
B2
1
PTA0
PTA0/FB_D2/SS1
PTA0
D9
8
C4
3
PTA1
PTA1/KBI1P0/TX1/FB_D1
PTA1
E9
9
D5
4
PTA2
PTA2/KBI1P1/RX1/ADP4
PTA2
1. There is one special case with regard to pullup enable functions. PTE4 can be programmed to operate as IRQ. When in that
mode, the pullup enable is controlled via IRQSC[IRQPDD].
MCF51MM256 Series Devices Reference Manual, Rev. 3
2-10
Freescale Semiconductor
Pins and Connections
Table 2-3. PTA Pinout Summary (Continued)
104
MAPBGA
100
LQFP
81
MAPBGA
80
LQFP
Default
Function
Composite Pin Name
PTA
H3
10
D6
5
PTA3
PTA3/KBI1P2/FB_D6/ADP5
PTA3
D2
11
C1
6
PTA4
PTA4/INP1+
PTA4
D1
12
C2
7
PTA5
PTA5
PTA5
C3
13
C3
8
PTA6
PTA6
PTA6
E2
14
D2
9
PTA7
PTA7/INP2+
PTA7
Table 2-4. PTB Pinout Summary
104
MAPBGA
100
LQFP
81
MAPBGA
80
LQFP
Default
Function
Composite Pin Name
PTB
E3
15
D3
10
PTB0
PTB0
PTB0
D3
16
D4
11
PTB1
PTB1/BLMS
PTB1
L8
38
J5
33
PTB2
PTB2/EXTAL1
PTB2
L7
39
J6
34
PTB3
PTB3/XTAL1
PTB3
L11
41
J8
36
PTB4
PTB4/EXTAL2
PTB4
L10
42
J9
37
PTB5
PTB5/XTAL2
PTB5
K5
43
G6
38
PTB6
PTB6/KBI1P3/RGPIOP0/FB_AD17
PTB6
K6
44
F7
39
PTB7
PTB7/KBI1P4/RGPIOP1/FB_AD0
PTB7
Table 2-5. PTC Pinout Summary
104
MAPBGA
100
LQFP
81
MAPBGA
80
LQFP
Default
Function
Composite Pin Name
PTC
J10
51
G7
40
PTC0
PTC0/MOSI2/FB_OE/FB_CS0
PTC0
J11
52
G8
41
PTC1
PTC1/MISO2/FB_D0/FB_AD1
PTC1
J9
53
G9
42
PTC2
PTC2/KBI1P5/SPSCK2/ADP6
PTC2
K7
54
H5
43
PTC3
PTC3/KBI1P6/SS2/ADP7
PTC3
K9
55
H6
44
PTC4
PTC4/KBI1P7/CMPP0/ADP8
PTC4
K10
56
H8
45
PTC5
PTC5/KBI2P0/CMPP1/ADP9
PTC5
K11
57
H9
46
PTC6
PTC6/KBI2P1/PRACMPO/ADP10
PTC6
F8
58
F8
47
PTC7
PTC7/KBI2P2/CLKOUT/ADP11
PTC7
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
2-11
Pins and Connections
Table 2-6. PTD Pinout Summary
104
MAPBGA
100
LQFP
81
MAPBGA
80
LQFP
Default
Function
Composite Pin Name
PTD
L9
59
H7
48
PTD0
PTD0/BKGD/MS
PTD0
K8
60
J7
49
PTD1
PTD1/CMPP2/RESET
PTD1
H11
61
E7
50
PTD2
PTD2/USB_ALTCLK/RGPIOP8/TPM1CH0
PTD2
H10
62
E8
51
PTD3
PTD3/USB_PULLUP(D+)/RGPIOP9/
TPM1CH1
PTD3
H9
63
F9
52
PTD4
PTD4/SDA/RGPIOP10/TPM1CH2
PTD4
G9
64
D7
53
PTD5
PTD5/SCL/RGPIOP11/TPM1CH3
PTD5
J8
65
E9
54
PTD6
PTD6/USB_ALTCLK/TX1
PTD6
G10
66
D8
55
PTD7
PTD7/USB_PULLUP(D+)/RX1
PTD7
Table 2-7. PTE Pinout Summary
104
MAPBGA
100
LQFP
81
MAPBGA
80
LQFP
Default
Function
Composite Pin Name
PTE
G11
67
D9
56
PTE0
PTE0/KBI2P3/FB_ALE/FB_CS1
PTE0
E11
72
C9
57
PTE1
PTE1/KBI2P4/RGPIOP13/FB_AD6
PTE1
D11
73
C8
58
PTE2
PTE2/KBI2P5/RGPIOP14/FB_AD7
PTE2
D10
74
B9
59
PTE3
PTE3/KBI2P6/FB_AD8
PTE3
C9
75
A9
60
PTE41
PTE4/CMPP3/TPMCLK/IRQ
PTE4
B8
78
C7
63
PTE5
PTE5/FB_D7/USB_SESSVLD/TX2
PTE5
C10
79
C6
64
PTE6
PTE6/FB_RW/USB_SESSEND/RX2
PTE6
C11
80
B6
65
PTE7
PTE7/USB_VBUSVLD/TPM2CH3
PTE7
1
PTE4/CMPP3/TPMCLK/IRQ is limited to input-only for the port I/O function.
Table 2-8. PTF Pinout Summary
104
MAPBGA
100
LQFP
81
MAPBGA
80
LQFP
Default
Function
Composite Pin Name
PTF
B9
81
B8
66
PTF0
PTF0/USB_ID/TPM2CH2
PTF0
B10
82
B7
67
PTF1
PTF1/RX2/USB_DP_DOWN/TPM2CH1
PTF1
B11
83
C5
68
PTF2
PTF2/TX2/USB_DM_DOWN/TPM2CH0
PTF2
A7
89
A8
69
PTF3
PTF3/SCL/FB_D5/FB_AD11
PTF3
A6
90
A9
70
PTF4
PTF4/SDA/FB_D4/FB_AD10
PTF4
B5
91
B5
71
PTF5
PTF5/KBI2P7/FB_D3/FB_AD9
PTF5
MCF51MM256 Series Devices Reference Manual, Rev. 3
2-12
Freescale Semiconductor
Pins and Connections
Table 2-8. PTF Pinout Summary (Continued)
104
MAPBGA
100
LQFP
81
MAPBGA
80
LQFP
Default
Function
Composite Pin Name
PTF
A1
98
A3
78
PTF6
PTF6/MOSI1
PTF6
A2
99
B1
79
PTF7
PTF7/MISO1
PTF7
Table 2-9. PTG Pinout Summary
104
MAPBGA
100
LQFP
81
MAPBGA
80
LQFP
Default
Function
Composite Pin Name
PTG
B1
100
A2
80
PTG0
PTG0/SPSCK1
PTG0
F4
—
A1
—
PTG1
PTG1
PTG1
C4
—
—
—
PTG2
PTG2
PTG2
B3
—
—
—
PTG3
PTG3
PTG3
C2
—
—
—
PTG4
PTG4
PTG4
C6
3
—
—
PTG5
PTG5/FB_RW
PTG5
C5
4
—
—
PTG6
PTG6/FB_AD19
PTG6
C7
5
—
—
PTG7
PTG7/FB_AD18
PTG7
Table 2-10. PTH Pinout Summary
104
MAPBGA
100
LQFP
81
MAPBGA
80
LQFP
Default
Function
Composite Pin Name
PTH
B7
6
—
—
PTH0
PTH0/FB_OE
PTH0
C8
7
—
—
PTH1
PTH1/FB_D0
PTH1
J7
45
—
—
PTH2
PTH2/RGPIOP2/FB_D7
PTH2
J6
46
—
—
PTH3
PTH3/RGPIOP3/FB_D6
PTH3
J5
47
—
—
PTH4
PTH4/RGPIOP4/FB_D5
PTH4
K4
48
—
—
PTH5
PTH5/RGPIOP5/FB_D4
PTH5
J4
49
—
—
PTH6
PTH6/RGPIOP6/FB_D3
PTH6
J3
50
—
—
PTH7
PTH7/RGPIOP7/FB_D2
PTH7
Table 2-11. PTJ Pinout Summary
104
MAPBGA
100
LQFP
81
MAPBGA
80
LQFP
Default
Function
Composite Pin Name
PTJ
F10
68
—
—
PTJ0
PTJ0/FB_AD2
PTJ0
F11
69
—
—
PTJ1
PTJ1/FB_AD3
PTJ1
F9
70
—
—
PTJ2
PTJ2/FB_AD4
PTJ2
E10
71
—
—
PTJ3
PTJ3/RGPIOP12/FB_AD5
PTJ3
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
2-13
Pins and Connections
Table 2-11. PTJ Pinout Summary
104
MAPBGA
100
LQFP
81
MAPBGA
80
LQFP
Default
Function
Composite Pin Name
PTJ
A11
84
—
—
PTJ4
PTJ4/RGPIOP15/FB_AD16
PTJ4
A10
85
—
—
PTJ5
PTJ5/FB_AD15
PTJ5
B6
86
—
—
PTJ6
PTJ6/FB_AD14
PTJ6
A9
87
—
—
PTJ7
PTJ7/FB_AD13
PTJ7
Table 2-12. OSC1 Pinout Summary
104
MAPBGA
100
LQFP
81
MAPBGA
80
LQFP
Default
Function
Composite Pin Name
OSC1
L8
38
J5
33
PTB2
PTB2/EXTAL1
EXTAL1
L7
39
J6
34
PTB3
PTB3/XTAL1
XTAL1
Table 2-13. OSC2 Pinout Summary
104
MAPBGA
100
LQFP
81
MAPBGA
80
LQFP
Default
Function
Composite Pin Name
OSC2
L11
41
J8
36
PTB4
PTB4/EXTAL2
EXTAL2
L10
42
J9
37
PTB5
PTB5/XTAL2
XTAL2
Table 2-14. KBI1 Pinout Summary
104
MAPBGA
100
LQFP
81
MAPBGA
80
LQFP
Default
Function
Composite Pin Name
KBI1
D9
8
C4
3
PTA1
PTA1/KBI1P0/TX1/FB_D1
KBI1P0
E9
9
D5
4
PTA2
PTA2/KBI1P1/RX1/ADP4
KBI1P1
H3
10
D6
5
PTA3
PTA3/KBI1P2/FB_D6/ADP5
KBI1P2
K5
43
G6
38
PTB6
PTB6/KBI1P3/RGPIOP0/FB_AD17
KBI1P3
K6
44
F7
39
PTB7
PTB7/KBI1P4/RGPIOP1/FB_AD0
KBI1P4
J9
53
G9
42
PTC2
PTC2/KBI1P5/SPSCK2/ADP6
KBI1P5
K7
54
H5
43
PTC3
PTC3/KBI1P6/SS2/ADP7
KBI1P6
K9
55
H6
44
PTC4
PTC4/KBI1P7/CMPP0/ADP8
KBI1P7
Table 2-15. KBI2 Pinout Summary
104
MAPBGA
100
LQFP
81
MAPBGA
80
LQFP
Default
Function
Composite Pin Name
KBI2
K10
56
H8
45
PTC5
PTC5/KBI2P0/CMPP1/ADP9
KBI2P0
K11
57
H9
46
PTC6
PTC6/KBI2P1/PRACMPO/ADP10
KBI2P1
MCF51MM256 Series Devices Reference Manual, Rev. 3
2-14
Freescale Semiconductor
Pins and Connections
Table 2-15. KBI2 Pinout Summary (Continued)
104
MAPBGA
100
LQFP
81
MAPBGA
80
LQFP
Default
Function
Composite Pin Name
KBI2
F8
58
F8
47
PTC7
PTC7/KBI2P2/CLKOUT/ADP11
KBI2P2
G11
67
D9
56
PTE0
PTE0/KBI2P3/FB_ALE/FB_CS1
KBI2P3
E11
72
C9
57
PTE1
PTE1/KBI2P4/RGPIOP13/FB_AD6
KBI2P4
D11
73
C8
58
PTE2
PTE2/KBI2P5/RGPIOP14/FB_AD7
KBI2P5
D10
74
B9
59
PTE3
PTE3/KBI2P6/FB_AD8
KBI2P6
B5
91
B5
71
PTF5
PTF5/KBI2P7/FB_D3/FB_AD9
KBI2P7
Table 2-16. SPI Pinout Summary
104
MAPBGA
100
LQFP
81
MAPBGA
80
LQFP
Default
Function
Composite Pin Name
SPI1
A2
99
B1
79
PTF7
PTF7/MISO1
MISO1
A1
98
A3
78
PTF6
PTF6/MOSI1
MOSI1
B1
100
A2
80
PTG0
PTG0/SPSCK1
SPSCK1
B2
1
B2
1
PTA0
PTA0/FB_D2/SS1
SS1
Table 2-17. SPI2 Pinout Summary
104
MAPBGA
100
LQFP
81
MAPBGA
80
LQFP
Default
Function
Composite Pin Name
SPI2
J11
52
G8
41
PTC1
PTC1/MISO2/FB_D0/FB_AD1
MISO2
J10
51
G7
40
PTC0
PTC0/MOSI2/FB_OE/FB_CS0
MOSI2
J9
53
G9
42
PTC2
PTC2/KBI1P5/SPSCK2/ADP6
SPSCK2
K7
54
H5
43
PTC3
PTC3/KBI1P6/SS2/ADP7
SS2
Table 2-18. IIC Pinout Summary
104
MAPBGA
100
LQFP
81
MAPBGA
80
LQFP
Default
Function
Composite Pin Name
IIC
G9
64
D7
53
PTD5
PTD5/SCL/RGPIOP11/TPM1CH3
SCL
A7
89
A8
69
PTF3
PTF3/SCL/FB_D5/FB_AD11
SCL
H9
63
F9
52
PTD4
PTD4/SDA/RGPIOP10/TPM1CH2
SDA
A6
90
A9
70
PTF4
PTF4/SDA/FB_D4/FB_AD10
SDA
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
2-15
Pins and Connections
Table 2-19. Other Pinout Summary
104
MAPBGA
100
LQFP
81
MAPBGA
80
LQFP
Default
Function
Composite Pin Name
Other
L9
59
H7
48
PTD0
PTD0/BKGD/MS
BKGD/MS
F8
58
F8
47
PTC7
PTC7/KBI2P2/CLKOUT/ADP11
CLKOUT
C9
75
A9
60
PTE4
PTE4/CMPP3/TPMCLK/IRQ
IRQ
K8
60
J7
49
PTD1
PTD1/CMPP2/RESET
RESET
Table 2-20. OPAMP Pinout Summary
104
MAPBGA
100
LQFP
81
MAPBGA
80
LQFP
Default
Function
Composite Pin Name
OPAMP
F2
19
D1
14
INP1-
INP1-
INP1-
D2
11
C1
6
PTA4
PTA4/INP1+
INP1+
F3
24
F3
19
INP2-
INP2-
INP2-
E2
14
D2
9
PTA7
PTA7/INP2+
INP2+
G2
20
E1
15
OUT1
OUT1
OUT1
G3
25
E3
20
OUT2
OUT2
OUT2
Table 2-21. TRIAMP Pinout Summary
104
MAPBGA
100
LQFP
81
MAPBGA
80
LQFP
Default
Function
Composite Pin Name
TRIAMP
G1
21
F2
16
TRIOUT1
TRIOUT1/DADP2
TRIOUT1
L1
27
G3
22
TRIOUT2
TRIOUT2/DADP3
TRIOUT2
H2
23
E2
18
VINN1
VINN1/DADM2
VINN1
K2
29
G4
24
VINN2
VINN2/DADM3
VINN2
H1
22
F1
17
VINP1
VINP1
VINP1
K1
28
H4
23
VINP2
VINP2
VINP2
Table 2-22. MFB Pinout Summary
104
MAPBGA
100
LQFP
81
MAPBGA
80
LQFP
Default
Function
Composite Pin Name
MFB
K6
44
F7
39
PTB7
PTB7/KBI1P4/RGPIOP1/FB_AD0
FB_AD0
A8
88
—
—
FB_AD12
FB_AD12
A9
87
—
—
PTJ7
PTJ7/FB_AD13
FB_AD13
B6
86
—
—
PTJ6
PTJ6/FB_AD14
FB_AD14
A10
85
—
—
PTJ5
PTJ5/FB_AD15
FB_AD15
A11
84
—
—
PTJ4
PTJ4/RGPIOP15/FB_AD16
FB_AD16
MCF51MM256 Series Devices Reference Manual, Rev. 3
2-16
Freescale Semiconductor
Pins and Connections
Table 2-22. MFB Pinout Summary (Continued)
104
MAPBGA
100
LQFP
81
MAPBGA
80
LQFP
Default
Function
Composite Pin Name
MFB
K5
43
G6
38
PTB6
PTB6/KBI1P3/RGPIOP0/FB_AD17
FB_AD17
C7
5
—
—
PTG7
PTG7/FB_AD18
FB_AD18
C5
4
—
—
PTG6
PTG6/FB_AD19
FB_AD19
F10
68
—
—
PTJ0
PTJ0/FB_AD2
FB_AD2
F11
69
—
—
PTJ1
PTJ1/FB_AD3
FB_AD3
F9
70
—
—
PTJ2
PTJ2/FB_AD4
FB_AD4
E10
71
—
—
PTJ3
PTJ3/RGPIOP12/FB_AD5
FB_AD5
E11
72
C9
57
PTE1
PTE1/KBI2P4/RGPIOP13/FB_AD6
FB_AD6
D11
73
C8
58
PTE2
PTE2/KBI2P5/RGPIOP14/FB_AD7
FB_AD7
D10
74
B9
59
PTE3
PTE3/KBI2P6/FB_AD8
FB_AD8
G11
67
D9
56
PTE0
PTE0/KBI2P3/FB_ALE/FB_CS1
FB_ALE/
FB_CS1
C8
7
—
—
PTH1
PTH1/FB_D0
FB_D0
J11
52
G8
41
PTC1
PTC1/MISO2/FB_D0/FB_AD1
FB_D0/
FB_AD1
D9
8
C4
3
PTA1
PTA1/KBI1P0/TX1/FB_D1
FB_D1
B2
1
B2
1
PTA0
PTA0/FB_D2/SS1
FB_D2
J3
50
—
—
PTH7
PTH7/RGPIOP7/FB_D2
FB_D2
J4
49
—
—
PTH6
PTH6/RGPIOP6/FB_D3
FB_D3
B5
91
B5
71
PTF5
PTF5/KBI2P7/FB_D3/FB_AD9
FB_D3/
FB_AD9
K4
48
—
—
PTH5
PTH5/RGPIOP5/FB_D4
FB_D4
A6
90
A9
70
PTF4
PTF4/SDA/FB_D4/FB_AD10
FB_D4/
FB_AD10
J5
47
—
—
PTH4
PTH4/RGPIOP4/FB_D5
FB_D5
A7
89
A8
69
PTF3
PTF3/SCL/FB_D5/FB_AD11
FB_D5/
FB_AD11
H3
10
D6
5
PTA3
PTA3/KBI1P2/FB_D6/ADP5
FB_D6
J6
46
—
—
PTH3
PTH3/RGPIOP3/FB_D6
FB_D6
J7
45
—
—
PTH2
PTH2/RGPIOP2/FB_D7
FB_D7
B8
78
C7
63
PTE5
PTE5/FB_D7/USB_SESSVLD/TX2
FB_D7
B7
6
—
—
PTH0
PTH0/FB_OE
FB_OE
J10
51
G7
40
PTC0
PTC0/MOSI2/FB_OE/FB_CS0
FB_OE/
FB_CS0
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
2-17
Pins and Connections
Table 2-22. MFB Pinout Summary (Continued)
104
MAPBGA
100
LQFP
81
MAPBGA
80
LQFP
Default
Function
Composite Pin Name
MFB
C6
3
—
—
PTG5
PTG5/FB_RW
FB_RW
C10
79
C6
64
PTE6
PTE6/FB_RW/USB_SESSEND/RX2
FB_RW
Table 2-23. DAC Pinout Summary
104
MAPBGA
100
LQFP
81
MAPBGA
80
LQFP
Default
Function
Composite Pin Name
DAC
L2
26
G2
21
DACO
DACO
DACO
Table 2-24. VREF Pinout Summary
104
MAPBGA
100
LQFP
81
MAPBGA
80
LQFP
Default
Function
Composite Pin Name
VREF
L4
32
G5
27
VREFO
VREFO
VREFO
Table 2-25. CMT Pinout Summary
104
MAPBGA
100
LQFP
81
MAPBGA
80
LQFP
Default
Function
Composite Pin Name
CMT
C1
2
A1
2
IRO
IRO
IRO
Table 2-26. P/G Pinout Summary
104
MAPBGA
100
LQFP
81
MAPBGA
80
LQFP
Default
Function
Composite Pin Name
P/G
D4
97
E6
77
VDD1
VDD1
VDD1
D6
40
E4
35
VDD2
VDD2
VDD2
D8
77
E5
62
VDD3
VDD3
VDD3
L6
36
J4
31
VDDA
VDDA
VDDA
H4
96
F6
76
VSS1
VSS1
VSS1
H6
37
F4
32
VSS2
VSS2
VSS2
H8
76
F5
61
VSS3
VSS3
VSS3
E1
17
J1
12
VSSA
VSSA
VSSA
Table 2-27. USB Pinout Summary
104
MAPBGA
100
LQFP
81
MAPBGA
80
LQFP
Default
Function
Composite Pin Name
USB
H11
61
E7
50
PTD2
PTD2/USB_ALTCLK/RGPIOP8/TPM1CH0
USB_ALTCLK
J8
65
E9
54
PTD6
PTD6/USB_ALTCLK/TX1
USB_ALTCLK
MCF51MM256 Series Devices Reference Manual, Rev. 3
2-18
Freescale Semiconductor
Pins and Connections
Table 2-27. USB Pinout Summary (Continued)
104
MAPBGA
100
LQFP
81
MAPBGA
80
LQFP
Default
Function
Composite Pin Name
USB
A4
93
B4
73
USB_DM
USB_DM
USB_DM
B11
83
C5
68
PTF2
PTF2/TX2/USB_DM_DOWN/TPM2CH0
USB_DM_DOWN
C4
—
—
—
PTG2
PTG2/USB_DM_DOWN
USB_DM_DOWN
A3
94
A4
74
USB_DP
USB_DP
USB_DP
B10
82
B7
67
PTF1
PTF1/RX2/USB_DP_DOWN/TPM2CH1
USB_DP_DOWN
B3
—
—
—
PTG3
PTG3/USB_DP_DOWN
USB_DP_DOWN
B9
81
B8
66
PTF0
PTF0/USB_ID/TPM2CH2
USB_ID
H10
62
E8
51
PTD3
PTD3/USB_PULLUP(D+)/RGPIOP9/
TPM1CH1
USB_PULLUP(D+)
G10
66
D8
55
PTD7
PTD7/USB_PULLUP(D+)/RX1
USB_PULLUP(D+)
C10
79
C6
64
PTE6
PTE6/FB_RW/USB_SESSEND/RX2
USB_SESSEND
F4
—
81
—
PTG1
PTG1/USB_SESSEND
USB_SESSEND
B8
78
C7
63
PTE5
PTE5/FB_D7/USB_SESSVLD/TX2
USB_SESSVLD
C2
—
—
—
PTG4
PTG4/USB_SESSVLD
USB_SESSVLD
C11
80
B6
65
PTE7
PTE7/USB_VBUSVLD/TPM2CH3
USB_VBUSVLD
B4
95
A5
75
VBUS
VBUS
VBUS
A5
92
A6
72
VUSB33
VUSB33
VUSB33
Table 2-28. SCI1 Pinout Summary
104
MAPBGA
100
LQFP
81
MAPBGA
80
LQFP
Default
Function
Composite Pin Name
SCI1
E9
9
D5
4
PTA2
PTA2/KBI1P1/RX1/ADP4
RX1
G10
66
D8
55
PTD7
PTD7/USB_PULLUP(D+) /RX1
RX1
D9
8
C4
3
PTA1
PTA1/KBI1P0/TX1/FB_D1
TX1
J8
65
E9
54
PTD6
PTD6/USB_ALTCLK/TX1
TX1
Table 2-29. SCI2 Pinout Summary
104
MAPBGA
100
LQFP
81
MAPBGA
80
LQFP
Default
Function
Composite Pin Name
SCI2
C10
79
C6
64
PTE6
PTE6/FB_RW/USB_SESSEND/RX2
RX2
B10
82
B7
67
PTF1
PTF1/RX2/USB_DP_DOWN/TPM2CH1
RX2
B8
78
C7
63
PTE5
PTE5/FB_D7/USB_SESSVLD/TX2
TX2
B11
83
C5
68
PTF2
PTF2/TX2/USB_DM_DOWN/TPM2CH0
TX2
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
2-19
Pins and Connections
Table 2-30. PRACMP Pinout Summary
104
MAPBGA
100
LQFP
81
MAPBGA
80
LQFP
Default
Function
Composite Pin Name
PRACMP
K9
55
H6
44
PTC4
PTC4/KBI1P7/CMPP0/ADP8
CMPP0
K10
56
H8
45
PTC5
PTC5/KBI2P0/CMPP1/ADP9
CMPP1
K8
60
J7
49
PTD1
PTD1/CMPP2/RESET
CMPP2
C9
75
A9
60
PTE4
PTE4/CMPP3/TPMCLK/IRQ
CMPP3
K11
57
H9
46
PTC6
PTC6/KBI2P1/PRACMPO/ADP10
PRACMPO
Table 2-31. ADC Pinout Summary
104
MAPBGA
100
LQFP
81
MAPBGA
80
LQFP
Default
Function
Composite Pin Name
ADC
K11
57
H9
46
PTC6
PTC6/KBI2P1/PRACMPO/ADP10
ADP10
F8
58
F8
47
PTC7
PTC7/KBI2P2/CLKOUT/ADP11
ADP11
E9
9
D5
4
PTA2
PTA2/KBI1P1/RX1/ADP4
ADP4
H3
10
D6
5
PTA3
PTA3/KBI1P2/FB_D6/ADP5
ADP5
J9
53
G9
42
PTC2
PTC2/KBI1P5/SPSCK2/ADP6
ADP6
K7
54
H5
43
PTC3
PTC3/KBI1P6/SS2/ADP7
ADP7
K9
55
H6
44
PTC4
PTC4/KBI1P7/CMPP0/ADP8
ADP8
K10
56
H8
45
PTC5
PTC5/KBI2P0/CMPP1/ADP9
ADP9
J2
31
H1
26
DADM0
DADM0
DADM0
L3
34
H3
29
DADM1
DADM1
DADM1
H2
23
E2
18
VINN1
VINN1/DADM2
DADM2
K2
29
G4
24
VINN2
VINN2/DADM3
DADM3
J1
30
G1
25
DADP0
DADP0
DADP0
K3
33
H2
28
DADP1
DADP1
DADP1
G1
21
F2
16
TRIOUT1
TRIOUT1/DADP2
DADP2
L1
27
G3
22
TRIOUT2
TRIOUT2/DADP3
DADP3
L5
35
J3
30
VREFH
VREFH
VREFH
F1
18
J2
13
VREFL
VREFL
VREFL
MCF51MM256 Series Devices Reference Manual, Rev. 3
2-20
Freescale Semiconductor
Pins and Connections
Table 2-32. TPM1 Pinout Summary
104
MAPBGA
100
LQFP
81
MAPBGA
80
LQFP
Default
Function
Composite Pin Name
TPM1
H11
61
E7
50
PTD2
PTD2/USB_ALTCLK/RGPIOP8/TPM1CH0
TPM1CH0
H10
62
E8
51
PTD3
PTD3/USB_PULLUP(D+)/RGPIOP9/
TPM1CH1
TPM1CH1
H9
63
F9
52
PTD4
PTD4/SDA/RGPIOP10/TPM1CH2
TPM1CH2
G9
64
D7
53
PTD5
PTD5/SCL/RGPIOP11/TPM1CH3
TPM1CH3
C9
75
A9
60
PTE4
PTE4/CMPP3/TPMCLK/IRQ
TPMCLK
Table 2-33. TPM2 Pinout Summary
104
MAPBGA
100
LQFP
81
MAPBGA
80
LQFP
Default
Function
Composite Pin Name
TPM2
B11
83
C5
68
PTF2
PTF2/TX2/USB_DM_DOWN/TPM2CH0
TPM2CH0
B10
82
B7
67
PTF1
PTF1/RX2/USB_DP_DOWN/TPM2CH1
TPM2CH1
B9
81
B8
66
PTF0
PTF0/USB_ID/TPM2CH2
TPM2CH2
C11
80
B6
65
PTE7
PTE7/USB_VBUSVLD/TPM2CH3
TPM2CH3
C9
75
A9
60
PTE4
PTE4/CMPP3/TPMCLK/IRQ
TPMCLK
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
2-21
Pins and Connections
2.6.2
Recommended System Connections
VREFO
0.1 F
CBYAD
0.1 F
SYSTEM
POWER
3.3 V
CBLK +
10 F
+
CBY
0.1 F
MCF51MM256
VDDA/VREFH
PORT
A
VSSA/VREFL
VDD1
VDD2
VDD3
PORT
B
VSS1
VSS2
VSS3
LCD
Glass
USB mini AB
SPI1
VUSB33
5
4 ID
3
2
1
0.1 F
USB_DP
USB_DM
VBUS
PORT
C
BACKGROUND
VDD
VDD
0.1 F
OPTIONAL
MANUAL
RESET
(NOTE 1)
RF1
C1
C2
X1
PORT
E
PTE0/KBI2P3/FB_ALE/FB_CS1
PTE1/KBI2P4/RGPIOP13/FB_AD6
PTE2/KBI2P5/RGPIOP14/FB_AD7
PTE3/KBI2P6/FB_AD8
PTE4/CMPP3/TPMCLK/IRQ
PTE5/FB_D7/USB_SESSVLD/TX2
PTE6/FB_RW/USB_SESSEND/RX2
PTE7/USB_VBUSVLD/TPM2CH3
PORT
F
PTF0/USB_ID/TPM2CH2
PTF1/RX2/USB_DP_DOWN/TPM2CH1
PTF2/TX2/USB_DM_DOWN/TPM2CH0
PTF3/SCL/FB_D5/FB_AD11
PTF4/SDA/FB_D4/FB_AD10
PTF5/KBI2P7/FB_D3/FB_AD9
PTF6/MOSI1
PTF7/MISO1
PORT
G
PTG0/SPSCK1
PTG1/USB_SESSEND
PTG2/USB_DM_DOWN
PTG3/USB_DP_DOWN
PTG4/USB_SESSVLD
PTG5/FB_RW
PTG6/FB_AD19
PTG7/FB_AD18
OPTIONAL
EMC
PROTECTION
(NOTE 3)
32KHz TOD
OSCILLATOR
XTAL1
EXTAL1
RF2
C4
X2
Optional
EXTAL2
C3 32KHz or 1-16MHz
OSCILLATOR
RS2
XTAL2
NOTE:
When using the XOSCVLP module in
low range and low power mode,
the external components RF,
RS, C1 and C2 are not required.
Ext. Flash
Expansion
MFB
PTJ0/FB_AD2
PTJ1/FB_AD3
PTJ2/FB_AD4
PTJ3/RGPIOP12/FB_AD5
PTJ4/RGPIOP15/FB_AD16
PTJ5/FB_AD15
PTJ6/FB_AD14
PTJ7/FB_AD13
PORT
J
PTH0/FB_OE
PTH1/FB_D0
PTH2/RGPIOP2/FB_D7
PTH3/RGPIOP3/FB_D6
PTH4/RGPIOP4/FB_D5
PTH5/RGPIOP5/FB_D4
PTH6/RGPIOP6/FB_D3
PTH7/RGPIOP7/FB_D2
PORT
H
PTC0/MOSI2/FB_OE/FB_CS0
PTC1/MISO2/FB_D0/FB_AD1
PTC2/KBI1P5/SPSCK2/ADP6
PTC3/KBI1P6/SS2/ADP7
PTC4/KBI1P7/CMPP0/ADP8
PTC5/KBI2P0/CMPP1/ADP9
PTC6/KBI2P1/PRACMPO/ADP10
PTC7/KBI2P2/CLKOUT/ADP11
PORT
D
RESET
RS1
PTB0
PTB1/BLMS
PTB2/EXTAL1
PTB3/XTAL1
PTB4/EXTAL2
PTB5/XTAL2
PTB6/KBI1P3/RGPIOP0/FB_AD17
PTB7/KBI1P4/RGPIOP1/FB_AD0
PTD0/BKGD/MS
PTD1/CMPP2/RESET
PTD2/USB_ALTCLK/RGPIOP8/TPM1CH0
PTD3/USB_PULLUP(D+)/RGPIOP9/TPM1CH1
PTD4/SDA/RGPIOP10/TPM1CH2
PTD5/SCL/RGPIOP11/TPM1CH3
PTD6/USB_ALTCLK/TX1
PTD7/USB_PULLUP(D+)/RX1
BKGD/MS
4.7 k–
10 k
PTA0/FB_D2/SS1
PTA1/KBI1P0/TX1/FB_D1
PTA2/KBI1P1/RX1/ADP4
PTA3/KBI1P2/FB_D6/ADP5
PTA4/INP1+
PTA5
PTA6
PTA7/INP2+
opto
isolator
RX1
TX1
opto
isolator
Figure 2-5. Recommended System Connections
MCF51MM256 Series Devices Reference Manual, Rev. 3
2-22
Freescale Semiconductor
Pins and Connections
2.6.3
Interfacing the SCIs to Off-Chip Opto-Isolators
SCI1 is designed with twice the normal I/O drive capability on the TX1 pin. The RX pin can either be fed
directly from the digital I/O buffer, or those signals can be pre-conditioned using the comparators as shown
in Figure 2-6 Similarly, the TX output can be modulated with the output of one of the timers before being
passed off chip.
SIMIPS[RX1IN]
-
Internal or external reference
+
analog
comparator
opto
RX1
isolator
RX
digital
buffer
SCI1/2
TX
0
opto
TX1
isolator
1
TPM Ch0 Output
TPM Ch1 Output
SIMIPS[MODTX1]
SIMIPS[MTBASE1]
On-Chip Components
Off-Chip Opto-Isolators
Figure 2-6. On-Chip Signal Conditioning Associated with SCI RX and TX Pins
Controls for the circuitry shown in Figure 2-6 are discussed in Section 5.7.13, “SIM Internal Peripheral
Select Register (SIMIPS).”
2.6.4
Power
VDD1,2,3 and VSS1,2,3 are the primary power supply pins for the microcontroller. This voltage source
supplies power to all I/O buffer circuitry and to an internal voltage regulator. The internal voltage regulator
provides regulated lower-voltage source to the CPU and other internal circuitry of the microcontroller.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
2-23
Pins and Connections
Typically, application systems have two separate capacitors across the power pins. In this case, there
should be a bulk electrolytic capacitor, such as a 10 F tantalum capacitor, to provide bulk charge storage
for the overall system and a 0.1 F ceramic bypass capacitor located as close to the microcontroller power
pins as practical to suppress high-frequency noise. The MCF51MM256 has three VDD pins. Each pin must
have a bypass capacitor for best noise suppression.
VDDA and VSSA are the analog power supply pins for the microcontroller. This voltage source supplies
power to the ADC module. A 0.1 F ceramic bypass capacitor should be located as close to the
microcontroller power pins as practical to suppress high-frequency noise.
VUSB33 maintains an output voltage of 3.3 V and sources enough current for the internal USB transceiver
and USB pullup resistor. The VBUS input is used to supply the voltage necessary to power the internal
USB 3.3V regulator. VUSB33 can also supply the internal USB when there is no VBUS supply and the
internal USB regulator is disabled.
For VUSB33, two separate capacitors (4.7 F bulk electrolytic stability capacitor and 0.47 F ceramic
bypass capacitors) must be connected across this pin to ground to decrease the output ripple of this voltage
regulator when it is enabled.
2.6.5
Oscillator
Immediately after reset, the microcontroller uses an internally generated clock provided by the
multipurpose clock generation (MCG) module.
The oscillator (XOSC1 or XOSC2) in this microcontroller is a Pierce oscillator that can accommodate a
crystal or ceramic resonator. Optionally, an external clock source can be connected to the EXTAL input
pin.
When using the oscillator module in low range and low power mode, the external components RF, RS, C1
and C2 are not required.
For using the oscillator module in other modes, refer to Figure 2-5 for the following discussion. RS (when
used) and RF should be low-inductance resistors such as carbon composition resistors. Wire-wound
resistors, and some metal film resistors, have too much inductance. C1 and C2 normally should be
high-quality ceramic capacitors that are specifically designed for high-frequency applications.
RF is used to provide a bias path to keep the EXTAL input in its linear range during crystal startup; its value
is not generally critical. Typical systems use 1 M to 10 M. Higher values are sensitive to humidity and
lower values reduce gain and (in extreme cases) could prevent startup.
C1 and C2 are typically in the 5 pF to 25 pF range and are chosen to match the requirements of a specific
crystal or resonator. Be sure to take into account printed circuit board (PCB) capacitance and
microcontroller pin capacitance when selecting C1 and C2. The crystal manufacturer typically specifies a
load capacitance that is the series combination of C1 and C2 (which are usually the same size). As a
first-order approximation, use 10 pF as an estimate of combined pin and PCB capacitance for each
oscillator pin (EXTAL and XTAL).
MCF51MM256 Series Devices Reference Manual, Rev. 3
2-24
Freescale Semiconductor
Pins and Connections
2.6.6
PTD1/CMPP2/RESET
After a power-on reset (POR) the PTD1/CMPP2/RESET pin defaults to RESET. Clearing RSTPE in
SOPT1 allows the pin to be a GPIO pin or as an input to the PRACMP. When configured as a GPIO, the
pin will remain as a GPIO until the next POR or LVD reset. When enabled, the RESET pin can be used to
reset the MCU from an external source when the pin is driven low. Internal power-on reset and low-voltage
reset circuitry typically make external reset circuitry unnecessary. This pin is normally connected to the
standard 6-pin background debug connector so a development system can directly reset the MCU system.
A manual external reset can be added by supplying a simple switch to ground (pull reset pin low to force
a reset).
Whenever any non-POR reset is initiated (whether from an external signal or from an internal system), the
enabled RESET pin is driven low for about 66 bus cycles. The reset circuitry decodes the cause of reset
and records it by setting a corresponding bit in the system reset status register (SRS).
In EMC-sensitive applications, an external RC filter is recommended on the reset pin. See Figure 2-5 for
an example.
2.6.7
PTE4/CMPP3/TPMCLK/IRQ
The IRQ pin is the input source for the IRQ interrupt. If the IRQ function is not enabled, this pin can be
used for other functions. In EMC-sensitive applications, an external RC filter is recommended on the IRQ
pin. See Figure 2-5. for an example.
NOTE
The voltage on the internally pulled up IRQ pin when measured is below
VDD. The internal gates connected to this pin are pulled to VDD. If the IRQ
pin is required to drive to a VDD level, an external pullup must be used.
2.6.8
Background / Mode Select (PTD0/BKGD/MS)
During a power-on-reset (POR) or background debug force reset (see bit BDFR in Section 29.3.3,
“Configuration/Status Register 2 (CSR2),” for more information), the BKGD/MS pin functions as a mode
select pin. Immediately after any reset, the pin functions as the background pin and can be used for
background debug communication.
If the BKGD/MS pin is unconnected, the microcontroller enters normal operating mode at the rising edge
of the internal reset after a POR or forced BDC reset. If a debug system is connected to the 6-pin standard
background debug header, it can hold BKGD/MS low during a POR or immediately after issuing a
background debug force reset1, which forces the microcontroller to halt mode.
The BKGD/MS pin is used primarily for background debug controller (BDC) communications using a
custom protocol that uses 16 clock cycles of the target microcontroller’s BDC clock per bit time. The target
microcontroller’s BDC clock could be as fast as the bus clock rate, so there should never be any significant
capacitance connected to the BKGD/MS pin that could interfere with background serial communications.
1. Specifically, BKGD must be held low through the first 16 cycles after deassertion of the internal reset.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
2-25
Pins and Connections
Although the BKGD/MS pin is a pseudo open-drain pin, the background debug communication protocol
provides brief, actively driven, high speed-up pulses to ensure fast rise times. Small capacitances from
cables and the absolute value of the internal pullup device play almost no role in determining rise and fall
times on the BKGD/MS pin.
2.6.9
ADC Reference Pins (VREFH, VREFL)
The VREFH and VREFL pins are the voltage reference high and voltage reference low inputs, respectively,
for the ADC module.
2.6.10
Bootloader Mode Select (BLMS)
During a power-on-reset (POR), the CPU detects the state of the PTB1/BLMS pin that functions as a mode
select pin. When the BLMS pin is held low and BKGD/MS is not pulled low, the CPU enters the
bootloader mode. During a power-on-reset (POR), an internal pullup device is automatically enabled in
PTB1/BLMS pin. Immediately after reset rises the pin functions as a general-purpose output only pin and
an internal pullup device is automatically disabled.
2.6.11
USB Data Pins (USB_DP, USB_DN)
The USB_DP (D+) and USB_DN (D–) pins are the analog input/output lines to/from full-speed internal
USB transceiver. An optional internal pullup resistor for the USB_DP pin, RPUDP, is available. See
Chapter 27, “USB On-the-GO (USBOTG)” for more details.
2.6.12
General-Purpose I/O and Peripheral Ports
The MCF51MM256 series microcontrollers support up to 69 general-purpose I/O pins, which are shared
with on-chip peripheral functions (timers, serial I/O, ADC, ACMP, etc.).
When a port pin is configured as a general-purpose output or a peripheral uses the port pin as an output,
software can select one of two drive strengths and enable or disable slew rate control. When a port pin is
configured as a general-purpose input or a peripheral uses the port pin as an input, software can enable a
pull-up device. Immediately after reset, all of these pins are configured as high-impedance
general-purpose inputs with internal pull-up devices disabled.
When an on-chip peripheral system is controlling a pin, data direction control bits determine what is read
from the port data registers, even though the peripheral controls the pin direction via the pin’s output buffer
enable. For information about controlling these pins as general-purpose I/O pins, see Chapter 6, “Parallel
Input/Output Control.”
NOTE
To avoid extra current drain from floating input pins, the reset initialization
routine in the application program should enable on-chip pullup devices or
change the direction of unused or non-bonded pins to outputs so they do not
float.
MCF51MM256 Series Devices Reference Manual, Rev. 3
2-26
Freescale Semiconductor
Chapter 3
Modes of Operation
3.1
Introduction
The operating modes of the MCF51MM256 series MCUs are described in this chapter. Entry into each
mode, exit from each mode, and functionality while in each of the modes are described.
The overall system mode is generally a function of a number of separate, but interrelated, variables: debug
mode, security mode, power mode and clock mode. Clock modes were discussed in Section 17.4.1, “MCG
Modes of Operation.” This chapter covers the other dimensions of the system operating mode.
3.2
•
•
•
•
•
•
•
•
Features
Debug mode for code development. For devices based on the V1 ColdFire core, such as those in
the MCF51MM256 series, debug mode and secure mode are mutually exclusive.
Secure mode — BDC access to CPU resources is extremely restricted. It is possible to tell that the
device has been secured, and to clear security, which involves mass erasing the on-chip flash
memory. No other CPU access is allowed. Secure mode can be used in conjunction with each of
the power modes below.
Bootloader mode — Enables USB communications to external host for programming and erasing
the FLASH as an alternate to using the BDC.
Run mode — CPU clocks can be run at full speed, and the internal supply is fully regulated.
LPrun mode — CPU and peripheral clocks are restricted to 250 kHz CPU clock and 125 kHz bus
clock maximum and the internal supply is in soft regulation.
Wait mode — The CPU shuts down to conserve power; peripheral clocks are running and full
regulation is maintained.
LPwait mode — CPU shuts down to conserve power; peripheral clocks are running at reduced
speed (125 kHz maximum) and the internal supply is in soft regulation.
Stop modes—System (CPU and peripheral) clocks are stopped.
— Stop4—All internal circuits are powered (full regulation mode) and internal clock sources at
max frequency for fastest recovery, LVD enabled, no clocking to peripherals ENBDM=1.
— Stop3—All internal circuits are powered and clocks sources are at minimal values (BLPI or
BLPE mode), LVD disabled, providing a good compromise between power utilization and
speed of recovery. ENBDM=0.
— Stop2—Partial power-down of internal circuits; RAM content is retained. The lowest power
mode for this device. A reset or IRQ is required to return from Stop2 mode.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
3-1
Modes of Operation
On the MCF51MM256 series MCUs, Wait, Stop2, Stop3 and Stop4 are all entered via the CPU STOP
instruction. See Table 3-1 and subsequent sections of this chapter for details.
3.3
Overview
The ColdFire CPU has two primary user modes of operation, run and stop. (The CPU also supports a halt
mode that is used strictly for debug operations.) The STOP instruction is used to invoke stop and wait
modes for this family of devices.
The Systems Option Register 1 (SOPT1) contains two bits which control operation of the STOP
instruction. If SOPT1[WAITE] is set when STOP is executed, the wait mode is entered. Otherwise, if
SOPT1[STOPE] is set, the CPU enters one of the stop modes. It is illegal to execute a STOP instruction if
neither STOPE or WAITE are set. This results in reset assertion if the Instruction-related Reset Disable bit
in the CPU Control Register (CPUCR[IRD]) is cleared or an illegal instruction exception if CPUCR[IRD]
is set.
The MCF51MM256 series devices augment stop, wait, and run in a number of ways. The power
management controller (PMC) can run the device in fully-regulated mode, standby mode, and partial
power-down mode. Standby (loose regulation) or partial power-down can be programmed to occur
naturally as a result of a STOP instruction. Additionally, standby mode can be explicitly invoked via the
LPR (low-power) bit in the PMC System Power Management Status & Control Register 2
(SPMSC2[LPR]). Use of standby is limited to bus frequencies less than 125 kHz; and neither standby nor
partial power-down are allowed when XCSR[ENBDM] bit is set to enable debugging in stop and wait
modes.
During partial power-down mode, the regulator is in standby mode and much of the digital logic on the
chip is switched off. These interactions can be seen schematically in Figure 3-1. This figure is for
conceptual purposes only. It does not reflect any sequence or time dependencies between the PMC and
other parts of the device, nor does it represent any actual design partitioning.
STOP
SPMSC2[PPDC]
SOPT1[STOPE]
In Stop Mode
Partial Power Down
SOPT1[WAITE]
LVD Off
SPMSC1[LVDE]
SPMSC1[LVDSE]
Standby Enable
Standby
XCSR[ENBDM]
SPMSC2[LPR]
Figure 3-1. Power Modes — Conceptual Drawing
It is illegal for the software to have SPMSC2[PPDC] and SPMSC2[LPR] asserted concurrently. This
restriction arises because the sequence of events from normal to low-power modes involves use of both
bits. After entering a low-power mode, it is not possible to switch to another low-power mode.
MCF51MM256 Series Devices Reference Manual, Rev. 3
3-2
Freescale Semiconductor
Modes of Operation
Table 3-1. CPU / Power Mode Selections
LPwait mode - processor clock is inactive,
peripherals are clocked at low frequency and
the PMC is loosely regulating.
Low voltage detects are not active.
x
Stop modes disabled; Illegal opcode reset
if STOP instruction executed and
CPUCR[IRD] is cleared, else illegal
instruction exception is generated.
0
1
1
0
Stop4 - Either low-power modes have not
been requested, or low voltage detects are
enabled or ENBDM = 1.
1
Stop3 - Low voltage detect in stop is not
enabled. Clocks must be at low frequency
and are gated. The regulator is in loose
regulation.
1
Stop2 - Low voltage detects are not active. If
BDC is enabled, stop4 is invoked rather than
stop2.
1
x
x
x
0
x
x
1
1
x
x
1
x
x
x
x
0
0
x
1
0
x
Wait mode - processor clock nominally
inactive, but peripherals are clocked.
x
PPDC
x
LPR
LPrun mode with low voltage detect
disabled - processor and peripherals
clocked at low frequency2.
Low voltage detects are not active.
x
0
0
SPMSC2
PMC
LVDSE
x
SPMSC1
PMC
LVDE
Run mode - processor and peripherals
clocked normally.
CSR2
BDC
ENBDM1
STOPE
Mode of Operation
WAITE
SOPT1
SIM
Effects on Sub-System
CPU and
Peripheral Clocks
On. MCG in any
mode
Low freq required.
MCG in BLPE
mode.
0
1
0
x
x
x
0
x
x
1
1
x
x
Periph clocks on.
CPU clock on if
ENBDM=1.
1
x
x
x
x
On
0
x
1
0
CPU clock is off.
Periph clocks at
low speed.
MCG in BLPE.
On
0
1
0
Function
of BKGD/
MS at
reset
1
1
0
0
x
x
x
0
0
x
1
1
1
0
x
1
1
0
1
1
x
x
x
x
CPU clock on.
Periph clocks off.
1
0
1
0
x
1
0
0
0
x
0
0
BDC Clock
Switched
Power
On
On
Note: When not
needed, the BDC
clock can be gated off
at the discretion of the
processor. The clock
is available within a
few cycles of demand
by the processor,
normally when a
negative edge is
detected on BKGD.
The BDM command
associated with that
negative edge may
not take affect.
Loose Reg
On
Loose Reg
Function of BKGD/MS
at reset
On
BDC clock enabled
only if ENBDM=1 prior
to entering stop.
On
0
Low freq required.
MCG in BLPE
mode. CPU and
peripheral clocks
are gated off.
Off
Loose Reg
1
N/A
N/A
Off
Peripheral clocks
off. CPU clock on if
ENBDM=1.
1
ENBDM is located in the upper byte of the XCSR register which is write-accessible only through BDC commands, see Section
29.3.2, “Extended Configuration/Status Register (XCSR)”.
2 250 kHz maximum CPU frequency in LPrun; 125 kHz maximum peripheral clock frequency.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
3-3
Modes of Operation
Stop3
Stop4
Mode
Run
Wait
Stop2
LPrun
Regulator State
Run
Full On
Wait
Full On
Stop4
Full On
LPrun
Standby
LPwait
Standby
Stop3
Standby
Stop2
Partial Power Off
LPwait
Figure 3-2. Allowable Power Mode Transitions for Mission Mode
Figure 3-2 illustrates mission mode state transitions allowed between the legal states shown in Table 3-1.
RESET must be asserted low, or the TOD must issue a wakeup signal, in order to exit stop2. Only interrupt
assertion is necessary to exit the other stop and wait modes.
Figure 3-3 takes the same set of states and transitions shown in Figure 3-2 and adds the BDM halt mode
for development purposes. If BDM is enabled, the chip automatically shifts LP modes into their fully
regulated equivalents. If software or debugger sets SPMSC2[LPR] while BDM is enabled,
SPMSC2[LPRS] reflects the fact that the regulator is not in standby. Similarly, SPMSC2[PPDF] does not
indicate a recovery from stop2 if XCSR[ENBDM] forced stop4 to occur in its place.1
Stated another way, if XCSR[ENBDM] has been set via the BDM interface, then the power management
controller keeps (or puts) the regulator in full regulation despite other settings in the contrary. The states
shown in Figure 3-3 then map as follows:
• LPrun  Run
• LPwait  Wait
• Stop3  Stop4
• Stop2  Stop4
From a software perspective (and disregarding PMC status bits), the system remains in the appropriate
low-power state, and can be debugged as such.
See Section 3.7, “Wait Modes,” for a description of the various ways to enter halt mode.
1. This can have subtle impacts on recovery from stop. The IRQ input can wake the device from stop4 if it has been enabled for
that purpose. A low on the RESETB pin wakes the device from stop2 (there is an asynchronous path to the power management
controller in that state).
MCF51MM256 Series Devices Reference Manual, Rev. 3
3-4
Freescale Semiconductor
Modes of Operation
Stop4
Stop3
8
4
9
7
1
10
Halt
Run
Stop2
LPrun
2
6
11
Wait
5
LPwait
3
Figure 3-3. All Allowable Power Mode Transitions for
Table 3-2 defines triggers for the various state transitions shown in Figure 3-2.
Table 3-2. Triggers for State Transition
Transition #
From
To
Run
LPrun
Trigger
Configure settings shown in Table 3-1, switch
LPR=1 last
Clear SPMSC2[LPR]
1
LPrun
Run
Interrupt when SPMSC2[LPWUI]=1
Negative transition on enabled BKGD/MS pin.
Pre-configure settings shown in Table 3-1, execute
STOP instruction
Run
Stop2
Stop2
Run
LPrun
LPwait
Pre-configure settings shown in Table 3-1, execute
STOP instruction
LPwait
LPrun
Interrupt when SPMSC2[LPWUI]=0
LPrun
Stop3
Execute STOP instruction
Stop3
LPrun
Interrupt when SPMSC2[LPWUI]=0
LPwait
Run
Interrupt when SPMSC2[LPWUI]=1
Run
LPwait
Run
Wait
Pre-configure settings shown in Table 3-1, execute
STOP instruction
Wait
Run
Interrupt
Run
Stop4
Stop4
Run
2
3
Assert zero on IRQ,RESET1 or TOD timeout.
Reload environment from RAM.
4
5
6
7
Not supported.
Pre-configure settings shown in Table 3-1, execute
STOP instruction
Interrupt
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
3-5
Modes of Operation
Table 3-2. Triggers for State Transition
Transition #
From
To
Stop3
Run
8
Interrupt when SPMSC2[LPWUI]=1
Pre-configure settings shown in Table 3-1, execute
STOP instruction. The LP bit does not have to be
set prior to entering Stop3 in this fashion. But low
voltage interrupts and BDM must be disabled.
Run
Stop3
Stop4
Halt
Halt
Stop4
Halt
Run
GO instruction issued via BDM
Run
Halt
When a BACKGROUND command is received
through the BKGD/MS pin OR
When a HALT instruction is executed OR
When encountering a BDM breakpoint
Wait
Halt
When a BACKGROUND command is received
through the BKGD/MS pin (XCSR[ENBDM] must
equal one).
Halt
Wait
Not supported.
9
10
11
1
Trigger
When a BACKGROUND command is received
through the BKGD/MS pin (XCSR[ENBDM] must
equal one).
Not supported.
An analog connection from this pin to the on-chip regulator wakes up the regulator, which then initiates a
power-on-reset sequence.
Individual power states are discussed in more detail in the following sections.
3.4
Secure Mode
While the MCU is in secure mode, there are severe restrictions on which debug commands can be used.
In this mode, only the upper byte of the core’s XCSR, CSR2, and CSR3 registers can be accessed. See
Chapter 29, “Version 1 ColdFire Debug (CF1_DEBUG),” for details.
3.5
Bootloader Mode
Upon exiting reset, the CPU fetches the SR and PC from locations 0x0 and 0x4 out of the bootloader ROM
and executes code starting at the newly set value of the PC. While executing out of the bootloader several
qualification factors are examined to determine whether to continue executing bootloader code or begin
executing user code. The bootloader ROM can be accessed in bootloader mode or user mode. This section
describes the valid operations and protection mechanism in bootloader and user modes.
The following four items will be examined after each reset of the MCU.
• BLMS pin
• SIGNATURE semaphore byte
• Flash block CRC checksum
• CRC BYPASS byte
MCF51MM256 Series Devices Reference Manual, Rev. 3
3-6
Freescale Semiconductor
Modes of Operation
3.5.1
Entering Bootloader Mode
Bootloader mode can be entered in the following four conditions:
• When BLMS pin is low and BKGD/MS is not pulled low during power-on-reset (POR), the
bootloader mode is entered directly with no other qualifications.
• When BLMS pin and BKGD/MS are high during power-on-reset (POR), a CHECKSUM BYPASS
flash location is examined. If it is not equal to 0x00 or 0xFF, then the bootloader mode is entered.
• When BLMS pin and BKGD/MS are high during power-on-reset (POR), a CHECKSUM BYPASS
flash location is examined. If it is equal to 0xFF, a flash CRC is calculated for the flash array and
compared with a FLASHCRC 16-bit word. If the result does not match, then the bootloader mode
is entered.
• After a reset (other than a power-on reset), the SIGNATURE semaphore byte is examined. If it is
equal to 0xC3, then the bootloader mode is entered.
3.5.2
Entering User mode
User mode can be entered in the following three conditions:
• When BLMS pin and BKGD/MS are high during power-on-reset (POR), and the CHECKSUM
BYPASS byte is equal to 0x00, the user mode is entered.
• When BLMS pin and BKGD/MS are high during power-on-reset (POR), and the CHECKSUM
BYPASS byte is equal to 0xFF, a flash CRC is calculated for the flash array and compared with a
FLASHCRC 16-bit word. If the result matches, the user mode is entered.
• When a reset occurs (other than a power-on reset), if the SIGNATURE semaphore is not equal to
0xC3, the user mode is entered.
3.5.3
Active Background Mode and Bootloader Mode Arbitrage
During POR, if both BKGD/MS and BLMS pins are low, active background mode is entered.
3.5.4
Bootloader Operation
This section describes the bootloader mechanism and bootloader flow chart.
The bootloader software is located in bootloader ROM. You can perform flash erasing and programming
when:
• Bootloader mode is entered.
• Flash block checksum that has been calculated and flash block checksum do not match after
power-on reset.
• SIGNATURE value in register matches.
3.5.4.1
Flash Block Checksum
Upon power-on reset (POR), if BLMSS = 0 and the value of checksum bypass is 0xFF, the bootloader
calculates the flash checksum. The checksum is calculated for the Flash locations:
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
3-7
Modes of Operation
(0x0000_0000:0x0000_F7FF)
(0x0001_0800:0x0002_F7FF)
(0x0003_0800: 0x0003_FFFF)
The calculated checksum are verified with a checksum written to the two bytes of the flash (FLASHCRC).
If the checksum matches, the previous bootloader operation was successful and the MCU jumps to the user
code entry and starts to execute user code. If the checksum does not match, it jumps to bootloader entry to
wait for commands.
Flash block checksum calculation uses 16-bit CRC.
3.5.4.2
SIGNATURE Semaphore Register
After a reset (other than a power-on reset), the bootloader verifies SIGNATURE semaphore register. If
SIGNATURE = 0xC3, the MCU jumps to bootloader entry to wait for commands. If not, it jumps to the
user code entry and starts to execute user code.
Users are required to provide a mechanism in their application code to set the SIGNATURE to 0xC3 and
initiate a reset if they want to re-enter bootloader mode after a successful user code has been programmed.
Alternatively, BKGD mode can be entered and SIGNATURE can be updated using BDM commands and
reset initiated with BKGD pin high.
3.5.4.3
Flash Partial Erase Semaphore
The value of flash partial erase is programmed by the user. Only when flash partial erase is programmed
to 0x00, can the partial erase flash array command be supported by bootloader.
The value of this byte is 0xFF when the device is shipped from Freescale.
MCF51MM256 Series Devices Reference Manual, Rev. 3
3-8
Freescale Semiconductor
Modes of Operation
3.5.4.4
Boot Mode Entry Flow Chart
Start
Jump to bootrom
Regular reset
NO
SIGNATURE
=0xC3?
Power-on reset?
YES
NO
YES
Configure the primary flash array
Note: The flash array select bit in the SOPT3 register must be
configured as determined by the Non-Volatile Flash Array Select
Register
NO
Checksum bypass
=0xFF?
BLMSS=1?
YES
YES
Calculate Flash
block checksum
NO
Bootloader Mode entered
Change SIGNATURE=0xC3
Flash checksum
match?
YES
Jump to user code entry,
User code executed.
NO
Checksum bypass
=0x00?
NO
Change SIGNATURE=0xC3
Change SIGNATURE=0xC3
YES
Jump to user code entry,
User code executed.
Initial bus frequency to
24 MHz,
Initial USB
Jump to bootloader entry
Waiting for CMD
Note: Only when FLASH PARTIAL ERASE=0x00,
this command is valid.
CMD=Partial erase?
YES
Put Pass/Fail on stack
NO
CMD=Mass erase?
YES
Put Pass/Fail on stack
NO
CMD=Program Flash?
YES
Put Pass/Fail on stack
NO
NO
CMD=Reset?
YES
Clear SIGNATURE
Figure 3-4. Bootloader Flow Chart
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
3-9
Modes of Operation
3.6
3.6.1
Run Modes
Run Mode
Run mode is the normal operating mode for the MCF51MM256 series MCUs. This mode is selected after
any internal reset including LVD and when both the BKGD/MS and BLMS pins are high after a POR exit
or a BDC forced reset. Upon exiting reset, the CPU fetches the SR and PC from locations 0x0 and 0x4 out
of the bootloader ROM and executes code starting at the newly set value of the PC.
NOTE
CPU during reset will access the bootloader ROM at 0x0 and 0x4 but
non-reset CPU, multi-master or bdm accesses will read user Flash.
3.6.2
Low-Power Run Mode (LPrun)
In the low-power run mode, the on-chip voltage regulator is put into its standby (or loose regulation) state.
In this state, the power consumption is reduced to a minimum that allows CPU functionality. Power
consumption is reduced the most by disabling the clocks to all unused peripherals by clearing the
corresponding bits in the SCGC1 and SCGC2 registers1.
Before entering this mode, the following conditions must be met:
• BLPE2 is the selected clock mode for the MCG. For more information, see Table 39-14.
• MCGC2[HGO] is cleared.
• The bus frequency is less than 125 kHz.
• The ADC must be in low-power mode (ADLPC=1) or disabled.
• Low-voltage detect must be disabled. The LVDE and/or LVDSE bit in SPMSC1 register must be
cleared.
• Flash programming/erasing is not allowed
After these conditions are met, low-power run mode can be entered by setting SPMSC2[LPR].
To re-enter standard run mode, clear the LPR bit. SPMSC2[LPRS] is a read-only status bit that can be used
to determine if the regulator is in full-regulation mode or not. When LPRS is cleared, the regulator is in
full-regulation mode and the MCU can run at full speed in any clock mode.
Assuming that SOPT1[BKGDPE] is set to enable BKGD/MS, the device also switches from LPrun to run
mode when it detects a negative transition on the BKGD/MS pin.
Low-power run mode also provides the option to return to full regulation if any interrupt occurs. This is
done by setting SPMSC2[LPWUI]. The MCG can then be set for full speed immediately in the interrupt
service routine.
3.6.2.1
BDM in Low-Power Run Mode
Low-power run mode cannot be entered when the MCU is in active background debug mode.
1. System clock gating control registers 1 and 2
2. FLL bypassed external low-power
MCF51MM256 Series Devices Reference Manual, Rev. 3
3-10
Freescale Semiconductor
Modes of Operation
If a device is in low-power run mode, a falling edge on an active BKGD/MS pin exits low-power run mode,
clears the LPR and LPRS bits, and returns the device to normal run mode.
3.7
3.7.1
Wait Modes
Wait Mode
Wait mode is entered by executing a STOP instruction after configuring the device as per Table 3-1. If the
WAITE control bit is set when STOP is executed, the Wait mode is entered. Upon execution of the STOP
instruction, the CPU enters a low-power state in which it is not clocked.
The V1 ColdFire core does not differentiate between Stop and Wait modes. The difference between the
two is at the device level. In Stop mode, most peripheral clocks are shut down; in Wait mode, they continue
to run.
The ENBDM bit in the XCSR register must be set prior to entering Wait mode if the device is required to
respond to BDM instructions after in Wait mode.
The low voltage detector, if enabled, can be configured to interrupt the CPU and exit Wait mode into Run
mode.
When an interrupt request occurs, the CPU exits Wait mode and resumes processing, beginning with the
stacking operations leading to the interrupt service routine.
3.7.2
Low-Power Wait Mode (LPwait)
Low-power wait mode is entered by executing a STOP instruction while the MCU is in low-power run
mode and configured per Table 3-1. In the low-power wait mode, the on-chip voltage regulator remains in
its standby state as in the low-power run mode. In this state, the power consumption is reduced to a
minimum that allows most modules to maintain funtionality. Power consumption is reduced the most by
disabling the clocks to all unused peripherals by clearing the corresponding bits in the SCGC registers.
Low-power run mode restrictions also apply to low-power wait mode.
If the LPWUI bit is set when the STOP instruction is executed, the voltage regulator returns to full
regulation when wait mode is exited. The MCG can be set for full speed immediately in the interrupt
service routine.
If the LPWUI bit is cleared when the STOP instruction is executed, the device returns to low-power run
mode.
Any reset exits low-power wait mode, clears the LPR bit, and returns the device to normal run mode.
3.7.2.1
BDM in Low-Power Wait Mode
If a device is in low-power wait mode, a falling edge on an active BKGD/MS pin exits low-power wait
mode, clears the LPR and LPRS bits, and returns the device to normal run mode.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
3-11
Modes of Operation
3.8
Stop Modes
One of three Stop modes are entered upon execution of a STOP instruction when SOPT1[STOPE] is set.
SOPT1[WAITE] must be clear. In Stop3 mode, the bus and CPU clocks are halted. If the ENBDM bit is
set prior to entering Stop4, only the peripheral clocks are halted. The MCG module can be configured to
leave the reference clocks running. See Chapter 17, “Multipurpose Clock Generator (S08MCGV3)” for
more information.
NOTE
If neither the WAITE nor STOPE bit is set when the CPU executes a STOP
instruction, the MCU does not enter either of the stop modes. Instead, it
initiates an illegal opcode reset (if CPUCR[IRD]=0) or generates an illegal
instruction exception.
The Stop modes are selected by setting the appropriate bits in the SPMSC2 register. Table 3-1 shows all
of the control bits that affect mode selection under various conditions. The selected mode is entered
following the execution of a STOP instruction.
Entry into the active background mode from run mode is enabled if ENBDM in XCSR is set. Chapter 29,
“Version 1 ColdFire Debug (CF1_DEBUG)” explains this register. If ENBDM is set when the CPU
executes a STOP instruction, the system clocks to the background debug logic remain active, and the
peripheral clocks get gated, when the MCU enters stop mode. Because of this behavior, background debug
communication remains possible.
Most background commands are not available in Stop mode. The memory-access-with-status commands
do not allow memory access, but they report an error indicating that the MCU is in Stop or Wait mode. The
BACKGROUND command can be used to wake the MCU from Stop mode and enter Active Background
debug mode if the ENBDM bit is set prior to entering Stop mode. After entering background debug mode,
all background commands are available.
In addition, the MCG and XOSC continue operation in the clock configurations set prior to stop entry.
Also, the voltage regulator does not enter its low-power standby state, but maintains full internal
regulation.
PPDC
stop
STOPE
STOP2
WAITE
LVDE
LVDSE
STOP3
ENBDM
STOP4
Figure 3-5. Stop Modes
MCF51MM256 Series Devices Reference Manual, Rev. 3
3-12
Freescale Semiconductor
Modes of Operation
3.8.1
Stop2 Mode
Stop2 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1. Most
of the internal circuitry of the MCU is powered off in Stop2 mode, with the exception of the RAM. Upon
entering Stop2 mode, all I/O pin control signals are latched so that the pins retain their states during Stop2
mode. Exiting from Stop2 mode is performed by asserting either wake-up pin: RESET or IRQ.
NOTE
IRQ always functions as an active-low wakeup input when the MCU is in
Stop2 mode, regardless of how the pin is configured before entering Stop2
mode. The pullup on this pin is always disabled in Stop2 mode. This pin
must be driven or pulled high externally while in Stop2 mode.
In addition, the TOD interrupt can wake the MCU from Stop2 mode, if enabled and using the low power
oscillator (LPO). If the TOD is using the external clock source (EREFSTEN = 1) or internal clock source
(IREFSTEN = 1), then the TOD is disabled in Stop2 mode.
Upon wake-up from Stop2 mode, the MCU starts up as from a power-on reset (POR):
• All module control and status registers are reset.
• The LVD reset function is enabled, and the MCU remains in the reset state if VDD is below the
LVD trip point (low trip point selected due to POR).
• The CPU takes the reset vector.
In addition to the above, upon waking up from Stop2 mode, SPMSC2[PPDF] is set. This flag is used to
direct user code to go to a Stop2 recovery routine. PPDF remains set, and the I/O pin states remain latched
until a 1 is written to SPMSC2[PPDACK]. To maintain I/O states for pins that were configured as
general-purpose I/O before entering Stop2 mode, software must restore the contents of the I/O port
registers, which have been saved in RAM, to the port registers before writing to SPMSC2[PPDACK]. If
the port registers are not restored from RAM before writing to SPMSC2[PPDACK], then the pins switch
to their reset states when SPMSC2[PPDACK] is written.
For pins that were configured as peripheral I/O, software must reconfigure the peripheral module that
interfaces to the pin before writing to SPMSC2[PPDACK]. If the peripheral module is not enabled before
writing to SPMSC2[PPDACK], the pins are controlled by their associated port control registers when the
I/O latches are opened.
3.8.2
Stop3 Mode
Stop3 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1
(SPMSC2[PPDC] = 0 and SPMSC1[LVDSE] = 0). The states of all of the internal registers and logic,
RAM contents, and I/O pin states are maintained. Stop3 mode can be exited by asserting RESET, or by an
interrupt from one of the following sources: the USB resume interrupt, ADC, IRQ, KBI, or the ACMP. If
Stop3 mode is exited by means of the RESET pin, then the MCU is reset and operation resumes after taking
the reset vector. Exit by means of one of the internal interrupt sources results in the MCU taking the
appropriate interrupt vector.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
3-13
Modes of Operation
3.8.3
Stop4 Mode
Stop4 mode is entered by executing a STOP instruction under the conditions shown in Table 3-1
(SPMSC1[LVDSE]=1). The states of all of the internal registers and logic, RAM contents, and I/O pin
states are maintained. The MCG is configured to be running with the PLL or FLL engaged. Stop4 can be
exited by asserting RESET, or by an interrupt from one of the following sources: the Time of Day (TOD)
interrupt, the USB resume interrupt, LVD, ADC, IRQ, KBI, or the ACMP. If stop4 is exited by means of
the RESET pin, the MCU is reset and operation resumes after taking the reset vector. Exit by means of one
of the internal interrupt sources results in the MCU taking the appropriate interrupt vector.
3.8.3.1
LVD Enabled in Stop Mode
The LVD is capable of generating an interrupt or a reset when the supply voltage drops below the LVD
voltage. If the LVD is enabled in stop (SPMSC1[LVDE] && SPMSC1[LVDSE] = 1) at the time the CPU
executes a STOP instruction, then the voltage regulator remains active during Stop mode. If the user
attempts to enter Stop2 mode with the LVD enabled for Stop mode, the MCU enters Stop4 mode instead.
For the ADC to operate, the LVD must be left enabled when entering Stop4 mode. For the ACMP to
operate when PRACMPC1[PRGINS] is set, the VREF must be left enabled when entering Stop4. For the
OSC to operate with an external reference when MCGC2[RANGE] is set, the LVD must be left enabled
when entering Stop4 mode.
3.9
On-Chip peripheral Modules in Stop and Low-power Modes
When the MCU enters any stop mode (wait not included), system clocks to the internal peripheral modules
are stopped. Even in the exception case (ENBDM = 1), where clocks to the background debug logic
continue to operate, clocks to the peripheral systems are halted to reduce power consumption. Refer to
Section 3.8.1, “Stop2 Mode,” and Section 3.8.2, “Stop3 Mode,” for specific information on system
behavior in stop modes.
When the MCU enters LPwait or LPrun modes, system clocks to the internal peripheral modules continue
based on the settings of the clock gating control registers (SCGC1 and SCGC2).
Table 3-3 defines terms used in Table 3-4 to describe operation of components on the chip in the various
low-power modes.
Table 3-3. Abbreviations used in Table 3-4
1
Voltage Regulator
Clocked1
Not Clocked
Full Regulation
FullOn
FullNoClk
FullADACK2
Soft Regulation
SoftOn3
SoftNoClk
Disabled
SoftADACK4
Off
N/A
Off
Subject to module enables and settings of System Clock Gating Control Registers 1 and 2 (SCGC1 and
SCGC2).
MCF51MM256 Series Devices Reference Manual, Rev. 3
3-14
Freescale Semiconductor
Modes of Operation
2
This ADC-specific mode defines the case where the device is fully regulated and the normal peripheral clock
is stopped. In this case, the ADC can run using its internally generated asynchronous ADACK clock.
3
Analog modules must be in their low-power mode when the device is operated in this state.
4
This ADC-specific mode defines the case where the device is in soft regulation and the normal peripheral
clock is stopped. In this case, the ADC can only be run using its low-power mode and internally generated
asynchronous ADACK clock.
Table 3-4. Low-Power Mode Behavior
Mode
Peripheral
Stop2
Stop3
Stop4
LPwait
Wait
Run
LPrun
Off
Standby1
Standby
SoftNoClk
Standby
On
SoftOn
RAM
Standby
Standby
Standby
SoftNoClk
Standby
On
SoftOn
Flash
Off
Standby
Standby
SoftNoClk
On
On
SoftOn
Port I/O Registers
Off
Standby
Standby
SoftOn
On
On
SoftOn
Pin States
Held2
Standby
Standby
—
Standby
On
—
ADC,3
Off
On
On
SoftOn
On
On
SoftOn
ACMP
Off
On
On
SoftOn
On
On
SoftOn
BDC/BDM
Off
Standby
On
SoftOn
On
On
SoftOn
COP
Off
Standby
Standby
SoftOn
On
On
SoftOn
Optionally
On
Optionally On
On
All Modes
RANGE=0
HGO=0
On
All Modes
On
RANGE=0
HGO=0
MCG
Off
On4
On
—
On
On
—
SIM
Off
On
On
—
On
On
—
IIC
Off
Standby
Standby
SoftOn
On
On
SoftOn
IRQ
Off
(Wake Up
via POR)5
NoClk
(Wake Up)
NoClk
(Wake Up)
SoftOn
On
On
SoftOn
KBI
Off
NoClk
(Wake Up)
NoClk
(Wake Up)
SoftOn
On
On
SoftOn
LVD/LVW
Off
Standby
On
(Wake Up)
Disabled
On
On
Disabled
TOD
Optionally
On if using
XOSC1 or
LPO
enabled
On
(Wake Up)
On
(Wake Up)
—
On
On
—
SCIx
Off
Standby
Standby
SoftOn
On
On
SoftOn
SPIx
Off
Standby
Standby
SoftOn
On
On
SoftOn
DAC
Off
Standby
Standby
—
On
On
—
OPAMP
Off
On
On
—
On
On
—
TRIAMP
Off
On
On
—
On
On
—
VREF
Off
Standby
Standby
—
On
On
—
V1 ColdFire core
Mini-FlexBus
Crystal Oscillator
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
3-15
Modes of Operation
Table 3-4. Low-Power Mode Behavior (Continued)
Mode
Peripheral
Stop2
Stop3
Stop4
LPwait
Wait
Run
LPrun
USB (SIE and
Transceiver)
Off
Optionally On6
Optionally
On6
—
On
On
—
USB 3.3V
Regulator
Off
Optionally On7
Optionally
On7
—
On
On
—
TPMx
Off
Standby
Standby
SoftOn
On
On
SoftOn
CMT
Off
Standby
Standby
—
On
On
—
Parital
Shutdown.
1kHz osc if
enabled
On
On
SoftOn
1 kHz osc on
On
On
SoftOn
1 kHz osc on
Voltage Regulator
/ PMC
1
2
3
4
5
6
7
OFF=power off,clocks disabled; ON=power on,clocks enabled; Standby= power on, clocks disabled
This behavior is due to operation of the I/O cells in conjunction with the PMC. The Mini-Flexbus does not actually save state
during the transitions through stop2.
LVD must be enabled to run in stop if converting the bandgap channel.
User must select BLPI or BLPE prior to entering STOP3 mode.
The RESET pin also has a direct connection to the on-chip regulator wakeup input. Asserting a low on this pin while in STOP2
triggers the PMC to wakeup. As a result, the device undergoes a power-on-reset sequence.
USBEN in CTL is set, else off.
USBVREN in USBTRC0 is set to enable USB 3.3V Regulator, else off
3.10
Debug Mode
Debug mode functions are managed through the background debug controller (BDC) in the V1 ColdFire
core. The BDC provides the means for analyzing MCU operation during software development.
Debug commands are of two types:
• Non-intrusive commands, defined as commands that can be issued while the user program is
running. Non-intrusive commands can be issued through the BKGD pin while the MCU is in Run
mode; non-intrusive commands can also be executed when the MCU is in the Halt mode.
Non-intrusive commands include:
— Memory access commands
— Memory-access-with-status commands
— Debug register access commands
— Miscellaneous commands such as BACKGROUND, READ_PSTB, and SYNC_PC
• Active background commands, which can only be executed while the MCU is in Halt mode. Active
background commands include commands to:
— Read or write CPU registers
— Leave Halt mode to return to the user application program (GO)
The CPU Halt mode is entered in a number of ways:
• The BKGD/MS pin is low during POR
MCF51MM256 Series Devices Reference Manual, Rev. 3
3-16
Freescale Semiconductor
Modes of Operation
•
•
•
•
•
•
•
•
The BKGD/MS pin is low immediately after issuing a background debug force reset (see Section
29.3.3, “Configuration/Status Register 2 (CSR2),” for details)
A background debug force reset occurs and (CSR2[BDFR] = 1) and CSR2[BFHBR] = 1
A computer operating properly reset occurs and CSR2[COPHR] = 1
An illegal operand reset occurs and CSR2[IOPHR] = 1
An illegal address reset occurs and CSR2[IADHR] = 1
A BACKGROUND command is received through the BKGD/MS pin. If necessary, this wakes the
part from Stop/Wait modes
A HALT instruction is executed
Encountering a BDM breakpoint and the trigger response is programmable to generate a halt
While in Halt mode, CPU waits for serial background commands rather than executing instructions from
the user application program.
The BDC clock source is controlled by the XCSR[CLKSW] bit. When XCSR[CLKSW] is 1, the BDC
serial clock is BUSCLK. When XCSR[CLKSW] is 0, the BDC serial clock is MCGLCLK. This signal is
supplied from the on-chip DCO. Normally, MCGLCLK should be used when the device is in any of the
following clock modes: FBE, FEI, FBI, and FEE. The FLL clocks are not available when the device is in
BLPE and BLPI modes. In these cases, MCGOUT should be used.
The ENBDM bit determines whether the device can be placed in Halt mode, whether the CPU and BDC
serial clocks continue to run in Stop modes, and if the regulator can be placed into Standby mode. Again,
if booting to Halt mode, ENBDM and CLKSW are automatically set.
If ENBDM is cleared, the ColdFire core treats the HALT instruction as an illegal instruction and responds
with a reset event (if CPUCR[IRD] = 0) or a processor exception (if CPUCR[IRD] = 1).
When the XCSR[ENBDM] is set, the device can be restarted from Stop/Wait via the BDM interface.
Most users will not need to be aware of these nuances because they are normally visible only to the
development tools.
The debug interface is used to program a bootloader or user application program into the flash program
memory before the MCU is operated in Run mode for the first time. When the MCU is shipped from the
Freescale Semiconductor factory, the flash program memory is erased by default unless specifically noted,
so there is no program that could be executed in run mode until the flash memory is initially programmed.
The debug interface can also be used to erase and reprogram the flash memory after it has been previously
programmed.
For additional information about the debug interface, refer to Chapter 29, “Version 1 ColdFire Debug
(CF1_DEBUG).”
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
3-17
Modes of Operation
MCF51MM256 Series Devices Reference Manual, Rev. 3
3-18
Freescale Semiconductor
Chapter 4
Memory
4.1
MCF51MM256 Series Memory Map
As shown in Figure 4-1, on-chip memory in the MCF51MM256 series microcontrollers consists of RAM,
Boot ROM, space available for off chip expansion and flash program memory for nonvolatile data storage,
plus I/O and control/status registers.
MCF51MM128
MCF51MM256
CPU Address
CPU Address
0x(00)00_0000
0x(00)00_0000
Flash
0x(00)03_FFFF
0x(00)04_0000
256 KBytes
0x(00)01_FFFF
0x(00)02_0000
Reserved
Reserved
0x(00)30_0000
0x(00)30_0000
0x(00)30_1FFF
USB Boot ROM
0x(00)30_1FFF
Reserved
0x(00)3F_FFFF
0x(00)40_0000
Available for off-chip
expansion
Reserved
0x(00)3F_FFFF
0x(00)40_0000
Available for off-chip
expansion
RAM1
32 KBytes
0x(00)9F_FFFF
0x(00)A0_0000
0x(00)FF_7FFF
0x(00)FF_8000
0x(00)FF_FFFF
USB Boot ROM
0x(00)7F_FFFF
0x(00)80_0000
0x(00)7F_FFFF
0x(00)80_0000
0x(00)BF_FFFF
0x(00)C0_0000
0x(00)C0_000F
0x(00)C0_0010
Flash
128 KBytes
Available for
off-chip expansion
ColdFire RGPIO
Unimplemented
Slave
Peripherals
RAM1
32 KBytes
0x(00)9F_FFFF
0x(00)A0_0000
Available for
off-chip expansion
0x(00)BF_FFFF
0x(00)C0_0000
0x(00)C0_000F
0x(00)C0_0010
ColdFire RGPIO
Unimplemented
0x(00)FF_7FFF
0x(00)FF_8000
Slave
Peripherals
0x(00)FF_FFFF
1. RAM is wrapped and repeats every 0x7FFF. For
example, address 0x(00)80_0000 can also be
accessed at 0x(00)80_8000.
Figure 4-1. MCF51MM256 Series Memory Maps
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
4-1
Memory
Regions within the memory map are subject to restrictions with regard to the types of CPU accesses
allowed. These are outlined in Table 4-1. Non-supported access types terminate the bus cycle with an error
(and would typically generate a system reset in response to the error termination).
Table 4-1. CPU Access Type Allowed by Region
Read
Base Address
Write
Region
Byte
Word
Long
Byte
Word
Long
0x(00)00_0000
Flash
x
x
x
—
—
x
0x(00)30_0000
Boot ROM
x
x
x
—
—
—
0x(00)80_0000
RAM
x
x
x
x
x
x
0x(00)C0_0000
Rapid GPIO
x
x
x
x
x
x
0x(FF)FF_8000
Peripherals
x
x
x
x
x
x
0x(FF)FF_E800
Mini-FlexBus
x
x
x
x
x
x
Consistent with past ColdFire devices, flash configuration data is located at 0x(00)00_0400. The slave
peripherals section of the memory map is further broken into the following sub-sections:
0x(FF)FF_8000 – 0x(FF)FF_807F
Direct-page peripheral regs
0x(FF)FF_9800 – 0x(FF)FF_994F
High-page peripheral regs
0x(FF)FF_FFC0 – 0x(FF)FF_FFFF
Interrupt controller
The section of memory at 0x(00)C0_0000 is assigned for use by the ColdFire Rapid GPIO module. See
Table 4-7 for the rapid GPIO memory map and Chapter 9, “Rapid GPIO (RGPIO),” for further details on
the module.
The MCF51MM256 series microcontrollers use an 8-bit peripheral bus. The bus bridge from the ColdFire
system bus to the peripheral bus is capable of serializing 16-bit accesses into two 8-bit accesses and 32-bit
access into four 8-bit accesses. This can be used to speed access to properly aligned peripheral registers.
Not all peripheral registers are aligned to take advantage of this feature.
CPU accesses to those parts of the memory map marked as reserved in Figure 4-1 result in an illegal
address reset if CPUCR[ARD] = 0 or an address error exception if CPUCR[ARD] = 1.
The lower 32 Kbytes of flash memory and slave peripherals section of the memory map are most
efficiently accessed using the ColdFire absolute short addressing mode. RAM is most efficiently accessed
using the A5-relative addressing mode (address register indirect with displacement mode).
4.1.1
Register Addresses and Bit Assignments
Peripheral registers in the MCF51MM256 series microcontrollers are divided into two groups:
• Direct-page registers — located at 0x(FF)FF_8000 in the memory map.
• High-page registers — located at 0x(FF)FF_9800 in the memory map.
There is no functional advantage to locating peripherals in the direct page versus the high page peripheral
space for an MCF51MM256 series microcontroller. Both sets of registers may be efficiently accessed
MCF51MM256 Series Devices Reference Manual, Rev. 3
4-2
Freescale Semiconductor
Memory
using the ColdFire absolute short addressing mode. The areas are differentiated to maintain documentation
compatibility with the MC9S08MM128.
Peripheral register addresses for the MCF51MM256 series microcontrollers are shifted 0x(FF)FF_8000
compared with the MC9S08MM128 devices.
The ColdFire interrupt controller module is mapped in the peripheral space and occupies a 64-byte space
at the upper end of memory. Accordingly, its address decode is defined as
0x(FF)FF_FFC0–0x(FF)FF_FFFF. This 64-byte space includes the program-visible interrupt controller
registers as well as the space used for interrupt acknowledge (IACK) cycles.
There is a nonvolatile register area consisting of a block of 16 bytes in flash memory at
0x(00)00_0400–0x(00)00_040F. Nonvolatile register locations include:
— NVxPROT and NVxOPT are loaded into working registers at reset
— An 8-byte backdoor comparison key that optionally allows a user to gain controlled access to
secure memory
Because the nonvolatile register locations are flash memory, they must be erased and programmed like
other flash memory locations.
4.1.2
Detailed register addresses and bit assignments
Table 4-2 is a summary of all user-accessible direct-page registers and control bits.
In Table 4-2, the register names in column two are shown in bold to set them apart from the bit names to
the right. Cells that are not associated with named bits are shaded. A shaded cell with a 0 indicates this
unused bit always reads as a 0. Shaded cells with dashes indicate unused or reserved bit locations that could
read as 1s or 0s. When writing to these bits, write a 0 unless otherwise specified.
Recall that ColdFire has a big endian byte addressable memory architecture. The most significant byte of
each address is the lowest numbered as shown in Figure 4-2. Multi-byte operands (e.g., 16-bit words and
32-bit longwords) are referenced using an address pointing to the most significant (first) byte.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
4-3
Memory
31
24
23
16
15
8
7
0
Longword 0x(00)00_0000
Word 0x(00)00_0000
Byte 0x(00)00_0000
Word 0x(00)00_0002
Byte 0x(00)00_0001
Byte 0x(00)00_0002
Byte 0x(00)00_0003
Longword 0x(00)00_0004
Word 0x(00)00_0004
Byte 0x(00)00_0007
...
Byte 0x(00)00_0006
...
Byte 0x(00)00_0005
...
Byte 0x(00)00_0004
Word 0x(00)00_0006
Longword 0x(FF)FF_FFFC
Word 0x(FF)FF_FFFC
Byte 0x(FF)FF_FFFC
Word 0x(FF)FF_FFFE
Byte 0x(FF)FF_FFFD
Byte 0x(FF)FF_FFFE
Byte 0x(FF)FF_FFFF
Figure 4-2. ColdFire Memory Organization
Table 4-2. Direct-Page Register Summary
Address
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x(FF)FF_8000
PTAD
PTAD7
PTAD6
PTAD5
PTAD4
PTAD3
PTAD2
PTAD1
PTAD0
0x(FF)FF_8001
PTADD
PTADD7
PTADD6
PTADD5
PTADD4
PTADD3
PTADD2
PTADD1
PTADD0
0x(FF)FF_8002
PTBD
PTBD7
PTBD6
PTBD5
PTBD4
PTBD3
PTBD2
PTBD1
PTBD0
0x(FF)FF_8003
PTBDD
PTBDD7
PTBDD6
PTBDD5
PTBDD4
PTBDD3
PTBDD2
PTBDD1
PTBDD0
0x(FF)FF_8004
PTCD
PTCD7
PTCD6
PTCD5
PTCD4
PTCD3
PTCD2
PTCD1
PTCD0
0x(FF)FF_8005
PTCDD
PTCDD7
PTCDD6
PTCDD5
PTCDD4
PTCDD3
PTCDD2
PTCDD1
PTCDD0
0x(FF)FF_8006
PTDD
PTDD7
PTDD6
PTDD5
PTDD4
PTDD3
PTDD2
PTDD1
PTDD0
0x(FF)FF_8007
PTDDD
PTDDD7
PTDDD6
PTDDD5
PTDDD4
PTDDD3
PTDDD2
PTDDD1
PTDDD0
0x(FF)FF_8008(FF)FF_800F
RESERVED
—
—
—
—
—
—
—
—
0x(FF)FF_8010
DACDAT0H
DDAT0[15:8]
0x(FF)FF_8011
DACDAT0L
DDAT0[7:0]
0x(FF)FF_8012
DACDAT1H
DDAT1[15:8]
0x(FF)FF_8013
DACDAT1L
DDAT1[7:0]
0x(FF)FF_8014
DACDAT2H
DDAT2[15:8]
0x(FF)FF_8015
DACDAT2L
DDAT2[7:0]
0x(FF)FF_8016
DACDAT3H
DDAT3[15:8]
0x(FF)FF_8017
DACDAT3L
DDAT3[7:0]
0x(FF)FF_8018
DACDAT4H
DDAT4[15:8]
0x(FF)FF_8019
DACDAT4L
DDAT4[7:0]
MCF51MM256 Series Devices Reference Manual, Rev. 3
4-4
Freescale Semiconductor
Memory
Table 4-2. Direct-Page Register Summary (Continued)
Address
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x(FF)FF_801A
DACDAT5H
DDAT5[15:8]
0x(FF)FF_801B
DACDAT5L
DDAT5[7:0]
0x(FF)FF_801C
DACDAT6H
DDAT6[15:8]
0x(FF)FF_801D
DACDAT6L
DDAT6[7:0]
0x(FF)FF_801E
DACDAT7H
DDAT7[15:8]
0x(FF)FF_801F
DACDAT7L
DDAT7[7:0]
0x(FF)FF_8020
DACDAT8H
DDAT8[15:8]
0x(FF)FF_8021
DACDAT8L
DDAT8[7:0]
0x(FF)FF_8022
DACDAT9H
DDAT9[15:8]
0x(FF)FF_8023
DACDAT9L
DDAT9[7:0]
0x(FF)FF_8024
DACDAT10H
DDAT10[15:8]
0x(FF)FF_8025
DACDAT10L
DDAT10[7:0]
0x(FF)FF_8026
DACDAT11H
DDAT11[15:8]
0x(FF)FF_8027
DACDAT11L
DDAT11[7:0]
0x(FF)FF_8028
DACDAT12H
DDAT12[15:8]
0x(FF)FF_8029
DACDAT12L
DDAT12[7:0]
0x(FF)FF_802A
DACDAT13H
DDAT13[15:8]
0x(FF)FF_802B
DACDAT13L
DDAT13[7:0]
0x(FF)FF_802C
DACDAT14H
DDAT14[15:8]
0x(FF)FF_802D
DACDAT14L
DDAT14[7:0]
0x(FF)FF_802E
DACDAT15H
DDAT15[15:8]
0x(FF)FF_802F
DACDAT15L
DDAT15[7:0]
0x(FF)FF_8030
DACS
0
0
0
0
0
DACWM
DACRPT
DACRPB
0x(FF)FF_8031
DACC0
DACEN
DACRFS
DACTSEL
DACSTRG
LPEN
DACWIE
DACTIE
DACBIE
0x(FF)FF_8032
DACC1
0
0
0
0x(FF)FF_8033
DACC2
0x(FF)FF_8034
PRACMPCS
ACEN
0x(FF)FF_8035
PRACMPC0
0
0x(FF)FF_8036
PRACMPC1
PRGEN
PRGINS
0
PRGOS4
PRGOS3
PRGOS2
PRGOS1
PRGOS0
0x(FF)FF_8037
PRACMPC2
0
ACIPE6
ACIPE5
ACIPE4
ACIPE3
ACIPE2
ACIPE1
ACIPE0
0x(FF)FF_8038
MCGC1
CLKS
IREFS
IRCLKEN
IREFSTEN
0x(FF)FF_8039
MCGC2
BDIV
EREFS
ERCLKEN
EREFSTEN
0x(FF)FF_803A
MCGTRM
0x(FF)FF_803B
MCGSC
LOLS
LOCK
PLLST
IREFST
OSCINIT
FTRIM
0x(FF)FF_803C
MCGC3
LOLIE
PLLS
CME
DIV32
DACBFWM
DACBFMD
DACBFRP
ACMPF
DACBFE
DACBFUP
0
ACOPE
ACMPO
ACPSEL
ACINTS
0
ACNSEL
RDIV
RANGE
HGO
ACIEN
LP
TRIM
CLKST
VDIV
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
4-5
Memory
Table 4-2. Direct-Page Register Summary (Continued)
Address
Name
Bit 7
6
5
4
3
2
0x(FF)FF_803D
MCGC4
0
0
DMX32
0
0
0
0x(FF)FF_803E0x(FF)FF_803F
RESERVED
—
—
—
—
—
—
0x(FF)FF_8040
ADCSC1A
COCOA
AIENA
DIFFA
ADCHA
0x(FF)FF_8041
ADCSC1B
COCOB
AIENB
DIFFB
ADCHB
0x(FF)FF_8042
ADCSC1C
COCOC
AIENC
DIFFC
ADCHC
0x(FF)FF_8043
ADCSC1D
COCOD
AIEND
DIFFD
ADCHD
0x(FF)FF_8044
ADCSC1E
COCOE
AIENE
DIFFE
ADCHE
0x(FF)FF_8045
ADCSC1F
COCOF
AIENF
DIFFF
ADCHF
0x(FF)FF_8046
ADCSC1G
COCOG
AIENG
DIFFG
ADCHG
0x(FF)FF_8047
ADCSC1H
COCOH
AIENH
DIFFH
ADCHH
0x(FF)FF_8048
ADCCFG1
ADLPC
0x(FF)FF_8049
ADCCFG2
0
0x(FF)FF_804A
ADCRHA
DA[15:8]
0x(FF)FF_804B
ADCRLA
DA[7:0]
0x(FF)FF_804C
ADCRHB
DB[15:8]
0x(FF)FF_804D
ADCRLB
DB[7:0]
0x(FF)FF_804E
ADCRHC
DC[15:8]
0x(FF)FF_804F
ADCRLC
DC[7:0]
0x(FF)FF_8050
ADCRHD
DD[15:8]
0x(FF)FF_8051
ADCRLD
DD[7:0]
0x(FF)FF_8052
ADCRHE
DE[15:8]
0x(FF)FF_8053
ADCRLE
DE[7:0]
0x(FF)FF_8054
ADCRHF
DF[15:8]
0x(FF)FF_8055
ADCRLF
DF[7:0]
0x(FF)FF_8056
ADCRHG
DG[15:8]
0x(FF)FF_8057
ADCRLG
DG[7:0]
0x(FF)FF_8058
ADCRHH
DH[15:8]
0x(FF)FF_8059
ADCRLH
DH[7:0]
0x(FF)FF_805A0x(FF)FF_805B
RESERVED
0x(FF)FF_805C
VREFTRM
0x(FF)FF_805D
VREFSC
VREFEN
0
0
0x(FF)FF_805E
RESERVED
—
—
0x(FF)FF_805F
IRQSC
0
IRQPDD
—
ADIV
0
—
ADLSMP
0
—
1
Bit 0
DRST / DRS
—
MODE
0
ADACKEN
—
—
ADICLK
ADHSC
ADLSTS
—
—
—
—
0
0
VREFST
—
—
—
—
—
—
IRQEDG
IRQPE
IRQF
IRQACK
IRQIE
IRQMOD
TRM
MODE
MCF51MM256 Series Devices Reference Manual, Rev. 3
4-6
Freescale Semiconductor
Memory
Table 4-2. Direct-Page Register Summary (Continued)
Address
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x(FF)FF_8060
IICA1
AD7
AD6
AD5
AD4
AD3
AD2
AD1
0
0x(FF)FF_8061
IICF
0x(FF)FF_8062
IICC1
IICEN
IICIE
MST
TX
TXAK
RSTA
0
0
0x(FF)FF_8063
IICS
TCF
IAAS
BUSY
ARBL
0
SRW
IICIF
RXAK
0x(FF)FF_8064
IICD
0x(FF)FF_8065
IICC2
GCAEN
ADEXT
0
0
0
AD10
AD9
AD8
0x(FF)FF_8066
IICSMB
FACK
ALERTEN
SIICAEN
TCKSEL
SLTF
SHTF
0
0
0x(FF)FF_8067
IICA2
SAD7
SAD6
SAD5
SAD4
SAD3
SAD2
SAD1
0
0x(FF)FF_8068
IICSLTH
SSLT15
SSLT14
SSLT13
SSLT12
SSLT11
SSLT10
SSLT9
SSLT8
0x(FF)FF_8069
IICSLTL
SSLT7
SSLT6
SSLT5
SSLT4
SSLT3
SSLT2
SSLT1
SSLT0
0x(FF)FF_806A
IICFLT
0
0
0
0
FLT3
FLT2
FLT1
FLT0
0x(FF)FF_806B
RESERVED
—
—
—
—
—
—
—
—
0x(FF)FF_806C
KBI1SC
0
0
0
0
KB1F
KB1ACK
KB1IE
KBI1MOD
0x(FF)FF_806D
KBI1PE
KBI1PE7
KBI1PE6
KBI1PE5
KBI1PE4
KBI1PE3
KBI1PE2
KBI1PE1
KBI1PE0
0x(FF)FF_806E
KBI1ES
KB1EDG7
KB1EDG6
KB1EDG5
KB1EDG4
KB1EDG3
KB1EDG2
KB1EDG1
KB1EDG0
0x(FF)FF_806F
RESERVED
—
—
—
—
—
—
—
—
0x(FF)FF_8070
SPI1C1
SPIE
SPE
SPTIE
MSTR
CPOL
CPHA
SSOE
LSBFE
0x(FF)FF_8071
SPI1C2
SPMIE
SPIMODE
0
MODFEN
BIDIROE
0
SPISWAI
SPC0
0x(FF)FF_8072
SPI1BR
0
SPPR2
SPPR1
SPPR0
SPR3
SPR2
SPR1
SPR0
0x(FF)FF_8073
SPI1S
SPRF
SPMF
SPTEF
MODF
RNFULLF
TNEARF
TXFULLF
RFIFOEF
0x(FF)FF_8074
SPI1DH
Bit 15
14
13
12
11
10
9
Bit 8
0x(FF)FF_8075
SPI1DL
Bit 7
6
5
4
3
2
1
Bit 0
0x(FF)FF_8076
SPI1MH
Bit 15
14
13
12
11
10
9
Bit 8
0x(FF)FF_8077
SPI1ML
Bit 7
6
5
4
3
2
1
Bit 0
0x(FF)FF_8078
SPI1C3
0
0
TNEAREF
MARK
RNFULL
MARK
INTCLR
TNEARIEN
RNFULLIEN
FIFOMODE
0x(FF)FF_8079
SPI1CI
TXFERR
RXFERR
TXFOF
RXFOF
TNEAREFCI
RNFULLFCI
SPTEFCI
SPRFCI
0x(FF)FF_807A0x(FF)FF_807B
RESERVED
—
—
—
—
—
—
—
—
0x(FF)FF_807C
KBI2SC
0
0
0
0
KB2F
KB2ACK
KB2IE
KBI2MOD
0x(FF)FF_807D
KBI2PE
KBI2PE7
KBI2PE6
KBI2PE5
KBI2PE4
KBI2PE3
KBI2PE2
KBI2PE1
KBI2PE0
0x(FF)FF_807E
KBI2ES
KB2EDG7
KB2EDG6
KB2EDG5
KB2EDG4
KB2EDG3
KB2EDG2
KB2EDG1
KB2EDG0
0x(FF)FF_807F
RESERVED
—
—
—
—
—
—
—
—
MULT
ICR
DATA
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
4-7
Memory
Table 4-3. High-Page Register Summary
Address
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x(FF)FF_9800
SRS
POR
PIN
COP
ILOP
ILAD
LOC
LVD
0
0x(FF)FF_9801
Reserved
—
—
—
—
—
—
—
—
0x(FF)FF_9802
SOPT1
COPT1
COPT0
STOPE
WAITE
BLMSS
MBSL
BKGDPE
RSTPE
0x(FF)FF_9803
SOPT2
COPCLKS
COPW
USB_BIGEN
D
CLKOUT_EN
CMT_CLK_SE
L
—
—
ACIC
0x(FF)FF_98040x(FF)FF_9805
Reserved
—
—
—
—
—
—
—
—
0x(FF)FF_9806
SDIDH
ID11
ID10
ID9
ID8
0x(FF)FF_9807
SDIDL
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
0x(FF)FF_9808
SCGC1
CMT
TPM2
TPM1
ADC
DAC
IIC
SCI2
SCI1
0x(FF)FF_9809
SCGC2
USB
PDB
IRQ
KBI
PRACMP
MFB
SPI2
SPI1
0x(FF)FF_980A
SCGC3
VREF
CRC
FLS2
FLS1
TRIAMP2
TRIAMP1
GPOA2
GPOA1
0x(FF)FF_980B
SOPT3
SCI2PS
SCI1PS
IICPS
USBPS
MB_DATA
ARRAYSEL
SCI1_PAD
CMT_PAD
0x(FF)FF_980C
SOPT4
—
FBALEEN
FBAD12FE
FBAD12PUE
FBAD12SRE
FBAD12DSE
IROSRE
IRODSE
0x(FF)FF_980D
SOPT51
—
—
—
0x(FF)FF_980E
SIMIPS
ADCTRS
RX1N
—
—
MODTX1
0x(FF)FF_980F
SIGNATURE
0x(FF)FF_9810
CCSCTRL
0x(FF)FF_9811
CCSTMR1
CNT1
0x(FF)FF_9812
CCSTMR2
CNT2
0x(FF)FF_9813
CCSTMRIR
CNTIR
0x(FF)FF_9814
FPROTD
—
—
—
0x(FF)FF_9815
MFBPC1
MFBPEN_AD7
MFBPEN_AD6
0x(FF)FF_9816
MFBPC2
MFBPEN_AD1
5
0x(FF)FF_9817
MFBPC3
0x(FF)FF_9818
REV
—
—
MTBASE1
SIGNATURE SEMAPHORE
RANGE1
HGO1
ERCLKEN1
OSCINIT1
EREFS1
EN
TEST
SEL
—
—
—
—
FPDIS
MFBPEN_AD5
MFBPEN_AD4
MFBPEN_AD3
MFBPEN_AD2
MFBPEN_AD1
MFBPEN_AD0
MFBPEN_AD1
4
MFBPEN_AD1
3
MFBPEN_AD12
MFBPEN_AD11
MFBPEN_AD1
0
MFBPEN_AD9
MFBPEN_AD8
MFBPEN_D3
MFBPEN_D2
MFBPEN_D1
MFBPEN_D0
MFBPEN_AD19
MFBPEN_AD1
MFBPEN_AD17 MFBPEN_AD16
8
MFBPC4
EN_CS1
EN_CS0
EN_OE
EN_RW
MFBPEN_D7
0x(FF)FF_9819
SIMCO
—
—
—
—
—
0x(FF)FF_981A0x(FF)FF_981B
Reserved
—
—
—
—
—
—
—
—
0x(FF)FF_981C
SPMSC1
LVDF
LVDACK
LVDIE
LVDRE
LVDSE
LVDE
0
BGBE
0x(FF)FF_981D
SPMSC2
LPR
LPRS
LPWUI
0
PPDF
PPDACK
PPDE
PPDC
0x(FF)FF_981E
Reserved
—
—
—
—
—
—
—
—
0x(FF)FF_981F
SPMSC3
LVwF
LVWACK
LVDV
LVWV
LVWIE
0
0
0
0x(FF)FF_98200x(FF)FF_982F
Reserved
—
—
—
—
—
—
—
—
MFBPEN_D6
MFBPEN_D5
MFBPEN_D4
CS
MCF51MM256 Series Devices Reference Manual, Rev. 3
4-8
Freescale Semiconductor
Memory
Table 4-3. High-Page Register Summary (Continued)
Address
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x(FF)FF_9830
PTED
PTED7
PTED6
PTED5
PTED4
PTED3
PTED2
PTED1
PTED0
0x(FF)FF_9831
PTEDD
PTEDD7
PTEDD6
PTEDD5
—
PTEDD3
PTEDD2
PTEDD1
PTEDD0
0x(FF)FF_9832
PTFD
PTFD7
PTFD6
PTFD5
PTFD4
PTFD3
PTFD2
PTFD1
PTFD0
0x(FF)FF_9833
PTFDD
PTFDD7
PTFDD6
PTFDD5
PTFDD4
PTFDD3
PTFDD2
PTFDD1
PTFDD0
0x(FF)FF_98340x(FF)FF_9837
Reserved
—
—
—
—
—
—
—
—
0x(FF)FF_9838
SCI2BDH
LBKDIE
RXEDGIE
0
SBR12
SBR11
SBR10
SBR9
SBR8
0x(FF)FF_9839
SCI2BDL
SBR7
SBR6
SBR5
SBR4
SBR3
SBR2
SBR1
SBR0
0x(FF)FF_983A
SCI2C1
LOOPS
SCISWAI
RSRC
M
WAKE
ILT
PE
PT
0x(FF)FF_983B
SCI2C2
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
0x(FF)FF_983C
SCI2S1
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
0x(FF)FF_983D
SCI2S2
LBKDIF
RXEDGIF
0
RXINV
RWUID
BRK13
LBKDE
RAF
0x(FF)FF_983E
SCI2C3
R8
T8
TXDIR
TXINV
ORIE
NEIE
FEIE
PEIE
0x(FF)FF_983F
SCI2D
Bit 7
6
5
4
3
2
1
Bit 0
0x(FF)FF_9840
SPI2C1
SPI2E
SP2E
SP2TIE
MSTR
CPOL
CPHA
SSOE
LSBFE
0x(FF)FF_9841
SPI2C2
SPMIE
0
0
MODFEN
BIDIROE
0
SPI2SWAI
SP2C0
0x(FF)FF_9842
SPI2BR
0
SP2PR2
SP2PR1
SP2PR0
SP2R3
SP2R2
SP2R1
SP2R0
0x(FF)FF_9843
SPI2S
SP2RF
0
SP2TEF
MODF
0
0
0
0
0x(FF)FF_9844
Reserved
—
—
—
—
—
—
—
—
0x(FF)FF_9845
SPI2D
Bit 7
6
5
4
3
2
1
Bit 0
0x(FF)FF_9846
Reserved
—
—
—
—
—
—
—
—
0x(FF)FF_9847
SPI2MR
Bit 7
6
5
4
3
2
1
Bit 0
0x(FF)FF_9848
PTGD
PTGD7
PTGD6
PTGD5
PTGD4
PTGD3
PTGD2
PTGD1
PTGD0
0x(FF)FF_9849
PTGDD
PTGDD7
PTGDD6
PTGDD5
PTGDD4
PTGDD3
PTGDD2
PTGDD1
PTGDD0
0x(FF)FF_984A0x(FF)FF_984F
Reserved
—
—
—
—
—
—
—
—
0x(FF)FF_9850
PTAPE
PTAPE7
PTAPE6
PTAPE5
PTAPE4
PTAPE3
PTAPE2
PTAPE1
PTAPE0
0x(FF)FF_9851
PTASE
PTASE7
PTASE6
PTASE5
PTASE4
PTASE3
PTASE2
PTASE1
PTASE0
0x(FF)FF_9852
PTADS
PTADS7
PTADS6
PTADS5
PTADS4
PTADS3
PTADS2
PTADS1
PTADS0
0x(FF)FF_9853
PTAIFE
PTAIFE7
PTAIFE6
PTAIFE5
PTAIFE4
PTAIFE3
PTAIFE2
PTAIFE1
PTAIFE0
0x(FF)FF_9854
PTBPE
PTBPE7
PTBPE6
PTBPE5
PTBPE4
PTBPE3
PTBPE2
PTBPE1
PTBPE0
0x(FF)FF_9855
PTBSE
PTBSE7
PTBSE6
PTBSE5
PTBSE4
PTBSE3
PTBSE2
PTBSE1
PTBSE0
0x(FF)FF_9856
PTBDS
PTBDS7
PTBDS6
PTBDS5
PTBDS4
PTBDS3
PTBDS2
PTBDS1
PTBDS0
0x(FF)FF_9857
PTBIFE
PTBIFE7
PTBIFE6
PTBIFE5
PTBIFE4
PTBIFE3
PTBIFE2
PTBIFE1
PTBIFE0
0x(FF)FF_9858
PTCPE
PTCPE7
PTCPE6
PTCPE5
PTCPE4
PTCPE3
PTCPE2
PTCPE1
PTCPE0
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
4-9
Memory
Table 4-3. High-Page Register Summary (Continued)
Address
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x(FF)FF_9859
PTCSE
PTCSE7
PTCSE6
PTCSE5
PTCSE4
PTCSE3
PTCSE2
PTCSE1
PTCSE0
0x(FF)FF_985A
PTCDS
PTCDS7
PTCDS6
PTCDS5
PTCDS4
PTCDS3
PTCDS2
PTCDS1
PTCDS0
0x(FF)FF_985B
PTCIFE
PTCIFE7
PTCIFE6
PTCIFE5
PTCIFE4
PTCIFE3
PTCIFE2
PTCIFE1
PTCIFE0
0x(FF)FF_985C
PTDPE
PTDPE7
PTDPE6
PTDPE5
PTDPE4
PTDPE3
PTDPE2
PTDPE1
PTDPE0
0x(FF)FF_985D
PTDSE
PTDSE7
PTDSE6
PTDSE5
PTDSE4
PTDSE3
PTDSE2
PTDSE1
PTDSE0
0x(FF)FF_985E
PTDDS
PTDDS7
PTDDS6
PTDDS5
PTDDS4
PTDDS3
PTDDS2
PTDDS1
PTDDS0
0x(FF)FF_985F
PTDIFE
PTDIFE7
PTDIFE6
PTDIFE5
PTDIFE4
PTDIFE3
PTDIFE2
PTDIFE1
PTDIFE0
0x(FF)FF_9860
PTEPE
PTEPE7
PTEPE6
PTEPE5
PTEPE4
PTEPE3
PTEPE2
PTEPE1
PTEPE0
0x(FF)FF_9861
PTESE
PTESE7
PTESE6
PTESE5
PTESE4
PTESE3
PTESE2
PTESE1
PTESE0
0x(FF)FF_9862
PTEDS
PTEDS7
PTEDS6
PTEDS5
PTEDS4
PTEDS3
PTEDS2
PTEDS1
PTEDS0
0x(FF)FF_9863
PTEIFE
PTEIFE7
PTEIFE6
PTEIFE5
PTEIFE4
PTEIFE3
PTEIFE2
PTEIFE1
PTEIFE0
0x(FF)FF_9864
PTFPE
PTFPE7
PTFPE6
PTFPE5
PTFPE4
PTFPE3
PTFPE2
PTFPE1
PTFPE0
0x(FF)FF_9865
PTFSE
PTFSE7
PTFSE6
PTFSE5
PTFSE4
PTFSE3
PTFSE2
PTFSE1
PTFSE0
0x(FF)FF_9866
PTFDS
PTFDS7
PTFDS6
PTFDS5
PTFDS4
PTFDS3
PTFDS2
PTFDS1
PTFDS0
0x(FF)FF_9867
PTFIFE
PTFIFE7
PTFIFE6
PTFIFE5
PTFIFE4
PTFIFE3
PTFIFE2
PTFIFE1
PTFIFE0
0x(FF)FF_9868
PTGPE
PTGPE7
PTGPE6
PTGPE5
PTGPE4
PTGPE3
PTGPE2
PTGPE1
PTGPE0
0x(FF)FF_9869
PTGSE
PTGSE7
PTGSE6
PTGSE5
PTGSE4
PTGSE3
PTGSE2
PTGSE1
PTGSE0
0x(FF)FF_986A
PTGDS
PTGDS7
PTGDS6
PTGDS5
PTGDS4
PTGDS3
PTGDS2
PTGDS1
PTGDS0
0x(FF)FF_986B
PTGIFE
PTGIFE7
PTGIFE6
PTGIFE5
PTGIFE4
PTGIFE3
PTGIFE2
PTGIFE1
PTGIFE0
0x(FF)FF_986C
TIAMP1C0
TIAMPEN
LPEN
—
—
—
—
—
—
0x(FF)FF_986D
Reserved
—
—
—
—
—
—
—
—
0x(FF)FF_986E
TIAMP2C0
TIAMPEN
LPEN
—
—
—
—
—
—
0x(FF)FF_986F
Reserved
—
—
—
—
—
—
—
—
0x(FF)FF_9870
CMTCGH1
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
0x(FF)FF_9871
CMTCGL1
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
0x(FF)FF_9872
CMTCGH2
SH7
SH6
SH5
SH4
SH3
SH2
SH1
SH0
0x(FF)FF_9873
CMTCGL2
SL7
SL6
SL5
SL4
SL3
SL2
SL1
SL0
0x(FF)FF_9874
CMTOC
IROL
CMTPOL
IROPEN
0
0
0
0
0
0x(FF)FF_9875
CMTMSC
EOCF
CMTDIV1
CMTDIV0
EXSPC
BASE
FSK
EOCIE
MCGEN
0x(FF)FF_9876
CMTCMD1
MB15
MB14
MB13
MB12
MB11
MB10
MB9
MB8
0x(FF)FF_9877
CMTCMD2
MB7
MB6
MB5
MB4
MB3
MB2
MB1
MB0
0x(FF)FF_9878
CMTCMD3
SB15
SB14
SB13
SB12
SB11
SB10
SB9
SB8
0x(FF)FF_9879
CMTCMD4
SB7
SB6
SB5
SB4
SB3
SB2
SB1
SB0
0x(FF)FF_987A0x(FF)FF_987B
Reserved
—
—
—
—
—
—
—
—
MCF51MM256 Series Devices Reference Manual, Rev. 3
4-10
Freescale Semiconductor
Memory
Table 4-3. High-Page Register Summary (Continued)
Address
Name
Bit 7
6
5
4
3
2
0x(FF)FF_987C
GPAMP1C0
GPAMPEN
LPEN
—
—
—
—
0x(FF)FF_987D
GPAMP1C1
—
—
—
AMPRF2
AMPRF1
AMPRF0
AMPRI1
AMPRI0
0x(FF)FF_987E
GPAMP1C2
AMPPSEL2
AMPPSEL1
AMPPSEL0
AMPNSEL2
AMPNSEL1
AMPNSEL0
0x(FF)FF_987F0x(FF)FF_988F
Reserved
—
—
—
—
—
—
—
—
0x(FF)FF_9890
CRCH
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
0x(FF)FF_9891
CRCL
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x(FF)FF_9892
Transpose
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x(FF)FF_98930x(FF)FF_9897
Reserved
—
—
—
—
—
—
—
—
0x(FF)FF_9898
GPAMP2C0
GPAMPEN
LPEN
—
—
—
—
0x(FF)FF_9899
GPAMP2C1
—
—
—
AMPRF2
AMPRF1
AMPRF0
AMPRI1
AMPRI0
0x(FF)FF_989A
GPAMP2C2
—
AMPPSEL2
AMPPSEL1
AMPPSEL0
—
AMPNSEL2
AMPNSEL1
AMPNSEL0
0x(FF)FF_989B
Reserved
—
—
—
—
—
—
—
—
0x(FF)FF_989C
TODC
TODEN
TODR
TODCLKEN
0x(FF)FF_989D
TODSC
QSECF
QSECIE
SECIE
0x(FF)FF_989E
TODM
0x(FF)FF_989F
TODCNT
0x(FF)FF_98A0
TPM2SC
TOF
TOIE
CPWMS
CLKSB
CLKSA
PS2
PS1
PS0
0x(FF)FF_98A1
TPM2CNTH
Bit 15
14
13
12
11
10
9
Bit 8
0x(FF)FF_98A2
TPM2CNTL
Bit 7
6
5
4
3
2
1
Bit 0
0x(FF)FF_98A3
TPM2MODH
Bit 15
14
13
12
11
10
9
Bit 8
0x(FF)FF_98A4
TPM2MODL
Bit 7
6
5
4
3
2
1
Bit 0
0x(FF)FF_98A5
TPM2C0SC
CH0F
CH0IE
MS0B
MS0A
ELS0B
ELS0A
0
0
0x(FF)FF_98A6
TPM2C0VH
Bit 15
14
13
12
11
10
9
Bit 8
0x(FF)FF_98A7
TPM2C0VL
Bit 7
6
5
4
3
2
1
Bit 0
0x(FF)FF_98A8
TPM2C1SC
CH1F
CH1IE
MS1B
MS1A
ELS1B
ELS1A
0
0
0x(FF)FF_98A9
TPM2C1VH
Bit 15
14
13
12
11
10
9
Bit 8
0x(FF)FF_98AA
TPM2C1VL
Bit 7
6
5
4
3
2
1
Bit 0
0x(FF)FF_98AB
TPM2C2SC
CH2F
CH2IE
MS2B
MS2A
ELS2B
ELS2A
0
0
0x(FF)FF_98AC
TPM2C2VH
Bit 15
14
13
12
11
10
9
Bit 8
0x(FF)FF_98AD
TPM2C2VL
Bit 7
6
5
4
3
2
1
Bit 0
0x(FF)FF_98AE
TPM2C3SC
CH3F
CH3IE
MS3B
MS3A
ELS3B
ELS3A
0
0
0x(FF)FF_98AF
TPM2C3VH
Bit 15
14
13
12
11
10
9
Bit 8
0x(FF)FF_98B0
TPM2C3VL
Bit 7
6
5
4
3
2
1
Bit 0
TODCLKS
SECF
MTCHF
1
Bit 0
MODE
MODE
TODPS
MTCHIE
MTCHEN
TODM
MTCHWC
MQSEC
TODCNT
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
4-11
Memory
Table 4-3. High-Page Register Summary (Continued)
Address
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x(FF)FF_98B10x(FF)FF_98B7
Reserved
—
—
—
—
—
—
—
—
0x(FF)FF_98B8
SCI1BDH
LBKDIE
RXEDGIE
0
SBR12
SBR11
SBR10
SBR9
SBR8
0x(FF)FF_98B9
SCI1BDL
SBR7
SBR6
SBR5
SBR4
SBR3
SBR2
SBR1
SBR0
0x(FF)FF_98BA
SCI1C1
LOOPS
SCISWAI
RSRC
M
WAKE
ILT
PE
PT
0x(FF)FF_98BB
SCI1C2
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
0x(FF)FF_98BC
SCI1S1
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
0x(FF)FF_98BD
SCI1S2
LBKDIF
RXEDGIF
0
RXINV
RWUID
BRK13
LBKDE
RAF
0x(FF)FF_98BE
SCI1C3
R8
T8
TXDIR
TXINV
ORIE
NEIE
FEIE
PEIE
0x(FF)FF_98BF
SCI1D
Bit 7
6
5
4
3
2
1
Bit 0
0x(FF)FF_98C0
PDBSC
PDBEN
PDBIF
PDBIE
LDMOD
DACTOE
LDOK
0x(FF)FF_98C1
PDBC1
CONT
MULT
0x(FF)FF_98C2
PDBC2
BB7
BB6
BB5
BB4
BB3
BB2
BB1
SWTRIG
0x(FF)FF_98C3
PDBCHEN
CHEN7
CHEN6
CHEN5
CHEN4
CHEN3
CHEN2
CHEN1
CHEN0
0x(FF)FF_98C4
PDBMODH
MOD[15:8]
0x(FF)FF_98C5
PDBMODL
MOD[7:0]
0x(FF)FF_98C6
PDBCNTH
COUNT[15:8]
0x(FF)FF_98C7
PDBCNTL
COUNT[7:0]
0x(FF)FF_98C8
PDBIDLYH
IDELAY[15:8]
0x(FF)FF_98C9
PDBIDLYL
IDELAY[7:0]
0x(FF)FF_98CA
DACINTH
DACINT[15:8]
0x(FF)FF_98CB
DACINTL
DACINT[7:0]
0x(FF)FF_98CC
PDBDLYAH
DELAY[15:8]
0x(FF)FF_98CD
PDBDLYAL
DELAY[7:0]
0x(FF)FF_98CE
PDBDLYBH
DELAY[15:8]
0x(FF)FF_98CF
PDBDLYBL
DELAY[7:0]
0x(FF)FF_98D0
PDBDLYCH
DELAY[15:8]
0x(FF)FF_98D1
PDBDLYCL
DELAY[7:0]
0x(FF)FF_98D2
PDBDLYDH
DELAY[15:8]
0x(FF)FF_98D3
PDBDLYDL
DELAY[7:0]
0x(FF)FF_98D4
PDBDLYEH
DELAY[15:8]
0x(FF)FF_98D5
PDBDLYEL
DELAY[7:0]
0x(FF)FF_98D6
PDBDLYFH
DELAY[15:8]
0x(FF)FF_98D7
PDBDLYFL
DELAY[7:0]
0x(FF)FF_98D8
PDBDLYGH
DELAY[15:8]
PRESCALER
TOS
TRIGSEL
MCF51MM256 Series Devices Reference Manual, Rev. 3
4-12
Freescale Semiconductor
Memory
Table 4-3. High-Page Register Summary (Continued)
Address
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x(FF)FF_98D9
PDBDLYGL
DELAY[7:0]
0x(FF)FF_98DA
PDBDLYHH
DELAY[15:8]
0x(FF)FF_98DB
PDBDLYHL
DELAY[7:0]
0x(FF)FF_98DC(FF)FF_98DF
Reserved
—
—
—
—
—
—
—
—
0x(FF)FF_98E0
TPM1SC
TOF
TOIE
CPWMS
CLKSB
CLKSA
PS2
PS1
PS0
0x(FF)FF_98E1
TPM1CNTH
Bit 15
14
13
12
11
10
9
Bit 8
0x(FF)FF_98E2
TPM1CNTL
Bit 7
6
5
4
3
2
1
Bit 0
0x(FF)FF_98E3
TPM1MODH
Bit 15
14
13
12
11
10
9
Bit 8
0x(FF)FF_98E4
TPM1MODL
Bit 7
6
5
4
3
2
1
Bit 0
0x(FF)FF_98E5
TPM1C0SC
CH0F
CH0IE
MS0B
MS0A
ELS0B
ELS0A
0
0
0x(FF)FF_98E6
TPM1C0VH
Bit 15
14
13
12
11
10
9
Bit 8
0x(FF)FF_98E7
TPM1C0VL
Bit 7
6
5
4
3
2
1
Bit 0
0x(FF)FF_98E8
TPM1C1SC
CH1F
CH1IE
MS1B
MS1A
ELS1B
ELS1A
0
0
0x(FF)FF_98E9
TPM1C1VH
Bit 15
14
13
12
11
10
9
Bit 8
0x(FF)FF_98EA
TPM1C1VL
Bit 7
6
5
4
3
2
1
Bit 0
0x(FF)FF_98EB
TPM1C2SC
CH2F
CH2IE
MS2B
MS2A
ELS2B
ELS2A
0
0
0x(FF)FF_98EC
TPM1C2VH
Bit 15
14
13
12
11
10
9
Bit 8
0x(FF)FF_98ED
TPM1C2VL
Bit 7
6
5
4
3
2
1
Bit 0
0x(FF)FF_98EE
TPM1C3SC
CH3F
CH3IE
MS3B
MS3A
ELS3B
ELS3A
0
0
0x(FF)FF_98EF
TPM1C3VH
Bit 15
14
13
12
11
10
9
Bit 8
0x(FF)FF_98F0
TPM1C3VL
Bit 7
6
5
4
3
2
1
Bit 0
0x(FF)FF_98F10x(FF)FF_98F7
Reserved
—
—
—
—
—
—
—
—
0x(FF)FF_98F8
ADCCV1H
CV1[15:8]
0x(FF)FF_98F9
ADCCV1L
CV1[7:0]
0x(FF)FF_98FA
ADCCV2H
CV2[15:8]
0x(FF)FF_98FB
ADCCV2L
CV2[7:0]
0x(FF)FF_98FC
ADCSC2
ADACT
ADTRG
ACFE
ACFGT
ACREN
0
REFSEL
0x(FF)FF_98FD
ADCSC3
CAL
CALF
0
0
ADCO
AVGE
AVGS
0x(FF)FF_98FE
ADCOFSH
OFS[15:8]
0x(FF)FF_98FF
ADCOFSL
OFS[7:0]
0x(FF)FF_9900
ADCPGH
PG[15:8]
0x(FF)FF_9901
ADCPGL
PG[7:0]
0x(FF)FF_9902
ADCMGH
MG[15:8]
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
4-13
Memory
Table 4-3. High-Page Register Summary (Continued)
Address
Name
Bit 7
6
5
4
3
2
0x(FF)FF_9903
ADCMGL
0x(FF)FF_9904
ADCCLPD
0
0
CLPD
0x(FF)FF_9905
ADCCLPS
0
0
CLPS
0x(FF)FF_9906
ADCCLP4H
0
0
0x(FF)FF_9907
ADCCLP4L
0x(FF)FF_9908
ADCCLP3H
0x(FF)FF_9909
ADCCLP3L
CLP3[7:0]
0x(FF)FF_990A
ADCCLP2
CLP2
0x(FF)FF_990B
ADCCLP1
0
0x(FF)FF_990C
ADCCLP0
0
0
0x(FF)FF_990D
Reserved
—
—
0x(FF)FF_990E
ADCCLMD
0
0
CLMD
0x(FF)FF_990F
ADCCLMS
0
0
CLMS
0x(FF)FF_9910
ADCCLM4H
0
0
0x(FF)FF_9911
ADCCLM4L
0x(FF)FF_9912
ADCCLM3H
0x(FF)FF_9913
ADCCLM3L
CLM3[7:0]
0x(FF)FF_9914
ADCCLM2
CLM2
0x(FF)FF_9915
ADCCLM1
0
0x(FF)FF_9916
ADCCLM0
0
0
0x(FF)FF_9917
APCTL1
ADPC7
ADPC6
ADPC5
ADPC4
0x(FF)FF_9918
APCTL2
ADPC15
ADPC14
ADPC13
0x(FF)FF_99190x(FF)FF_991F
Reserved
—
—
—
0x(FF)FF_9920
F1CDIV
FDIVLD
PRDIV8
0x(FF)FF_9921
F1OPT
0x(FF)FF_9922
Reserved
—
0x(FF)FF_9923
F1CNFG
CBEIE
0x(FF)FF_9924
F1PROT
0x(FF)FF_9925
F1STAT
FCBEF
0x(FF)FF_9926
F1CMD
0
0x(FF)FF_99270x(FF)FF_992F
Reserved
—
—
0x(FF)FF_9930
F2CDIV
FDIVLD
PRDIV8
0x(FF)FF_9931
F2OPT
1
Bit 0
MG[7:0]
0
0
0
0
CLP4[9:8]
0
0
0
CLP3[8]
—
—
—
CLP4[7:0]
0
0
0
0
CLP1
CLP0
—
0
—
—
0
0
0
CLM4[9:8]
0
0
0
CLM3[8]
ADPC3
ADPC2
ADPC1
ADPC0
ADPC12
ADPC11
ADPC10
ADPC9
ADPC8
—
—
—
—
—
CLM4[7:0]
0
0
0
0
CLM1
KEYEN
CLM0
FDIV
0
0
0
0
SEC
—
—
—
—
—
—
—
CCIE
KEYACC
0
0
0
0
0
FPS
FCCF
FPVIOL
FACCERR
FPOPEN
0
FBLANK
0
0
—
—
—
FCMD
KEYEN
—
—
—
FDIV
0
0
0
0
SEC
MCF51MM256 Series Devices Reference Manual, Rev. 3
4-14
Freescale Semiconductor
Memory
Table 4-3. High-Page Register Summary (Continued)
1
Address
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x(FF)FF_9932
Reserved
—
—
—
—
—
—
—
—
0x(FF)FF_9933
F2CNFG
CBEIE
CCIE
KEYACC
0
0
0
0
0
0x(FF)FF_9934
F2PROT
0x(FF)FF_9935
F2STAT
FCBEF
0x(FF)FF_9936
F2CMD
0
0x(FF)FF_99370x(FF)FF_993F
Reserved
—
—
—
—
0x(FF)FF_9940
PTHD
PTHD7
PTHD6
PTHD5
0x(FF)FF_9941
PTHDD
PTHDD7
PTHDD6
0x(FF)FF_9942
PTJD
PTJD7
0x(FF)FF_9943
PTJDD
0x(FF)FF_99440x(FF)FF_9947
FPS
FPOPEN
FBLANK
0
0
—
—
—
—
PTHD4
PTHD3
PTHD2
PTHD1
PTHD0
PTHDD5
PTHDD4
PTHDD3
PTHDD2
PTHDD1
PTHDD0
PTJD6
PTJD5
PTJD4
PTJD3
PTJD2
PTJD1
PTJD0
PTJDD7
PTJDD6
PTJDD5
PTJDD4
PTJDD3
PTJDD2
PTJDD1
PTJDD0
Reserved
—
—
—
—
—
—
—
—
0x(FF)FF_9948
PTHPE
PTHPE7
PTHPE6
PTHPE5
PTHPE4
PTHPE3
PTHPE2
PTHPE1
PTHPE0
0x(FF)FF_9949
PTHSE
PTHSE7
PTHSE6
PTHSE5
PTHSE4
PTHSE3
PTHSE2
PTHSE1
PTHSE0
0x(FF)FF_994A
PTHDS
PTHDS7
PTHDS6
PTHDS5
PTHDS4
PTHDS3
PTHDS2
PTHDS1
PTHDS0
0x(FF)FF_994B
PTHIFE
PTHIFE7
PTHIFE6
PTHIFE5
PTHIFE4
PTHIFE3
PTHIFE2
PTHIFE1
PTHIFE0
0x(FF)FF_994C
PTJPE
PTJPE7
PTJPE6
PTJPE5
PTJPE4
PTJPE3
PTJPE2
PTJPE1
PTJPE0
0x(FF)FF_994D
PTJSE
PTJSE7
PTJSE6
PTJSE5
PTJSE4
PTJSE3
PTJSE2
PTJSE1
PTJSE0
0x(FF)FF_994E
PTJDS
PTJDS7
PTJDS6
PTJDS5
PTJDS4
PTJDS3
PTJDS2
PTJDS1
PTJDS0
0x(FF)FF_994F
PTJIFE
PTJIFE7
PTJIFE6
PTJIFE5
PTJIFE4
PTJIFE3
PTJIFE2
PTJIFE1
PTJIFE0
FCCF
FPVIOL
0
FACCERR
FCMD
This location is reserved for Freescale internal testing. Do not write any value to this location. Writing a value to this location can
affect on-chip LVD performance.
Table 4-4. USB Register Summary
Address
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x(FF)FF_9A00
PERID
0
0
ID5
ID4
ID3
ID2
ID1
ID0
0x(FF)FF_9A04
IDCOMP
1
1
NID5
NID4
NID3
NID2
NID1
NID0
0x(FF)FF_9A08
REV
REV7
REV6
REV5
REV4
REV3
REV2
REV1
REV0
0x(FF)FF_9A0C
ADD_INFO
0
0
IEHOST
0x(FF)FF_9A10
OTG_INT_
STAT
ID_CHG
1_MSEC
LINE_
STATE_
CHG
—
SESS_
VLD_
CHG
B_SESS_CH
G
—
A_VBUS_CH
G
0x(FF)FF_9A14
OTG_INT_EN
ID_EN
1_MSEC_EN
LINE_
STATE_
EN
—
SESS_
VLD_EN
B_SESS_EN
—
A_VBUS_EN
IRQ_NUM
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
4-15
Memory
Table 4-4. USB Register Summary (Continued)
Address
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x(FF)FF_9A18
OTG_STAT
ID
1_MSEC_EN
LINE_
STATE_
STABLE
—
SESS_
VLD
B_SESS_EN
D
—
A_VBUS_VL
D
0x(FF)FF_9A1C
OTG_CTRL
DP_HIGH
—
DP_LOW
DM_LOW
—
OTG_EN
—
—
0x(FF)FF_9A80
INT_STAT
STALL
ATTACH
RESUME
SLEEP
TOK_
DNE
SOF_
TOK
ERROR
USB_
RST
0x(FF)FF_9A84
INT_ENB
STALL_
EN
ATTACH_EN
RESUME_E
N
SLEEP_
EN
TOK_
DNE_EN
SOF_
TOK_EN
ERROR_EN
USB_
RST_EN
0x(FF)FF_9A88
ERR_STAT
BTS_
ERR
—
DMA_
ERR
BTO_
ERR
DFN8
CRC16
CRC5_
EOF
PID_ERR
0x(FF)FF_9A8C
ERRENB
BTSERR
—
BUFERR
BTOERR
DFN8
CRC16
0x(FF)FF_9A90
STAT
TX
ODD
—
—
0x(FF)FF_9A94
CTL
JSTATE
HOST_
MODE_
EN
RESUME
ODD_
RST
USB_EN/
SOF_EN
0x(FF)FF_9A98
ADDR
LS_EN
0x(FF)FF_9A9C
BDT_PAGE_01
BDT_
BA15
BDT_
BA14
BDT_
BA13
BDT_
BA12
BDT_
BA11
BDT_
BA10
BDT_
BA9
NOT USED
0x(FF)FF_9AA0
FRM_NUML
FRM7
FRM8
FRM5
FRM4
FRM3
FRM2
FRM1
FRM0
0x(FF)FF_9AA4
FRM_NUMH
0
0
0
0
0
FRM10
FRM9
FRM8
0x(FF)FF_9AA8
TOKEN
0x(FF)FF_9AAC
SOF_THLD
CNT7
CNT6
CNT5
CNT4
CNT3
CNT2
CNT1
CNT0
0x(FF)FF_9AB0
BDT_PAGE_02
BDT_
BA23
BDT_
BA22
BDT_
BA21
BDT_
BA20
BDT_
BA19
BDT_
BA18
BDT_
BA17
BDT_
BA16
0x(FF)FF_9AB4
BDT_PAGE_03
BDT_
BA31
BDT_
BA30
BDT_
BA29
BDT_
BA28
BDT_
BA27
BDT_
BA26
BDT_
BA25
BDT_
BA24
0x(FF)FF_9AB80x(FF)FF_9ABF
Reserved
—
—
—
—
—
—
—
—
0x(FF)FF_9AC0
ENDPT0
HOST_
WO_HUB
RETRY_DIS
0
EP_CTL_DIS
EP_RX_EN
EP_TX_
EN
EP_
STALL
EP_
HSHK
0x(FF)FF_9AC4
ENDPT1
HOST_
WO_HUB
RETRY_DIS
0
EP_CTL_DIS
EP_RX_EN
EP_TX_
EN
EP_
STALL
EP_
HSHK
0x(FF)FF_9AC8
ENDPT2
HOST_
WO_HUB
RETRY_DIS
0
EP_CTL_DIS
EP_RX_EN
EP_TX_
EN
EP_
STALL
EP_
HSHK
0x(FF)FF_9ACC
ENDPT3
HOST_
WO_HUB
RETRY_DIS
0
EP_CTL_DIS
EP_RX_EN
EP_TX_
EN
EP_
STALL
EP_
HSHK
0x(FF)FF_9AD0
ENDPT4
HOST_
WO_HUB
RETRY_DIS
0
EP_CTL_DIS
EP_RX_EN
EP_TX_
EN
EP_
STALL
EP_
HSHK
0x(FF)FF_9AD4
ENDPT5
HOST_
WO_HUB
RETRY_DIS
0
EP_CTL_DIS
EP_RX_EN
EP_TX_
EN
EP_
STALL
EP_
HSHK
0x(FF)FF_9AD8
ENDPT6
HOST_
WO_HUB
RETRY_DIS
0
EP_CTL_DIS
EP_RX_EN
EP_TX_
EN
EP_
STALL
EP_
HSHK
ENDP [3:0]
SE0
TXSUSPEND
/ TOKEN
BUSY
RESET
PIDERR
ADDR [6:0]
TOKEN_PID
TOKEN_ENDPT
MCF51MM256 Series Devices Reference Manual, Rev. 3
4-16
Freescale Semiconductor
Memory
Table 4-4. USB Register Summary (Continued)
Address
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x(FF)FF_9ADC
ENDPT7
HOST_
WO_HUB
RETRY_DIS
0
EP_CTL_DIS
EP_RX_EN
EP_TX_
EN
EP_
STALL
EP_
HSHK
0x(FF)FF_9AE0
ENDPT8
HOST_
WO_HUB
RETRY_DIS
0
EP_CTL_DIS
EP_RX_EN
EP_TX_
EN
EP_
STALL
EP_
HSHK
0x(FF)FF_9AE4
ENDPT9
HOST_
WO_HUB
RETRY_DIS
0
EP_CTL_DIS
EP_RX_EN
EP_TX_
EN
EP_
STALL
EP_
HSHK
0x(FF)FF_9AE8
ENDPT10
HOST_
WO_HUB
RETRY_DIS
0
EP_CTL_DIS
EP_RX_EN
EP_TX_
EN
EP_
STALL
EP_
HSHK
0x(FF)FF_9AEC
ENDPT11
HOST_
WO_HUB
RETRY_DIS
0
EP_CTL_DIS
EP_RX_EN
EP_TX_
EN
EP_
STALL
EP_
HSHK
0x(FF)FF_9AF0
ENDPT12
HOST_
WO_HUB
RETRY_DIS
0
EP_CTL_DIS
EP_RX_EN
EP_TX_
EN
EP_
STALL
EP_
HSHK
0x(FF)FF_9AF4
ENDPT13
HOST_
WO_HUB
RETRY_DIS
0
EP_CTL_DIS
EP_RX_EN
EP_TX_
EN
EP_
STALL
EP_
HSHK
0x(FF)FF_9AF8
ENDPT14
HOST_
WO_HUB
RETRY_DIS
0
EP_CTL_DIS
EP_RX_EN
EP_TX_
EN
EP_
STALL
EP_
HSHK
0x(FF)FF_9AFC
ENDPT15
HOST_
WO_HUB
RETRY_DIS
0
EP_CTL_DIS
EP_RX_EN
EP_TX_
EN
EP_
STALL
EP_
HSHK
0x(FF)FF_9B00
USB_CTRL
SUSP
PDE
—
—
—
—
0x(FF)FF_9B04
USB_OTG_
OBSERVE
DP_PU
DP_PD
0
DM_PD
—
—
—
—
0x(FF)FF_9B08
USB_OTG_
CONTROL
—
—
—
DPPULLUP_
NONOTG
ID
VBUS
VLD
SESS
VLD
SESS
END
0x(FF)FF_9B0C
USBTRC0
USB
RESET
USBPU
USB
RESMEN
—
—
USB
VREN
—
USB_
RESUME_IN
T
0x(FF)FF_9B10
OTGPIN
—
USBID
DP
DOWN
DM
DOWN
PULLUP
VBUS
VLD
SESS
END
SESS
VLD
0x(FF)FF_9B110x(FF)FF_9BFF
Reserved
—
—
—
—
—
—
—
—
3
2
1
Bit 0
CLK_SRC
Table 4-5. Mini-FlexBus Register Summary
Address
Name
Bit 7
6
5
4
0x(FF)FF_E800
0x(FF)FF_E801
0x(FF)FF_E802
BA[31:24]
MBCSAR0
0x(FF)FF_E803
BA[23:16]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0x(FF)FF_E804
0x(FF)FF_E805
0x(FF)FF_E806
BAM[31:24]
MBCSMR0
0x(FF)FF_E807
BAM[23:16]
—
—
—
—
—
—
—
WP
—
—
—
—
—
—
—
V
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
4-17
Memory
Table 4-5. Mini-FlexBus Register Summary (Continued)
Address
Name
Bit 7
6
5
4
3
2
1
Bit 0
—
—
—
—
—
—
—
—
—
0
0x(FF)FF_E808
0x(FF)FF_E809
0x(FF)FF_E80A
MBCSCR0
ASET
RDAH
WS
0x(FF)FF_E80B
—
PS
—
0x(FF)FF_E80C
0x(FF)FF_E80D
0x(FF)FF_E80E
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BAM[23:16]
MBCSMR1
—
—
—
—
—
—
—
WP
—
—
—
—
—
—
—
V
—
—
SWS
SWSEN
MBCSCR1
—
ASET
RDAH
WRAH
WS
0x(FF)FF_E817
4.1.3
—
—
0x(FF)FF_E814
0x(FF)FF_E816
—
BAM[31:24]
0x(FF)FF_E813
0x(FF)FF_E815
AA
BA[23:16]
MBCSAR1
0x(FF)FF_E810
0x(FF)FF_E812
MUX
BA[31:24]
0x(FF)FF_E80F
0x(FF)FF_E811
WRAH
PS
BEM
BSTR
BSTW
—
MUX
AA
—
—
Flash Module Reserved Memory Locations
Several reserved flash memory locations, shown in Table 4-6, are used for storing values used by
corresponding peripheral registers. These registers include an 8-byte backdoor key that can be used to gain
access to secure memory resources. During reset events, the contents of the flash protection byte
(NVxPROT) and flash nonvolatile byte (NVxOPT) in the reserved flash memory are transferred into the
corresponding FxPROT and FxOPT registers in the high-page register area to control security and block
protection options.
Table 4-6. Reserved Flash Memory Addresses
Address
Register
7
6
5
4
3
2
1
0
0x(00)00_03FC–
0x(00)00_03FD
Reserved
—
—
—
—
—
—
—
—
0x(00)00_03FE
Storage of FTRIM
0
0
0
0
0
0
0
FTRIM
0x(00)00_03FF
Storage of MCGTRM
TRIM
0x(00)00_0400–
0x(00)00_0407
8-Byte Backdoor Comparison Key
0x(00)00_0408
FCHKSH
0x(00)00_0409
FCHKSL
0x(00)00_040A
CHKSBYP
MCF51MM256 Series Devices Reference Manual, Rev. 3
4-18
Freescale Semiconductor
Memory
Table 4-6. Reserved Flash Memory Addresses (Continued)
Address
Register
7
6
5
0x(00)00_040B
1
4
3
2
1
0
Partial_Erase_Semaphore
0x(00)00_040D
NVxPROT
0x(00)00_040E
Reserved
0x(00)00_040F
NVxOPT
0x(00)00_0410
FLASHAS
FPS
—
—
KEYEN
0
0
FPOPEN
—
—
—
—
—
—
0
0
0
0
SEC
0
0
0
0
ARRAYSEL1
Bit1 is the Flash Array Select Protection bit and Bit0 is the Flash Array Select bit. If Bit 1 = 0, then FLASHAS_Bit0 is copied to
the SOPT3_ARRAYSEL bit. If Bit1 = 1, then nothing happens. This can be confusing for cases when flash is in an erased state.
The factory trim values are stored in the flash information row (IFR)1 and are automatically loaded into
the MCGTRM and MCGSC registers after any reset. The oscillator trim values stored in TRIM and
FTRIM can be reprogrammed by third party programmers and must be copied into the corresponding
MCG registers (MCGTRM and MCGSC) by user code to override the factory trim.
NOTE
When the MCU is in active BDM, the trim value in the IFR is not loaded.
Instead, the MCGTRM register resets to 0x80 and MCGSC[FTRIM] resets
to zero.
Provided the key enable (KEYEN) bit is set, the 8-byte comparison key can be used to temporarily
disengage memory security. This key mechanism can be accessed only through user code running in secure
memory (A security key cannot be entered directly through background debug commands). This security
key can be disabled completely by clearing the KEYEN bit. If the security key is disabled, the only way
to disengage security is by mass-erasing the flash (normally through the background debug interface) and
verifying the flash is blank.
4.1.4
ColdFire Rapid GPIO Memory Map
The rapid GPIO module is mapped into a 16-byte area starting at location 0xC0_0000. Its memory map is
shown below in Table 4-7.
Table 4-7. V1 ColdFire Rapid GPIO Memory Map
1.
Address
Register
Name
Bit 7
6
5
4
3
2
0x(00)C0_0000
RGPIO_DIR
15
14
13
12
11
0x(00)C0_0001
RGPIO_DIR
7
6
5
4
3
0x(00)C0_0002
RGPIO_DATA
15
14
13
12
0x(00)C0_0003
RGPIO_DATA
7
6
5
0x(00)C0_0004
RGPIO_ENB
15
14
0x(00)C0_0005
RGPIO_ENB
7
6
0x(00)C0_0006
RGPIO_CLR
15
14
1
Bit 0
10
9
8
2
1
0
11
10
9
8
4
3
2
1
0
13
12
11
10
9
8
5
4
3
2
1
0
13
12
11
10
9
8
IFR — Nonvolatile information memory that can only be accessed during production test. During production test, system
initialization, configuration, and test information is stored in the IFR. This information cannot be read or modified in normal
user or background debug modes.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
4-19
Memory
Table 4-7. V1 ColdFire Rapid GPIO Memory Map (Continued)
4.1.5
Address
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x(00)C0_0007
RGPIO_CLR
7
6
5
4
3
2
1
0
0x(00)C0_0008
Reserved
—
—
—
—
—
—
—
—
0x(00)C0_0009
Reserved
—
—
—
—
—
—
—
—
0x(00)C0_000A
RGPIO_SET
15
14
13
12
11
10
9
8
0x(00)C0_000B
RGPIO_SET
7
6
5
4
3
2
1
0
0x(00)C0_000C
Reserved
—
—
—
—
—
—
—
—
0x(00)C0_000D
Reserved
—
—
—
—
—
—
—
—
0x(00)C0_000E
RGPIO_TOG
15
14
13
12
11
10
9
8
0x(00)C0_000F
RGPIO_TOG
7
6
5
4
3
2
1
0
ColdFire Interrupt Controller Memory Map
The V1 ColdFire interrupt controller (CF1_INTC) register map is sparsely-populated, but retains
compatibility with earlier ColdFire interrupt controller definitions. The CF1_INTC occupies the upper
64 bytes of the 4 GB address space and all memory locations are accessed as 8-bit (byte) operands.
Table 4-8. V1 ColdFire Interrupt Controller Memory Map
Address
Register Name
msb
0x(FF)FF_FFC0–
0x(FF)FF_FFDF
Bit Number
lsb
Reserved
—
—
—
—
—
—
—
—
0x(FF)FF_FFD0
INTC_FRC
0
LVL1
LVL2
LVL3
LVL4
LVL5
LVL6
LVL7
0x(FF)FF_FFD1–
0x(FF)FF_FFD7
Reserved
—
—
—
—
—
—
—
—
—
—
0x(FF)FF_FFD8
INTC_PL6P7
0
0
REQN
0x(FF)FF_FFD9
INTC_PL6P6
0
0
REQN
0x(FF)FF_FFDA
Reserved
—
—
—
—
—
0x(FF)FF_FFDB
INTC_WCR
ENB
0
0
0
0
—
0x(FF)FF_FFDC–
0x(FF)FF_FFDD
Reserved
—
—
—
—
—
0x(FF)FF_FFDE
INT_SFRC
0
0
SET
0x(FF)FF_FFDF
INT_CFRC
0
0
CLR
0x(FF)FF_FFE0
INTC_SWIACK
0
0x(FF)FF_FFE1–
0x(FF)FF_FFE3
Reserved
—
0x(FF)FF_FFE4
INTC_
LVL1IACK
0
0x(FF)FF_FFE5–
0x(FF)FF_FFE7
Reserved
—
0x(FF)FF_FFE8
INTC_
LVL2IACK
0
0x(FF)FF_FFE9–
0x(FF)FF_FFEB
Reserved
—
0x(FF)FF_FFEC
INTC_
LVL3IACK
0
0x(FF)FF_FFED–
0x(FF)FF_FFEF
Reserved
—
MASK
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VECN
—
—
—
—
VECN
—
—
—
—
VECN
—
—
—
—
VECN
—
—
—
—
MCF51MM256 Series Devices Reference Manual, Rev. 3
4-20
Freescale Semiconductor
Memory
Table 4-8. V1 ColdFire Interrupt Controller Memory Map (Continued)
4.2
Address
Register Name
msb
0x(FF)FF_FFF0
INTC_
LVL4IACK
0
0x(FF)FF_FFF1–
0x(FF)FF_FFF3
Reserved
—
0x(FF)FF_FFF4
INTC_
LVL5IACK
0
0x(FF)FF_FFF5–
0x(FF)FF_FFF7
Reserved
—
0x(FF)FF_FFF8
INTC_
LVL6IACK
0
0x(FF)FF_FFF9–
0x(FF)FF_FFFB
Reserved
—
0x(FF)FF_FFFC
INTC_
LVL7IACK
0
0x(FF)FF_FFFD–
0x(FF)FF_FFFF
Reserved
—
Bit Number
lsb
VECN
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VECN
—
—
—
—
VECN
—
—
—
—
VECN
—
—
—
—
RAM
The MCF51MM256 series microcontroller includes up to 32 Kbytes of static RAM. RAM is most
efficiently accessed using the A5-relative addressing mode (address register indirect with displacement
mode). Any single bit in this area can be accessed with the bit manipulation instructions (BCLR,
BSET,etc.).
At power-on, the contents of RAM are uninitialized. RAM data is unaffected by any reset provided that
the supply voltage does not drop below the minimum value for RAM retention (VRAM).
4.3
Flash Memory
The flash memory is for program storage and read-only data. In-circuit programming allows the operating
program to be loaded into the flash memory after final assembly of the application product. It is possible
to program the entire array through the single-wire background debug interface. Because no special
voltages are needed for flash erase and programming operations, in-application programming is also
possible through other software-controlled communication paths.
Flash memory is ideal for single-supply applications allowing for field reprogramming without requiring
external high voltage sources for program or erase operations. The flash module includes a memory
controller that executes commands to modify flash memory contents.
Array read access time is one bus cycle for bytes, aligned words, and aligned longwords.
Multiple accesses are needed for misaligned words and longword operands. For flash memory, an erased
bit reads 1 and a programmed bit reads 0. It is not possible to read from a flash block while any command
is executing on that specific flash block.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
4-21
Memory
CAUTION
A flash block address must be in the erased state before being programmed.
Cumulative programming of bits within a flash block address is not allowed
except for status field updates required in EEPROM emulation applications.
Flash memory on this device must be programmed 32-bits at a time with long word address aligned when
the low-voltage detect flag (LVDF) in the System Power Management Status and Control 1 register
(SPMSC1) is clear. If SPMSC1[LVDF] is set, the programming sequence must be modified such that odd
and even bytes are written separately. This device’s flash memory is organized as two 16-bit wide blocks
interleaved to yield a 32-bit data path. When programming flash if LVDF is set, alternate bytes must be set
to 0xFF as shown in Table 4-9. Failure to adhere to these guidelines may result in a partially programmed
flash array.
Table 4-9. Alternate Bytes Setting
4.3.1
Addresses
Desired Value
Values Programmed
0x00 – 0x03
0x00 – 0x03
0x5555_AAAA
0x55FF_AAFF
0xFF55_FFAA
0x04 – 0x07
0x04 – 0x07
0xCCCC_CCCC
0xCCFF_CCFF
0xFFCC_FFCC
0x08 – 0x0B
0x08 – 0x0B
0x1234_5678
0x12FF_56FF
0xFF34_FF78
0x0C – 0x0F
0x0C – 0x0F
0x9ABC_DEF0
0x9AFF_DEFF
0xFFBC_FFF0
Features
Features of the flash memory include:
• The MCF51MM256 series incorporate dual flash controllers, allowing the microcontroller to
execute code from one flash array while programming the other.
• Flash size
— MCF51MM256: 262,144 bytes (256 sectors if 1024 bytes each)
— MCF51MM128: 131,072 (128 sectors of 1024 bytes each)
• Automated program and erase algorithm
• Fast program and sector erase operation
• Burst program command for faster flash array program times
• Single power supply program and erase
• Command interface for fast program and erase operation
• Up to 100,000 program/erase cycles at typical voltage and temperature
• Flexible block protection (on any 2-Kbyte memory boundary for each flash block)
• Security feature to prevent unauthorized access to on-chip memory and resources
• Auto power-down for low-frequency read accesses
MCF51MM256 Series Devices Reference Manual, Rev. 3
4-22
Freescale Semiconductor
Memory
4.3.2
Dual Flash Controllers
The MCF51MM256 and MCF51MM128 devices each separate available flash into two distinct blocks.
Each block is controlled by its own, independent, flash controller. Memory mapping of the individual
arrays is impacted by the current state of ARRAYSEL bit in the SOPT3 register as shown in Table 4-10.
Upon initial power up, ARRAYSEL=0, and Array 1 is located at the bottom of the memory map with Array
2 above it. Setting ARRAYSEL=1 reverses the locations of the two arrays in the memory map. The V1
ColdFire core will normally boot from 0x(00)00_0000. The procedure to swap flash arrays must be located
in RAM, and must include the following steps:
• Disable flash speculation by the V1 ColdFire CPU by setting CPUCR[FSD] to 1
• Disable all interrupts
• Toggle ARRAYSEL
• Re-enable interrupts
• If desired, re-enable flash seculation by the V1 ColdFire CPU by re-setting CPUCR[FSD] to 0
• jump back (using an indirect jump) to main application code residing in flash memory
Note that swapping flash arrays as discussed above does NOT change the location of the flash controllers
in the memory map. Registers in FTSR1 and FTSR2 are fixed in the memory map. Only the flash arrays
are impacted by changing ARRAYSEL.
Table 4-10. Flash Array Base Address
ARRAYSEL
Array
MCF51MM256
MCF51MM128
0 (initial POR value)
FTSR1
0x(00)00_0000
0x(00)00_0000
0x(00)02_0000
0x(00)01_0000
0x(00)00_0000
0x(00)00_0000
FTSR2
1
FTSR1
FTSR2
4.3.3
Register Descriptions
The flash controller (FTSR) contains a set of 12 control and status registers. Detailed descriptions of each
register bit are provided in the sections that follow.
4.3.3.1
Flash Clock Divider Register (FxCDIV)
The FxCDIV register controls the length of timed events in program and erase algorithms executed by the
flash memory controller. All bits in the FxCDIV register are readable and writable with restrictions as
determined by the value of FDIVLD when writing to the FxCDIV register.
R
7
6
5
FDIVLD
PRDIV8
0
0
4
3
2
1
0
0
0
0
FDIV
W
Reset
0
0
0
Figure 4-3. Flash Clock Divider Register (FxCDIV)
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
4-23
Memory
Table 4-11. FxCDIV Field Descriptions
Field
Description
7
FDIVLD
Clock Divider Load Control. When writing to the FxCDIV register for the first time after a reset, the value of the
FDIVLD bit written controls the future ability to write to the FxCDIV register:
0 Writing a 0 to FDIVLD locks the FxCDIV register contents; all future writes to FxCDIV are ignored.
1 Writing a 1 to FDIVLD keeps the FxCDIV register writable; next write to FxCDIV is allowed.
When reading the FxCDIV register, the value of the FDIVLD bit read indicates the following:
0 FxCDIV register has not been written to since the last reset.
1 FxCDIV register has been written to since the last reset.
6
PRDIV8
Enable Prescalar by 8.
0 The bus clock is directly fed into the clock divider.
1 The bus clock is divided by 8 before feeding into the clock divider.
5–0
FDIV
4.3.3.2
Clock Divider Bits. The combination of PRDIV8 and FDIV[5:0] must divide the bus clock down to a frequency
of 150 kHz–200 kHz. The minimum divide ratio is 2 (PRDIV8 = 0, FDIV = 0x01) and the maximum divide ratio is
512 (PRDIV8 = 1, FDIV = 0x3F).
Flash Options Register (FxOPT and NVxOPT)
The FxOPT register holds all bits associated with the security of the MCU and flash module. All bits in
the FxOPT register are readable but are not writable.
The FxOPT register is loaded from the flash configuration field during the reset sequence, indicated by F
in Figure 4-4.
The security feature in the flash module is described in Section 4.4, “Functional Description”.
7
6
KEYEN
R
5
4
3
2
0
0
0
0
0
0
0
0
1
0
SEC
W
Reset
F
F
F
F
Figure 4-4. Flash Options Register (FxOPT)
Table 4-12. FxOPT Field Descriptions
Field
Description
7–6
KEYEN
Backdoor Key Security Enable Bits. The KEYEN[1:0] bits define the enabling of backdoor key access to the
flash module.
00 Disabled
01 Disabled (Preferred KEYEN state to disable Backdoor Key Access)
10 Enabled
11 Disabled
5–2
Reserved, should be cleared.
1–0
SEC
Flash Security Bits. The SEC[1:0] bits define the security state of the MCU. If the flash module is unsecured
using backdoor key access, the SEC[1:0] bits are forced to the unsecured state.
00 Unsecured
01 Unsecured
10 Secured
11 Unsecured
MCF51MM256 Series Devices Reference Manual, Rev. 3
4-24
Freescale Semiconductor
Memory
4.3.3.3
Flash Configuration Register (FxCNFG)
The FxCNFG register gates the security backdoor writes.
KEYACC is readable and writable while all remaining bits read 0 and are not writable. KEYACC is only
writable if KEYEN is set to the enabled state (see Section 4.3.3.2, “Flash Options Register (FxOPT and
NVxOPT)”).
NOTE
Flash array reads are allowed while KEYACC is set.
R
7
6
5
CBEIE
CCIE
KEYACC
0
0
0
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Figure 4-5. Flash Configuration Register (FxCNFG)
Table 4-13. FxCNFG Field Descriptions
Field
Description
7
CBEIE
Command Buffer Empty Interrupt Enable — The CBEIE bit enables an interrupt in case of an empty command
buffer in the flash module.
0 Command buffer empty interrupt disabled.
1 An interrupt will be requested whenever the CBEIF flag (see Section 4.3.3.5, “Flash Status Register
(FxSTAT)”) is set.
6
CCIE
Command Complete Interrupt Enable — The CCIE bit enables an interrupt in case all commands have been
completed in the flash module.
0 Command complete interrupt disabled.
1 An interrupt will be requested whenever the CCIF flag (see Section 4.3.3.5, “Flash Status Register (FxSTAT)”)
is set.
5
KEYACC
4–0
4.3.3.4
Enable Security Key Writing
0 Writes to the flash block are interpreted as the start of a command write sequence.
1 Writes to the flash block are interpreted as keys to open the backdoor.
Reserved,
Flash Protection Register (FxPROT and NVxPROT)
NOTE
The FxPROT register defines which flash sectors are protected against
program or erase operations. FxPROT bits are readable and writable as long
as the size of the protected flash memory is being increased. Any write to
FxPROT that attempts to decrease the size of the protected flash memory is
ignored.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
4-25
Memory
MCF51MM256/128 have two flash blocks. Each block protection is configured by its respective FxPROT
and NVxPROT registers. The flash block swap feature is described in Section 4.1.3, “Flash Module
Reserved Memory Locations.” The protection follows the flash block instead of the memory addresses.
During the reset sequence, the FxPROT register is loaded from the flash protection byte in the flash
configuration field, indicated by F in Figure 4-6. To change the flash protection loaded during the reset
sequence, the flash sector containing the flash configuration field must be unprotected. Then, the flash
protection byte must be reprogrammed.
Trying to alter data in any protected area in the flash memory results in a protection violation error and
FxSTAT[FPVIOL] is set. The mass erase of the flash array is not possible if any of the flash sectors
contained in the flash array are protected.
7
6
5
R
4
3
2
1
FPS
0
FPOPEN
W
Reset
F
F
F
F
F
F
F
F
Figure 4-6. Flash Protection Register (FxPROT)
Table 4-14. FxPROT Field Descriptions
Field
Description
7–1
FPS
Flash Protection Size. With FPOPEN set, the FPS bits determine the size of the protected flash address range
as shown in Table 4-15.
0
FPOPEN
Flash Protection Open
0 Flash array fully protected.
1 Flash array protected address range determined by FPS bits.
Table 4-15. Flash Protection Address Range
FPS
FPOPEN
Protected Address Range
Relative to Flash Array Base
Protected
Size
—
0
0x0_0000–0x1_FFFF
128 Kbytes
0x00–0x3F
0x0_0000–0x1_FFFF
128 Kbytes
0x40
0x0_0000–0x1_F7FF
126 Kbytes
0x41
0x0_0000–0x1_EFFF
124 Kbytes
0x0_0000–0x1_E7FF
122 Kbytes
0x43
0x0_0000–0x1_DFFF
120 Kbytes
0x44
0x0_0000–0x1_D7FF
118 Kbytes
0x45
0x0_0000–0x1_CFFF
116 Kbytes
0x46
0x0_0000-0x1_C7FF
114 Kbytes
0x42
1
MCF51MM256 Series Devices Reference Manual, Rev. 3
4-26
Freescale Semiconductor
Memory
Table 4-15. Flash Protection Address Range (Continued)
Protected Address Range
Relative to Flash Array Base
Protected
Size
0x47
0x0_0000–0x1_BFFF
112 Kbytes
...
...
...
0x5B
0x0_0000–0x1_1FFF
72 Kbytes
0x5C
0x0_0000–0x1_17FF
70 Kbytes
0x5D
0x0_0000–0x1_0FFF
68 Kbytes
0x5E
0x0_0000–0x1_07FF
66 Kbytes
0x5F
0x0_0000–0x0_FFFF
64 Kbytes
0x60
0x0_0000–0x0_F7FF
62 Kbytes
0x61
0x0_0000–0x0_EFFF
60 Kbytes
0x62
0x0_0000–0x0_E7FF
58 Kbytes
0x0_0000–0x0_DFFF
56 Kbytes
...
...
...
0x77
0x0_0000–0x0_3FFF
16 Kbytes
0x78
0x0_0000–0x0_37FF
14 Kbytes
0x79
0x0_0000–0x0_2FFF
12 Kbytes
0x7A
0x0_0000–0x0_27FF
10 Kbytes
0x7B
0x0_0000–0x0_1FFF
8 Kbytes
0x7C
0x0_0000–0x0_17FF
6 Kbytes
0x7D
0x0_0000–0x0_0FFF
4 Kbytes
0x7E
0x0_0000–0x0_07FF
2 Kbytes
0x7F
No Protection
0 Kbytes
FPS
0x63
4.3.3.5
FPOPEN
1
Flash Status Register (FxSTAT)
The FxSTAT register defines the operational status of the flash module. FCBEF, FPVIOL and FACCERR
are readable and writable. FBLANK is readable and not writable. The remaining bits read 0 and are not
writable.
7
6
5
4
3
2
1
0
R
FCBEF
FCCF
FPVIOL
FACCERR
0
FBLANK
0
0
W
w1c1
w1c
w1c
0
0
0
0
0
0
1
Reset
1
1
w1c stands for writing 1 to clear.
Figure 4-7. Flash Status Register (FxSTAT)
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
4-27
Memory
Table 4-16. FxSTAT Field Descriptions
Field
Description
7
FCBEF
Command Buffer Empty Flag. The FCBEF flag indicates that the command buffer is empty so that a new
command write sequence can be started when performing burst programming. Writing a 0 to the FCBEF flag has
no effect on FCBEF. Writing a 0 to FCBEF after writing an aligned address to the flash array memory, but before
FCBEF is cleared, aborts a command write sequence and causes the FACCERR flag to be set. Writing a 0 to
FCBEF outside of a command write sequence does not set the FACCERR flag. Writing a 1 to this bit clears it.
0 Command buffers are full.
1 Command buffers are ready to accept a new command.
6
FCCF
Command Complete Flag. The FCCF flag indicates that there are no more commands pending. The FCCF flag
is cleared when FCBEF is cleared and sets automatically upon completion of all active and pending commands.
The FCCF flag does not set when an active program command completes and a pending burst program
command is fetched from the command buffer. Writing to the FCCF flag has no effect on FCCF.
0 Command in progress.
1 All commands are completed.
5
FPVIOL
Protection Violation Flag. The FPVIOL flag indicates an attempt was made to program or erase an address in
a protected area of the flash memory during a command write sequence. Writing a 0 to the FPVIOL flag has no
effect on FPVIOL. Writing a 1 to this bit clears it. While FPVIOL is set, it is not possible to launch a command or
start a command write sequence.
0 No protection violation detected.
1 Protection violation has occurred.
4
FACCERR
Access Error Flag. The FACCERR flag indicates an illegal access has occurred to the flash memory caused by
either a violation of the command write sequence, issuing an illegal flash command (see Section 4.3.3.6, “Flash
Command Register (FxCMD)”), or the execution of a CPU STOP instruction while a command is executing
(FCCF = 0). Writing a 0 to the FACCERR flag has no effect on FACCERR. Writing a 1 to this bit clears it. While
FACCERR is set, it is not possible to launch a command or start a command write sequence.
0 No access error detected.
1 Access error has occurred.
3
Reserved, must be cleared.
2
FBLANK
1–0
4.3.3.6
Flag Indicating the Erase Verify Operation Status. When the FCCF flag is set after completion of an erase
verify command, the FBLANK flag indicates the result of the erase verify operation. The FBLANK flag is cleared
by the flash module when FCBEF is cleared as part of a new valid command write sequence. Writing to the
FBLANK flag has no effect on FBLANK.
0 Flash block verified as not erased.
1 Flash block verified as erased.
Reserved, should be cleared.
Flash Command Register (FxCMD)
The FxCMD register is the flash command register. Bits 6–0 are readable and writable during a command
write sequence, while bit 7 reads 0 and is not writable.
7
R
6
5
4
0
3
2
1
0
0
0
0
FCMD
W
Reset
0
0
0
0
0
Figure 4-8. Flash Command Register (FxCMD)
MCF51MM256 Series Devices Reference Manual, Rev. 3
4-28
Freescale Semiconductor
Memory
Table 4-17. FxCMD Field Descriptions
Field
7
Description
Reserved, must be cleared.
6–0
FCMD
4.4
Flash Command. Valid flash commands are shown below. Writing any command other than those listed sets
the FACCERR flag in the FxSTAT register.
0x05 Erase verify
0x20 Program
0x25 Burst program
0x40 Sector erase
0x41 Mass erase
Functional Description
4.4.1
Flash Command Operations
Flash command operations execute program, erase, and erase verify algorithms described in this section.
The program and erase algorithms are controlled by the flash memory controller whose time base, FCLK,
is derived from the bus clock via a programmable divider.
The next sections describe:
1.
2.
3.
4.
How to write the FCDIV register to set FCLK
Command write sequences to program, erase, and erase verify operations on the flash memory
Valid flash commands
Effects resulting from illegal flash command write sequences or aborting flash operations
4.4.1.1
Writing the FCDIV Register
Prior to issuing any flash command after a reset, write the FCDIV register to divide the bus clock within
150–200 kHz. The FCDIV[PRDIV8, FDIV] bits must be set as described in Figure 4-9.
For example, if the bus clock frequency is 25 MHz, FCDIV[FDIV] should be set to 0x0F (001111) and the
FCDIV[PRDIV8] bit set to 1. The resulting FCLK frequency is then 195 kHz. In this case, the flash
program and erase algorithm timings are increased over the optimum target by:
(200 - 195)  200 = 3%
Eqn. 4-1
CAUTION
Program and erase command execution time increase proportionally with
the period of FCLK. Programming or erasing the flash memory with
FCLK less than 150 kHz should be avoided. Setting FCDIV to a value such
that FCLK is less than 150 kHz can destroy the flash memory due to
overstress. Setting FCDIV to a value where FCLK is greater than 200 kHz
can result in incomplete programming or erasure of the flash memory cells.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
4-29
Memory
If the FCDIV register is written, the FDIVLD bit is automatically set. If the FDIVLD bit is 0, the FCDIV
register has not been written since the last reset. If the FCDIV register has not been written to, the flash
command loaded during a command write sequence does not execute and FSTAT[FACCERR] is set.
START
PRDIV8 = 0 (reset)
bus_clock
0.3MHz?
yes
ALL PROGRAM AND ERASE
COMMANDS IMPOSSIBLE
no
bus_clock
12.8MHz?
no
yes
set PRDIV8 = 1
PRDCLK = bus_clock/8
PRDCLK[kHz]/200
an integer?
yes
PRDCLK = bus_clock
no
set FDIV[5:0] = INT(PRDCLK[kHz]/200)
set FDIV[5:0] = PRDCLK[kHz]/200-1
FCLK = (PRDCLK)/(1+FDIV[5:0])
END
Note:
• FCLK is the clock of the flash timing control block
• INT(x) is the integer part of x (e.g. INT(4.323) = 4)
Figure 4-9. Determination Procedure for PRDIV8 and FDIV Bits
4.4.1.2
Command Write Sequence
The flash command controller supervises the command write sequence to execute program, erase, and
erase verify algorithms.
Before starting a command write sequence, the FACCERR and FPVIOL flags in the FSTAT register must
be clear and the FCBEF flag must be set (see Section 4.3.3.5).
MCF51MM256 Series Devices Reference Manual, Rev. 3
4-30
Freescale Semiconductor
Memory
A command write sequence consists of three steps that must be strictly adhered to with writes to the flash
module not permitted between the steps. However, flash register and array reads are allowed during a
command write sequence. The basic command write sequence is as follows:
1. Write to a valid address in the flash array memory.
2. Write a valid command to the FCMD register.
3. Clear the FCBEF flag in the FSTAT register by writing a 1 to FCBEF to launch the command.
After a command is launched, the completion of the command operation is indicated by the setting of
FSTAT[FCCF]. The FCCF flag sets upon completion of all active and buffered burst program commands.
4.4.2
Flash Commands
Table 4-18 summarizes the valid flash commands along with the effects of the commands on the flash
block.
Table 4-18. Flash Command Description
FCMD
NVM
Command
0x05
Erase Verify
0x20
Program
0x25
Burst Program
0x40
Sector Erase
Erase all memory bytes in a sector of the flash array.
0x41
Mass Erase
Erase all memory bytes in the flash array.
A mass erase of the full flash array is only possible when no protection is enabled prior
to launching the command.
Function on Flash Memory
Verify all memory bytes in the flash array memory are erased.
If the flash array memory is erased, FSTAT[FBLANK] sets upon command completion.
Program an address in the flash array.
Program an address in the flash array with the internal address incrementing after the
program operation.
CAUTION
A flash block address must be in the erased state before being programmed.
Cumulative programming of bits within a flash block address is not allowed
except for status field updates required in EEPROM emulation applications.
4.4.2.1
Erase Verify Command
The erase verify operation verifies that the entire flash array memory is erased.
An example flow to execute the erase verify operation is shown in Figure 4-10. The erase verify command
write sequence is as follows:
1. Write to a flash block address to start the command write sequence for the erase verify command.
The address and data written are ignored.
2. Write the erase verify command, 0x05, to the FCMD register.
3. Clear the FCBEF flag in the FSTAT register by writing a 1 to FCBEF to launch the erase verify
command.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
4-31
Memory
After launching the erase verify command, FSTAT[FCCF] sets after the operation has completed. The
number of bus cycles required to execute the erase verify operation is equal to the number of addresses in
the flash array memory plus several bus cycles as measured from the time the FCBEF flag is cleared until
the FCCF flag is set. Upon completion of the erase verify operation, FSTAT[FBLANK] is set if all
addresses in the flash array memory are verified to be erased. If any address in the flash array memory is
not erased, the erase verify operation terminates and FSTAT[FBLANK] remains cleared.
START
Read: FCDIV register
Clock Register
Written
Check
yes
Note: FCDIV needs to
be set after each reset
no
FDIVLD
Set?
Write: FCDIV register
Read: FSTAT register
no
FCBEF
Set?
Command
Buffer Empty Check
yes
Access Error and
Protection Violation
Check
FACCERR/FPVIOL
Set?
no
yes
1.
Write: Flash Block Address
and Dummy Data
2.
Write: FCMD register
Erase Verify Command 0x05
3.
Write: FSTAT register
Clear FCBEF 0x80
Write: FSTAT register
Clear FACCERR/FPVIOL 0x30
Read: FSTAT register
Bit Polling for
Command Completion
Check
FCCF
Set?
no
yes
Erase Verify
Status
FBLANK
Set?
no
yes
EXIT
Flash Block
Erased
EXIT
Flash Block
Not Erased
Figure 4-10. Example Erase Verify Command Flow
MCF51MM256 Series Devices Reference Manual, Rev. 3
4-32
Freescale Semiconductor
Memory
4.4.2.2
Program Command
The program operation programs a previously erased address in the flash memory using an embedded
algorithm. An example flow to execute the program operation is shown in Figure 4-11. The program
command write sequence is as follows:
1. Write to a flash block address to start the command write sequence for the program command. The
data written is programmed to the address written.
2. Write the program command, 0x20, to the FCMD register.
3. Clear the FCBEF flag in the FSTAT register by writing a 1 to FCBEF to launch the program
command.
If an address to be programmed is in a protected area of the flash block, FSTAT[FPVIOL] sets and the
program command does not launch. After the program command has successfully launched and the
program operation has completed, FSTAT[FCCF] is set.
START
Read: FCDIV register
Clock Register
Written
Check
yes
Note: FCDIV needs to
be set after each reset
no
FDIVLD
Set?
Write: FCDIV register
Read: FSTAT register
FCBEF
Set?
Command
Buffer Empty Check
no
yes
Access Error and
Protection Violation
Check
FACCERR/FPVIOL
Set?
no
1.
Write: Flash Array Address
and Program Data
2.
Write: FCMD register
Program Command 0x20
3.
Write: FSTAT register
Clear FCBEF 0x80
yes
Write: FSTAT register
Clear FACCERR/FPVIOL 0x30
Read: FSTAT register
Bit Polling for
Command Completion
Check
FCCF
Set?
no
yes
EXIT
Figure 4-11. Example Program Command Flow
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
4-33
Memory
4.4.2.3
Burst Program Command
The burst program operation programs previously erased data in the flash memory using an embedded
algorithm.
While burst programming, two internal data registers operate as a buffer and a register (2-stage FIFO) so
that a second burst programming command along with the necessary data can be stored to the buffers while
the first burst programming command remains in progress. This pipelined operation allows a time
optimization when programming more than one consecutive address on a specific row in the flash array as
the high voltage generation can be kept active in between two programming commands.
An example flow to execute the burst program operation is shown in Figure 4-12. The burst program
command write sequence is as follows:
1. Write to a flash block address to start the command write sequence for the burst program command.
The data written is programmed to the address written.
2. Write the program burst command, 0x25, to the FCMD register.
3. Clear the FCBEF flag in the FSTAT register by writing a 1 to FCBEF to launch the program burst
command.
4. After the FCBEF flag in the FSTAT register returns to a 1, repeat steps 1 through 3. The address
written is ignored but is incremented internally.
The burst program procedure can be used to program the entire flash memory even while crossing row
boundaries within the flash array. If data to be burst programmed falls within a protected area of the flash
array, FSTAT[FPVIOL] is set and the burst program command does not launch. After the burst program
command has successfully launched and the burst program operation has completed, FSTAT[FCCF] is set
unless a new burst program command write sequence has been buffered. By executing a new burst
program command write sequence on sequential addresses after the FCBEF flag in the FSTAT register has
been set, a greater than 50% faster programming time for the entire flash array can be effectively achieved
when compared to using the basic program command.
MCF51MM256 Series Devices Reference Manual, Rev. 3
4-34
Freescale Semiconductor
Memory
START
Read: FCDIV register
Clock Register
Written
Check
yes
Note: FCDIV needs to
be set after each reset
no
FDIVLD
Set?
Write: FCDIV register
Read: FSTAT register
FCBEF
Set?
Command
Buffer Empty Check
no
yes
Access Error and
Protection Violation
Check
FACCERR/FPVIOL
Set?
no
yes
1.
Write: Flash Array Address
and Program Data
2.
Write: FCMD register
Burst Program Command 0x25
3.
Write: FSTAT register
Clear FCBEF 0x80
Write: FSTAT register
Clear FACCERR/FPVIOL 0x30
Read: FSTAT register
Bit Polling for
Command Buffer Empty
Check
FCBEF
Set?
no
yes
Sequential
Programming
Decision
Next
Address?
yes
no
Read: FSTAT register
Bit Polling for
Command Completion
Check
FCCF
Set?
no
yes
EXIT
Figure 4-12. Example Burst Program Command Flow
4.4.2.4
Sector Erase Command
The sector erase operation erases all addresses in a 2Kbyte sector of flash memory using an embedded
algorithm.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
4-35
Memory
An example flow to execute the sector erase operation is shown in Figure 4-13. The sector erase command
write sequence is as follows:
1. Write to a flash block address to start the command write sequence for the sector erase command.
The flash address written determines the sector to be erased while the data written is ignored.
2. Write the sector erase command, 0x40, to the FCMD register.
3. Clear the FCBEF flag in the FSTAT register by writing a 1 to FCBEF to launch the sector erase
command.
If a flash sector to be erased is in a protected area of the flash block, FSTAT[FPVIOL] is set and the sector
erase command does not launch. After the sector erase command has successfully launched and the sector
erase operation has completed, FSTAT[FCCF] is set.
START
Read: FCDIV register
Clock Register
Written
Check
yes
Note: FCDIV needs to
be set after each reset
no
FDIVLD
Set?
Write: FCDIV register
Read: FSTAT register
FCBEF
Set?
Command
Buffer Empty Check
no
yes
Access Error and
Protection Violation
Check
FACCERR/FPVIOL
Set?
no
yes
1.
Write: Flash Sector Address
and Dummy Data
2.
Write: FCMD register
Sector Erase Command 0x40
3.
Write: FSTAT register
Clear FCBEF 0x80
Write: FSTAT register
Clear FACCERR/FPVIOL 0x30
Read: FSTAT register
Bit Polling for
Command Completion
Check
FCCF
Set?
no
yes
EXIT
Figure 4-13. Example Sector Erase Command Flow
MCF51MM256 Series Devices Reference Manual, Rev. 3
4-36
Freescale Semiconductor
Memory
4.4.2.5
Mass Erase Command
The mass erase operation erases the entire flash array memory using an embedded algorithm. An example
flow to execute the mass erase operation is shown in Figure 4-14. The mass erase command write sequence
is as follows:
1. Write to a flash block address to start the command write sequence for the mass erase command.
The address and data written is ignored.
2. Write the mass erase command, 0x41, to the FCMD register.
3. Clear the FCBEF flag in the FSTAT register by writing a 1 to FCBEF to launch the mass erase
command.
If the flash array memory to be mass erased contains any protected area, FSTAT[FPVIOL] is set and the
mass erase command does not launch. After the mass erase command has successfully launched and the
mass erase operation has completed, FSTAT[FCCF] is set.
START
Read: FCDIV register
Clock Register
Written
Check
yes
Note: FCDIV needs to
be set after each reset
no
FDIVLD
Set?
Write: FCDIV register
Read: FSTAT register
FCBEF
Set?
Command
Buffer Empty Check
no
yes
Access Error and
Protection Violation
Check
FACCERR/FPVIOL
Set?
no
yes
1.
Write: Flash Memory Address
and Dummy Data
2.
Write: FCMD register
Mass Erase Command 0x41
3.
Write: FSTAT register
Clear FCBEF 0x80
Write: FSTAT register
Clear FACCERR/FPVIOL 0x30
Read: FSTAT register
Bit Polling for
Command Completion
Check
FCCF
Set?
no
yes
EXIT
Figure 4-14. Example Mass Erase Command Flow
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
4-37
Memory
NOTE
The BDM can also perform a mass erase and verify command. See
Chapter 29, “Version 1 ColdFire Debug (CF1_DEBUG),” for details.
4.4.3
4.4.3.1
Illegal Flash Operations
Flash Access Violations
The FACCERR flag is set during the command write sequence if any of the following illegal steps are
performed, causing the command write sequence to immediately abort:
1. Writing to a flash address before initializing the FCDIV register.
2. This scenario can cause an illegal address reset as this operation is not supported per the memory
map. To cause an exception instead of a system reset, set the ADR bit of core register CPUCR.
After setting the ADR bit, performing a write operation sets the FACCERR flag.
3. Writing to any flash register other than FCMD after writing to a flash address.
4. Writing to a second flash address in the same command write sequence.
5. Writing an invalid command to the FCMD register.
6. Writing a command other than burst program while FCBEF is set and FCCF is clear.
7. When security is enabled, writing a command other than erase verify or mass erase to the FCMD
register when the write originates from a non-secure memory location or from the background
debug mode.
8. Writing to a flash address after writing to the FCMD register.
9. Writing to any flash register other than FSTAT (to clear FCBEF) after writing to the FCMD
register.
10. Writing a 0 to the FCBEF flag in the FSTAT register to abort a command write sequence.
The FACCERR flag is also set if the MCU enters stop mode while any command is active (FCCF=0). The
operation is aborted immediately and, if burst programming, any pending burst program command is
purged (see Section 4.4.4.2, “Stop Modes”).
The FACCERR flag does not set if any flash register is read during a valid command write sequence.
If the flash memory is read during execution of an algorithm (FCCF = 0), the read operation returns invalid
data and the FACCERR flag is not set.
If the FACCERR flag is set in the FSTAT register, clear the FACCERR flag before starting another
command write sequence (see Section 4.3.3.5, “Flash Status Register (FxSTAT)”).
4.4.3.2
Flash Protection Violations
The FPVIOL flag is set after the command is written to the FCMD register if any of the following illegal
operations are attempted:
1. Writing the program command if the address written in the command write sequence was in a
protected area of the flash array.
MCF51MM256 Series Devices Reference Manual, Rev. 3
4-38
Freescale Semiconductor
Memory
2. Writing the sector erase command if the address written in the command write sequence was in a
protected area of the flash array.
3. Writing the mass erase command while any flash protection is enabled.
As a result of any of the above, the command write sequence immediately aborts. If FSTAT[FPVIOL] is
set, clear the FPVIOL flag before starting another command write sequence (see Section 4.3.3.5, “Flash
Status Register (FxSTAT)”).
4.4.4
4.4.4.1
Operating Modes
Wait Mode
If a command is active (FCCF = 0) when the MCU enters wait mode, the active command and any buffered
command is completed.
4.4.4.2
Stop Modes
If a command is active (FCCF = 0) when the MCU enters any stop mode, the operation is aborted. If the
operation is program or erase, the flash array data being programmed or erased may be corrupted and the
FCCF and FACCERR flags are set. If active, the high voltage circuitry to the flash array is immediately
switched off when entering stop mode. Upon exit from stop mode, the FCBEF flag is set and any buffered
command is not launched. The FACCERR flag must be cleared before starting a command write sequence
(see Section 4.4.1.2, “Command Write Sequence”).
NOTE
As active commands are immediately aborted when the MCU enters stop
mode, do not use the STOP instruction during program or erase operations.
Active commands continue when the MCU enters wait mode. Use of the
STOP instruction when SOPT1[WAITE] is set is acceptable.
4.4.4.3
Background Debug Mode
In background debug mode, the FPROT register is writable without restrictions. If the MCU is unsecured,
all flash commands listed in Table 4-12 can be executed. If the MCU is secured, only a compound mass
erase and erase verify command can be executed. See Chapter 29, “Version 1 ColdFire Debug
(CF1_DEBUG),” for details.
4.4.5
Flash Security
The flash module provides the necessary security information to the MCU. During each reset sequence,
the flash module determines the security state of the MCU as defined in Section 4.1.3, “Flash Module
Reserved Memory Locations”.
The contents of the flash security byte in the flash configuration field (see Section 4.3.3.3) must be
changed directly by programming the flash security byte location when the MCU is unsecured and the
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
4-39
Memory
sector containing the flash security byte is unprotected. If the flash security byte is left in a secured state,
any reset causes the MCU to initialize into a secure operating mode.
4.4.6
4.4.6.1
Resets
Flash Reset Sequence
On each reset, the flash module executes a reset sequence to hold CPU activity while reading the following
resources from the flash block:
• MCU control parameters (see Section 4.1.3)
• Flash protection byte (see Section 4.1.3 and Section 4.3.3.4)
• Flash nonvolatile byte (see Section 4.1.3)
• Flash security byte (see Section 4.1.3 and Section 4.3.3.2)
4.4.6.2
Reset While Flash Command Active
If a reset occurs while any flash command is in progress, that command is immediately aborted. The state
of the flash array address being programmed or the sector/block being erased is not guaranteed.
4.4.6.3
Program and Erase Times
Before any program or erase command can be accepted, the flash clock divider (FCDIV) must be written
to set the internal clock for the flash module to a frequency (fFCLK) between 150 kHz and 200 kHz.
If the initial flash event is a mass erase and verify from BDM, then CSR3[31:24] must be loaded before
the XCSR is written to initiate the erase and verify. The data in the XCSR and CSR3 is then loaded into
the flash’s FCDIV register. (See Section 29.3.4, “Configuration/Status Register 3 (CSR3)”). However, if
the first flash event is executed by the processor directly, the flash’s FCDIV register is written directly, and
the XCSR and CSR3 are not involved.
One period of the resulting clock (1/fFCLK) is used by the command processor to time program and erase
pulses. An integer number of these timing pulses are used by the command processor to complete a
program or erase command.
Program and erase times are given in the MCF51MM256 Data Sheet, order number MCF51MM256.
4.5
Security
The MCF51MM256/128 microcontroller includes circuitry to prevent unauthorized access to the contents
of flash and RAM memory. When security is engaged, BDM access is restricted to the upper byte of the
ColdFire CSR, XCSR, and CSR2 registers. RAM, flash memory, peripheral registers and most of the CPU
register set are not available via BDM. Programs executing from internal memory have normal access to
all microcontroller memory locations and resources.
The MCF51MM256/128 devices include two independent flash blocks in support of the robust update
feature for on-chip flash. Each flash block has its own set of two security bits as described below. Security
must be clear ON BOTH flash blocks in order for the device to be unsecured. This allows the device to
MCF51MM256 Series Devices Reference Manual, Rev. 3
4-40
Freescale Semiconductor
Memory
remain secure, even when updating one of the two flash blocks during a code upgrade. The remainder of
this section discusses security from the perspective of a single flash block. Routines for clearing flash
security must be applied to both blocks before the device can be unsecured.
Security is engaged or disengaged based on the state of two nonvolatile register bits (SEC01, SEC00) in
the FxOPT register. During reset, the contents of the nonvolatile location, NVxOPT, are copied from flash
into the working FxOPT register in high-page register space. A user engages security by programming the
NVxOPT location which can be done at the same time the flash memory is programmed. The 1:0 stage
engages the security and other three combinations disengage security.
Upon exiting reset, the XCSR[25] bit in the ColdFire CPU is initialized to one if the device is secured, zero
otherwise.
A user can choose to allow or disallow a security unlocking mechanism through an 8-byte backdoor
security key. The security key can be written by the CPU executing from internal memory. It cannot be
entered without the cooperation of a secure user program. The procedure for this is detailed in Section
4.5.1, “Unsecuring the MCU using Backdoor Key Access.”
Development tools will unsecure devices via an alternate BDM-based methodology shown in Figure 4-15.
Because both RESET and BKGD pins can be reprogrammed via software, a power-on-reset is required to
be absolutely certain of obtaining control of the device via BDM, which is a required prerequisite for
clearing security. Other methods (outlined in red in Figure 4-15) can also be used, but may not work under
all circumstances.
This device supports two levels of security. Both restrict BDM communications as outlined above. In
addition, SOPT1[SL] (see Section 5.7.3, “System Options 1 (SOPT1) Register”) can be used to
enable/disable off-chip data accesses through the Mini-FlexBus interface. Off-chip op code accesses
through the Mini-FlexBus are always disallowed when security is enabled.
4.5.1
Unsecuring the MCU using Backdoor Key Access
The MCU may be unsecured by using the backdoor key access feature that requires knowledge of the
contents of the backdoor keys (see Section 4.1.3, “Flash Module Reserved Memory Locations”). If the
KEYEN[1:0] bits are in the enabled state (see Section 4.3.3.2, “Flash Options Register (FxOPT and
NVxOPT)”) and the KEYACC bit is set, a write to a backdoor key address in the flash memory triggers a
comparison between the written data and the backdoor key data stored in the flash memory. If all backdoor
keys are written to the correct addresses in the correct order and the data matches the backdoor keys stored
in the flash memory, the MCU is unsecured. The data must be written to the backdoor keys sequentially.
Values 0x0000_0000 and 0xFFFF_FFFF are not permitted as backdoor keys. While the KEYACC bit is
set, reads of the flash memory return valid data.
The user code stored in the flash memory must have a method of receiving the backdoor keys from an
external stimulus. This external stimulus would typically be through one of the on-chip serial ports.
If the KEYEN[1:0] bits are in the enabled state (see Section 4.3.3.2, “Flash Options Register (FxOPT and
NVxOPT)”), the MCU can be unsecured by the backdoor key access sequence described below:
1. Set FxCNFG[KEYACC].
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
4-41
Memory
2. Execute three NOP instructions to provide time for the backdoor state machine to load the starting
address and number of keys required into the flash state machine.
3. Sequentially write the correct longwords to the flash address(es) containing the backdoor keys.
4. Clear the KEYACC bit. Depending on the user code used to write the backdoor keys, a wait cycle
(NOP) may be required before clearing the KEYACC bit.
5. If all data written match the backdoor keys, the MCU is unsecured and the SEC[1:0] bits in the
NVxOPT register are forced to an unsecured state.
The backdoor key access sequence is monitored by an internal security state machine. An illegal operation
during the backdoor key access sequence causes the security state machine to lock, leaving the MCU in
the secured state. A reset of the MCU causes the security state machine to exit the lock state and allows a
new backdoor key access sequence to be attempted. The following operations during the backdoor key
access sequence lock the security state machine:
1. If any of the keys written does not match the backdoor keys programmed in the flash array.
2. If the keys are written in the wrong sequence.
3. If any of the keys written are all 0’s or all 1’s.
4. If the KEYACC bit does not remain set while the keys are written.
5. If any of the keys are written on successive MCU clock cycles.
6. Executing a STOP instruction before all keys have been written.
After the backdoor keys have been correctly matched, the MCU is unsecured. After the MCU is unsecured,
the flash security byte can be programmed to the unsecure state, if desired.
In the unsecure state, you have full control of the contents of the backdoor keys by programming the
associated addresses in the flash configuration field (see Section 4.1.3, “Flash Module Reserved Memory
Locations”).
The security as defined in the flash security byte is not changed by using the backdoor key access sequence
to unsecure. The stored backdoor keys are unaffected by the backdoor key access sequence. After the next
reset of the MCU, the security state of the flash module is determined by the flash security byte. The
backdoor key access sequence has no effect on the program and erase protections defined in the flash
protection register (FxPROT).
It is not possible to unsecure the MCU by using the backdoor key access sequence in background debug
mode (BDM) as the MCU does not allow flash array writes in BDM to the flash module.
MCF51MM256 Series Devices Reference Manual, Rev. 3
4-42
Freescale Semiconductor
Memory
N = number of cycles for SIM to release
internal reset. Adder of 16 imposed by the
ColdFire core.
secure state unknown / unpowered
hold BKGD=0, apply power, wait N+16 cycles for
POR to de-assert
BKGD=0 during reset will
ensure that ENBDM comes up "1"
FLL Enabled, Internal Reference (FEI)
at 10MHz is reset default for the ICS
secure state unknown, CPU halted, FEI 10MHz
clock, sync required
SYNC
xcsr[31:24] != 1000 01-1
secure state unknown,, CPU halted, FEI 10MHz
clock, synchronized to debugger
STOP
error condition
check code or device
STOP
already unsecured
Read XCSR
xcsr[25]=0
xcsr[31:24]==0x87
set PRDIV8 and clock divider fields in CSR3
.
write xcsr[31:24]=0x87 to initiate erase/verify
of flash memory
read xcsr[25] to confirm
erase/verify complete
A
The write IS required
no
The FTSR is responsible for supplying
an "erase completed and verified" flag
for use by the core in this step.
Ways to enter BDM halt mode:
yes
on-chip flash is erased and un-secure
write csr2[25:24]=11 to initiate BDM reset to halt or
write csr2[25:0]=01 to initiate BDM reset to run
1
Delay "TBD" cycles
Device is unsecure
1. The last three steps are optional, but
recommended.
1.
2.
3.
4.
5.
BKGD=0 during POR
BKGD=0 during BDM reset
BFHBR=1 during BDM reset
COP reset and CSR2[COPHR]=1
Illegal op code reset and
CSR2[IOPHR]=1
6. Illegal address reset and
CSR2[IADHR]=1
7. Loss of Lock reset with
CSR2[LOLHR]=1
8. Issue BACKGROUND cmd via BDM
interface
9. HALT instruction
10.BDM breakpoint
11.ColdFire Fault-on-Fault
Of these, only method (1) is
guaranteed to work under all
circumstances.
Figure 4-15. Procedure for Clearing Security on MCF51MM256/128 MCUs via the BDM Port 1
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
4-43
Memory
secure state unknown / unpowered
hold BKGD=0, apply power, wait N+16 cycles for
POR to de-assert
secure state unknown, CPU halted, FEI 10MHz
clock, sync required
N = number of cycles for SIM to release
internal reset. Adder of 16 imposed by the
ColdFire core.
BKGD=0 during reset will
ensure that ENBDM comes up "1"
FLL Enabled, Internal Reference (FEI)
at 10MHz is reset default for the ICS
SYNC
secure state unknown,, CPU halted, FEI 10MHz
clock, synchronized to debugger
xcsr[31:24] != 1000 01-1
STOP
error condition
check code or device
STOP
already unsecured
Read XCSR
xcsr[25]=0
xcsr[31:24]==0x87
set PRDIV8 and clock divider fields in CSR3
write xcsr[31:24]=0x8F to transfer divider info to
FTSR
Write PTIMER bits to CSR3
write xcsr[31:24]=0x97 to transfer PTIMER info to
FTSR and initiate erase/verify of flash memory
A
Figure 4-16. Procedure for Clearing Security on MCF51MM256/128 MCUs via the BDM Port 2
MCF51MM256 Series Devices Reference Manual, Rev. 3
4-44
Freescale Semiconductor
Chapter 5
Resets, Interrupts, and General System Control
5.1
Introduction
This section discusses basic reset and interrupt mechanisms and the various sources of reset and interrupt
on an MCF51MM256 series microcontroller. Some interrupt sources from peripheral modules are
discussed in greater detail within other sections of this document. This section gathers basic information
about all reset and interrupt sources in one place for easy reference.
5.2
Features
Reset and interrupt features include:
• Multiple sources of reset for flexible system configuration and reliable operation
• System reset status (SRS) register to indicate source of most recent reset
• Separate interrupt vector for most modules (reduces polling overhead) (see Table 5-1)
5.3
Microcontroller Reset
Resetting the microcontroller provides a way to start processing from a known set of initial conditions.
When the ColdFire processor exits reset, it fetches initial 32-bit values for the supervisor stack pointer and
program counter from locations 0x(00)00_0000 and 0x(00)00_0004 respectively. On-chip peripheral
modules are disabled and I/O pins are initially configured as general-purpose high-impedance inputs with
pull-up devices disabled.
The MCF51MM256 series microcontrollers have the following sources for reset:
• Power-on reset (POR)
• External pin reset (PIN)
• Computer operating properly (COP) timer
• Illegal opcode detect (ILOP)
• Illegal address detect (ILAD)
• Low-voltage detect (LVD)
• Clock generator (MCG) loss of clock reset (LOC)
• Background debug forced reset
Each of these sources, with the exception of the background debug forced reset, has an associated bit in
the system reset status register (SRS).
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
5-1
Resets, Interrupts, and General System Control
5.3.1
Computer Operating Properly (COP) Watchdog
The COP watchdog is intended to force a system reset when the application software fails to execute as
expected. To prevent a system reset from the COP timer (when it is enabled), application software must
reset the COP counter periodically. If the application program gets lost and fails to reset the COP counter
before it times out, a system reset is generated to force the system back to a known starting point.
After any reset, the COP watchdog is enabled (see Section 5.7.3, “System Options 1 (SOPT1) Register,”
for additional information). If the COP watchdog is not used in an application, it can be disabled by
clearing SOPT1[COPT].
The COP counter is reset by writing 0x55 and 0xAA (in this order) to the address of SRS during the
selected timeout period. Writes do not affect the data in the read-only SRS. As soon as the write sequence
is done, the COP timeout period is restarted. If the program fails to do this during the time-out period, the
microcontroller resets. Also, if any value other than 0x55 or 0xAA is written to SRS, the microcontroller
is immediately reset.
The SOPT2[COPCLKS] field (see Section 5.7.4, “System Options 2 (SOPT2) Register,” for additional
information) selects the clock source used for the COP timer. The clock source options are the bus clock
or an internal 1 kHz LPOCLK source. With each clock source, there are three associated time-outs
controlled by SOPT1[COPT]. Table 5-7 summarizes the control functions of the COPCLKS and COPT
bits. The COP watchdog defaults to operation from the 1 kHz LPOCLK source and the longest time-out
(210 cycles).
When the bus clock source is selected, windowed COP operation is available by setting SOPT2[COPW].
In this mode, writes to the SRS register to clear the COP timer must occur in the last 25% of the selected
timeout period. A premature write immediately resets the microcontroller. When the 1 kHz LPOCLK
source is selected, windowed COP operation is not available.
The COP counter is initialized by the first writes to the SOPT1 and SOPT2 registers and after any system
reset. Subsequent writes to SOPT1 and SOPT2 have no effect on COP operation. Even if the application
uses the reset default settings of the COPT, COPCLKS, and COPW bits, the user should write to the
write-once SOPT1 and SOPT2 registers during reset initialization to lock in the settings. This prevents
accidental changes if the application program gets lost.
The write to SRS that services (clears) the COP counter should not be placed in an interrupt service routine
(ISR) because the ISR could continue to be executed periodically even if the main application program
fails.
If the bus clock source is selected, the COP counter does not increment while the microcontroller is in
background debug mode or while the system is in stop mode. The COP counter resumes when the
microcontroller exits background debug mode or stop mode.
If the 1 kHz LPOCLK source is selected, the COP counter is re-initialized to zero upon entry to
background debug mode or stop mode and begins from zero upon exit from background debug mode or
stop mode.
MCF51MM256 Series Devices Reference Manual, Rev. 3
5-2
Freescale Semiconductor
Resets, Interrupts, and General System Control
5.3.2
Illegal Opcode Detect (ILOP)
The default configuration of the V1 ColdFire core enables the generation of an MCU reset in response to
the processor's attempted execution of an illegal instruction (except for the ILLEGAL opcode), illegal line
A, illegal line F instruction or the detection of a privilege violation (attempted execution of a supervisor
instruction while in user mode).
The attempted execution of the STOP instruction with (SOPT[STOPE] = 0 && SOPT[WAITE] = 0) is
treated as an illegal instruction.
The attempted execution of the HALT instruction with XCSR[ENBDM] = 0 is treated as an illegal
instruction.
The processor generates a reset in response to any of these events if CPUCR[IRD] = 0. If this
configuration bit is set, the processor generates the appropriate exception instead of forcing a reset.
5.3.3
Illegal Address Detect (ILAD)
The default configuration of the V1 ColdFire core enables the generation of an MCU reset in response to
any processor-detected address error, bus error termination, RTE format error or fault-on-fault condition.
The processor generates a reset if CPUCR[ARD] = 0. If this configuration bit is set, the processor
generates the appropriate exception instead of forcing a reset, or simply halts the processor in response to
the fault-on-fault condition.
5.4
Interrupts & Exceptions
The interrupt architecture of ColdFire utilizes a 3-bit encoded interrupt priority level sent from the
interrupt controller to the core, providing 7 levels of interrupt requests. Level 7 represents the highest
priority interrupt level, while level 1 is the lowest priority. The processor samples for active interrupt
requests once per instruction by comparing the encoded priority level against a 3-bit interrupt mask
value (I) contained in bits 10:8 of the processor’s status register (SR). If the priority level is greater than
the SR[I] field at the sample point, the processor suspends normal instruction execution and initiates
interrupt exception processing.
Level 7 interrupts are treated as non-maskable and edge-sensitive within the processor, while levels 1-6
are treated as level-sensitive and may be masked depending on the value of the SR[I] field. For correct
operation, the ColdFire processor requires that, after asserted, the interrupt source remain asserted until
explicitly disabled by the interrupt service routine.
During the interrupt exception processing, the CPU does the following tasks in order:
1. enters supervisor mode,
2. disables trace mode,
3. uses the vector provided by the INTC when the interrupt was signaled (if CPUCR[IACK] = 0) or
explicitly fetches an 8-bit vector from the INTC (if CPUCR[IACK] = 1).
This byte-sized operand fetch during exception processing is known as the interrupt acknowledge (IACK)
cycle. The fetched data provides an index into the exception vector table that contains up to 256 addresses
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
5-3
Resets, Interrupts, and General System Control
(depending upon the specific device), each pointing to the beginning of a specific exception service
routine.
In particular, the first 64 exception vectors are reserved for the processor to manage reset, error conditions
(access, address), arithmetic faults, system calls, etc. Vectors 64–255 are reserved for interrupt service
routines. The MCF51MM256 series microcontrollers support 37 peripheral interrupt sources and an
additional seven software interrupt sources. These are mapped into the standard seven ColdFire interrupt
levels, with up to 9 levels of prioritization within a given level by the V1 ColdFire interrupt controller. See
Table 5-1 for details.
After the interrupt vector number has been retrieved, the processor continues by creating a stack frame in
memory. For ColdFire, all exception stack frames are two longwords in length, and contain 32 bits of
vector and status register data, along with the 32-bit program counter value of the instruction that was
interrupted. After the exception stack frame is stored in memory, the processor accesses the 32-bit pointer
from the exception vector table using the vector number as the offset, and then jumps to that address to
begin execution of the service routine. After the status register is stored in the exception stack frame, the
SR[I] mask field is set to the level of the interrupt being acknowledged, effectively masking that level and
all lower values while in the service routine.
All ColdFire processors guarantee that the first instruction of the service routine is executed before
interrupt sampling is resumed. By making this initial instruction a load of the SR, interrupts can be safely
disabled, if required. Optionally, the processor can be configured to automatically raise the mask level to
7 for any interrupt during exception processing by setting CPUCR[IME] = 1.
During the execution of the service routine, the appropriate actions must be performed on the peripheral
to negate the interrupt request.
For more information on exception processing, see the ColdFire Programmer’s Reference Manual. For
additional information specific to this device, see Chapter 29, “Version 1 ColdFire Debug
(CF1_DEBUG).”
5.4.1
External Interrupt Request (IRQ) Pin
External interrupts are managed by the IRQ status and control register, IRQSC. When the IRQ function is
enabled, synchronous logic monitors the pin for edge-only or edge-and-level events. When the
microcontroller is in stop mode and system clocks are shut down, a separate asynchronous path is used, so
the IRQ pin (if enabled) can wake the microcontroller.
•
•
NOTE
This pin does not contain a clamp diode to VDD and should not be driven
above VDD.
The voltage measured on the internally pulled up IRQ pin will not be
pulled to VDD. The internal gates connected to this pin are pulled to
VDD. The IRQ pullup should not be used to pull up components external
to the microcontroller.
MCF51MM256 Series Devices Reference Manual, Rev. 3
5-4
Freescale Semiconductor
Resets, Interrupts, and General System Control
5.4.1.1
Pin Configuration Options
The IRQ pin enable (IRQPE) control bit in IRQSC must be set for the IRQ pin to act as the interrupt request
(IRQ) input. As an IRQ input, the user can choose the polarity of edges or levels detected (IRQEDG),
whether the pin detects edges-only or edges and levels (IRQMOD), and whether an event causes an
interrupt or only sets the IRQF flag that can be polled by software (IRQIE).
The IRQ pin, when enabled, defaults to use an internal pull device (IRQPDD = 0), configured as a pull-up
or pull-down depending on the polarity chosen. If the user desires to use an external pull-up or pull-down,
the IRQPDD can be set to turn off the internal device.
•
•
5.4.1.2
NOTE
This pin does not contain a clamp diode to VDD and should not be driven
above VDD.
The voltage measured on the internally pulled up IRQ pin is not pulled
to VDD. The internal gates connected to this pin are pulled to VDD. The
IRQ pullup should not be used to pull up components external to the
microcontroller.
Edge and Level Sensitivity
The IRQMOD control bit re-configures the detection logic so it detects edge events and pin levels. In the
edge and level detection mode, the IRQF status flag becomes set when an edge is detected (when the IRQ
pin changes from the deasserted to the asserted level), but the flag is continuously set (and cannot be
cleared) as long as the IRQ pin remains at the asserted level.
5.4.2
Interrupt Vectors, Sources, and Local Masks
Table 5-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table
are the labels used in the Freescale Semiconductor-provided equate file for the MCF51MM256 series
microcontrollers. The table is sorted by priority of the sources, with higher-priority sources at the top of
the table. The force_lvl entries do not follow the address and vector number order of the surrounding
vectors.
Table 5-1. Address Assignments for Reset and Interrupt Vectors
Vector
Number(s)
Vector Address
Offset
Interrupt
Level
Priority within
Level
Stacked
Program
Counter
0
0x000
—
N/A
—
Initial supervisor
stack pointer
1
0x004
—
N/A
—
Initial program
counter
2–63
—
—
N/A
—
Reserved for
internal CPU
exceptions (see
Table 7-6)
Assignment
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
5-5
Resets, Interrupts, and General System Control
Table 5-1. Address Assignments for Reset and Interrupt Vectors (Continued)
Vector
Number(s)
Vector Address
Offset
Interrupt
Level
Priority within
Level
Stacked
Program
Counter
Assignment
—
—
7
7-5
—
Reserved
64
0x100
7
mid
Next
IRQ_pin
65
0x104
7
3
Next
Low_voltage_detect
66
0x108
7
2
Next
Loss of Lock
67
0x10C
7
1
Next
Reserved
—
—
6
7
—
Reserved for
remapped vector #1
—
—
6
6
—
Reserved for
remapped vector #2
68
0x110
6
5
Next
PDB
69
0x114
6
4
Next
DAC
70
0x118
6
3
Next
SPI1
71
0x11C
6
2
Next
ADC
72
0x120
6
1
Next
USB_Status
73
0x124
5
7
Next
TPM1_ch0
74
0x128
5
6
Next
TPM1_ch1
75
0x12C
5
5
Next
TPM1_ch2
76
0x130
5
4
Next
TPM1_ch3
77
0x134
5
3
Next
TPM1_ovfl
78
0x138
5
2
Next
SPI2
79
0x13C
5
1
Next
CMT
80
0x140
4
7
Next
TPM2_ch0
81
0x144
4
6
Next
TPM2_ch1
82
0x148
4
5
Next
TPM2_ch2
83
0x14C
4
4
Next
TPM2_ch3
84
0x150
4
3
Next
TPM2_ovfl
85
0x154
4
2
Next
IIC
86
0x158
4
1
Next
PRACMP
87
0x15C
3
7
Next
SCI1_err
88
0x160
3
6
Next
SCI1_rx
89
0x164
3
5
Next
SCI1_tx
MCF51MM256 Series Devices Reference Manual, Rev. 3
5-6
Freescale Semiconductor
Resets, Interrupts, and General System Control
Table 5-1. Address Assignments for Reset and Interrupt Vectors (Continued)
Vector
Number(s)
Vector Address
Offset
Interrupt
Level
Priority within
Level
Stacked
Program
Counter
Assignment
90
0x168
3
4
Next
SCI2_err
91
0x16C
3
3
Next
SCI2_rx
92
0x170
3
2
Next
SCI2_tx
93
0x174
3
1
Next
EXPANSION
94
0x178
2
7
Next
EXPANSION
95
0x17C
2
6
Next
KBI1
96
0x180
2
5
Next
KBI2
97
0x184
2
4
Next
TOD
98
0x188
2
3
Next
EXPANSION
99
0x18C
2
2
Next
EXPANSION
100
0x190
2
1
Next
EXPANSION
101
0x194
1
7
Next
EXPANSION
102
0x198
1
6
Next
EXPANSION
103
0x19C
7
0
Next
Level 7 Software
Interrupt
104
0x1A0
6
0
Next
Level 6 Software
Interrupt
105
0x1A4
5
0
Next
Level 5 Software
Interrupt
106
0x1A8
4
0
Next
Level 4 Software
Interrupt
107
0x1AC
3
0
Next
Level 3 Software
Interrupt
108
0x1B0
2
0
Next
Level 2 Software
Interrupt
109
0x1B4
1
0
Next
Level 1 Software
Interrupt
110
0x1B8
1
5
Next
EXPANSION
111
0x1BC
1
4
Next
EXPANSION
112
0x1C0
1
3
Next
FTSR1
113
0x1C4
1
2
Next
FTSR2
114
0x1C8
1
1
Next
EXPANSION
115
0x1CC
N/A
N/A
Next
Reserved
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
5-7
Resets, Interrupts, and General System Control
Table 5-1. Address Assignments for Reset and Interrupt Vectors (Continued)
Vector
Number(s)
Vector Address
Offset
Interrupt
Level
Priority within
Level
Stacked
Program
Counter
Assignment
…
…
…
…
Next
Reserved
255
0x3FC
N/A
N/A
Next
Reserved
Not shown in Table 5-1 are the standard set of ColdFire exceptions, many of which apply to this device.
These are listed below in Table 5-2.
The CPU configuration register (CPUCR) within the supervisor programming model allows the users to
determine if specific ColdFire exception conditions are to generate a normal exception or a system reset.
The default state of the CPUCR forces a system reset for any of the exception types listed in Table 5-2.
Table 5-2. ColdFire Exception Vector Table1
Vector
Exception
Reset Disabled via CPUCR
Reported using SRS
64-98
I/O Interrupts
N/A
—
61
Unsupported instruction
N/A
—
47
Trap #15
N/A
—
46
Trap #14
N/A
—
45
Trap #13
N/A
—
44
Trap #12
N/A
—
43
Trap #11
N/A
—
42
Trap #10
N/A
—
41
Trap #9
N/A
—
40
Trap #8
N/A
—
39
Trap #7
N/A
—
38
Trap #6
N/A
—
37
Trap #5
N/A
—
36
Trap #4
N/A
—
35
Trap #3
N/A
—
34
Trap #2
N/A
—
33
Trap #1
N/A
—
32
Trap #0
N/A
—
24
Spurious IRQ
N/A
—
14
Format error
CPUCR[31]
ilad
12
Debug breakpoint IRQ
N/A
—
11
Illegal LineF
CPUCR[30]
ilop
MCF51MM256 Series Devices Reference Manual, Rev. 3
5-8
Freescale Semiconductor
Resets, Interrupts, and General System Control
Table 5-2. ColdFire Exception Vector Table1 (Continued)
Vector
Exception
Reset Disabled via CPUCR
Reported using SRS
10
Illegal LineA
CPUCR[30]
ilop
9
Trace
N/A
—
8
Privileged Violation
CPUCR[30]
ilop
4
Illegal instruction
CPUCR[30]
ilop2
3
Address error
CPUCR[31]
ilad
2
Access error
CPUCR[31]
ilad
n/a
Flt-on-Flt Halt
CPUCR[31]
ilad
1
Exception vector numbers not appearing in this table are not applicable to the V1 core and
are “reserved”.
2
The execution of the ILLEGAL instruction (0x4AFC) always generates an illegal instruction
exception, regardless of the state of CPUCR[30].
5.5
Low-Voltage Detect (LVD) System
The MCF51MM256/128 microcontroller includes a system to protect against low voltage conditions to
protect memory contents and control microcontroller system states during supply voltage variations. The
system is comprised of a power-on reset (POR) circuit and a LVD circuit with a user-selectable trip
voltage, either high (VLVDH) or low (VLVDL). The LVD circuit is enabled when the SPMSC1[LVDE] bit
is set and the trip voltage is selected by the SPMSC3[LVDV] bit. The LVD is disabled upon entering Stop2
or Stop3 modes unless the LVDSE bit is set. If both LVDE and LVDSE are set when the STOP instruction
is processed, the device will enter STOP4 mode. The LVD can be left enabled in this mode.
5.5.1
Power-On Reset Operation
When power is initially applied to the microcontroller, or when the supply voltage drops below the
power-on reset re-arm voltage level, VPOR, the POR circuit will cause a reset condition. As the supply
voltage rises, the LVD circuit will hold the microcontroller in reset until the supply has risen above the
LVD low threshold, VLVDL. Both the POR bit and the LVD bit in SRS are set following a POR.
5.5.2
LVD Reset Operation
The LVD can be configured to generate a reset upon detection of a low voltage condition by setting
LVDRE to 1. The low voltage detection threshold is determined by the LVDV bit. After an LVD reset has
occurred, the LVD system will hold the microcontroller in reset until the supply voltage has risen above
the low voltage detection threshold. The LVD bit in the SRS register is set following either an LVD reset
or POR.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
5-9
Resets, Interrupts, and General System Control
5.5.3
LVD Interrupt Operation
When a low-voltage condition is detected and the LVD circuit is configured using SPMSC1 for interrupt
operation (LVDE set, LVDIE set, and LVDRE clear), then LVDF in SPMSC1 will be set and an LVD
interrupt request will occur. To clear the LVDF bit, write a 1 to the LVDACK bit in SPMSC1.
5.5.4
Low-Voltage Warning (LVW) Interrupt Operation
The LVD system has a low voltage warning flag (LVWF) to indicate that the supply voltage is
approaching, but is above, the LVD voltage. The LVW also has an interrupt associated with it, enabled by
setting the SPMSC3[LVWIE] bit. If enabled, an LVW interrupt request will occur when the LVWF is set.
Write a 1 to the SPMSC3[LVWACK] bit to clear LVWF. There are two user-selectable trip voltages for
the LVW, one high (VLVWH) and one low (VLVWL). Use the SPMSC3[LVWV] bit to select the trip voltage.
5.6
Peripheral Clock Gating
The MCF51MM256 series microcontroller includes a clock gating system to manage the bus clock sources
to the individual peripherals. Using this system, the user can enable or disable the bus clock to each of the
peripherals at the clock source, eliminating unnecessary clocks to peripherals which are not in use; thereby
reducing the overall run and wait mode currents.
Out of reset, all peripheral clocks will be enabled. For lowest possible run or wait currents, user software
should disable the clock source to any peripheral not in use. The actual clock will be enabled or disabled
immediately following the write to the clock gating control registers (SCGC1, SCGC2, SCGC3). Any
peripheral with a gated clock can not be used unless its clock is enabled. Writing to the registers of a
peripheral with a disabled clock has no effect.
NOTE
Your software should disable the peripheral before disabling the clocks to
the peripheral. When clocks are re-enabled to a peripheral, the peripheral
registers need to be re-initialized by software.
In stop modes, the bus clock is disabled for all gated peripherals, regardless of the settings in the SCGC1,
SCGC2, and SCGC3 registers.
5.7
Reset, Interrupt, and System Control Registers and Control Bits
One 8-bit register in the direct page register space and eight 8-bit registers in the high-page register space
are related to reset and interrupt systems.
Refer to Section 4.1.2, “Detailed register addresses and bit assignments,” for the absolute address
assignments for all registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
Some control bits in the SOPT1 and SPMSC2 registers are related to modes of operation. Although brief
descriptions of these bits are provided here, the related functions are discussed in greater detail in
Chapter 3, “Modes of Operation.”
MCF51MM256 Series Devices Reference Manual, Rev. 3
5-10
Freescale Semiconductor
Resets, Interrupts, and General System Control
5.7.1
Interrupt Pin Request Status and Control Register (IRQSC)
This direct page register includes status and control bits used to configure the IRQ function, report status,
and acknowledge IRQ events.
7
R
6
5
4
IRQPDD
IRQEDG
IRQPE
0
3
2
IRQF
0
W
Reset
1
0
IRQIE
IRQMOD
0
0
IRQACK
0
0
0
0
0
0
Figure 5-1. Interrupt Request Status and Control Register (IRQSC)
Table 5-3. IRQSC Register Field Descriptions
Field
7
Description
Reserved, should be cleared.
6
IRQPDD
Interrupt Request (IRQ) Pull Device Disable— This read/write control bit is used to disable the internal
pull-up/pull-down device when the IRQ pin is enabled (IRQPE = 1) allowing for an external device to be used.
0 IRQ pull device enabled if IRQPE = 1.
1 IRQ pull device disabled if IRQPE = 1.
5
IRQEDG
Interrupt Request (IRQ) Edge Select — This read/write control bit is used to select the polarity of edges or
levels on the IRQ pin that cause IRQF to be set. The IRQMOD control bit determines whether the IRQ pin is
sensitive to both edges and levels or only edges. When IRQEDG = 1 and the internal pull device is enabled, the
pull-up device is reconfigured as an optional pull-down device.
0 IRQ is falling edge or falling edge/low-level sensitive.
1 IRQ is rising edge or rising edge/high-level sensitive.
4
IRQPE
IRQ Pin Enable — This read/write control bit enables the IRQ pin function. When this bit is set the IRQ pin can
be used as an external interrupt request.
0 IRQ pin function is disabled.
1 IRQ pin function is enabled.
3
IRQF
2
IRQACK
1
IRQIE
0
IRQMOD
IRQ Flag — This read-only status bit indicates when an interrupt request event has occurred.
0 No IRQ request.
1 IRQ event detected.
IRQ Acknowledge — This write-only bit is used to acknowledge interrupt request events (write 1 to clear IRQF).
Writing 0 has no meaning or effect. Reads always return 0. If edge-and-level detection is selected (IRQMOD = 1),
IRQF cannot be cleared while the IRQ pin remains at its asserted level.
IRQ Interrupt Enable — This read/write control bit determines whether IRQ events generate an interrupt
request.
0 Interrupt request when IRQF set is disabled (use polling).
1 Interrupt requested when IRQF = 1.
IRQ Detection Mode — This read/write control bit selects edge-only detection or edge-and-level detection. The
IRQEDG control bit determines the polarity of edges and levels that are detected as interrupt request events. See
Section 5.4.1.2, “Edge and Level Sensitivity” for more details.
0 IRQ event on falling edges or rising edges only.
1 IRQ event on falling edges and low levels or on rising edges and high levels.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
5-11
Resets, Interrupts, and General System Control
5.7.2
System Reset Status Register (SRS)
This high page register includes read-only status flags to indicate the source of the most recent reset. When
a debug host forces reset by setting CSR2[BDFR], none of the status bits in SRS is set. To reset the COP
counter, write 0x55 and 0xAA (in this order) to the address of SRS during the selected timeout period. The
reset state of these bits depends on what caused the microcontroller to reset.
R
7
6
5
4
3
2
1
0
POR
PIN
COP
ILOP
ILAD
LOC
LVD
0
W
Writing any value to SRS address clears COP watchdog timer.
POR:
1
0
0
0
0
0
1
0
LVD:
u
0
0
0
0
0
1
0
Any other
reset:
0
Note1
Note1
Note1
Note1
0
0
0
1
Any of these reset sources that are active at the time of reset entry causes the corresponding bit(s) to be set. Bits corresponding
to sources that are not active at the time of reset entry are cleared.
Figure 5-2. System Reset Status (SRS)
Table 5-4. SRS Register Field Descriptions
Field
Description
7
POR
Power-On Reset — Reset was caused by the power-on detection logic. Because the internal supply voltage was
ramping up at the time, the low-voltage reset (LVD) status bit is also set to indicate that the reset occurred while
the internal supply was below the LVD threshold.
0 Reset not caused by POR.
1 POR caused reset.
6
PIN
External Reset Pin — Reset was caused by an active-low level on the external reset pin.
0 Reset not caused by external reset pin.
1 Reset came from external reset pin.
5
COP
Computer Operating Properly (COP) Watchdog — Reset was caused by the COP watchdog timer timing out.
This reset source can be blocked by SOPT1[COPT] = 0b00.
0 Reset not caused by COP timeout.
1 Reset caused by COP timeout.
4
ILOP
Illegal Opcode — Reset was caused by an attempt to execute an unimplemented or illegal opcode. This includes
any illegal instruction [except the ILLEGAL (0x4AFC) opcode] or a privilege violation (execution of a privileged
instruction in user mode). The STOP instruction is considered illegal if stop is disabled by
((SOPT[STOPE] = 0) && (SOPT[WAITE] = 0)). The HALT instruction is considered illegal if the BDM interface is
disabled by XCSR[ENBDM] = 0.
0 Reset not caused by an illegal opcode.
1 Reset caused by an illegal opcode.
3
ILAD
Illegal Address — Reset was caused by the processor's attempted access of an illegal address in the memory
map, an address error, an RTE format error or the fault-on-fault condition. All the illegal address resets are
enabled when CPUCR[ARD] = 0. When CPUCR[ARD] = 1, then the appropriate processor exception is
generated instead of the reset, or if a fault-on-fault condition is reached, the processor simply halts.
0 Reset not caused by an illegal access.
1 Reset caused by an illegal access.
MCF51MM256 Series Devices Reference Manual, Rev. 3
5-12
Freescale Semiconductor
Resets, Interrupts, and General System Control
Table 5-4. SRS Register Field Descriptions (Continued)
Field
Description
2
LOC
Loss-of-Clock Reset — Reset was caused by a loss of external clock.
0 Reset not caused by a loss of external clock.
1 Reset caused by a loss of external clock.
1
LVD
Low Voltage Detect — If the LVD is enabled with LVDRE set, and the supply drops below the LVD trip voltage,
an LVD reset occurs. This bit is also set by POR.
0 Reset not caused by LVD trip or POR.
1 Reset caused by LVD trip or POR.
5.7.3
System Options 1 (SOPT1) Register
This high-page register has four write-once bits and one write anytime bit. For the write-once bits, only
the first write after reset is honored. All bits in the register can be read at any time. Any subsequent attempt
to write a write-once bit is ignored to avoid accidental changes to these sensitive settings. SOPT1 should
be written to during the reset initialization program to set the desired controls, even if the desired settings
are the same as the reset settings.
7
R
6
COPT1
5
4
3
STOPE1
WAITE
2
1
0
MBSL
BKGDPE1
RSTPE1
BLMSS
W
POR:
1
1
0
1
0
0
1
1
LVD:
1
1
0
1
0
0
1
1
Any other
reset:
1
1
0
1
0
0
1
u
1
These bits can be written only one time after reset. Subsequent writes are ignored.
Figure 5-3. System Options 1 (SOPT1) Register
Table 5-5. SOPT1 Field Descriptions
Field
Description
7–6
COPT
COP Watchdog Timeout — These write-once bits select the timeout period of the COP. COPT along with
SOPT2[COPCLKS] defines the COP timeout period as described in Table 5-7.
5
STOPE
Stop Mode Enable — This write-once bit is used to enable stop mode. If stop and wait modes are disabled and
a user program attempts to execute a STOP instruction, an illegal opcode reset may be generated depending on
CPUCR[IRD].
4
WAITE
WAIT Mode Enable — This write-anytime bit is used to enable WAIT mode. If stop and wait modes are disabled
and a user program attempts to execute a STOP instruction, an illegal opcode reset may be generated depending
on CPUCR[IRD].
3
BLMSS
Boot Loader Mode Select Status— This Read only bit shows the status of the BLMS bit during the last Power
on Reset.
0 BLMS pin was high at last POR
1 BLMS pin was low at last POR.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
5-13
Resets, Interrupts, and General System Control
Table 5-5. SOPT1 Field Descriptions (Continued)
Field
Description
2
MBSL
Mini-FlexBus Security Level — If security is enabled via the mechanisms outlined in Section 18.1.5,
“Mini-FlexBus Security Level,” then this bit affects what CPU operations can access off-chip via the Mini-FlexBus
interface. This bit has no effect if security is not enabled.
0 All off-chip access (opcode and data) via the Mini-FlexBus is disallowed.
1 Off-chip opcode accessed are disallowed. Data accesses are allowed.
1
BKGDPE
Background Debug Mode Pin Enable — This write-once bit when set enables the PTD0/BKGD/MS pin to
function as BKGD/MS. When clear, the pin functions as one of its output only alternative functions. This pin
defaults to the BKGD/MS function following any MCU reset.
0 PTD0/BKGD/MS pin functions as PTD0.
1 PTD0/BKGD/MS pin functions as BKGD/MS.
RESET Pin Enable — When set, this write-once bit enables the PTD1/CMPP2/RESET pin to function as RESET.
When clear, the pin functions as an open-drain output only. This pin defaults to its RESET function following an
MCU POR or LVD. When RSTPE is set, an internal pullup device is enabled on RESET.
0 PTD1/CMPP2/RESET pin functions as PTD1.
1 PTD1/CMPP2/RESET pin functions as RESET.
0
RSTPE
5.7.4
System Options 2 (SOPT2) Register
This high page register contains bits to configure microcontroller specific features on the MCF51MM256
series microcontrollers.
R
7
6
5
4
3
2
1
COPCLKS1
COPW1
USB_
BIGEND
CMT_CLK_
SEL
0
0
CLKOUT_EN
0
0
1
0
0
0
W
Reset:
1
0
ACIC
0
0
This bit can be written to only one time after reset. Additional writes are ignored.
Figure 5-4. System Options 2 (SOPT2) Register
Table 5-6. SOPT2 Register Field Descriptions
Field
7
COPCLKS
6
COPW
5
USB_BIGEND
Description
COP Watchdog Clock Select — This write-once bit selects the clock source of the COP watchdog.
0 Internal 1 kHz LPOCLK is source to COP.
1 Bus clock is source to COP.
COP Window Mode — This write-once bit specifies whether the COP operates in Normal or Window mode.
In Window mode, the 0x55–0xAA write sequence to the SRS register must occur within the last 25% of the
selected period; any write to the SRS register during the first 75% of the selected period resets the
microcontroller.
0 Normal mode
1 Window mode
USB Big Endian — This bit is used to control the endianess (byte order) in USB:
0 Little Endian
1 Big Endian
MCF51MM256 Series Devices Reference Manual, Rev. 3
5-14
Freescale Semiconductor
Resets, Interrupts, and General System Control
Table 5-6. SOPT2 Register Field Descriptions (Continued)
Field
Description
4
CLKOUT_EN
Clock Output Enable — This bit is used to mux out the BUSCLK clock to PTC7.
0 BUSCLK is not available on the external pin PTC7.
1 BUSCLK is available on the external pin PTC7.
3
CMT Clock Select — This bit selects between BUSCLK and BUSCLK/3 to the CMT module.
CMT_CLK_SEL 0 Clock source to CMT is BUSCLK.
1 Clock source to CMT is BUSCLK/3.
0
ACIC
Analog Comparator to Input Capture Enable— This bit connects the output of the ACMP to TPM1 input
channel 0. See Chapter 11, “Programmable Analog Comparator (S08PRACMPV1),” and Chapter 25,
“Timer/Pulse-Width Modulator (S08TPMV3),” for more details on this feature.
0 ACMP output not connected to TPM1 input channel 0.
1 ACMP output connected to TPM1 input channel 0.
Table 5-7. COP Configuration Options
Control Bits
Clock Source
COP Window1 Opens
(SOPT2[COPW] = 1)
COP Overflow Count
SOPT2[COPCLKS]
SOPT1[COPT]
N/A
00
N/A
N/A
COP is disabled
0
01
1 kHz LPOCLK
N/A
25 cycles (32 ms2)
0
10
1 kHz LPOCLK
N/A
28 cycles (256 ms2)
0
11
1 kHz LPOCLK
N/A
210 cycles (1,024 ms2)
1
01
BUSCLK
6,144 cycles
213 cycles1
1
10
BUSCLK
49,152 cycles
216 cycles1
1
11
BUSCLK
196,608 cycles
218 cycles1
1
Windowed COP operation requires the user to clear the COP timer in the last 25% of the selected timeout period. This column
displays the minimum number of clock counts required before the COP timer can be reset when in windowed COP mode
(SOPT2[COPW] = 1).
2 Values shown in milliseconds based on t
LPO = 1 ms.
5.7.5
SIM Clock Set and Select Register (SIMCO)
This register controls operation of the CLKOUT pin. The CS field in this register controls the output mux
function for the CLKOUT pin. The various clock sources must be enabled/disabled via the appropriate
controls elsewhere in the device.
7
6
5
4
3
R
0
0
0
0
0
W
—1
Reset:
1
0
2
1
0
CS
0
0
0
0
0
0
0
Bit 7 of SIMCO register is reserved for internal Freescale testing. Writing a “1” to this bit impacts TPM1 external clock selection.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
5-15
Resets, Interrupts, and General System Control
Table 5-8. SIMCO Bit Field Descriptions
Field
Description
7–3
Reserved
2–0
CS
CLKOUT Select
000 CLKOUT = 0
001 CLKOUT = Crystal oscillator 1
010 CLKOUT = Crystal oscillator 2
011 CLKOUT = internal RC oscillator
100 CLKOUT = BUSCLK
101 CLKOUT = CPUCLK
110 CLKOUT = LPOCLK
111 CLKOUT = ADC asynchronous clock
5.7.6
System Device Identification Register (SDIDH, SDIDL)
These high page read-only registers are included so host development systems can identify the ColdFire
derivative. This allows the development software to recognize where specific memory blocks, registers,
and control bits are located in a target microcontroller.
Additional configuration information about the ColdFire core and memory system is loaded into the 32-bit
D0 (core) and D1 (memory) registers at reset. This information can be stored into memory by the system
startup code for later use by configuration-sensitive application code.
7
6
R
5
4
REV
3
2
1
0
ID11
ID10
ID9
ID8
1
1
0
0
W
Reset:
—
—
—
—
Figure 5-5. System Device Identification Register — High (SDIDH)
Table 5-9. SDIDH Register Field Descriptions
Field
7–4
REV
3–0
ID[11:8]
R
Description
Revision Number. This field indicates the chip revision number.
Part Identification Number — Each derivative in the ColdFire family has a unique identification number. The
MCF51MM256 series microcontrollers are hard coded to the value 0xC04. See also ID bits in Table 5-10.
7
6
5
4
3
2
1
0
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
0
0
0
0
0
1
0
0
W
Reset:
Figure 5-6. System Device Identification Register — Low (SDIDL)
MCF51MM256 Series Devices Reference Manual, Rev. 3
5-16
Freescale Semiconductor
Resets, Interrupts, and General System Control
Table 5-10. SDIDL Register Field Descriptions
Field
7–0
ID[7–0]
5.7.7
Description
Part Identification Number — Each derivative in the ColdFire family has a unique identification number. The
MCF51MM256 series microcontrollers are hard coded to the value 0xC04. See also ID bits in Table 5-9.
System Clock Gating Control 1 Register (SCGC1)
This high page register contains control bits to enable or disable the bus clock to the CMT, TPMx, ADC,
DAC, IIC, and SCIx modules. Gating off the clocks to unused peripherals is used to reduce the
microcontroller’s run and wait currents. See Section 5.6, “Peripheral Clock Gating,” for more information.
7
6
5
4
3
2
1
0
CMT
TPM2
TPM1
ADC
DAC
IIC
SCI2
SCI1
1
1
1
1
1
1
1
1
R
W
Reset:
Figure 5-7. System Clock Gating Control 1 Register (SCGC1)
Table 5-11. SCGC1 Register Field Descriptions
Field
Description
7
CMT
CMT Clock Gate Control — This bit controls the clock gate to the CMT module.
0 Bus clock to the CMT module is disabled.
1 Bus clock to the CMT module is enabled.
6
TPM2
TPM2 Clock Gate Control — This bit controls the clock gate to the TPM2 module.
0 Bus clock to the TPM2 module is disabled.
1 Bus clock to the TPM2 module is enabled.
5
TPM1
TPM1 Clock Gate Control — This bit controls the clock gate to the TPM1 module.
0 Bus clock to the TPM1 module is disabled.
1 Bus clock to the TPM1 module is enabled.
4
ADC
ADC Clock Gate Control — This bit controls the clock gate to the ADC module.
0 Bus clock to the ADC module is disabled.
1 Bus clock to the ADC module is enabled.
3
DAC
DAC Clock Gate Control — This bit controls the clock gate to the DAC module.
0 Bus clock to the DAC module is disabled.
1 Bus clock to the DAC module is enabled.
2
IIC
IIC Clock Gate Control — This bit controls the clock gate to the IIC1 module.
0 Bus clock to the IIC module is disabled.
1 Bus clock to the IIC module is enabled.
1
SCI2
SCI2 Clock Gate Control — This bit controls the clock gate to the SCI2 module.
0 Bus clock to the SCI2 module is disabled.
1 Bus clock to the SCI2 module is enabled.
0
SCI1
SCI1 Clock Gate Control — This bit controls the clock gate to the SCI1 module.
0 Bus clock to the SCI1 module is disabled.
1 Bus clock to the SCI1 module is enabled.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
5-17
Resets, Interrupts, and General System Control
5.7.8
System Clock Gating Control 2 Register (SCGC2)
This high page register contains control bits to enable or disable the bus clock to the USB, PDB, IRQ, KBI,
ACMP, Mini-FlexBus, and SPIx modules. Gating off the clocks to unused peripherals is used to reduce the
microcontroller’s run and wait currents. See Section 5.6, “Peripheral Clock Gating,” for more information.
7
6
5
4
3
2
1
0
USB
PDB
IRQ
KBI
PRACMP
MFB
SPI2
SPI1
1
1
1
1
1
1
1
1
R
W
POR:
Figure 5-8. System Clock Gating Control 2 Register (SCGC2)
Table 5-12. SCGC2 Register Field Descriptions
Field
Description
7
USB
USB Clock Gate Control — This bit controls the bus clock gate to the USB module.
0 Bus clock to the USB module is disabled.
1 Bus clock to the USB module is enabled.
6
PDB
PDB Clock Gate Control — This bit controls the bus clock gate to the PDB registers.
0 Bus clock to PDB registers is disabled.
1 Bus clock to PDB registers is enabled.
5
IRQ
IRQ Clock Gate Control — This bit controls the bus clock gate to the IRQ module.
0 Bus clock to the IRQ module is disabled.
1 Bus clock to the IRQ module is enabled.
4
KBI
KBI Clock Gate Control — This bit controls the clock gate to both of the KBI modules.
0 Bus clock to the KBI modules is disabled.
1 Bus clock to the KBI modules is enabled.
3
PRACMP
PRACMP Clock Gate Control — This bit controls the clock gate to the PRACMP modules.
0 Bus clock to the PRACMP module is disabled.
1 Bus clock to the PRACMP module is enabled.
2
MFB
MFB Clock Gate Control — This bit controls the bus clock gate to the MFB module. Only the bus clock is gated;
the clock source of MFB is not controlled by this bit.
0 Bus clock to the MFB module is disabled.
1 Bus clock to the MFB module is enabled.
1
SPI2
SPI2 Clock Gate Control — This bit controls the clock gate to the SPI2 module.
0 Bus clock to the SPI2 module is disabled.
1 Bus clock to the SPI2 module is enabled.
0
SPI1
SPI1 Clock Gate Control — This bit controls the clock gate to the SPI1 module.
0 Bus clock to the SPI1 module is disabled.
1 Bus clock to the SPI1 module is enabled.
5.7.9
System Clock Gating Control 3 Register (SCGC3)
This high page register contains control bits to enable or disable the bus clock to the following modules:
• VREF
• FLSx
MCF51MM256 Series Devices Reference Manual, Rev. 3
5-18
Freescale Semiconductor
Resets, Interrupts, and General System Control
•
•
TRIAMPx
GPOAx
Gating off the clocks to unused peripherals is used to reduce the microcontroller’s run and wait currents.
See Section 5.6, “Peripheral Clock Gating,” for more information.
7
6
5
4
3
2
1
0
VREF
CRC
FLS2
FLS1
TRIAMP2
TRIAMP1
GPOA2
GPOA1
1
1
1
1
1
1
1
1
R
W
Reset:
Figure 5-9. System Clock Gating Control 3 Register (SCGC3)
Table 5-13. SCGC3 Register Field Descriptions
Field
Description
7
VREF
VREF Clock Gate Control — This bit controls the clock gate to the VREF module.
0 Bus clock to the VREF module is disabled.
1 Bus clock to the VREF module is enabled.
6
CRC
CRC Clock Gate Control — This bit controls the clock gate to the CRC module.
0 Bus clock to the CRC module is disabled.
1 Bus clock to the CRC module is enabled.
5
FLS2
FLS2 Clock Gate Control — This bit controls the clock gate to the FLS2 module.
0 Bus clock to the FLS2 module is disabled.
1 Bus clock to the FLS2 module is enabled.
4
FLS1
FLS1 Clock Gate Control — This bit controls the clock gate to the FLS1 module.
0 Bus clock to the FLS1 module is disabled.
1 Bus clock to the FLS1 module is enabled.
3
TRIAMP2
TRIAMP2 Clock Gate Control — This bit controls the clock gate to the TRIAMP2 module.
0 Bus clock to the TRIAMP2 module is disabled.
1 Bus clock to the TRIAMP2 module is enabled.
2
TRIAMP1
TRIAMP1 Clock Gate Control — This bit controls the clock gate to the TRIAMP1 module.
0 Bus clock to the TRIAMP1 module is disabled.
1 Bus clock to the TRIAMP1 module is enabled.
1
GPOA2
GPOA2 Clock Gate Control — This bit controls the clock gate to the GPOA2 module.
0 Bus clock to the GPOA2 module is disabled.
1 Bus clock to the GPOA2 module is enabled.
0
GPOA1
GPOA1 Clock Gate Control — This bit controls the clock gate to the GPOA1 module.
0 Bus clock to the GPOA1 module is disabled.
1 Bus clock to the GPOA1 module is enabled.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
5-19
Resets, Interrupts, and General System Control
5.7.10
System Options 3 Register (SOPT3)
This register contains a bit that controls the pad drive strength for the CMT module.
7
6
5
4
3
2
1
0
SCI2PS
SCI1PS
IICPS
USB_PS
MB_DATA
ARRAYSEL
SCI1_PAD
CMT_PAD
Reset:
0
0
0
0
0
u1
0
0
POR:
0
0
0
0
0
0
0
0
R
W
Figure 5-10. System Options 3 Register (SOPT3)
1
This bit is reinitialized by POR, all other resets do not affect this bit.
Table 5-14. SOPT3 Field Descriptions
Field
Description
7
SCI2PS
Configures TX2 and RX2 signal locations.
0 PTE5, PTE6
1 PTF1, PTF2
6
SCI1PS
Configures TX1 and RX1 signal locations.
0 PTA1, PTA2
1 PTD6, PTD7
5
IICPS
Configures SDA and SCL signal locations.
0 PTD4, PTD5
1 PTF4, PTF3
4
USB_PS
Configures USB signals as described below:
0
USB_SESSVLD pin PTG4
USB_SESSEND pin PTG1
USB_PULLUP(D+) pin PTD3
USB_DP_DOWN pin PTG3
USB_DM_DOWN pin PTG2
USB_ALTCLK pin PTD2
1
USB_SESSVLD pin PTE7
USB_SESSEND pin PTE6
USB_PULLUP(D+) pin PTD7
USB_DP_DOWN pin PTF1
USB_DM_DOWN pin PTF2
USB_ALTCLK pin PTD6
MCF51MM256 Series Devices Reference Manual, Rev. 3
5-20
Freescale Semiconductor
Resets, Interrupts, and General System Control
Table 5-14. SOPT3 Field Descriptions (Continued)
Field
Description
3
MB_DATA
Mini-FlexBus data bus configuration bit — This bit determines which MFB signals are routed to which pins as
described below:
MB_DATA = 0
FB_D0 pin PTH1
FB_D2 pin PTH7
FB_D3 pin PTH6
FB_D4 pin PTH5
FB_D5 pin PTH4
FB_D6 pin PTH3
FB_D7 pin PTH2
FB_RW pin PTG5
FB_OE pin PTH0
MB_DATA = 1
FB_D0 pin PTC1
FFB_D2 pin PTA0
FB_D3 pin PTF5
FB_D4 pin PTF4
FB_D5 pin PTF3
FB_D6 pin PTA3
FB_D7 pin PTE5
FB_RW pin PTE6
FB_OE pin PTC0
2
Array select — This bit determines the mapping of the 2 flash arrays as described in Table 4-10.
ARRAYSEL
1
SCI1_PAD
SCI_PAD pad drive strength — This bit controls the SCI1 TX(PTD6) pad drive strength by connecting two pads
together.
0 single-pad drive strength
1 dual-pads bounding drive strength
0
CMT_PAD
CMT pad drive strength — This bit controls the CMT pad drive strength by connecting two pads together.
0 single-pad drive strength
1 dual-pads bounding drive strength
5.7.11
System Options 4 Register (SOPT4)
This register contains bits that control the drive strength and slew rate of various ports.
7
R
6
5
4
3
2
1
0
IROSRE
IRODSE
0
0
0
FBALEEN
FBAD12IFE FBAD12PUE FBAD12SRE FBAD12DSE
W
Reset:
0
0
0
0
0
0
Figure 5-11. System Options 4 Register (SOPT4)
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
5-21
Resets, Interrupts, and General System Control
Table 5-15. SOPT4 Field Descriptions
Field
7
Description
Reserved, should be cleared.
6
FBALEEN
Mini-FlexBus address latch enable
1 The ALE function is provided on the PTE0 pin if the EN_CS1 is set and the Mini-Flexbus is enabled.
0 Address latch disable.
5
FBAD12FE
Input filter enable for the pin where the FB_AD12 signal is located
1 Input filter enable.
0 Input filter disable.
4
Pull-up enable for the pin where the FB_AD12 signal is located
FBAD12PUE 1 Pull-up enable.
0 Pull-up disable.
3
Output slew rate control enable for the pin where the FB_AD12 signal is located
FBAD12SRE 1 Output slew rate control enable.
0 Output slew rate control disable.
2
Drive strength control enable for the pin where the FB_AD12 signal is located
FBAD12DSE 1 Drive strength control enable.
0 Drive strength control disable.
1
IROSRE
Output slew rate control enable for IRO pin
1 Output slew rate control enable.
0 Output slew rate control disable.
0
IRODSE
Drive strength control enable for IRO pin
1 Drive strength control enable.
0 Drive strength control disable.
5.7.12
System Options 5 Register (SOPT5)
CAUTION
This location is reserved for Freescale internal testing. Do not write any
value to this location. Writing a value to this location can affect on-chip
LVD performance.
5.7.13
SIM Internal Peripheral Select Register (SIMIPS)
The fields in this register control source used for the SCI1 RX pin, as well as modulation choice for the
SCI1 TX pin. The various clock sources used for modulation purposes must be enabled/disabled via the
appropriate controls elsewhere in the device. See Figure 2-6 for an illustration of these controls in action.
MCF51MM256 Series Devices Reference Manual, Rev. 3
5-22
Freescale Semiconductor
Resets, Interrupts, and General System Control
7
6
ADCTRS
RX1IN
0
0
R
5
4
0
0
3
2
1
0
0
MTBASE1
MODTX1
W
Reset:
0
0
0
0
0
0
Figure 5-12. SIM Internal Peripheral Select Register (SIMIPS)
Table 5-16. SIMIPS Register Bit Fields
Field
Description
7
ADCTRS
ADC Hardware Trigger Select
0 PDB is the source of ADHWT. This is the default case for user applications.
1 TOD interrupt is the source of ADHWT. The typical application is to use the ADC for the VDD measurements.
6
RX1IN
SCI1 RX Input Pin Select
0 RX1 is fed from the digital input pin (assuming RX1 is enabled on that pin)
1 RX1 is fed from the output of comparator 1
3-2
MTBASE1
SCI1 TX Modulation Time Base Select
00 TPM1CH0
01 TPM1CH1
10 TPM2CH0
11 TPM2CH1
0
MODTX1
Modulate TX1
0 Do not modulate the output of SCI1
1 Modulate the output of SCI1 with the timebase selected via the MTBASE1 field
5.7.14
Signature Register (Signature)
7
6
5
4
3
2
1
0
0
0
0
R
Signature Semaphore
W
POR:
0
0
0
0
0
Figure 5-13. Signature Register (Signature)
Table 5-17. Signature Register Field Descriptions
Field
Description
7:0
Signature
The SIGNATURE semaphore is used as the semaphore to jump to bootloader mode or not after regular reset.
This byte only can be cleared by power-on reset (POR), content retains after regular reset.
5.7.15
System Power Management Status and Control 1
Register (SPMSC1)
This high page register contains status and control bits to support the low voltage detect function, and to
enable the bandgap voltage reference for use by the ADC module. This register should be written during
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
5-23
Resets, Interrupts, and General System Control
the user’s reset initialization program to set the desired controls even if the desired settings are the same
as the reset settings.
R
7
6
LVDF1
0
W
Reset:
1
2
5
4
3
2
LVDIE
LVDRE2
LVDSE
LVDE2
0
1
1
1
1
0
0
BGBE
LVDACK
0
0
0
0
LVDF is set in the case when VSupply transitions below the trip point or after reset and VSupply is already below VLVW.
This bit can be written only one time after reset. Additional writes are ignored.
Figure 5-14. System Power Management Status and Control 1 Register (SPMSC1)
Table 5-18. SPMSC1 Register Field Descriptions
Field
7
LVDF
6
LVDACK
Description
Low-Voltage Detect Flag — The LVDF bit indicates the low-voltage detect status.
0 Low-voltage detect is not present.
1 Low-voltage detect is present or was present.
Low-Voltage Detect Acknowledge — If LVDF = 1, a low-voltage condition has occurred. To acknowledge this
low-voltage detect, write 1 to LVDACK, which automatically clears LVDF to 0 if the low-voltage detect is no longer
present.
5
LVDIE
Low-Voltage Detect Interrupt Enable — This bit enables hardware interrupt requests for LVDF.
0 Hardware interrupt disabled (use polling).
1 Request a hardware interrupt when LVDF = 1.
4
LVDRE
Low-Voltage Detect Reset Enable — This write-once bit enables LVDF events to generate a hardware reset
(provided LVDE = 1).
0 LVDF does not generate hardware resets.
1 Force an MCU reset when an enabled low-voltage detect event occurs.
3
LVDSE
Low-Voltage Detect Stop Enable — Provided LVDE = 1, this read/write bit determines whether the low-voltage
detect function operates when the MCU is in stop mode.
0 Low-voltage detect disabled during stop mode.
1 Low-voltage detect enabled during stop mode.
2
LVDE
Low-Voltage Detect Enable — This write-once bit enables low-voltage detect logic and qualifies the operation
of other bits in this register.
0 LVD logic disabled.
1 LVD logic enabled.
0
BGBE
Bandgap Buffer Enable — This bit enables an internal buffer for the bandgap voltage reference for use by the
ADC module on one of its internal channels.
0 Bandgap buffer disabled.
1 Bandgap buffer enabled.
5.7.16
System Power Management Status and Control 2 Register
(SPMSC2)
This high page register contains status and control bits to configure the low power run and wait modes as
well as configure the stop mode behavior of the microcontroller.
SPMSC2 is not reset when exiting from STOP2.
MCF51MM256 Series Devices Reference Manual, Rev. 3
5-24
Freescale Semiconductor
Resets, Interrupts, and General System Control
7
R
6
5
LPRS
LPR
4
3
2
0
PPDF
0
LPWUI
0
PPDE1
PPDC
1
0
PPDACK
W
Reset:
1
0
0
0
0
-
0
Figure 5-15. System Power Management Status and Control 2 Register (SPMSC2)
1
PPDE is a write-once bit that can be used to permanently disable the PPDC bit.
Table 5-19. SPMSC2 Bit Field Descriptions
Field
Description
7
LPR
Low-Power Regulator Control — The LPR bit controls entry into the low-power run and low-power wait modes
in which the voltage regulator is put into standby. This bit cannot be set if PPDC=1. If PPDC and LPR are set in
a single write instruction, only PPDC is actually set. LPR is cleared when an interrupt occurs in low-power mode
and the LPWUI bit is 1.
0 Low-power run and low-power wait modes are disabled.
1 Low-power run and low-power wait modes are requested.
6
LPRS
Low-Power Regulator Status — This read-only status bit indicates that the voltage regulator has entered into
standby for the low-power run or wait mode.
0 The voltage regulator is not currently in standby.
1 The voltage regulator is currently in standby.
5
LPWUI
Low-Power Wake-Up on Interrupt — This bit controls whether or not the voltage regulator exits standby when
any active MCU interrupt occurs.
0 The voltage regulator remains in standby on an interrupt.
1 The voltage regulator exits standby on an interrupt. LPR is cleared.
4
3
PPDF
2
PPDACK
RESERVED
Partial Power-Down Flag — This read-only status bit indicates that the microcontroller has recovered from
Stop2 mode.
0 Microcontroller has not recovered from Stop2 mode.
1 Microcontroller recovered from Stop2 mode.
Partial Power-Down Acknowledge — Writing a 1 to PPDACK clears the PPDF bit.
1
PPDE
Partial Power-Down Enable —The write-once PPDE bit can be used to lockout the partial power-down feature.
This is a write-once bit.
0 Partial power-down is not enabled.
1 Partial power-down is enabled and controlled via the PPDC bit.
0
PPDC
Partial Power-Down Control — The PPDC bit controls which power-down mode is selected. This bit cannot be
set if LPR = 1. If PPDC and LPR are set in a single write instruction, only PPDC will actually be set. PPDE must
be set in order for PPDC to be set.
0 Stop3 low power mode enabled.
1 Stop2 partial power-down mode enabled.
1 See
the MCF51MM256 Data Sheet Electrical Characteristics appendix for minimum and maximum values.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
5-25
Resets, Interrupts, and General System Control
5.7.17
System Power Management Status and Control 3 Register
(SPMSC3)
This register reports the status of the low voltage warning function and is used to select the low voltage
detect trip voltage. SPMSC3 is not reset when exiting from stop2.
R
7
6
LVWF
0
W
1
5
4
3
LVDV
LVWV
LVWIE
2
1
0
0
0
0
LVWACK
POR:
01
0
0
0
0
0
0
0
LVR:
01
0
U
U
0
0
0
0
Other
resets:
01
0
U
U
0
0
0
0
LVWF is set when VSupply transitions below the trip point or after reset and VSupply is already below VLVW.
Figure 5-16. System Power Management Status and Control 3 Register (SPMSC3)
Table 5-20. SPMSC3 Bit Field Descriptions
Field
7
LVWF
6
LVWACK
Description
Low-Voltage Warning Flag — The LVWF bit indicates the low voltage warning status.
0 Low voltage warning not present.
1 Low voltage warning is present or was present.
Low-Voltage Warning Acknowledge — Writing a 1 to LVWACK clears LVWF if a low voltage warning is not
present.
5
LVDV
Low-Voltage Detect Voltage Select — The LVDV bit selects the LVD trip point voltage (VLVD).
0 Low trip point selected (VLVD = VLVDL).
1 High trip point selected (VLVD = VLVDH).
4
LVWV
Low-Voltage Warning Voltage Select — The LVWV bit selects the LVW trip point voltage (VLVW).
0 Low trip point selected (VLVW = VLVWL).
1 High trip point selected (VLVW = VLVWH).
3
LVWIE
Low-Voltage Warning Interrupt Enable — This bit enables hardware interrupt requests for LVWF.
0 Hardware interrupt disabled (use polling).
1 Request a hardware interrupt when LVWF is set.
2–0
Reserved, should be cleared.
Table 5-21. LVD and LVW Trip Point Typical Values1
LVDV:LVWV
LVW Trip Point
LVD Trip Point
00
VLVWL = 2.15
VLVDL = 1.86
01
VLVWH = 2.6
MCF51MM256 Series Devices Reference Manual, Rev. 3
5-26
Freescale Semiconductor
Resets, Interrupts, and General System Control
Table 5-21. LVD and LVW Trip Point Typical Values1 (Continued)
1
5.7.18
LVDV:LVWV
LVW Trip Point
LVD Trip Point
10
Not Recommended
VLVWL = 2.15
VLVDH = 2.33
11
VLVWH = 2.6
Note: Data in this table may not be up-to-date. Please refer to the DC Characteristics table
in the MCF51MM256 series Data Sheet for the latest values.
Flash Protection Disable Register (FPROTD)
The FPROTD register provides a secure way for the USB bootrom code to overwrite the flash block
protection registers. Back to back writes of 0x55 and 0xAA to FROTD, provided the device is in bootmode
sets the FPDIS bit. The FPDIS bit is used as a signal to the flash module to allow writes to each block
protection register.
Any writes other than 0x55 followed by 0xAA clears the FPDIS bit.
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
FPDIS
W
Reset:
1
See Note
0
0
0
0
0
0
0
0
Back to back writes of 0x55 and 0xAA, set FPDIS, any other back to back data clears FPDIS.
Figure 5-17. Flash Protection Disable Register (FPROTD)
Table 5-22. FPROTD Field Descriptions
Field
Description
0
FPDIS
This bit is set when the device is in bootmode and back to back writes of 0x55 and 0xAA occur. It is cleared during
any writes other than 0x55 followed by 0xAA.
0 Writes to the flash block protection registers are not allowed
1 Writes to flash block protection registers are allowed
5.7.19
Mini-FlexBus Pin Control 1 (MFBPC1)
When the Mini-FlexBus is enabled this register is used to enable or disable the Mini-FlexBus functionality
for the associated pin. Each of the 32 Mini-FlexBus signals has a corresponding enable bit as described
below.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
5-27
Resets, Interrupts, and General System Control
7
6
5
4
3
2
1
0
MFBPEN_
AD7
MFBPEN_
AD6
MFBPEN_
AD5
MFBPEN_
AD4
MFBPEN_
AD3
MFBPEN_
AD2
MFBPEN_
AD1
MFBPEN_
AD0
POR:
0
0
0
0
0
0
0
0
LVR:
0
0
0
0
0
0
0
0
Other
resets:
0
0
0
0
0
0
0
0
R
W
Figure 5-18. Mini-FlexBus Pin Control 1 (MFBPC1)
Table 5-23. MFBPC1 Field Descriptions
Field
Description
7
Mini-FlexBus pin control for FB_AD7
MFBPEN_AD7 0 FB_AD7 functionality disabled
1 FB_AD7 functionality enabled if the Mini-FlexBus is enabled.
6
Mini-FlexBus pin control for FB_AD6
MFBPEN_AD6 0 FB_AD6 functionality disabled
1 FB_AD6 functionality enabled if the Mini-FlexBus is enabled.
5
Mini-FlexBus pin control for FB_AD5
MFBPEN_AD5 0 FB_AD5 functionality disabled
1 FB_AD5 functionality enabled if the Mini-FlexBus is enabled.
4
Mini-FlexBus pin control for FB_AD4
MFBPEN_AD4 0 FB_AD4 functionality disabled
1 FB_AD4 functionality enabled if the Mini-FlexBus is enabled.
3
Mini-FlexBus pin control for FB_AD3
MFBPEN_AD3 0 FB_AD3 functionality disabled
1 FB_AD3 functionality enabled if the Mini-FlexBus is enabled.
2
Mini-FlexBus pin control for FB_AD2
MFBPEN_AD2 0 FB_AD2 functionality disabled
1 FB_AD2 functionality enabled if the Mini-FlexBus is enabled.
1
Mini-FlexBus pin control for FB_AD1
MFBPEN_AD1 0 FB_AD1 functionality disabled
1 FB_AD1 functionality enabled if the Mini-FlexBus is enabled.
0
Mini-FlexBus pin control for FB_AD0
MFBPEN_AD0 0 FB_AD0 functionality disabled
1 FB_AD0 functionality enabled if the Mini-FlexBus is enabled.
5.7.20
Mini-FlexBus Pin Control 2 (MFBPC2)
When the Mini-FlexBus is enabled this register is used to enable or disable the Mini-FlexBus functionality
for the associated pin. Each of the 32 Mini-FlexBus signals has a corresponding enable bit as described
below.
MCF51MM256 Series Devices Reference Manual, Rev. 3
5-28
Freescale Semiconductor
Resets, Interrupts, and General System Control
7
R MFBPEN_A
D15
W
6
5
4
3
2
1
0
MFBPEN_A
D14
MFBPEN_A
D13
MFBPEN_A
D12
MFBPEN_A
D11
MFBPEN_A
D10
MFBPEN_A
D9
MFBPEN_A
D8
POR:
0
0
0
0
0
0
0
0
LVR:
0
0
0
0
0
0
0
0
Other
resets:
0
0
0
0
0
0
0
0
Figure 5-19. Mini-FlexBus Pin Control 2 (MFBPC2)
Table 5-24. MFBPC2 Field Descriptions
Field
Description
7
MFBPEN_AD15
Mini-FlexBus pin control for FB_AD15
0 FB_AD15 functionality disabled
1 FB_AD15 functionality enabled if the Mini-FlexBus is enabled.
6
MFBPEN_AD14
Mini-FlexBus pin control for FB_AD14
0 FB_AD14 functionality disabled
1 FB_AD14 functionality enabled if the Mini-FlexBus is enabled.
5
MFBPEN_AD13
Mini-FlexBus pin control for FB_AD13
0 FB_AD13 functionality disabled
1 FB_AD13 functionality enabled if the Mini-FlexBus is enabled.
4
MFBPEN_AD12
Mini-FlexBus pin control for FB_AD12
0 FB_AD12 functionality disabled
1 FB_AD12 functionality enabled if the Mini-FlexBus is enabled.
3
MFBPEN_AD11
Mini-FlexBus pin control for FB_AD11
0 FB_AD11 functionality disabled
1 FB_AD11 functionality enabled if the Mini-FlexBus is enabled.
2
MFBPEN_AD10
Mini-FlexBus pin control for FB_AD10
0 FB_AD10 functionality disabled
1 FB_AD10 functionality enabled if the Mini-FlexBus is enabled.
1
MFBPEN_AD9
Mini-FlexBus pin control for FB_AD9
0 FB_AD9 functionality disabled
1 FB_AD9 functionality enabled if the Mini-FlexBus is enabled.
0
MFBPEN_AD8
Mini-FlexBus pin control for FB_AD8
0 FB_AD8 functionality disabled
1 FB_AD8 functionality enabled if the Mini-FlexBus is enabled.
5.7.21
Mini-FlexBus Pin Control 3 (MFBPC3)
When the Mini-FlexBus is enabled this register is used to enable or disable the Mini-FlexBus functionality
for the associated pin. Each of the 32 Mini-FlexBus signals has a corresponding enable bit as described
below.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
5-29
Resets, Interrupts, and General System Control
7
6
5
4
R
MFBPEN_D3 MFBPEN_D2 MFBPEN_D1 MFBPEN_D0
W
3
2
1
0
MFBPEN_A
D19
MFBPEN_A
D18
MFBPEN_A
D17
MFBPEN_A
D16
POR:
0
0
0
0
0
0
0
0
LVR:
0
0
0
0
0
0
0
0
Any
other
reset:
0
0
0
0
0
0
0
0
Figure 5-20. Mini-FlexBus Pin Control 3 (MFBPC3)
Table 5-25. MFBPC3 Field Descriptions
Field
Description
7
MFBPEN_D3
Mini-FlexBus pin control for FB_D3
0 FB_D3 functionality disabled
1 FB_D3 functionality enabled if the Mini-FlexBus is enabled.
6
MFBPEN_D2
Mini-FlexBus pin control for FB_D2
0 FB_D2 functionality disabled
1 FB_D2 functionality enabled if the Mini-FlexBus is enabled.
5
MFBPEN_D1
Mini-FlexBus pin control for FB_D1
0 FB_D1 functionality disabled
1 FB_D1 functionality enabled if the Mini-FlexBus is enabled.
4
MFBPEN_D0
Mini-FlexBus pin control for FB_D0
0 FB_D0 functionality disabled
1 FB_D0 functionality enabled if the Mini-FlexBus is enabled.
3
MFBPEN_AD19
Mini-FlexBus pin control for FB_AD19
0 FB_AD19 functionality disabled
1 FB_AD19 functionality enabled if the Mini-FlexBus is enabled.
2
MFBPEN_AD18
Mini-FlexBus pin control for FB_AD18
0 FB_AD18 functionality disabled
1 FB_AD18 functionality enabled if the Mini-FlexBus is enabled.
1
MFBPEN_AD17
Mini-FlexBus pin control for FB_AD17
0 FB_AD17 functionality disabled
1 FB_AD 17 functionality enabled if the Mini-FlexBus is enabled.
0
MFBPEN_AD16
Mini-FlexBus pin control for FB_AD16
0 FB_AD16 functionality disabled
1 FB_AD16 functionality enabled if the Mini-FlexBus is enabled.
5.7.22
Mini-FlexBus Pin Control 4 (MFBPC4)
When the Mini-FlexBus is enabled this register is used to enable or disable the Mini-FlexBus functionality
for the associated pin. Each of the 32 Mini-FlexBus signals has a corresponding enable bit as described
below.
MCF51MM256 Series Devices Reference Manual, Rev. 3
5-30
Freescale Semiconductor
Resets, Interrupts, and General System Control
7
6
5
4
3
2
1
0
EN_CS1
EN_CS0
EN_OE
EN_RW
POR:
0
0
0
0
0
0
0
0
LVR:
0
0
0
0
0
0
0
0
Any
other
reset:
0
0
0
0
0
0
0
0
R
MFBPEN_D7 MFBPEN_D6 MFBPEN_D5 MFBPEN_D4
W
Figure 5-21. Mini-FlexBus Pin Control 4 (MFBPC4)
Table 5-26. MFBPC4 Field Descriptions
Field
Description
7
EN_CS1
Mini-FlexBus pin control for FB_CS1/FB_ALE
0 FB_CS1/ALE functionality disabled
1 FB_CS1/ALE functionality enabled if the Mini-FlexBus is enabled.
6
EN_CS0
Mini-FlexBus pin control for FB_CS0
0 FB_CS0 functionality disabled
1 FB_CS0 functionality enabled if the Mini-FlexBus is enabled.
5
EN_OE
Mini-FlexBus pin control for FB_OE
0 FB_OE functionality disabled
1 FB_OE functionality enabled if the Mini-FlexBus is enabled.
4
EN_RW
Mini-FlexBus pin control for FB_RW
0 FB_RW functionality disabled
1 FB_RW functionality enabled if the Mini-FlexBus is enabled.
3
MFBPEN_D7
Mini-FlexBus pin control for FB_D7
0 FB_D7 functionality disabled
1 FB_D7 functionality enabled if the Mini-FlexBus is enabled.
2
MFBPEN_D6
Mini-FlexBus pin control for FB_D6
0 FB_D6 functionality disabled
1 FB_D6 functionality enabled if the Mini-FlexBus is enabled.
1
MFBPEN_D5
Mini-FlexBus pin control for FB_D5
0 FB_D5 functionality disabled
1 FB_D5 functionality enabled if the Mini-FlexBus is enabled.
0
MFBPEN_D4
Mini-FlexBus pin control for FB_D4
0 FB_D4 functionality disabled
1 FB_D4 functionality enabled if the Mini-FlexBus is enabled.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
5-31
Resets, Interrupts, and General System Control
MCF51MM256 Series Devices Reference Manual, Rev. 3
5-32
Freescale Semiconductor
Chapter 6
Parallel Input/Output Control
This section explains software controls related to parallel input/output (I/O) and pin control. The
MCF51MM256 series MCUs have up to nine parallel I/O ports which include a total of 69 I/O pins and
one input-only pin, and 2 output only pins. See Chapter 2, “Pins and Connections,” for more information
about pin assignments and external hardware considerations of these pins.
In addition to standard I/O port functionality, some port pins have set/clear/toggle functions which are
integrated as part of the ColdFire core itself to improve edge resolution on those pins. See Section 6.3,
“ColdFire V1 Rapid GPIO Functionality,” and Chapter 9, “Rapid GPIO (RGPIO),” for additional details.
Many port pins are shared with on-chip peripherals such as time systems, communication systems, or
keyboard interrupts as shown in Figure 1-1. The peripheral modules have priority over the general-purpose
I/O functions so that when a peripheral is enabled, the I/O functions associated with the shared pins may
be disabled.
After reset, the shared peripheral functions are disabled and the pins are configured as inputs
(PTxDDn = 0). The pin control functions for each pin are configured as follows: slew rate control enabled
(PTxSEn = 1), low drive strength selected (PTxDSn = 0), and internal pull-ups disabled (PTxPEn = 0).
NOTE
Not all general-purpose I/O pins are available on all packages. To avoid
extra current drain from floating input pins, the user’s reset initialization
routine in the application program must either enable on-chip pull-up
devices or change the direction of unconnected pins to outputs so the pins
do not float.
6.1
Port Data and Data Direction
Reading and writing of parallel I/Os are performed through the port data registers. The direction, either
input or output, is controlled through the port data direction registers. The parallel I/O port function for an
individual pin is illustrated in the block diagram shown in Figure 6-1.
The data direction control bit (PTxDDn) determines whether the output buffer for the associated pin is
enabled, and also controls the source for port data register reads. The input buffer for the associated pin is
always enabled unless the pin is enabled as an analog function or is an output-only pin.
When a shared digital function is enabled for a pin, the output buffer is controlled by the shared function.
However, the data direction register bit will continue to control the source for reads of the port data register.
When a shared analog function is enabled for a pin, both the input and output buffers are disabled. A value
of 0 is read for any port data bit where the bit is an input (PTxDDn = 0) and the input buffer is disabled. In
general, whenever a pin is shared with both an alternate digital function and an analog function, the analog
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
6-1
Parallel Input/Output Control
function has priority such that if both the digital and analog functions are enabled, the analog function
controls the pin.
It is good programming practice to write to the port data register before changing the direction of a port
pin to become an output. This ensures that the pin will not be driven momentarily with an old data value
that happened to be in the port data register.
PTxDDn
Data Direction Control
D
Output Enable
Q
PTxDn
Port Data Register
D
Q
Output Data
1
Port Read
Data
0
Synchronizer
Input Data
BUSCLK
Figure 6-1. Classic Parallel I/O Block Diagram: Ports A-H, J
6.2
Pull-up, Slew Rate, and Drive Strength
A set of high page registers are used to control pull-ups, slew rate, and drive strength for the pins. They
may also be used in conjunction with the peripheral functions on these pins. These registers are associated
with the parallel I/O ports, but operate independently of the parallel I/O registers.
6.2.1
Port Internal Pull-up Enable
An internal pull-up device can be enabled for each port pin by setting the corresponding bit in the pull-up
enable register (PTxPEn). The pull-up device is disabled if the pin is configured as an output by the parallel
I/O control logic or any shared peripheral function regardless of the state of the corresponding pull-up
enable register bit. The pull-up device is also disabled if the pin is controlled by an analog function.
6.2.2
Port Slew Rate Enable
Slew rate control can be enabled for each port pin by setting the corresponding bit in the slew rate control
register (PTxSEn). When enabled, slew control limits the rate at which an output can transition in order to
reduce EMC emissions. Slew rate control has no effect on pins that are configured as inputs.
MCF51MM256 Series Devices Reference Manual, Rev. 3
6-2
Freescale Semiconductor
Parallel Input/Output Control
6.2.3
Port Drive Strength Select
An output pin can be selected to have high output drive strength by setting the corresponding bit in the
drive strength select register (PTxDSn). When high drive is selected, a pin is capable of sourcing and
sinking greater current. Even though every I/O pin can be selected as high drive, the user must ensure that
the total current source and sink limits for the MCU are not exceeded. Drive strength selection is intended
to affect the DC behavior of I/O pins. However, the AC behavior is also affected. High drive allows a pin
to drive a greater load with the same switching speed as a low drive enabled pin into a smaller load.
Because of this, the EMC emissions may be affected by enabling pins as high drive.
6.2.4
Port Input Filter Enable
The pad cells used on this device incorporate optional low pass filters on the digital input functions. These
may be enabled by setting the appropriate bit in the input filter enable register (PTxIFE[n]) corresponding
to a given pin. When set high, a low pass filter (10MHz to 30MHz bandwidth) is enabled in the logic input
path. When set low, the filter is bypassed.
The filter is enabled during and after reset by setting the associated PTxIFE bit. The filter is disabled
through software control by clearing the associated PTxIFE bit.
6.3
ColdFire V1 Rapid GPIO Functionality
The V1 ColdFire core is capable of performing higher speed I/O via its system bus, which does not have
latency penalties associated with the on-chip peripheral bus bridge. The ColdFire core contains separate
set/clear/data registers which reside at address 0xC0_0000. This functionality can be programmed to take
priority on some ports.
This functionality is further defined in Chapter 9, “Rapid GPIO (RGPIO).”
6.4
Keyboard Interrupts
Some port pins can be configured as keyboard interrupt inputs and as an external means of waking the
MCU from stop or wait low-power modes. The block diagram for each keyboard interrupt logic is shown
Figure 6-2.
BUSCLK
KBACK
1
KBIxP0
0
S
RESET
VDD
KBF
D CLRQ
KBIPE0
SYNCHRONIZER
CK
KBEDG0
KEYBOARD
INTERRUPT FF
1
KBIxPn
0
S
KBIPEn
STOP
STOP BYPASS
KBI
INTERRUPT
REQUEST
KBIMOD
KBIE
KBEDGn
Figure 6-2. Port Interrupt Block Diagram
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
6-3
Parallel Input/Output Control
Writing to the KBIPEn bits in the keyboard x interrupt pin enable register (KBIxPE) independently enables
or disables each port pin. Each port can be configured as edge sensitive or edge and level sensitive based
on the KBIMOD bit in the keyboard interrupt status and control register (KBIxSC). Edge sensitivity can
be software programmed to be either falling or rising; the level can be either low or high. The polarity of
the edge or edge and level sensitivity is selected using the KBEDGn bits in the keyboard interrupt edge
select register (KBIxES).
Synchronous logic is used to detect edges. Prior to detecting an edge, enabled port inputs must be at the
deasserted logic level. A falling edge is detected when an enabled port input signal is seen as a logic 1 (the
deasserted level) during one bus cycle and then a logic 0 (the asserted level) during the next cycle. A rising
edge is detected when the input signal is seen as a logic 0 during one bus cycle and then a logic 1 during
the next cycle.
6.4.1
Edge Only Sensitivity
A valid edge on an enabled port pin will set KBF in KBIxSC. If the KBIxSC[KBIE] bit is set, an interrupt
request will be presented to the CPU. Clearing of KBF is accomplished by writing a 1 to
KBIxSC[KBACK].
6.4.2
Edge and Level Sensitivity
A valid edge or level on an enabled port pin will set the KBIxSC[KBF] bit. If KBIxSC[KBIE] is set, an
interrupt request will be presented to the CPU. Clearing of KBF is accomplished by writing a 1 to
KBIxSC[KBACK], provided all enabled port inputs are at their deasserted levels. KBF will remain set if
any enabled port pin is asserted while attempting to clear by writing a 1 to KBACK.
6.4.3
Pull-up/Pull-down Resistors
The keyboard interrupt pins can be configured to use an internal pull-up/pull-down resistor using the
associated I/O port pull-up enable register. If an internal resistor is enabled, the KBIxES register is used to
select whether the resistor is a pull-up (KBEDGn = 0) or a pull-down (KBEDGn = 1).
6.4.4
Keyboard Interrupt Initialization
When an interrupt pin is first enabled, it is possible to get a false interrupt flag. To prevent a false interrupt
request during pin interrupt initialization, the user should do the following:
1. Mask interrupts by clearing KBIxSC[KBIE].
2. Select the pin polarity by setting the appropriate KBIxES[KBEDGn] bits.
3. If using internal pull-up/pull-down device, configure the associated pull enable bits in KBIxPE.
4. Enable the interrupt pins by setting the appropriate KBIxPE[KBIPEn] bits.
5. Write to KBIxSC[KBACK] to clear any false interrupts.
6. Set KBIxSC[KBIE] to enable interrupts.
MCF51MM256 Series Devices Reference Manual, Rev. 3
6-4
Freescale Semiconductor
Parallel Input/Output Control
6.5
Pin Behavior in Stop Modes
Pin behavior following execution of a STOP instruction depends on the stop mode that is entered. An
explanation of pin behavior for the various stop modes follows:
• Stop2 mode is a partial power-down mode, whereby I/O latches are maintained in their state as
before the STOP instruction was executed (port states are lost and will need to be restored upon
exiting stop2). CPU register status and the state of I/O registers should be saved in RAM before
the STOP instruction is executed to place the MCU in Stop2 mode.
Upon recovery from Stop2 mode, before accessing any I/O, the user should examine the state of
the SPMSC2[PPDF] bit. If the PPDF bit is cleared, I/O must be initialized as if a power-on-reset
had occurred. If the PPDF bit is set, I/O register states should be restored from the values saved in
RAM before the STOP instruction was executed and peripherals may require initialization or
restoration to their pre-stop condition. The user must then write a 1 to the SPMSC2[PPDACK] bit.
Access to I/O is now permitted again in the user application program.
• In Stop3 and Stop4 modes, all I/O is maintained because internal logic circuity stays powered.
Upon recovery, normal I/O function is available to the user.
6.6
Parallel I/O, Keyboard Interrupt, and Pin Control Registers
This section provides information about the registers associated with the parallel I/O ports. The data and
data direction registers and the keyboard interrupt registers are located in page zero of the memory map.
The pull-up, slew rate, drive strength, and interrupt control registers are located in the high page section
of the memory map.
Refer to tables in Chapter 4, “Memory,” for the absolute address assignments for all parallel I/O and their
pin control registers. This section refers to registers and control bits only by their names. A Freescale
Semiconductor-provided equate or header file normally is used to translate these names into the
appropriate absolute addresses.
6.6.1
Port A Registers
Port A is an 8bit Input Output Port.
On reset the pins will default to the input state and under the I/O control.
Port A is controlled by the registers listed below.
6.6.1.1
Port A Data Register (PTAD)
7
6
5
4
3
2
1
0
PTAD7
PTAD6
PTAD5
PTAD4
PTAD3
PTAD2
PTAD1
PTAD0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-3. Port A Data Register (PTAD)
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
6-5
Parallel Input/Output Control
Table 6-1. PTAD Register Field Descriptions
Field
Description
7–0
PTADn
Port A Data Register Bits — For port A pins that are inputs, reads return the logic level on the pin. For port A
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pull-ups/pull-downs disabled.
6.6.1.2
Port A Data Direction Register (PTADD)
7
6
5
4
3
2
1
0
PTADD7
PTADD6
PTADD5
PTADD4
PTADD3
PTADD2
PTADD1
PTADD0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-4. Port A Data Direction Register (PTADD)
Table 6-2. PTADD Register Field Descriptions
Field
Description
7–0
PTADDn
Data Direction for Port A Bits — These read/write bits control the direction of port A pins and what is read for
PTAD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn.
6.6.1.3
Port A Pull Enable Register (PTAPE)
7
6
5
4
3
2
1
0
PTAPE7
PTAPE6
PTAPE5
PTAPE4
PTAPE3
PTAPE2
PTAPE1
PTAPE0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-5. Internal Pull Enable for Port A Register (PTAPE)
Table 6-3. PTAPE Register Field Descriptions
Field
Description
7–0
PTAPEn
Internal Pull Enable for Port A Bits — Each of these control bits determines if the internal pull-up device is
enabled for the associated PTA pin. For port A pins that are configured as outputs, these bits have no effect and
the internal pull devices are disabled.
0 Internal pull-up device disabled for port A bit n.
1 Internal pull-up device enabled for port A bit n.
MCF51MM256 Series Devices Reference Manual, Rev. 3
6-6
Freescale Semiconductor
Parallel Input/Output Control
6.6.1.4
Port A Slew Rate Enable Register (PTASE)
7
6
5
4
3
2
1
0
PTASE7
PTASE6
PTASE51
PTASE4
PTASE3
PTASE2
PTASE1
PTASE0
0
0
0
0
0
0
0
0
R
W
Reset:
1
PTASE5 has no effect on the open drain PTA5 pin.
Figure 6-6. Slew Rate Enable for Port A Register (PTASE)
Table 6-4. PTASE Register Field Descriptions
Field
Description
7–0
PTASEn
Output Slew Rate Enable for Port A Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port A bit n.
1 Output slew rate control enabled for port A bit n.
6.6.1.5
Port A Drive Strength Selection Register (PTADS)
7
6
5
4
3
2
1
0
PTADS7
PTADS6
PTADS51
PTADS4
PTADS3
PTADS2
PTADS1
PTADS0
0
0
0
0
0
0
0
0
R
W
Reset:
1
PTADS5 has no effect on the open drain PTA5 pin.
Figure 6-7. Drive Strength Selection for Port A Register (PTADS)
Table 6-5. PTADS Register Field Descriptions
Field
Description
7–0
PTADSn
Output Drive Strength Selection for Port A Bits — Each of these control bits selects between low and high
output drive for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port A bit n.
1 High output drive strength selected for port A bit n.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
6-7
Parallel Input/Output Control
6.6.1.6
Port A Input Filter Enable Register (PTAIFE)
The Port A pin incorporates an optional input low-pass filter. Set the associated PTAIFE bit during and
after reset to enable the filter. To disable the filter, clear the associated PTAIFE bit through software
control.
7
6
5
4
3
2
1
0
PTAIFE7
PTAIFE6
PTAIFE5
PTAIFE4
PTAIFE3
PTAIFE2
PTAIFE1
PTAIFE0
1
1
1
1
1
1
1
1
R
W
Reset:
Figure 6-8. Input Filter Enable for Port A Register (PTAIFE)
Table 6-6. PTAIFE Register Field Descriptions
Field
7–0
PTAIFEn
6.6.2
Description
Input Filter Enable for Port A Bits — Input low-pass filter enable control bits for PTA pins.
0 Input filter disabled.
1 Input filter enabled.
Port B Registers
Port B is controlled by the registers listed below.
6.6.2.1
Port B Data Register (PTBD)
7
6
5
4
3
2
1
0
PTBD7
PTBD6
PTBD5
PTBD4
PTBD3
PTBD2
PTBD11
PTBD0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-9. Port B Data Register (PTBD)
1
Reading PTBD1 always returns the contents of PTBD1 regardless of the setting of the PTBDD1 bit.
Table 6-7. PTBD Register Field Descriptions
Field
Description
7–0
PTBDn
Port B Data Register Bits — For port B pins that are inputs, reads return the logic level on the pin. For port B
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port B pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTBD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pull-ups/pull-downs disabled.
MCF51MM256 Series Devices Reference Manual, Rev. 3
6-8
Freescale Semiconductor
Parallel Input/Output Control
6.6.2.2
Port B Data Direction Register (PTBDD)
7
6
5
4
3
2
1
0
PTBDD7
PTBDD6
PTBDD5
PTBDD4
PTBDD3
PTBDD2
PTBDD11
PTBDD0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-10. Port B Data Direction Register (PTBDD)
1
PTBDD1 has no effect on the output only PTB1 pin.
Table 6-8. PTBDD Register Field Descriptions
Field
Description
7–0
PTBDDn
Data Direction for Port B Bits — These read/write bits control the direction of port B pins and what is read for
PTBD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn.
6.6.2.3
Port B Pull Enable Register (PTBPE)
7
6
5
4
3
2
1
0
PTBPE7
PTBPE6
PTBPE5
PTBPE4
PTBPE3
PTBPE2
PTBPE11
PTBPE0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-11. Internal Pull Enable for Port B Register (PTBPE)
1
PTBPE1 has no effect on the output only PTB1 pin.
Table 6-9. PTBPE Register Field Descriptions
Field
Description
7–0
PTBPEn
Internal Pull Enable for Port B Bits — Each of these control bits determines if the internal pull-up device is
enabled for the associated PTB pin. For port B pins that are configured as outputs, these bits have no effect and
the internal pull devices are disabled.
0 Internal pull-up device disabled for port B bit n.
1 Internal pull-up device enabled for port B bit n.
6.6.2.4
Port B Slew Rate Enable Register (PTBSE)
7
6
5
4
3
2
1
0
PTBSE7
PTBSE6
PTBSE5
PTBSE4
PTBSE3
PTBSE2
PTBSE1
PTBSE0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-12. Slew Rate Enable for Port B Register (PTBSE)
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
6-9
Parallel Input/Output Control
Table 6-10. PTBSE Register Field Descriptions
Field
Description
7–0
PTBSEn
Output Slew Rate Enable for Port B Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTB pin. For port B pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port B bit n.
1 Output slew rate control enabled for port B bit n.
6.6.2.5
Port B Drive Strength Selection Register (PTBDS)
7
6
5
4
3
2
1
0
PTBDS7
PTBDS6
PTBDS5
PTBDS4
PTBDS3
PTBDS2
PTBDS1
PTBDS0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-13. Drive Strength Selection for Port B Register (PTBDS)
Table 6-11. PTBDS Register Field Descriptions
Field
Description
7–0
PTBDSn
Output Drive Strength Selection for Port B Bits — Each of these control bits selects between low and high
output drive for the associated PTB pin. For port B pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port B bit n.
1 High output drive strength selected for port B bit n.
6.6.2.6
Port B Input Filter Enable Register (PTBIFE)
The Port B pin incorporates an optional input low-pass filter. Set the associated PTBIFE bit during and
after reset to enable the filter. To disable the filter, clear the associated PTBIFE bit through software
control.
7
6
5
4
3
2
1
0
PTBIFE7
PTBIFE6
PTBIFE5
PTBIFE4
PTBIFE3
PTBIFE2
PTBIFE1
PTBIFE0
1
1
1
1
1
1
1
1
R
W
Reset:
Figure 6-14. Input Filter Enable for Port B Register (PTBIFE)
Table 6-12. PTBIFE Register Field Descriptions
Field
7–0
PTBIFEn
Description
Input Filter Enable for Port B Bits — Input low-pass filter enable control bits for PTB pins.
0 Input filter disabled.
1 Input filter enabled.
MCF51MM256 Series Devices Reference Manual, Rev. 3
6-10
Freescale Semiconductor
Parallel Input/Output Control
6.6.3
Port C Registers
Port C is controlled by the registers listed below.
6.6.3.1
Port C Data Register (PTCD)
7
6
5
4
3
2
1
0
PTCD7
PTCD6
PTCD5
PTCD4
PTCD3
PTCD2
PTCD1
PTCD0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-15. Port C Data Register (PTCD)
Table 6-13. PTCD Register Field Descriptions
Field
Description
7–0
PTCDn
Port C Data Register Bits — For port C pins that are inputs, reads return the logic level on the pin. For port C
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port C pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTCD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pull-ups disabled.
6.6.3.2
Port C Data Direction Register (PTCDD)
7
6
5
4
3
2
1
0
PTCDD7
PTCDD6
PTCDD5
PTCDD4
PTCDD3
PTCDD2
PTCDD1
PTCDD0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-16. Port C Data Direction Register (PTCDD)
Table 6-14. PTCDD Register Field Descriptions
Field
Description
7–0
PTCDDn
Data Direction for Port C Bits — These read/write bits control the direction of port C pins and what is read for
PTCD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port C bit n and PTCD reads return the contents of PTCDn.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
6-11
Parallel Input/Output Control
6.6.3.3
Port C Pull Enable Register (PTCPE)
7
6
5
4
3
2
1
0
PTCPE7
PTCPE6
PTCPE5
PTCPE4
PTCPE3
PTCPE2
PTCPE1
PTCPE0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-17. Internal Pull Enable for Port C Register (PTCPE)
Table 6-15. PTCPE Register Field Descriptions
Field
Description
7–0
PTCPEn
Internal Pull Enable for Port C Bits — Each of these control bits determines if the internal pull-up device is
enabled for the associated PTC pin. For port C pins that are configured as outputs, these bits have no effect and
the internal pull devices are disabled.
0 Internal pull-up device disabled for port C bit n.
1 Internal pull-up device enabled for port C bit n.
6.6.3.4
Port C Slew Rate Enable Register (PTCSE)
7
6
5
4
3
2
1
0
PTCSE7
PTCSE6
PTCSE5
PTCSE4
PTCSE3
PTCSE2
PTCSE1
PTCSE0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-18. Slew Rate Enable for Port C Register (PTCSE)
Table 6-16. PTCSE Register Field Descriptions
Field
Description
7–0
PTCSEn
Output Slew Rate Enable for Port C Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTC pin. For port C pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port C bit n.
1 Output slew rate control enabled for port C bit n.
6.6.3.5
Port C Drive Strength Selection Register (PTCDS)
7
6
5
4
3
2
1
0
PTCDS7
PTCDS6
PTCDS5
PTCDS4
PTCDS3
PTCDS2
PTCDS1
PTCDS0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-19. Drive Strength Selection for Port C Register (PTCDS)
MCF51MM256 Series Devices Reference Manual, Rev. 3
6-12
Freescale Semiconductor
Parallel Input/Output Control
Table 6-17. PTCDS Register Field Descriptions
Field
Description
7–0
PTCDSn
Output Drive Strength Selection for Port C Bits — Each of these control bits selects between low and high
output drive for the associated PTC pin. For port C pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port C bit n.
1 High output drive strength selected for port C bit n.
6.6.3.6
Port C Input Filter Enable Register (PTCIFE)
The Port C pin incorporates an optional input low-pass filter. Set the associated PTCIFE bit during and
after reset to enable the filter. To disable the filter, clear the associated PTCIFE bit through software
control.
7
6
5
4
3
2
1
0
PTCIFE7
PTCIFE6
PTCIFE5
PTCIFE4
PTCIFE3
PTCIFE2
PTCIFE1
PTCIFE0
1
1
1
1
1
1
1
1
R
W
Reset:
Figure 6-20. Input Filter Enable for Port C Register (PTCIFE)
Table 6-18. PTCIFE Register Field Descriptions
Field
7–0
PTCIFEn
6.6.4
Description
Input Filter Enable for Port C Bits — Input low-pass filter enable control bits for PTC pins.
0 Input filter disabled.
1 Input filter enabled.
Port D Registers
Port D is controlled by the registers listed below.
PTD0 is an output only pin, so the control bits for input functions have no effect on this pin.
6.6.4.1
Port D Data Register (PTDD)
7
6
5
4
3
2
1
0
PTDD7
PTDD6
PTDD5
PTDD4
PTDD3
PTDD2
PTDD1
PTDD01
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-21. Port D Data Register (PTDD)
1
Reads of bit PTDD0 always return the contents of the PTDD0, regardless of the value stored in the PTDDD0 bit.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
6-13
Parallel Input/Output Control
Table 6-19. PTDD Register Field Descriptions
Field
Description
7–0
PTDDn
Port D Data Register Bits — For port D pins that are inputs, reads return the logic level on the pin. For port D
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port D pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTDD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pull-ups/pull-downs disabled.
6.6.4.2
Port D Data Direction Register (PTDDD)
7
6
5
4
3
2
1
0
PTDDD7
PTDDD6
PTDDD5
PTDDD4
PTDDD3
PTDDD2
PTDDD1
PTDDD01
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-22. Port D Data Direction Register (PTDDD)
1
PTDDD0 has no effect in the output only PTD0 pin
Table 6-20. PTDDD Register Field Descriptions
Field
Description
7–0
PTDDDn
Data Direction for Port D Bits — These read/write bits control the direction of port D pins and what is read for
PTDD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port D bit n and PTDD reads return the contents of PTDDn.
6.6.4.3
Port D Pull Enable Register (PTDPE)
7
6
5
4
3
2
1
0
PTDPE7
PTDPE6
PTDPE5
PTDPE4
PTDPE3
PTDPE2
PTDPE1
PTDPE01
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-23. Internal Pull Enable for Port D Register (PTDPE)
1
PTDPE0 has no effect in the output only PTD0 pin
Table 6-21. PTDPE Register Field Descriptions
Field
Description
7–0
PTDPEn
Internal Pull Enable for Port D Bits — Each of these control bits determines if the internal pull-up device is
enabled for the associated PTD pin. For port D pins that are configured as outputs, these bits have no effect and
the internal pull devices are disabled.
0 Internal pull-up device disabled for port D bit n.
1 Internal pull-up device enabled for port D bit n.
MCF51MM256 Series Devices Reference Manual, Rev. 3
6-14
Freescale Semiconductor
Parallel Input/Output Control
6.6.4.4
Port D Slew Rate Enable Register (PTDSE)
7
6
5
4
3
2
1
0
PTDSE7
PTDSE6
PTDSE5
PTDSE4
PTDSE3
PTDSE2
PTDSE1
PTDSE0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-24. Slew Rate Enable for Port D Register (PTDSE)
Table 6-22. PTDSE Register Field Descriptions
Field
Description
7–0
PTDSEn
Output Slew Rate Enable for Port D Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTD pin. For port D pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port D bit n.
1 Output slew rate control enabled for port D bit n.
6.6.4.5
Port D Drive Strength Selection Register (PTDDS)
7
6
5
4
3
2
1
0
PTDDS7
PTDDS6
PTDDS5
PTDDS4
PTDDS3
PTDDS2
PTDDS1
PTDDS0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-25. Drive Strength Selection for Port D Register (PTDDS)
Table 6-23. PTDDS Register Field Descriptions
Field
Description
7–0
PTDDSn
Output Drive Strength Selection for Port D Bits — Each of these control bits selects between low and high
output drive for the associated PTD pin. For port D pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port D bit n.
1 High output drive strength selected for port D bit n.
6.6.4.6
Port D Input Filter Enable Register (PTDIFE)
The Port D pin incorporates an optional input low-pass filter. Set the associated PTDIFE bit during and
after reset to enable the filter. To disable the filter, clear the associated PTDIFE bit through software
control.
7
6
5
4
3
2
1
0
PTDIFE7
PTDIFE6
PTDIFE5
PTDIFE4
PTDIFE3
PTDIFE2
PTDIFE1
PTDIFE0
1
1
1
1
1
1
1
1
R
W
Reset:
Figure 6-26. Input Filter Enable for Port D Register (PTDIFE)
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
6-15
Parallel Input/Output Control
Table 6-24. PTDIFE Register Field Descriptions
Field
7–0
PTDIFEn
6.6.5
Description
Input Filter Enable for Port D Bits — Input low-pass filter enable control bits for PTD pins.
0 Input filter disabled.
1 Input filter enabled.
Port E Registers
Port E is controlled by the registers listed below.
PTE4 is an input only pin. The control bits for input functions do not have an effect on this pin.
6.6.5.1
Port E Data Register (PTED)
7
6
5
4
3
2
1
0
PTED7
PTED6
PTED5
PTED41
PTED3
PTED2
PTED1
PTED0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-27. Port E Data Register (PTED)
1
Reads of bit PTED4 always return the pin value.
Table 6-25. PTED Register Field Descriptions
Field
Description
7–0
PTEDn
Port E Data Register Bits — For port E pins that are inputs, reads return the logic level on the pin. For port E
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port E pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTED to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pull-ups disabled.
6.6.5.2
Port E Data Direction Register (PTEDD)
7
6
5
4
3
2
1
0
PTEDD7
PTEDD6
PTEDD5
0
PTEDD3
PTEDD2
PTEDD1
PTEDD0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-28. Port E Data Direction Register (PTEDD)
MCF51MM256 Series Devices Reference Manual, Rev. 3
6-16
Freescale Semiconductor
Parallel Input/Output Control
Table 6-26. PTEDD Register Field Descriptions
Field
Description
7–0
PTEDDn
Data Direction for Port E Bits — These read/write bits control the direction of port E pins and what is read for
PTED reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port E bit n and PTED reads return the contents of PTEDn.
P
Table 6-27. PTETOG Register Field Descriptions
Field
7–0
PTETOGn
6.6.5.3
Description
Toggle Enable for Port E Bits — Writing any bit to one in this location will toggle the corresponding bit in the
data register. Writing a zero to any bit in this register has no effect.
0 Corresponding PTEDn maintains current value.
1 Corresponding PTEDn is toggled once.
Port E Pull Enable Register (PTEPE)
7
6
5
4
3
2
1
0
PTEPE7
PTEPE6
PTEPE5
PTEPE4
PTEPE3
PTEPE2
PTEPE1
PTEPE0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-29. Internal Pull Enable for Port E Register (PTEPE)
Table 6-28. PTEPE Register Field Descriptions
Field
Description
7–0
PTEPEn
Internal Pull Enable for Port E Bits — Each of these control bits determines if the internal pull-up device is
enabled for the associated PTE pin. For port E pins that are configured as outputs, these bits have no effect and
the internal pull devices are disabled.
0 Internal pull-up device disabled for port E bit n.
1 Internal pull-up device enabled for port E bit n.
6.6.5.4
Port E Slew Rate Enable Register (PTESE)
7
6
5
4
3
2
1
0
PTESE7
PTESE6
PTESE5
PTESE41
PTESE3
PTESE2
PTESE1
PTESE0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-30. Slew Rate Enable for Port E Register (PTESE)
1
PTE4SE has no effect on the PTE4 pin
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
6-17
Parallel Input/Output Control
Table 6-29. PTESE Register Field Descriptions
Field
Description
7–0
PTESEn
Output Slew Rate Enable for Port E Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTE pin. For port E pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port E bit n.
1 Output slew rate control enabled for port E bit n.
6.6.5.5
Port E Drive Strength Selection Register (PTEDS)
7
6
5
4
3
2
1
0
PTEDS7
PTEDS6
PTEDS5
PTEDS41
PTEDS3
PTEDS2
PTEDS1
PTEDS0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-31. Drive Strength Selection for Port E Register (PTEDS)
1
PTEDS4 has no effect on the PTE4 pin
Table 6-30. PTEDS Register Field Descriptions
Field
Description
7–0
PTEDSn
Output Drive Strength Selection for Port E Bits — Each of these control bits selects between low and high
output drive for the associated PTE pin. For port E pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port E bit n.
1 High output drive strength selected for port E bit n.
6.6.5.6
Port E Input Filter Enable Register (PTEIFE)
The Port E pin incorporates an optional input low-pass filter. Set the associated PTEIFE bit during and after
reset to enable the filter. To disable the filter, clear the associated PTEIFE bit through software control.
7
6
5
4
3
2
1
0
PTEIFE7
PTEIFE6
PTEIFE5
PTEIFE4
PTEIFE3
PTEIFE2
PTEIFE1
PTEIFE0
1
1
1
1
1
1
1
1
R
W
Reset:
Figure 6-32. Input Filter Enable for Port E Register (PTEIFE)
Table 6-31. PTEIFE Register Field Descriptions
Field
7–0
PTEIFEn
Description
Input Filter Enable for Port E Bits — Input low-pass filter enable control bits for PTE pins.
0 Input filter disabled.
1 Input filter enabled.
MCF51MM256 Series Devices Reference Manual, Rev. 3
6-18
Freescale Semiconductor
Parallel Input/Output Control
6.6.6
Port F Registers
Port F is controlled by the registers listed below.
PTF6 is an output only pin, so the control bits for input functions have no effect on this pin.
6.6.6.1
Port F Data Register (PTFD)
7
6
5
4
3
2
1
0
PTFD7
PTFD6
PTFD5
PTFD4
PTFD3
PTFD2
PTFD1
PTFD0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-33. Port F Data Register (PTFD)
Table 6-32. PTFD Register Field Descriptions
Field
Description
7–0
PTFDn
Port F Data Register Bits — For port F pins that are inputs, reads return the logic level on the pin. For port F
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port F pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTFD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pull-ups disabled.
6.6.6.2
Port F Data Direction Register (PTFDD)
7
6
5
4
3
2
1
0
PTFDD7
PTFDD6
PTFDD5
PTFDD4
PTFDD3
PTFDD2
PTFDD1
PTFDD0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-34. Port F Data Direction Register (PTFDD)
Table 6-33. PTFDD Register Field Descriptions
Field
Description
7–0
PTFDDn
Data Direction for Port F Bits — These read/write bits control the direction of port F pins and what is read for
PTFD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port F bit n and PTFD reads return the contents of PTFDn.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
6-19
Parallel Input/Output Control
6.6.6.3
Port F Pull Enable Register (PTFPE)
7
6
5
4
3
2
1
0
PTFPE7
PTFPE6
PTFPE5
PTFPE4
PTFPE3
PTFPE2
PTFPE1
PTFPE0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-35. Internal Pull Enable for Port F Register (PTFPE)
Table 6-34. PTFPE Register Field Descriptions
Field
Description
7–0
PTFPEn
Internal Pull Enable for Port F Bits — Each of these control bits determines if the internal pull-up device is
enabled for the associated PTF pin. For port F pins that are configured as outputs, these bits have no effect and
the internal pull devices are disabled.
0 Internal pull-up device disabled for port F bit n.
1 Internal pull-up device enabled for port F bit n.
6.6.6.4
Port F Slew Rate Enable Register (PTFSE)
7
6
5
4
3
2
1
0
PTFSE7
PTFSE6
PTFSE5
PTFSE4
PTFSE3
PTFSE2
PTFSE1
PTFSE0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-36. Slew Rate Enable for Port F Register (PTFSE)
Table 6-35. PTFSE Register Field Descriptions
Field
Description
7–0
PTFSEn
Output Slew Rate Enable for Port F Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTF pin. For port F pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port F bit n.
1 Output slew rate control enabled for port F bit n.
6.6.6.5
Port F Drive Strength Selection Register (PTFDS)
7
6
5
4
3
2
1
0
PTFDS7
PTFDS6
PTFDS5
PTFDS4
PTFDS3
PTFDS2
PTFDS1
PTFDS0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-37. Drive Strength Selection for Port F Register (PTFDS)
MCF51MM256 Series Devices Reference Manual, Rev. 3
6-20
Freescale Semiconductor
Parallel Input/Output Control
Table 6-36. PTFDS Register Field Descriptions
Field
Description
7–0
PTFDSn
Output Drive Strength Selection for Port F Bits — Each of these control bits selects between low and high
output drive for the associated PTF pin. For port F pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port F bit n.
1 High output drive strength selected for port F bit n.
6.6.6.6
Port F Input Filter Enable Register (PTFIFE)
The Port F pin incorporates an optional input low-pass filter. Set the associated PTFIFE bit during and after
reset to enable the filter. To disable the filter, clear the associated PTFIFE bit through software control.
7
6
5
4
3
2
1
0
PTFIFE7
PTFIFE6
PTFIFE5
PTFIFE4
PTFIFE3
PTFIFE2
PTFIFE1
PTFIFE0
1
1
1
1
1
1
1
1
R
W
Reset:
Figure 6-38. Input Filter Enable for Port F Register (PTFIFE)
Table 6-37. PTFIFE Register Field Descriptions
Field
7–0
PTFIFEn
6.6.7
Description
Input Filter Enable for Port F Bits — Input low-pass filter enable control bits for PTF pins.
0 Input filter disabled.
1 Input filter enabled.
Port G Registers
Port G is controlled by the registers listed below.
6.6.7.1
Port G Data Register (PTGD)
7
6
5
4
3
2
1
0
PTGD7
PTGD6
PTGD5
PTGD4
PTGD3
PTGD2
PTGD1
PTGD0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-39. Port G Data Register (PTGD)
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
6-21
Parallel Input/Output Control
Table 6-38. PTGD Register Field Descriptions
Field
Description
7–0
PTGDn
Port G Data Register Bits — For port G pins that are inputs, reads return the logic level on the pin. For port G
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port G pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTGD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pull-ups disabled.
6.6.7.2
Port G Data Direction Register (PTGDD)
7
6
5
4
3
2
1
0
PTGDD7
PTGDD6
PTGDD5
PTGDD4
PTGDD3
PTGDD2
PTGDD1
PTGDD0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-40. Port G Data Direction Register (PTGDD)
Table 6-39. PTGDD Register Field Descriptions
Field
Description
7–0
PTGDDn
Data Direction for Port G Bits — These read/write bits control the direction of port G pins and what is read for
PTGD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port G bit n and PTGD reads return the contents of PTGDn.
6.6.7.3
Port G Pull Enable Register (PTGPE)
7
6
5
4
3
2
1
0
PTGPE7
PTGPE6
PTGPE5
PTGPE4
PTGPE3
PTGPE2
PTGPE1
PTGPE0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-41. Internal Pull Enable for Port G Register (PTGPE)
Table 6-40. PTGPE Register Field Descriptions
Field
Description
7–0
PTGPEn
Internal Pull Enable for Port G Bits — Each of these control bits determines if the internal pull-up device is
enabled for the associated PTG pin. For port G pins that are configured as outputs, these bits have no effect and
the internal pull devices are disabled.
0 Internal pull-up device disabled for port G bit n.
1 Internal pull-up device enabled for port G bit n.
MCF51MM256 Series Devices Reference Manual, Rev. 3
6-22
Freescale Semiconductor
Parallel Input/Output Control
6.6.7.4
Port G Slew Rate Enable Register (PTGSE)
7
6
5
4
3
2
1
0
PTGSE7
PTGSE6
PTGSE5
PTGSE4
PTGSE3
PTGSE2
PTGSE1
PTGSE0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-42. Slew Rate Enable for Port G Register (PTGSE)
Table 6-41. PTGSE Register Field Descriptions
Field
Description
7–0
PTGSEn
Output Slew Rate Enable for Port G Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTG pin. For port G pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port G bit n.
1 Output slew rate control enabled for port G bit n.
6.6.7.5
Port G Drive Strength Selection Register (PTGDS)
7
6
5
4
3
2
1
0
PTGDS7
PTGDS6
PTGDS5
PTGDS4
PTGDS3
PTGDS2
PTGDS1
PTGDS0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-43. Drive Strength Selection for Port G Register (PTGDS)
Table 6-42. PTGDS Register Field Descriptions
Field
Description
7–0
PTGDSn
Output Drive Strength Selection for Port G Bits — Each of these control bits selects between low and high
output drive for the associated PTG pin. For port G pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port G bit n.
1 High output drive strength selected for port G bit n.
6.6.7.6
Port G Input Filter Enable Register (PTGIFE)
The Port G pin incorporates an optional input low-pass filter. Set the associated PTGIFE bit during and
after reset to enable the filter. To disable the filter, clear the associated PTGIFE bit through software
control.
7
6
5
4
3
2
1
0
PTGIFE7
PTGIFE6
PTGIFE5
PTGIFE4
PTGIFE3
PTGIFE2
PTGIFE1
PTGIFE0
1
1
1
1
1
1
1
1
R
W
Reset:
Figure 6-44. Input Filter Enable for Port G Register (PTGIFE)
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
6-23
Parallel Input/Output Control
Table 6-43. PTGIFE Register Field Descriptions
Field
7–0
PTGIFEn
6.6.8
Description
Input Filter Enable for Port G Bits — Input low-pass filter enable control bits for PTG pins.
0 Input filter disabled.
1 Input filter enabled.
Port H Registers
Port H is controlled by the registers listed below.
6.6.8.1
Port H Data Register (PTHD)
7
6
5
4
3
2
1
0
PTHD7
PTHD6
PTHD5
PTHD4
PTHD3
PTHD2
PTHD1
PTHD0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-45. Port H Data Register (PTHD)
Table 6-44. PTHD Register Field Descriptions
Field
Description
7–0
PTHDn
Port H Data Register Bits — For port H pins that are inputs, reads return the logic level on the pin. For port H
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port H pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTHD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pull-ups disabled.
6.6.8.2
Port H Data Direction Register (PTHDD)
7
6
5
4
3
2
1
0
PTHDD7
PTHDD6
PTHDD5
PTHDD4
PTHDD3
PTHDD2
PTHDD1
PTHDD0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-46. Port H Data Direction Register (PTHDD)
Table 6-45. PTHDD Register Field Descriptions
Field
Description
7–0
PTHDDn
Data Direction for Port H Bits — These read/write bits control the direction of port H pins and what is read for
PTHD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port H bit n and PTHD reads return the contents of PTHDn.
MCF51MM256 Series Devices Reference Manual, Rev. 3
6-24
Freescale Semiconductor
Parallel Input/Output Control
6.6.8.3
Port H Pull Enable Register (PTHPE)
7
6
5
4
3
2
1
0
PTHPE4
PTHPE3
PTHPE2
PTHPE1
PTHPE0
0
0
0
0
0
R
W
Reset:
0
0
0
Figure 6-47. Internal Pull Enable for Port H Register (PTHPE)
Table 6-46. PTHPE Register Field Descriptions
Field
Description
4–0
PTHPEn
Internal Pull Enable for Port H Bits — Each of these control bits determines if the internal pull-up device is
enabled for the associated PTH pin. For port H pins that are configured as outputs, these bits have no effect and
the internal pull devices are disabled.
0 Internal pull-up device disabled for port H bit n.
1 Internal pull-up device enabled for port H bit n.
6.6.8.4
Port H Slew Rate Enable Register (PTHSE)
7
6
5
4
3
2
1
0
PTHSE7
PTHSE6
PTHSE5
PTHSE4
PTHSE3
PTHSE2
PTHSE1
PTHSE0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-48. Slew Rate Enable for Port H Register (PTHSE)
Table 6-47. PTHSE Register Field Descriptions
Field
Description
7–0
PTHSEn
Output Slew Rate Enable for Port H Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTH pin. For port H pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port H bit n.
1 Output slew rate control enabled for port H bit n.
6.6.8.5
Port H Drive Strength Selection Register (PTHDS)
7
6
5
4
3
2
1
0
PTHDS7
PTHDS6
PTHDS5
PTHDS4
PTHDS3
PTHDS2
PTHDS1
PTHDS0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-49. Drive Strength Selection for Port H Register (PTHDS)
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
6-25
Parallel Input/Output Control
Table 6-48. PTHDS Register Field Descriptions
Field
Description
7–0
PTHDSn
Output Drive Strength Selection for Port H Bits — Each of these control bits selects between low and high
output drive for the associated PTH pin. For port H pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port H bit n.
1 High output drive strength selected for port H bit n.
6.6.8.6
Port H Input Filter Enable Register (PTHIFE)
The Port H pin incorporates an optional input low-pass filter. Set the associated PTHIFE bit during and
after reset to enable the filter. To disable the filter, clear the associated PTHIFE bit through software
control.
7
6
5
4
3
2
1
0
PTHIFE7
PTHIFE6
PTHIFE5
PTHIFE4
PTHIFE3
PTHIFE2
PTHIFE1
PTHIFE0
1
1
1
1
1
1
1
1
R
W
Reset:
Figure 6-50. Input Filter Enable for Port H Register (PTHIFE)
Table 6-49. PTHIFE Register Field Descriptions
Field
7–0
PTHIFEn
6.6.9
Description
Input Filter Enable for Port H Bits — Input low-pass filter enable control bits for PTH pins.
0 Input filter disabled.
1 Input filter enabled.
Port J Registers
Port J is controlled by the registers listed below.
6.6.9.1
Port J Data Register (PTJD)
7
6
5
4
3
2
1
0
PTJD7
PTJD6
PTJD5
PTJD4
PTJD3
PTJD2
PTJD1
PTJD0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-51. Port J Data Register (PTJD)
MCF51MM256 Series Devices Reference Manual, Rev. 3
6-26
Freescale Semiconductor
Parallel Input/Output Control
Table 6-50. PTJD Register Field Descriptions
Field
Description
7–0
PTJDn
Port J Data Register Bits — For port J pins that are inputs, reads return the logic level on the pin. For port J
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port J pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTJD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pull-ups disabled.
6.6.9.2
Port J Data Direction Register (PTJDD)
7
6
5
4
3
2
1
0
PTJDD7
PTJDD6
PTJDD5
PTJDD4
PTJDD3
PTJDD2
PTJDD1
PTJDD0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-52. Port J Data Direction Register (PTJDD)
Table 6-51. PTJDD Register Field Descriptions
Field
Description
7–0
PTJDDn
Data Direction for Port J Bits — These read/write bits control the direction of port J pins and what is read for
PTJD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port J bit n and PTJD reads return the contents of PTJDn.
6.6.9.3
Port J Pull Enable Register (PTJPE)
7
6
5
4
3
2
1
0
PTJPE7
PTJPE6
PTJPE5
PTJPE4
PTJPE3
PTJPE2
PTJPE1
PTJPE0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-53. Internal Pull Enable for Port J Register (PTJPE)
Table 6-52. PTJPE Register Field Descriptions
Field
Description
4–0
PTJPEn
Internal Pull Enable for Port J Bits — Each of these control bits determines if the internal pull-up device is
enabled for the associated PTJ pin. For port J pins that are configured as outputs, these bits have no effect and
the internal pull devices are disabled.
0 Internal pull-up device disabled for port J bit n.
1 Internal pull-up device enabled for port J bit n.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
6-27
Parallel Input/Output Control
6.6.9.4
Port J Slew Rate Enable Register (PTJSE)
7
6
5
4
3
2
1
0
PTJSE7
PTJSE6
PTJSE5
PTJSE4
PTJSE3
PTJSE2
PTJSE1
PTJSE0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-54. Slew Rate Enable for Port J Register (PTJSE)
Table 6-53. PTJSE Register Field Descriptions
Field
Description
7–0
PTJSEn
Output Slew Rate Enable for Port J Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTJ pin. For port J pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port J bit n.
1 Output slew rate control enabled for port J bit n.
6.6.9.5
Port J Drive Strength Selection Register (PTJDS)
7
6
5
4
3
2
1
0
PTJDS7
PTJDS6
PTJDS5
PTJDS4
PTJDS3
PTJDS2
PTJDS1
PTJDS0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-55. Drive Strength Selection for Port J Register (PTJDS)
Table 6-54. PTJDS Register Field Descriptions
Field
Description
7–0
PTJDSn
Output Drive Strength Selection for Port J Bits — Each of these control bits selects between low and high
output drive for the associated PTJ pin. For port J pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port J bit n.
1 High output drive strength selected for port J bit n.
6.6.9.6
Port J Input Filter Enable Register (PTJIFE)
The Port J pin incorporates an optional input low-pass filter. Set the associated PTJIFE bit during and after
reset to enable the filter. To disable the filter, clear the associated PTJIFE bit through software control.
7
6
5
4
3
2
1
0
PTJIFE7
PTJIFE6
PTJIFE5
PTJIFE4
PTJIFE3
PTJIFE2
PTJIFE1
PTJIFE0
1
1
1
1
1
1
1
1
R
W
Reset:
Figure 6-56. Input Filter Enable for Port J Register (PTJIFE)
MCF51MM256 Series Devices Reference Manual, Rev. 3
6-28
Freescale Semiconductor
Parallel Input/Output Control
Table 6-55. PTJIFE Register Field Descriptions
Field
7–0
PTJIFEn
6.6.10
Description
Input Filter Enable for Port J Bits — Input low-pass filter enable control bits for PTJ pins.
0 Input filter disabled.
1 Input filter enabled.
Keyboard Interrupt 1 (KBI1) Registers
KBI1 is controlled by the registers listed below. Table 6-56 shows KBI1 pin mapping to the port I/O pins.
Table 6-56. KBI1 Pin Mapping
Port pin
PTC4
PTC3
PTC2
PTB7
PTB6
PTA3
PTA2
PTA1
KBI1 pin
KBI1P7
KBI1P6
KBI1P5
KBI1P4
KBI1P3
KBI1P2
KBI1P1
KBI1P0
1
0
KB1IE
KBI1MOD
0
0
6.6.10.1
R
KBI1 Interrupt Status and Control Register (KBI1SC)
7
6
5
4
3
2
0
0
0
0
KB1F
0
W
Reset:
KB1ACK
0
0
0
0
0
0
Figure 6-57. KBI1 Interrupt Status and Control Register (KBI1SC)
Table 6-57. KBI1SC Register Field Descriptions
Field
7–4
3
KB1F
2
KB1ACK
1
KB1IE
0
KBI1MOD
Description
Reserved, should be cleared.
KBI1 Interrupt Flag — KBF indicates when a KBI1 interrupt is detected. Writes have no effect on KBF.
0 No KBI1 interrupt detected.
1 KBI1 interrupt detected.
KBI1 Interrupt Acknowledge — Writing a 1 to KBACK is part of the flag clearing mechanism. KBACK always
reads as 0.
KBI1 Interrupt Enable — KBIE determines whether a KBI1 interrupt is requested.
0 KBI1 interrupt request not enabled.
1 KBI1 interrupt request enabled.
KBI1 Detection Mode — KBIMOD (along with the KBI1ES bits) controls the detection mode of the KBI1 interrupt
pins.
0 KBI1 pins detect edges only.
1 KBI1 pins detect both edges and levels.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
6-29
Parallel Input/Output Control
6.6.10.2
KBI1 Interrupt Pin Select Register (KBI1PE)
7
6
5
4
3
2
1
0
KBI1PE7
KBI1PE6
KBI1PE5
KBI1PE4
KBI1PE3
KBI1PE2
KBI1PE1
KBI1PE0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-58. KBI1 Interrupt Pin Select Register (KBI1PE)
Table 6-58. KBI1PE Register Field Descriptions
Field
Description
7–0
KBI1PEn
6.6.10.3
KBI1 Interrupt Pin Selects — Each of the KBIPEn bits enable the corresponding KBI1 interrupt pin.
0 Pin not enabled as interrupt.
1 Pin enabled as interrupt.
KBI1 Interrupt Edge Select Register (KBI1ES)
7
6
5
4
3
2
1
0
KB1EDG7
KB1EDG6
KB1EDG5
KB1EDG4
KB1EDG3
KB1EDG2
KB1EDG1
KB1EDG0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-59. KBI1 Edge Select Register (KBI1ES)
6.6.11
Keyboard Interrupt 2 (KBI2) Registers
Table 6-59. KBI2ES Register Field Descriptions
Field
Description
7–0
KBEDGn
KBI2 Edge Selects — Each of the KBEDGn bits serves a dual purpose by selecting the polarity of the active
interrupt edge as well as selecting a pull-up or pull-down device if enabled.
0 A pull-up device is connected to the associated pin and detects falling edge/low level for interrupt generation.
1 A pull-down device is connected to the associated pin and detects rising edge/high level for interrupt
generation.
KBI2 is controlled by the registers listed below. Table 6-56 shows KBI2 pin mapping to the port I/O pins.
Table 6-60. KBI2 Pin Mapping
Port pin
PTF5
PTE3
PTE2
PTE1
PTE0
PTC7
PTC6
PTC5
KBI2 pin
KBI2P7
KBI2P6
KBI2P5
KBI2P4
KBI2P3
KBI2P2
KBI2P1
KBI2P0
MCF51MM256 Series Devices Reference Manual, Rev. 3
6-30
Freescale Semiconductor
Parallel Input/Output Control
6.6.11.1
R
KBI2 Interrupt Status and Control Register (KBI2SC)
7
6
5
4
3
2
0
0
0
0
KB2F
0
W
Reset:
1
0
KB2IE
KBI2MOD
0
0
KB2ACK
0
0
0
0
0
0
Figure 6-60. KBI2 Interrupt Status and Control Register (KBI2SC)
Table 6-61. KBI2SC Register Field Descriptions
Field
7–4
3
KB2F
2
KB2ACK
1
KB2IE
0
KBI2MOD
6.6.11.2
Description
Reserved, should be cleared.
KBI2 Interrupt Flag — KBF indicates when a KBI2 interrupt is detected. Writes have no effect on KBF.
0 No KBI2 interrupt detected.
1 KBI2 interrupt detected.
KBI2 Interrupt Acknowledge — Writing a 1 to KBACK is part of the flag clearing mechanism. KBACK always
reads as 0.
KBI2 Interrupt Enable — KBIE determines whether a KBI2 interrupt is requested.
0 KBI2 interrupt request not enabled.
1 KBI2 interrupt request enabled.
KBI2 Detection Mode — KBIMOD (along with the KBI2ES bits) controls the detection mode of the KBI2 interrupt
pins.
0 KBI2 pins detect edges only.
1 KBI2 pins detect both edges and levels.
KBI2 Interrupt Pin Select Register (KBI2PE)
7
6
5
4
3
2
1
0
KBI2PE7
KBI2PE6
KBI2PE5
KBI2PE4
KBI2PE3
KBI2PE2
KBI2PE1
KBI2PE0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-61. KBI2 Interrupt Pin Select Register (KBI2PE)
Table 6-62. KBI2PE Register Field Descriptions
Field
7–0
KBI2PEn
Description
KBI2 Interrupt Pin Selects — Each of the KBIPEn bits enable the corresponding KBI2 interrupt pin.
0 Pin not enabled as interrupt.
1 Pin enabled as interrupt.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
6-31
Parallel Input/Output Control
6.6.11.3
KBI2 Interrupt Edge Select Register (KBI2ES)
7
6
5
4
3
2
1
0
KB2EDG7
KB2EDG6
KB2EDG5
KB2EDG4
KB2EDG3
KB2EDG2
KB2EDG1
KB2EDG0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 6-62. KBI2 Edge Select Register (KBI2ES)
Table 6-63. KBI2ES Register Field Descriptions
Field
Description
7–0
KB2EDGn
KBI2 Edge Selects — Each of the KBEDGn bits serves a dual purpose by selecting the polarity of the active
interrupt edge as well as selecting a pull-up or pull-down device if enabled.
0 A pull-up device is connected to the associated pin and detects falling edge/low level for interrupt generation.
1 A pull-down device is connected to the associated pin and detects rising edge/high level for interrupt
generation.
MCF51MM256 Series Devices Reference Manual, Rev. 3
6-32
Freescale Semiconductor
Chapter 7
ColdFire Core
7.1
Introduction
This section describes the organization of the Version 1 (V1) ColdFire® processor core and an overview
of the program-visible registers. For detailed information on instructions, see the ISA_C definition in the
ColdFire Family Programmer’s Reference Manual.
7.1.1
Overview
As with all ColdFire cores, the V1 ColdFire core is comprised of two separate pipelines decoupled by an
instruction buffer.
IAG
Instruction
Address
Generation
IC
Instruction
Fetch Cycle
IB
FIFO
Instruction Buffer
Instruction
Fetch
Pipeline
Address [ 23 :0]
Read Data[31:0]
Operand
Execution
Pipeline
& Select,
DSOC Decode
Operand Fetch
Write Data[31:0]
AGEX
Address
Generation,
Execute
Figure 7-1. V1 ColdFire Core Pipelines
The instruction fetch pipeline (IFP) is a two-stage pipeline for prefetching instructions. The prefetched
instruction stream is then gated into the two-stage operand execution pipeline (OEP), that decodes the
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
7-1
ColdFire Core
instruction, fetches the required operands, and then executes the required function. Because the IFP and
OEP pipelines are decoupled by an instruction buffer serving as a FIFO queue, the IFP is able to prefetch
instructions in advance of their actual use by the OEP thereby minimizing time stalled waiting for
instructions.
The V1 ColdFire core pipeline stages include the following:
• Two-stage instruction fetch pipeline (IFP) (plus optional instruction buffer stage)
— Instruction address generation (IAG) — Calculates the next prefetch address
— Instruction fetch cycle (IC)—Initiates prefetch on the processor’s local bus
— Instruction buffer (IB) — Optional buffer stage minimizes fetch latency effects using FIFO
queue
• Two-stage operand execution pipeline (OEP)
— Decode and select/operand fetch cycle (DSOC)—Decodes instructions and fetches the
required components for effective address calculation, or the operand fetch cycle
— Address generation/execute cycle (AGEX)—Calculates operand address or executes the
instruction
When the instruction buffer is empty, opcodes are loaded directly from the IC cycle into the operand
execution pipeline. If the buffer is not empty, the IFP stores the contents of the fetched instruction in the
IB until it is required by the OEP. The instruction buffer on the V1 core contains three longwords of
storage.
For register-to-register and register-to-memory store operations, the instruction passes through both OEP
stages once. For memory-to-register and read-modify-write memory operations, an instruction is
effectively staged through the OEP twice; the first time to calculate the effective address and initiate the
operand fetch on the processor’s local bus, and the second time to complete the operand reference and
perform the required function defined by the instruction.
The resulting pipeline and local bus structure allow the V1 ColdFire core to deliver sustained high
performance across a variety of demanding embedded applications.
7.2
Memory Map/Register Description
The following sections describe the processor registers in the user and supervisor programming models.
The programming model is selected based on the processor privilege level (user mode or supervisor mode)
as defined by the S bit of the status register (SR). Table 7-1 lists the processor registers.
The user-programming model consists of the following registers:
• 16 general-purpose 32-bit registers (D0–D7, A0–A7)
• 32-bit program counter (PC)
• 8-bit condition code register (CCR)
• MAC registers (described fully in Chapter 8, “Multiply-Accumulate Unit (MAC)”)
— One 32-bit accumulator(ACC) register
— One 16-bit mask register (MASK)
— 8-bit Status register (MACSR)
MCF51MM256 Series Devices Reference Manual, Rev. 3
7-2
Freescale Semiconductor
ColdFire Core
The supervisor programming model is to be used only by system control software to implement restricted
operating system functions, I/O control, and memory management. All accesses that affect the control
features of ColdFire processors are in the supervisor programming model, that consists of registers
available in user mode as well as the following control registers:
• 16-bit status register (SR)
• 32-bit supervisor stack pointer (SSP)
• 32-bit vector base register (VBR)
• 32-bit CPU configuration register (CPUCR)
Table 7-1. ColdFire Core Programming Model
BDM Command1
Width
(bits)
Register
Access
Reset Value
Written with
Section/Page
MOVEC2
Supervisor/User Access Registers
Load: 0x60
Store: 0x40
Data Register 0 (D0)
32
R/W
See
7.3.3.14/7-19
No
7.2.1/7-4
Load: 0x61
Store: 0x41
Data Register 1 (D1)
32
R/W
See
7.3.3.14/7-19
No
7.2.1/7-4
Load: 0x6–7
Store: 0x4–7
Data Register –7 (D–D7)
32
R/W
POR: Undefined
Else: Unaffected
No
7.2.1/7-4
Address Register 0–6 (A0–A6)
32
R/W
POR: Undefined
Else: Unaffected
No
7.2.2/7-4
Load: 0x6F
Store: 0x4F
User A7 Stack Pointer (A7)
32
R/W
POR: Undefined
Else: Unaffected
No
7.2.3/7-5
Load: 0xE4
Store: 0xC4
MAC Status Register (MACSR)
8
R/W
0x00
No
8.2.1/8-2
Load: 0xE5
Store: 0xC5
MAC Address Mask Register (MASK)
16
R/W
0xFFFF
No
8.2.2/8-4
Load: 0xE6
Store: 0xC6
MAC Accumulator (ACC)
32
R/W
POR: Undefined
Else: Unaffected
No
8.2.3/8-5
Load: 0xEE
Store: 0xCE
Condition Code Register (CCR)
8
R/W
POR: Undefined
Else: Unaffected
No
7.2.4/7-5
Load: 0xEF
Store: 0xCF
Program Counter (PC)
32
R/W
Contents of
location
0x(00)00_0004
No
7.2.5/7-6
Load: 0x68–E
Store: 0x48–E
Supervisor Access Only Registers
Load: 0xE0
Store: 0xC0
Supervisor A7 Stack Pointer
(OTHER_A7)
32
R/W
Contents of
location
0x(00)00_0000
No
7.2.3/7-5
Load: 0xE1
Store: 0xC1
Vector Base Register (VBR)
32
R/W
See section
Yes;
Rc = 0x801
7.2.6/7-7
Load: 0xE2
Store: 0xC2
CPU Configuration Register (CPUCR)
32
W
See section
Yes;
Rc = 0x802
7.2.7/7-7
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
7-3
ColdFire Core
Table 7-1. ColdFire Core Programming Model (Continued)
BDM Command1
Load: 0xEE
Store: 0xCE
Register
Status Register (SR)
Width
(bits)
Access
Reset Value
16
R/W
0x27--
Written with
Section/Page
MOVEC2
No
7.2.8/7-8
1
The values listed in this column represent the 8-bit BDM command code used when accessing the core registers via the 1-pin
BDM port. For more information see Chapter 29, “Version 1 ColdFire Debug (CF1_DEBUG).” (These BDM commands are not
similar to other ColdFire processors.)
2
If the given register is written using the MOVEC instruction, the 12-bit control register address (Rc) is also specified.
7.2.1
Data Registers (D0–D7)
D0–D7 data registers are for bit (1-bit), byte (8-bit), word (16-bit) and longword (32-bit) operations; they
can also be used as index registers.
NOTE
Registers D0 and D1 contain hardware configuration details after reset. See
Section 7.3.3.14, “Reset Exception” for more details.
BDM: Load: 0x60 + n; n = 0-7 (Dn)
Store: 0x40 + n; n = 0-7 (Dn)
Access: User read/write
BDM read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
8
7
6
5
4
3
2
1
0
Data
W
Reset
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
(D2-D7)
Reset
(D0, D1)
See Section 7.3.3.14, “Reset Exception”
Figure 7-2. Data Registers (D0–D7)
7.2.2
Address Registers (A0–A6)
These registers can be used as software stack pointers, index registers, or base address registers. They can
also be used for word and longword operations.
BDM: Load: 0x68 + n; n = 0–6 (An)
Store: 0x48 + n; n = 0–6 (An)
Access: User read/write
BDM read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
R
Address
W
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
Figure 7-3. Address Registers (A0–A6)
MCF51MM256 Series Devices Reference Manual, Rev. 3
7-4
Freescale Semiconductor
ColdFire Core
7.2.3
Supervisor/User Stack Pointers (A7 and OTHER_A7)
This ColdFire architecture supports two independent stack pointer (A7) registers—the supervisor stack
pointer (SSP) and the user stack pointer (USP). The hardware implementation of these two
program-visible 32-bit registers does not identify one as the SSP and the other as the USP. Instead, the
hardware uses one 32-bit register as the active A7 and the other as OTHER_A7. Thus, the register contents
are a function of the processor operation mode, as shown in the following:
if SR[S] = 1
then
else
A7 = Supervisor Stack Pointer
OTHER_A7 = User Stack Pointer
A7 = User Stack Pointer
OTHER_A7 = Supervisor Stack Pointer
The BDM programming model supports direct reads and writes to A7 and OTHER_A7. It is the
responsibility of the external development system to determine, based on the setting of SR[S], the mapping
of A7 and OTHER_A7 to the two program-visible definitions (SSP and USP).
To support dual stack pointers, the following two supervisor instructions are included in the ColdFire
instruction set architecture to load/store the USP:
move.l Ay,USP;move to USP
move.l USP,Ax;move from USP
These instructions are described in the ColdFire Family Programmer’s Reference Manual. All other
instruction references to the stack pointer, explicit or implicit, access the active A7 register.
NOTE
The USP must be initialized using the move.l
entry into user mode.
Ay,USP instruction before any
The SSP is loaded during reset exception processing with the contents of
location 0x(00)00_0000.
BDM: Load: 0x6F (A7)
Store: 0x4F (A7)
Load: 0xE0 (OTHER_A7)
Store: 0xC0 (OTHER_A7)
Access: A7: User or BDM read/write
OTHER_A7: Supervisor or BDM read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
R
Address
W
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
Figure 7-4. Stack Pointer Registers (A7 and OTHER_A7)
7.2.4
Condition Code Register (CCR)
The CCR is the LSB of the processor status register (SR). Bits 4–0 act as indicator flags for results
generated by processor operations. The extend bit (X) is also an input operand during multiprecision
arithmetic computations. The CCR register must be explicitly loaded after reset and before any compare
(CMP), Bcc, or Scc instructions are executed.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
7-5
ColdFire Core
BDM: LSB of Status Register (SR)
Load: 0xEE (SR)
Store: 0xCE (SR)
R
Access: User read/write
BDM read/write
7
6
5
0
0
0
4
3
2
1
0
X
N
Z
V
C
—
—
—
—
—
W
Reset:
0
0
0
Figure 7-5. Condition Code Register (CCR)
Table 7-2. CCR Field Descriptions
Field
7–5
Description
Reserved, must be cleared.
4
X
Extend condition code bit. Set to the C-bit value for arithmetic operations; otherwise not affected or set to a specified
result.
3
N
Negative condition code bit. Set if most significant bit of the result is set; otherwise cleared.
2
Z
Zero condition code bit. Set if result equals zero; otherwise cleared.
1
V
Overflow condition code bit. Set if an arithmetic overflow occurs implying the result cannot be represented in operand
size; otherwise cleared.
0
C
Carry condition code bit. Set if a carry out of the operand msb occurs for an addition or if a borrow occurs in a
subtraction; otherwise cleared.
7.2.5
Program Counter (PC)
The PC contains the currently executing instruction address. During instruction execution and exception
processing, the processor automatically increments PC contents or places a new value in the PC. The PC
is a base address for PC-relative operand addressing.
The PC is initially loaded during reset exception processing with the contents at location 0x(00)00_0004.
BDM: Load: 0xEF (PC)
Store: 0xCF (PC)
Access: User read/write
BDM read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
R 0 0 0 0 0 0 0 0
Address
W
Reset 0 0 0 0 0 0 0 0 – – – – – – – – – – – – – – – – – – – – – – – –
Figure 7-6. Program Counter Register (PC)
MCF51MM256 Series Devices Reference Manual, Rev. 3
7-6
Freescale Semiconductor
ColdFire Core
7.2.6
Vector Base Register (VBR)
The VBR contains the base address of the exception vector table in the memory. To access the vector table,
the displacement of an exception vector is added to the value in VBR. The lower 20 bits of the VBR are
not implemented by ColdFire processors. They are assumed to be zero, forcing the table to be aligned on
a 1 MB boundary.
In addition, because the V1 ColdFire core supports a 16 MB address space, the upper byte of the VBR is
also forced to zero. The VBR can be used to relocate the exception vector table from its default position
in the flash memory (address 0x(00)00_0000) to the base of the RAM (address 0x(00)80_0000) if needed.
BDM: 0x801 (VBR)
Load: 0xE1 (VBR)
Store: 0xC1 (VBR)
Access: Supervisor read/write
BDM read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R 0 0 0 0 0 0 0 0
Base
Address
W
8
7
6
5
4
3
2
1
0
– – – – – – – – – – – – – – – – – – – –
Reset 0 0 0 0 0 0 0 0 0 0 0 0 – – – – – – – – – – – – – – – – – – – –
Figure 7-7. Vector Base Register (VBR)
7.2.7
CPU Configuration Register (CPUCR)
The CPUCR provides supervisor mode configurability of specific core functionality. Certain hardware
features can be enabled/disabled individually based on the state of the CPUCR.
BDM: 0x802 (CPUCR)
Load: 0xE2 (CPUCR)
Store: 0xC2 (CPUCR)
31
30
29
28
Access: Supervisor read/write
BDM read/write
27
26
R
25
0
ARD IRD IAE IME BWD
FSD
W
Reset
0
0
0
0
0
0
0
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CB – – – – – – – – – – – – – – – – – – – – – – – –
RR
0
– – – – – – – – – – – – – – – – – – – – – – – –
Figure 7-8. CPU Configuration Register (CPUCR)
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
7-7
ColdFire Core
Table 7-3. CPUCR Field Descriptions
Field
Description
31
ARD
Address-related reset disable. Used to disable the generation of a reset event in response to a processor exception
caused by an address error, a bus error, an RTE format error, or a fault-on-fault halt condition.
0 The detection of these types of exception conditions or the fault-on-fault halt condition generate a reset event.
1 No reset is generated in response to these exception conditions.
30
IRD
Instruction-related reset disable. Used to disable the generation of a reset event in response to a processor exception
caused by the attempted execution of an illegal instruction (except for the ILLEGAL opcode), illegal line A, illegal
line F instructions, or a privilege violation.
0 The detection of these types of exception conditions generate a reset event.
1 No reset is generated in response to these exception conditions.
29
IAE
Interrupt acknowledge (IACK) enable. Forces the processor to generate an IACK read cycle from the interrupt
controller during exception processing to retrieve the vector number of the interrupt request being acknowledged. The
processor’s execution time for an interrupt exception is slightly improved when this bit is cleared.
0 The processor uses the vector number provided by the interrupt controller at the time the request is signaled.
1 IACK read cycle from the interrupt controller is generated.
28
IME
Interrupt mask enable. Forces the processor to raise the interrupt level mask (SR[I]) to 7 during every interrupt
exception.
0 As part of an interrupt exception, the processor sets SR[I] to the level of the interrupt being serviced.
1 As part of an interrupt exception, the processor sets SR[I] to 7. This disables all level 1-6 interrupt requests but
allows recognition of the edge-sensitive level 7 requests.
27
BWD
Buffered write disable. The ColdFire core is capable of marking processor memory writes as bufferable or
non-bufferable.
0 Writes are buffered and the bus cycle is terminated immediately with zero wait states.
1 Disable the buffering of writes. In this configuration, the write transfer is terminated based on the response time
of the addressed destination memory device.
Note: If buffered writes are enabled (BWD = 0), any error status is lost as the immediate termination of the data
transfer assumes an error-free completion.
26
25
FSD
24
CBRR
23–0
7.2.8
Reserved, must be cleared.
Flash speculation disabled. Disables certain performance-enhancing features related to address speculation in the
flash memory controller.
0 The flash controller tries to speculate on read accesses to improve processor performance by minimizing the
exposed flash memory access time. Recall the basic flash access time is two processor cycles.
1 Certain flash address speculation is disabled.
Crossbar round-robin arbitration enable. Configures the crossbar slave ports to fixed-priority or round-robin
arbitration.
0 Fixed-priority arbitration
1 Round robin arbitration
Reserved, must be cleared.
Status Register (SR)
The SR stores the processor status and includes the CCR, the interrupt priority mask, and other control
bits. In supervisor mode, software can access the entire SR. In user mode, only the lower 8 bits (CCR) are
accessible. The control bits indicate the following states for the processor: trace mode (T bit), supervisor
or user mode (S bit), and master or interrupt state (M bit). All defined bits in the SR have read/write access
when in supervisor mode. The lower byte of the SR (the CCR) must be loaded explicitly after reset and
before any compare (CMP), Bcc, or Scc instructions execute.
MCF51MM256 Series Devices Reference Manual, Rev. 3
7-8
Freescale Semiconductor
ColdFire Core
BDM: Load: 0xEE (SR)
Store: 0xCE (SR)
Access: Supervisor read/write
BDM read/write
System Byte
15
R
W
Reset
T
0
14
0
0
13
12
S
M
1
0
11
Condition Code Register (CCR)
10
0
0
9
8
I
1
1
1
7
6
5
0
0
0
0
0
0
4
3
2
1
0
X
N
Z
V
C
—
—
—
—
—
Figure 7-9. Status Register (SR)
Table 7-4. SR Field Descriptions
Field
Description
15
T
Trace enable. When set, the processor performs a trace exception after every instruction.
14
Reserved, must be cleared.
13
S
Supervisor/user state.
0 User mode
1 Supervisor mode
12
M
Master/interrupt state. Bit is cleared by an interrupt exception and software can set it during execution of the RTE or
move to SR instructions.
11
Reserved, must be cleared.
10–8
I
Interrupt level mask. Defines current interrupt level. Interrupt requests are inhibited for all priority levels less than or
equal to current level, except edge-sensitive level 7 requests, which cannot be masked.
7–0
CCR
Refer to Section 7.2.4, “Condition Code Register (CCR)”.
7.3
7.3.1
Functional Description
Instruction Set Architecture (ISA_C)
The original ColdFire instruction set architecture (ISA_A) was derived from the M68000 family opcodes
based on extensive analysis of embedded application code. The ISA was optimized for code compiled
from high-level languages where the dominant operand size was the 32-bit integer declaration. This
approach minimized processor complexity and cost, while providing excellent performance for compiled
applications.
After the initial ColdFire compilers were created, developers noted there were certain ISA additions that
would enhance code density and overall performance. Additionally, as users implemented ColdFire-based
designs into a wide range of embedded systems, they found certain frequently-used instruction sequences
that could be improved by the creation of additional instructions.
The original ISA definition minimized support for instructions referencing byte- and word-sized operands.
Full support for the move byte and move word instructions was provided, but the only other opcodes
supporting these data types are CLR (clear) and TST (test). A set of instruction enhancements has been
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
7-9
ColdFire Core
implemented in subsequent ISA revisions, ISA_B and ISA_C. The new opcodes primarily addressed three
areas:
1. Enhanced support for byte and word-sized operands
2. Enhanced support for position-independent code
3. Miscellaneous instruction additions to address new functionality
Table 7-5 summarizes the instructions added to revision ISA_A to form revision ISA_C. For more details
see the ColdFire Family Programmer’s Reference Manual.
Table 7-5. Instruction Enhancements over Revision ISA_A
Instruction
BITREV
The contents of the destination data register are bit-reversed; that is, new Dn[31] equals old
Dn[0], new Dn[30] equals old Dn[1], ..., new Dn[0] equals old Dn[31].
BYTEREV
The contents of the destination data register are byte-reversed; that is, new Dn[31:24] equals
old Dn[7:0], ..., new Dn[7:0] equals old Dn[31:24].
FF1
The data register, Dn, is scanned, beginning from the most-significant bit (Dn[31]) and ending
with the least-significant bit (Dn[0]), searching for the first set bit. The data register is then
loaded with the offset count from bit 31 where the first set bit appears.
MOV3Q.L
Move from USP
Move to USP
Moves 3-bit immediate data to the destination location.
User Stack Pointer  Destination register
Source register  User Stack Pointer
MVS.{B,W}
Sign-extends source operand and moves it to destination register.
MVZ.{B,W}
Zero-fills source operand and moves it to destination register.
SATS.L
Performs saturation operation for signed arithmetic and updates destination register,
depending on CCR[V] and bit 31 of the register.
TAS.B
Performs indivisible read-modify-write cycle to test and set addressed memory byte.
Bcc.L
Branch conditionally, longword
BSR.L
Branch to sub-routine, longword
CMP.{B,W}
Compare, byte and word
CMPA.W
Compare address, word
CMPI.{B,W}
MOVEI
STLDSR
7.3.2
Description
Compare immediate, byte and word
Move immediate, byte and word to memory using Ax with displacement
Pushes the contents of the status register onto the stack and then reloads the status register
with the immediate data value.
Exception Processing Overview
Exception processing for ColdFire processors is streamlined for performance. The ColdFire processors
differ from the M68000 family because they include:
• A simplified exception vector table
• Reduced relocation capabilities using the vector-base register
MCF51MM256 Series Devices Reference Manual, Rev. 3
7-10
Freescale Semiconductor
ColdFire Core
•
•
A single exception stack frame format
Use of separate system stack pointers for user and supervisor modes.
All ColdFire processors use an instruction restart exception model. Exception processing includes all
actions from fault condition detection to the initiation of fetch for first handler instruction. Exception
processing is comprised of four major steps:
1. The processor makes an internal copy of the SR and then enters supervisor mode by setting the S
bit and disabling trace mode by clearing the T bit. The interrupt exception also forces the M bit to
be cleared and the interrupt priority mask to set to current interrupt request level.
2. The processor determines the exception vector number. For all faults except interrupts, the
processor performs this calculation based on exception type. For interrupts, the processor
performs an interrupt-acknowledge (IACK) bus cycle to obtain the vector number from the
interrupt controller if CPUCR[IAE] is set. The IACK cycle is mapped to special locations within
the interrupt controller’s address space with the interrupt level encoded in the address. If
CPUCR[IAE] is cleared, the processor uses the vector number supplied by the interrupt controller
at the time the request was signaled for improved performance.
3. The processor saves the current context by creating an exception stack frame on the system stack.
The exception stack frame is created at a 0-modulo-4 address on top of the system stack pointed to
by the supervisor stack pointer (SSP). As shown in Figure 7-10, the processor uses a simplified
fixed-length stack frame for all exceptions. The exception type determines whether the program
counter placed in the exception stack frame defines the location of the faulting instruction (fault)
or the address of the next instruction to be executed (next).
4. The processor calculates the address of the first instruction of the exception handler. By definition,
the exception vector table is aligned on a 1 MB boundary. This instruction address is generated by
fetching an exception vector from the table located at the address defined in the vector base register.
The index into the exception table is calculated as (4  vector number). After the exception vector
has been fetched, the vector contents determine the address of the first instruction of the desired
handler. After the instruction fetch for the first opcode of the handler has initiated, exception
processing terminates and normal instruction processing continues in the handler.
All ColdFire processors support a 1024-byte vector table aligned on any 1 MB address boundary (see
Table 7-6). For the V1 ColdFire core, the only practical locations for the vector table are based at
0x(00)00_0000 in the flash or 0x(00)80_0000 in the internal SRAM.
The table contains 256 exception vectors; the first 64 are defined for the core and the remaining 192 are
device-specific peripheral interrupt vectors. See Chapter 10, “Interrupt Controller (CF1_INTC)” for
details on the device-specific interrupt sources.
For the V1 ColdFire core, the table is partially populated with the first 64 reserved for internal processor
exceptions, while vectors 64-102 are reserved for the peripheral I/O requests and the seven software
interrupts. Vectors 103–255 are unused and reserved.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
7-11
ColdFire Core
Table 7-6. Exception Vector Assignments
1
Vector
Number(s)
Vector
Offset (Hex)
Stacked
Program
Counter
Assignment
0
0x000
—
Initial supervisor stack pointer
1
0x004
—
Initial program counter
2
0x008
Fault
Access error
3
0x00C
Fault
Address error
4
0x010
Fault
Illegal instruction
5–7
0x014–0x01C
—
Reserved
8
0x020
Fault
Privilege violation
9
0x024
Next
Trace
10
0x028
Fault
Unimplemented line-A opcode
11
0x02C
Fault
Unimplemented line-F opcode
12
0x030
Next
Debug interrupt
13
0x034
—
Reserved
14
0x038
Fault
Format error
15–23
0x03C–0x05C
—
Reserved
24
0x060
Next
Spurious interrupt
25–31
0x064–0x07C
—
Reserved
32–47
0x080–0x0BC
Next
Trap # 0-15 instructions
48–60
0x0C0–0x0F0
—
Reserved
61
0x0F4
Fault
Unsupported instruction
62–63
0x0F8–0x0FC
—
Reserved
64–102
0x100–0x198
Next
Device-specific interrupts
103–255
0x19C–0x3FC
—
Reserved
Fault refers to the PC of the instruction that caused the exception. Next refers to the PC
of the instruction that follows the instruction that caused the fault.
All ColdFire processors inhibit interrupt sampling during the first instruction of all exception handlers.
This allows any handler to disable interrupts effectively, if necessary, by raising the interrupt mask level
contained in the status register. In addition, the ISA_C architecture includes an instruction (STLDSR) that
stores the current interrupt mask level and loads a value into the SR. This instruction is specifically
intended for use as the first instruction of an interrupt service routine that services multiple interrupt
requests with different interrupt levels. Finally, the V1 ColdFire core includes the CPUCR[IME] bit that
forces the processor to automatically raise the mask level to 7 during the interrupt exception, removing the
need for any explicit instruction in the service routine to perform this function. For more details, see
ColdFire Family Programmer’s Reference Manual.
MCF51MM256 Series Devices Reference Manual, Rev. 3
7-12
Freescale Semiconductor
ColdFire Core
7.3.2.1
Exception Stack Frame Definition
Figure 7-10 shows exception stack frame. The first longword contains the 16-bit format/vector word (F/V)
and the 16-bit status register, and the second longword contains the 32-bit program counter address.
SSP 
31 30 29 28 27
Format
26 25 24 23 22 21 20 19 18 17
FS[3:2]
Vector
+ 0x4
16 15 14 13 12 11 10 9
FS[1:0]
8
7
6
5
4
3
2
1
0
Status Register
Program Counter
Figure 7-10. Exception Stack Frame Form
The 16-bit format/vector word contains three unique fields:
• A 4-bit format field at the top of the system stack is always written with a value of 4, 5, 6, or 7 by
the processor, indicating a two-longword frame format. See Table 7-7.
Table 7-7. Format Field Encodings
•
Original SSP @ Time
of Exception, Bits 1:0
SSP @ 1st
Instruction of
Handler
Format Field
00
Original SSP - 8
0100
01
Original SSP - 9
0101
10
Original SSP - 10
0110
11
Original SSP - 11
0111
There is a 4-bit fault status field, FS[3:0], at the top of the system stack. This field is defined for
access and address errors only and written as zeros for all other exceptions. See Table 7-8.
Table 7-8. Fault Status Encodings
•
FS[3:0]
Definition
00xx
Reserved
0100
Error on instruction fetch
0101
Reserved
011x
Reserved
1000
Error on operand write
1001
Reserved
101x
Reserved
1100
Error on operand read
1101
Reserved
111x
Reserved
The 8-bit vector number, vector[7:0], defines the exception type and is calculated by the processor
for all internal faults and represents the value supplied by the interrupt controller in case of an
interrupt. See Table 7-6.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
7-13
ColdFire Core
7.3.3
7.3.3.1
Processor Exceptions
Access Error Exception
The default operation of the V1 ColdFire processor is the generation of an illegal address reset event if an
access error (also known as a bus error) is detected. If CPUCR[ARD] is set, the reset is disabled and a
processor exception is generated as detailed below.
The exact processor response to an access error depends on the memory reference being performed. For
an instruction fetch, the processor postpones the error reporting until the faulted reference is needed by an
instruction for execution. Therefore, faults during instruction prefetches followed by a change of
instruction flow do not generate an exception. When the processor attempts to execute an instruction with
a faulted opword and/or extension words, the access error is signaled and the instruction is aborted. For
this type of exception, the programming model has not been altered by the instruction generating the access
error.
If the access error occurs on an operand read, the processor immediately aborts the current instruction’s
execution and initiates exception processing. In this situation, any address register updates attributable to
the auto-addressing modes, (for example, (An)+,-(An)), have already been performed, so the programming
model contains the updated An value. In addition, if an access error occurs during a MOVEM instruction
loading from memory, any registers already updated before the fault occurs contain the operands from
memory.
The V1 ColdFire processor uses an imprecise reporting mechanism for access errors on operand writes.
Because the actual write cycle may be decoupled from the processor’s issuing of the operation, the
signaling of an access error appears to be decoupled from the instruction that generated the write.
Accordingly, the PC contained in the exception stack frame merely represents the location in the program
when the access error was signaled. All programming model updates associated with the write instruction
are completed. The NOP instruction can collect access errors for writes. This instruction delays its
execution until all previous operations, including all pending write operations, are complete. If any
previous write terminates with an access error, it is guaranteed to be reported on the NOP instruction.
7.3.3.2
Address Error Exception
The default operation of the V1 ColdFire processor is the generation of an illegal address reset event if an
address error is detected. If CPUCR[ARD] equals 1, then the reset is disabled and a processor exception
is generated as detailed below.
Any attempted execution transferring control to an odd instruction address (if bit 0 of the target address is
set) results in an address error exception.
Any attempted use of a word-sized index register (Xn.w) or a scale factor of eight on an indexed effective
addressing mode generates an address error, as does an attempted execution of a full-format indexed
addressing mode, which is defined by bit 8 of extension word 1 being set.
If an address error occurs on an RTS instruction, the Version 1 ColdFire processor overwrites the faulting
return PC with the address error stack frame.
MCF51MM256 Series Devices Reference Manual, Rev. 3
7-14
Freescale Semiconductor
ColdFire Core
7.3.3.3
Illegal Instruction Exception
The default operation of the V1 ColdFire processor is the generation of an illegal opcode reset event if an
illegal instruction is detected. If CPUCR[IRD] is set, the reset is disabled and a processor exception is
generated as detailed below. There is one special case involving the ILLEGAL opcode (0x4AFC);
attempted execution of this instruction always generates an illegal instruction exception, regardless of the
state of the CPUCR[IRD] bit.
The ColdFire variable-length instruction set architecture supports three instruction sizes: 16, 32, or 48 bits.
The first instruction word is known as the operation word (or opword), while the optional words are known
as extension word 1 and extension word 2. The opword is further subdivided into three sections: the upper
four bits segment the entire ISA into 16 instruction lines, the next 6 bits define the operation mode
(opmode), and the low-order 6 bits define the effective address. See Figure 7-11. The opword line
definition is shown in Table 7-9.
15
14
13
12
11
Line
10
9
8
7
6
5
4
OpMode
3
2
1
0
Effective Address
Mode
Register
Figure 7-11. ColdFire Instruction Operation Word (Opword) Format
Table 7-9. ColdFire Opword Line Definition
Opword[Line]
Instruction Class
0x0
Bit manipulation, Arithmetic and Logical Immediate
0x1
Move Byte
0x2
Move Long
0x3
Move Word
0x4
Miscellaneous
0x5
Add (ADDQ) and Subtract Quick (SUBQ), Set according to Condition Codes (Scc)
0x6
PC-relative change-of-flow instructions
Conditional (Bcc) and unconditional (BRA) branches, subroutine calls (BSR)
0x7
Move Quick (MOVEQ), Move with sign extension (MVS) and zero fill (MVZ)
0x8
Logical OR (OR)
0x9
Subtract (SUB), Subtract Extended (SUBX)
0xA
MAC, Move 3-bit Quick (MOV3Q)
0xB
Compare (CMP), Exclusive-OR (EOR)
0xC
Logical AND (AND), Multiply Word (MUL)
0xD
Add (ADD), Add Extended (ADDX)
0xE
Arithmetic and logical shifts (ASL, ASR, LSL, LSR)
0xF
Write DDATA (WDDATA), Write Debug (WDEBUG)
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
7-15
ColdFire Core
In the original M68000 ISA definition, lines A and F were effectively reserved for user-defined operations
(line A) and co-processor instructions (line F). Accordingly, there are two unique exception vectors
associated with illegal opwords in these two lines.
Any attempted execution of an illegal 16-bit opcode (except for line-A and line-F opcodes) generates an
illegal instruction exception (vector 4). Additionally, any attempted execution of any non-MAC line-A and
most line-F opcodes generate their unique exception types, vector numbers 10 and 11, respectively.
ColdFire cores do not provide illegal instruction detection on the extension words on any instruction,
including MOVEC.
The V1 ColdFire processor also detects two special cases involving illegal instruction conditions:
1. If execution of the stop instruction is attempted and neither low-power stop nor wait modes are
enabled, the processor signals an illegal instruction.
2. If execution of the halt instruction is attempted and BDM is not enabled
(XCSR[ENBDM] equals 0), the processor signals an illegal instruction.
In both cases, the processor response is then dependent on the state of CPUCR[IRD]— a reset event or a
processor exception.
7.3.3.4
Privilege Violation
The default operation of the V1 ColdFire processor is the generation of an illegal opcode reset event if a
privilege violation is detected. If CPUCR[IRD] is set, the reset is disabled and a processor exception is
generated as detailed below.
The attempted execution of a supervisor mode instruction while in user mode generates a privilege
violation exception. See ColdFire Programmer’s Reference Manual for a list of supervisor-mode
instructions.
There is one special case involving the HALT instruction. Normally, this opcode is a supervisor mode
instruction, but if the debug module's CSR[UHE] is set, then this instruction can be also be executed in
user mode for debugging purposes.
7.3.3.5
Trace Exception
To aid in program development, all ColdFire processors provide an instruction-by-instruction tracing
capability. While in trace mode, indicated by setting of the SR[T] bit, the completion of an instruction
execution (for all but the stop instruction) signals a trace exception. This functionality allows a debugger
to monitor program execution.
The stop instruction has the following effects:
1. The instruction before the stop executes and then generates a trace exception. In the exception stack
frame, the PC points to the stop opcode.
2. When the trace handler is exited, the stop instruction executes, loading the SR with the immediate
operand from the instruction.
3. The processor then generates a trace exception. The PC in the exception stack frame points to the
instruction after the stop, and the SR reflects the value loaded in the previous step.
MCF51MM256 Series Devices Reference Manual, Rev. 3
7-16
Freescale Semiconductor
ColdFire Core
If the processor is not in trace mode and executes a stop instruction where the immediate operand sets
SR[T], hardware loads the SR and generates a trace exception. The PC in the exception stack frame points
to the instruction after the stop, and the SR reflects the value loaded in step 2.
Because ColdFire processors do not support any hardware stacking of multiple exceptions, it is the
responsibility of the operating system to check for trace mode after processing other exception types. As
an example, consider a TRAP instruction execution while in trace mode. The processor initiates the trap
exception and then passes control to the corresponding handler. If the system requires that a trace exception
be processed, it is the responsibility of the trap exception handler to check for this condition (SR[T] in the
exception stack frame set) and pass control to the trace handler before returning from the original
exception.
7.3.3.6
Unimplemented Line-A Opcode
The default operation of the V1 ColdFire processor is the generation of an illegal opcode reset event if an
unimplemented line-A opcode is detected. If CPUCR[IRD] is set, the reset is disabled and a processor
exception is generated as detailed below.
A line-A opcode is defined when bits 15-12 of the opword are 0b1010. This exception is generated by the
attempted execution of an undefined line-A opcode.
7.3.3.7
Unimplemented Line-F Opcode
The default operation of the V1 ColdFire processor is the generation of an illegal opcode reset event if an
unimplemented line-F opcode is detected. If CPUCR[IRD] is set, the reset is disabled and a processor
exception is generated as detailed below.
A line-F opcode is defined when bits 15-12 of the opword are 0b1111. This exception is generated when
attempting to execute an undefined line-F opcode.
7.3.3.8
Debug Interrupt
See Chapter 29, “Version 1 ColdFire Debug (CF1_DEBUG),” for a detailed explanation of this exception,
which is generated in response to a hardware breakpoint register trigger. The processor does not generate
an IACK cycle, but rather calculates the vector number internally (vector number 12). Additionally,
SR[M,I] are unaffected by the interrupt.
7.3.3.9
RTE and Format Error Exception
The default operation of the V1 ColdFire processor is the generation of an illegal address reset event if an
RTE format error is detected. If CPUCR[ARD] is set, the reset is disabled and a processor exception is
generated as detailed below.
When an RTE instruction is executed, the processor first examines the 4-bit format field to validate the
frame type. For a ColdFire core, any attempted RTE execution (where the format is not equal to {4,5,6,7})
generates a format error. The exception stack frame for the format error is created without disturbing the
original RTE frame and the stacked PC pointing to the RTE instruction.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
7-17
ColdFire Core
The selection of the format value provides some limited debug support for porting code from M68000
applications. On M68000 family processors, the SR was located at the top of the stack. On those
processors, bit 30 of the longword addressed by the system stack pointer is typically zero. Thus, if an RTE
is attempted using this old format, it generates a format error on a ColdFire processor.
If the format field defines a valid type, the processor: (1) reloads the SR operand, (2) fetches the second
longword operand, (3) adjusts the stack pointer by adding the format value to the auto-incremented address
after the fetch of the first longword, and then (4) transfers control to the instruction address defined by the
second longword operand within the stack frame.
7.3.3.10
TRAP Instruction Exception
The TRAP #n instruction always forces an exception as part of its execution and is useful for implementing
system calls. The TRAP instruction may be used to change from user to supervisor mode.
This set of 16 instructions provides a similar but expanded functionality compared to the S08’s SWI
(software interrupt) instruction. Do not confuse these instructions and their functionality with the
software-scheduled interrupt requests, which are handled like normal I/O interrupt requests by the
interrupt controller. The processing of the software-scheduled IRQs can be masked, based on the interrupt
priority level defined by the SR[I] field.
7.3.3.11
Unsupported Instruction Exception
If execution of a valid instruction is attempted but the required hardware is not present in the processor, an
unsupported instruction exception is generated. The instruction functionality can then be emulated in the
exception handler, if desired.
All ColdFire cores record the processor hardware configuration in the D0 register immediately after the
negation of RESET. See Section 7.3.3.14, “Reset Exception,” for details.
7.3.3.12
Interrupt Exception
Interrupt exception processing includes interrupt recognition and the fetch of the appropriate vector from
the interrupt controller using an IACK cycle or using the previously-supplied vector number, under control
of CPUCR[IAE]. See Chapter 10, “Interrupt Controller (CF1_INTC),” for details on the interrupt
controller.
7.3.3.13
Fault-on-Fault Halt
The default operation of the V1 ColdFire processor is the generation of an illegal address reset event if a
fault-on-fault halt condition is detected. If CPUCR[ARD] is set, the reset is disabled and the processor is
halted as detailed below.
If a ColdFire processor encounters any type of fault during the exception processing of another fault, the
processor immediately halts execution with the catastrophic fault-on-fault condition. A reset is required to
to exit this state.
MCF51MM256 Series Devices Reference Manual, Rev. 3
7-18
Freescale Semiconductor
ColdFire Core
7.3.3.14
Reset Exception
Asserting the reset input signal (RESET) to the processor causes a reset exception. The reset exception has
the highest priority of any exception; it provides for system initialization and recovery from catastrophic
failure. Reset also aborts any processing in progress when the reset input is recognized. Processing cannot
be recovered.
The reset exception places the processor in the supervisor mode by setting the SR[S] bit and disables
tracing by clearing the SR[T] bit. This exception also clears the SR[M] bit and sets the processor’s SR[I]
field to the highest level (level 7, 0b111). Next, the VBR is initialized to zero (0x0000_0000). The control
registers specifying the operation of any memories (e.g., cache and/or RAM modules) connected directly
to the processor are disabled.
NOTE
Other implementation-specific registers are also affected. Refer to each
module in this reference manual for details on these registers.
After the processor is granted the bus, it performs two longword read-bus cycles. The first longword at
address 0x(00)00_0000 is loaded into the supervisor stack pointer and the second longword at address
0x(00)00_0004 is loaded into the program counter. After the initial instruction is fetched from memory,
program execution begins at the address in the PC. If an access error or address error occurs before the first
instruction is executed, the processor enters the fault-on-fault state.
ColdFire processors load hardware configuration information into the D0 and D1 general-purpose
registers after system reset. The hardware configuration information is loaded immediately after the
reset-in signal is negated. This allows an emulator to read out the contents of these registers via the BDM
to determine the hardware configuration.
Information loaded into D0 defines the processor hardware configuration as shown in Figure 7-12.
BDM: Load: 0x60 (D0)
Store: 0x40 (D0)
31
30
Access: User read-only
BDM read-only
29
28
R
27
26
25
24
23
22
PF
21
20
19
18
VER
17
16
REV
W
Reset
1
15
R MAC
1
0
0
1
1
1
1
0
0
7
6
14
13
12
11
10
9
8
DIV
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
5
4
3
2
1
0
ISA
DEBUG
W
Reset
1
0
0
1
0
1
0
0
1
Figure 7-12. D0 Hardware Configuration Info
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
7-19
ColdFire Core
Table 7-10. D0 Hardware Configuration Info Field Description
Field
Description
31–24
PF
Processor family. This field is fixed to a hex value of 0xCF indicating a ColdFire core is present.
23–20
VER
ColdFire core version number. Defines the hardware microarchitecture version of ColdFire core.
0001 V1 ColdFire core (This is the value used for this device.)
0010 V2 ColdFire core
0011 V3 ColdFire core
0100 V4 ColdFire core
0101 V5 ColdFire core
Else Reserved for future use
19–16
REV
Processor revision number. The default is 0b0000.
15
MAC
MAC present. This bit signals if the optional multiply-accumulate (MAC) execution engine is present in processor core.
0 MAC execute engine not present in core.
1 MAC execute engine is present in core. (This is the value used for this device.)
14
DIV
Divide present. This bit signals if the hardware divider (DIV) is present in the processor core.
0 Divide execute engine not present in core. (This is the value used for this device.)
1 Divide execute engine is present in core.
13–8
Reserved.
7–4
ISA
ISA revision. Defines the instruction-set architecture (ISA) revision level implemented in ColdFire processor core.
0000 ISA_A
0001 ISA_B
0010 ISA_C (This is the value used for this device.)
1000 ISA_A+
Else Reserved
3–0
Debug module revision number. Defines revision level of the debug module used in the ColdFire processor core.
DEBUG 0000 DEBUG_A
0001 DEBUG_B
0010 DEBUG_C
0011 DEBUG_D
0100 DEBUG_E
1001 DEBUG_B+ (This is the value used for this device.)
1011 DEBUG_D+
1111 DEBUG_D+PST Buffer
Else Reserved
MCF51MM256 Series Devices Reference Manual, Rev. 3
7-20
Freescale Semiconductor
ColdFire Core
Information loaded into D1 defines the local memory hardware configuration as shown in the figure below.
BDM: Load: 0x61 (D1)
Store: 0x41 (D1)
31
R
30
Access: User read-only
BDM read-only
29
28
27
26
25
24
23
22
21
20
19
1
FLASHSZ
18
17
16
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
1
0
1
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
W
Reset
R
ROMSZ
SRAMSZ
W
Reset
1
0
1
0
1
0
1
1
1
0
The FLASHSZ size depends on memory size. The size shown is for 256 KB flash.
Figure 7-13. D1 Hardware Configuration Info
Table 7-11. D1 Hardware Configuration Information Field Description
Field
31–24
23–19
FLASHSZ
Description
Reserved.
Flash bank size.
00000-01110 No flash
10000 64 KB flash
10010 128 KB flash
10011 96 KB flash
10100 256 KB flash (This is the value used for this device)
10110 512 KB flash
Else Reserved for future use
Note: The FLASHSZ size depends on memory size. The size shown is for 256 KB flash.
18–16
Reserved
15–12
Reserved, resets to 0b0001
11–8
ROMSZ
Boot ROM size. Indicates the size of the boot ROM.
0000 No boot ROM
0001 512 bytes
0010 1 KB
0011 2 KB
0100 4 KB
0101 8 KB (This is the value used for this device)
0110 16 KB
0111 32 KB
Else Reserved for future use
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
7-21
ColdFire Core
Table 7-11. D1 Hardware Configuration Information Field Description (Continued)
Field
7–3
SRAMSZ
2–0
7.3.4
Description
SRAM bank size.
00000 No SRAM
00010 512 bytes
00100 1 KB
00110 2 KB
01000 4 KB
01010 8 KB
01100 16 KB
01111 24 KB
01110 32 KB (This is the value used for this device)
10000 64 KB
10010 128 KB
Else Reserved for future use
Reserved.
Instruction Execution Timing
This section presents processor instruction execution times in terms of processor-core clock cycles. The
number of operand references for each instruction is enclosed in parentheses following the number of
processor clock cycles. Each timing entry is presented as C(R/W) where:
• C is the number of processor clock cycles, including all applicable operand fetches and writes, and
all internal core cycles required to complete the instruction execution.
• R/W is the number of operand reads (R) and writes (W) required by the instruction. An operation
performing a read-modify-write function is denoted as (1/1).
This section includes the assumptions concerning the timing values and the execution time details.
7.3.4.1
Timing Assumptions
For the timing data presented in this section, these assumptions apply:
1. The OEP is loaded with the opword and all required extension words at the beginning of each
instruction execution. This implies that the OEP does not wait for the IFP to supply opwords and/or
extension words.
2. The OEP does not experience any sequence-related pipeline stalls. The most common example of
stall involves consecutive store operations, excluding the MOVEM instruction. For all STORE
operations (except MOVEM), certain hardware resources within the processor are marked as busy
for two clock cycles after the final decode and select/operand fetch cycle (DSOC) of the store
instruction. If a subsequent STORE instruction is encountered within this 2-cycle window, it is
stalled until the resource again becomes available. Thus, the maximum pipeline stall involving
consecutive STORE operations is two cycles. The MOVEM instruction uses a different set of
resources and this stall does not apply.
3. The OEP completes all memory accesses without any stall conditions caused by the memory itself.
Thus, the timing details provided in this section assume that an infinite zero-wait state memory is
attached to the processor core.
MCF51MM256 Series Devices Reference Manual, Rev. 3
7-22
Freescale Semiconductor
ColdFire Core
4. All operand data accesses are aligned on the same byte boundary as the operand size; for example,
16-bit operands aligned on 0-modulo-2 addresses, 32-bit operands aligned on 0-modulo-4
addresses.
The processor core decomposes misaligned operand references into a series of aligned accesses as
shown in Table 7-12.
Table 7-12. Misaligned Operand References
7.3.4.2
address[1:0]
Size
Bus
Operations
Additional
C(R/W)
01 or 11
Word
Byte, Byte
2(1/0) if read
1(0/1) if write
01 or 11
Long
Byte, Word,
Byte
3(2/0) if read
2(0/2) if write
10
Long
Word, Word
2(1/0) if read
1(0/1) if write
MOVE Instruction Execution Times
Table 7-13 lists execution times for MOVE.{B,W} instructions; Table 7-14 lists timings for MOVE.L.
NOTE
For all tables in this section, the execution time of any instruction using the
PC-relative effective addressing modes is the same for the comparable
An-relative mode.
ET with {<ea> = (d16,PC)}
equals ET with {<ea> = (d16,An)}
ET with {<ea> = (d8,PC,Xi*SF)}
equals ET with {<ea> = (d8,An,Xi*SF)}
The nomenclature xxx.wl refers to both forms of absolute addressing, xxx.w
and xxx.l.
Table 7-13. MOVE Byte and Word Execution Times
Destination
Source
Rx
(Ax)
(Ax)+
-(Ax)
(d16,Ax)
(d8,Ax,Xi*SF)
xxx.wl
Dy
1(0/0)
1(0/1)
1(0/1)
1(0/1)
1(0/1)
2(0/1)
1(0/1)
Ay
1(0/0)
1(0/1)
1(0/1)
1(0/1)
1(0/1)
2(0/1)
1(0/1)
(Ay)
2(1/0)
3(1/1)
3(1/1)
3(1/1)
3(1/1)
4(1/1))
3(1/1)
(Ay)+
2(1/0)
3(1/1)
3(1/1)
3(1/1)
3(1/1)
4(1/1))
3(1/1)
-(Ay)
2(1/0)
3(1/1)
3(1/1)
3(1/1)
3(1/1)
4(1/1))
3(1/1)
(d16,Ay)
2(1/0)
3(1/1)
3(1/1)
3(1/1)
3(1/1)
—
—
(d8,Ay,Xi*SF)
3(1/0)
4(1/1)
4(1/1)
4(1/1)
—
—
—
xxx.w
2(1/0)
3(1/1)
3(1/1)
3(1/1)
—
—
—
xxx.l
2(1/0)
3(1/1)
3(1/1)
3(1/1)
—
—
—
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
7-23
ColdFire Core
Table 7-13. MOVE Byte and Word Execution Times (Continued)
Destination
Source
Rx
(Ax)
(Ax)+
-(Ax)
(d16,Ax)
(d8,Ax,Xi*SF)
xxx.wl
(d16,PC)
2(1/0)
3(1/1)
3(1/1)
3(1/1)
3(1/1)
—
—
(d8,PC,Xi*SF)
3(1/0)
4(1/1)
4(1/1)
4(1/1))
—
—
—
#xxx
1(0/0)
3(0/1)
3(0/1)
3(0/1)
1(0/1)
—
—
Table 7-14. MOVE Long Execution Times
Destination
Source
Rx
(Ax)
(Ax)+
-(Ax)
(d16,Ax)
(d8,Ax,Xi*SF)
xxx.wl
Dy
1(0/0)
1(0/1)
1(0/1)
1(0/1)
1(0/1)
2(0/1)
1(0/1)
Ay
1(0/0)
1(0/1)
1(0/1)
1(0/1)
1(0/1)
2(0/1)
1(0/1)
(Ay)
2(1/0)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
3(1/1)
2(1/1)
(Ay)+
2(1/0)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
3(1/1)
2(1/1)
-(Ay)
2(1/0)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
3(1/1)
2(1/1)
(d16,Ay)
2(1/0)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
—
—
(d8,Ay,Xi*SF)
3(1/0)
3(1/1)
3(1/1)
3(1/1)
—
—
—
xxx.w
2(1/0)
2(1/1)
2(1/1)
2(1/1)
—
—
—
xxx.l
2(1/0)
2(1/1)
2(1/1)
2(1/1)
—
—
—
(d16,PC)
2(1/0)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
—
—
(d8,PC,Xi*SF)
3(1/0)
3(1/1)
3(1/1)
3(1/1)
—
—
—
#xxx
1(0/0)
2(0/1)
2(0/1)
2(0/1)
—
—
—
7.3.4.3
Standard One Operand Instruction Execution Times
Table 7-15. One Operand Instruction Execution Times
Effective Address
Opcode
<EA>
Rn
(An)
(An)+
-(An)
(d16,An)
(d8,An,Xn*SF)
xxx.wl
#xxx
BITREV
Dx
1(0/0)
—
—
—
—
—
—
—
BYTEREV
Dx
1(0/0)
—
—
—
—
—
—
—
CLR.B
<ea>
1(0/0)
1(0/1)
1(0/1)
1(0/1)
1(0/1)
2(0/1)
1(0/1)
—
CLR.W
<ea>
1(0/0)
1(0/1)
1(0/1)
1(0/1)
1(0/1)
2(0/1)
1(0/1)
—
CLR.L
<ea>
1(0/0)
1(0/1)
1(0/1)
1(0/1)
1(0/1)
2(0/1)
1(0/1)
—
EXT.W
Dx
1(0/0)
—
—
—
—
—
—
—
EXT.L
Dx
1(0/0)
—
—
—
—
—
—
—
EXTB.L
Dx
1(0/0)
—
—
—
—
—
—
—
MCF51MM256 Series Devices Reference Manual, Rev. 3
7-24
Freescale Semiconductor
ColdFire Core
Table 7-15. One Operand Instruction Execution Times (Continued)
Effective Address
Opcode
<EA>
Rn
(An)
(An)+
-(An)
(d16,An)
(d8,An,Xn*SF)
xxx.wl
#xxx
FF1
Dx
1(0/0)
—
—
—
—
—
—
—
NEG.L
Dx
1(0/0)
—
—
—
—
—
—
—
NEGX.L
Dx
1(0/0)
—
—
—
—
—
—
—
NOT.L
Dx
1(0/0)
—
—
—
—
—
—
—
SATS.L
Dx
1(0/0)
—
—
—
—
—
—
—
SCC
Dx
1(0/0)
—
—
—
—
—
—
—
SWAP
Dx
1(0/0)
—
—
—
—
—
—
—
TAS.B
<ea>
—
3(1/1)
3(1/1)
3(1/1)
3(1/1)
4(1/1)
3(1/1)
—
TST.B
<ea>
1(0/0)
2(1/0)
2(1/0)
2(1/0)
2(1/0)
3(1/0)
2(1/0)
1(0/0)
TST.W
<ea>
1(0/0)
2(1/0)
2(1/0)
2(1/0)
2(1/0)
3(1/0)
2(1/0)
1(0/0)
TST.L
<ea>
1(0/0)
2(1/0)
2(1/0)
2(1/0)
2(1/0)
3(1/0)
2(1/0)
1(0/0)
7.3.4.4
Standard Two Operand Instruction Execution Times
Table 7-16. Two Operand Instruction Execution Times
Effective Address
Opcode
<EA>
Rn
(An)
(An)+
-(An)
(d16,An) (d8,An,Xn*SF)
(d16,PC) (d8,PC,Xn*SF)
xxx.wl
#xxx
ADD.L
<ea>,Rx
1(0/0)
3(1/0)
3(1/0)
3(1/0)
3(1/0)
4(1/0)
3(1/0)
1(0/0)
ADD.L
Dy,<ea>
—
3(1/1)
3(1/1)
3(1/1)
3(1/1)
4(1/1)
3(1/1)
—
ADDI.L
#imm,Dx
1(0/0)
—
—
—
—
—
—
—
ADDQ.L
#imm,<ea>
1(0/0)
3(1/1)
3(1/1)
3(1/1)
3(1/1)
4(1/1)
3(1/1)
—
ADDX.L
Dy,Dx
1(0/0)
—
—
—
—
—
—
—
AND.L
<ea>,Rx
1(0/0)
3(1/0)
3(1/0)
3(1/0)
3(1/0)
4(1/0)
3(1/0)
1(0/0)
AND.L
Dy,<ea>
—
3(1/1)
3(1/1)
3(1/1)
3(1/1)
4(1/1)
3(1/1)
—
ANDI.L
#imm,Dx
1(0/0)
—
—
—
—
—
—
—
ASL.L
<ea>,Dx
1(0/0)
—
—
—
—
—
—
1(0/0)
ASR.L
<ea>,Dx
1(0/0)
—
—
—
—
—
—
1(0/0)
BCHG
Dy,<ea>
2(0/0)
4(1/1)
4(1/1)
4(1/1)
4(1/1)
5(1/1)
4(1/1)
—
BCHG
#imm,<ea>
2(0/0)
4(1/1)
4(1/1)
4(1/1)
4(1/1)
—
—
—
BCLR
Dy,<ea>
2(0/0)
4(1/1)
4(1/1)
4(1/1)
4(1/1)
5(1/1)
4(1/1)
—
BCLR
#imm,<ea>
2(0/0)
4(1/1)
4(1/1)
4(1/1)
4(1/1)
—
—
—
BSET
Dy,<ea>
2(0/0)
4(1/1)
4(1/1)
4(1/1)
4(1/1)
5(1/1)
4(1/1)
—
BSET
#imm,<ea>
2(0/0)
4(1/1)
4(1/1)
4(1/1)
4(1/1)
—
—
—
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
7-25
ColdFire Core
Table 7-16. Two Operand Instruction Execution Times (Continued)
Effective Address
Opcode
<EA>
Rn
(An)
(An)+
-(An)
(d16,An) (d8,An,Xn*SF)
(d16,PC) (d8,PC,Xn*SF)
xxx.wl
#xxx
BTST
Dy,<ea>
2(0/0)
3(1/0)
3(1/0)
3(1/0)
3(1/0)
4(1/0)
3(1/0)
—
BTST
#imm,<ea>
1(0/0)
3(1/0)
3(1/0)
3(1/0)
3(1/0)
—
—
—
CMP.B
<ea>,Rx
1(0/0)
3(1/0)
3(1/0)
3(1/0)
3(1/0)
4(1/0)
3(1/0)
1(0/0)
CMP.W
<ea>,Rx
1(0/0)
3(1/0)
3(1/0)
3(1/0)
3(1/0)
4(1/0)
3(1/0)
1(0/0)
CMP.L
<ea>,Rx
1(0/0)
3(1/0)
3(1/0)
3(1/0)
3(1/0)
4(1/0)
3(1/0)
1(0/0)
CMPI.B
#imm,Dx
1(0/0)
—
—
—
—
—
—
—
CMPI.W
#imm,Dx
1(0/0)
—
—
—
—
—
—
—
CMPI.L
#imm,Dx
1(0/0)
—
—
—
—
—
—
—
EOR.L
Dy,<ea>
1(0/0)
3(1/1)
3(1/1)
3(1/1)
3(1/1)
4(1/1)
3(1/1)
—
EORI.L
#imm,Dx
1(0/0)
—
—
—
—
—
—
—
LEA
<ea>,Ax
—
1(0/0)
—
—
1(0/0)
2(0/0)
1(0/0)
—
LSL.L
<ea>,Dx
1(0/0)
—
—
—
—
—
—
1(0/0)
LSR.L
<ea>,Dx
1(0/0)
—
—
—
—
—
—
1(0/0)
MOVEQ.L
#imm,Dx
—
—
—
—
—
—
—
1(0/0)
OR.L
<ea>,Rx
1(0/0)
3(1/0)
3(1/0)
3(1/0)
3(1/0)
4(1/0)
3(1/0)
1(0/0)
OR.L
Dy,<ea>
—
3(1/1)
3(1/1)
3(1/1)
3(1/1)
4(1/1)
3(1/1)
—
ORI.L
#imm,Dx
1(0/0)
—
—
—
—
—
—
—
SUB.L
<ea>,Rx
1(0/0)
3(1/0)
3(1/0)
3(1/0)
3(1/0)
4(1/0)
3(1/0)
1(0/0)
SUB.L
Dy,<ea>
—
3(1/1)
3(1/1)
3(1/1)
3(1/1)
4(1/1)
3(1/1)
—
SUBI.L
#imm,Dx
1(0/0)
—
—
—
—
—
—
—
SUBQ.L
#imm,<ea>
1(0/0)
3(1/1)
3(1/1)
3(1/1)
3(1/1)
4(1/1)
3(1/1)
—
SUBX.L
Dy,Dx
1(0/0)
—
—
—
—
—
—
—
7.3.4.5
Miscellaneous Instruction Execution Times
Table 7-17. Miscellaneous Instruction Execution Times
Effective Address
Opcode
LINK.W
<EA>
Ay,#imm
MOV3Q.L #imm,<ea>
Rn
(An)
(An)+
-(An)
(d16,An)
(d8,An,Xn*SF)
xxx.wl
#xxx
2(0/1)
—
—
—
—
—
—
—
1(0/0)
1(0/1)
1(0/1)
1(0/1)
1(0/1)
2(0/1)
1(0/1)
—
MOVE.L
Ay,USP
3(0/0)
—
—
—
—
—
—
—
MOVE.L
USP,Ax
3(0/0)
—
—
—
—
—
—
—
MOVE.W
CCR,Dx
1(0/0)
—
—
—
—
—
—
—
MOVE.W
<ea>,CCR
1(0/0)
—
—
—
—
—
—
1(0/0)
MOVE.W
SR,Dx
1(0/0)
—
—
—
—
—
—
—
MCF51MM256 Series Devices Reference Manual, Rev. 3
7-26
Freescale Semiconductor
ColdFire Core
Table 7-17. Miscellaneous Instruction Execution Times (Continued)
Effective Address
Opcode
<EA>
Rn
(An)
(An)+
-(An)
(d16,An)
(d8,An,Xn*SF)
xxx.wl
#xxx
MOVE.W
<ea>,SR
7(0/0)
—
—
—
—
—
—
7(0/0) 2
MOVEC
Ry,Rc
9(0/1)
—
—
—
—
—
—
—
MOVEM.L
<ea>,and
list
—
1+n(n/0)
—
—
1+n(n/0)
—
—
—
MOVEM.L
and
list,<ea>
—
1+n(0/n)
—
—
1+n(0/n)
—
—
—
MVS
<ea>,Dx
1(0/0)
2(1/0)
2(1/0)
2(1/0)
2(1/0)
3(1/0)
2(1/0)
1(0/0)
MVZ
<ea>,Dx
1(0/0)
2(1/0)
2(1/0)
2(1/0)
2(1/0)
3(1/0)
2(1/0)
1(0/0)
3(0/0)
—
—
—
—
—
—
—
2(0/1)
—
NOP
PEA
<ea>
PULSE
2(0/1)
4
5
—
2(0/1)
—
—
1(0/0)
—
—
—
—
—
—
—
3(0/1)
STLDSR
#imm
—
—
—
—
—
—
—
5(0/1)
STOP
#imm
—
—
—
—
—
—
—
3(0/0) 3
TRAP
#imm
—
—
—
—
—
—
—
12(1/2)
TPF
1(0/0)
—
—
—
—
—
—
—
TPF.W
1(0/0)
—
—
—
—
—
—
—
TPF.L
1(0/0)
—
—
—
—
—
—
—
UNLK
Ax
2(1/0)
—
—
—
—
—
—
—
WDDATA
<ea>
—
3(1/0)
3(1/0)
3(1/0)
3(1/0)
4(1/0)
3(1/0)
—
WDEBUG
<ea>
—
5(2/0)
—
—
5(2/0)
—
—
—
1The
n is the number of registers moved by the MOVEM opcode.
a MOVE.W #imm,SR instruction is executed and imm[13] equals 1, the execution time is 1(0/0).
3The execution time for STOP is the time required until the processor begins sampling continuously for interrupts.
4PEA execution times are the same for (d16,PC).
5PEA execution times are the same for (d8,PC,Xn*SF).
2If
7.3.4.6
MAC Instruction Execution Times
Table 7-18. MAC Instruction Execution Times
Effective Address
Opcode
<EA>
Rn
(An)
(An)+
-(An)
(d16,An)
(d8,An,
xxx.wl
Xn*SF)
#xxx
MAC.L
Ry, Rx
3(0/0)
—
—
—
—
—
—
—
MAC.L
Ry, Rx, <ea>, Rw
—
(1/0)
(1/0)
(1/0)
(1/0)1
—
—
—
MAC.W
Ry, Rx
1(0/0)
—
—
—
—
—
—
—
MAC.W
Ry, Rx, <ea>, Rw
—
(1/0)
(1/0)
(1/0)
(1/0)1
—
—
—
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
7-27
ColdFire Core
Table 7-18. MAC Instruction Execution Times (Continued)
Effective Address
Opcode
<EA>
Rn
(An)
(An)+
-(An)
(d16,An)
(d8,An,
xxx.wl
Xn*SF)
#xxx
MOVE.L
<ea>y, Racc
1(0/0)
—
—
—
—
—
—
1(0/0)
MOVE.L
<ea>y, MACSR
2(0/0)
—
—
—
—
—
—
2(0/0)
MOVE.L
<ea>y, Rmask
1(0/0)
—
—
—
—
—
—
1(0/0)
2
MOVE.L
Racc,<ea>x
1(0/0)
—
—
—
—
—
—
—
MOVE.L
MACSR,<ea>x
1(0/0)
—
—
—
—
—
—
—
MOVE.L
Rmask, <ea>x
1(0/0)
—
—
—
—
—
—
—
MSAC.L
Ry, Rx
3(0/0)
—
—
—
—
—
—
—
MSAC.W
Ry, Rx
1(0/0)
—
—
—
—
—
—
—
MSAC.L
Ry, Rx, <ea>, Rw
—
(1/0)
(1/0)
(1/0)
(1/0)1
—
—
—
—
—
—
MSAC.W
Ry, Rx, <ea>, Rw
—
(1/0)
(1/0)
(1/0)
(1/0)1
MULS.L
<ea>y, Dx
5(0/0)
(1/0)
(1/0)
(1/0)
(1/0)
—
—
—
MULS.W
<ea>y, Dx
3(0/0)
(1/0)
(1/0)
(1/0)
(1/0)
(1/0)
(1/0)
3(0/0)
MULU.L
<ea>y, Dx
5(0/0)
(1/0)
(1/0)
(1/0)
(1/0)
—
—
—
MULU.W
<ea>y, Dx
3(0/0)
(1/0)
(1/0)
(1/0)
(1/0)
(1/0)
(1/0)
3(0/0)
1
2
Effective address of (d16,PC) not supported
Storing the accumulator requires one additional processor clock cycle when rounding is performed
7.3.4.7
Branch Instruction Execution Times
Table 7-19. General Branch Instruction Execution Times
Effective Address
Opcode
<EA>
Rn
(An)
(An)+
-(An)
(d16,An)
(d16,PC)
(d8,An,Xi*SF)
(d8,PC,Xi*SF)
xxx.wl
#xxx
BRA
—
—
—
—
2(0/1)
—
—
—
BSR
—
—
—
—
3(0/1)
—
—
—
JMP
<ea>
—
3(0/0)
—
—
3(0/0)
4(0/0)
3(0/0)
—
JSR
<ea>
—
3(0/1)
—
—
3(0/1)
4(0/1)
3(0/1)
—
RTE
—
—
7(2/0)
—
—
—
—
—
RTS
—
—
5(1/0)
—
—
—
—
—
MCF51MM256 Series Devices Reference Manual, Rev. 3
7-28
Freescale Semiconductor
ColdFire Core
Table 7-20. Bcc Instruction Execution Times
Opcode
Forward
Taken
Forward
Not Taken
Backward
Taken
Backward
Not Taken
Bcc
3(0/0)
1(0/0)
2(0/0)
3(0/0)
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
7-29
ColdFire Core
MCF51MM256 Series Devices Reference Manual, Rev. 3
7-30
Freescale Semiconductor
Chapter 8
Multiply-Accumulate Unit (MAC)
8.1
Introduction
This chapter describes the functionality, microarchitecture, and performance of the multiply-accumulate
(MAC) unit in the ColdFire family of processors.
8.1.1
Overview
The MAC design provides a set of DSP operations that can improve the performance of embedded code
while supporting the integer multiply instructions of the baseline ColdFire architecture.
The MAC provides functionality in three related areas:
1. Signed and unsigned integer multiplication
2. Multiply-accumulate operations supporting signed and unsigned integer operands as well as
signed, fixed-point, and fractional operands
3. Miscellaneous register operations
The MAC features a three-stage execution pipeline optimized for 16-bit operands, with a 16x16 multiply
array and a single 32-bit accumulator.
The three areas of functionality are addressed in detail in following sections. The logic required to support
this functionality is contained in a MAC module (Figure 8-1).
Operand Y
Operand X
X
Shift 0,1,-1
+/-
Accumulator(s)
Figure 8-1. Multiply-Accumulate Functionality Diagram
8.1.1.1
Introduction to the MAC
The MAC is an extension of the basic multiplier in most microprocessors. It is typically implemented in
hardware within an architecture and supports rapid execution of signal processing algorithms in fewer
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
8-1
Multiply-Accumulate Unit (MAC)
cycles than comparable non-MAC architectures. For example, small digital filters can tolerate some
variance in an algorithm’s execution time, but larger, more complicated algorithms such as orthogonal
transforms may have more demanding speed requirements beyond scope of any processor architecture and
may require full DSP implementation.
To balance speed, size, and functionality, the ColdFire MAC is optimized for a small set of operations that
involve multiplication and cumulative additions. Specifically, the multiplier array is optimized for
single-cycle pipelined operations with a possible accumulation after product generation. This functionality
is common in many signal processing applications. The ColdFire core architecture is also modified to
allow an operand to be fetched in parallel with a multiply, increasing overall performance for certain DSP
operations.
Consider a typical filtering operation where the filter is defined as in Equation 8-1.
N–1
yi =
N–1
 a  k y  i – k  +  b  k x  i – k 
k=1
Eqn. 8-1
k=0
Here, the output y(i) is determined by past output values and past input values. This is the general form of
an infinite impulse response (IIR) filter. A finite impulse response (FIR) filter can be obtained by setting
coefficients a(k) to zero. In either case, the operations involved in computing such a filter are multiplies
and product summing. To show this point, reduce Equation 8-1 to a simple, four-tap FIR filter, shown in
Equation 8-2, in which the accumulated sum is a past data values and coefficients sum.
3
yi =
 b  k x  i – k  = b  0 x  i  + b  1 x  i – 1  + b  2 x  i – 2  + b  3 x  i – 3 
Eqn. 8-2
k=0
8.2
Memory Map/Register Definition
The following table and sections explain the MAC registers:
Table 8-1. MAC Memory Map
BDM1
Register
Width
(bits)
Access
Reset Value
Section/Page
Read: 0xE4
Write: 0xC4
MAC Status Register (MACSR)
8
R/W
0x00
8.2.1/8-2
Read: 0xE5
Write: 0xC5
MAC Address Mask Register (MASK)
16
R/W
0xFFFF
8.2.2/8-4
Read: 0xE6
Write: 0xC6
Accumulator (ACC)
32
R/W
Undefined
8.2.3/8-5
1
For more information see Chapter 29, “Version 1 ColdFire Debug (CF1_DEBUG).”
8.2.1
MAC Status Register (MACSR)
The MAC status register (MACSR) contains a 4-bit operational mode field and condition flags.
Operational mode bits control whether operands are signed or unsigned and whether they are treated as
integers or fractions. These bits also control the overflow/saturation mode and the way in which rounding
is performed. Negative, zero, and overflow condition flags are also provided.
MCF51MM256 Series Devices Reference Manual, Rev. 3
8-2
Freescale Semiconductor
Multiply-Accumulate Unit (MAC)
BDM: Read: 0xE4 (MACSR)
Write: 0xC4
Access: Supervisor read/write
BDM read/write
7
6
5
4
3
2
1
0
OMC
S/U
F/I
R/T
N
Z
V
C
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 8-2. MAC Status Register (MACSR)
Table 8-2. MACSR Field Descriptions
Field
Description
7
OMC
Overflow saturation mode. Enables or disables saturation mode on overflow. If set, the accumulator is set
to the appropriate constant (see S/U field description) on any operation that overflows the accumulator.
After saturation, the accumulator remains unaffected by any other MAC or MSAC instructions until the
overflow bit is cleared or the accumulator is directly loaded.
6
S/U
Signed/unsigned operations.
In integer mode:
S/U determines whether operations performed are signed or unsigned. It also determines the accumulator
value during saturation, if enabled.
0 Signed numbers. On overflow, if OMC is enabled, the accumulator saturates to the most positive
(0x7FFF_FFFF) or the most negative (0x8000_0000) number, depending on the instruction and the
product value that overflowed.
1 Unsigned numbers. On overflow, if OMC is enabled, the accumulator saturates to the smallest value
(0x0000_0000) or the largest value (0xFFFF_FFFF), depending on the instruction.
In fractional mode:
S/U controls rounding while storing the accumulator to a general-purpose register.
0 Move accumulator without rounding to a 16-bit value. Accumulator is moved to a general-purpose
register as a 32-bit value.
1 The accumulator is rounded to a 16-bit value using the round-to-nearest (even) method when moved to
a general-purpose register. See Section 8.3.1.1, “Rounding”. The resulting 16-bit value is stored in the
lower word of the destination register. The upper word is zero-filled. This rounding procedure does not
affect the accumulator value.
5
F/I
Fractional/integer mode. Determines whether input operands are treated as fractions or integers.
0 Integers can be represented in signed or unsigned notation, depending on the value of S/U.
1 Fractions are represented in signed, fixed-point, two’s complement notation. Values range from -1 to
1 - 2-15 for 16-bit fractions and -1 to 1 - 2-31 for 32-bit fractions. See Section 8.3.4, “Data
Representation."
4
R/T
Round/truncate mode. Controls rounding procedure for MSAC.L instructions when in fractional mode.
0 Truncate. The product’s lsbs are dropped before it is combined with the accumulator.
1 Round-to-nearest (even). The 64-bit product of two 32-bit, fractional operands is rounded to the nearest
32-bit value. If the low-order 32 bits equal 0x8000_0000, the upper 32 bits are rounded to the nearest
even (lsb = 0) value. See Section 8.3.1.1, “Rounding”.
3
N
Negative. Set if the msb of the result is set, otherwise cleared. N is affected only by MAC, MSAC, and load
operations; it is not affected by MULS and MULU instructions.
2
Z
Zero. Set if the result equals zero, otherwise cleared. This bit is affected only by MAC, MSAC, and load
operations; it is not affected by MULS and MULU instructions.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
8-3
Multiply-Accumulate Unit (MAC)
Table 8-2. MACSR Field Descriptions (Continued)
Field
Description
1
V
Overflow. Set if an arithmetic overflow occurs, implying that the result cannot be represented in the operand
size. After set, V remains set until the accumulator register is loaded with a new value or MACSR is directly
loaded. MULS and MULU instructions do not change this value.
0
Carry. This field is always zero.
Table 8-3 summarizes the interaction of the MACSR[S/U,F/I,R/T] control bits.
Table 8-3. Summary of S/U, F/I, and R/T Control Bits
8.2.2
S/U
F/I
R/T
Operational Modes
0
0
x
Signed, integer
0
1
0
Signed, fractional
Truncate on MAC.L and MSAC.L
No round on accumulator stores
0
1
1
Signed, fractional
Round on MAC.L and MSAC.L
No round on accumulator stores
1
0
x
Unsigned, integer
1
1
0
Signed, fractional
Truncate on MAC.L and MSAC.L
Round-to-16-bits on accumulator stores
1
1
1
Signed, fractional
Round on MAC.L and MSAC.L
Round-to-16-bits on accumulator stores
Mask Register (MASK)
The MASK register performs a simple AND with the operand address for MAC instructions. The
processor calculates the normal operand address and, if enabled, that address is then ANDed with
{0xFFFF, MASK[15:0]} to form the final address. Therefore, with certain MASK bits cleared, the operand
address can be constrained to a certain memory region. This is used primarily to implement circular queues
with the (An)+ addressing mode.
This minimizes the addressing support required for filtering, convolution, or any routine that implements
a data array as a circular queue. For MAC + MOVE operations, the MASK contents can optionally be
included in all memory effective address calculations. The syntax is as follows:
mac.sz
Ry,RxSF,<ea>y&,Rw
The & operator enables the MASK use and causes bit 5 of the extension word to be set. The exact
algorithm for the use of MASK is:
MCF51MM256 Series Devices Reference Manual, Rev. 3
8-4
Freescale Semiconductor
Multiply-Accumulate Unit (MAC)
if extension word, bit [5] = 1, the MASK bit, then
if <ea> = (An)
oa = An & {0xFFFF, MASK}
if <ea> = (An)+
oa = An
An = (An + 4) & {0xFFFF, MASK}
if <ea> =-(An)
oa = (An - 4) & {0xFFFF, MASK}
An = (An - 4) & {0xFFFF, MASK}
if <ea> = (d16,An)
oa = (An + se_d16) & {0xFFFF0x, MASK}
Here, oa is the calculated operand address and se_d16 is a sign-extended 16-bit displacement. For
auto-addressing modes of post-increment and pre-decrement, the updated An value calculation is also
shown.
Use of the post-increment addressing mode, {(An)+} with the MASK is suggested for circular queue
implementations.
BDM: Read: 0xE5 (MASK)
Write: 0xC5
15
14
13
Access: User read/write
BDM read/write
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
R
MASK
W
Reset
1
1
1
1
1
1
1
1
1
Figure 8-3. Mask Register (MASK)
Table 8-4. MASK Field Descriptions
Field
Description
15–0
MASK
8.2.3
Performs a simple AND with the operand address for MAC instructions.
Accumulator Register (ACC)
The accumulator register store 32-bits of the MAC operation result.
BDM: Read: 0xE6 (ACC)
Write: 0xC6
Access: User read/write
BDM read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
8
7
6
5
4
3
2
1
0
Accumulator
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
Figure 8-4. Accumulator Register (ACC)
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
8-5
Multiply-Accumulate Unit (MAC)
Table 8-5. ACC Field Descriptions
Field
31–0
Accumulator
8.3
Description
Store 32-bits of the result of the MAC operation.
Functional Description
The MAC speeds execution of ColdFire integer-multiply instructions (MULS and MULU) and provides
additional functionality for multiply-accumulate operations. By executing MULS and MULU in the MAC,
execution times are minimized and deterministic compared to the 2-bit/cycle algorithm with early
termination that the OEP normally uses if no MAC hardware is present.
The added MAC instructions to the ColdFire ISA provide for the multiplication of two numbers, followed
by the addition or subtraction of the product to or from the value in the accumulator. Optionally, the
product may be shifted left or right by 1 bit before addition or subtraction. Hardware support for saturation
arithmetic can be enabled to minimize software overhead when dealing with potential overflow conditions.
Multiply-accumulate operations support 16- or 32-bit input operands in these formats:
• Signed integers
• Unsigned integers
• Signed, fixed-point, fractional numbers
The MAC is optimized for 16-bit multiplications to keep the area consumption low. Two 16-bit operands
produce a 32-bit product. Longword operations are performed by reusing the 16-bit multiplier array at the
expense of a small amount of extra control logic. Again, the product of two 32-bit operands is a 32-bit
result. For longword integer operations, only the least significant 32 bits of the product are calculated. For
fractional operations, the entire 64-bit product is calculated and then truncated or rounded to a 32-bit result
using the round-to-nearest (even) method.
Because the multiplier array is implemented in a three-stage pipeline, MAC instructions have an effective
issue rate of 1 cycle for word operations, 3 cycles for longword integer operations, and 4 cycles for 32-bit
fractional operations.
All arithmetic operations use register-based input operands, and summed values are stored in the
accumulator. Therefore, an additional MOVE instruction is needed to store data in a general-purpose
register.
The need to move large amounts of data presents an obstacle to obtaining high throughput rates in DSP
engines. Existing ColdFire instructions can accommodate these requirements. A MOVEM instruction can
efficiently move large data blocks. The ability to load an operand simultaneously from memory into a
register and execute a MAC instruction makes some DSP operations such as filtering and convolution
more manageable.
The programming model includes a mask register (MASK), which can optionally be used to generate an
operand address during MAC + MOVE instructions. The register application with auto-increment
addressing mode supports efficient implementation of circular data queues for memory operands.
MCF51MM256 Series Devices Reference Manual, Rev. 3
8-6
Freescale Semiconductor
Multiply-Accumulate Unit (MAC)
8.3.1
Fractional Operation Mode
This section describes behavior when the fractional mode is used (MACSR[F/I] is set).
8.3.1.1
Rounding
When the processor is in fractional mode, there are two operations during which rounding can occur:
1. The 32-bit accumulator is moved into a general purpose register. If MACSR[S/U] is cleared, the
accumulator is stored as is in the destination register; if it is set, the 32-bit value is rounded to a
16-bit value using the round-to-nearest (even) method. The resulting 16-bit number is stored in the
lower word of the destination register. The upper word is zero-filled. The accumulator value is
unaffected by this rounding procedure.
2. Execution of a MAC (or MSAC) instruction with 32-bit operands. If MACSR[R/T] is zero,
multiplying two 32-bit numbers creates a 64-bit product truncated to the upper 32 bits; otherwise,
it is rounded using round-to-nearest (even) method.
To understand the round-to-nearest-even method, consider the following example involving the rounding
of a 32-bit number, R0, to a 16-bit number. Using this method, the 32-bit number is rounded to the closest
16-bit number possible. Let the high-order 16 bits of R0 be named R0.U and the low-order 16 bits be R0.L.
• If R0.L is less than 0x8000, the result is truncated to the value of R0.U.
• If R0.L is greater than 0x8000, the upper word is incremented (rounded up).
• If R0.L is 0x8000, R0 is half-way between two 16-bit numbers. In this case, rounding is based on
the lsb of R0.U, so the result is always even (lsb = 0).
— If the lsb of R0.U equals 1 and R0.L equals 0x8000, the number is rounded up.
— If the lsb of R0.U equals 0 and R0.L equals 0x8000, the number is rounded down.
This method minimizes rounding bias and creates as statistically correct an answer as possible.
The rounding algorithm is summarized in the following pseudocode:
if R0.L < 0x8000
then Result = R0.U
else if R0.L > 0x8000
then Result = R0.U + 1
else if lsb of R0.U = 0
then Result = R0.U
else Result = R0.U + 1
/* R0.L = 0x8000 */
The round-to-nearest-even technique is also known as convergent rounding.
8.3.1.2
Saving and Restoring the MAC Programming Model
The presence of rounding logic in the MAC output datapath requires special care during the MAC’s
save/restore process. In particular, any result rounding modes must be disabled during the save/restore
process so the exact bit-wise contents of the MAC registers are accessed. Consider the memory structure
containing the MAC programming model:
struct
macState {
int acc;
int mask;
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
8-7
Multiply-Accumulate Unit (MAC)
int macsr;
} macState;
The following assembly language routine shows the proper sequence for a correct MAC state save. This
code assumes all Dn and An registers are available for use, and the memory location of the state save is
defined by A7.
MAC_state_save:
move.l
clr.l
move.l
move.l
move.l
movem.l
macsr,d7
d0
d0,macsr
acc,d5
mask,d6
#0x00e0,(a7)
;
;
;
;
;
;
save the macsr
zero the register to ...
disable rounding in the macsr
save the accumulator
save the address mask
move the state to memory
This code performs the MAC state restore:
MAC_state_restore:
movem.l (a7),#0x00e0; restore the state from memory
move.l #0,macsr
; disable rounding in the macsr
move.l d5,acc
; restore the accumulator
move.l d6,mask
; restore the address mask
move.l d7,macsr
; restore the macsr
Executing this sequence type can correctly save and restore the exact state of the MAC programming
model.
8.3.1.3
MULS/MULU
MULS and MULU are unaffected by fractional-mode operation; operands remain assumed to be integers.
8.3.1.4
Scale Factor in MAC or MSAC Instructions
The scale factor is ignored while the MAC is in fractional mode.
8.3.2
MAC Instruction Set Summary
Table 8-6 summarizes MAC unit instructions.
Table 8-6. MAC Instruction Summary
Command
Mnemonic
Description
Multiply Signed
muls <ea>y,Dx
Multiplies two signed operands yielding a signed result
Multiply Unsigned
mulu <ea>y,Dx
Multiplies two unsigned operands yielding an unsigned result
Multiply Accumulate
mac Ry,RxSF
msac Ry,RxSF
Multiplies two operands, then adds/subtracts the product
to/from the accumulator
Multiply Accumulate
with Load
mac Ry,RxSF,Rw
msac Ry,RxSF,Rw
Multiplies two operands, combines the product to the
accumulator while loading a register with the memory
operand
Load Accumulator
move.l {Ry,#imm},ACC
Loads the accumulator with a 32-bit operand
Store Accumulator
move.l ACC,Rx
Writes the contents of the accumulator to a CPU register
MCF51MM256 Series Devices Reference Manual, Rev. 3
8-8
Freescale Semiconductor
Multiply-Accumulate Unit (MAC)
Table 8-6. MAC Instruction Summary (Continued)
Command
Mnemonic
Description
Load MACSR
move.l {Ry,#imm},MACSR
Writes a value to MACSR
Store MACSR
move.l MACSR,Rx
Write the contents of MACSR to a CPU register
Store MACSR to CCR
move.l MACSR,CCR
Write the contents of MACSR to the CCR
Load MAC Mask Reg
move.l {Ry,#imm},MASK
Writes a value to the MASK register
Store MAC Mask Reg
move.l MASK,Rx
Writes the contents of the MASK to a CPU register
8.3.3
MAC Instruction Execution Times
The instruction execution times for the MAC can be found in Section 7.3.4.6, “MAC Instruction Execution
Times”.
8.3.4
Data Representation
MACSR[S/U,F/I] selects one of the following three modes, where each mode defines a unique operand
type:
1. Two’s complement signed integer: In this format, an N-bit operand value lies in the range -2(N-1)
< operand < 2(N-1) - 1. The binary point is right of the lsb.
2. Unsigned integer: In this format, an N-bit operand value lies in the range 0 < operand < 2N - 1. The
binary point is right of the lsb.
3. Two’s complement, signed fractional: In an N-bit number, the first bit is the sign bit. The remaining
bits signify the first N-1 bits after the binary point. Given an N-bit number, aN-1aN-2aN-3... a2a1a0,
its value is given by the equation in Equation 8-3.
N–2
value = –  1  a N – 1  +
2
– i + 1 – N 
 ai
Eqn. 8-3
i=0
This format can represent numbers in the range -1 < operand < 1 - 2(N-1).
For words and longwords, the largest negative number that can be represented is -1, whose internal
representation is 0x8000 and 0x8000_0000, respectively. The largest positive word is 0x7FFF or (1 - 2-15);
the most positive longword is 0x7FFF_FFFF or (1 - 2-31).
8.3.5
MAC Opcodes
MAC opcodes are described in the ColdFire Programmer’s Reference Manual.
Remember the following:
• Unless otherwise noted, the value of MACSR[N,Z] is based on the result of the final operation that
involves the product and the accumulator.
• The overflow (V) flag is managed differently. It is set if the complete product cannot be represented
as a 32-bit value (this applies to 32  32 integer operations only) or if the combination of the
product with the accumulator cannot be represented in the given number of bits. This indicator is
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
8-9
Multiply-Accumulate Unit (MAC)
•
treated as a sticky flag, meaning after set, it remains set until the accumulator or the MACSR is
directly loaded. See Section 8.2.1, “MAC Status Register (MACSR)”.
The optional 1-bit shift of the product is specified using the notation {<< | >>} SF, where <<1
indicates a left shift and >>1 indicates a right shift. The shift is performed before the product is
added to or subtracted from the accumulator. Without this operator, the product is not shifted. If the
MAC is in fractional mode (MACSR[F/I] is set), SF is ignored and no shift is performed. Because
a product can overflow, the following guidelines are implemented:
— For unsigned word and longword operations, a zero is shifted into the product on right shifts.
— For signed, word operations, the sign bit is shifted into the product on right shifts unless the
product is zero. For signed, longword operations, the sign bit is shifted into the product unless
an overflow occurs or the product is zero, in which case a zero is shifted in.
— For all left shifts, a zero is inserted into the lsb position.
The following pseudocode explains basic MAC or MSAC instruction functionality. This example is
presented as a case statement covering the three basic operating modes with signed integers, unsigned
integers, and signed fractionals. Throughout this example, a comma-separated list in curly brackets, {},
indicates a concatenation operation.
switch (MACSR[6:5])
/* MACSR[S/U, F/I] */
{
case 0:
/* signed integers */
if (MACSR.OMC == 0 || MACSR.V == 0)
then {
MACSR.V = 0
/* select the input operands */
if (sz == word)
then {if (U/Ly == 1)
then operandY[31:0] = {sign-extended
else operandY[31:0] = {sign-extended
if (U/Lx == 1)
then operandX[31:0] = {sign-extended
else operandX[31:0] = {sign-extended
}
else {operandY[31:0] = Ry[31:0]
operandX[31:0] = Rx[31:0]
}
Ry[31], Ry[31:16]}
Ry[15], Ry[15:0]}
Rx[31], Rx[31:16]}
Rx[15], Rx[15:0]}
/* perform the multiply */
product[63:0] = operandY[31:0] * operandX[31:0]
/* check for product overflow */
if ((product[63:31] != 0x0000_0000_0) && (product[63:31] != 0xffff_ffff_1))
then {
/* product overflow */
MACSR.V = 1
if (inst == MSAC && MACSR.OMC == 1)
then if (product[63] == 1)
then result[31:0] = 0x7fff_ffff
else result[31:0] = 0x8000_0000
else if (MACSR.OMC == 1)
then /* overflowed MAC,
saturationMode enabled */
if (product[63] == 1)
then result[31:0] = 0x8000_0000
MCF51MM256 Series Devices Reference Manual, Rev. 3
8-10
Freescale Semiconductor
Multiply-Accumulate Unit (MAC)
else result[31:0] = 0x7fff_ffff
}
/* scale product before combining with accumulator */
switch (SF)
/* 2-bit scale factor */
{
case 0:
/* no scaling specified */
break;
case 1:
/* SF = “<< 1” */
if (product[31] ^ product[30])
then {MACSR.V = 1
if (inst == MSAC && MACSR.OMC == 1)
then if (product[63] == 1)
then result[31:0] = 0x7fff_ffff
else result[31:0] = 0x8000_0000
else if (MACSR.OMC == 1)
then /* overflowed MAC,
saturationMode enabled */
if (product[63] == 1)
then result[31:0] = 0x8000_0000
else result[31:0] = 0x7fff_ffff
}
else product[31:0] = {product[30:0], 0}
break;
case 2:
/* reserved encoding */
break;
case 3:
/* SF = “>> 1” */
if (MACSR.OMC == 0 || MACSR.V = 0)
then product[31:0] = {product[31], product[31:1]}
break;
}
/* combine with accumulator */
if (MACSR.V == 0)
then {if (inst == MSAC)
then result[31:0] = acc[31:0] - product[31:0]
else result[31:0] = acc[31:0] + product[31:0]
}
/* check for accumulation overflow */
if (accumulationOverflow == 1)
then {MACSR.V = 1
if (MACSR.OMC == 1)
then /* accumulation overflow,
saturationMode enabled */
if (result[31] == 1)
then result[31:0] = 0x7fff_ffff
else result[31:0] = 0x8000_0000
}
/* transfer the result to the accumulator */
acc[31:0] = result[31:0]
MACSR.N = result[31]
if (result[31:0] == 0x0000_0000)
then MACSR.Z = 1
else MACSR.Z = 0
}
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
8-11
Multiply-Accumulate Unit (MAC)
break;
case 1:
case 3:
/* signed fractionals */
if (MACSR.OMC == 0 || MACSR.V == 0)
then {
MACSR.V = 0
if (sz == word)
then {if (U/Ly == 1)
then operandY[31:0] = {Ry[31:16],
else operandY[31:0] = {Ry[15:0],
if (U/Lx == 1)
then operandX[31:0] = {Rx[31:16],
else operandX[31:0] = {Rx[15:0],
}
else {operandY[31:0] = Ry[31:0]
operandX[31:0] = Rx[31:0]
}
0x0000}
0x0000}
0x0000}
0x0000}
/* perform the multiply */
product[63:0] = (operandY[31:0] * operandX[31:0]) << 1
/* check for product rounding */
if (MACSR.R/T == 1)
then { /* perform convergent rounding */
if (product[31:0] > 0x8000_0000)
then product[63:32] = product[63:32] + 1
else if ((product[31:0] == 0x8000_0000) && (product[32] == 1))
then product[63:32] = product[63:32] + 1
}
/* combine with accumulator */
if (inst == MSAC)
then result[31:0] = acc[31:0] - product[63:32]
else result[31:0] = acc[31:0] + product[63:32]
/* check for accumulation overflow */
if (accumulationOverflow == 1)
then {MACSR.V = 1
if (MACSR.OMC == 1)
then /* accumulation overflow,
saturationMode enabled */
if (result[31] == 1)
then result[31:0] = 0x7fff_ffff
else result[31:0] = 0x8000_0000
}
/* transfer the result to the accumulator */
acc[31:0] = result[31:0]
MACSR.N = result[31]
if (result[31:0] == 0x0000_0000)
then MACSR.Z = 1
else MACSR.Z = 0
}
break;
case 2:
/* unsigned integers */
MCF51MM256 Series Devices Reference Manual, Rev. 3
8-12
Freescale Semiconductor
Multiply-Accumulate Unit (MAC)
if (MACSR.OMC == 0 || MACSR.V == 0)
then {
MACSR.V = 0
/* select the input operands */
if (sz == word)
then {if (U/Ly == 1)
then operandY[31:0] = {0x0000,
else operandY[31:0] = {0x0000,
if (U/Lx == 1)
then operandX[31:0] = {0x0000,
else operandX[31:0] = {0x0000,
}
else {operandY[31:0] = Ry[31:0]
operandX[31:0] = Rx[31:0]
}
Ry[31:16]}
Ry[15:0]}
Rx[31:16]}
Rx[15:0]}
/* perform the multiply */
product[63:0] = operandY[31:0] * operandX[31:0]
/* check for product overflow */
if (product[63:32] != 0x0000_0000)
then {
/* product overflow */
MACSR.V = 1
if (inst == MSAC && MACSR.OMC == 1)
then result[31:0] = 0x0000_0000
else if (MACSR.OMC == 1)
then /* overflowed MAC,
saturationMode enabled */
result[31:0] = 0xffff_ffff
}
/* scale product before combining with accumulator */
switch (SF)
/* 2-bit scale factor */
{
case 0:
/* no scaling specified */
break;
case 1:
/* SF = “<< 1” */
if (product[31] == 1)
then {MACSR.V = 1
if (inst == MSAC && MACSR.OMC == 1)
then result[31:0] = 0x0000_0000
else if (MACSR.OMC == 1)
then /* overflowed MAC,
saturationMode enabled */
result[31:0] = 0xffff_ffff
}
else product[31:0] = {product[30:0], 0}
break;
case 2:
/* reserved encoding */
break;
case 3:
/* SF = “>> 1” */
product[31:0] = {0, product[31:1]}
break;
}
/* combine with accumulator */
if (MACSR.V == 0)
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
8-13
Multiply-Accumulate Unit (MAC)
then {if (inst == MSAC)
then result[31:0] = acc[31:0] - product[31:0]
else result[31:0] = acc[31:0] + product[31:0]
}
/* check for accumulation overflow */
if (accumulationOverflow == 1)
then {MACSR.V = 1
if (inst == MSAC && MACSR.OMC == 1)
then result[31:0] = 0x0000_0000
else if (MACSR.OMC == 1)
then /* overflowed MAC,
saturationMode enabled */
result[31:0] = 0xffff_ffff
}
/* transfer the result to the accumulator */
acc[31:0] = result[31:0]
MACSR.N = result[31]
if (result[31:0] == 0x0000_0000)
then MACSR.Z = 1
else MACSR.Z = 0
}
break;}
MCF51MM256 Series Devices Reference Manual, Rev. 3
8-14
Freescale Semiconductor
Chapter 9
Rapid GPIO (RGPIO)
9.1
Introduction
The Rapid GPIO (RGPIO) module provides a 16-bit general-purpose I/O module directly connected to the
processor’s high-speed 32-bit local bus. This connection plus support for single-cycle, zero wait-state data
transfers allows the RGPIO module to provide improved pin performance when compared to more
traditional GPIO modules located on the internal slave peripheral bus.
Many of the pins associated with a device may be used for several different functions. Their primary
functions are to provide external interfaces to access off-chip resources. When not used for their primary
function, many of the pins may be used as general-purpose digital I/O (GPIO) pins. The definition of the
exact pin functions and the affected signals is specific to each device. Every GPIO port, including the
RGPIO module, has registers that configure, monitor, and control the port pins.
•
NOTE
Most pin functions default to GPIO and must be software configured
before using RGPIO.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
9-1
Rapid GPIO (RGPIO)
Figure 9-1 shows the MCF51MM256 series block diagram with the RGPIO highlighted.
Figure 9-1. MCF51MM256 Series Block Diagram Highlighting RGPIO Block and Pins
MCF51MM256 Series Devices Reference Manual, Rev. 3
9-2
Freescale Semiconductor
Rapid GPIO (RGPIO)
9.1.1
Overview
The RGPIO module provides 16-bits of high-speed GPIO functionality, mapped to the processor’s bus.
The key features of this module include:
• 16 bits of high-speed GPIO functionality connected to the processor’s local 32-bit bus
• Memory-mapped device connected to the ColdFire core’s local bus
— Support for all access sizes: byte, word, and longword
— All reads and writes complete in a single data phase cycle for zero wait-state response
• Data bits can be accessed directly or via alternate addresses to provide set, clear, and toggle
functions
— Alternate addresses allow set, clear, toggle functions using simple store operations without the
need for read-modify-write references
• Unique data direction and pin enable control registers
• Package pin toggle rates typically 1.5–3.5x faster than comparable pin mapped onto peripheral bus
A simplified block diagram of the RGPIO module is shown in Figure 9-2. The details of the pin muxing
and pad logic are device-specific.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
9-3
Rapid GPIO (RGPIO)
RGPIO
module
data to module
0
16
0
16
31
31
Pin Enables
31
15
Direction
decode
address
Control
Write D ata
mux
0 Read D ata
16
15
31
rgpio_enable
rgpio_direction
rgpio_data_out
rgpio_data_in
0
31
data from module
Pin Muxing + Pad Logic
Local Bus
RGPIO[15:0]
Figure 9-2. RGPIO Block Diagram
9.1.2
Features
The major features of the RGPIO module providing 16 bits of high-speed general-purpose input/output
are:
• Small memory-mapped device connected to the processor’s local bus
— All memory references complete in a single cycle to provide zero wait-state responses
— Located in processor’s high-speed clock domain
• Simple programming model
— Four 16-bit registers, mapped as three program-visible locations
– Register for pin enables
– Register for controlling the pin data direction
– Register for storing output pin data
– Register for reading current pin state
MCF51MM256 Series Devices Reference Manual, Rev. 3
9-4
Freescale Semiconductor
Rapid GPIO (RGPIO)
– The two data registers (read, write) are mapped to a single program-visible location
— Alternate addresses to perform data set, clear, and toggle functions using simple writes
— Separate read and write programming model views enable simplified driver software
– Support for any access size (byte, word, or longword)
9.1.3
Modes of Operation
The RGPIO module does not support any special modes of operation. As a memory-mapped device
located on the processor’s high-speed local bus, it responds based strictly on memory address and does not
consider the operating mode (supervisor, user) of its references.
9.2
External Signal Description
9.2.1
Overview
As shown in Figure 9-2, the RGPIO module’s interface to external logic is indirect via the device
pin-muxing and pad logic. For a list of the associated RGPIO input/output signals, see Table 9-1.
Table 9-1. RGPIO Module External I/O Signals
Signal Name
RGPIO[15:0]
9.2.2
Type
I/O
Description
RGPIO Data Input/Output
Detailed Signal Descriptions
Table 9-2 provides descriptions of the RGPIO module’s input and output signals.
Table 9-2. RGPIO Detailed Signal Descriptions
Signal
RGPIO[15:0]
I/O
Description
I/O Data Input/Output. When configured as an input, the state of this signal is reflected in the read
data register. When configured as an output, this signal is the output of the write data register.
State
Meaning
Asserted—
Input: Indicates the RGPIO pin was sampled as a logic high at the time of
the read.
Output: Indicates a properly-enabled RGPIO output pin is to be driven high.
Negated—
Input: Indicates the RGPIO pin was sampled as a logic low at the time of the
read.
Output: Indicates a properly-enabled RGPIO output pin is to be driven low.
Timing
Assertion/Negation—
Input: Anytime. The input signal is sampled at the rising-edge of the
processor’s high-speed clock on the data phase cycle of a read transfer of
this register.
Output: Occurs at the rising-edge of the processor’s high-speed clock on
the data phase cycle of a write transfer to this register. This output is
asynchronously cleared by system reset.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
9-5
Rapid GPIO (RGPIO)
9.3
Memory Map/Register Definition
The RGPIO module provides a compact 16-byte programming model based at a system memory address
of 0x(00)C0_0000 (noted as RGPIO_BASE throughout the chapter). As previously noted, the
programming model views are different between reads and writes as this enables simplified software for
manipulation of the RGPIO pins.
Additionally, the RGPIO programming model is defined with a 32-bit organization. The basic size of each
program-visible register is 16 bits, but the programming model may be referenced using byte (8-bit), word
(16-bit) or longword (32-bit) accesses. Performance is typically maximized using 32-bit accesses.
NOTE
Writes to the two-byte fields at RGPIO_BASE + 0x8 and
RGPIO_BASE + 0xC are allowed, but do not affect any program-visible
register within the RGPIO module.
Table 9-3. RGPIO Write Memory Map
Offset
Address
Register
Width
(bits)
Access Reset Value
Section/Page
0x00
RGPIO Data Direction Register (RGPIO_DIR)
16
W
0x0000
9.3.1/9-7
0x02
RGPIO Write Data Register (RGPIO_DATA)
16
W
0x0000
9.3.2/9-7
0x04
RGPIO Pin Enable Register (RGPIO_ENB)
16
W
0x0000
9.3.3/9-8
0x06
RGPIO Write Data Clear Register (RGPIO_CLR)
16
W
N/A
9.3.4/9-8
0x0A
RGPIO Write Data Set Register (RGPIO_SET)
16
W
N/A
9.3.5/9-9
0x0E
RGPIO Write Data Toggle Register (RGPIO_TOG)
16
W
N/A
9.3.6/9-9
Table 9-4. RGPIO Read Memory Map
Offset
Address
Register
Width
(bits)
Access Reset Value
Section/Page
0x00
RGPIO Data Direction Register (RGPIO_DIR)
16
R
0x0000
9.3.1/9-7
0x02
RGPIO Write Data Register (RGPIO_DATA)
16
R
0x0000
9.3.2/9-7
0x04
RGPIO Pin Enable Register (RGPIO_ENB)
16
R
0x0000
9.3.3/9-8
0x06
RGPIO Write Data Register (RGPIO_DATA)
16
R
0x0000
9.3.2/9-7
0x08
RGPIO Data Direction Register (RGPIO_DIR)
16
R
0x0000
9.3.1/9-7
0x0A
RGPIO Write Data Register (RGPIO_DATA)
16
R
0x0000
9.3.2/9-7
0x0C
RGPIO Data Direction Register (RGPIO_DIR)
16
R
0x0000
9.3.1/9-7
0x0E
RGPIO Write Data Register (RGPIO_DATA)
16
R
0x0000
9.3.2/9-7
MCF51MM256 Series Devices Reference Manual, Rev. 3
9-6
Freescale Semiconductor
Rapid GPIO (RGPIO)
9.3.1
RGPIO Data Direction (RGPIO_DIR)
The read/write RGPIO_DIR register defines whether a properly-enabled RGPIO pin is configured as an
input or output:
• Setting any bit in RGPIO_DIR configures a properly-enabled RGPIO port pin as an output
• Clearing any bit in RGPIO_DIR configures a properly-enabled RGPIO port pin as an input
At reset, all bits in the RGPIO_DIR are cleared.
Offset: RGPIO_Base + 0x0 (RGPIO_DIR)
RGPIO_Base + 0x8
RGPIO_Base + 0xC
15
14
13
12
11
Access: Read/write
Read-only
Read-only
10
9
8
R
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
DIR
W
Reset
7
0
0
0
0
0
0
0
0
Figure 9-3. RGPIO Data Direction Register (RGPIO_DIR)
Table 9-5. RGPIO_DIR Field Descriptions
Field
15–0
DIR
9.3.2
Description
Data direction.
0 A properly-enabled RGPIO pin is configured as an input
1 A properly-enabled RGPIO pin is configured as an output
RGPIO Data (RGPIO_DATA)
The RGPIO_DATA register specifies the write data for a properly-enabled RGPIO output pin or the
sampled read data value for a properly-enabled input pin. An attempted read of the RGPIO_DATA register
returns undefined data for disabled pins, since the data value is dependent on the device-level pin muxing
and pad implementation. The RGPIO_DATA register is read/write. At reset, all bits in the RGPIO_DATA
registers are cleared.
To set bits in a RGPIO_DATA register, directly set the RGPIO_DATA bits or set the corresponding bits in
the RGPIO_SET register. To clear bits in the RGPIO_DATA register, directly clear the RGPIO_DATA
bits, or clear the corresponding bits in the RGPIO_CLR register. Setting a bit in the RGPIO_TOG register
inverts (toggles) the state of the corresponding bit in the RGPIO_DATA register.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
9-7
Rapid GPIO (RGPIO)
Offset: RGPIO_Base + 0x2 (RGPIO_DATA)
RGPIO_Base + 0x6
RGPIO_Base + 0xA
RGPIO_Base + 0xE
15
14
13
12
11
Access: Read/write
Read/Indirect Write
Read/Indirect Write
Read/Indirect Write
10
9
8
R
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
DATA
W
Reset
7
0
0
0
0
0
0
0
0
Figure 9-4. RGPIO Data Register (RGPIO_DATA)
Table 9-6. RGPIO_DATA Field Descriptions
Field
Description
15–0
DATA
RGPIO data.
0 A properly-enabled RGPIO output pin is driven with a logic 0, or a properly-enabled RGPIO input pin was read as
a logic 0
1 A properly-enabled RGPIO output pin is driven with a logic 1, or a properly-enabled RGPIO input pin was read as
a logic 1
9.3.3
RGPIO Pin Enable (RGPIO_ENB)
The RGPIO_ENB register configures the corresponding package pin as a RGPIO pin instead of the normal
GPIO pin mapped onto the peripheral bus.
The RGPIO_ENB register is read/write. At reset, all bits in the RGPIO_ENB are cleared, disabling the
RGPIO functionality.
Offset: RGPIO_Base + 0x4 (RGPIO_ENB)
15
14
13
12
11
Access: Read/write
10
9
8
R
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
ENB
W
Reset
7
0
0
0
0
0
0
0
0
Figure 9-5. RGPIO Enable Register (RGPIO_ENB)
Table 9-7. RGPIO_ENB Field Descriptions
Field
15–0
ENB
9.3.4
Description
Enable pin for RGPIO
0 The corresponding package pin is configured for use as a normal GPIO pin, not a RGPIO
1 The corresponding package pin is configured for use as a RGPIO pin
RGPIO Clear Data (RGPIO_CLR)
The RGPIO_CLR register provides a mechanism to clear specific bits in the RGPIO_DATA by performing
a simple write. Clearing a bit in RGPIO_CLR clears the corresponding bit in the RGPIO_DATA register.
MCF51MM256 Series Devices Reference Manual, Rev. 3
9-8
Freescale Semiconductor
Rapid GPIO (RGPIO)
Setting it has no effect. The RGPIO_CLR register is write-only; reads of this address return the
RGPIO_DATA register.
Offset: RGPIO_Base + 0x6 (RGPIO_CLR)
15
14
13
12
11
Access: Write-only
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
R
W
Reset
CLR
—
—
—
—
—
—
—
—
Figure 9-6. RGPIO Clear Data Register (RGPIO_CLR)
Table 9-8. RGPIO_CLR Field Descriptions
Field
15–0
CLR
9.3.5
Description
Clear data bit
0 Clears the corresponding bit in the RGPIO_DATA register
1 No effect
RGPIO Set Data (RGPIO_SET)
The RGPIO_SET register provides a mechanism to set specific bits in the RGPIO_DATA register by
performing a simple write. Setting a bit in RGPIO_SET asserts the corresponding bit in the RGPIO_DATA
register. Clearing it has no effect. The RGPIO_SET register is write-only; reads of this address return the
RGPIO_DATA register.
Offset: RGPIO_Base + 0xA (RGPIO_SET)
Access: Write-only
15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
R
W
Reset
SET
Figure 9-7. RGPIO Set Data Register (RGPIO_SET)
Table 9-9. RGPIO_SET Field Descriptions
Field
15–0
SET
9.3.6
Description
Set data bit
0 No effect
1 Sets the corresponding bit in the RGPIO_DATA register
RGPIO Toggle Data (RGPIO_TOG)
The RGPIO_TOG register provides a mechanism to invert (toggle) specific bits in the RGPIO_DATA
register by performing a simple write. Setting a bit in RGPIO_TOG inverts the corresponding bit in the
RGPIO_DATA register. Clearing it has no effect. The RGPIO_TOG register is write-only; reads of this
address return the RGPIO_DATA register.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
9-9
Rapid GPIO (RGPIO)
Offset: RGPIO_Base + 0xE (RGPIO_TOG)
15
14
13
12
11
Access: Write-only
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
R
W
Reset
TOG
—
—
—
—
—
—
—
—
Figure 9-8. RGPIO Toggle Data Register (RGPIO_TOG)
Table 9-10. RGPIO_TOG Field Descriptions
Field
15–0
TOG
9.4
Description
Toggle data.
0 No effect
1 Inverts the corresponding bit in RGPIO_DATA
Functional Description
The RGPIO module is a relatively-simple design with its behavior controlled by the program-visible
registers defined within its programming model.
The RGPIO module is connected to the processor’s local two-stage pipelined bus with the stages of the
ColdFire core’s operand execution pipeline (OEP) mapped directly onto the bus. This structure allows the
processor access to the RGPIO module for single-cycle pipelined reads and writes with a zero wait-state
response (as viewed in the system bus data phase stage).
9.5
Initialization Information
The reset state of the RGPIO module disables the entire 16-bit data port. Prior to using the RGPIO port,
software typically:
• Enables the appropriate pins in RGPIO_ENB
• Configures the pin direction in RGPIO_DIR
• Defines the contents of the data register (RGPIO_DATA)
9.6
Application Information
This section examines the relative performance of the RGPIO output pins for two simple applications
• The processor executes a loop to toggle an output pin for a specific number of cycles, producing a
square-wave output
• The processor transmits a 16-bit message using a three-pin SPI-like interface with a serial clock,
serial chip select, and serial data bit.
In both applications, the relative speed of the GPIO output is presented as a function of the location of the
output bit (RGPIO versus peripheral bus GPIO).
MCF51MM256 Series Devices Reference Manual, Rev. 3
9-10
Freescale Semiconductor
Rapid GPIO (RGPIO)
9.6.1
Application 1: Simple Square-Wave Generation
In this example, several different instruction loops are executed, each generating a square-wave output
with a 50% duty cycle. For this analysis, the executed code is mapped into the processor’s RAM. This
configuration is selected to remove any jitter from the output square wave caused by the limitations
defined by the two-cycle flash memory accesses and restrictions on the initiation of a flash access. The
following instruction loops were studied:
• BCHG_LOOP — In this loop, a bit change instruction was executed using the GPIO data byte as
the operand. This instruction performs a read-modify-write operation and inverts the addressed bit.
A pulse counter is decremented until the appropriate number of square-wave pulses have been
generated.
• SET+CLR_LOOP — For this construct, two store instructions are executed: one to set the GPIO
data pin and another to clear it. Single-cycle NOP instructions (the tpf opcode) are included to
maintain the 50% duty cycle of the generated square wave. The pulse counter is decremented until
the appropriate number of square-wave pulse have been generated.
The square-wave output frequency was measured and the relative performance results are presented in
Table 9-11. The relative performance is stated as a fraction of the processor’s operating frequency, defined
as f MHz. The performance of the BCHG loop operating on a GPIO output is selected as the reference.
Table 9-11. Square-Wave Output Performance
Peripheral Bus-mapped GPIO
Loop
Sq-Wave
Frequency
RGPIO
Frequency @ Relative
CPU f = 50 MHz Speed
Sq-Wave
Frequency
Frequency @ Relative
CPU f = 50 MHz Speed
(1/24)  f MHz
2.083 MHz
1.00x
(1/14)  f MHz
3.571 MHz
1.71x
set+clr (+toggle) (1/12)  f MHz
4.167 MHz
2.00x
(1/8)  f MHz
6.250 MHz
3.00x
bchg
NOTE
The square-wave frequency is measured from rising-edge to rising-edge,
where the output wave has a 50% duty cycle.
9.6.2
Application 2: 16-bit Message Transmission using SPI Protocol
In this second example, a 16-bit message is transmitted using three programmable output pins. The output
pins include a serial clock, an active-high chip select, and the serial data bit. The software is configured to
sample the serial data bit at the rising-edge of the clock with the data sent in a most-significant to
least-significant bit order. The resulting 3-bit output is shown in Figure 9-9.
gpio_cs
gpio_clk
gpio_data
15
14
13
2
1
0
Figure 9-9. GPIO SPI Example Timing Diagram
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
9-11
Rapid GPIO (RGPIO)
For this example, the processing of the SPI message is considerably more complex than the generation of
a simple square wave of the previous example. The code snippet used to extract the data bit from the
message and build the required GPIO data register writes is shown in Figure 9-10.
# subtest: send a 16-bit message via a SPI interface using a RGPIO
# the SPI protocol uses a 3-bit value: clock, chip-select, data
# the data is centered around the rising-edge of the clock
align
16
send_16b_spi_message_rgpio:
00510: 4fef fff4
lea
-12(%sp),%sp
#
00514: 48d7 008c
movm.l &0x8c,(%sp)
#
00518: 3439 0080 0582
mov.w
RAM_BASE+message2,%d2
0051e: 760f
movq.l &15,%d3
#
00520: 7e10
movq.l &16,%d7
#
00522: 207c 00c0 0003
mov.l
&RGPIO_DATA+1,%a0
#
00528: 203c 0000 ffff
mov.l
&0xffff,%d0
#
0052e: 3140 fffd
mov.w
%d0,-3(%a0)
#
00532: 3140 0001
mov.w
%d0,1(%a0)
#
00536:
0053c:
0053e:
00540:
00542:
00544:
223c 0001 0000
2001
e6a8
5880
1080
6002
00548:
0054a:
0054c:
0054e:
00550:
00552:
00554:
00556:
00558:
0055a:
0055c:
0055e:
00560:
3202
2001
e6a8
1080
5880
e38a
51fc
51fc
51fc
51fc
1080
5387
66e6
allocate stack space
save d2,d3,d7
# get 16-bit message
static shift count
message bit length
pointer to low-order data byte
data value for _ENB and _DIR regs
set RGPIO_DIR register
set RGPIO_ENB register
mov.l
mov.l
lsr.l
addq.l
mov.b
bra.b
align
&0x10000,%d1
%d1,%d0
%d3,%d0
&4,%d0
%d0,(%a0)
L%1
4
#
#
#
#
#
d1[17:16] = {clk, cs}
copy into temp reg
align in d0[2:0]
set clk = 1
initialize data
mov.w
mov.l
lsr.l
mov.b
addq.l
lsl.l
tpf
tpf
tpf
tpf
mov.b
subq.l
bne.b
%d2,%d1
%d1,%d0
%d3,%d0
%d0,(%a0)
&4,%d0
&1,%d2
#
#
#
#
#
#
#
d1[17:15] = {clk, cs, data}
copy into temp reg
align in d0[2:0]
transmit data with clk = 0
force clk = 1
d2[15] = new message data bit
preserve 50% duty cycle
%d0,(%a0)
&1,%d7
L%1
# transmit data with clk = 1
# decrement loop counter
00562: c0bc 0000 fff5
00568: 1080
and.l
mov.b
&0xfff5,%d0
%d0,(%a0)
# negate chip-select
# update gpio
0056a: 4cd7 008c
0056e: 4fef 000c
00572: 4e75
movm.l
lea
rts
(%sp),&0x8c
12(%sp),%sp
# restore d2,d3,d7
# deallocate stack space
L%1:
Figure 9-10. GPIO SPI Code Example
The resulting SPI performance, as measured in the effective Mbps transmission rate for the 16-bit message,
is shown in Table 9-12.
MCF51MM256 Series Devices Reference Manual, Rev. 3
9-12
Freescale Semiconductor
Rapid GPIO (RGPIO)
Table 9-12. Emulated SPI Performance using GPIO Outputs
Peripheral Bus-mapped GPIO
RGPIO
SPI Speed @
CPU f = 50 MHz
Relative
Speed
SPI Speed @
CPU f = 50 MHz
Relative
Speed
2.063 Mbps
1.00x
3.809 Mbps
1.29x
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
9-13
Rapid GPIO (RGPIO)
MCF51MM256 Series Devices Reference Manual, Rev. 3
9-14
Freescale Semiconductor
Chapter 10
Interrupt Controller (CF1_INTC)
10.1
Introduction
The CF1_INTC interrupt controller (CF1_INTC) is intended for use in low-cost microcontroller designs
using the Version 1 (V1) ColdFire processor core. In keeping with the general philosophy for devices based
on this low-end 32-bit processor, the interrupt controller generally supports less programmability
compared to similar modules in other ColdFire microcontrollers and embedded microprocessors.
However, CF1_INTC provides the required functionality with a minimal silicon cost.
These requirements guide the CF1_INTC module definition to support Freescale’s Controller Continuum:
• The priorities of the interrupt requests between comparable HCS08 and V1 ColdFire devices are
identical.
• Supports a mode of operation (through software convention with hardware assists) equivalent to
the S08’s interrupt processing with only one level of nesting.
• Leverages the current ColdFire interrupt controller programming model and functionality, but with
a minimal hardware implementation and cost.
Table 10-1 provides a high-level architectural comparison between HCS08 and ColdFire exception
processing as these differences are important in the definition of the CF1_INTC module. Throughout this
document, the term IRQ refers to an interrupt request and ISR refers to an interrupt service routine to
process an interrupt exception.
Table 10-1. Exception Processing Comparison
Attribute
Exception Vector Table
More on Vectors
Exception Stack Frame
Interrupt Levels
Non-Maskable IRQ Support
HCS08
32 two-byte entries, fixed location at upper
end of memory
103 four-byte entries, located at lower end of
memory at reset, relocatable with the VBR
2 for CPU + 30 for IRQs, reset at upper
address
64 for CPU + 39 for IRQs, reset at lowest
address
5-byte frame: CCR, A, X, PC
8-byte frame: F/V, SR, PC; General-purpose
registers (An, Dn) must be saved/restored
by the ISR
1 = f(CCR[I])
7= f (SR[I]) with automatic hardware support
for nesting
No
Yes, with level 7 interrupts
Core-enforced IRQ Sensitivity No
INTC Vectoring
V1 ColdFire
Fixed priorities and vector assignments
Level 7 is edge sensitive, else level sensitive
Fixed priorities and vector assignments, plus
any 2 IRQs can be remapped as the highest
priority level 6 requests
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
10-1
Interrupt Controller (CF1_INTC)
Table 10-1. Exception Processing Comparison (Continued)
Attribute
HCS08
V1 ColdFire
Software IACK
No
Yes
Exit Instruction from ISR
RTI
RTE
10.1.1
Overview
Interrupt exception processing includes interrupt recognition, aborting the current instruction execution
stream, storing an 8-byte exception stack frame in the memory, calculation of the appropriate vector, and
passing control to the specified interrupt service routine.
Unless specifically noted otherwise, all ColdFire processors sample for interrupts once during each
instruction’s execution during the first cycle of execution in the OEP. Additionally, all ColdFire processors
use an instruction restart exception model.
The ColdFire processor architecture defines a 3-bit interrupt priority mask field in the processor’s status
register (SR[I]). This field, and the associated hardware, support seven levels of interrupt requests with the
processor providing automatic nesting capabilities. The levels are defined in descending numeric order
with 7 > 6 ... > 1. Level 7 interrupts are treated as non-maskable, edge-sensitive requests while levels 6–1
are maskable, level-sensitive requests. The SR[I] field defines the processor’s current interrupt level. The
processor continuously compares the encoded IRQ level from CF1_INTC against SR[I]. Recall that
interrupt requests are inhibited for all levels less than or equal to the current level, except the edge-sensitive
level 7 request that cannot be masked.
Exception processing for ColdFire processors is streamlined for performance and includes all actions from
detecting the fault condition to the initiation of fetch for the first handler instruction. Exception processing
is comprised of four major steps.
1. The processor makes an internal copy of the status register (SR) and enters supervisor mode by
setting SR[S] and disabling trace mode by clearing SR[T]. The occurrence of an interrupt
exception also forces the master mode (M) bit to clear and the interrupt priority mask (I) to set to
the level of the current interrupt request.
2. The processor determines the exception vector number. For all faults except interrupts, the
processor performs this calculation based on the exception type. For interrupts, the processor
performs an IACK bus cycle to obtain the vector number from the interrupt controller if
CPUCR[IAE] equals 1. The IACK cycle is mapped to special locations within the interrupt
controller’s IPS address space with the interrupt level encoded in the address. If
CPUCR[IAE] equals 0, the processor uses the vector number supplied by the interrupt controller
at the time the request was signaled (for improved performance).
3. The processor saves the current context by creating an exception stack frame on the system stack.
As a result, exception stack frame is created at a 0-modulo-4 address on top of the system stack
defined by the supervisor stack pointer (SSP). The processor uses an 8-byte stack frame for all
exceptions. It contains the vector number of the exception, the contents of the status register at the
time of the exception, and the program counter (PC) at the time of the exception. The exception
MCF51MM256 Series Devices Reference Manual, Rev. 3
10-2
Freescale Semiconductor
Interrupt Controller (CF1_INTC)
type determines whether the program counter placed in the exception stack frame defines the
location of the faulting instruction (fault) or the address of the next instruction to be executed
(next). For interrupts, the stacked PC is always the address of the next instruction to be executed.
4. The processor calculates the address of the first instruction of the exception handler. By definition,
the exception vector table is aligned on a 1MB boundary. This instruction address is generated by
fetching a 32-bit exception vector from the table located at the address defined in the vector base
register (VBR). The index into the exception table is calculated as (4  vector number). After the
exception vector has been fetched, the contents of the vector serves as a 32-bit pointer to the
address of the first instruction of the desired handler. After the instruction fetch for the first opcode
of the handler has been initiated, exception processing terminates and normal instruction
processing continues in the handler.
All ColdFire processors support a 1024-byte vector table aligned on any 1-MB address boundary. For the
V1 ColdFire core, the only practical locations for the vector table are based at 0x(00)00_0000 in the flash
or 0x(00)80_0000 in the RAM. The table contains 256 exception vectors; the first 64 are reserved for
internal processor exceptions, and the remaining 192 are device-specific interrupt vectors. The IRQ
assignment table is partially populated depending on the exact set of peripherals for the given device.
The basic ColdFire interrupt controller supports up to 63 request sources mapped as nine priorities for each
of the seven supported levels (7 levels  9 priorities per level). Within the nine priorities within a level, the
mid-point is typically reserved for package-level IRQ inputs. The levels and priorities within the level
follow a descending order: 7 > 6 > ... > 1 > 0.
The HCS08 architecture supports a 32-entry exception vector table: the first two vectors are reserved for
internal CPU/system exceptions and the remaining are available for I/O interrupt requests. The
requirement for an exact match between the interrupt requests and priorities across two architectures
means the sources are mapped to a sparsely-populated two-dimensional ColdFire array of seven interrupt
levels and nine priorities within the level. The following association between the HCS08 and ColdFire
vector numbers applies:
ColdFire Vector Number = 62 + HCS08 Vector Number
The CF1_INTC performs a cycle-by-cycle evaluation of the active requests and signals the highest-level,
highest-priority request to the V1 ColdFire core in the form of an encoded interrupt level and the exception
vector associated with the request. The module also includes a byte-wide interface to access its
programming model. These interfaces are shown in the simplified block diagram of Figure 10-1.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
10-3
Interrupt Controller (CF1_INTC)
Interrupt Source Number
CF1_INTC
data to module
8
address
decode
ipr
Enable
Wakeup
INTC_WCR
INTC_FRC
mux

>

Prioritization
and
Vector Gen
IACK
Vector Mux
Spurious Vector
Level n Vector
mux
data from module
8
Wakeup
Interrupt Level & Vector
to V1 ColdFire core
Peripheral Bus
Figure 10-1. CF1_INTC Block Diagram
10.1.2
Features
The Version 1 ColdFire interrupt controller includes:
• Memory-mapped off-platform slave module
— 64-byte space located at top end of memory: 0x(FF)FF_FFC0–0x(FF)FF_FFFF
— Programming model accessed via the peripheral bus
— Encoded interrupt level and vector sent directly to processor core
• Support of 44 peripheral I/O interrupt requests plus seven software (one per level) interrupt
requests
• Fixed association between interrupt request source and level plus priority
— I/O requests assigned across seven available levels and nine priorities per level
MCF51MM256 Series Devices Reference Manual, Rev. 3
10-4
Freescale Semiconductor
Interrupt Controller (CF1_INTC)
•
•
•
— Exactly matches HCS08 interrupt request priorities
— Up to two requests can be remapped to the highest maskable level + priority
Unique vector number for each interrupt source
— ColdFire vector number = 62 + HCS08 vector number
— Details on IRQ and vector assignments are device-specific
Support for service routine interrupt acknowledge (software IACK) read cycles for improved
system performance
Combinatorial path provides wakeup signal from wait and stop modes
10.1.3
Modes of Operation
The CF1_INTC module does not support any special modes of operation. As a memory-mapped slave
peripheral located on the platform’s slave bus, it responds based strictly on the memory addresses of the
connected bus.
One special behavior of the CF1_INTC deserves mention. When the device enters a wait or stop mode and
certain clocks are disabled, there is an input signal that can be asserted to enable a purely-combinational
logic path for monitoring the assertion of an interrupt request. After a request of unmasked level is
asserted, this combinational logic path asserts an output signal that is sent to the clock generation logic to
re-enable the internal device clocks to exit the low-power mode.
10.2
External Signal Description
The CF1_INTC module does not include any external interfaces.
10.3
Memory Map/Register Definition
The CF1_INTC module provides a 64-byte programming model mapped to the upper region of the 16 MB
address space. All the register names are prefixed with INTC_ as an abbreviation for the full module name.
The programming model is referenced using 8-bit accesses. Attempted references to undefined (reserved)
addresses or with a non-supported access type (for example, a write to a read-only register) generate a bus
error termination.
The programming model follows the definition from previous ColdFire interrupt controllers. This
compatibility accounts for the various memory holes in this module’s memory map.
The CF1_INTC module is based at address 0x(FF)FF_FFC0 (referred to as CF1_INTC_BASE throughout
the chapter) and occupies the upper 64 bytes of the peripheral space. The module memory map is shown
in Table 10-2.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
10-5
Interrupt Controller (CF1_INTC)
Table 10-2. CF1_INTC Memory Map
Offset
Address
Register Name
Register Description
Width
(bits)
Access
Reset Value
Section/
Page
0x10
INTC_FRC
CF1_INTC Force Interrupt Register
8
R/W
0x00
10.3.1/10-6
0x18
INTC_PL6P7
CF1_INTC Programmable Level 6, Priority 7
8
R/W
0x00
10.3.2/10-7
0x19
INTC_PL6P6
CF1_INTC Programmable Level 6, Priority 6
8
R/W
0x00
10.3.2/10-7
0x1B
INTC_WCR
CF1_INTC Wakeup Control Register
8
R/W
0x80
10.3.3/10-8
0x1E
INTC_SFRC
CF1_INTC Set Interrupt Force Register
8
Write
—
10.3.4/10-9
0x1F
INTC_CFRC
CF1_INTC Clear Interrupt Force Register
8
Write
—
10.3.5/10-10
0x20
INTC_SWIACK
CF1_INTC Software Interrupt Acknowledge
8
Read
0x00
10.3.6/10-11
0x24
INTC_LVL1IACK
CF1_INTC Level 1 Interrupt Acknowledge
8
Read
0x18
10.3.6/10-11
0x28
INTC_LVL2IACK
CF1_INTC Level 2 Interrupt Acknowledge
8
Read
0x18
10.3.6/10-11
0x2C
INTC_LVL3IACK
CF1_INTC Level 3 Interrupt Acknowledge
8
Read
0x18
10.3.6/10-11
0x30
INTC_LVL4IACK
CF1_INTC Level 4 Interrupt Acknowledge
8
Read
0x18
10.3.6/10-11
0x34
INTC_LVL5IACK
CF1_INTC Level 5 Interrupt Acknowledge
8
Read
0x18
10.3.6/10-11
0x38
INTC_LVL6IACK
CF1_INTC Level 6 Interrupt Acknowledge
8
Read
0x18
10.3.6/10-11
0x3C
INTC_LVL7IACK
CF1_INTC Level 7 Interrupt Acknowledge
8
Read
0x18
10.3.6/10-11
10.3.1
Force Interrupt Register (INTC_FRC)
The INTC_FRC register allows software to generate a unique interrupt for each possible level at the lowest
priority within the level for functional or debug purposes. These interrupts may be self-scheduled by
setting one or more of the bits in the INTC_FRC register. In some cases, the handling of a normal interrupt
request may cause critical processing by the service routine along with the scheduling (using the
INTC_FRC register) of a lower priority level interrupt request to be processed at a later time for
less-critical task handling.
The INTC_FRC register may be modified directly using a read-modify-write sequence or through a simple
write operation using the set/clear force interrupt registers (INTC_SFRC, INTC_CFRC).
NOTE
Take special notice of the bit numbers within this register, 63–56. This is for
compatibility with other ColdFire interrupt controllers.
MCF51MM256 Series Devices Reference Manual, Rev. 3
10-6
Freescale Semiconductor
Interrupt Controller (CF1_INTC)
Offset: CF1_INTC_BASE + 0x10 (INTC_FRC)
63
R
Access: Read/Write
62
61
60
59
58
57
56
LVL1
LVL2
LVL3
LVL4
LVL5
LVL6
LVL7
0
0
0
0
0
0
0
0
W
Reset
0
Figure 10-2. Force Interrupt Register (INTC_FRC)
Table 10-3. INTC_FRC Field Descriptions
Field
63
Description
Reserved, must be cleared.
62
LVL1
Force Level 1 interrupt.
0 Negates the forced level 1 interrupt request.
1 Forces a level 1 interrupt request.
61
LVL2
Force Level 2 interrupt.
0 Negates the forced level 2 interrupt request.
1 Forces a level 2 interrupt request.
60
LVL3
Force Level 3 interrupt.
0 Negates the forced level 3 interrupt request.
1 Forces a level 3 interrupt request.
59
LVL4
Force Level 4 interrupt.
0 Negates the forced level 4 interrupt request.
1 Forces a level 4 interrupt request.
58
LVL5
Force Level 5 interrupt.
0 Negates the forced level 5 interrupt request.
1 Forces a level 5 interrupt request.
57
LVL6
Force Level 6 interrupt.
0 Negates the forced level 6 interrupt request.
1 Forces a level 6 interrupt request.
55
LVL7
Force Level 7 interrupt.
0 Negates the forced level 7 interrupt request.
1 Forces a level 7 interrupt request.
10.3.2
INTC Programmable Level 6, Priority {7,6} Registers
(INTC_PL6P{7,6})
The level seven interrupt requests cannot have their levels reassigned. However, any of the remaining
peripheral interrupt requests can be reassigned as the highest priority maskable requests using these two
registers (INTC_PL6P7 and INTC_PL6P6). The vector number associated with the interrupt requests does
not change. Rather, only the interrupt request's level and priority are altered, based on the contents of the
INTC_PL6P{7,6} registers.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
10-7
Interrupt Controller (CF1_INTC)
NOTE
The requests associated with the INTC_FRC register have a fixed level and
priority that cannot be altered.
The INTC_PL6P7 register specifies the highest-priority, maskable interrupt request that is defined as the
level six, priority seven request. The INTC_PL6P6 register specifies the second-highest-priority, maskable
interrupt request defined as the level six, priority six request. Reset clears both registers, disabling any
request re-mapping.
For an example of the use of these registers, see Section 10.6.2, “Using INTC_PL6P{7,6} Registers.”
Offset: CF1_INTC_BASE + 0x18 (INTC_PL6P7)
CF1_INTC_BASE + 0x19 (INTC_PL6P6)
R
7
6
0
0
5
Access: Read/Write
4
3
2
1
0
0
0
0
REQN
W
Reset
0
0
0
0
0
Figure 10-3. Programmable Level 6, Priority {7,6} Registers (INTC_PL6P{7,6})
Table 10-4. INTC_PL6P{7,6} Field Descriptions
Field
7–6
5–0
REQN
10.3.3
Description
Reserved, must be cleared.
Request number. Defines the peripheral IRQ number to be remapped as the level 6, priority 7 (for INTC_PL6P7)
request and level 6, priority 6 (for INTC_PL6P6) request.
Note: The value must be a valid interrupt number. Unused or reserved interrupt numbers are ignored.
INTC Wakeup Control Register (INTC_WCR)
The interrupt controller provides a combinatorial logic path to generate a special wakeup signal to exit
from the wait or stop modes. The INTC_WCR register defines wakeup condition for interrupt recognition
during wait and stop modes. This mode of operation works as follows:
1. Write to the INTC_WCR to enable this operation (set INTC_WCR[ENB]) and define the interrupt
mask level needed to force the core to exit wait or stop mode (INTC_WCR[MASK]). The
maximum value of INTC_WCR[MASK] is 0x6 (0b110). The INTC_WCR is enabled with a mask
level of 0 as the default after reset.
2. Execute a stop instruction to place the processor into wait or stop mode.
3. After the processor is stopped, the interrupt controller enables special logic that evaluates the
incoming interrupt sources in a purely combinatorial path; no clocked storage elements are
involved.
4. If an active interrupt request is asserted and the resulting interrupt level is greater than the mask
value contained in INTC_WCR[MASK], the interrupt controller asserts the wakeup output signal.
This signal is routed to the clock generation logic to exit the low-power mode and resume
processing.
MCF51MM256 Series Devices Reference Manual, Rev. 3
10-8
Freescale Semiconductor
Interrupt Controller (CF1_INTC)
Typically, the interrupt mask level loaded into the processor's status register field (SR[I]) during the
execution of the stop instruction matches the INTC_WCR[MASK] value.
The interrupt controller's wakeup signal is defined as:
wakeup = INTC_WCR[ENB] & (level of any asserted_int_request > INTC_WCR[MASK])
Offset: CF1_INTC_BASE + 0x1B (INTC_WCR)
7
R
Access: Read/Write
6
5
4
3
0
0
0
0
2
ENB
1
0
MASK
W
Reset
1
0
0
0
0
0
0
0
Figure 10-4. Wakeup Control Register (INTC_WCR)
Table 10-5. INTC_WCR Field Descriptions
Field
Description
7
ENB
Enable wakeup signal.
0 Wakeup signal disabled
1 Enables the assertion of the combinational wakeup signal to the clock generation logic.
6–3
Reserved, must be cleared.
2–0
MASK
Interrupt mask level. Defines the interrupt mask level during wait or stop mode and is enforced by the hardware to
be within the range 0–6. If INTC_WCR[ENB] is set, when an interrupt request of a level higher than MASK occurs,
the interrupt controller asserts the wakeup signal to the clock generation logic.
10.3.4
INTC Set Interrupt Force Register (INTC_SFRC)
The INTC_SFRC register provides a simple memory-mapped mechanism to set a given bit in the
INTC_FRC register to assert a specific level interrupt request. The data value written causes the
appropriate bit in the INTC_FRC register to be set. Attempted reads of this register generate an error
termination.
This register is provided so interrupt service routines can generate a forced interrupt request without the
need to perform a read-modify-write sequence on the INTC_FRC register.
Offset: CF1_INTC_BASE + 0x1E (INTC_SFRC)
7
6
5
Access: Write-only
4
3
2
1
0
0
0
0
R
W
Reset
SET
0
0
0
0
0
Figure 10-5. INTC_SFRC Register
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
10-9
Interrupt Controller (CF1_INTC)
Table 10-6. INTC_SFRC Field Descriptions
Field
Description
7–6
Reserved, must be cleared.
5–0
SET
For data values within the 56–62 range, the corresponding bit in the INTC_FRC register is set, as defined below.
0x38 Bit 56, INTC_FRC[LVL7] is set
0x39 Bit 57, INTC_FRC[LVL6] is set
0x3A Bit 58, INTC_FRC[LVL5] is set
0x3B Bit 59, INTC_FRC[LVL4] is set
0x3C Bit 60, INTC_FRC[LVL3] is set
0x3D Bit 61, INTC_FRC[LVL2] is set
0x3E Bit 62, INTC_FRC[LVL1] is set
Note: Data values outside this range do not affect the INTC_FRC register. It is recommended the data values be
restricted to the 0x38–0x3E (56–62) range to ensure compatibility with future devices.
10.3.5
INTC Clear Interrupt Force Register (INTC_CFRC)
The INTC_CFRC register provides a simple memory-mapped mechanism to clear a given bit in the
INTC_FRC register to negate a specific level interrupt request. The data value on the register write causes
the appropriate bit in the INTC_FRC register to be cleared. Attempted reads of this register generate an
error termination.
This register is provided so interrupt service routines can negate a forced interrupt request without the need
to perform a read-modify-write sequence on the INTC_FRC register.
Offset: CF1_INTC_BASE + 0x1F (INTC_CFRC)
7
6
W
0
0
Reset
0
0
5
Access: Write-only
4
3
2
1
0
0
0
0
R
CLR
0
0
0
Figure 10-6. INTC_CFRC Register
Table 10-7. INTC_CFRC Field Descriptions
Field
Description
7–6
Reserved, must be cleared.
5–0
CLR
For data values within the 56–62 range, the corresponding bit in the INTC_FRC register is cleared, as defined below.
0x38 Bit 56, INTC_FRC[LVL7] is cleared
0x39 Bit 57, INTC_FRC[LVL6] is cleared
0x3A Bit 58, INTC_FRC[LVL5] is cleared
0x3B Bit 59, INTC_FRC[LVL4] is cleared
0x3C Bit 60, INTC_FRC[LVL3] is cleared
0x3D Bit 61, INTC_FRC[LVL2] is cleared
0x3E Bit 62, INTC_FRC[LVL1] is cleared
Note: Data values outside this range do not affect the INTC_FRC register. It is recommended the data values be
restricted to the 0x38–0x3E (56–62) range to ensure compatibility with future devices.
MCF51MM256 Series Devices Reference Manual, Rev. 3
10-10
Freescale Semiconductor
Interrupt Controller (CF1_INTC)
10.3.6
INTC Software and Level-n IACK Registers (n = 1,2,3,...,7)
The eight read-only interrupt acknowledge (IACK) registers can be explicitly addressed by the
memory-mapped accesses or implicitly addressed by a processor-generated interrupt acknowledge cycle
during exception processing when CPUCR[IAE] is set. In either case, the interrupt controller's actions are
similar.
First, consider an IACK cycle to a specific level, a level-n IACK. When this type of IACK arrives in the
interrupt controller, the controller examines all currently-active level-n interrupt requests, determines the
highest priority within the level, and then responds with the unique vector number corresponding to that
specific interrupt source. The vector number is supplied as the data for the byte-sized IACK read cycle.
If there is no active interrupt source at the time of the level-n IACK, a special spurious interrupt vector
(vector number 24 (0x18)) is returned. It is the responsibility of the service routine to manage this error
situation.
This protocol implies the interrupting peripheral is not accessed during the acknowledge cycle because the
interrupt controller completely services the acknowledge. This means the interrupt source must be
explicitly disabled in the peripheral device by the interrupt service routine. This approach provides unique
vector capability for all interrupt requests, regardless of the complexity of the peripheral device.
Second, the interrupt controller also supports the concept of a software IACK. This is the ability to query
the interrupt controller near the end of an interrupt service routine (after the current interrupt request has
been negated) to determine if there are any pending (but currently masked) interrupt requests. If the
response to the software IACK's byte operand read is non-zero, the service routine uses the returned value
as the vector number of the highest pending interrupt request and passes control to the appropriate new
handler. If the returned value is zero, there is no pending interrupt request.
This process avoids the overhead of a context restore and RTE instruction execution, followed
immediately by another interrupt exception and context save. In system environments with high rates of
interrupt activity, this mechanism can noticeably improve overall performance. For additional details on
software IACKs, see Section 10.6.3, “More on Software IACKs.”
Offset: CF1_INTC_BASE + 0x20 (INTC_SWIACK)
CF1_INTC_BASE + 0x20 + (4n) (INTC_LVLnIACK)
7
R
6
5
4
0
Access: Read-only
3
2
1
0
VECN
W
SWIACK Reset
0
0
0
0
0
0
0
0
LVLnIACK Reset
0
0
0
1
1
0
0
0
Table 10-8. Software and Level-n IACK Registers (INTC_SWIACK, INTC_LVLnIACK)
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
10-11
Interrupt Controller (CF1_INTC)
Table 10-9. INTC_SWIACK, INTC_LVLnIACK Field Descriptions
Field
Description
7
Reserved, must be cleared.
6–0
VECN
Vector number. Indicates the appropriate vector number.
For the SWIACK register, it is the highest-level, highest-priority request currently being asserted in the CF1_INTC
module. If there are no pending requests, VECN is zero.
For the LVLnIACK register, it is the highest priority request within the specified level-n. If there are no pending
requests within the level, VECN is 0x18 (24) to signal a spurious interrupt.
10.3.7
Interrupt Request Level and Priority Assignments
This section provides multiple views of the interrupt request assignment: a two-dimensional view of levels
and priorities within the level (Table 10-11) and a tabular representation based on request priority
(Table 10-12).
The CF1_INTC module implements a sparsely-populated 7  9 matrix of levels (7) and priorities within
each level (9). In this representation, the leftmost top cell (level 7, priority 7) is the highest interrupt request
while the rightmost lowest cell (level 1, priority 0) is the lowest interrupt request. The following legend is
used for this table:
Table 10-10. Legend for Table 10-11
Interrupt Request
Source
Interrupt
Source
Number
Vector
Number
NOTE
For remapped and forced interrupts, the interrupt source number entry
indicates the register or register field that enables the corresponding
interrupt.
Table 10-11. ColdFire [Level][Priority within Level] Matrix Interrupt Assignments
Priority within Level
Level
7
6
5
4
—
—
—
—
Midpoint
IRQ_pin
7
remapped
PDB
2
1
0
Low_voltage Loss of lock
force_lvl7
—
0
remapped
3
64
1
DAC
65
2
SPI1
6
66
ADC
FRC[56] 103
USB_Status
force_lvl6
—
PL6P7
*
TPM1_ch0
PL6P6
*
TPM1_ch1
4
68
TPM1_ch2
5
69
6
TPM1_ch3
5
70
TPM1_ovfl
7
71
SPI2
8
67
CMT
FRC[57] 104
force_lvl5
—
9
73
10
74
11
75
12
76
13
77
14
78
15
79
FRC[58] 105
MCF51MM256 Series Devices Reference Manual, Rev. 3
10-12
Freescale Semiconductor
Interrupt Controller (CF1_INTC)
Table 10-11. ColdFire [Level][Priority within Level] Matrix Interrupt Assignments (Continued)
Priority within Level
Level
7
6
5
4
Midpoint
TPM2_ch0
TPM2_ch1
TPM2_ch2
TPM2_ch3
4
2
1
0
TPM2_ovfl
IIC
PRACMP
force_lvl4
—
16
80
SCI1_err
17
81
18
SCI1_rx
82
SCI1_tx
19
83
20
SCI2_err
84
21
SCI2_rx
3
87
24
88
25
KBI1
89
26
KBI2
90
32
96
SCI2_tx
91
28
33
—
—
FRC[59] 106
force_lvl3
92
FRC[60] 107
force_lvl2
—
—
—
97
FRC[61] 108
FTSR1
—
86
TOD
—
95
22
—
27
—
31
1
85
—
23
2
3
—
FTSR2
force_lvl1
—
—
41
112
42
113
FRC[62] 109
Table 10-12 presents the same information on interrupt request assignments, but from the highest priority
request to the lowest.
Table 10-12. V1 ColdFire Interrupt Assignments
Priority
Interrupt Source
within Level
Number
IRQ Source
Level
Vector
IRQ_pin
7
mid
0
64
low_voltage
7
3
1
65
loss_of_lock
7
2
2
66
Reserved
7
1
—
*
Force_lvl7
7
0
INTC_FRC[56]
103
Reserved for
remapped vector #1
6
7
INTC_PL6P7
*
Reserved for
remapped vector #2
6
6
INTC_PL6P6
*
PDB
6
5
4
68
DAC
6
4
5
69
SPI1
6
3
6
70
ADC
6
2
7
71
USB_status
6
1
8
72
force_lvl6
6
0
INTC_FRC[57]
104
tpm1_ch0
5
7
9
73
tpm1_ch1
5
6
10
74
tpm1_ch2
5
5
11
75
tpm1_ch3
5
4
12
76
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
10-13
Interrupt Controller (CF1_INTC)
Table 10-12. V1 ColdFire Interrupt Assignments (Continued)
Priority
Interrupt Source
within Level
Number
IRQ Source
Level
Vector
tpm1_ovfl
5
3
13
77
SPI2
5
2
14
78
CMT
5
1
15
79
force_lvl5
5
0
INTC_FRC[58]
105
tpm2_ch0
4
7
16
80
tpm2_ch1
4
6
17
81
tpm2_ch2
4
5
18
82
tpm2_ch3
4
4
19
83
tpm2_ovfl
4
3
20
84
IIC
4
2
21
85
PRACMP
4
1
22
86
force_lvl4
4
0
INTC_FRC[59]
106
SCI1_err
3
7
23
87
SCI1_rx
3
6
24
88
SCI1_tx
3
5
25
89
SCI2_err
3
4
26
90
SCI2_rx
3
3
27
91
SCI2_tx
3
2
28
92
Reserved
3
1
—
93
force_lvl3
3
0
INTC_FRC[60]
107
Reserved
2
7
—
94
KBI1
2
6
31
95
KBI2
2
5
32
96
TOD
2
4
33
97
Reserved
2
3
—
98
Reserved
2
2
—
99
Reserved
2
1
—
100
Force_lvl2
2
0
INTC_FRC[61]
108
Reserved
1
7
—
101
Reserved
1
6
—
102
Reserved
1
5
—
110
Reserved
1
4
—
111
MCF51MM256 Series Devices Reference Manual, Rev. 3
10-14
Freescale Semiconductor
Interrupt Controller (CF1_INTC)
Table 10-12. V1 ColdFire Interrupt Assignments (Continued)
10.4
Priority
Interrupt Source
within Level
Number
IRQ Source
Level
Vector
FTSR1
1
3
41
112
FTSR2
1
2
42
113
Reserved
1
1
—
114
Force_lvl1
1
0
INTC_FRC[62]
109
Functional Description
The basic operation of the CF1_INTC is detailed in the preceding sections. This section describes special
rules applicable to non-maskable level seven interrupt requests and the module’s interfaces.
10.4.1
Handling of Non-Maskable Level 7 Interrupt Requests
The CPU treats level seven interrupts as non-maskable, edge-sensitive requests, while levels one through
six are maskable, level-sensitive requests. As a result of this definition, level seven interrupt requests are
a special case. The edge-sensitive nature of these requests means the encoded 3-bit level input from the
CF1_INTC to the V1 ColdFire core must change state before the CPU detects an interrupt. A
non-maskable interrupt (NMI) is generated each time the encoded interrupt level changes to level seven
(regardless of the SR[I] field) and each time the SR[I] mask changes from seven to a lower value while the
encoded request level remains at seven.
10.5
Initialization Information
The reset state of the CF1_INTC module enables the default IRQ mappings and clears any software-forced
interrupt requests (INTC_FRC is cleared). Immediately after reset, the CF1_INTC begins its
cycle-by-cycle evaluation of any asserted interrupt requests and forms the appropriate encoded interrupt
level and vector information for the V1 Coldfire processor core. The ability to mask individual interrupt
requests using the interrupt controller’s IMR is always available, regardless of the level of a particular
interrupt request.
10.6
Application Information
This section discusses three application topics: emulation of the HCS08’s one level interrupt nesting
structure, elevating the priority of two IRQs, and more details on the operation of the software interrupt
acknowledge (SWIACK) mechanism.
10.6.1
Emulation of the HCS08’s 1-Level IRQ Handling
As noted in Table 10-1, the HCS08 architecture specifies a 1-level IRQ nesting capability. Interrupt
masking is controlled by CCR[I], the interrupt mask flag: clearing CCR[I] enables interrupts, while setting
CCR[I] disables interrupts. The ColdFire architecture defines seven interrupt levels, controlled by the 3-bit
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
10-15
Interrupt Controller (CF1_INTC)
interrupt priority mask field in the status register, SR[I], and the hardware automatically supports nesting
of interrupts.
To emulate the HCS08’s 1-level IRQ capabilities on V1 ColdFire, only two SR[I] settings are used:
• Writing 0 to SR[I] enables interrupts.
• Writing 7 to SR[I] disables interrupts.
The ColdFire core treats the level seven requests as non-maskable, edge-sensitive interrupts.
ColdFire processors inhibit interrupt sampling during the first instruction of all exception handlers. This
allows any handler to effectively disable interrupts, if necessary, by raising the interrupt mask level
contained in the status register as the first instruction in the ISR. In addition, the V1 instruction set
architecture (ISA_C) includes an instruction (STLDSR) that stores the current interrupt mask level and
loads a value into the SR. This instruction is specifically intended for use as the first instruction of an
interrupt service routine that services multiple interrupt requests with different interrupt levels. For more
details see the ColdFire Family Programmer’s Reference Manual. A MOVE-to-SR instruction also
performs a similar function.
To emulate the HCS08’s 1-level IRQ nesting mechanisms, the ColdFire implementation enables interrupts
by clearing SR[I] (typically when using RTE to return to a process) and disables interrupts upon entering
every interrupt service routine by one of three methods:
1. Execution of STLDSR #0x2700 as the first instruction of an ISR.
2. Execution of MOVE.w #0x2700,SR as the first instruction of an ISR.
3. Static assertion of CPUCR[IME] that forces the processor to load SR[I] with seven automatically
upon the occurrence of an interrupt exception. Because this method removes the need to execute
multi-cycle instructions of #1 or #2, this approach improves system performance.
10.6.2
Using INTC_PL6P{7,6} Registers
Section 10.3.2, “INTC Programmable Level 6, Priority {7,6} Registers (INTC_PL6P{7,6}),” describes
control registers that provide the ability to dynamically alter the request level and priority of two IRQs.
Specifically, these registers provide the ability to reassign two IRQs to be the highest level 6 (maskable)
requests. Consider the following example.
Suppose the system operation desires to remap the receive and transmit interrupt requests of a serial
communication device (SCI1) as the highest two maskable interrupts. The default assignments for the
SCI1 transmit and receive interrupts are:
• sci1_rx = interrupt source 25 = vector 88 = level 3, priority 6
• sci1_tx = interrupt source 26 = vector 89 = level 3, priority 5
To remap these two requests, the INTC_PL6P{7,6} registers are programmed with the desired interrupt
source number:
•
•
Setting INTC_PL6P7 to 25 (0x19), remaps sci1_rx as level 6, priority 7.
Setting INTC_PL6P6 to 26 (0x1A), remaps sci1_tx as level 6, priority 6.
The reset state of the INTC_PL6P{7,6} registers disables any request remapping.
MCF51MM256 Series Devices Reference Manual, Rev. 3
10-16
Freescale Semiconductor
Interrupt Controller (CF1_INTC)
10.6.3
More on Software IACKs
As previously mentioned, the notion of a software IACK refers to the ability to query the interrupt
controller near the end of an interrupt service routine (after the current interrupt request has been cleared)
to determine if there are any pending (but currently masked) interrupt requests. If the response to the
software IACK’s byte operand read is non-zero, the service routine uses the value as the vector number of
the highest pending interrupt request and passes control to the appropriate new handler. This process
avoids the overhead of a context restore and RTE instruction execution, followed immediately by another
interrupt exception and context save. In system environments with high rates of interrupt activity, this
mechanism can improve overall system performance noticeably.
To illustrate this concept, consider the following ISR code snippet shown in Figure 10-7.
align
4
irqxx_entry:
00588: 4fef fff0 lea
-16(sp),sp
0058c: 48d7 0303 movem.l #0x0303,(sp)
# allocate stack space
# save d0/d1/a0/a1 on stack
irqxx_alternate_entry:
00590:
....
005c0:
005c4:
005c8:
005ca:
005cc:
005d0:
71b8
0c00
6f0a
91c8
2270
4ee9
irqxx_swiack:
ffe0 mvz.b
INTC_SWIACK.w,d0
0041 cmpi.b #0x41,d0
ble.b
irqxx_exit
sub.l
a0,a0
0c00 move.l 0(a0,d0.l*4),a1
0008 jmp
8(a1)
align
4
irqxx_exit:
005d4: 4cd7 0303 movem.l (sp),#0x0303
005d8: 4fef 0010 lea
16(sp),sp
005dc: 4e73
rte
#
#
#
#
#
#
perform software IACK
pending IRQ or level 7?
no pending IRQ, then exit
clear a0
fetch pointer from xcpt table
goto alternate isr entry point
# restore d0/d1/a0/a1
# deallocate stack space
# return from handler
Figure 10-7. ISR Code Snippet with SWIACK
This snippet includes the prologue and epilogue for an interrupt service routine as well as code needed to
perform software IACK.
At the entry point (irqxx_entry), there is a two-instruction prologue to allocate space on the supervisor
stack to save the four volatile registers (d0, d1, a0, a1) defined in the ColdFire application binary interface.
After saving these registers, the ISR continues at the alternate entry point.
The software IACK is performed near the end of the ISR, after the source of the current interrupt request
is negated. First, the appropriate memory-mapped byte location in the interrupt controller is read
(PC = 0x5C0). The CF1_INTC module returns the vector number of the highest priority pending request.
If no request is pending, zero is returned. The compare instruction is needed to manage a special case
involving pending level seven requests. Because the level seven requests are non-maskable, the ISR is
interrupted to service one of these requests. To avoid any race conditions, this check ignores the level seven
vector numbers. The result is the conditional branch (PC = 0x5C8) is taken if there are no pending requests
or if the pending request is a level seven.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
10-17
Interrupt Controller (CF1_INTC)
If there is a pending non-level seven request, execution continues with a three instruction sequence to
calculate and then branch to the appropriate alternate ISR entry point. This sequence assumes the
exception vector table is based at address 0x(00)00_0000 and that each ISR uses the same two-instruction
prologue shown here. The resulting alternate entry point is a fixed offset (8 bytes) from the normal entry
point defined in the exception vector table.
The ISR epilogue includes a three instruction sequence to restore the volatile registers from the stack and
return from the interrupt exception.
This example is intentionally simple, but does show how performing the software IACK and passing
control to an alternate entry point when there is a pending but masked interrupt request can avoid the
execution of the ISR epilogue, another interrupt exception, and the ISR prologue.
MCF51MM256 Series Devices Reference Manual, Rev. 3
10-18
Freescale Semiconductor
Chapter 11
Programmable Analog Comparator (S08PRACMPV1)
11.1
Introduction
The PRACMP is a CMOS comparator with a programmable reference input. The comparator has up to
four (4) input pins, each of them can be compared with any input pins. An internal programmable reference
generator divides the Vin into 32 levels; the Vin can be selected from two external sources. Output of this
reference generator can be one of the eight selectable inputs to the comparator. The comparator circuit is
designed to operate across the full range of the supply voltage (rail-to-rail operation).
11.1.1
PRACMP Configuration Information
When using the bandgap reference voltage for input to PRACMP, enable the VREF output to supply a
reference signal to the PRACMP. See the VREF module chapter for information on how to enable the
VREF output. For the value of the bandgap voltage reference, see the data sheet for this device.
NOTE
For these devices, Vin2 is connected to VREFO. Therefore, the PRGINS bit
in the PRACMPC1 register selects:
•
•
11.1.2
VREFO when PRGINS=0
VDD when PRGINS=1
PRACMP/TPM Configuration Information
The PRACMP module can be configured to connect the output of the analog comparator to TPM1 input
capture channel 0 by setting the ACIC bit in SOPT2. With ACIC set, the TPM1CH0 pin is not available
externally regardless of the configuration of the TPM1 module.
11.1.3
PRACMP/OPAMP Configuration Information
The OPAMP can provide internal or external input to the PRACMP.
11.1.4
PRACMP Clock Gating
Use the PRACMP bit in the SCGC2 register to gate on and off the bus clock to the PRACMP module. This
bit is set after any reset which enables the bus clock to this module. To conserve power, clear the PRACMP
bitto disable the clock to this module when not in use. See 5.6, “Peripheral Clock Gating,” for details.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
11-1
Programmable Analog Comparator (S08PRACMPV1)
Figure 11-1. Block Diagram Highlighting PRACMP Block and Pins
/
MCF51MM256 Series Devices Reference Manual, Rev. 3
11-2
Freescale Semiconductor
Programmable Analog Comparator (S08PRACMPV1)
11.1.5
Features
PRACMP features include:
• MCF51MM256 series On-chip programmable reference generator output (1/32 Vin to Vin, step is
1/32 Vin, Vin can be selected from external VDD and internal VREFO)
• Typically 5 mV of input offset
• Less than 40 A in enable mode and less than 1 nA in disable mode (excluding programmable
reference generator)
• Fixed ACMP hysteresis which is from 3 mV to 20 mV
• Up to eight selectable comparator inputs; each input can be compared with any input by any
polarity sequence
• Selectable interrupt on rising edge, falling edge, or either rising or falling edges of comparator
output
• Remains operational in stop3 mode
11.1.6
Modes of Operation
This section defines the PRACMP operation in wait, stop, and background debug modes.
11.1.6.1
Operation in Wait Mode
The PRACMP continues to operate in wait mode if enabled. The interrupt can wake up the MCU if
enabled.
11.1.6.2
Operation in Stop Mode
The PRACMP (including PRG and ACMP) continues to operate in stop3 mode if enabled. If ACIEN is
set, a PRACMP interrupt still can be generated to wake the MCU up from stop3 mode.
If the stop3 is exited by an interrupt, the PRACMP remains the setting before entering the stop. If stop3 is
exited with a reset, the PRACMP goes into its reset.
To conserve power, turn it off if its output is not used as a reference input of ACMP, because the PRG
consumes additional power.
In stop2 mode, the PRACMP is shut down completely. Any waking up from stop2 brings PRACMP to its
reset state.
11.1.6.3
Operation in Background Mode
When the MCU is in active background debug mode, the PRACMP continues operating normally.
11.1.7
Block Diagram
The block diagram of the PRACMP module is shown in Figure 11-2.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
11-3
Programmable Analog Comparator (S08PRACMPV1)
External VDD Internal VREFO
PRGINS
Vin2
Vin1
PRGOS[4:0]
MUX
Vin
PRG output
MUX
32-level
PRGEN
Enable ACMP output pin
ACOPE
PRG
Enable ACMP Input Pins
ACIPEN[6:0]
ACEN
ACPSEL[2:0]
ACMP
MUX
External Reference 0
External Reference 1
External Reference 2
External Reference 3
External Reference 4
External Reference 5
External Reference 6
ACMPO
+
Output
–
Edge Detection
MUX
ACIEN
MUX
ACMPF
Interrupt
ACINTS[1:0]
Stop mode
ACNSEL[2:0]
Figure 11-2. PRACMP Block Diagram
11.2
External Signal Description
The output of PRACMP can also be mapped to an external pin. When the output is mapped to an external
pin, register bit ACOPE controls the pin to enable/disable the PRACMP output function.
MCF51MM256 Series Devices Reference Manual, Rev. 3
11-4
Freescale Semiconductor
Programmable Analog Comparator (S08PRACMPV1)
11.3
Memory Map and Register Definition
Table 11-1 is the memory map of the programmable reference analog comparator (PRACMP).
Table 11-1. Module Memory Map
Address
Use
Access
Base + $0
PRACMP Control and Status Register (PRACMPCS)
Read/Write
Base + $1
PRACMP Control Register 0 (PRACMPC0)
Read/Write
Base + $2
PRACMP Control Register 1 (PRACMPC1)
Read/Write
Base + $3
PRACMP Control Register 2 (PRACMPC2)
Read/Write
Refer to the direct-page register summary in the memory chapter of this reference manual for the absolute
address assignments for all PRACMP registers.
11.3.1
PRACMP Control and Status Register (PRACMPCS)
7
6
5
ACEN
ACMPF
0
0
4
3
2
1
0
ACMPO
R
ACOPE
ACINTS
ACIEN
W
Reset
0
0
0
0
0
0
Unimplemented or Reserved
Figure 11-3. PRACMP Control and Status Register (PRACMPCS)
Table 11-2. PRACMPCS Descriptions
Field
7
ACEN
Description
ACMP enable control bit
0 The ACMP is disabled
1 The ACMP is enabled
6
ACMPF
ACMP Interrupt Flag Bit — Synchronously set by hardware when ACMP output has a valid edge defined by
ACINTS[1:0]. The setting of this bit lags the ACMPO 2 bus clocks. Clear ACMPF bit by writing a 0 to this bit.
Writing a 1 to this bit has not effect.
4
ACOPE
ACMP Output Pin Enable — ACOPE enables the pad logic so that the output can be placed onto an external pin
0 Output of ACMP can’t be placed onto external pin
1 Output of ACMP can be placed onto external pin
3
ACMPO
ACMP Output Bit — ACMP output is synchronized by bus clock to form this bit. It changes following the ACMP
output. This bit is a read only bit.
• Set when the output of the ACMP is high
• Cleared when the output of the ACMP is low
• After any reset or when the ACMP is disabled, this bit is read as 0.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
11-5
Programmable Analog Comparator (S08PRACMPV1)
Table 11-2. PRACMPCS Descriptions (Continued)
Field
2:1
ACINTS
[1:0]
0
ACIEN
11.3.2
Description
ACMP Interrupt Select — Determines the sensitivity modes of the interrupt trigger.
00 ACMP interrupt on output falling or rising edge
01 ACMP interrupt on output falling edge
10 ACMP interrupt on output rising edge
11 Reserved
ACMP Interrupt Enable — Enables an ACMP CPU interrupt
1 Enable the ACMP Interrupt
0 Disable the ACMP Interrupt
PRACMP Control Register 0 (PRACMPC0)
7
6
5
4
3
2
R
1
0
ACNSEL1
ACPSEL
W
Reset
0
0
0
0
0
0
0
0
Unimplemented or Reserved
Figure 11-4. PRACMP Control Register 0 (PRACMPC0)
1
Selects negative input, same as ACPSEL
Table 11-3. PRACMPC0 Field Descriptions
Field
1
Description
6:4
ACPSEL[2:0]
ACMP Positive Input Select1
000 External reference 0, CMPP0
001 External reference 1, CMPP1
010 External reference 2, CMPP2
011 External reference 3, CMPP3
100 GPAMP1 Output , OPAMP OUT1
101 GPAMP2 Output , OPAMP OUT2
110 Buffered Bandgap Voltage , PMC bandgap VREF
111 Internal PRG output, external VDD, VREF out
2:0
ACNSEL[2:0]
ACMP Negative Input Select1
000 External reference 0, CMPP0
001 External reference 1, CMPP1
010 External reference 2, CMPP2
011 External reference 3, CMPP3
100 GPAMP1 Output , OPAMP OUT1
101 GPAMP2 Output , OPAMP OUT2
110 Buffered Bandgap Voltage , PMC bandgap VREF
111 Internal PRG output, external VDD, VREF out
Do not configure ACPSEL and ACNSEL to use the same value to operate the comparator. Selecting the same channel for the
comparator may cause an unstable oscilliation on the output of the comparator.
MCF51MM256 Series Devices Reference Manual, Rev. 3
11-6
Freescale Semiconductor
Programmable Analog Comparator (S08PRACMPV1)
11.3.3
PRACMP Control Register 1 (PRACMPC1)
7
6
5
PRGEN
PRGINS
0
0
4
3
2
1
0
PRGOS4
PRGOS3
PRGOS2
PRGOS1
PRGOS0
0
0
0
0
0
R
W
Reset
0
Unimplemented or Reserved
Figure 11-5. PRACMP Control Register 1 (PRACMPC1)
Table 11-4. PRACMPC1 Field Descriptions
Field
Description
7
PRGEN
Programmable Reference Generator Enable — The PRGEN bit starts the Programmable Reference
Generator operation.
0 The PRG system is disabled
1 The PRG system is enabled
6
PRGINS
Programmable Reference Generator Input Selection
0 The PRG selects VREF out (~1.2V) as the reference voltage
1 The PRG selects Vin1 (external power supply)as the reference voltage
4:0
PRGOS[4:0]
Programmable Reference Generator Output Selection — The output voltage is selected by the following
formula:
Voutput= (Vin/32)x(PRGOS[4:0]+1)
The Voutput range is from Vin/32 to Vin, the step is Vin/32
Table 11-5 lists the output configuration of programmable reference generator (PRG).
Table 11-5. PRG Out Configuration
PRGOS[4:0]
Output Voltage of PRG
00000
1VIn/32
00001
2VIn/32
00010
3VIn/32
00011
4VIn/32
00100
5VIn/32
00101
6VIn/32
00110
7VIn/32
00111
8VIn/32
01000
9VIn/32
01001
10VIn/32
01010
11VIn/32
01011
12VIn/32
01100
13VIn/32
01101
14VIn/32
01110
15VIn/32
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
11-7
Programmable Analog Comparator (S08PRACMPV1)
Table 11-5. PRG Out Configuration (Continued)
11.3.4
Output Voltage of PRG
01111
16VIn/32
10000
17VIn/32
10001
18VIn/32
10010
19VIn/32
10011
20VIn/32
10100
21VIn/32
10101
22VIn/32
10110
23VIn/32
10111
24VIn/32
11000
25VIn/32
11001
26VIn/32
11010
27VIn/32
11011
28VIn/32
11100
29VIn/32
11101
30VIn/32
11110
31VIn/32
11111
VIn
PRACMP Control Register 2 (PRACMPC2)
7
R
PRGOS[4:0]
6
5
4
3
2
1
0
ACIPE6
ACIPE5
ACIPE4
ACIPE3
ACIPE2
ACIPE1
ACIPE0
0
0
0
0
0
0
0
0
W
Reset
0
Unimplemented or Reserved
Figure 11-6. PRACMP Control Register 2 (PRACMPC2)
Table 11-6. PRACMPC2 Field Descriptions
Field
Description
6:0
ACMP Input Pin Enable — This 7-bit register controls if the corresponding PRACMP external pin can be driven
ACIPE6:ACIPE0 an analog input.
0 The corresponding external analog input is not allowed
1 The corresponding external analog input is allowed
11.4
Functional Description
The PRACMP module is functionally composed of two parts: programmable reference generator (PRG)
and analog comparator (ACMP).
MCF51MM256 Series Devices Reference Manual, Rev. 3
11-8
Freescale Semiconductor
Programmable Analog Comparator (S08PRACMPV1)
The programmable reference generator (PRG) includes a 32-level DAC (digital to analog convertor) and
relevant control logic. PRG can select one of two reference inputs, Vin1(external Vdd) or Vin2(internal
regulated Vdd), as the DAC input Vin by setting PRGINS bit of PRACMPC1. After the DAC is enabled,
it converts the data set in PRGOS[4:0] bits of PRACMPC1 to a stepped analog output which is fed into
ACMP as an internal reference input. This stepped analog ouput is also mapped out of the module. The
output voltage range is from Vin/32 to Vin..The step size is Vin/32.
The ACMP can achieve the analog comparison between positive input and negative input, and then give
out a digital output and relevant interrupt. Both the positive and negative input of ACMP can be selected
from the eight common inputs: seven external reference inputs and one internal reference input from the
PRG output. The positive input of ACMP is selected by ACPSEL[2:0] bits of PRACMPC0 and the
negative input is selected by ACNSEL[2:0] bits of PRACMPC0. Any pair of the eight inputs can be
compared by configuring the PRACMPC0 with the appropriate value.
After the ACMP is enabled by setting ACEN in PRACMPCS, the comparison result appears as a digital
output. Whenever a valid edge defined in ACINTS[1:0] occurs, the ACMPF bit in PRACMPCS register
is asserted. If ACIEN is set, a PRACMP CPU interrupt occurs. The valid edge is defined by
ACINTS[1:0].When ACINTS[1:0] = 00, both the rising edge and falling edge on the ACMP output are
valid. When ACINTS[1:0] = 01, only the falling edge on ACMP output is valid. When ACINTS[1:0] =
10, only rising edge on ACMP output is valid. ACINTS[1:0] = 11 is reserved.
The ACMP output is synchronized by the bus clock to generate ACMPO bit in PRACMPCS so that the
CPU can read the comparison. In stop3 mode if the output of ACMP is changed, ACMPO can’t be updated
in time. The output can be synchronized and the ACMPO bit can be updated upon the waking up of the
CPU because of the availability of the bus clock. The ACMPO changes following the comparison result,
so it can serve as a tracking flag that continuously indicates the voltage delta on the inputs.
If a reference input external to the chip is selected as an input of ACMP, the corresponding ACIPE bit of
PRACMPC2 should be set to enable the input from pad interface. If the output of the ACMP needs to be
put onto the external pin, the ACOPE bit of PRACMPCS must enable the ACMP pin function of pad logic.
11.5
Setup and Operation of PRACMP
The two parts of PRACMP (PRG and ACMP) can be set up and operated independently. But if the PRG
works as an input of the ACMP, the PRG must be configured before the ACMP is enabled.
Because the input-switching can cause problems on the ACMP inputs, the user should complete the input
selection before enabling the ACMP and should not change the input selection setting when the ACMP is
enabled to avoid unexpected output. Similarly, because the programmable reference generator (PRG)
experiences a setup delay after the PRGOS[4:0] is changed, the user should complete the setting of
PRGOS[4:0] before PRG is enabled.
11.6
Resets
During a reset the PRACMP is configured in the default mode. Both ACMP and PRG are disabled.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
11-9
Programmable Analog Comparator (S08PRACMPV1)
11.7
Interrupts
NOTE
If the bus clock is available when a valid edge (as defined in ACINTS[1:0])
occurs, the ACMPF bit in PRACMPCS register is asserted.
•
•
If ACIEN is set, a PRACMP interrupt event occurs. The ACMPF bit
remains asserted until the PRACMP interrupt is cleared by software
When in stop3 mode, a valid edge on ACMP output generates an
asynchronous interrupt which can wake the MCU up from stop3. To
clear the interrupt, write a 0 to the ACMPF bit.
MCF51MM256 Series Devices Reference Manual, Rev. 3
11-10
Freescale Semiconductor
Chapter 12
Analog-to-Digital Converter (S08ADC16V1)
12.1
Introduction
The 16-bit analog-to-digital converter (ADC) is a successive approximation ADC designed for operation
within an integrated microcontroller system-on-chip.
Figure 12-2 shows the block diagram with the ADC module highlighted.
12.1.1
Status and Control and Result Registers
This series of devices contains 8 Status and Control 1 registers and 8 result registers. These registers allow
up to eight ADC conversions to occur without CPU intervention using hardware triggering. Hardware
trigger operation is supported with the PDB peripheral.
12.1.2
ADC and TRIAMP Configuration
The DADP2/DADM2 and DADP3/DADM3 pins are internally connected to the TRIOUTx /VINNx pins
of the Trans-Impedance Amplifier (TRIAMP) peripheral. When deferential conversions are completed for
these pins, it allows the voltage across an external feedback resistor to be analyzed.
12.1.3
Dedicated ADC Pins
The DADPn and DADMn pins are dedicated differential ADC pins.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
12-1
Analog-to-Digital Converter (S08ADC16V1)
12.1.4
ADC Reference Selection
This device has the ability to select from several different reference voltages for the ADC. The following
table describes the options available for this device.
f
Table 12-1. Reference Assignment
REFSEL
Reference Source
00
PAD, VREFH, VREFL
01
Internal VREF module
10
PMC bandgap
11
Reserved
REFSEL is at the lowest 2 bits of register ADCSC2 and selects the voltage reference for the ADC.
• If REFSEL = 00, then PAD, VREFL, and VREFH act as the ADC conversion reference.
• If REFSEL = 01, then the internal VREF module output acts as the ADC conversion reference.
• If REFSEL = 10, then 1.2 V PMC bandgap output acts as the ADC conversion reference.
• If REFSEL = 11 (reserved), then selects the default voltage reference same as REFSEL = 2’b00.
12.1.5
Module Configurations
This section provides device-specific information for configuring the ADC.
12.1.5.1
Configurations for Stop Modes
The ADC, if enabled, must be configured to use the asynchronous clock source, ADACK, to meet the ADC
minimum frequency requirements. The VREF output must be enabled in order to convert the bandgap
channel in stop mode.
MCF51MM256 Series Devices Reference Manual, Rev. 3
12-2
Freescale Semiconductor
Analog-to-Digital Converter (S08ADC16V1)
12.1.5.2
Differential Channel Assignments
The ADC differential channel assignments for the devices are shown in Table 12-2. Differential channels
are selected when the DIFFn bit in the corrensponding ADSC1n register is set (DIFFn= 1). Reserved
channels convert to an unknown value.
Table 12-2. ADC Differential Channel Assignment
1
ADCH
Channel
Input
Pin Control
ADCH
Channel
Input
Pin Control
00000
DAD0
DADP0 and DADM0
ADPC0
10000
R
Reserved
N/A
00001
DAD1
DADP1 and DADM1
ADPC1
10001
R
Reserved
N/A
00010
DAD2
DADP2 and DADM2
ADPC2
10010
R
Reserved
N/A
00011
DAD3
DADP3 and DADM3
ADPC3
10011
R
Reserved
N/A
00100
R
Reserved
N/A
10100
R
Reserved
N/A
00101
R
Reserved
N/A
10101
R
Reserved
N/A
00110
R
Reserved
N/A
10110
R
Reserved
N/A
00111
R
Reserved
N/A
10111
R
Reserved
N/A
01000
R
Reserved
N/A
11000
R
Reserved
N/A
01001
R
Reserved
N/A
11001
R
Reserved
N/A
01010
R
Reserved
N/A
11010
Temp-Diff
erential
Temperature
Sensor1
N/A
01011
R
Reserved
N/A
11011
Bandgap
PMC Bandgap
N/A
01100
R
Reserved
N/A
11100
R
Reserved
N/A
01101
R
Reserved
N/A
11101
VREFH
VREFH
N/A
01110
R
Reserved
N/A
11110
R
Reserved
N/A
01111
R
Reserved
N/A
11111
Module
Disabled
None
N/A
1 For information, see Section 12.1.5.6, “Temperature Sensor.”
12.1.5.3
Single-Ended Channel Assignments
The ADC single-ended channel assignments for the devices are shown in Table 12-3. Single-ended
channels are selected when the DIFFn bit in the corrensponding ADSC1n register is cleared (DIFFn= 0).
Reserved channels convert to an unknown value.
Table 12-3. ADC Single-Ended Channel Assignment
ADCH
Channel
Input
Pin Control
ADCH
Channel
Input
Pin Control
00000
DADP0
DADP0
ADPC0
10000
AD16
OUT2(from OPAMP)
ADPC16
00001
DADP1
DADP1
ADPC1
10001
AD17
DACO
ADPC17
00010
DADP2
TRIOUT1/DADP2
ADPC2
10010
AD18
Reserved
ADPC18
00011
DADP3
TRIOUT2/DADP3
ADPC3
10011
AD19
Reserved
ADPC19
00100
AD4
PTA2/KBI1P1/RX1/ADP4
ADPC4
10100
AD20
Reserved
ADPC20
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
12-3
Analog-to-Digital Converter (S08ADC16V1)
Table 12-3. ADC Single-Ended Channel Assignment (Continued)
1
ADCH
Channel
Input
Pin Control
ADCH
Channel
Input
Pin Control
00101
AD5
PTA3/KBI1P2/FB_D6/ADP5
ADPC5
10101
AD21
Reserved
ADPC21
00110
AD6
PTC2/KBI1P5/SPSCK2/ADP6
ADPC6
10110
AD22
Reserved
ADPC22
00111
AD7
PTC3/KBI1P6/SS2/ADP7
ADPC7
10111
AD23
Reserved
ADPC23
01000
AD8
PTC4/KBI1P7/CMPP0/ADP8
ADPC8
11000
AD24
VREFO
ADPC24
01001
AD9
PTC5/KBI2P0/CMPP1/ADP9
ADPC9
11001
R
Reserved
N/A
01010
AD10
PTC6/KBI2P1/PACMPO/ADP10
ADPC10
11010
Temp
Single-ended
Temperature
Sensor1
N/A
01011
AD11
PTC7/KBI2P2/CLKOUT/ADP11
ADPC11
11011
Bandgap
PMC Bandgap
N/A
01100
AD12
Reserved
N/A
11100
R
Reserved
N/A
01101
AD13
Reserved
N/A
11101
VREFH
VREFH
N/A
01110
AD14
ACMP_OUT
ADPC14
11110
VREFL
VREFL
N/A
01111
AD15
OUT1 (from OPAMP)
ADPC15
11111
Module
Disabled
None
N/A
For information, see Section 12.1.5.6, “Temperature Sensor.”
NOTE
Enable the VREF output to supply the bandgap voltage. See Chapter 28,
“Voltage Reference Module (S08VREFV1),” for information on how to
enable the VREF output. For the value of the bandgap voltage reference,
see the data sheet.
12.1.5.4
Alternate Clock
The ADC is capable of performing conversions using the MCU bus clock, the bus clock divided by two,
the local asynchronous clock (ADACK) within the module, or the alternate clock (ALTCLK). The
ALTCLK is connected to the MCGERCLK. See Chapter 17, “Multipurpose Clock Generator
(S08MCGV3)” for more information.
12.1.5.5
Hardware Triggers
The ADC hardware trigger can be provided from the:
• Time of Day (TOD) module
• Programmable Delay Block (PDB)
The ADCTRS bit from the SIMIPS register selects the hardware trigger source.
The PDB can be configured to generate up to eight hardware trigger select signals. The ADC hardware
trigger select signals pre-select one of the eight ADCSC1n registers as the source for the next ADC
conversion.
MCF51MM256 Series Devices Reference Manual, Rev. 3
12-4
Freescale Semiconductor
Analog-to-Digital Converter (S08ADC16V1)
12.1.5.6
Temperature Sensor
The ADC module includes a temperature sensor whose output is connected to one of the ADC analog
channel inputs. Equation 12-1 provides an approximate transfer function of the temperature sensor.
Temp = 25 - ((VTEMP -VTEMP25)  m)
Eqn. 12-1
where:
— VTEMP is the voltage of the temperature sensor channel at the ambient temperature.
— VTEMP25 is the voltage of the temperature sensor channel at 25C.
— m is the hot or cold voltage versus temperature slope in V/C.
For temperature calculations, use the VTEMP25 and m values in the data sheet.
Have your application code, read the temperature sensor channel, calculate VTEMP, and compare it to
VTEMP25. If VTEMP is greater than VTEMP25, the cold slope value is applied in Equation 12-1. If VTEMP
is less than VTEMP25, the hot slope value is applied in Equation 12-1.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
12-5
Analog-to-Digital Converter (S08ADC16V1)
Figure 12-1. Block Diagram Highlighting ADC Block and Pins
MCF51MM256 Series Devices Reference Manual, Rev. 3
12-6
Freescale Semiconductor
Analog-to-Digital Converter (S08ADC16V1)
12.1.6
ADC Clock Gating
The bus clock to the ADC can be gated on and off using the ADC bit in SCGC1. This bit is set after any
reset which enables the bus clock to this module. To conserve power, the ADC bit can be cleared to disable
the clock to this module when not in use. See Section 5.7.7, “System Clock Gating Control 1 Register
(SCGC1),” for details.
12.1.7
Features
Features of the ADC module include:
• Linear successive approximation algorithm with up to 16-bit resolution
• Up to four pairs of differential and 24 single-ended external analog inputs
• Output Modes:
— Differential 16-bit, 13-bit, 11-bit, and 9-bit modes
— Single-ended 16-bit, 12-bit, 10-bit, and 8-bit modes
• Output formatted in 2s complement 16b sign extended for differential modes
• Output in right-justified unsigned format for single-ended
• Single or continuous conversion (automatic return to idle after single conversion)
• Configurable sample time and conversion speed/power
• Conversion complete / Hardware average complete flag and interrupt
• Input clock selectable from up to four sources
• Operation in wait or stop3 modes for lower noise operation
• Asynchronous clock source for lower noise operation with option to output the clock
• Selectable asynchronous hardware conversion trigger with hardware channel select
• Automatic compare with interrupt for less-than, greater-than or equal-to, within range, or
out-of-range, programmable value
• Temperature sensor
• Hardware average function
• Selectable voltage reference
— Internal
— External
— Alternate
• Self-Calibration mode
12.1.8
Block Diagram
Figure 12-2 provides a block diagram of the ADC module.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
12-7
Analog-to-Digital Converter (S08ADC16V1)
ADHWTSA
ADCSC1A
Conversion
Trigger
Control
ADHWTSn
ADHWT
ADCSC1n
ADTRG
Compare true 1
ADACKEN
Async
Clock Gen
ADICLK
ADIV
ADLPC/ADHSC
ADLSMP/ADLSTS
ADCO
MODE
trigger
DDIFFn
complete
AIENn
COCOn
ADCHn
Control Registers (ADCSC2, ADCCFG1, ADCCFG2)
Interrupt
ADCK
MCU STOP
AD23
TempP
Bus Clock

ALTCLK
abort
convert
transfer
DADP3
AD4
initialize
DADP0
sample
Control Sequencer
ADACK
Clock
Divide
ADVINP
PG, MG
ADVINM
CLPx
CLMx
Calibration
ADCOFS
CAL
AVGE, AVGS
VREFSH
Averager
Formatting
CALF
ADCSC3
MODE, DIFFn
ADCCFG1,2
D
ADCRHA:ADCRLA
transfer
VREFSL
VREFL
VALTL
VBGL
ADCCLMx
OFS
Offset Subtractor
DADM3
VREFH
VALTH
VBGH
ADCCLPx
SAR Converter
DADM0
TempM
ADCxG
ADCRHn:ADCRLn
ACFE
ACFGT, ACREN
Compare true
Compare
Logic
CV1
ADCSC2
1
CV2
ADCCV1, ADCCV2
Figure 12-2. ADC Block Diagram
12.2
External Signal Description
The ADC module supports up to four pairs of differential inputs and 24 single-ended inputs. Each
differential pair requires two inputs, DADPx and DADMx.The ADC also requires four
supply/reference/ground connections.
Table 12-4. Signal Properties
Name
Function
DADP0-DADP3
Differential Analog Channel Inputs
DADM0-DADM3
Differential Analog Channel Inputs
MCF51MM256 Series Devices Reference Manual, Rev. 3
12-8
Freescale Semiconductor
Analog-to-Digital Converter (S08ADC16V1)
Table 12-4. Signal Properties (Continued)
12.2.1
Name
Function
AD4–AD23
Analog Channel inputs
VREFSH
Voltage Reference Select High
VREFSL
Voltage Reference Select Low
VDDAD
Analog power supply
VSSAD
Analog ground
Analog Power (VDDAD)
The ADC analog portion uses VDDAD as its power connection. In some packages, VDDAD is connected
internally to VDD. If externally available, connect the VDDAD pin to the same voltage potential as VDD.
External filtering may be necessary to ensure clean VDDAD for good results.
12.2.2
Analog Ground (VSSAD)
The ADC analog portion uses VSSAD as its ground connection. In some packages, VSSAD is connected
internally to VSS. If externally available, connect the VSSAD pin to the same voltage potential as VSS.
12.2.3
Voltage Reference Select High (VREFSH)
VREFSH is the high-reference voltage for the converter.
The ADC can be configured to accept one of three voltage reference pairs for VREFSH. Each pair contains
a positive reference which must be between the minimum Ref Voltage High (defined in) and VDDAD, and
a ground reference which must be at the same potential as VSSAD.
The three pairs are:
• external (VREFH and VREFL)
• alternate (VALTH and VALTL)
• internal bandgap (VBGH and VBGL)
These voltage references are selected using the REFSEL bits in the ADCSC2 register.The alternate (VALTH
and VALTL) voltage reference pair may select additional external pins or internal sources depending on
MCU configuration.Consult the module introduction for information on the Voltage References specific
to this MCU.
In some packages, VREFH is connected in the package to VDDAD. If externally available, the positive
reference(s) may be connected to the same potential as VDDAD or may be driven by an external source to
a level between the minimum Ref Voltage High (defined in the Data Sheet) and the VDDAD potential
(VREFH must never exceed VDDAD).
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
12-9
Analog-to-Digital Converter (S08ADC16V1)
12.2.4
Voltage Reference Select Low (VREFL)
VREFSL is the low reference voltage for the converter.The ADC can be configured to accept one of three
voltage reference pairs for VREFSL. Each pair contains a positive reference which must be between the
minimum Ref Voltage High (defined in Appendix A) and VDDAD, and a ground reference which must be
at the same potential as VSSAD. The three pairs are external (VREFH and VREFL), alternate (VALTH and
VALTL) and the internal bandgap (VBGH and VBGL). These voltage references are selected using the
REFSEL bits.The alternate (VALTH and VALTL) voltage reference pair may select additional external pins
or internal sources depending on MCU configuration.Consult the module introduction for information on
the Voltage References specific to this MCU.
In some packages, VREFL is connected in the package to VSSAD. If externally available, connect the ground
reference(s) to the same voltage potential as VSSAD.
12.2.5
Analog Channel Inputs (ADx)
The ADC module supports up to 24 single-ended analog inputs. A single-ended input is selected for
conversion through the ADCHn channel select bits when the DIFFn bit in the ADCSC1n register is low.
12.2.6
Differential Analog Channel Inputs (DADx)
The ADC module supports up to four differential analog channel inputs. Each differential analog input is
a pair of external pins (DADPx and DADMx) referenced to each other to provide the most accurate analog
to digital readings. A differential input is selected for conversion through the ADCHn channel select bits
when the DIFFn bit in the ADCSC1n register bit is high.
12.3
Register Definition
These memory-mapped registers control and monitor operation of the ADC:
•
•
•
•
•
•
•
•
•
•
•
•
Status and channel control registers, ADCSC1A:ADCSC1n
Configuration registers, ADCCFG1 and ADCCFG2
Data result registers, ADCRHA:ADCRLA to ADCRHn:ADCRLn
Compare value registers, ADCCV1H, ADCCV1L, ADCCV2H, and ADCCV2L
General status and control registers, ADCSC2 and ADCSC3
Configuration registers, ADCCFG1 and ADCCFG2
Offset Correction Registers, ADCOFSH and ADCOFSL
Plus-input gain registers, ADCPGH and ADCPGL
Minus-input gain registers, ADCMGH and ADCMGL
Plus-side general calibration registers, ADCCLP0, ADCCLP1, ADCCLP2, ADCCLP3H,
ADCCLP3L, ADCCLP4H, ADCCLP4L, ADCCLSP, ADCCLDP
Minus-side general calibration registers, ADCCLM0, ADCCLM1, ADCCLM2, ADCCLM3H,
ADCCLM3L, ADCCLM4H, ADCCLM4L, ADCCLSM, ADCCLDM
Pin enable registers, APCTL1, APCTL2
MCF51MM256 Series Devices Reference Manual, Rev. 3
12-10
Freescale Semiconductor
Analog-to-Digital Converter (S08ADC16V1)
12.3.1
Status and Control Registers 1 (ADCSC1A:ADCSC1n)
This section describes the function of the ADC status and channel control registers, ADCSC1A through
ADCSC1n. ADCSC1A is used for both software and hardware trigger modes of operation.
ADCSC1B-ADCSC1n indicate potentially multiple ADCSC1 registers for use only in hardware trigger
mode. Consult the module introduction for information on the number of ADCSC1n registers specific to
this MCU. The ADCSC1A to ADCSC1n registers have identical fields, and are used in a “ping-pong”
approach to control ADC operation. At any one point in time, only one of the ADCSC1A to ADCSC1n
registers is actively controlling ADC conversions. Updating ADCSC1A while ADCSC1n is actively
controlling a conversion is allowed (and vice-versa for any of the ADCSC1n registers specific to this
MCU). Writing ADCSC1A while ADCSC1A is actively controlling a conversion aborts the current
conversion. In software trigger mode (ADTRG=0), writes to ADCSC1A subsequently initiates a new
conversion (if the ADCHn bits are equal to a value other than all 1s). Similarly, writing any of the
ADCSC1n registers while that specific ADCSC1n register is actively controlling a conversion aborts the
current conversion. Any of the ADCSC1B -ADCSC1n registers are not used for software trigger operation
and therefore writes to the ADCSC1B -ADCSC1n registers do not initiate a new conversion.
7
R
6
5
AIENn
DIFFn
0
0
4
3
2
1
0
1
1
COCOn
ADCHn
W
Reset:
0
1
1
1
Figure 12-3. Status and Channel Control Register 1n (ADCSC1n)
Table 12-5. ADCSC1:ADCSC1n Field Descriptions
Field
Description
7
COCOn
Conversion Complete Flag - The COCOn flag is a read-only bit that is set each time a conversion is completed
when the compare function is disabled (ACFE=0) and the hardware average function is disabled (AVGE=0).
When the compare function is enabled (ACFE=1), the COCOn flag is set upon completion of a conversion only
if the compare result is true. When the hardware average function is enabled (AVGE=1), the COCOn flag is set
upon completion of the selected number of conversions (determined by the AVGS bits). The COCO1 flag will also
set at the completion of a Calibration sequence. The COCOn bit is cleared when the respective ADCSCn is
written or when the respective ADCRLn is read.
0 Conversion not completed
1 Conversion completed
6
AIENn
Interrupt Enable - AIENn enables conversion complete interrupts. When COCOn becomes set while the
respective AIENn is high, an interrupt is asserted.
0 Conversion complete interrupt disabled
1 Conversion complete interrupt enabled
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
12-11
Analog-to-Digital Converter (S08ADC16V1)
Table 12-5. ADCSC1:ADCSC1n Field Descriptions (Continued)
Field
Description
5
DIFFn
Differential Mode Enable - DIFFn configures the ADC to operate in differential mode. When enabled this mode
automatically selects from the differential channels, changes the conversion algorithm and the number of cycles
to complete a conversion.
0 Single-ended conversions and input channels are selected
1 Differential conversions and input channels are selected
4:0
Input Channel Select - The ADCHn bits form a 5-bit field that selects one of the input channels. The input
ADCHn[4:0] channel decode is dependent upon the value of the DIFFn bit as detailed in Table 12-6.
The successive approximation converter subsystem is turned off when the channel select bits are all set(ADCHn
= 11111). This feature allows for explicit disabling of the ADC and isolation of the input channel from all sources.
Terminating continuous conversions this way prevents an additional, single conversion from being performed. It
is not necessary to set the channel select bits to all ones to place the ADC in a low-power state when continuous
conversions are not enabled because the module automatically enters a low-power state when a conversion
completes.
Table 12-6. Input Channel Select
ADCHn
Input Selected when DIFFn=0
Input Selected when DIFFn=1
00000–00011
DADP0-DADP3
DAD0-DAD31
00100-10111
AD4-AD23
Reserved
11000-11001
Reserved
Reserved
11010
Temp Sensor (single-ended)
Temp Sensor (differential)
11011
Bandgap (single-ended)
Bandgap (differential)
11100
Reserved
Reserved
11101
VREFSH
2
11110
VREFSL2
-VREFSH2 (differential)
Reserved
11111
1
2
12.3.2
Module disabled
DAD0-DAD3 are associated with the input pin pairs DADPx and DADMx.
Voltage Reference selected is determined by the REFSEL bits in the ADCSC2 register.
Refer to Section 12.4.3 for more information on voltage reference selection.
Configuration Register 1 (ADCCFG1)
ADCCFG1 selects the mode of operation, clock source, clock divide, and configure for low power or long
sample time.
7
6
5
4
3
2
1
0
R
ADLPC
ADIV
ADLSMP
MODE
ADICLK
W
Reset:
0
0
0
0
0
0
0
0
Figure 12-4. Configuration Register (ADCCFG1)
MCF51MM256 Series Devices Reference Manual, Rev. 3
12-12
Freescale Semiconductor
Analog-to-Digital Converter (S08ADC16V1)
Table 12-7. ADCCFG1 Register Field Descriptions
Field
7
ADLPC
Description
Low-Power Configuration - ADLPC controls the power configuration of the successive approximation
converter. This optimizes power consumption when higher sample rates are not required.
0 Normal power configuration
1 Low-power configuration: The power is reduced at the expense of maximum clock speed.
6:5
ADIV[6:5]
Clock Divide Select - ADIV selects the divide ratio used by the ADC to generate the internal clock ADCK.
Table 12-8 shows the available clock configurations.
4
ADLSMP
Sample Time Configuration - ADLSMP selects between different sample times based on the conversion mode
selected. This bit adjusts the sample period to allow higher impedance inputs to be accurately sampled or to
maximize conversion speed for lower impedance inputs. Longer sample times can also be used to lower overall
power consumption when continuous conversions are enabled if high conversion rates are not required. When
ADLSMP=1, the Long Sample Time Select bits (ADLSTS[1:0]) can select the extent of the long sample time.
0 Short sample time
1 Long sample time (The ADLTS bits can select the extent of the long sample time)
3:2
MODE[3:2]
Conversion Mode Selection - MODE bits are used to select between the ADC resolution mode. See Table 12-9.
1:0
Input Clock Select - ADICLK bits select the input clock source to generate the internal clock ADCK. See
ADICLK[1:0] Table 12-10.
Table 12-8. Clock Divide Select
ADIV
Divide Ratio
Clock Rate
00
1
Input clock
01
2
Input clock 2
10
4
Input clock 4
11
8
Input clock 8
Table 12-9. Conversion Modes
Conversion Mode Description
MODE
DIFFn
00
0
single-ended 8-bit conversion
00
1
Differential 9-bit conversion with 2s complement output
01
0
single-ended 12-bit conversion
01
1
Differential 13-bit conversion with 2s complement output
10
0
single-ended 10-bit conversion
10
1
Differential 11-bit conversion with 2s complement output
11
0
single-ended 16-bit conversion
11
1
Differential 16-bit conversion with 2s complement output
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
12-13
Analog-to-Digital Converter (S08ADC16V1)
Table 12-10. Input Clock Select
12.3.3
ADICLK
Selected Clock Source
00
Bus clock
01
Bus clock divided by 2
10
Alternate clock (ALTCLK)
11
Asynchronous clock (ADACK)
Configuration Register 2 (ADCCFG2)
ADCCFG2 selects differential mode, the special high speed configuration for very high speed
conversions, and selects the long sample time duration during long sample mode.
R
7
6
5
4
0
0
0
0
3
2
ADACKEN
ADHSC
0
0
1
0
ADLSTS
W
Reset:
0
0
0
0
0
0
Figure 12-5. Configuration Register 2(ADCCFG2)
Table 12-11. ADCCFG2 Register Field Descriptions
Field
Description
3
ADACKEN
Asynchronous clock output enable - ADACKEN enables the ADC’s asynchronous clock source and the clock
source output regardless of the conversion and input clock select (ADICLK bits) status of the ADC. Based on
MCU configuration the asynchronous clock may be used by other modules (see module introduction section).
Setting this bit allows the clock to be used even while the ADC is idle or operating from a different clock source.
Also, latency of initiating a single or first-continuous conversion with the asynchronous clock selected is reduced
since the ADACK clock is already operational.
0 Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a
conversion is active
1 Asynchronous clock and clock output enabled regardless of the state of the ADC
2
ADHSC
High Speed Configuration- ADHSC configures the ADC for very high speed operation. The conversion
sequence is altered (4 ADCK cycles added to the conversion time) to allow higher speed conversion clocks.
0 Normal conversion sequence selected
1 High speed conversion sequence selected (4 additional ADCK cycles to total conversion time)
1:0
ADLSTS
Long Sample Time Select - ADLSTS selects between the extended sample times when long sample time is
selected (ADLSMP=1). This allows higher impedance inputs to be accurately sampled or to maximize conversion
speed for lower impedance inputs. Longer sample times can also be used to lower overall power consumption
when continuous conversions are enabled if high conversion rates are not required.
00 Default longest sample time (20 extra ADCK cycles; 24 ADCK cycles total)
01 12 extra ADCK cycles; 16 ADCK cycles total sample time
10 6 extra ADCK cycles; 10 ADCK cycles total sample time
11 2 extra ADCK cycles; 6 ADCK cycles total sample time
MCF51MM256 Series Devices Reference Manual, Rev. 3
12-14
Freescale Semiconductor
Analog-to-Digital Converter (S08ADC16V1)
12.3.4
Data Result Registers (ADCRHA:ADCRLA to ADCRHn:ADCRLn)
The Data Result Registers (ADCRHA:ADCRLA to ADCRHn:ADCRLn) contain the result of an ADC
conversion of the channel selected by the respective status and channel control register
(ADCSC1A:ADCSC1n). For every ADCSC1A:ADCSC1n status and channel control register, there is a
respective ADCRHA:ADCRLA to ADCRHn:ADCRLn data result register. Consult the module
introduction for information on the number of ADCRHn:ADCRLn registers specific to this MCU.Reading
ADCRHn prevents the ADC from transferring subsequent conversion results into the result registers until
ADCRLn is read. If ADCRLn is not read until after the next conversion is completed, the intermediate
conversion result is lost. In 8-bit single-ended mode, there is no interlocking with ADCRLn.
7
6
5
4
3
2
1
0
0
0
0
0
D[15:8]
R
W
Reset:
0
0
0
0
Figure 12-6. Data Result High Register (ADCRHn)
7
6
5
4
3
2
1
0
0
0
0
0
D[7:0]
R
W
Reset:
0
0
0
0
Figure 12-7. Data Result Low Register (ADCRLn)
ADCRHn contains the upper bits of the result of a conversion based on the conversion mode. ADCRLn
contains the lower eight bits of the result of a conversion, or all eight bits of an 8-bit single-ended
conversion. Unused bits in the ADCRHn register are cleared in unsigned right justified modes and carry
the sign bit (MSB) in sign extended 2’s complement modes. For example when configured for 10-bit
single-ended mode, D[15:10] are cleared. When configured for 11-bit differential mode, D[15:10] carry
the sign bit (bit 10 extended through bit 15).
Table 12-12 describes the behavior of the data result registers in the different modes of operation.
Table 12-12. Data Result Register Description
Data Result Register bits
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Format
D15
Conversion
Mode
16b differential
S
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
signed 2’s complement
16b single-ended
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
unsigned right justified
13b differential
S
S
S
S
D
D
D
D
D
D
D
D
D
D
D
D
sign extended 2’s
complement
12b single-ended
0
0
0
0
D
D
D
D
D
D
D
D
D
D
D
D
unsigned right justified
11b differential
S
S
S
S
S
S
D
D
D
D
D
D
D
D
D
D
sign extended 2’s
complement
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
12-15
Analog-to-Digital Converter (S08ADC16V1)
Table 12-12. Data Result Register Description
Data Result Register bits
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Format
D15
Conversion
Mode
10b single-ended
0
0
0
0
0
0
D
D
D
D
D
D
D
D
D
D
unsigned right justified
9b differential
S
S
S
S
S
S
S
S
D
D
D
D
D
D
D
D
sign extended 2’s
complement
8b single-ended
0
0
0
0
0
0
0
0
D
D
D
D
D
D
D
D
unsigned right justified
S: Sign bit or sign bit extension.
D: Data (2’s complement data if indicated).
12.3.5
Compare Value Registers (ADCCV1H:ADCCV1L and ADCCV2H:ADCCV2L)
The Compare Value Registers (ADCCV1H:ADCCV1L & ADCCV2H:ADCCV2L) contain a compare
value used to compare with the conversion result when the compare function is enabled (ACFE=1). This
register is formatted the same for both bit position definition and value format (unsigned or sign-extended
2’s complement) as the Data Result Registers (ADCRHn:ADCRLn) in the different modes of operation
(See Table 12-12). Therefore, the compare function only uses the compare value register bits that are
related to the ADC mode of operation.
The compare value 2 registers (ADCCV2H:ADCCV2L) are utilized only when the compare range
function is enabled (ACREN=1).
In all modes except 8-bit single-ended conversions, the ADCCV1H register holds the upper bits of the first
compare value. In 8-bit single-ended mode, ADCCV1H is not used during compare. In all conversion
modes, the ADCCV1L register holds the lower 8 bits of the first compare value. The compare function is
further detailed in Section 12.4.6.
7
6
5
4
3
2
1
0
0
0
0
0
R
CV1[15:8]
W
Reset:
0
0
0
0
Figure 12-8. Compare Value 1 High Register (ADCCV1H)
7
6
5
4
3
2
1
0
0
0
0
0
R
CV1[7:0]
W
Reset:
0
0
0
0
Figure 12-9. Compare Value 1 Low Register(ADCCV1L)
MCF51MM256 Series Devices Reference Manual, Rev. 3
12-16
Freescale Semiconductor
Analog-to-Digital Converter (S08ADC16V1)
7
6
5
4
3
2
1
0
0
0
0
0
R
CV2[15:8]
W
Reset:
0
0
0
0
Figure 12-10. Compare Value 2 High Register (ADCCV2H)
7
6
5
4
3
2
1
0
0
0
0
0
R
CV2[7:0]
W
Reset:
0
0
0
0
Figure 12-11. Compare Value 2Low Register(ADCCV2L)
12.3.6
Status and Control Register 2 (ADCSC2)
The ADCSC2 register contains the conversion active, hardware/software trigger select, compare function
and voltage reference select of the ADC module.
7
R
6
5
4
3
ADTRG
ACFE
ACFGT
ACREN
0
0
0
0
ADACT
2
1
0
0
REFSEL
W
Reset:
0
0
0
0
Figure 12-12. Status and Control Register 2 (ADCSC2)
Table 12-13. ADCSC2 Register Field Descriptions
Field
Description
7
ADACT
Conversion Active - ADACT indicates that a conversion or hardware averaging is in progress. ADACT is set
when a conversion is initiated and cleared when a conversion is completed or aborted.
0 Conversion not in progress
1 Conversion in progress
6
ADTRG
Conversion Trigger Select - ADTRG selects the type of trigger used for initiating a conversion. Two types of
trigger are selectable: software trigger and hardware trigger. When software trigger is selected, a conversion is
initiated following a write to ADCSC1A. When hardware trigger is selected, a conversion is initiated following the
assertion of the ADHWT input after a pulse of the ADHWTSn input.Refer to Section 12.4.5.1 for more information
on initiating conversions.
0 Software trigger selected
1 Hardware trigger selected
5
ACFE
Compare Function Enable - ACFE enables the compare function.
0 Compare function disabled
1 Compare function enabled
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
12-17
Analog-to-Digital Converter (S08ADC16V1)
Table 12-13. ADCSC2 Register Field Descriptions (Continued)
Field
Description
4
ACFGT
Compare Function Greater Than Enable - ACFGT configures the compare function to check the conversion
result relative to the compare value register(s) (ADCCV1H:ADCCV1L and ADCCV2H:ADCCV2L) based upon
the value of ACREN. The ACFE bit must be set for ACFGT to have any effect. The compare function modes are
further detailed in Table 12-24 in Section 12.4.6.
0 Configures Less Than Threshold, Outside Range Not Inclusive and Inside Range Not Inclusive functionality
based on the values placed in the ADCCV1 and ADCCV2 registers.
1 Configures GreaterThan Or EqualTo Threshold, Outside Range Inclusive and Inside Range Inclusive
functionality based on the values placed in the ADCCV1 and ADCCV2 registers.
3
ACREN
Compare Function Range Enable - ACREN configures the compare function to check the conversion result of
the input being monitored is either between or outside the range formed by the compare value registers
(ADCCV1H:ADCCV1L and ADCCV2H:ADCCV2L) determined by the value of ACFGT.The ACFE bit must be set
for ACFGT to have any effect. The compare function modes are further detailed in Table 12-24 in Section 12.4.6.
0 Range function disabled. Only the compare value 1 register (ADCCV1H:ADCCV1L) is compared.
1 Range function enabled. Both compare value registers (ADCCV1H:ADCCV1L and ADCCV2H:ADCCV2L) are
compared.
1:0
REFSEL
[1:0]
Voltage Reference Selection - REFSEL bits select the voltage reference source used for conversions.Refer to
Section 12.4.3 for more information on voltage reference selection.
00 Default voltage reference pin pair (External pins VREFH and VREFL).
01 Alternate reference pair (VALTH and VALTL). This pair may be additional external pins or internal sources
depending on MCU configuration.Consult the module introduction for information on the Voltage Reference
specific to this MCU.
10 Internal bandgap reference and associated ground reference (VBGH and VBGL).
11 Reserved - Selects default voltage reference (VREFH and VREFL) pin pair.
12.3.7
Status and Control Register 3 (ADCSC3)
The ADCSC3 register controls the calibration, continuous convert and hardware averaging functions of
the ADC module.
7
R
6
5
4
CALF
0
0
CAL
3
2
ADCO
AVGE
0
0
1
0
AVGS
W
Reset:
0
0
0
0
0
0
Figure 12-13. Status and Control Register 3 (ADCSC3)
MCF51MM256 Series Devices Reference Manual, Rev. 3
12-18
Freescale Semiconductor
Analog-to-Digital Converter (S08ADC16V1)
Table 12-14. ADCSC3 Register Field Descriptions
Field
Description
7
CAL
Calibration - CAL begins the calibration sequence when set. This bit stays set while the calibration is in progress
and is cleared when the calibration sequence is complete. The CALF bit must be checked to determine the result
of the calibration sequence. Once started, the calibration routine cannot be interrupted by writes to the ADC
registers or the results will be invalid and the CALF bit will set. Setting the CAL bit will abort any current
conversion.
6
CALF
Calibration Failed Flag - CALF displays the result of the calibration sequence. The calibration sequence will fail
if ADTRG = 1, any ADC register is written, or any stop mode is entered before the calibration sequence
completes.The CALF bit is cleared by writing a 1 to this bit.
0 Calibration completed normally.
1 Calibration failed. ADC accuracy specifications are not guaranteed.
3
ADCO
Continuous Conversion Enable - ADCO enables continuous conversions.Refer to Section 12.4.5.1 for more
information on initiating conversions.
0 One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating
a conversion.
1 Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after
initiating a conversion.
2
AVGE
Hardware average enable - AVGE enables the hardware average function of the ADC.
0 Hardware average function disabled
1 Hardware average function enabled
1:0
AVGS
Hardware Average select - AVGS determine how many ADC conversions will be averaged to create the ADC
average result.
00 - 4 Samples averaged
01 - 8 Samples averaged
10 - 16 Samples averaged
11 - 32 Samples averaged
12.3.8
ADC Offset Correction Register (ADCOFSH:ADCOFSL)
The ADC Offset Correction Register (ADCOFSH:ADCOFSL) contains the user-selected or
calibration-generated offset error correction value.
This register is a 2’s complement, left justified, 16b value formed by the concatenation of:
• ADCOFSH
• ADCOFSL.
The value in the offset correction registers (ADCOFSH:ADCOFSL) is subtracted from the conversion and
the result is transferred into the result registers (ADCRHn:ADCRLn).
NOTE
If the result is above the maximum or below the minimum result value, it is forced to the appropriate limit
for the current mode of operation.For additional information, please see Section 12.4.8.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
12-19
Analog-to-Digital Converter (S08ADC16V1)
7
6
5
4
3
2
1
0
0
0
0
0
R
OFS[15:8]
W
Reset:
0
0
0
0
Figure 12-14. Offset Calibration High Register (ADCOFSH)
7
6
5
4
3
2
1
0
0
0
0
0
R
OFS[7:0]
W
Reset:
0
0
0
0
Figure 12-15. Offset Calibration Low Register (ADCOFSL)
12.3.9
ADC Plus-Side Gain Register (ADCPGH:ADCPGL)
The Plus-Side Gain Register (ADCPGH:ADCPGL) contains the gain error correction for the plus-side
input in differential mode or the overall conversion in single-ended mode. ADCPGH:ADCPGL represent
a 16 bit floating point number representation of the gain adjustment factor, with the decimal point fixed
between ADPG15 and ADPG14. This register must be written by the user with the value described in the
calibration procedure or the gain error specifications may not be met.
7
6
5
4
3
2
1
0
0
0
1
1
R
PG[15:8]
W
Reset:
1
0
0
0
Figure 12-16. ADC Plus Gain High Register (ADCPGH)
7
6
5
4
3
2
1
0
0
0
0
0
R
PG[7:0]
W
Reset:
0
0
0
1
Figure 12-17. ADC Plus Gain Low Register (ADCPGL)
12.3.10 ADC Minus-Side Gain Register (ADCMGH:ADCMGL)
The Minus-Side Gain Register (ADCMGH:ADCMGL) contains the gain error correction for the
minus-side input in differential mode. This register is ignored in single-ended mode.
ADCMGH:ADCMGL represent a 16 bit floating point number representation of the gain adjustment
MCF51MM256 Series Devices Reference Manual, Rev. 3
12-20
Freescale Semiconductor
Analog-to-Digital Converter (S08ADC16V1)
factor, with the decimal point fixed between ADPG15 and ADPG14. This register must be written by the
user with the value described in the calibration procedure or the gain error specifications may not be met.
7
6
5
4
3
2
1
0
0
0
1
1
R
MG[15:8]
W
Reset:
1
0
0
0
Figure 12-18. ADC Gain Register (ADCMGH)
7
6
5
4
3
2
1
0
0
0
0
0
R
MG[7:0]
W
Reset:
0
0
0
1
Figure 12-19. ADC Gain Register (ADCMGL)
12.3.11 ADC Plus-Side General Calibration Value Registers (ADCCLPx)
The Plus-Side General Calibration Value Registers (ADCCLPx) contain calibration information that is
generated by the calibration function. These registers contain seven calibration values of varying widths:
CLP0[5:0], CLP1[6:0], CLP2[7:0], CLP3[8:0], CLP4[9:0], CLPS[5:0], and CLPD[5:0]. ADCCLPx are
automatically set once the self calibration sequence is done (CAL is cleared). If these registers are written
by the user after calibration, the linearity error specifications may not be met.
R
7
6
0
0
5
4
3
2
1
0
1
0
1
2
1
0
0
0
0
1
0
CLPD[5:0]
W
Reset:
0
0
0
1
1
Figure 12-20. Plus-Side General Calibration Register (ADCCLPD)
R
7
6
0
0
5
4
3
CLPS[5:0]
W
Reset:
0
0
1
0
0
Figure 12-21. Plus-Side General Calibration Register (ADCCLPS)
R
7
6
5
4
3
2
0
0
0
0
0
0
CLP4[9:8]
W
Reset:
0
0
0
0
0
0
1
0
Figure 12-22. Plus-Side General Calibration Register (ADCCLP4H)
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
12-21
Analog-to-Digital Converter (S08ADC16V1)
7
6
5
4
3
2
1
0
0
0
0
0
R
CLP4[7:0]
W
Reset:
0
0
0
0
Figure 12-23. Plus-Side General Calibration Register (ADCCLP4L)
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
CLP3[8]
W
Reset:
0
0
0
0
0
0
0
1
Figure 12-24. Plus-Side General Calibration Register (ADCCLP3H)
7
6
5
4
3
2
1
0
0
0
0
0
R
CLP3[7:0]
W
Reset:
0
0
0
0
Figure 12-25. Plus-Side General Calibration Register (ADCCLP3L)
7
6
5
4
3
2
1
0
0
0
0
0
2
1
0
0
0
0
2
1
0
0
0
0
R
CLP2[7:0]
W
Reset:
1
0
0
0
Figure 12-26. Plus-Side General Calibration Register (ADCCLP2)
7
R
6
5
4
3
0
CLP1[6:0]
W
Reset:
0
1
0
0
0
Figure 12-27. Plus-Side General Calibration Register (ADCCLP1)
R
7
6
0
0
5
4
3
CLP0[5:0]
W
Reset:
0
0
1
0
0
Figure 12-28. Plus-Side General Calibration Register (ADCCLP0)
MCF51MM256 Series Devices Reference Manual, Rev. 3
12-22
Freescale Semiconductor
Analog-to-Digital Converter (S08ADC16V1)
12.3.12 ADC Minus-Side General Calibration Value Registers (ADCCLMx)
ADCCLMx contain calibration information that is generated by the calibration function. These registers
contain seven calibration values of varying widths: CLM0[5:0], CLM1[6:0], CLM2[7:0], CLM3[8:0],
CLM4[9:0], CLMS[5:0], and CLMD[5:0]. ADCCLMx are automatically set once the self calibration
sequence is done (CAL is cleared). If these registers are written by the user after calibration, the linearity
error specifications may not be met.
R
7
6
0
0
5
4
3
2
1
0
1
0
1
CLMD[5:0]
W
Reset:
0
0
0
1
1
Figure 12-29. Minus-Side General Calibration Register (ADCCLMD)
R
7
6
0
0
5
4
3
2
1
0
0
0
1
CLMS[5:0]
W
Reset:
0
0
1
1
0
Figure 12-30. Minus-Side General Calibration Register (ADCCLMS)
R
7
6
5
4
3
2
0
0
0
0
0
0
1
0
CLM4[9:8]
W
Reset:
0
0
0
0
0
0
1
1
Figure 12-31. Minus-Side General Calibration Register (ADCCLM4H)
7
6
5
4
3
2
1
0
0
0
0
0
R
CLM4[7:0]
W
Reset:
0
0
0
1
Figure 12-32. Minus-Side General Calibration Register (ADCCLM4L)
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
CLM3[8]
W
Reset:
0
0
0
0
0
0
0
1
Figure 12-33. Minus-Side General Calibration Register (ADCCLM3H)
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
12-23
Analog-to-Digital Converter (S08ADC16V1)
7
6
5
4
3
2
1
0
1
0
0
0
R
CLM3[7:0]
W
Reset:
1
0
0
0
Figure 12-34. Minus-Side General Calibration Register (ADCCLM3L)
7
6
5
4
3
2
1
0
0
1
0
0
R
CLM2[7:0]
W
Reset:
1
1
0
0
Figure 12-35. Minus-Side General Calibration Register (ADCCLM2)
7
R
6
5
4
3
2
1
0
0
1
0
0
CLM1[6:0]
W
Reset:
0
1
1
0
0
Figure 12-36. Minus-Side General Calibration Register (ADCCLM1)
R
7
6
0
0
5
4
3
2
1
0
0
0
1
CLM0[5:0]
W
Reset:
0
0
1
1
0
Figure 12-37. Minus-Side General Calibration Register (ADCCLM0)
12.3.13 Pin Control 1 Register (APCTL1)
The pin control registers disable the I/O port control of MCU pins used as analog inputs. APCTL1 is used
to control the pins associated with channels 0–7 of the ADC module.
7
6
5
4
3
2
1
0
0
0
0
0
R
ADPC[7:0]
W
Reset:
0
0
0
0
Figure 12-38. Pin Control 1 Register (APCTL1)
MCF51MM256 Series Devices Reference Manual, Rev. 3
12-24
Freescale Semiconductor
Analog-to-Digital Converter (S08ADC16V1)
Table 12-15. APCTL1 Register Field Descriptions
Field
Description
7
ADPC7
ADC Pin Control 7 - ADPC7 controls the pin associated with channel AD7.
0 AD7 pin I/O control enabled
1 AD7 pin I/O control disabled
6
ADPC6
ADC Pin Control 6 - ADPC6 controls the pin associated with channel AD6.
0 AD6 pin I/O control enabled
1 AD6 pin I/O control disabled
5
ADPC5
ADC Pin Control 5- ADPC5 controls the pin associated with channel AD5.
0 AD5 pin I/O control enabled
1 AD5 pin I/O control disabled
4
ADPC4
ADC Pin Control 4 - ADPC4 controls the pin associated with channel AD4.
0 AD4 pin I/O control enabled
1 AD4 pin I/O control disabled
3
ADPC3
ADC Pin Control 3 - ADPC3 controls the pin associated with channel AD3.
0 AD3 pin I/O control enabled
1 AD3 pin I/O control disabled
2
ADPC2
ADC Pin Control 2 - ADPC2 controls the pin associated with channel AD2.
0 AD2 pin I/O control enabled
1 AD2 pin I/O control disabled
1
ADPC1
ADC Pin Control 1 - ADPC1 controls the pin associated with channel AD1.
0 AD1 pin I/O control enabled
1 AD1 pin I/O control disabled
0
ADPC0
ADC Pin Control 0 - ADPC0 controls the pin associated with channel AD0.
0 AD0 pin I/O control enabled
1 AD0 pin I/O control disabled
12.3.14 Pin Control 2 Register (APCTL2)
APCTL2 controls channels 8–15 of the ADC module.
7
6
5
4
3
2
1
0
0
0
0
0
R
ADPC[15:8]
W
Reset:
0
0
0
0
Figure 12-39. Pin Control 2 Register (APCTL2)
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
12-25
Analog-to-Digital Converter (S08ADC16V1)
Table 12-16. APCTL2 Register Field Descriptions
Field
Description
7
ADPC15
ADC Pin Control 15 - ADPC15 controls the pin associated with channel AD15.
0 AD15 pin I/O control enabled
1 AD15 pin I/O control disabled
6
ADPC14
ADC Pin Control 14 - ADPC14 controls the pin associated with channel AD14.
0 AD14 pin I/O control enabled
1 AD14 pin I/O control disabled
5
ADPC13
ADC Pin Control 13 - ADPC13 controls the pin associated with channel AD13.
0 AD13 pin I/O control enabled
1 AD13 pin I/O control disabled
4
ADPC12
ADC Pin Control 12 - ADPC12 controls the pin associated with channel AD12.
0 AD12 pin I/O control enabled
1 AD12 pin I/O control disabled
3
ADPC11
ADC Pin Control 11 - ADPC11 controls the pin associated with channel AD11.
0 AD11 pin I/O control enabled
1 AD11 pin I/O control disabled
2
ADPC10
ADC Pin Control 10 - ADPC10 controls the pin associated with channel AD10.
0 AD10 pin I/O control enabled
1 AD10 pin I/O control disabled
1
ADPC9
ADC Pin Control 9 - ADPC9 controls the pin associated with channel AD9.
0 AD9 pin I/O control enabled
1 AD9 pin I/O control disabled
0
ADPC8
ADC Pin Control 8 - ADPC8 controls the pin associated with channel AD8.
0 AD8 pin I/O control enabled
1 AD8 pin I/O control disabled
12.4
Functional Description
The ADC module is disabled during reset, stop2 or when the ADCHn bits are all high. The module is idle
when a conversion has completed and another conversion has not been initiated. When idle and the
asynchronous clock output enable is disabled (ADACKEN=0), the module is in its lowest power state. The
ADC can perform an analog-to-digital conversion on any of the software selectable channels. All modes
perform conversion by a successive approximation algorithm.
To meet accuracy specifications, the ADC module must be calibrated using the on chip calibration
function. Calibration is recommended to be done after any reset. See Section 12.4.7 for details on how to
perform calibration.
When the conversion is completed, the result is placed in the data registers (ADCRHn and ADCRLn). The
conversion complete flag (COCOn) is then set and an interrupt is generated if the respective conversion
complete interrupt has been enabled (AIENn=1).
The ADC module has the capability of automatically comparing the result of a conversion with the
contents of the compare value registers. The compare function is enabled by setting the ACFE bit and
operates with any of the conversion modes and configurations.
MCF51MM256 Series Devices Reference Manual, Rev. 3
12-26
Freescale Semiconductor
Analog-to-Digital Converter (S08ADC16V1)
The ADC module has the capability of automatically averaging the result of multiple conversions. The
hardware average function is enabled by setting the AVGE bit and operates with any of the conversion
modes and configurations.
12.4.1
Clock Select and Divide Control
One of four clock sources can be selected as the clock source for the ADC module. This clock source is
then divided by a configurable value to generate the input clock to the converter (ADCK). The clock is
selected from one of the following sources by means of the ADICLK bits.
• The bus clock. This is the default selection following reset.
• The bus clock divided by two. For higher bus clock rates, this allows a maximum divide by 16 of
the bus clock with using the ADIV bits.
• ALTCLK, as defined for this MCU (See module section introduction).
• The asynchronous clock (ADACK). This clock is generated from a clock source within the ADC
module. Conversions are possible using ADACK as the input clock source while the MCU is in
stop3 mode. Refer to Section 12.4.5.4 for more information.
Whichever clock is selected, its frequency must fall within the specified frequency range for ADCK. If the
available clocks are too slow, the ADC may not perform according to specifications. If the available clocks
are too fast, the clock must be divided to the appropriate frequency. This divider is specified by the ADIV
bits and can be divide-by 1, 2, 4, or 8.
12.4.2
Input Select and Pin Control
The pin control registers (APCTL1, APCTL2) disable the I/O port control of the pins used as analog
inputs.When a pin control register bit is set, the following conditions are forced for the associated MCU
pin:
• The output buffer is forced to its high impedance state.
• The input buffer is disabled. A read of the I/O port returns a zero for any pin with its input buffer
disabled.
• The pullup is disabled.
12.4.3
Voltage Reference Selection
The ADC can be configured to accept one of three voltage reference pairs as the reference voltage (VREFSH
and VREFSL) used for conversions. Each pair contains a positive reference which must be between the
minimum Ref Voltage High (defined in Appendix A) and VDDAD, and a ground reference which must be
at the same potential as VSSAD. The three pairs are external (VREFH and VREFL), alternate (VALTH and
VALTL) and the internal bandgap (VBGH and VBGL). These voltage references are selected using the
REFSEL bits in the ADCSC2 register.The alternate (VALTH and VALTL) voltage reference pair may select
additional external pins or internal sources depending on MCU configuration.Consult the module
introduction for information on the Voltage References specific to this MCU.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
12-27
Analog-to-Digital Converter (S08ADC16V1)
12.4.4
Hardware Trigger and Channel Selects
The ADC module has a selectable asynchronous hardware conversion trigger, ADHWT, that is enabled
when the ADTRG bit is set and a hardware trigger select event (ADHWTSn) has occurred. This source is
not available on all MCUs. Consult the module introduction for information on the ADHWT source and
the ADHWTSn configurations specific to this MCU.
When the ADHWT source is available and hardware trigger is enabled (ADTRG=1), a conversion is
initiated on the rising edge of the ADHWT after a hardware trigger select event (ADHWTSn) has
occurred. If a conversion is in progress when a rising edge of a trigger occurs, the rising edge is ignored.
In continuous convert configuration, only the initial rising edge to launch continuous conversions is
observed and until conversion gets aborted the ADC will continue to do conversions on the same ADC
Status and Control register that initiated the conversion. The hardware trigger function operates in
conjunction with any of the conversion modes and configurations.
The hardware trigger select event (ADHWTSn) must be set prior to and during the receipt of the ADHWT
signal. If these conditions are not met the converter may ignore the trigger or use the incorrect
configuration. If a hardware trigger select event gets asserted during a conversion, it must stay asserted
until end of current conversion and remain set until the receipt of the ADHWT signal to trigger a new
conversion. The channel and status fields selected for the conversion will depend on the active trigger
select signal (ADHWTSA active selects ADCSC1A; ADHWTSn active selects ADCSC1n).
NOTE
Asserting more than one hardware trigger select signal (ADHWTSn) at the
same time will result in unknown results. To avoid this, only select one
hardware trigger select signal (ADHWTSn) prior to the next intended
conversion.
When the conversion is completed, the result is placed in the data registers associated with the ADHWTSn
received (ADHWTSA active selects ADCRHA:ADCRLA; ADHWTSn active selects
ADCRHn:ADCRLn). The conversion complete flag associated with the ADHWTSn received (COCOn)
is then set and an interrupt is generated if the respective conversion complete interrupt has been enabled
(AIENn=1).
12.4.5
Conversion Control
Conversions can be performed as determined by the MODE bits and the DIFFn bit as shown in Table 12-9.
Conversions can be initiated by a software or hardware trigger. In addition, the ADC module can be
configured for low power operation, long sample time, continuous conversion, hardware average and
automatic compare of the conversion result to a software determined compare value.
12.4.5.1
Initiating Conversions
A conversion is initiated:
• Following a write to ADCSC1A (with ADCHA bits not all 1’s) if software triggered operation is
selected (ADTRG=0).
MCF51MM256 Series Devices Reference Manual, Rev. 3
12-28
Freescale Semiconductor
Analog-to-Digital Converter (S08ADC16V1)
•
Following a hardware trigger (ADHWT) event if hardware triggered operation is selected
(ADTRG=1) and a hardware trigger select event (ADHWTSn) has occurred. The channel and
status fields selected will depend on the active trigger select signal (ADHWTSA active selects
ADCSC1A; ADHWTSn active selects ADCSC1n; if neither is active the off condition is selected).
NOTE
Selecting more than one hardware trigger select signal (ADHWTSn) prior
to a conversion completion will result in unknown results. To avoid this,
only select one hardware trigger select signal (ADHWTSn) prior to a
conversion completion.
•
Following the transfer of the result to the data registers when continuous conversion is enabled
(ADCO=1).
If continuous conversions are enabled, a new conversion is automatically initiated after the completion of
the current conversion. In software triggered operation (ADTRG=0), continuous conversions begin after
ADCSC1A is written and continue until aborted. In hardware triggered operation(ADTRG=1 and one
ADHWTSn event has occurred), continuous conversions begin after a hardware trigger event and continue
until aborted.
If hardware averaging is enabled, a new conversion is automatically initiated after the completion of the
current conversion until the correct number of conversions is completed. In software triggered operation,
conversions begin after ADCSC1A is written. In hardware triggered operation, conversions begin after a
hardware trigger. If continuous conversions are also enabled, a new set of conversions to be averaged are
initiated following the last of the selected number of conversions.
12.4.5.2
Completing Conversions
A conversion is completed when the result of the conversion is transferred into the data result registers,
ADCRHn and ADCRLn. If the compare functions are disabled, this is indicated by the setting of COCOn.
If hardware averaging is enabled, COCOn sets only if the last of the selected number of conversions is
complete. If the compare function is enabled, COCOn sets and conversion result data is transferred only
if the compare condition is true. If both hardware averaging and compare functions are enabled then
COCOn sets only if the last of the selected number of conversions is complete and the compare condition
is true. An interrupt is generated if AIENn is high at the time that COCOn is set.In all modes except 8-bit
single-ended conversions, a blocking mechanism prevents a new result from overwriting previous data in
ADCRHn and ADCRLn if the previous data is in the process of being read (the ADCRHn register has been
read but the ADCRLn register has not). When blocking is active, the conversion result data transfer is
blocked, COCOn is not set, and the new result is lost. In the case of single conversions with the compare
function enabled and the compare condition false, blocking has no effect and ADC operation is terminated.
In all other cases of operation, when a conversion result data transfer is blocked, another conversion is
initiated regardless of the state of ADCO (single or continuous conversions enabled).
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
12-29
Analog-to-Digital Converter (S08ADC16V1)
NOTE
If continuous conversions are enabled, the blocking mechanism could result
in the loss of data occurring at specific timepoints. To avoid this issue, the
data must be read in fewer cycles than an ADC conversion time, accounting
for interrupt or software polling loop latency.
If single conversions are enabled, the blocking mechanism could result in
several discarded conversions and excess power consumption. To avoid this
issue, the data registers must not be read after initiating a single conversion
until the conversion completes.
12.4.5.3
Aborting Conversions
Any conversion in progress is aborted when:
•
Writing ADCSC1A while ADCSC1A is actively controlling a conversion aborts the current
conversion. In software trigger mode (ADTRG=0), a write to ADCSC1A initiates a new conversion
(if the ADCHA bits are equal to a value other than all 1s). Writing any of the ADCSC1(B-n)
registers while that specific ADCSC1(B-n) register is actively controlling a conversion aborts the
current conversion.The ADCSC1(B-n) registers are not used for software trigger operation and
therefore writes to the ADCSC1(B-n) registers do not initiate a new conversion.
•
A write to any ADC register besides the ADCSC1A:ADCSC1n registers occurs. This indicates a
mode of operation change has occurred and the current conversion is therefore invalid.
•
The MCU is reset or enters stop2 mode.
•
The MCU enters stop3 mode with ADACK not enabled.
When a conversion is aborted, the contents of the data registers, ADCRHn and ADCRLn, are not altered.
The data registers continue to be the values transferred after the completion of the last successful
conversion. If the conversion was aborted by a reset or stop2, ADCRHA:ADCRLA and
ADCRHn:ADCRLn return to their reset states.
12.4.5.4
Power Control
The ADC module remains in its idle state until a conversion is initiated. If ADACK is selected as the
conversion clock source but the asynchronous clock output is disabled (ADACKEN=0), the ADACK
clock generator will also remain in its idle state (disabled) until a conversion is initiated. If the
asynchronous clock output is enabled (ADACKEN=1), it will remain active regardless of the state of the
ADC or the MCU power mode.
Power consumption when the ADC is active can be reduced by setting ADLPC. This results in a lower
maximum value for fADCK (see the electrical specifications).
MCF51MM256 Series Devices Reference Manual, Rev. 3
12-30
Freescale Semiconductor
Analog-to-Digital Converter (S08ADC16V1)
12.4.5.5
Sample Time and Total Conversion Time
The total conversion time depends upon: the sample time (as determined by ADLSMP and ADLSTS bits),
the MCU bus frequency, the conversion mode (as determined by MODE and DIFFn bits), the high speed
configuration (ADHSC bit), and the frequency of the conversion clock (fADCK).
The ADHSC bit is used to configure a higher clock input frequency. This will allow faster overall
conversion times. In order to meet internal A/D converter timing requirements the ADHSC bit adds
additional ADCK cycles. Conversions with ADHSC = 1 take four more ADCK cycles. ADHSC should be
used when the ADCLK exceeds the limit for ADHSC = 0.
After the module becomes active, sampling of the input begins. ADLSMP and ADLSTS select between
sample times based on the conversion mode that is selected. When sampling is complete, the converter is
isolated from the input channel and a successive approximation algorithm is performed to determine the
digital value of the analog signal. The result of the conversion is transferred to ADCRHn and ADCRLn
upon completion of the conversion algorithm.
If the bus frequency is less than the fADCK frequency, precise sample time for continuous conversions
cannot be guaranteed when short sample is enabled (ADLSMP=0). The maximum total conversion time
is determined by the clock source chosen and the divide ratio selected. The clock source is selectable by
the ADICLK bits, and the divide ratio is specified by the ADIV bits. The maximum total conversion time
for all configurations is summarized in the equation below. Refer to Table 12-20 through Table 18-27 for
the variables referenced in the equation.
Conversion Time Equation
Eqn. 12-2
ConversionTime = SFCAdder + AverageNum   BCT + LSTAdder + HSCAdder 
1
ADLSMP
ADACKEN
ADICLK
Table 12-17. Single or First Continuous Time Adder (SFCAdder)
1
x
0x, 10
3 ADCK cycles + 5 bus clock cycles
1
1
11
3 ADCK cycles + 5 bus clock cycles1
1
0
11
5s + 3 ADCK cycles + 5 bus clock cycles
0
x
0x, 10
5 ADCK cycles + 5 bus clock cycles
0
1
11
5 ADCK cycles + 5 bus clock cycles1
0
0
11
5s + 5 ADCK cycles + 5 bus clock cycles
Single or First Continuous Time Adder
(SFCAdder)
ADACKEN must be 1 for at least 5us prior to the conversion is initiated
to achieve this time
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
12-31
Analog-to-Digital Converter (S08ADC16V1)
Table 12-18. Average Number Factor (AverageNum)
AVGE
AVGS[1:0]
Average Number
Factor (AverageNum)
0
xx
1
1
00
4
1
01
8
1
10
16
1
11
32
Mode
Table 12-19. Base Conversion Time (BCT)
Base Conversion
Time (BCT)
8b se
17 ADCK cycles
9b diff
27 ADCK cycles
10b s.e.
20 ADCK cycles
11b diff
30 ADCK cycles
12b s.e.
20 ADCK cycles
13b diff
30 ADCK cycles
16b s.e.
25 ADCK cycles
16b diff
34 ADCK cycles
ADLSMP
ADLSTS
Table 12-20. Long Sample Time Adder (LSTAdder)
Long Sample Time
Adder (LSTAdder)
0
xx
0 ADCK cycles
1
00
20 ADCK cycles
1
01
12 ADCK cycles
1
10
6 ADCK cycles
1
11
2 ADCK cycles
MCF51MM256 Series Devices Reference Manual, Rev. 3
12-32
Freescale Semiconductor
Analog-to-Digital Converter (S08ADC16V1)
Table 12-21. High-Speed Conversion Time Adder (HSCAdder)
ADHSC
High Speed
Conversion Time
Adder (HSCAdder)
0
0 ADCK cycles
1
4 ADCK cycles
NOTE
The ADCK frequency must be between fADCK minimum and fADCK
maximum to meet ADC specifications.
12.4.5.6
Conversion Time Examples
The following examples use Equation 12-2 and the information provided in Table 12-20 through
Table 18-27.
12.4.5.6.1
Typical conversion time configuration
A typical configuration for ADC conversion is: 10-bit mode, with the bus clock selected as the input clock
source, the input clock divide-by-1 ratio selected, and a bus frequency of 8 MHz, long sample time
disabled and high speed conversion enabled. The conversion time for a single conversion is calculated by
using Equation 12-2 and the information provided in Table 12-20 through Table 18-27. The table below
lists the variables of Equation 12-2.
Table 12-22. Typical Conversion Time
Variable
Time
SFCAdder
5 ADCK cycles + 5 bus clock cycles
AverageNum
1
BCT
20 ADCK cycles
LSTAdder
0
HSCAdder
4
The resulting conversion time is generated using the parameters listed in Table 12-24. So, for Bus clock
equal to 8 MHz and ADCK equal to 8 MHz, the resulting conversion time is 4.25 us.
12.4.5.6.2
Long conversion time configuration
A configuration for long ADC conversion is: 16-bit differential mode, with the bus clock selected as the
input clock source, the input clock divide-by-8 ratio selected, and a bus frequency of 8 MHz, long sample
time enabled and configured for longest adder and high speed conversion disabled. Average enabled for
32 conversions. The conversion time for this conversion is calculated by using Equation 12-2 and the
information provided in Table 12-20 through Table 18-27. The table below list the variables of
Equation 12-2.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
12-33
Analog-to-Digital Converter (S08ADC16V1)
Table 12-23. Long Conversion Time
Variable
Time
SFCAdder
3 ADCK cycles + 5 bus clock cycles
AverageNum
32
BCT
34 ADCK cycles
LSTAdder
20 ADCK cycles
HSCAdder
0
The resulting conversion time is generated using the parameters listed in Table 12-24. So, for Bus clock
equal to 8 MHz and ADCK equal to 1 MHz the resulting total conversion time is 1.732 ms.
12.4.5.7
Hardware Average Function
The hardware average function can be enabled (AVGE=1) to perform a hardware average of multiple
conversions. The number of conversions is determined by the AVGS[1:0] bits, which select 4, 8, 16 or 32
conversions to be averaged. While the hardware average function is in progress, the ADACT bit is set.
After the selected input is sampled and converted, the result is placed in an accumulator from which an
average is calculated once the selected number of conversions has been completed. When hardware
averaging is selected the completion of a single conversion will not set the COCOn bit.
If the compare function is either disabled or evaluates true, after the selected number of conversions are
completed, the average conversion result is transferred into the data result registers, ADCRHn and
ADCRLn, and the COCOn bit is set. An ADC interrupt is generated upon the setting of COCOn if the
respective ADC interrupt is enabled (AIENn=1).
NOTE
The hardware average function can perform conversions on a channel while
the MCU is in wait or stop3 mode. The ADC interrupt wakes the MCU
when the hardware average is complete if AIENn was set.
12.4.6
Automatic Compare Function
The compare function can be configured to check if the result is less than or greater-than-or-equal-to a
single compare value, or if the result falls within or outside a range determined by two compare values.
The compare mode is determined by ACFGT, ACREN and the values in the compare value
registers(ADCCV1H:ADCCV1L and ADCCV2H:ADCCV2L). After the input is sampled and converted,
MCF51MM256 Series Devices Reference Manual, Rev. 3
12-34
Freescale Semiconductor
Analog-to-Digital Converter (S08ADC16V1)
the compare values (ADCCV1H:ADCCV1L and ADCCV2H:ADCCV2L) are used as described in
Table 12-24.There are six compare modes as shown in Table 12-24.
ACFGT
ACREN
Table 12-24. Compare Modes
ADCCV1
relative to
ADCCV2
0
0
-
Less than threshold
Compare true if the result is less than the ADCCV1
registers.
1
0
-
Greater than or equal to threshold
Compare true if the result is greater than or equal to
ADCCV1 registers.
0
1
Less than
or equal
Outside range, not inclusive
Compare true if the result is less than ADCCV1 Or the
result is Greater than ADCCV2
0
1
Greater
than
Inside range, not inclusive
Compare true if the result is less than ADCCV1 And the
result is greater than ADCCV2
1
1
Less Than
or equal
Inside range, inclusive
Compare true if the result is greater than or equal to
ADCCV1 And the result is less than or equal to
ADCCV2
1
1
Greater
than
Outside range, inclusive
Compare true if the result is greater than or equal to
ADCCV1 Or the result is less than or equal to ADCCV2
Function
Compare Mode Description
With the ADC range enable bit set, ADCREN =1, if compare value register 1(ADCCV1 value) is less than
or equal to the compare value register 2 (ADCCV2 value), setting ACFGT will select a
trigger-if-inside-compare-range, inclusive-of-endpoints function. Clearing ACFGT will select a
trigger-if-outside-compare-range, not-inclusive-of-endpoints function.
If ADCCV1 is greater than the ADCCV2, setting ACFGT will select a trigger-if-outside-compare-range,
inclusive-of-endpoints function. Clearing ACFGT will select a trigger-if-inside-compare-range,
not-inclusive-of-endpoints function.
If the condition selected evaluates true, COCOn is set.
Upon completion of a conversion while the compare function is enabled, if the compare condition is not
true, COCOn is not set and the conversion result data will not be transferred to the result register. If the
hardware averaging function is enabled, the compare function compares the averaged result to the compare
values. The same compare function definitions apply. An ADC interrupt is generated upon the setting of
COCOn if the respective ADC interrupt is enabled (AIENn=1).
NOTE
The compare function can monitor the voltage on a channel while the MCU
is in wait or stop3 mode. The ADC interrupt wakes the MCU when the
compare condition is met.
12.4.7
Calibration Function
The ADC contains a self-calibration function that is required to achieve the specified accuracy. Calibration
must be run or valid calibration values written after any reset and before a conversion is initiated. The
calibration function sets the offset calibration value and the plus-side and minus-side calibration values.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
12-35
Analog-to-Digital Converter (S08ADC16V1)
The offset calibration value is automatically stored in the ADC Offset Correction Registers (ADCOFSH
and ADCOFSL) and the plus-side and minus-side calibration values are automatically stored in the ADC
Plus-Side and Minus-Side Calibration registers (CLPD, CLPS, CLP4, CLP3, CLP2, CLP1, CLP0 and
CLMD, CLMS, CLP4, CLM3, CLM2, CLM1, CLM0). The user must configure the ADC correctly prior
to calibration, and must generate the plus-side and minus-side gain calibration results and store them in the
ADC GAIN registers (ADCPGH and ADCPGL) after the calibration function completes.
Prior to calibration, the user must configure the ADC’s clock source and frequency, low power
configuration, voltage reference selection, sample time and the high speed configuration according to the
application’s clock source availability and needs. If the application uses the ADC in a wide variety of
configurations, the configuration for which the highest accuracy is required should be selected, or multiple
calibrations can be done for the different configurations. The input channel, conversion mode continuous
function, compare function, hardware average function, resolution mode, and differential/single-ended
mode are all ignored during the calibration function.
To initiate calibration, the user sets the CAL bit and the calibration will automatically begin if the ADTRG
bit = 0. If ADTRG = 1, the CAL bit will not get set and the calibration fail flag (CALF) will be set. While
calibration is active, no ADC register can be written and no stop mode may be entered or the calibration
routine will be aborted causing the CAL bit to clear and the CALF bit to set. At the end of a calibration
sequence the COCO bit of the ADSC1A register will be set. The AIEN1 bit can be used to allow an
interrupt to occur at the end of a calibration sequence. If at the end of calibration routine the CALF bit is
not set, the automatic calibration routine completed successfully.
To complete calibration, the user must generate the gain calibration values using the following procedure:
• Initialize (clear) a 16b variable in RAM.
• Add the following plus-side calibration results CLP0, CLP1, CLP2, CLP3, CLP4, and CLPS to the
variable.
• Divide the variable by two.
• Set the MSB of the variable.
• The previous two steps can be achieved by setting the carry bit, rotating-right through the carry bit
on the high byte and again on the low byte.
• Store the value in the plus-side gain calibration registers ADCPGH and ADCPGL.
• Repeat procedure for the minus-side gain calibration value.
When complete the user may reconfigure and use the ADC as desired. A second calibration may also be
performed if desired by clearing and again setting the CAL bit.
Overall the calibration routine may take as many as 14000 ADCK cycles and 100 bus cycles, depending
on the results and the clock source chosen. For an 8 MHz clock source this is about 1.7 msec. To reduce
this latency, the calibration values (offset, plus- and minus-side gain, and plus- and minus-side calibration
values) may be stored in flash after an initial calibration and recovered prior to the first ADC conversion.
This should reduce the calibration latency to 20 register store operations on all subsequent power, reset, or
stop2 mode recoveries.
MCF51MM256 Series Devices Reference Manual, Rev. 3
12-36
Freescale Semiconductor
Analog-to-Digital Converter (S08ADC16V1)
12.4.8
User Defined Offset Function
The ADC Offset Correction Register (ADCOFSH:ADCOFSL) contains the user selected or calibration
generated offset error correction value. This register is a 2’s complement, left justified, 16b value formed
by the concatenation of ADCOFSH and ADCOFSL. The value in the offset correction registers
(ADCOFSH:ADCOFSL) is subtracted from the conversion and the result is transferred into the result
registers (ADCRHn:ADCRLn). If the result is above the maximum or below the minimum result value, it
is forced to the appropriate limit for the current mode of operation.For additional information please see
Section 12.4.8
The formatting of the ADC Offset Correction Register is different from the Data Result Registers
(ADCRHn:ADCRLn) to preserve the resolution of the calibration value regardless of the conversion mode
selected. Lower order bits are ignored in lower resolution modes. For example, in 8b single-ended mode,
the bits OFS[14:7] are subtracted from D[7:0]; bit OFS[15] indicates the sign (negative numbers are
effectively added to the result) and bits OFS[6:0] are ignored. The same bits are used in 9b differential
mode since bit OFS[15] indicates the sign bit, which maps to bit D[8]. For 16b differential mode, all bits
OFS[15:0] are directly subtracted from the conversion result data D[15:0]. Finally, in 16b single-ended
mode, there is no bit in the Offset Correction Register corresponding to the least significant result bit D[0],
so odd values (-1 or +1, etc.) cannot be subtracted from the result.ADCOFSH is automatically set
according to calibration requirements once the self calibration sequence is done (CAL is cleared). Write
ADCOFSH:ADCOFSL to override the calibration result if desired. If the Offset Correction Register is
written to a value that is different from the calibration value, the ADC error specifications may not be met.
It is recommended that the value generated by the calibration function be stored in memory before
overwriting with a specified value.
NOTE
There is an effective limit to the values of Offset that can be set. If the
magnitude of the offset is too great, the results of the conversions cap off at
the limits.
Use the offset calibration function to remove application offsets or DC bias values. The Offset Correction
Registers ADCOFSH and ADCOFSL may be written with a number in 2’s complement format and this
offset will be subtracted from the result (or hardware averaged value). To add an offset, store the negative
offset in 2’s complement format and the effect will be an addition. An offset correction that results in an
out-of-range value will be forced to the minimum or maximum value (the minimum value for single-ended
conversions is 0x0000; for a differential conversion 0x8000).
To preserve accuracy, the calibrated offset value initially stored in the ADCOFS registers must be added
to the user defined offset. For applications which may change the offset repeatedly during operation, it is
recommended to store the initial offset calibration value in flash so that it can be recovered and added to
any user offset adjustment value -nd the sum stored in the ADCOFS registers.
12.4.9
Temperature Sensor
The ADC module includes a temperature sensor whose output is connected to one of the ADC analog
channel inputs. Equation 12-3 provides an approximate transfer function of the temperature sensor.
Temp = 25 - ((VTEMP -VTEMP25)  m)
Eqn. 12-3
where:
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
12-37
Analog-to-Digital Converter (S08ADC16V1)
— VTEMP is the voltage of the temperature sensor channel at the ambient temperature.
— VTEMP25 is the voltage of the temperature sensor channel at 25C.
— m is the hot or cold voltage versus temperature slope in V/C.
For temperature calculations, use the VTEMP25 and m values from the ADC Electricals table.
In application code, the user reads the temperature sensor channel, calculates VTEMP, and compares to
VTEMP25. If VTEMP is greater than VTEMP25 the cold slope value is applied in Equation 12-3. If VTEMP is
less than VTEMP25 the hot slope value is applied in Equation 12-3.
For more information on using the temperature sensor, consult AN3031.
12.4.10 MCU Wait Mode Operation
Wait mode is a lower power-consumption standby mode from which recovery is fast because the clock
sources remain active. If a conversion is in progress when the MCU enters wait mode, it continues until
completion. Conversions can be initiated while the MCU is in wait mode by means of the hardware trigger
or if continuous conversions are enabled.
The bus clock, bus clock divided by two, and ADACK are available as conversion clock sources while in
wait mode. The use of ALTCLK as the conversion clock source in wait is dependent on the definition of
ALTCLK for this MCU. Consult the module introduction for information on ALTCLK specific to this
MCU.
If the compare and hardware averaging functions are disabled, a conversion complete event sets the
COCOn and generates an ADC interrupt to wake the MCU from wait mode if the respective ADC interrupt
is enabled (AIENn=1). If the hardware averaging function is enabled the COCOn will set (and generate an
interrupt if enabled) when the selected number of conversions are complete. If the compare function is
enabled the COCOn will set (and generate an interrupt if enabled) only if the compare conditions are met.
If a single conversion is selected and the compare trigger is not met, the ADC will return to its idle state
and cannot wake the MCU from wait mode unless a new conversion is initiated by the hardware trigger.
12.4.11 MCU Stop3 Mode Operation
Stop mode is a low power-consumption standby mode during which most or all clock sources on the MCU
are disabled.
12.4.11.1 Stop3 Mode With ADACK Disabled
If the asynchronous clock, ADACK, is not selected as the conversion clock, executing a stop instruction
aborts the current conversion and places the ADC in its idle state. The contents of the ADC registers,
including ADCRHn and ADCRLn, are unaffected by stop3 mode. After exiting from stop3 mode, a
software or hardware trigger is required to resume conversions.
MCF51MM256 Series Devices Reference Manual, Rev. 3
12-38
Freescale Semiconductor
Analog-to-Digital Converter (S08ADC16V1)
12.4.11.2 Stop3 Mode With ADACK Enabled
If ADACK is selected as the conversion clock, the ADC continues operation during stop3 mode. For
guaranteed ADC operation, the MCU’s voltage regulator must remain active during stop3 mode. Consult
the module introduction for configuration information for this MCU.
If a conversion is in progress when the MCU enters stop3 mode, it continues until completion. Conversions
can be initiated while the MCU is in stop3 mode by means of the hardware trigger or if continuous
conversions are enabled.
If the compare and hardware averaging functions are disabled, a conversion complete event sets the
COCOn and generates an ADC interrupt to wake the MCU from stop3 mode if the respective ADC
interrupt is enabled (AIENn = 1). The result register will contain the data from the first completed
conversion that occurred during stop3 mode. If the hardware averaging function is enabled the COCOn
will set (and generate an interrupt if enabled) when the selected number of conversions are complete. If
the compare function is enabled the COCOn will set (and generate an interrupt if enabled) only if the
compare conditions are met. If a single conversion is selected and the compare is not true, the ADC will
return to its idle state and cannot wake the MCU from stop3 mode unless a new conversion is initiated by
another hardware trigger.
NOTE
The ADC module can wake the system from low-power stop and cause the
MCU to begin consuming run-level currents without generating a system
level interrupt. To prevent this scenario, software should ensure the
conversion result data transfer blocking mechanism (discussed in Section
12.4.5.2, “Completing Conversions) is cleared when entering stop3 and
continuing ADC conversions.
12.4.12 MCU Stop2 Mode Operation
The ADC module is automatically disabled when the MCU enters stop2 mode. All module registers
contain their reset values following exit from stop2. Therefore, the module must be re-enabled and
re-configured following exit from stop2.
12.5
Initialization Information
This section gives an example that provides some basic direction on how to initialize and configure the
ADC module. You can configure the module for 8-, 10-, 12-, or 16-bit single-ended resolution or 9-, 11-,
13-, or 16-bit differential resolution, single or continuous conversion, and a polled or interrupt approach,
among many other options. Refer to Table 12-8, Table 12-9, and Table 12-10 for information used in this
example.
NOTE
Hexadecimal values designated by a preceding 0x, binary values designated
by a preceding %, and decimal values have no preceding character.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
12-39
Analog-to-Digital Converter (S08ADC16V1)
12.5.1
12.5.1.1
ADC Module Initialization Example
Initialization Sequence
Before the ADC module can be used to complete conversions, an initialization procedure must be
performed. A typical sequence is as follows:
1. Calibrate the ADC by following the calibration instructions in Section 12.4.7.
2. Update the configuration register (ADCCFG) to select the input clock source and the divide ratio
used to generate the internal clock, ADCK. This register is also used for selecting sample time and
low-power configuration.
3. Update status and control register 2 (ADCSC2) to select the conversion trigger (hardware or
software) and compare function options, if enabled.
4. Update status and control register 3 (ADSC3) to select whether conversions will be continuous or
completed only once (ADCO) and to select whether to perform hardware averaging.
5. Update status and control register (ADCSC1:ADCSC1n) to select whether conversions will be
single-ended or differential and to enable or disable conversion complete interrupts. The input
channel on which conversions will be performed is also selected here.
12.5.1.2
Pseudo-Code Example
In this example, the ADC module is set up with interrupts enabled to perform a single 10-bit conversion
at low power with a long sample time on input channel 1, where the internal ADCK clock is derived from
the bus clock divided by 1.
ADCCFG = 0x98 (%10011000)
Bit 7
ADLPC
1
Configures for low power (lowers maximum clock speed.
Bit 6:5
ADIV
00
Sets the ADCK to the input clock  1.
Bit 4
ADLSMP
1
Configures for long sample time.
Bit 3:2
MODE
10
Sets mode at 10-bit conversions.
Bit 1:0
ADICLK
00
Selects bus clock as input clock source.
ADCSC2 = 0x00 (%00000000)
Bit 7
ADACT
0
Flag indicates if a conversion is in progress.
Bit 6
ADTRG
0
Software trigger selected.
Bit 5
ACFE
0
Compare function disabled.
Bit 4
ACFGT
0
Not used in this example.
Bit 3:2
00
Reserved, always reads zero.
Bit 1:0
00
Reserved for Freescale’s internal use; always write zero.
ADCSC1A = 0x41 (%01000001)
Bit 7
COCOA
0
Read-only flag which is set when a conversion completes.
Bit 6
AIENA
1
Conversion complete interrupt enabled.
Bit 5
ADCOA
0
One conversion only (continuous conversions disabled).
Bit 4:0
ADCHA
00001
Input channel 1 selected as ADC input channel.
MCF51MM256 Series Devices Reference Manual, Rev. 3
12-40
Freescale Semiconductor
Analog-to-Digital Converter (S08ADC16V1)
ADCRHA/LA = 0xxx
Holds results of conversion. Read high byte (ADCRHA) before low byte (ADCRLA) so that
conversion data cannot be overwritten with data from the next conversion.
ADCCVH/L = 0xxx
Holds compare value when compare function enabled.
APCTL1=0x02
AD1 pin I/O control disabled. All other AD pins remain general purpose I/O pins.
APCTL2=0x00
All other AD pins remain general purpose I/O pins.
Reset
Initialize ADC
ADCCFG = 0x98
ADCSC2 = 0x00
ADCSC1n = 0x41
Check
COCOn=1?
No
Yes
Read ADCRHn
Then ADCRLn To
Clear COCOn Bit
Continue
Figure 12-40. Initialization Flowchart for Example
12.6
Application Information
This section contains information for using the ADC module in applications. The ADC has been designed
to be integrated into a microcontroller for use in embedded control applications requiring an A/D
converter.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
12-41
Analog-to-Digital Converter (S08ADC16V1)
12.6.1
External Pins and Routing
The following sections discuss the external pins associated with the ADC module and how they should be
used for best results.
12.6.1.1
Analog Supply Pins
The ADC module has analog power and ground supplies (VDDAD and VSSAD) available as separate pins
on some devices. VSSAD is shared on the same pin as the MCU digital VSS on some devices. On other
devices, VSSAD and VDDAD are shared with the MCU digital supply pins. In these cases, there are separate
pads for the analog supplies bonded to the same pin as the corresponding digital supply so that some degree
of isolation between the supplies is maintained.
When available on a separate pin, both VDDAD and VSSAD must be connected to the same voltage potential
as their corresponding MCU digital supply (VDD and VSS) and must be routed carefully for maximum
noise immunity and bypass capacitors placed as near as possible to the package.
If separate power supplies are used for analog and digital power, the ground connection between these
supplies must be at the VSSAD pin. This should be the only ground connection between these supplies if
possible. The VSSAD pin makes a good single point ground location.
12.6.1.2
Analog Voltage Reference Pins
In addition to the analog supplies, the ADC module has connections for two reference voltage inputs used
by the converter, VREFSH and VREFSL. VREFSH is the high reference voltage for the converter. VREFSL is
the low reference voltage for the converter.
The ADC can be configured to accept one of three voltage reference pairs for VREFSH and VREFSL. Each
pair contains a positive reference and a ground reference. The three pairs are external (VREFH and VREFL),
alternate (VALTH and VALTL) and the internal bandgap (VBGH and VBGL). These voltage references are
selected using the REFSEL bits in the ADCSC2 register. The alternate (VALTH and VALTL) voltage
reference pair may select additional external pins or internal sources depending on MCU configuration.
Consult the module introduction for information on the Voltage References specific to this MCU.
In some packages, the external or alternate pairs are connected in the package to VDDAD and VSSAD,
respectively. One of these positive references may be shared on the same pin as VDDAD on some devices.
One of these ground references may be shared on the same pin as VSSAD on some devices.
If externally available, the positive reference may be connected to the same potential as VDDAD or may be
driven by an external source to a level between the minimum Ref Voltage High (defined in Appendix A)
and the VDDAD potential (the positive reference must never exceed VDDAD). If externally available, the
ground reference must be connected to the same voltage potential as VSSAD. The voltage reference pairs
must be routed carefully for maximum noise immunity and bypass capacitors placed as near as possible to
the package.
AC current in the form of current spikes required to supply charge to the capacitor array at each successive
approximation step is drawn through the VREFH and VREFL loop. The best external component to meet this
current demand is a 0.1 F capacitor with good high frequency characteristics. This capacitor is connected
between VREFH and VREFL and must be placed as near as possible to the package pins. Resistance in the
MCF51MM256 Series Devices Reference Manual, Rev. 3
12-42
Freescale Semiconductor
Analog-to-Digital Converter (S08ADC16V1)
path is not recommended because the current causes a voltage drop that could result in conversion errors.
Inductance in this path must be minimum (parasitic only).
12.6.1.3
Analog Input Pins
The external analog inputs are typically shared with digital I/O pins on MCU devices. The pin I/O control
is disabled by setting the appropriate control bit in one of the pin control registers. Conversions can be
performed on inputs without the associated pin control register bit set. It is recommended that the pin
control register bit always be set when using a pin as an analog input. This avoids problems with contention
because the output buffer is in its high impedance state and the pullup is disabled. Also, the input buffer
draws DC current when its input is not at VDD or VSS. Setting the pin control register bits for all pins used
as analog inputs should be done to achieve lowest operating current.
Empirical data shows that capacitors on the analog inputs improve performance in the presence of noise
or when the source impedance is high. Use of 0.01 F capacitors with good high-frequency characteristics
is sufficient. These capacitors are not necessary in all cases, but when used they must be placed as near as
possible to the package pins and be referenced to VSSA.
For proper conversion, the input voltage must fall between VREFH and VREFL. If the input is equal to or
exceeds VREFH, the converter circuit converts the signal to 0xFFF (full scale 12-bit representation), 0x3FF
(full scale 10-bit representation) or 0xFF (full scale 8-bit representation). If the input is equal to or less
than VREFL, the converter circuit converts it to 0x000. Input voltages between VREFH and VREFL are
straight-line linear conversions. There is a brief current associated with VREFL when the sampling
capacitor is charging.
For minimal loss of accuracy due to current injection, pins adjacent to the analog input pins should not be
transitioning during conversions.
12.6.2
Sources of Error
Several sources of error exist for A/D conversions. These are discussed in the following sections.
12.6.2.1
Sampling Error
For proper conversions, the input must be sampled long enough to achieve the proper accuracy. Given the
maximum input resistance of approximately 7k and input capacitance of approximately 5.5 pF, sampling
to within 1/4LSB (at 12-bit resolution) can be achieved within the minimum sample window (3.5 cycles @
8 MHz maximum ADCK frequency) provided the resistance of the external analog source (RAS) is kept
below 2 k.
Higher source resistances or higher-accuracy sampling is possible by setting ADLSMP and changing the
ADLSTS bits (to increase the sample window) or decreasing ADCK frequency to increase sample time.
12.6.2.2
Pin Leakage Error
Leakage on the I/O pins can cause conversion error if the external analog source resistance (RAS) is high.
If this error cannot be tolerated by the application, keep RAS lower than VDDAD / (2N*ILEAK) for less than
1/4LSB leakage error (N = 8 in 8-bit, 10 in 10-bit or 12 in 12-bit mode).
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
12-43
Analog-to-Digital Converter (S08ADC16V1)
12.6.2.3
Noise-Induced Errors
System noise that occurs during the sample or conversion process can affect the accuracy of the
conversion. The ADC accuracy numbers are guaranteed as specified only if the following conditions are
met:
• There is a 0.1 F low-ESR capacitor from VREFH to VREFL.
• There is a 0.1 F low-ESR capacitor from VDDAD to VSSAD.
• If inductive isolation is used from the primary supply, an additional 1 F capacitor is placed from
VDDAD to VSSAD.
• VSSAD (and VREFL, if connected) is connected to VSS at a quiet point in the ground plane.
• Operate the MCU in wait or stop3 mode before initiating (hardware triggered conversions) or
immediately after initiating (hardware or software triggered conversions) the ADC conversion.
— For software triggered conversions, immediately follow the write to ADCSC1 with a stop
instruction.
— For stop3 mode operation, select ADACK as the clock source. Operation in stop3 reduces VDD
noise but increases effective conversion time due to stop recovery.
• There is no I/O switching, input or output, on the MCU during the conversion.
There are some situations where external system activity causes radiated or conducted noise emissions or
excessive VDD noise is coupled into the ADC. In these situations, or when the MCU cannot be placed in
wait or stop3 or I/O activity cannot be halted, these recommended actions may reduce the effect of noise
on the accuracy:
• Place a 0.01 F capacitor (CAS) on the selected input channel to VREFL or VSSAD (this improves
noise issues, but affects the sample rate based on the external analog source resistance).
• Average the result by converting the analog input many times in succession and dividing the sum
of the results. Four samples are required to eliminate the effect of a 1LSB, one-time error.
• Reduce the effect of synchronous noise by operating off the asynchronous clock (ADACK) and
averaging. Noise that is synchronous to ADCK cannot be averaged out.
12.6.2.4
Code Width and Quantization Error
The ADC quantizes the ideal straight-line transfer function into 4096 steps (in 12-bit mode). Each step
ideally has the same height (1 code) and width. The width is defined as the delta between the transition
points to one code and the next. The ideal code width for an N bit converter (in this case N can be 8, 10 or
12), defined as 1LSB, is:
1 lsb = (VREFH - VREFL) / 2N
Eqn. 12-4
There is an inherent quantization error due to the digitalization of the result. For 8-bit or 10-bit conversions
the code transitions when the voltage is at the midpoint between the points where the straight line transfer
function is exactly represented by the actual transfer function. Therefore, the quantization error will be 
1/2 lsb in 8- or 10-bit mode. As a consequence, however, the code width of the first (0x000) conversion is
only 1/2 lsb and the code width of the last (0xFF or 0x3FF) is 1.5 lsb.
MCF51MM256 Series Devices Reference Manual, Rev. 3
12-44
Freescale Semiconductor
Analog-to-Digital Converter (S08ADC16V1)
For 12-bit conversions the code transitions only after the full code width is present, so the quantization
error is 1 lsb to 0 lsb and the code width of each step is 1 lsb.
12.6.2.5
Linearity Errors
The ADC may also exhibit non-linearity of several forms. Every effort has been made to reduce these
errors but the system should be aware of them because they affect overall accuracy. These errors are:
• Zero-scale error (EZS) (sometimes called offset) — This error is defined as the difference between
the actual code width of the first conversion and the ideal code width (1/2 lsb in 8-bit or 10-bit
modes and 1 lsb in 12-bit mode). If the first conversion is 0x001, the difference between the actual
0x001 code width and its ideal (1 lsb) is used.
• Full-scale error (EFS) — This error is defined as the difference between the actual code width of
the last conversion and the ideal code width (1.5 lsb in 8-bit or 10-bit modes and 1LSB in 12-bit
mode). If the last conversion is 0x3FE, the difference between the actual 0x3FE code width and its
ideal (1LSB) is used.
• Differential non-linearity (DNL) — This error is defined as the worst-case difference between the
actual code width and the ideal code width for all conversions.
• Integral non-linearity (INL) — This error is defined as the highest-value the (absolute value of the)
running sum of DNL achieves. More simply, this is the worst-case difference of the actual
transition voltage to a given code and its corresponding ideal transition voltage, for all codes.
• Total unadjusted error (TUE) — This error is defined as the difference between the actual transfer
function and the ideal straight-line transfer function and includes all forms of error.
12.6.2.6
Code Jitter, Non-Monotonicity, and Missing Codes
Analog-to-digital converters are susceptible to three special forms of error. These are code jitter,
non-monotonicity, and missing codes.
Code jitter is when, at certain points, a given input voltage converts to one of two values when sampled
repeatedly. Ideally, when the input voltage is infinitesimally smaller than the transition voltage, the
converter yields the lower code (and vice-versa). However, even small amounts of system noise can cause
the converter to be indeterminate (between two codes) for a range of input voltages around the transition
voltage. This range is normally around ±1/2 lsb in 8-bit or 10-bit mode, or around 2 lsb in 12-bit mode,
and increases with noise.
This error may be reduced by repeatedly sampling the input and averaging the result. Additionally the
techniques discussed in Section 12.6.2.3 reduces this error.
Non-monotonicity is defined as when, except for code jitter, the converter converts to a lower code for a
higher input voltage. Missing codes are those values never converted for any input value.
In 8-bit or 10-bit mode, the ADC is guaranteed to be monotonic and have no missing codes.
V
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
12-45
Analog-to-Digital Converter (S08ADC16V1)
MCF51MM256 Series Devices Reference Manual, Rev. 3
12-46
Freescale Semiconductor
Chapter 13
Cyclic Redundancy Check (CRC)
13.1
Introduction
The CRC block provides hardware acceleration for CRC16-CCITT compliancy with x16 + x12 + x5 + 1
polynomial. It is implemented on the 8-bit peripheral bus, and provides a very simple programming
interface of only two 8-bit registers. The V1 ColdFire 8-bit peripheral bus bridge serializes 16-bit accesses
into two 8-bit accesses, so both registers can be read/written using a single 16-bit read/write instruction.
This peripheral is available in both RUN and LPRUN modes.
NOTE
For details on low-power mode operation, refer to Table 3-4 in Chapter 3,
“Modes of Operation”.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
13-1
Cyclic Redundancy Check (CRC)
Figure 13-1. Block Diagram with the CRC Module Highlighted
MCF51MM256 Series Devices Reference Manual, Rev. 3
13-2
Freescale Semiconductor
Cyclic Redundancy Check (CRC)
13.1.1
Features
Features of the CRC module include:
• Hardware CRC generator circuit using 16-bit shift register
• CRC16-CCITT compliancy with x16 + x12 + x5 + 1 polynomial
• Error detection for all single, double, odd, and most multi-bit errors
• Programmable initial seed value
• High-speed CRC calculation
• Optional feature to transpose input data and CRC result via transpose register, required on
applications where bytes are in LSb (Least Significant bit) format.
13.1.2
Modes of Operation
This section defines the CRC operation in run, wait, and stop modes.
• Run Mode — This is the basic mode of operation.
• Wait Mode — The CRC module is operational.
• Stop 2 Modes —The CRC module is not functional in these modes and will be put into its reset
state upon recovery from stop.
• Stop 3 Mode — In this mode, the CRC module will go into a low-power standby state. Any CRC
calculations in progress will stop and resume after the CPU goes into run mode.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
13-3
Cyclic Redundancy Check (CRC)
13.1.3
Block Diagram
Figure 13-2 provides a block diagram of the CRC module.
7
0
CRC Low Register (CRCL)
15
14
12
13
11
6
......
5
4
3
2
1
0
16-bit CRC Generator Circuit
15
8
CRC High Register (CRCH)
Figure 13-2. Cyclic Redundancy Check (CRC) Module Block Diagram
13.2
External Signal Description
There are no CRC signals that connect off chip.
13.3
13.3.1
Register Definition
Memory Map
Table 13-1. CRC Register Summary
Name
CRCH
(offset=0)
7
6
5
4
3
2
1
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
R
W
MCF51MM256 Series Devices Reference Manual, Rev. 3
13-4
Freescale Semiconductor
Cyclic Redundancy Check (CRC)
Table 13-1. CRC Register Summary
Name
CRCL
(offset=1)
7
6
5
4
3
2
1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
W
TRANSPOSE R
(offset=2)
W
NOTE
The transpose feature (offset=2) is optional. If this feature is required by the
MCU, parameter TRANSPOSE_FEATURE should be 1’b1. Otherwise, it
should be 1’b0 (default).
NOTE
Offsets 4,5,6 and 7 are also mapped onto the CRCL register. This is an alias
only used on CF1Core (version 1 of ColdFire core) and should be ignored
for HCS08 cores. See Section 13.4.2, “Programming model extension for
CF1Core for more details.
13.3.2
Register Descriptions
The CRC module includes:
• A 16-bit CRC result and seed register (CRCH:CRCL)
• An 8-bit transpose register to convert from LSb to MSb format (or vice-versa) when required by
the application
Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address
assignments for all CRC registers. This section refers to registers only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
13.3.2.1
CRC High Register (CRCH)
7
6
5
4
3
2
1
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0
0
0
0
0
0
0
0
R
W
Reset
Figure 13-3. CRC High Register (CRCH)
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
13-5
Cyclic Redundancy Check (CRC)
Table 13-2. Register Field Descriptions
Field
Description
7:0
CRCH
CRCH — This is the high byte of the 16-bit CRC register. A write to CRCH will load the high byte of the initial 16-bit
seed value directly into bits 15-8 of the shift register in the CRC generator. The CRC generator will then expect the
low byte of the seed value to be written to CRCL and loaded directly into bits 7-0 of the shift register. Once both seed
bytes written to CRCH:CRCL have been loaded into the CRC generator, and a byte of data has been written to
CRCL, the shift register will begin shifting. A read of CRCH will read bits 15-8 of the current CRC calculation result
directly out of the shift register in the CRC generator.
13.3.2.2
CRC Low Register (CRCL)
7
6
5
4
3
2
1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 13-4. CRC Low Register (CRCL)
Table 13-3. Register Field Descriptions
Field
Description
7:0
CRCL
CRCL — This is the low byte of the 16-bit CRC register. Normally, a write to CRCL will cause the CRC generator to
begin clocking through the 16-bit CRC generator. As a special case, if a write to CRCH has occurred previously, a
subsequent write to CRCL will load the value in the register as the low byte of a 16-bit seed value directly into bits
7-0 of the shift register in the CRC generator. A read of CRCL will read bits 7-0 of the current CRC calculation result
directly out of the shift register in the CRC generator.
13.3.2.3
Transpose Register (TRANSPOSE)
7
6
5
4
3
2
1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 13-5. CRC High Register (CRCH)
Table 13-4. Register Field Descriptions
Field
Description
7:0
TRANSPOSE -- This register is used to transpose data, converting from LSb to MSb (or vice-versa). The byte to be
TRANSP transposed should be first written to TRANSPOSE and then subsequent reads from TRANSPOSE will return the
OSE
transposed value of the last written byte (bit 7 becomes bit 0, bit 6 becomes bit 1, and so forth).
MCF51MM256 Series Devices Reference Manual, Rev. 3
13-6
Freescale Semiconductor
Cyclic Redundancy Check (CRC)
13.4
Functional Description
To enable the CRC function, a write to the CRCH register will trigger the first half of the seed mechanism
which will place the CRCH value directly into bits 15-8 of the CRC generator shift register. The CRC
generator will then expect a write to CRCL to complete the seed mechanism.
As soon as the CRCL register is written to, its value will be loaded directly into bits 7-0 of the shift register,
and the second half of the seed mechanism will be complete. This value in CRCH:CRCL will be the initial
seed value in the CRC generator.
Now the first byte of the data on which the CRC calculation will be applied should be written to CRCL.
This write after the completion of the seed mechanism will trigger the CRC module to begin the CRC
checking process. The CRC generator will shift the bits in the CRCL register (MSB first) into the shift
register of the generator. One Bus cycle after writing to CRCL all 8 bits have been shifted into the CRC
generator, and then the result of the shifting, or the value currently in the shift register, can be read directly
from CRCH:CRCL, and the next data byte to include in the CRC calculation can be written to the CRCL
register.
This next byte will then also be shifted through the CRC generator’s 16-bit shift register, and after the
shifting has been completed, the result of this second calculation can be read directly from CRCH:CRCL.
After each byte has finished shifting, a new CRC result will appear in CRCH:CRCL, and an additional
byte may be written to the CRCL register to be included within the CRC16-CCITT calculation. A new
CRC result will appear in CRCH:CRCL each time 8-bits have been shifted into the shift register.
To start a new CRC calculation, write to CRCH, and the seed mechanism for a new CRC calculation will
begin again.
13.4.1
ITU-T (CCITT) Recommendations and Expected CRC Results
The CRC polynomial 0x1021 (x16 + x12 + x5 + 1) is popularly known as CRC-CCITT since it was initially
proposed by the ITU-T (formerly CCITT) committee.
Although the ITU-T recommendations are very clear about the polynomial to be used, 0x1021, they accept
variations in the way the polynomial is implemented:
•
•
ITU-T V.41 implements the same circuit shown in Figure 13-2, but it recommends a SEED =
0x0000.
ITU-T T.30 and ITU-T X.25 implement the same circuit shown in Figure 13-2, but they
recommend the final CRC result to be negated (one-complement operation). Also, they
recommend a SEED = 0xFFFF.
Moreover, it is common to find circuits in literature slightly different from the one suggested by the
recommendations above, but also known as CRC-CCITT circuits (many variations require the message to
be augmented with zeros).
The circuit implemented in the CRC module is exactly the one suggested by the ITU-T V.41
recommendation, with an added flexibility of a programmable SEED. As in ITU-T V.41, no augmentation
is needed and the CRC result is not negated. Table 13-5 shows some expected results that can be used as
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
13-7
Cyclic Redundancy Check (CRC)
a reference. Notice that these are ASCII string messages. For example, message “123456789” is encoded
with bytes 0x31 to 0x39 (see ASCII table).
Table 13-5. Expected CRC results
ASCII String Message
1
13.4.2
SEED
CRC result
(initial CRC value)
“A”
0x0000
0x58e5
“A”
0xffff
0xb915
“A”
0x1d0f1
0x9479
“123456789”
0x0000
0x31c3
“123456789”
0xffff
0x29b1
“123456789”
0x1d0f1
0xe5cc
A string of 256 upper case “A”
characters with no line breaks
0x0000
0xabe3
A string of 256 upper case “A”
characters with no line breaks
0xffff
0xea0b
A string of 256 upper case “A”
characters with no line breaks
0x1d0f1
0xe938
One common variation of CRC-CCITT require the message to
be augmented with zeros and a SEED=0xFFFF. The CRC
module will give the same results of this alternative
implementation when SEED=0x1D0F and no message
augmentation.
Programming model extension for CF1Core
The CRC module extends its original programming model to allow faster CRC calculations on CF1 cores.
Memory offsets 0x4, 0x5, 0x6 and 0x7 are mapped (aliased) onto the CRCL register, in a way that the
CF1Core can execute 32-bit store instructions to write data to the CRC module. The code should use a
single mov.l store instruction to send four bytes beginning at address 0x4, which will be decomposed by
the platform into four sequential/consecutive byte writes to offsets 0x4-0x7 (all aliased to the CRCL
position).
In addition, reads from 0x4-0x7 return the contents of the CRCL register. Reads from 0x2-0x3
(unused/reserved) return 0x00. Writes to 0x2-0x3 have no effect.
Due to internal CF1Core characteristics, this approach provides a greater data transfer rate than the original
programming model used on HCS08 (single byte writes to CRCL position). Figure 13-6 illustrates a
message calculation on CF1Core.
MCF51MM256 Series Devices Reference Manual, Rev. 3
13-8
Freescale Semiconductor
Cyclic Redundancy Check (CRC)
load seed
(0xffff)
1
write data (0x31 to 0x39),
mov.l + mov.l + mov.b
stall
cycle*
2
3
4
5
6
7
8
9
10
11
12
0x0
0x1
0x4
0x5
0x6
0x7
0x4
0x5
0x6
0x7
0x1
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
13
read CRC
result
14
15
16
ipg_clk
ips_addr
0x0
0x1
ips_module_en
ips_rwb
ips_xfr_wait
ips_wdata
0xff
ips_rdata
0x29
0xb1
* On cycle 13, there is a read-after-write hazard, since calculation of 0x39 data is underway. ips_xfr_wait is asserted to signalize
a stall cycle (the IPS master should wait until cycle 14 to read the CRC result).
Figure 13-6. CRC calculation of ASCII message “123456789” (0x31 to 0x39) on CF1Core
13.4.3
Transpose feature
The CRC module provides an optional feature to transpose data (invert bit order). This feature is specially
useful on applications where the LSb format is used, since the CRC CCITT expects data in the MSb
format. In that case, before writing new data bytes to CRCL, these bytes should be transposed as follows:
1. Write data byte to TRANSPOSE register
2. Read data from TRANSPOSE register (subsequent reads will result in the transposed value of the
last written data)
3. Write transposed byte to CRCL.
After all data is fed into CRC, the CRCH:CRCL result is available in the MSb format. Then, these two
bytes should also be transposed: the values read from CRCH:CRCL should be written/read to/from the
TRANSPOSE register.
Although the transpose feature was initially designed to address LSb applications interfacing with the CRC
module, it is important to notice that this feature is not necessarily tied to CRC applications. Since it was
designed as an independent register, any application should be able to transpose data by writing/reading
to/from the TRANSPOSE register (e.g. Big endian / Little endian conversion in USB).
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
13-9
Cyclic Redundancy Check (CRC)
13.5
Initialization Information
To initialize the CRC Module and initiate a CRC16-CCITT calculation, follow this procedure:
1. Write high byte of initial seed value to CRCH.
2. Write low byte of initial seed value to CRCL.
3. Write first byte of data on which CRC is to be calculated to CRCL (an alternative option is offered
for CF1Cores. See Section 13.4.2, “Programming model extension for CF1Core).
4. In the next bus cycle after step 3, if desired, the CRC result from the first byte can be read from
CRCH:CRCL.
5. Repeat steps 3-4 until the end of all data to be checked.
MCF51MM256 Series Devices Reference Manual, Rev. 3
13-10
Freescale Semiconductor
Chapter 14
Carrier Modulator Timer (CMT)
14.1
Introduction
The CMT consists of a carrier generator, modulator, and transmitter that drives the infrared out (IRO) pin.
14.2
Clock Selection
The SOPT2[CMT_CLK_SEL] bit selects between bus clock and bus clock divided by 3 as the CMT input
clock. This bit can be used to implement a slower timebase for the CMT, when in high bus speed
configurations.
NOTE
In the S08 MM core, the bus clock is the only clock source for CMT.
14.3
IRO Pin Description
The IRO pin is the only pin associated with the CMT. The pin is driven by the transmitter output when the
CMTMSC[MCGEN] bit and the CMTOC[IROPEN] bit are set. If MCGEN is clear and the IROPEN bit
is set, the pin is driven by the CMTOC[IROL] bit. This enables user software to directly control the state
of the IRO pin by writing to the IROL bit. If IROPEN is clear, the pin is disabled and is not driven by the
CMT module. This is so the CMT can be configured as a modulo timer for generating periodic interrupts
without causing pin activity.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
14-1
Carrier Modulator Timer (CMT)
Table 14-1. Block Diagram with CMT Module Highlighted
MCF51MM256 Series Devices Reference Manual, Rev. 3
14-2
Freescale Semiconductor
Carrier Modulator Timer (CMT)
14.4
Features
The CMT consists of a carrier generator, modulator, and transmitter which drives the infrared out pin. The
features of this module include:
• Four modes of operation
— Time with independent control of high and low times
— Baseband
— Frequency shift key (FSK)
— Direct software control of IRO pin
• Extended space operation in time, baseband, and FSK modes
• Selectable input clock divide: 1, 2, 4, or 8
• Interrupt on end of cycle
— Ability to disable IRO pin and use as timer interrupt
14.5
CMT Block Diagram
PRIMARY/SECONDARY SELECT
CLOCK
CONTROL CMTCLK
MODULATOR
IRO
PIN
TRANSMITTER
OUTPUT
IROL
IROPEN
CMTPOL
MCGEN
CMTCMD REGS
MIREQ
EOC INT EN
EOC FLAG
EXSPC
BASE
FSK
CMTCG REGS
CMTDIV
CARRIER
GENERATOR
MODULATOR
OUT
CARRIER
OUT (fcg)
CMT REGISTERS
AND BUS INTERFACE
CMT
input clock
INTERNAL BUS
IIREQ
Figure 14-1. Carrier Modulator Transmitter Module Block Diagram
14.6
External Signal Descriptions
There is only one pin associated with the CMT, the IRO pin. The pin is driven by the transmitter output
when the MCGEN bit in the CMTMSC register is set and the IROPEN bit in the CMTOC register is set.
If the MCGEN bit is clear and the IROPEN bit is set, the pin is driven by the IROL bit in the CMTOC
register. This enables user software to directly control the state of the IRO pin by writing to the IROL bit.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
14-3
Carrier Modulator Timer (CMT)
If the IROPEN bit is clear, the pin is disabled and is not driven by the CMT module. This is so the CMT
can be configured as a modulo timer for generating periodic interrupts without causing pin activity.
14.7
Register Definition
The following registers control and monitor CMT operation:
•
•
•
•
CMT carrier generator data registers (CMTCGH1, CMTCGL1, CMTCGH2, CMTCGL2)
CMT output control register (CMTOC)
CMT modulator status and control register (CMTMSC)
CMT modulator period data registers (CMTCMD1, CMTCMD2, CMTCMD3, CMTCMD4)
14.7.1
Carrier Generator Data Registers (CMTCGH1, CMTCGL1,
CMTCGH2, and CMTCGL2)
The carrier generator data registers contain the primary and secondary high and low values for generating
the carrier output.
CMTCGH1
7
6
5
4
3
2
1
0
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
Reset:
U
U
U
U
U
U
U
U
CMTCGL1
7
6
5
4
3
2
1
0
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
Reset:
U
U
U
U
U
U
U
U
CMTCGH2
7
6
5
4
3
2
1
0
SH7
SH6
SH5
SH4
SH3
SH2
SH1
SH0
Reset:
U
U
U
U
U
U
U
U
CMTCGL2
7
6
5
4
3
2
1
0
SL7
SL6
SL5
SL4
SL3
SL2
SL1
SL0
U
U
U
U
U
U
U
U
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Reset:
Figure 14-2. CMT Carrier Generator Data Registers (CMTCGH1, CMTCGL1, CMTCGH2, CMTCGL2)
MCF51MM256 Series Devices Reference Manual, Rev. 3
14-4
Freescale Semiconductor
Carrier Modulator Timer (CMT)
Table 14-2. Carrier High and Low Time Data Values
Carrier
Data Values
Primary Carrier High
and Low Time Data
Values
Secondary Carrier High
and Low Time Data
Values
14.7.2
Description
When selected, these bits contain the number of input clocks required to
generate the carrier high and low time periods. When operating in time
mode (see Section 14.8.2.1, “Time Mode”) this register pair is always
selected. When operating in FSK mode (see Section 14.8.2.3, “FSK
Mode”) this register pair and the secondary register pair are alternately
selected under control of the modulator. The primary carrier high and low
time values are undefined out of reset. These bits must be written to
nonzero values before the carrier generator is enabled to avoid spurious
results.
PH0–PH7 and
PL0–PL7
SH0–SH7 and
SL0–SL7
When selected, these bits contain the number of input clocks required to
generate the carrier high and low time periods. When operating in time
mode (see Section 14.8.2.1, “Time Mode”) this register pair is never
selected. When operating in FSK mode (see Section 14.8.2.3, “FSK
Mode”) this register pair and the primary register pair are alternately
selected under control of the modulator. The secondary carrier high and
low time values are undefined out of reset. These bits must be written to
nonzero values before the carrier generator is enabled when operating in
FSK mode.
CMT Output Control Register (CMTOC)
This register is used to control the IRO output of the CMT module.
7
6
5
IROL
CMTPOL
IROPEN
0
0
0
R
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
W
Reset:
Figure 14-3. CMT Output Control Register (CMTOC)
Table 14-3. PRACMPxCS Field Descriptions
Field
Description
7
IROL
IRO Latch Control
Reading IROL reads the state of the IRO latch. Writing IROL changes the state of the IRO pin when the MCGEN
bit in the CMTMSC register is clear and the IROPEN bit is set.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
14-5
Carrier Modulator Timer (CMT)
Table 14-3. PRACMPxCS Field Descriptions (Continued)
Field
Description
6
CMTPOL
CMT Output Polarity
The CMTPOL bit controls the polarity of the IRO pin output of the CMT.
1 IRO pin is active high
0 IRO pin is active low
5
IROPEN
IRO Pin Enable
The IROPEN bit is used to enable and disable the IRO pin. When the pin is enabled, it is an output which drives
out either the CMT transmitter output or the state of the IROL bit depending on whether the MCGEN bit in the
CMTMSC register is set or not. Also, the state of the output is either inverted or not depending on the state of the
CMTPOL bit. When the pin is disabled, it is in a high impedance state so as not to draw any current. The pin is
disabled during reset.
0 IRO pin disabled
1 IRO pin enabled as output
14.7.3
CMT Modulator Status and Control Register
The CMT modulator status and control register (CMTMSC) contains the modulator and carrier generator
enable (MCGEN), end of cycle interrupt enable (EOCIE), FSK mode select (FSK), baseband enable
(BASE), extended space (EXSPC), prescaler (CMTDIV) bits, and the end of cycle (EOCF) status bit.
7
R
6
5
4
3
2
1
0
EXSPC
BASE
FSK
EOCIE
MCGEN
0
0
0
0
0
EOCF
CMTDIV
W
Reset:
0
0
0
Figure 14-4. CMT Modulator Status and Control Register (CMTMSC)
MCF51MM256 Series Devices Reference Manual, Rev. 3
14-6
Freescale Semiconductor
Carrier Modulator Timer (CMT)
Table 14-4. PRACMPxCS Field Descriptions
Field
Description
7
EOCF
End Of Cycle Status Flag
The EOCF bit is set when:
• The modulator is not currently active and the MCGEN bit is set to begin the initial CMT transmission.
• At the end of each modulation cycle while the MCGEN bit is set. This is recognized when a match occurs
between the contents of the space period register and the down counter. At this time, the counter is initialized
with the (possibly new) contents of the mark period buffer, CMTCMD1 and CMTCMD2, and the space period
register is loaded with the (possibly new) contents of the space period buffer, CMTCMD3 and CMTCMD4.
This flag is cleared by a read of the CMTMSC register followed by an access of CMTCMD2 or CMTCMD4.
In the case where the MCGEN bit is cleared and then set before the end of the modulation cycle, EOCF will not
be set when MCGEN is set, but will be set at the end of the current modulation cycle.
0 No end of modulation cycle occurrence since flag last cleared
1 End of modulator cycle has occurred
6–5
CMTDIV
CMT Clock Divide Prescaler
The CMT clock divide prescaler causes the CMT to be clocked at the CMT input clock frequency, or the CMT
input clock frequency divided by 1, 2 ,4, or 8. Since these bits are not double buffered, they should not be changed
during a transmission.
00 CMT input clock 1
01 CMT input clock 2
10 CMT input clock 4
11 CMT input clock 8
4
EXSPC
Extended Space Enable
The EXSPC bit enables extended space operation
1 Extended space enabled
0 Extended space disabled
3
BASE
2
FSK
1
EOCIE
0
MCGEN
Baseband Enable
When set, the BASE bit disables the carrier generator and forces the carrier output high for generation of
baseband protocols. When BASE is clear, the carrier generator is enabled and the carrier output toggles at the
frequency determined by values stored in the carrier data registers. See Section 14.8.2.2, “Baseband Mode”.
This bit is cleared by reset. This bit is not double buffered and should not be written to during a transmission.
0 Baseband mode disabled
1 Baseband mode enabled
FSK Mode Select
The FSK bit enables FSK operation
0 CMT operates in Time or Baseband mode
1 CMT operates in FSK mode
End of Cycle Interrupt Enable
A CPU interrupt will be requested when EOCF is set if EOCIE is high.0CPU interrupt disabled
1 CPU interrupt enabled
Modulator and Carrier Generator Enable
Setting MCGEN will initialize the carrier generator and modulator and will enable all clocks. Once enabled, the
carrier generator and modulator will function continuously. When MCGEN is cleared, the current modulator cycle
will be allowed to expire before all carrier and modulator clocks are disabled (to save power) and the modulator
output is forced low. To prevent spurious operation, the user should initialize all data and control registers before
enabling the system.
0 Modulator and carrier generator disabled
1 Modulator and carrier generator enabled
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
14-7
Carrier Modulator Timer (CMT)
14.7.4
CMT Modulator Data Registers (CMTCMD1, CMTCMD2, CMTCMD3
and CMTCMD4)
The modulator data registers control the mark and space periods of the modulator for all modes. The
contents of these registers are transferred to the modulator down counter and space period register upon
the completion of a modulation period.
CMTCMD1
7
6
5
4
3
2
1
0
MB15
MB14
MB13
MB12
MB11
MB10
MB9
MB8
R
W
Reset:
CMTCMD2
Unaffected by Reset
7
6
5
4
3
2
1
0
MB7
MB6
MB5
MB4
MB3
MB2
MB1
MB0
R
W
Reset:
CMTCMD3
Unaffected by Reset
7
6
5
4
3
2
1
0
SB15
SB14
SB13
SB12
SB11
SB10
SB9
SB8
R
W
Reset:
CMTCMD4
Unaffected by Reset
7
6
5
4
3
2
1
0
SB7
SB6
SB5
SB4
SB3
SB2
SB1
SB0
R
W
Reset:
Unaffected by Reset
Figure 14-5. CMT Modulator Data Registers (CMTCMD1, CMTCMD2, CMTCMD3 and CMTCMD4)
14.8
Functional Description
The CMT module consists of a carrier generator, a modulator, a transmitter output and control registers.
The block diagram is shown in Figure 14-1. The module has three main modes of operation:
• Time
• Baseband
• Frequency shift key (FSK).
When operating in time mode, the user independently defines the high and low times of the carrier signal
to determine both period and duty cycle. The carrier generator resolution is 125 ns when operating with an
8 MHz internal bus frequency and the CMTMSC[CMTDIV] equal 00. The carrier generator can generate
MCF51MM256 Series Devices Reference Manual, Rev. 3
14-8
Freescale Semiconductor
Carrier Modulator Timer (CMT)
signals with periods between 250 ns (4 MHz) and 127.5 s (7.84 kHz) in steps of 125 ns. The table below
shows the relationship between the clock divide bits and the carrier generator resolution, minimum carrier
generator period, and minimum modulator period.
Table 14-5. Clock Divide
CMT Input
Clock (MHz)
CMTDIV
Carrier Generator
Resolution (s)
Min Carrier
Generator Period
(s)
Min
Modulator Period
(s)
8
00
0.125
0.25
1.0
8
01
0.25
0.5
2.0
8
10
0.5
1.0
4.0
8
11
1.0
2.0
8.0
The possible duty cycle options will depend upon the number of counts required to complete the carrier
period. For example, a 1.6 MHz signal has a period of 625 ns and will therefore require 5 x 125 ns counts
to generate. These counts may be split between high and low times, so the duty cycles available will be
20% (one high, four low), 40% (two high, three low), 60% (three high, two low) and 80% (four high, one
low).
For lower frequency signals with larger periods, higher resolution (as a percentage of the total period) duty
cycles are possible.
When the BASE bit in the CMT modulator status and control register (CMTMSC) is set, the carrier output
(fcg) to the modulator is held to IRO pin active level continuously to allow for the generation of baseband
protocols.
A third mode allows the carrier generator to alternate between two sets of high and low times. When
operating in FSK mode, the generator will toggle between the two sets when instructed by the modulator,
allowing the user to dynamically switch between two carrier frequencies without CPU intervention.
The modulator provides a simple method to control protocol timing. The modulator has a minimum
resolution of 1.0 s with an 8 MHz internal CMT input clock. It can count bus clocks (to provide real-time
control) or it can count carrier clocks (for self-clocked protocols). See Section 14.8.2, “Modulator” for
more details.
The transmitter output block controls the state of the infrared out pin (IRO). The modulator output is gated
on to the IRO pin when the modulator/carrier generator is enabled.
A summary of the possible modes is shown in Table 14-6.
Table 14-6. CMT Modes of Operation
Mode
Time
MCGEN
Bit1
BASE
Bit2
FSK
Bit(2)
EXSPC
Bit
1
0
0
0
Comment
fcg controlled by primary high and low registers.
fcg transmitted to IRO pin when modulator gate is open.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
14-9
Carrier Modulator Timer (CMT)
Table 14-6. CMT Modes of Operation (Continued)
Mode
MCGEN
Bit1
BASE
Bit2
FSK
Bit(2)
EXSPC
Bit
Baseband
1
1
x
0
fcg is always active level. IRO pin active level when modulator
gate is open.
FSK
1
0
1
0
fcg control alternates between primary high/low registers and
secondary high/low registers.
fcg transmitted to IRO pin when modulator gate is open.
Extended
Space
1
x
x
1
Setting the EXSPC bit causes subsequent modulator cycles to
be spaces (modulator out not asserted) for the duration of the
modulator period (mark and space times).
IRO Latch
0
x
x
x
IROL bit controls state of IRO pin.
1
2
Comment
To prevent spurious operation, initialize all data and control registers before beginning a transmission (MCGEN=1).
These bits are not double buffered and should not be changed during a transmission (while MCGEN=1).
14.8.1
Carrier Generator
The carrier signal is generated by counting a register-selected number of input clocks (125 ns for an 8 MHz
bus) for both the carrier high time and the carrier low time. The period is determined by the total number
of clocks counted. The duty cycle is determined by the ratio of high time clocks to total clocks counted.
The high and low time values are user programmable and are held in two registers.
An alternate set of high/low count values is held in another set of registers to allow the generation of dual
frequency FSK (frequency shift keying) protocols without CPU intervention.
NOTE
Only non-zero data values are allowed. The carrier generator will not work
if any of the count values are equal to zero.
The MCGEN bit in the CMTMSC register must be set and the BASE bit must be cleared to enable carrier
generator clocks. When the BASE bit is set, the carrier output to the modulator is held to IRO pin active
level continuously. The block diagram is shown in Figure 14-1.
MCF51MM256 Series Devices Reference Manual, Rev. 3
14-10
Freescale Semiconductor
Carrier Modulator Timer (CMT)
SECONDARY HIGH COUNT REGISTER
PRIMARY HIGH COUNT REGISTER
CMTCLK
BASE
FSK
MCGEN
CLOCK AND OUTPUT CONTROL
=?
CARRIER OUT (fcg)
CLK
CLR
8-BIT UP COUNTER
PRIMARY/
SECONDARY
SELECT
=?
SECONDARY LOW COUNT REGISTER
PRIMARY LOW COUNT REGISTER
Figure 14-6. Carrier Generator Block Diagram
The high/low time counter is an 8-bit up counter. After each increment, the contents of the counter are
compared with the appropriate high or low count value register. When the compare value is reached, the
counter is reset to a value of 0x01, and the compare is redirected to the other count value register.
Assuming that the high time count compare register is currently active, a valid compare will cause the
carrier output to be driven IRO pin active level. The counter will continue to increment (starting at reset
value of 0x01). When the value stored in the selected low count value register is reached, the counter will
again be reset and the carrier output will be driven IRO pin inactive level.
The cycle repeats, automatically generating a periodic signal which is directed to the modulator. The
lowest frequency (maximum period) and highest frequency (minimum period) which can be generated are
defined as:
fmax = fCMTCLK(2 x 1) Hz
Eqn. 14-1
fmin = fCMTCLK(2 x (28 – 1)) Hz
Eqn. 14-2
In the general case, the carrier generator output frequency is:
fcg = fCMTCLK (Highcount + Lowcount) Hz
Eqn. 14-3
Where:
0 < Highcount < 256 and
0 < Lowcount < 256
The duty cycle of the carrier signal is controlled by varying the ratio of high time to low + high time. As
the input clock period is fixed, the duty cycle resolution will be proportional to the number of counts
required to generate the desired carrier period.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
14-11
Carrier Modulator Timer (CMT)
Highcount
Duty Cycle = ---------------------------------------------------------------Highcount + Lowcount
14.8.2
Eqn. 14-4
Modulator
The modulator has three main modes of operation:
• The modulator can gate the carrier onto the modulator output (Time mode)
• The modulator can control the logic level of the modulator output (Baseband mode)
• The modulator can count carrier periods and instruct the carrier generator to alternate between two
carrier frequencies whenever a modulation period (mark + space counts) expires (FSK mode)
The modulator includes a 17-bit down counter with underflow detection. The counter is loaded from the
16-bit modulation mark period buffer registers, CMTCMD1 and CMTCMD2. The most significant bit is
loaded with a logic zero and serves as a sign bit. When the counter holds a positive value, the modulator
gate is open and the carrier signal is driven to the transmitter block.
When the counter underflows, the modulator gate is closed and a 16-bit comparator is enabled which
compares the logical complement of the value of the down counter with the contents of the modulation
space period register which has been loaded from the registers, CMTCMD3 and CMTCMD4.
When a match is obtained the cycle repeats by opening the modulator gate, reloading the counter with the
contents of CMTCMD1 and CMTCMD2, and reloading the modulation space period register with the
contents of CMTCMD3 and CMTCMD4.
Should the contents of the modulation space period register be all zeroes, the match will be immediate and
no space period will be generated (for instance, for FSK protocols which require successive bursts of
different frequencies).
The MCGEN bit in the CMTMSC register must be set to enable the modulator timer.
MCF51MM256 Series Devices Reference Manual, Rev. 3
14-12
Freescale Semiconductor
Carrier Modulator Timer (CMT)
16 BITS
0
MODE
CMTCMD1:CMTCMD2
8
CMTCLOCK
CLOCK CONTROL
.
MS BIT
COUNTER
17-BIT DOWN COUNTER *
CARRIER OUT (fcg)
16
LOAD
MODULATOR GATE
.
MODULATOR
OUT
EOC FLAG SET
=?
SYSTEM CONTROL
EOCIE
EXSPC
SPACE PERIOD REGISTER *
BASE
FSK
16
MODULE INTERRUPT REQUEST
PRIMARY/SECONDARY SELECT
CMTCMD3:CMTCMD4
16 BITS
* DENOTES HIDDEN REGISTER
Figure 14-7. Modulator Block Diagram
14.8.2.1
Time Mode
When the modulator operates in time mode (MCGEN bit is set, BASE bit is clear, and FSK bit is clear),
the modulation mark period consists of an integer number of CMTCLK8 clock periods. The modulation
space period consists of zero or an integer number of CMTCLK8 clock periods. With an 8 MHz bus and
CMTDIV = 00, the modulator resolution is 1 s and has a maximum mark and space period of about
65.535 ms each. See Figure 14-8 for an example of the time mode and baseband mode outputs.
The mark and space time equations for time and baseband mode are:
tmark = (CMTCMD1:CMTCMD2 + 1) fCMTCLK 
Eqn. 14-5
tspace = CMTCMD3:CMTCMD4 fCMTCLK 
Eqn. 14-6
where CMTCMD1:CMTCMD2 and CMTCMD3:CMTCMD4 are the decimal values of the concatenated
registers.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
14-13
Carrier Modulator Timer (CMT)
CMTCLK  8
Carrier out (fcg)
Modulator Gate
Mark
Space
Mark
IRO pin (time mode)
IRO pin
(baseband mode)
CMTOC[CMTPOL]=0
Figure 14-8. Example CMT Output in Time and Baseband Modes
14.8.2.2
Baseband Mode
Baseband mode (MCGEN bit is set and BASE bit is set) is a derivative of time mode, where the mark and
space period is based on (CMTCLK8) counts. The mark and space calculations are the same as in time
mode. In this mode the modulator output will be at active level for the duration of the mark period and at
an inactive level for the duration of a space period. See Figure 14-8 for an example of the output for both
baseband and time modes. In the example, the carrier out frequency (fcg) is generated with a high count of
0x01 and a low count of 0x02 which results in a divide of 3 of CMTCLK with a 33% duty cycle. The
modulator down counter was loaded with the value 0x0003 and the space period register with 0x0002.
NOTE
The waveforms in Figure 14-8 and Figure 14-9 are for the purpose of
conceptual illustration and are not meant to represent precise timing
relationships between the signals shown.
14.8.2.3
FSK Mode
When the modulator operates in FSK mode (MCGEN bit is set, FSK bit is set, and BASE bit is clear), the
modulation mark and space periods consist of an integer number of carrier clocks (space period can be
zero). When the mark period expires, the space period is transparently started (as in time mode). The
carrier generator toggles between primary and secondary data register values whenever the modulator
space period expires.
MCF51MM256 Series Devices Reference Manual, Rev. 3
14-14
Freescale Semiconductor
Carrier Modulator Timer (CMT)
The space period provides an interpulse gap (no carrier). If CMTCMD3:CMTCMD4 = 0x0000, then the
modulator and carrier generator will switch between carrier frequencies without a gap or any carrier
glitches (zero space).
Using timing data for carrier burst and interpulse gap length calculated by the CPU, FSK mode can
automatically generate a phase-coherent, dual-frequency FSK signal with programmable burst and
interburst gaps.
The mark and space time equations for FSK mode are:
tmark = (CMTCMD1:CMTCMD2 + 1) fcg
Eqn. 14-7
tspace = CMTCMD3:CMTCMD4 fcg
Eqn. 14-8
Where fcg is the frequency output from the carrier generator. The example in figure below shows what the
IRO pin output looks like in FSK mode with the following values: CMTCMD1:CMTCMD2 = 0x0003,
CMTCMD3:CMTCMD4 = 0x0002, primary carrier high count = 0x01, primary carrier low count = 0x02,
secondary carrier high count = 0x03, and secondary carrier low count = 0x01.
CARRIER OUT (fcg)
MODULATOR GATE
MARK1
SPACE1
MARK2
SPACE2
MARK1
SPACE1
MARK2
IRO PIN
Figure 14-9. Example CMT Output in FSK Mode
14.8.2.4
Extended Space Operation
In either time, baseband or FSK mode, the space period can be made longer than the maximum possible
value of the space period register. Setting the EXSPC bit in the CMTMSC register will force the modulator
to treat the next modulation period (beginning with the next load of the counter and space period register)
as a space period equal in length to the mark and space counts combined. Subsequent modulation periods
will consist entirely of these extended space periods with no mark periods. Clearing EXSPC will return
the modulator to standard operation at the beginning of the next modulation period.
14.8.2.4.1
EXSPC Operation in Time Mode
To calculate the length of an extended space in time or baseband modes, add the mark and space times and
multiply by the number of modulation periods that EXSPC is set.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
14-15
Carrier Modulator Timer (CMT)
texspace = (tmark + tspace) x (number of modulation periods)
Eqn. 14-9
For an example of extended space operation, see Figure 14-10.
NOTE
The EXSPC feature can be used to emulate a zero mark event.
SET EXSPC
CLEAR EXSPC
Figure 14-10. Extended Space Operation
14.8.2.4.2
EXSPC Operation in FSK Mode
In FSK mode, the modulator continues to count carrier out clocks, alternating between the primary and
secondary registers at the end of each modulation period.
To calculate the length of an extended space in FSK mode, one needs to know whether the EXSPC bit was
set on a primary or secondary modulation period, as well as the total number of both primary and
secondary modulation periods completed while the EXSPC bit is high. A status bit for the current
modulation is not accessible to the CPU. If necessary, software should maintain tracking of the current
modulation cycle (primary or secondary). The extended space period ends at the completion of the space
period time of the modulation period during which the EXSPC bit is cleared.
If the EXSPC bit was set during a primary modulation cycle, use the equation:
texspace = (tspace)p + (tmark + tspace)s + (tmark + tspace)p +...
Eqn. 14-10
Where the subscripts p and s refer to mark and space times for the primary and secondary modulation
cycles.
If the EXSPC bit was set during a secondary modulation cycle, use the equation:
texspace = (tspace)s + (tmark + tspace)p + (tmark + tspace)s +...
14.8.3
Eqn. 14-11
Transmitter
The transmitter output block controls the state of the infrared out pin (IRO). The modulator output is gated
on to the IRO pin when the modulator/carrier generator is enabled. When the modulator/carrier generator
is disabled, the IRO pin is controlled by the state of the IRO latch.
A polarity bit in the CMTOC register enables the IRO pin to be high true or low true.
14.8.4
CMT Interrupts
The end of cycle flag (EOCF) is set when:
MCF51MM256 Series Devices Reference Manual, Rev. 3
14-16
Freescale Semiconductor
Carrier Modulator Timer (CMT)
•
•
The modulator is not currently active and the MCGEN bit is set to begin the initial CMT
transmission
At the end of each modulation cycle (when the counter is reloaded from CMTCMD1:CMTCMD2)
while the MCGEN bit is set
In the case where the MCGEN bit is cleared and then set before the end of the modulation cycle, the EOCF
bit will not be set when the MCGEN is set, but will become set at the end of the current modulation cycle.
When the MCGEN becomes disabled, the CMT module does not set the EOC flag at the end of the last
modulation cycle.
The EOCF bit is cleared by reading the CMT modulator status and control register (CMTMSC) followed
by an access of CMTCMD2 or CMTCMD4.
If the EOC interrupt enable (EOCIE) bit is high when the EOCF bit is set, the CMT module will generate
an interrupt request. The EOCF bit must be cleared within the interrupt service routine to prevent another
interrupt from being generated after exiting the interrupt service routine.
The EOC interrupt is coincident with loading the down-counter with the contents of
CMTCMD1:CMTCMD2 and loading the space period register with the contents of
CMTCMD3:CMTCMD4. The EOC interrupt provides a means for the user to reload new mark/space
values into the modulator data registers. Modulator data register updates will take effect at the end of the
current modulation cycle. Note that the down-counter and space period register are updated at the end of
every modulation cycle, irrespective of interrupt handling and the state of the EOCF flag.
14.8.5
14.8.5.1
Low-Power Mode Operation
Wait Mode Operation
During wait mode the CMT, if enabled, will continue to operate normally. However, there will be no new
codes or changes of pattern mode while in wait mode, because the CPU is not operating.
14.8.5.2
Stop3 Mode Operation
During Stop3 mode, clocks to the CMT module are halted. No registers are affected.
Note that because the clocks are halted, the CMT will resume upon exit from Stop3. Software should
ensure that the Stop3 mode is not entered while the modulator is still in operation to prevent the IRO pin
from being asserted while in Stop3 mode. This may require a time-out period from the time that the
MCGEN bit is cleared to allow the last modulator cycle to complete.
14.8.5.3
Stop2 Mode Operation
During Stop2 mode, the CMT module is completely powered off internally and the IRO pin state at the
time that Stop2 mode is entered is latched and held. To prevent the IRO pin from being asserted while in
Stop2 mode, software should assure that the pin is not active when entering Stop2 mode. Upon wake-up
from Stop2 mode, the CMT module will be in the reset state.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
14-17
Carrier Modulator Timer (CMT)
14.8.5.4
Background Mode Operation
When the microcontroller is in active background mode, the CMT temporarily suspends all counting until
the microcontroller returns to normal user mode.
MCF51MM256 Series Devices Reference Manual, Rev. 3
14-18
Freescale Semiconductor
Chapter 15
12-bit Digital to Analog Converter (DAC12LVLPv1)
15.1
Introduction
The 12-bit Digital to Analog converter (DAC) can provide a voltage output on the DACO pin. Figure 15-1
shows the block diagram with the DAC highlighted.
15.1.1
DAC Clock Gating
The bus clock to the DAC can be gated on and off using the DAC bit in SCGC1. These bits are set after
any reset, which enables the bus clock to this module. To conserve power, these bits can be cleared to
disable the clock to this module when not in use. See Section 5.6, “Peripheral Clock Gating,” for details.
15.1.2
DAC Vext and Vint Configuration
On this device, Vext is connected to VDDA and Vint is connected to the bandgap voltage, Vrefo.
15.1.3
DAC Hardware Trigger Configuration
On this device, the hardware trigger is connected to the PDB output.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
15-1
12-bit Digital to Analog Converter (DAC12LVLPv1)
Figure 15-1. Block Diagram Highlighting DAC Blocks and Pins
MCF51MM256 Series Devices Reference Manual, Rev. 3
15-2
Freescale Semiconductor
12-bit Digital to Analog Converter (DAC12LVLPv1)
15.1.4
Features
The DAC module features include:
• 1.8 V — 3.6 V operation.
• On-chip programmable reference generator output (1/4096 Vin to Vin, step is 1/4096 Vin)
• Vin can be selected from two reference sources:
— While VDDA is 1.8 V ~ 3.6 V, VREFH_EXT (VDDA) can be used and guaranteed.
— While VDDA is 2.4 V ~ 3.6 V, both VREFH_INT (output of VREF) and VREFH_EXT
(VDDA) can be used and guaranteed.
• Optional operation in STOP3 mode
• 16-word data buffer supported with configurable watermark and multiple operation modes
15.1.5
Block Diagram
Figure 15-2 is the block diagram of the DAC module.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
15-3
12-bit Digital to Analog Converter (DAC12LVLPv1)
Vext
Vint
DACRFS
MUX
AMP Buffer
Vin
DACEN
-
MUX
4096-level
LPEN
VDD
Vout
Vo
+
DACDAT[11:0]
12
DAC Hardware Trigger
DACBFWMF
DACBWIE
DACSWTRG
DACBFWM
DACBFEN
&
DACBFRPTF
DATA
BUFFER
DACBFUP
DACBTIE
dac_interrupt
&
OR
DACBFRPBF
DACBFRP
DACBBIE
&
DACBFMD
DACTSEL
Figure 15-2. DAC Block Diagram
15.2
Register Definition
The DAC has 20 8-bit registers to control analog comparator and programmable voltage divider to perform
the Digital to Analog functions.
MCF51MM256 Series Devices Reference Manual, Rev. 3
15-4
Freescale Semiconductor
12-bit Digital to Analog Converter (DAC12LVLPv1)
15.2.1
DAC Data Register x (DACDATxH:DACDATxL)
7
6
5
4
3
2
1
0
0
0
0
R
DACDATx[7:0]
W
Reset
0
0
0
0
0
Figure 15-3. DAC Data Register x Low (DACDATxL)
7
6
5
4
3
2
1
0
R
DACDATx[11:8]
W
Reset
0
0
0
0
0
0
0
0
Figure 15-4. DAC Data Register x High (DACDATxH)
When the DAC Buffer is not enabled, DACDAT0[11:0] controls the output voltage based on the following
formula.
Vout = Vin * (1+DACDAT0[11:0])/4096
Eqn. 15-1
When the DAC Buffer is enabled, DACDATx[11:0] is mapped to the 16-word buffer. Refer to 3.1 “DAC
Buffer Operation” for details.
When writing a new value to DAC Data Register x (DACDATxH:DACDATxL), the write order should be
DACDATxH first, then DACDATxL. Otherwise the value will not be properly loaded to the effective DAC
hard block and a mismatch between the DAC output may be observed. Reading DACDATx as the
write-value does not mean the value is properly loaded to the DAC hard block. Therefore, the write
sequence of high byte first then low byte must be followed.
15.2.2
DAC Status Register (DACS)
7
2
1
0
R
DACWM
DACRPT
DACRPB
W
0
0
0
0
1
0
Reset
6
0
0
5
0
4
0
3
0
Figure 15-5. DAC Status Register
NOTE
If one of the flag is set, it must be cleared by software, or it will keep it’s
value. Write zero value to the status register, the relevant bit (s) will be
cleared. It’s no effect to write 1 to this register. After reset, DACRPT is set,
it can be cleared by software if needed. The flag registers can be set only
when the data buffer status is changed.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
15-5
12-bit Digital to Analog Converter (DAC12LVLPv1)
Table 15-1. DAC Status Register
Field
Description
7:3
Reserved
2
DACWM
DAC buffer watermark flag.
0 The DAC buffer read pointer doesn’t reach the watermark level
1 The DAC buffer read pointer reaches the watermark level
1
DACRPT
DAC buffer read pointer top position flag.
0 The DAC buffer read pointer is not zero
1 The DAC buffer read pointer is zero
0
DACRPB
DAC buffer read pointer bottom position flag.
0 The DAC buffer read pointer isn’t equal to the DACBFUP
1 The DAC buffer read pointer is equal to the DACBFUP.
15.2.3
DAC Control Register (DACC0)
7
6
5
4
3
2
1
0
DACEN
DACRFS
DACTSEL
DACSTRG
LPEN
DACWIE
DACTIE
DACBIE
0
0
0
0
0
0
0
0
R
W
Reset
Figure 15-6. DAC Control Register 0 (DACC0)
Table 15-2. DACC0 Field Descriptions
Field
7
DACEN
Description
DAC enable — The DACEN bit starts the Programmable Reference Generator operation.
0 The DAC system is disabled.
1 The DAC system is enabled.
6
DACRFS
DAC Reference Select
0 The DAC selects Vint as the reference voltage.
1 The DAC selects Vext as the reference voltage.
5
DACTSEL
DAC trigger select
0 The DAC hardware trigger is selected.
1 The DAC software trigger is selected.
4
DACSTRG
DAC software trigger — active high. This is a write-only bit; it is always “0” when read. If the DAC software
trigger is selected and buffer enabled, writing a 1 to this bit advances the buffer read pointer once.
0 The DAC soft trigger is not valid.
1 The DAC soft trigger is valid.
3
LPEN
2
DACWIE
DAC low power control
0 High power mode.
1 Low power mode.
DAC buffer watermark interrupt enable.
0 The DAC buffer watermark interrupt is disabled.
1 The DAC buffer watermark interrupt is enabled.
MCF51MM256 Series Devices Reference Manual, Rev. 3
15-6
Freescale Semiconductor
12-bit Digital to Analog Converter (DAC12LVLPv1)
Table 15-2. DACC0 Field Descriptions (Continued)
Field
Description
1
DACTIE
DAC buffer read pointer top flag interrupt enable.
0 The DAC buffer read pointer top flag interrupt is disabled.
1 The DAC buffer read pointer top flag interrupt is enabled.
0
DACBIE
DAC buffer read pointer bottom flag interrupt enable.
0 The DAC buffer read pointer bottom flag interrupt is disabled.
1 The DAC buffer read pointer bottom flag interrupt is enabled.
15.2.4
DAC Control Register1 (DACC1)
7
6
5
4
3
2
1
0
R
DACBFWM
DACBFMD
DACBFE
W
Reset
0
0
0
0
0
0
0
0
Figure 15-7. DAC Control Register 1 (DACC1)
Table 15-3. DACC1 Field Descriptions
Field
7:3
Description
Reserved
4:3
DACBFWM
DAC Buffer Watermark Select — When the word number between the read pointer and the upper address
is equal to DACBFWM, the DACWM bit in status register will be set. DACWM can be used to inform the
software need to refresh the DAC buffer.
00 1 word
01 2 words
10 3 words
11 4 words
2:1
DACBFMD
DAC Buffer Work Mode Select
00 Normal mode
01 Swing mode
10 One-time scan mode
11 Reserved
0
DACBFE
DAC Buffer Enable
0 Buffer read pointer disabled. The converted data is always the first word of the buffer.
1 Buffer read pointer enabled. The converted data is the word that the read pointer points to. It means
converted data can be from any word of the buffer.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
15-7
12-bit Digital to Analog Converter (DAC12LVLPv1)
15.2.5
DAC Control Register 2 (DACC2)
7
6
5
4
3
2
1
0
1
1
R
DACBFRP
DACBFUP
W
Reset
0
0
0
0
1
1
Figure 15-8. DAC Control Register 2 (DACC2)
Table 15-4. DACC2 Field Descriptions
Field
Description
7:4
DACBFRP
DAC Buffer Read Pointer — These 4 bits keep the current value of the buffer read pointer
3:0
DACBFUP
DAC Buffer Upper Limit — These 4 bits select the buffer’s upper limit. The buffer read pointer cannot exceed
it.
15.3
Functional Description
The 12-bit Digital-to-Analog Convertor (DAC12LVLP) module can select one of two reference inputs
Vin1 and Vin2 as the DAC reference voltage (Vin) by DACRFS bit of DACC0 register. Refer to the module
introduction for information on the source for Vext and Vint. When the DAC12LVLP is enabled, it converts
the data in DACDAT0[11:0] or the data from the DAC data buffer to a stepped analog output voltage. The
output voltage range is from Vin/4096 to Vin, and the step is Vin/4096.
15.3.1
DAC Data Buffer Operation
When the DAC is enabled and the buffer isn’t enabled, the DAC12LVLP module always converts the data
in DACDAT0 to analog output voltage.
When both the DAC and the buffer are enabled, the DAC12LVLP converts the data in the data buffer to
analog output voltage. The data buffer read pointer advances to the next word in the event the hardware
trigger or the software trigger occurs. Refer to the DAC12LVLP Introduction section for the hardware
trigger connection. The data buffer can be configured to operate in normal mode, swing mode, or one-time
scan mode. When the buffer operation is switched from one mode to another, the read pointer doesn’t
change. The read pointer can be set to any value between 0 and DACBFUP by writing DACBFRP in
DACC2.
15.3.1.1
Buffer Normal Mode
This is the default mode. The buffer works as a circular buffer. The read pointer increases by one every
time when the trigger occurs. When the read pointer reaches the upper limit, it goes to the zero directly in
the next trigger event.
MCF51MM256 Series Devices Reference Manual, Rev. 3
15-8
Freescale Semiconductor
12-bit Digital to Analog Converter (DAC12LVLPv1)
15.3.1.2
Buffer Swing Mode
This mode is similar to the Normal mode. But when the read pointer reaches the upper limit, it doesn’t go
to the zero. It will descend by one in the next trigger events until zero is reached.
15.3.1.3
Buffer One-time Scan Mode
The read pointer increases by one every time the trigger occurs. When it reaches the upper limit, it stops.
If the read pointer is reset to an address other than the upper limit, it will increase to the upper address and
then stop.
NOTE
If the software set the read pointer to the upper limit, the read pointer will
not advance in this mode.
15.3.2
Resets
During reset, the DAC12LVLP is configured in the default mode. DAC12LVLP is disabled.
15.3.3
15.3.3.1
Low Power Mode Operation
Wait Mode Operation
In wait mode, the DAC12LVLP operates normally if enabled.
15.3.3.2
Stop Mode Operation
The DAC12LVLP continues to operate in stop3 mode if enabled, the output voltage will hold the value
before STOP.
In stop2 mode, the DAC12LVLP is fully shut down.
15.3.4
Background Mode Operation
When the MCU is in active background mode, the DAC12LVLP operates normally.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
15-9
12-bit Digital to Analog Converter (DAC12LVLPv1)
MCF51MM256 Series Devices Reference Manual, Rev. 3
15-10
Freescale Semiconductor
Chapter 16
Inter-Integrated Circuit (S08IICV3)
16.1
Introduction
The inter-integrated circuit (IIC) provides a method of communication between a number of devices. The
interface is designed to operate up to 100 kbps with maximum bus loading and timing. The device is
capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading. The
maximum communication length and the number of devices that can be connected are limited by a
maximum bus capacitance of 400 pF.
•
•
16.1.1
NOTE
MCF51MM256 series devices do not include stop1 mode. Please ignore
references to stop1.
The SDA and SCL should not be driven above VDD. These pins are
pseudo open-drain and contain a protection diode to VDD.
Module Configuration
The IIC module pins, SDA and SCL can be repositioned under software control using IICPS in SOPT3 as
shown in Table 16-1. IICPS in SOPT3 selects which general-purpose I/O ports are associated with IIC
operation.
Table 16-1. IIC Position Options
16.1.2
IICPS in SOPT3
Port Pin for SDA
Port Pin for SCL
0 (default)
PTD4
PTD5
1
PTF4
PTF3
IIC Clock Gating
The bus clock to the IIC can be gated on and off using the IIC bit in SCGC1. This bit is set after any reset,
which enables the bus clock to this module. To conserve power, the IIC bit can be cleared to disable the
clock to this module when not in use. See Section 5.7.7, “System Clock Gating Control 1 Register
(SCGC1),” for details.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
16-1
Inter-Integrated Circuit (S08IICV3)
Figure 16-1. Block Diagram with IIC Module Highlighted
Supports System Management Bus Specification (SMBus), version 2.
MCF51MM256 Series Devices Reference Manual, Rev. 3
16-2
Freescale Semiconductor
Inter-Integrated Circuit (S08IICV3)
16.1.3
Features
The IIC includes these distinctive features:
• Compatible with IIC bus standard
• Multi-master operation
• Software programmable for one of 64 different serial clock frequencies
• Software selectable acknowledge bit
• Interrupt driven byte-by-byte data transfer
• Arbitration lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
• START and STOP signal generation/detection
• Repeated START signal generation/detection
• Acknowledge bit generation/detection
• Bus busy detection
• General call recognition
• 10-bit address extension
• Support System Management Bus Specification(SMBus), version2
• Programmable glitch input filter
16.1.4
Modes of Operation
A brief description of the IIC in the various MCU modes follows:
• Run mode — This is the basic mode of operation. To conserve power in this mode, disable the
module.
• Wait mode — The module continues to operate while the MCU is in wait mode and can provide
a wake-up interrupt.
• Stop mode — The IIC is inactive in stop3 mode for reduced power consumption. The STOP
instruction does not affect IIC register states. Stop2 will reset the register contents.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
16-3
Inter-Integrated Circuit (S08IICV3)
16.1.5
Block Diagram
Figure 16-2 is a block diagram of the IIC.
ADDRESS
DATA BUS
INTERRUPT
ADDR_DECODE
CTRL_REG
DATA_MUX
FREQ_REG
ADDR_REG
STATUS_REG
DATA_REG
INPUT FILTER
SYNC
START
STOP
ARBITRATION
ACK/NACK
TIMEOUTS
CONTROL
CLOCK
CONTROL
IN/OUT
DATA
SHIFT
REGISTER
ADDRESS
COMPARE
SCL
SDA
Figure 16-2. IIC Functional Block Diagram
16.2
External Signal Description
This section describes each user-accessible pin signal.
16.2.1
SCL — Serial Clock Line
The bidirectional SCL is the serial clock line of the IIC system.
16.2.2
SDA — Serial Data Line
The bidirectional SDA is the serial data line of the IIC system.
MCF51MM256 Series Devices Reference Manual, Rev. 3
16-4
Freescale Semiconductor
Inter-Integrated Circuit (S08IICV3)
16.3
Register Definition
16.3.1
Module Memory Map
The IIC has ten 8-bit registers. The base address of the module is hardware programmable. The IIC register
map is fixed and begins at the module’s base address. Table 16-2 summarizes the IIC module’s address
space. The following section describes the bit-level arrangement and functionality of each register.
Table 16-2. Module Memory Map
Address
Use
Access
Base + $0000
IIC Address Register 1 (IICA1)
read/write
Base + $0001
IIC Frequency Divider Register (IICF)
read/write
Base + $0002
IIC Control Register 1 (IICC1)
read/write
Base + $0003
IIC Status Register (IICS)
read
Base + $0004
IIC Data IO Register (IICD)
read/write
Base + $0005
IIC Control Register 2 (IICC2)
read/write
Base + $0006
IIC input programmable filter (IICFLT)
read/write
Base + $0006
SMBUS IIC Control and Status Register (IICSMB)
read/write
Base + $0007
IIC Address Register 2 (IICA2)
read/write
Base + $0008
IIC SCL Low Time Out Register High (IICSLTH)
read/write
Base + $0009
IIC SCL Low Time Out Register Low (IICSLTL)
read/write
Base + $000A
IIC input programmable filter (IICFLT)
read/write
This section consists of the IIC register descriptions in address order.
Refer to the direct-page register summary in the Memory chapter of this document for the absolute address
assignments for all IIC registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
NOTE
If SMBus is selected, then the IICFLT’s address is $000A, or it should be
$0006.
16.3.2
IIC Address Register 1 (IICA1)
7
6
5
4
3
2
1
AD7
AD6
AD5
AD4
AD3
AD2
AD1
0
0
0
0
0
0
0
0
0
R
W
Reset
0
= Unimplemented or Reserved
Figure 16-3. IIC Address Register 1 (IICA1)
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
16-5
Inter-Integrated Circuit (S08IICV3)
Table 16-3. IICA1 Field Descriptions
Field
Description
7:1
AD[7:1]
Slave Address 1— The AD[7:1] field contains the slave address to be used by the IIC module. This field is used
on the 7-bit address scheme and the lower seven bits of the 10-bit address scheme.
16.3.3
IIC Frequency Divider Register (IICF)
7
6
5
4
3
2
1
0
0
0
0
R
MULT
ICR
W
Reset
0
0
0
0
0
Figure 16-4. IIC Frequency Divider Register (IICF)
Table 16-4. IICF Field Descriptions
Field
Description
7:6
MULT
IIC Multiplier Factor — The MULT bits define the multiplier factor mul. This factor is used along with the SCL
divider to generate the IIC baud rate. The multiplier factor mul as defined by the MULT bits is provided below.
00 mul = 01
01 mul = 02
10 mul = 04
11 Reserved
5:0
ICR
IIC Clock Rate — The ICR bits are used to prescale the bus clock for bit rate selection. These bits and the MULT
bits are used to determine the IIC baud rate, the SDA hold time, the SCL Start hold time and the SCL Stop hold
time. Table 16-5 provides the SCL divider and hold values for corresponding values of the ICR.
The SCL divider multiplied by multiplier factor mul is used to generate IIC baud rate.
IIC baud rate = bus speed (Hz)/(mul * SCL divider)
Eqn. 16-1
SDA hold time is the delay from the falling edge of SCL (IIC clock) to the changing of SDA (IIC data).
SDA hold time = bus period (s) * mul * SDA hold value
Eqn. 16-2
SCL Start hold time is the delay from the falling edge of SDA (IIC data) while SCL is high (Start condition) to the
falling edge of SCL (IIC clock).
SCL Start hold time = bus period (s) * mul * SCL Start hold value
Eqn. 16-3
SCL Stop hold time is the delay from the rising edge of SCL (IIC clock) to the rising edge of SDA
SDA (IIC data) while SCL is high (Stop condition).
SCL Stop hold time = bus period (s) * mul * SCL Stop hold value
Eqn. 16-4
MCF51MM256 Series Devices Reference Manual, Rev. 3
16-6
Freescale Semiconductor
Inter-Integrated Circuit (S08IICV3)
For example if the bus speed is 8MHz, the table below shows the possible hold time values with different
ICR and MULT selections to achieve an IIC baud rate of 100kbps.
Hold times (s)
MULT
ICR
SDA
SCL Start
SCL Stop
0x2
0x00
3.500
3.000
5.500
0x1
0x07
2.500
4.000
5.250
0x1
0x0B
2.250
4.000
5.250
0x0
0x14
2.125
4.250
5.125
0x0
0x18
1.125
4.750
5.125
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
16-7
Inter-Integrated Circuit (S08IICV3)
Table 16-5. IIC Divider and Hold Values
ICR
(hex)
SCL
Divider
SDA Hold
Value
SCL Hold
(Start)
Value
SCL Hold
(Stop)
Value
ICR
(hex)
SCL
Divider
SDA Hold
Value
SCL Hold
(Start)
Value
SCL Hold
(Stop)
Value
00
20
7
6
11
20
160
17
78
81
01
22
7
7
12
21
192
17
94
97
02
24
8
8
13
22
224
33
110
113
03
26
8
9
14
23
256
33
126
129
04
28
9
10
15
24
288
49
142
145
05
30
9
11
16
25
320
49
158
161
06
34
10
13
18
26
384
65
190
193
07
40
10
16
21
27
480
65
238
241
08
28
7
10
15
28
320
33
158
161
09
32
7
12
17
29
384
33
190
193
0A
36
9
14
19
2A
448
65
222
225
0B
40
9
16
21
2B
512
65
254
257
0C
44
11
18
23
2C
576
97
286
289
0D
48
11
20
25
2D
640
97
318
321
0E
56
13
24
29
2E
768
129
382
385
0F
68
13
30
35
2F
960
129
478
481
10
48
9
18
25
30
640
65
318
321
11
56
9
22
29
31
768
65
382
385
12
64
13
26
33
32
896
129
446
449
13
72
13
30
37
33
1024
129
510
513
14
80
17
34
41
34
1152
193
574
577
15
88
17
38
45
35
1280
193
638
641
16
104
21
46
53
36
1536
257
766
769
17
128
21
58
65
37
1920
257
958
961
18
80
9
38
41
38
1280
129
638
641
19
96
9
46
49
39
1536
129
766
769
1A
112
17
54
57
3A
1792
257
894
897
1B
128
17
62
65
3B
2048
257
1022
1025
1C
144
25
70
73
3C
2304
385
1150
1153
1D
160
25
78
81
3D
2560
385
1278
1281
1E
192
33
94
97
3E
3072
513
1534
1537
1F
240
33
118
121
3F
3840
513
1918
1921
MCF51MM256 Series Devices Reference Manual, Rev. 3
16-8
Freescale Semiconductor
Inter-Integrated Circuit (S08IICV3)
16.3.4
IIC Control Register (IICC1)
7
6
5
4
3
2
IICEN
IICIE
MST
TX
TXAK
RSTA
0
0
0
0
0
0
1
0
0
0
R
W
Reset
= Unimplemented or Reserved
Figure 16-5. IIC Control Register (IICC1)
Table 16-6. IICC1 Field Descriptions
Field
Description
7
IICEN
IIC Enable — The IICEN bit determines whether the IIC module is enabled.
0 IIC is not enabled.
1 IIC is enabled.
6
IICIE
IIC Interrupt Enable — The IICIE bit determines whether an IIC interrupt is requested.
0 IIC interrupt request not enabled.
1 IIC interrupt request enabled.
5
MST
Master Mode Select — When the MST bit is changed from a 0 to a 1, a START signal is generated on the bus
and master mode is selected. When this bit changes from a 1 to a 0 a STOP signal is generated and the mode
of operation changes from master to slave.
0 Slave mode.
1 Master mode.
4
TX
Transmit Mode Select — The TX bit selects the direction of master and slave transfers. In master mode this bit
should be set according to the type of transfer required. Therefore, for address cycles, this bit will always be high.
When addressed as a slave this bit should be set by software according to the SRW bit in the status register.
0 Receive.
1 Transmit.
3
TXAK
Transmit Acknowledge Enable — This bit specifies the value driven onto the SDA during data acknowledge
cycles for both master and slave receivers.
There are two conditions will effect NAK/ACK generation.
If FACK (fast NACK/ACK) is cleared,
0 An acknowledge signal will be sent out to the bus on the following receiving data byte.
1 No acknowledge signal response is sent to the bus on the following receiving data byte.
If FASK bit is set. no ACK or NACK is sent out after receiving one data byte until this TXAK bit is written
0 An acknowledge signal will be sent out to the bus on the current receiving data byte
1 No acknowledge signal response is sent to the bus on the current receiving data byte
Note: SCL is held to low until TXAK is written.
2
RSTA
(Write Only
read always
0)
Repeat START — Writing a 1 to this bit will generate a repeated START condition provided it is the current
master. Attempting a repeat at the wrong time will result in loss of arbitration.
0 No repeat start detected in bus operation.
1 Repeat start generated.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
16-9
Inter-Integrated Circuit (S08IICV3)
16.3.5
IIC Status Register (IICS)
7
R
6
5
TCF
4
BUSY
IAAS
3
2
0
SRW
ARBL
1
0
RXAK
IICIF
W
Reset
1
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 16-6. IIC Status Register (IICS)
Table 16-7. IICS Field Descriptions
Field
Description
7
TCF
Transfer Complete Flag — This bit is set on the completion of a byte and acknowledge bit transfer. Note that
this bit is only valid during or immediately following a transfer to the IIC module or from the IIC module.The TCF
bit is cleared by reading the IICD register in receive mode or writing to the IICD in transmit mode.
0 Transfer in progress.
1 Transfer complete.
6
IAAS
Addressed as a Slave — The IAAS bit is set when one of the following conditions is met
1) When the calling address matches the programmed slave address,
2) If the GCAEN bit is set and a general call is received.
3) If SIICAEN bit is set, when the calling address matches the 2nd programmed slave address
4) If ALERTEN bit is set and SMBus alert response address is received
This bit is set before ACK bit. The CPU needs to check the SRW bit and set TX/RX bit accordingly. Writing the
IICC1 register with any value clears this bit.
0 Not addressed.
1 Addressed as a slave.
5
BUSY
Bus Busy — The BUSY bit indicates the status of the bus regardless of slave or master mode. The BUSY bit is
set when a START signal is detected and cleared when a STOP signal is detected.
0 Bus is idle.
1 Bus is busy.
4
ARBL
Arbitration Lost — This bit is set by hardware when the arbitration procedure is lost. The ARBL bit must be
cleared by software, by writing a 1 to it.
0 Standard bus operation.
1 Loss of arbitration.
2
SRW
Slave Read/Write — When addressed as a slave the SRW bit indicates the value of the R/W command bit of
the calling address sent to the master.
0 Slave receive, master writing to slave.
1 Slave transmit, master reading from slave.
MCF51MM256 Series Devices Reference Manual, Rev. 3
16-10
Freescale Semiconductor
Inter-Integrated Circuit (S08IICV3)
Table 16-7. IICS Field Descriptions (Continued)
Field
Description
1
IICIF
IIC Interrupt Flag — The IICIF bit is set when an interrupt is pending. This bit must be cleared by software, by
writing a 1 to it in the interrupt routine. One of the following events can set the IICIF bit:
• One byte transfer including ACK/NACK bit completes if FACK = 0
• One byte transfer including ACK/NACK bit completes if FACK = 1 and this byte is an address byte
• One byte transfer excluding ACK/NCAK bit completes if FACK = 1 and this byte is a data byte. an ACK or
NACK is sent out on the bus by writing 0 or 1 to TXAK after this bit is set.
• Match of slave addresses to calling address (Primary Slave address, General Call address, Alert
Response address, and Second Slave address) (Received address is stored in data register)
• Arbitration lost
• Timeouts in SMBus mode except high timeout
0 No interrupt pending.
1 Interrupt pending.
NOTE: The IICIF will be cleared right after 1 bus cycle delay after writing a logic 1 to it.
0
RXAK
Receive Acknowledge — When the RXAK bit is low, it indicates an acknowledge signal has been received after
the completion of one byte of data transmission on the bus. If the RXAK bit is high it means that no acknowledge
signal is detected.
0 Acknowledge received.
1 No acknowledge received.
16.3.6
IIC Data I/O Register (IICD)
7
6
5
4
3
2
1
0
0
0
0
0
R
DATA
W
Reset
0
0
0
0
Figure 16-7. IIC Data I/O Register (IICD)
Table 16-8. IICD Field Descriptions
Field
Description
7:0
DATA
Data — In master transmit mode, when data is written to the IICD, a data transfer is initiated. The most significant
bit is sent first. In master receive mode, reading this register initiates receiving of the next byte of data.
NOTE
When transitioning out of master receive mode, the IIC mode should be
switched before reading the IICD register to prevent an inadvertent
initiation of a master receive data transfer.
In slave mode, the same functions are available after an address match has occurred.
Note that the TX bit in IICC must correctly reflect the desired direction of transfer in master and slave
modes for the transmission to begin. For instance, if the IIC is configured for master transmit but a master
receive is desired, then reading the IICD will not initiate the receive.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
16-11
Inter-Integrated Circuit (S08IICV3)
Reading the IICD will return the last byte received while the IIC is configured in either master receive or
slave receive modes. The IICD does not reflect every byte that is transmitted on the IIC bus, nor can
software verify that a byte has been written to the IICD correctly by reading it back.
In master transmit mode, the first byte of data written to IICD following assertion of MST (Start bit) or
assertion of RSTA bit (repeated Start ) is used for the address transfer and should comprise of the calling
address (in bit 7 to bit 1) concatenated with the required R/W bit (in position bit 0).
MCF51MM256 Series Devices Reference Manual, Rev. 3
16-12
Freescale Semiconductor
Inter-Integrated Circuit (S08IICV3)
16.3.7
IIC Control Register 2 (IICC2)
7
6
GCAEN
ADEXT
0
0
R
5
4
3
0
0
0
2
1
0
AD10
AD9
AD8
0
0
0
W
Reset
0
0
0
= Unimplemented or Reserved
Figure 16-8. IIC Control Register (IICC2)
Table 16-9. IICC2 Field Descriptions
Field
Description
7
GCAEN
General Call Address Enable — The GCAEN bit enables or disables general call address.
0 General call address is disabled
1 General call address is enabled.
6
ADEXT
Address Extension — The ADEXT bit controls the number of bits used for the slave address.
0 7-bit address scheme
1 10-bit address scheme
2:0
AD[10:8]
Slave Address — The AD[10:8] field contains the upper three bits of the slave address in the 10-bit address
scheme. This field is only valid when the ADEXT bit is set.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
16-13
Inter-Integrated Circuit (S08IICV3)
16.3.8
IIC SMBus Control and Status Register (IICSMB)
7
6
5
4
3
FACK
ALERTEN
SIICAEN
TCKSEL
SLTF
0
0
0
0
0
R
2
1
0
0
0
SHTF
W
Reset
0
= Unimplemented or Reserved
NOTE
Table 16-10. IICSMB Field Descriptions
Field
Description
7
FACK
Fast NACK/ACK enable — For SMBus Packet Error Checking, CPU should be able to issue an ACK or NACK
according to the result of receiving data byte.
0 ACK or NACK will be sent out on the following receiving data byte.
1 Writing an 0 to TXAK after receiving data byte will generate an ACK; Writing an 1 to TXAK after receiving data
byte will generate a NACK
6
ALERTEN
SMBus Alert Response Address Enable — The ALERTEN bit enables or disable SMBus alert response
address.
0 SMBus alert response address matching is disabled
1 SMBus alert response address matching is enabled.
5
SIICAEN
Second IIC Address Enable — The SIICAEN bit enables or disable SMBus device default address.
0 IIC Address Register 2 matching is disabled.
1 IIC Address Register 2 matching is enabled.
4
TCKSEL
Time Out Counter Clock Select— This bit selects the clock sources of Time Out Counter
0 Time Out Counter counts at bus/64 frequency
1 Time Out Counter counts at the bus frequency
3
SLTF
SCL Low Timeout Flag — This read-only bit is set to logic 1 when IICSLT loaded non zero value (LoValue) and
a SCL Low Time Out occurs. This bit is cleared by software, by writting a logic 1 to it or IICIF.
0 No LOW TIME OUT occurs.
1 A LOW TIME OUT occurs.
Note: LOW TIME OUT function is disabled when IIC SCL LOW TIMER OUT register is set to zero
2
SHTF
SCL High Timeout Flag — This read-only bit is set to logic 1 when SCL and SDA are held high more than clock
* LoValue/512, which indicates the Bus Free. This bit is cleared automatically.
0 No HIGH TIMEOUT occurs.
1 An HIGH TIMEOUT occurs.
NOTE
1. A master can assume that the bus is free if it detects that the clock and
data signals have been high for greater than THIGH,MAX, however, the
SHTF will rise in bus transmission process but bus idle state.
2. When TCKSEL=1 there is no meaning to monitor SHTF since the bus
speed is too high to match the protocol of SMBus.
MCF51MM256 Series Devices Reference Manual, Rev. 3
16-14
Freescale Semiconductor
Inter-Integrated Circuit (S08IICV3)
16.3.9
IIC Address Register 2 (IICA2)
7
6
5
4
3
2
1
SAD7
SAD6
SAD5
SAD4
SAD3
SAD2
SAD1
1
1
0
0
0
0
1
0
0
R
W
Reset
0
= Unimplemented or Reserved
Field
Description
7:1
SAD[7:1]
SMBUs Address — The AD[7:1] field contains the slave address to be used by the SMBus. This field is used on
the device default address or other related address
16.3.10 IIC SCL Low Time Out Register High (IICSLTH)
7
6
5
4
3
2
1
0
SSLT15
SSLT14
SSLT13
SSLT12
SSLT11
SSLT10
SSLT9
SSLT8
0
0
0
0
0
0
0
0
R
W
Reset
= Unimplemented or Reserved
Field
Description
7:0
SSLT[15:8]
The value in this register is the most significant byte of SCL low time out value that determines the time-out period
of SCL low.
16.3.11 IIC SCL LowTime Out register Low (IICSLTL)
7
6
5
4
3
2
1
0
SSLT7
SSLT6
SSLT5
SSLT4
SSLT3
SSLT2
SSLT1
SSLT0
0
0
0
0
0
0
0
0
R
W
Reset
= Unimplemented or Reserved
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
16-15
Inter-Integrated Circuit (S08IICV3)
Field
Description
7:0
SSLT[7:0]
The value in this register is the least significant byte of SCL low time out value that determines the time-out period
of SCL low..
16.3.12 IIC Programmable Input Glitch Filter (IICFLT)
R
7
6
5
4
0
0
0
0
3
2
1
0
FLT3
FLT2
FLT1
FLT0
0
0
0
0
W
Reset
0
0
0
0
= Unimplemented or Reserved
Table 16-11. IICFLT Field Descriptions
Field
3:0
FLT
Description
IIC Programmable Filter Factor
contain the programming controls for the width of glitch (in terms of bus clock cycles) the filter
should absorb; in other words, the filter does not let glitches less than or equal to this width setting pass.
FLT[3:0]
0000 No Filter / Bypass
0001 Filter glitches up to width of 1 (half) IPBUS clock cycle
0010 Filter glitches up to width of 2 (half) IPBUS clock cycles
0011 Filter glitches up to width of 3 (half) IPBUS clock cycles
0100 Filter glitches up to width of 4 (half) IPBUS clock cycles
0101 Filter glitches up to width of 5 (half) IPBUS clock cycles
0110 Filter glitches up to width of 6 (half) IPBUS clock cycles
0111 Filter glitches up to width of 7 (half) IPBUS clock cycles
1000 Filter glitches up to width of 8 (half) IPBUS clock cycle
1001 Filter glitches up to width of 9 (half) IPBUS clock cycles
1010 Filter glitches up to width of 10 (half) IPBUS clock cycles
1011 Filter glitches up to width of 11 (half) IPBUS clock cycles
1100 Filter glitches up to width of 12 (half) IPBUS clock cycles
1101 Filter glitches up to width of 13 (half) IPBUS clock cycles
1110 Filter glitches up to width of 14 (half) IPBUS clock cycles
1111 Filter glitches up to width of 15 (half) IPBUS clock cycles
NOTE:
The width of the FLT is an integration option which can be changed in different SoCs
And Also the clock source used is an integration configurative option - It could be the 2X IPBus clock or the IPbus
clock - which one needs to be identified at architectural definition. For the 4-bit definitions above, hard
descriptions of "half" IPBUS clock cycles will not be the case when the IPBUS clock is used for filtering logic.
MCF51MM256 Series Devices Reference Manual, Rev. 3
16-16
Freescale Semiconductor
Inter-Integrated Circuit (S08IICV3)
16.4
Functional Description
This section provides a complete functional description of the IIC module.
16.4.1
IIC Protocol
The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices
connected to it must have open drain or open collector outputs. A logic AND function is exercised on both
lines with external pull-up resistors. The value of these resistors is system dependent.
Normally, a standard communication is composed of four parts:
• START signal
• Slave address transmission
• Data transfer
• STOP signal
The STOP signal should not be confused with the CPU STOP instruction. The IIC bus system
communication is described briefly in the following sections and illustrated in Figure 16-9.
MSB
SCL
SDA
1
LSB
2
3
4
5
6
7
START
SIGNAL
1
XXX
3
4
5
6
2
3
4
5
6
7
8
D7
D6
D5
D4
D3
D2
D1
D0
7
8
1
9
READ/ ACK
WRITE BIT
XX
9
NO STOP
ACK SIGNAL
BIT
MSB
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
CALLING ADDRESS
1
DATA BYTE
LSB
2
LSB
READ/ ACK
WRITE BIT
CALLING ADDRESS
MSB
SDA
9
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
START
SIGNAL
SCL
8
MSB
LSB
2
3
4
5
6
7
8
9
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
REPEATED
START
SIGNAL
NEW CALLING ADDRESS
READ/ NO STOP
SIGNAL
WRITE ACK
BIT
Figure 16-9. IIC Bus Transmission Signals
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
16-17
Inter-Integrated Circuit (S08IICV3)
16.4.1.1
START Signal
When the bus is free; in other words, no master device is engaging the bus (both SCL and SDA lines are
at logical high), a master may initiate communication by sending a START signal. As shown in
Figure 16-9, a START signal is defined as a high-to-low transition of SDA while SCL is high. This signal
denotes the beginning of a new data transfer (each data transfer may contain several bytes of data) and
brings all slaves out of their idle states.
16.4.1.2
Slave Address Transmission
The first byte of data transferred immediately after the START signal is the slave address transmitted by
the master. This is a seven-bit calling address followed by a R/W bit. The R/W bit tells the slave the desired
direction of data transfer.
1 = Read transfer, the slave transmits data to the master.
0 = Write transfer, the master transmits data to the slave.
Only the slave with a calling address that matches the one transmitted by the master will respond by
sending back an acknowledge bit. This is done by pulling the SDA low at the 9th clock (see Figure 16-9).
No two slaves in the system may have the same address. If the IIC module is the master, it must not
transmit an address that is equal to its own slave address. The IIC cannot be master and slave at the same
time. However, if arbitration is lost during an address cycle, the IIC will revert to slave mode and operate
correctly even if it is being addressed by another master.
16.4.1.3
Data Transfer
Before successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a direction
specified by the R/W bit sent by the calling master.
All transfers that come after an address cycle are referred to as data transfers, even if they carry sub-address
information for the slave device
Each data byte is 8 bits long. Data may be changed only while SCL is low and must be held stable while
SCL is high as shown in Figure 16-9. There is one clock pulse on SCL for each data bit, the MSB being
transferred first. Each data byte is followed by a 9th (acknowledge) bit, which is signalled from the
receiving device. An acknowledge is signalled by pulling the SDA low at the ninth clock. In summary, one
complete data transfer needs nine clock pulses.
If the slave receiver does not acknowledge the master in the 9th bit time, the SDA line must be left high
by the slave. The master interprets the failed acknowledge as an unsuccessful data transfer.
If the master receiver does not acknowledge the slave transmitter after a data byte transmission, the slave
interprets this as an end of data transfer and releases the SDA line.
In either case, the data transfer is aborted and the master does one of two things:
• Relinquishes the bus by generating a STOP signal.
• Commences a new calling by generating a repeated START signal.
MCF51MM256 Series Devices Reference Manual, Rev. 3
16-18
Freescale Semiconductor
Inter-Integrated Circuit (S08IICV3)
16.4.1.4
STOP Signal
The master can terminate the communication by generating a STOP signal to free the bus. However, the
master may generate a START signal followed by a calling command without generating a STOP signal
first. This is called repeated START. A STOP signal is defined as a low-to-high transition of SDA while
SCL at logical 1 (see Figure 16-9).
The master can generate a STOP even if the slave has generated an acknowledge at which point the slave
must release the bus.
16.4.1.5
Repeated START Signal
As shown in Figure 16-9, a repeated START signal is a START signal generated without first generating
a STOP signal to terminate the communication. This is used by the master to communicate with another
slave or with the same slave in different mode (transmit/receive mode) without releasing the bus.
16.4.1.6
Arbitration Procedure
The IIC bus is a true multi-master bus that allows more than one master to be connected on it. If two or
more masters try to control the bus at the same time, a clock synchronization procedure determines the bus
clock, for which the low period is equal to the longest clock low period and the high is equal to the shortest
one among the masters. The relative priority of the contending masters is determined by a data arbitration
procedure, a bus master loses arbitration if it transmits logic 1 while another master transmits logic 0. The
losing masters immediately switch over to slave receive mode and stop driving SDA output. In this case,
the transition from master to slave mode does not generate a STOP condition. Meanwhile, a status bit is
set by hardware to indicate loss of arbitration.
16.4.1.7
Clock Synchronization
Because wire-AND logic is performed on the SCL line, a high-to-low transition on the SCL line affects all
the devices connected on the bus. The devices start counting their low period and after a device’s clock has
gone low, it holds the SCL line low until the clock high state is reached. However, the change of low to
high in this device clock may not change the state of the SCL line if another device clock is still within its
low period. Therefore, synchronized clock SCL is held low by the device with the longest low period.
Devices with shorter low periods enter a high wait state during this time (see Figure 16-10). When all
devices concerned have counted off their low period, the synchronized clock SCL line is released and
pulled high. There is then no difference between the device clocks and the state of the SCL line and all the
devices start counting their high periods. The first device to complete its high period pulls the SCL line
low again.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
16-19
Inter-Integrated Circuit (S08IICV3)
DELAY
START COUNTING HIGH PERIOD
SCL1
SCL2
SCL
INTERNAL COUNTER RESET
Figure 16-10. IIC Clock Synchronization
16.4.1.8
Handshaking
The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold
the SCL low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces
the master clock into wait states until the slave releases the SCL line.
16.4.1.9
Clock Stretching
The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. After
the master has driven SCL low the slave can drive SCL low for the required period and then release it. If
the slave SCL low period is greater than the master SCL low period then the resulting SCL bus signal low
period is stretched.
MCF51MM256 Series Devices Reference Manual, Rev. 3
16-20
Freescale Semiconductor
Inter-Integrated Circuit (S08IICV3)
16.4.2
10-bit Address
For 10-bit addressing, 0x11110 is used for the first 5 bits of the first address byte. Various combinations of
read/write formats are possible within a transfer that includes 10-bit addressing.
16.4.2.1
Master-Transmitter Addresses a Slave-Receiver
The transfer direction is not changed (see Table 16-12). When a 10-bit address follows a START
condition, each slave compares the first seven bits of the first byte of the slave address (11110XX) with
its own address and tests whether the eighth bit (R/W direction bit) is 0. It is possible that more than one
device will find a match and generate an acknowledge (A1). Each slave that finds a match will compare
the eight bits of the second byte of the slave address with its own address, but only one slave will find a
match and generate an acknowledge (A2). The matching slave will remain addressed by the master until
it receives a STOP condition (P) or a repeated START condition (Sr) followed by a different slave address.
S
Slave Address 1st 7 bits
R/W
11110 + AD10 + AD9
0
Slave Address 2nd byte
A1
AD[8:1]
A2
Data
A
...
Data
A/A
P
Table 16-12. Master-Transmitter Addresses Slave-Receiver with a 10-bit Address
After the master-transmitter has sent the first byte of the 10-bit address, the slave-receiver will see an IIC
interrupt. User software must ensure that for this interrupt, the contents of IICD are ignored and not treated
as valid data.
16.4.2.2
Master-Receiver Addresses a Slave-Transmitter
The transfer direction is changed after the second R/W bit (see Table 16-13). Up to and including
acknowledge bit A2, the procedure is the same as that described for a master-transmitter addressing a
slave-receiver. After the repeated START condition (Sr), a matching slave remembers that it was addressed
before. This slave then checks whether the first seven bits of the first byte of the slave address following
Sr are the same as they were after the START condition (S), and tests whether the eighth (R/W) bit is 1. If
there is a match, the slave considers that it has been addressed as a transmitter and generates acknowledge
A3. The slave-transmitter remains addressed until it receives a STOP condition (P) or a repeated START
condition (Sr) followed by a different slave address.
After a repeated START condition (Sr), all other slave devices will also compare the first seven bits of the
first byte of the slave address with their own addresses and test the eighth (R/W) bit. However, none of
them will be addressed because R/W = 1 (for 10-bit devices), or the 11110XX slave address (for 7-bit
devices) does not match.
S
Slave Address
1st 7 bits
R/W
11110 + AD10 + AD9
0
A1
Slave Address
2nd byte
AD[8:1]
A2
Sr
Slave Address
1st 7 bits
R/W
11110 + AD10 + AD9
1
A3
Data
A
...
Data
A
P
Table 16-13. Master-Receiver Addresses a Slave-Transmitter with a 10-bit Address
After the master-receiver has sent the first byte of the 10-bit address, the slave-transmitter will see an IIC
interrupt. User software must ensure that for this interrupt, the contents of IICD are ignored and not treated
as valid data.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
16-21
Inter-Integrated Circuit (S08IICV3)
16.4.3
Address Matching
All received Addresses can be requested in 7-bit or 10-bit address. IIC Address Register 1, which contains
IIC primary slave address, always participates the address matching process. If the GCAEN bit is set,
general call will participate the address matching process. If the ALERTEN bit is set, alert response will
participate the address matching process. If SIICAEN bit is set, the IIC Address Register 2 will participate
the address matching process.
When the IIC responds to one of above mentioned address, it acts as a slave-receiver and the IAAS bit is
set after the address cycle. Software need to read the IICD register after the first byte transfer to determine
which the address is matched.
16.4.4
System Management Bus Specification
SMBus provides a control bus for system and power management related tasks. A system may use SMBus
to pass messages to and from devices instead of tripping individual control lines. Removing the individual
control lines reduces pin count. Accepting messages ensures future expandability.With System
Management Bus, a device can provide manufacturer information, tell the system what its model/part
number is, save its state for a suspend event, report different types of errors, accept control parameters, and
return its status.
16.4.4.1
Timeouts
The TTIMEOUT,MIN parameter allows a master or slave to conclude that a defective device is holding the
clock low indefinitely or a master is intentionally trying to drive devices off the bus. It is highly
recommended that a slave device release the bus (stop driving the bus and let SCL and SDA float high)
when it detects any single clock held low longer than TTIMEOUT,MIN. Devices that have detected this
condition should reset their communication and be able to receive a new START condition in no later than
TTIMEOUT,MAX.
SMBus defines a clock low time-out, TTIMEOUT of 35 ms and specifies TLOW: SEXT as the cumulative clock
low extend time for a slave device and specifies TLOW: MEXT as the cumulative clock low extend time for
a master device.
16.4.4.1.1
SCL Low Timeout
If the SCL line is held low by a slave device on the bus, no further communication is possible.
Furthermore, the master cannot force the SCL line high to correct the error condition. To solve this
problem, the SMBus protocol specifies that devices participating in a transfer must detect any clock cycle
held low longer than a “timeout” value condition. Devices that have detected the timeout condition must
reset the communication. When active master, if the IIC detects that SMBCLK low has exceeded the value
of TTIMEOUT,MIN it must generate a stop condition within or after the current data byte in the transfer
process. When slave, upon detection of the TTIMEOUT,MIN condition, the IIC shall reset its communication
and be able to receive a new START condition.
MCF51MM256 Series Devices Reference Manual, Rev. 3
16-22
Freescale Semiconductor
Inter-Integrated Circuit (S08IICV3)
16.4.4.1.2
SCL High (SMBus Free) Timeout
The IIC shall assume that the bus is idle, when it has determined that the SMBCLK and SMBDAT signals
have been high for at least THIGH:MAX.HIGH timeout can occur in two ways: 1) HIGH timeout detected
after a STOP condition appears on the bus; 2) HIGH timeout detected after a START condition, but before
a STOP condition appears on the bus.Any master detecting either scenario can assume the bus is free then
SHTF rises. HIGH timeout occurred in scenario 2 if it ever detects that both the following is true:BUSY
bit is high and SHTF is high.
16.4.4.1.3
CSMBCLK TIMEOUT MEXT
Figure1-10: Timeout measurement intervals illustrates the definition of the timeout intervals, TLOW:SEXT
and TLOW:MEXT. When master mode, the I2C must not cumulatively extend its clock cycles for a period
greater than TLOW:MEXT within a byte, where each byte is defined as START-to-ACK, ACK-to-ACK, or
ACK-to-STOP. When CSMBCLK TIMEOUT MEXT occurs SMBus MEXT will rise and also trigger the
SLTF.
16.4.4.1.4
CSMBCLK TIMEOUT SEXT
A Master is allowed to abort the transaction in progress to any slave that violates the TLOW:SEXT or
TTIMEOUT,MIN specifications. This can be accomplished by the Master issuing a STOP condition at the
conclusion of the byte transfer in progress. When slave, the I2C must not cumulatively extend its clock
cycles for a period greater than TLOW:SEXT during any message from the initial START to the STOP. When
CSMBCLK TIMEOUT SEXT occurs SEXT will rise and also trigger SLTF.
TLOW:SEXT
Start
ClkAck
TLOW:MEXT
Stop
ClkAck
TLOW:MEXT
TLOW:MEXT
SCL
SDA
Figure 16-11. Timeout measurement intervals
NOTE
CSMBCLK TIMEOUT SEXT and MEXT are optional functions which will
be implemented in second step.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
16-23
Inter-Integrated Circuit (S08IICV3)
16.4.4.2
FAST ACK and NACK
To improve reliability and communication robustness, implementation of Packet Error Checking (PEC) by
SMBus devices is optional for SMBus devices but required for devices participating in and only during
the Address Resolution Protocol (ARP) process. The PEC is a CRC-8 error checking byte, calculated on
all the message bytes. The PEC is appended to the message by the device that supplied the last data byte.
If the PEC is present but not correct, a NACK is issued by receiver. Otherwise an ACK will be issued. In
order to calculate the CRC-8 by software, this module can hold SCL line to low after receiving eighth SCL
(bit 8th) if this byte is a data byte. So software can determine whether an ACK or NACK should be sent
out to the bus by setting or clearing TXAK bit if FASK (fast ACK/NACK enable bit) is enabled.
SMBus requires devices to acknowledge their own address always, as a mechanism to detect a removable
devices presence on the bus (battery, docking station, etc.) Besides to indicate a slave device busy
condition, SMBus is using the NACK mechanism also to indicate the reception of an invalid command or
data. Since such a condition may occur on the last byte of the transfer, it is required that SMBus devices
have the ability to generate the not acknowledge after the transfer of each byte and before the completion
of the transaction. This is important because SMBus does not provide any other resend signaling. This
difference in the use of the NACK signaling has implications on the specific implementation of the SMBus
port, especially in devices that handle critical system data such as the SMBus host and the SBS
components.
NOTE
In the last byte of master receive slave transmit mode, the master should
send NACK to bus so FACK should be switched off before the last byte
transmit.
16.5
Resets
The IIC is disabled after reset. The IIC cannot cause an MCU reset.
16.6
Interrupts
The IIC generates a single interrupt.
An interrupt from the IIC is generated when any of the events in Table 16-14 occur, provided the IICIE bit
is set. The interrupt is driven by bit IICIF (of the IIC status register) and masked with bit IICIE (of the IIC
control register). The IICIF bit must be cleared by software by writing a 1 to it in the interrupt routine. The
user can determine the interrupt type by reading the status register. For SMBus timeouts interrupt, the
interrupt is driven by SLTF and masked with bit IICIE. The SLTF bit must be cleared by software by
MCF51MM256 Series Devices Reference Manual, Rev. 3
16-24
Freescale Semiconductor
Inter-Integrated Circuit (S08IICV3)
writing a 1 to it in the interrupt routine. The user can determine the interrupt type by reading the status
register.
NOTE
In Master receive mode, the FACK should be set zero before the last byte
transfer.
Table 16-14. Interrupt Summary
16.6.1
Interrupt Source
Status
Flag
Local Enable
Complete 1-byte transfer
TCF
IICIF
IICIE
Match of received calling address
IAAS
IICIF
IICIE
Arbitration Lost
ARBL
IICIF
IICIE
SMBus Timeout Interrupt Flag
SLTF
IICIF
IICIE
Byte Transfer Interrupt
The TCF (transfer complete flag) bit is set at the falling edge of the 9th clock to indicate the completion
of byte transfer.
16.6.2
Address Detect Interrupt
When the calling address matches the programmed slave address (IIC address register) or when the
GCAEN bit is set and a general call is received, the IAAS bit in the status register is set. The CPU is
interrupted, provided the IICIE is set. The CPU must check the SRW bit and set its Tx mode accordingly.
16.6.3
Arbitration Lost Interrupt
The IIC is a true multi-master bus that allows more than one master to be connected on it. If two or more
masters try to control the bus at the same time, the relative priority of the contending masters is determined
by a data arbitration procedure. The IIC module asserts this interrupt when it loses the data arbitration
process and the ARBL bit in the status register is set.
Arbitration is lost in the following circumstances:
• SDA sampled as a low when the master drives a high during an address or data transmit cycle.
• SDA sampled as a low when the master drives a high during the acknowledge bit of a data receive
cycle.
• A START cycle is attempted when the bus is busy.
• A repeated START cycle is requested in slave mode.
• A STOP condition is detected when the master did not request it.
This bit must be cleared by software by writing a 1 to it.
16.6.4
Timeouts Interrupt in SMbus
When IICIE is set, the IIC asserts a timeout interrupt output SLTF upon detection of any of the mentioned
timeout conditions, with one exception. The HIGH TIMEOUT mechanism shall not be used to influence
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
16-25
Inter-Integrated Circuit (S08IICV3)
the timeout interrupt output, because the HIGH TIMEOUT indicates an idle condition on the bus.And
SLTF will rise when it matches the HIGH TIMEOUT and fall automatically to just indicate the bus status.
16.6.5
Programmable input glitch filter
An IIC glitch filter has been added outside the IIC legacy modules, but within the IIC package. This filter
can absorb glitches on the IIC clock and data lines for I2C module. The width of the glitch to absorb can
be specified in terms of number of half bus clock cycles. A single glitch filter control register is provided
as IICFLT. Effectively, any down-up-down or up-down-up transition on the data line that occurs within the
number of clock cycles programmed here is ignored by the IIC.the programmer only needs to specify the
size of glitch (in terms of bus clock cycles) for the filter to absorb and not pass.
MCF51MM256 Series Devices Reference Manual, Rev. 3
16-26
Freescale Semiconductor
Inter-Integrated Circuit (S08IICV3)
16.7
1.
2.
3.
4.
5.
1.
2.
3.
4.
5.
6.
7.
Initialization/Application Information
Module Initialization (Slave)
Write: IICC2
— to enable or disable general call
— to select 10-bit or 7-bit addressing mode
Write: IICA1
— to set the slave address
Write: IICC1
— to enable IIC and interrupts
Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data
Initialize RAM variables used to achieve the routine shown in Figure 16-12
Module Initialization (Master)
Write: IICF
— to set the IIC baud rate (example provided in this chapter)
Write: IICC1
— to enable IIC and interrupts
Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data
Initialize RAM variables used to achieve the routine shown in Figure 16-12
Write: IICC1
— to enable TX
Write: IICC1
— to enable MST (master mode)
Write: IICD
— with the address of the target slave. (The LSB of this byte will determine whether the communication is
master receive or transmit.)
Module Use
The routine shown in Figure 16-12 can handle both master and slave IIC operations. For slave operation, an
incoming IIC message that contains the proper address will begin IIC communication. For master operation,
communication must be initiated by writing to the IICD register.
Register Model
AD[7:1]
IICA1
0
Address to which the module will respond when addressed as a slave (in slave mode)
MULT
IICF
ICR
Baud rate = BUSCLK / (2 x MULT x (SCL DIVIDER))
IICC1
IICEN
IICIE
MST
TX
TXAK
RSTA
0
0
BUSY
ARBL
0
SRW
IICIF
RXAK
AD9
AD8
Module configuration
IICS
TCF
IAAS
Module status flags
DATA
IICD
Data register; Write to transmit IIC data read to read IIC data
IICC2 GCAEN ADEXT
0
0
0
AD10
0
0
FLT3
FLT2
Address configuration
IICFLT
0
0
FLT1
FLT0
IIC Programmable Input Glitch Filter
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
16-27
Inter-Integrated Circuit (S08IICV3)
Clear
IICIF
Master
Mode
?
Y
TX
N
Arbitration
Lost
?
Y
RX
Tx/Rx
?
N
Last Byte
Transmitted
?
N
Clear ARBL
Y
RXAK=0
?
Last
Byte to Be Read
?
N
N
N
Y
Y
IAAS=1
?
Y
IAAS=1
?
Y
Address Transfer
See Note 1
Y
End of
Addr Cycle
(Master Rx)
?
Y
Y
(Read)
2nd Last
Byte to Be Read
?
N
SRW=1
?
Write Next
Byte to IICD
Set TXACK =1
Generate
Stop Signal
(MST = 0)
RX
TX/RX
?
TX
N (Write)
N
N
Data Transfer
See Note 2
Y
Set TX
Mode
ACK from
Receiver
?
N
Switch to
Rx Mode
Dummy Read
from IICD
Generate
Stop Signal
(MST = 0)
Read Data
from IICD
and Store
Read Data
from IICD
and Store
Tx Next
Byte
Write Data
to IICD
Set RX
Mode
Switch to
Rx Mode
Dummy Read
from IICD
Dummy Read
from IICD
RTI
NOTES:
1. If general call is enabled, a check must be done to determine whether the received address was a general call address (0x00). If the received address was a
general call address, then the general call must be handled by user software.
2. When 10-bit addressing is used to address a slave, the slave will see an interrupt following the first byte of the extended address. User software must ensure that
for this interrupt, the contents of IICD are ignored and not treated as a valid data transfer.
Figure 16-12. Typical IIC Interrupt Routine
MCF51MM256 Series Devices Reference Manual, Rev. 3
16-28
Freescale Semiconductor
Inter-Integrated Circuit (S08IICV3)
Y
N
SLTF?
Y
N
FACK?
Clear IICIF
Flow Chart1
Master
Mode
?
Y
TX
N
Y
RX
Tx/Rx
?
See Note 2
Arbitration
Lost
?
N
Last Byte
Transmitted
?
N
Clear ARBL
Y
RXAK=0
?
Last
Byte to Be Read
?
N
N
N
Y
Y
IAAS=1
?
Y
IAAS=1
?
Y
N
Address Transfer
See Note 1
Y
End of
Addr Cycle
(Master Rx)
?
Y
Y
(Read)
2nd Last
Byte to Be Read
?
N
SRW=1
?
Clear IICIF
Generate
Stop Signal
(MST = 0)
Y
ACK from
Receiver
?
Set TX
Mode
N
Write Next
Byte to IICD
Clear IICIF
Generate
Stop Signal
(MST = 0)
Set TXAK to
Proper Value
Clear IICIF
Write Data
to IICD
Read Data
from IICD
and Store
Tx Next
Byte
Switch to
Rx Mode
Dummy Read
from IICD
Clear IICIF
Set TXAK
To proper
Value
See Note 3
RX
TX
N (Write)
N
Set TXACK =1
Set Fack = 0
TX/RX
?
Read Data
from IICD
and Store
Set RX
Mode
Switch to
Rx Mode
Dummy Read
from IICD
Dummy Read
from IICD
RTI
NOTES:
1. If general call siicaen is enabled, a check must be done to determine whether the received address was a general call address (0x00) or SMbus device default
address. If the received address was one of them, then it must be handled by user software.
2. Flow chart1 means figure 1-12 Typical IIC Interrupt Routine.
3. Delay about 1-2bit scl cycle waiting data register updated then clear IICIF
Figure 16-14. Typical IIC SMBus Interrupt Routine
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
16-29
Inter-Integrated Circuit (S08IICV3)
16.8
SMBALERT#
Another optional signal is an interrupt line for devices that want to trade their ability to master for a pin.
SMBALERT# is a wired-AND signal just as the SMBCLK and SMBDAT signals are. SMBALERT# is
used in conjunction with the SMBus General Call Address. Messages invoked with the SMBus are 2 bytes
long. (Now there is no ALERT# port in current block)
A slave-only device can signal the host through SMBALERT# that it wants to talk. The host processes the
interrupt and simultaneously accesses all SMBALERT# devices through the Alert Response Address
(ARA). Only the device(s) which pulled SMBALERT# low will acknowledge the Alert Response
Address.
The host performs a modified Receive Byte operation. The 7 bit device address provided by the slave
transmit device is placed in the 7 most significant bits of the byte. The eighth bit can be a zero or one.
If more than one device pulls SMBALERT# low, the highest priority (lowest address) device will win
communication rights via standard arbitration during the slave address transfer.
After acknowledging the slave address the device must disengage its SMBALERT# pulldown. If the host
still sees SMBALERT# low when the message transfer is complete, it knows to read the ARA again.
A host which does not implement the SMBALERT# signal may periodically access the ARA.
s
Alert Response
Rd A
Address
Device Address
A
P
Table 0-1. A 7-bit-Addressable Device Responds to an ARA
NOTE: The user should put Device Address on bus by software after response to the Alert response
address in current block.
MCF51MM256 Series Devices Reference Manual, Rev. 3
16-30
Freescale Semiconductor
Chapter 17
Multipurpose Clock Generator (S08MCGV3)
17.1
Introduction
The multipurpose clock generator (MCG) module provides several clock source choices for this device.
The module contains a frequency-locked loop (FLL) and a phase-locked loop (PLL) that are controllable
by an internal or an external reference clock. The module can select either of the FLL or PLL clocks or
either of the internal or external reference clocks as a source for the MCU system clock. The selected clock
source is passed through a reduced bus divider that allows a lower output clock frequency to be derived.
For USB operation on this series of devices, the MCG must be configured for PLL engaged external (PEE)
mode to achieve a MCGOUT frequency of 48 MHz.
These devices are unique in that they support a Time of Day module which includes a dedicated oscillator.
The TOD oscillator can also be used as the reference clock into the MCG.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
17-1
Multipurpose Clock Generator (S08MCGV3)
Figure 17-1. Block Diagram with MCG Module Highlighted
MCF51MM256 Series Devices Reference Manual, Rev. 3
17-2
Freescale Semiconductor
Multipurpose Clock Generator (S08MCGV3)
17.1.1
Clock Check & Select Function
The “Clock Check & Select” feature of the following figures is a very simple block used to check the
oscillator clocks for activity and control the mux which selects the external clock for the MCG. This
function is implemented external to the MCG module itself, and is specific to this device.
The four registers that comprise this operation are described in the following table.
Table 17-1. Clock Check & Select Registers
Clock Check & Select Control Register
CCSTMR1
8-bit counter incremented by XOSC1 timebase
CCSTMR2
8-bit counter incremented by XOSC2 timebase
CCSTMRIR
8-bit counter incremented via IR clock timebase
XTAL2
EXTAL1
CCSCTRL
XTAL1
Function
EXTAL2
Register
TOD
Clock Check
& Select
XOSC2
XOSC1
OSCOUT2
MCGIRCLK
OSCOUT1
oscillator control
MCG
oscillator control
Figure 17-2. A subset of Figure 1-3
17.1.2
Clock Check & Select Control (CCSCTRL)
7
6
RANGE1
HGO1
0
0
5
4
3
2
1
0
EREFS1
EN
TEST
SEL
1
0
0
0
R
ERCLKEN1 OSCINIT1
W
Reset:
0
0
Figure 17-3. Clock Check & Select Control Register (CCSCTRL)
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
17-3
Multipurpose Clock Generator (S08MCGV3)
Table 17-2. CCS Control Register Field Descriptions
Field
Description
7
RANGE1
Frequency Range Select — Selects the frequency range for the external oscillator 1 (XOSC1).
0 Low frequency range selected for the external oscillator.
1 High frequency range selected for the external oscillator.
6
HGO1
High-Gain Oscillator Select — The HGO bit controls the external oscillator 1 (XOSC1) mode of operation.
0 Configures external oscillator for low-power operation.
1 Configures external oscillator for high-gain operation.
5
External Clock Enable — The ERCLKEN1 bit enables the external reference clock provided by XOSC1 for use
ERCLKEN1 as MCGERCLK.
0 MCGERCLK inactive.
1 MCGERCLK active.
4
OSCINIT1
Oscillator Initialization — The OSCINIT1 bit indicates the external clock source has finished its initialization
cycles and is stabilized.
3
EREFS1
External Reference Select — The EREFS1 bit selects the source for the external reference clock of the MCG
when using XOSC1.
0 External Clock Source requested.
1 Oscillator requested.
2
EN
Enable bit — The EN bit disables inputs to the clock check counter to save power.
0 The OSCOUT1, OSCOUT2, and MCGIRCLK inputs to the clock check counters are disabled for power saving.
1 The clock inputs are enabled.
1
TEST
Test bit — Writing a “1” to this bit clears CCSTMR1, CCSTMR2 and CCSTMRIR. The three counters will then
begin incrementing until any one of the three hits 0xFF, at which point the test completes, and TEST is cleared.
0
SEL
Select bit — The SEL bit selects the external clock input to the MCG. This bit should only be changed when the
MCG is NOT utilizing the external clock input.
0 XOSC2 is selected as the external clock input to the MCG and XOSC1 is selected to the TOD (default).
1 XOSC1 is selected as the external clock input to the MCG and TOD.
17.1.3
CCS XOSC1 Timer Register (CCSTMR1)
7
6
5
4
R
3
2
1
0
0
0
0
0
CNT1
W
Reset:
0
0
0
0
Figure 17-4. CCS XOSC1 Timer Register (CCSTMR1)
Table 17-3. CCSTMR1 Register Field Descriptions
Field
7-0
CNT1
Description
CNT1 — This register is one of three used to compare XOSC1, XOSC2 and internal relaxation oscillator
frequencies. It is initialized to zero upon a write of “1” to CCSCTRL[TEST]. It contains a valid value once
CCSCTRL[TEST] resets itself to “0”. By comparing the values of the three registers, application code can
determine the crude health of the various clock sources.
MCF51MM256 Series Devices Reference Manual, Rev. 3
17-4
Freescale Semiconductor
Multipurpose Clock Generator (S08MCGV3)
17.1.4
CCS XOSC2 Timer Register (CCSTMR2)
7
6
5
4
R
3
2
1
0
0
0
0
0
CNT2
W
Reset:
0
0
0
0
Figure 17-5. CCS XOSC2 Timer Register (CCSTMR2)
Table 17-4. CCSTMR2 Register Field Descriptions
Field
Description
7-0
CNT2
CNT2 —This register is one of three used to compare XOSC1, XOSC2 and internal relaxation oscillator
frequencies. It is initialized to zero upon a write of “1” to CCSCTRL[TEST]. It contains a valid value once
CCSCTRL[TEST] resets itself to “0”. By comparing the values of the three registers, application code can
determine the crude health of the various clock sources.
17.1.5
CCS Internal Reference Clock Timer Register (CCSTMRIR)
7
6
5
4
R
3
2
1
0
0
0
0
0
CNTIR
W
Reset:
0
0
0
0
Figure 17-6. CCS Internal Reference Clock Timer Register (CCSTMRIR)
Table 17-5. CCSTMRIR Register Field Descriptions
Field
7-0
CNTIR
17.1.6
Description
CNTIR —This register is one of three used to compare XOSC1, XOSC2 and internal relaxation oscillator
frequencies. It is initialized to zero upon a write of “1” to CCSCTRL[TEST]. It contains a valid value once
CCSCTRL[TEST] resets itself to “0”. By comparing the values of the three registers, application code can
determine the crude health of the various clock sources.
Operation
The clock check and select (CCS) feature is a basic clock monitor of the internal reference clock and two
XOSC clocks using the following 8-bit counters:
• CCSTMR1
• CCSTMR2
• CCSTMRIR
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
17-5
Multipurpose Clock Generator (S08MCGV3)
The major purpose of this feature is to monitor the stability and availability of the XOSC clocks and
provide a rough frequency measurement of the three clock sources. The registers are 8-bit so the maximum
count is 255.
Basically, whichever counter reaches 255 first sends a stop signal to the other two counters. It takes
approximately 3 clock cycles for the stop signal to sync with the other two counters. Software can then
compare the three registers to obtain a crude (3/256 is ~1.2%) measurement of how well the three
frequencies correlate.
NOTE
The clock check feature should only be used to check the stability and
availability of the XOSC clocks. CCS is not intended to be used as an
accurate frequency measurement of the clocks.
17.1.7
Features
Key features of the MCG module are:
• Frequency-locked loop (FLL)
— Internal or external reference clock can be used to control the FLL
• Phase-locked loop (PLL)
— Voltage-controlled oscillator (VCO)
— Modulo VCO frequency divider
— Phase/Frequency detector
— Integrated loop filter
— Lock detector with interrupt capability
• Internal reference clock
— Nine trim bits for accuracy
— Can be selected as the clock source for the MCU
• External reference clock
— Control for a separate crystal oscillator
— Clock monitor with reset capability
— Can be selected as the clock source for the MCU
• Reference divider is provided
• Clock source selected can be divided down by 1, 2, 4, or 8
• BDC clock (MCGLCLK) is provided as a constant divide-by-2 of the DCO output whether in an
FLL or PLL mode.Three selectable digitally controlled oscillators (DCOs) optimized for different
frequency ranges.
• Option to maximize DCO output frequency for a 32,768 Hz external reference clock source.
• The PLL can be used to drive MCGPLLSCLK even when MCGOUT is driven from one of the
reference clocks (PBE mode).
MCF51MM256 Series Devices Reference Manual, Rev. 3
17-6
Freescale Semiconductor
Multipurpose Clock Generator (S08MCGV3)
External Reference Clock
Crystal Oscillator
(XOSC) (required)
CME
EREFS
ERCLKEN
MCGERCLK
EREFSTEN
IRCLKEN
MCGIRCLK
HGO
Clock
Monitor
CLKS
BDIV
RANGE
/ 2n
OSCINIT
LOC
DIV32
LP
MCGOUT
n=0-3
DMX32
FLL
DCOH
Filter DCOM
DCOL
MCGPLLSCLK
DCOOUT
Lock
Detector
RDIV
PLLS
LOLS LOCK
DRS
/ 2n
/ 25
/2
n=0-7
MCGFFCLK
MCGFFCLKVALID
MCGLCLK
LP
IREFS
IREFSTEN
Internal
Reference
Clock
TRIM
Phase
Detector
Charge
Pump
VDIV
Internal
Filter
/(4,8,12,...,48)
FTRIM
VCO
VCOOUT
PLL
DRST IREFST CLKST OSCINIT
Multipurpose Clock Generator (MCG)
Figure 17-7. Multipurpose Clock Generator (MCG) Block Diagram
NOTE
The MCG requires the attachment of a crystal oscillator (XOSC) module,
which provides an external reference clock.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
17-7
Multipurpose Clock Generator (S08MCGV3)
17.1.8
Modes of Operation
There are several modes of operation for the MCG. For details, see Section 17.4.1, “MCG Modes of
Operation.”
17.2
External Signal Description
There are no MCG signals that connect off chip.
17.3
Register Definition
17.3.1
MCG Control Register 1 (MCGC1)
7
6
5
4
3
2
1
0
IREFS
IRCLKEN
IREFSTEN
1
0
0
R
CLKS
RDIV
W
Reset:
0
0
0
0
0
Figure 17-8. MCG Control Register 1 (MCGC1)
Table 17-6. MCG Control Register 1 Field Descriptions
Field
Description
7:6
CLKS
Clock Source Select — Selects the system clock source.
00 Encoding 0 — Output of FLL or PLL is selected.
01 Encoding 1 — Internal reference clock is selected.
10 Encoding 2 — External reference clock is selected.
11 Encoding 3 — Reserved, defaults to 00.
5:3
RDIV
External Reference Divider — Selects the amount to divide down the external reference clock. If the FLL is
selected, the resulting frequency must be in the range 31.25 kHz to 39.0625 kHz. If the PLL is selected, the
resulting frequency must be in the range 1 MHz to 2 MHz. See Table 17-7 and Table 17-8 for the divide-by factors.
2
IREFS
Internal Reference Select — Selects the reference clock source.
1 Internal reference clock selected
0 External reference clock selected
1
IRCLKEN
0
IREFSTEN
Internal Reference Clock Enable — Enables the internal reference clock for use as MCGIRCLK.
1 MCGIRCLK active
0 MCGIRCLK inactive
Internal Reference Stop Enable — Controls whether or not the internal reference clock remains enabled when
the MCG enters stop mode.
1 Internal reference clock stays enabled in stop if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI mode before
entering stop
0 Internal reference clock is disabled in stop
MCF51MM256 Series Devices Reference Manual, Rev. 3
17-8
Freescale Semiconductor
Multipurpose Clock Generator (S08MCGV3)
Table 17-7. FLL External Reference Divide Factor
Divide Factor
RDIV
RANGE:DIV32
0:X
RANGE:DIV32
1:0
RANGE:DIV32
1:1
0
1
1
32
1
2
2
64
2
4
4
128
3
8
8
256
4
16
16
512
5
32
32
1024
6
64
64
Reserved
7
128
128
Reserved
Table 17-8. PLL External Reference Divide Factor
RDIV
Divide Factor
0
1
1
2
2
4
3
8
4
16
5
32
6
64
7
128
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
17-9
Multipurpose Clock Generator (S08MCGV3)
17.3.2
MCG Control Register 2 (MCGC2)
7
6
5
4
3
2
RANGE
HGO
LP
EREFS
0
0
0
0
1
0
R
BDIV
ERCLKEN EREFSTEN
W
Reset:
0
1
0
0
Figure 17-9. MCG Control Register 2 (MCGC2)
Table 17-9. MCG Control Register 2 Field Descriptions
Field
Description
7:6
BDIV
Bus Frequency Divider — Selects the amount to divide down the clock source selected by the CLKS bits in the
MCGC1 register. This controls the bus frequency.
00 Encoding 0 — Divides selected clock by 1
01 Encoding 1 — Divides selected clock by 2 (reset default)
10 Encoding 2 — Divides selected clock by 4
11 Encoding 3 — Divides selected clock by 8
5
RANGE
4
HGO
3
LP
2
EREFS
1
ERCLKEN
Frequency Range Select — Selects the frequency range for the crystal oscillator or external clock source.
1 High frequency range selected for the crystal oscillator of 1 MHz to 16 MHz (1 MHz to 40 MHz for external
clock source)
0 Low frequency range selected for the crystal oscillator of 32 kHz to 100 kHz (32 kHz to 1 MHz for external
clock source)
High Gain Oscillator Select — Controls the crystal oscillator mode of operation.
1 Configure crystal oscillator for high gain operation
0 Configure crystal oscillator for low power operation
Low Power Select — Controls whether the FLL (or PLL) is disabled in bypassed modes.
1 FLL (or PLL) is disabled in bypass modes (lower power).
0 FLL (or PLL) is not disabled in bypass modes.
External Reference Select — Selects the source for the external reference clock.
1 Oscillator requested
0 External Clock Source requested
External Reference Enable — Enables the external reference clock for use as MCGERCLK.
1 MCGERCLK active
0 MCGERCLK inactive
0
External Reference Stop Enable — Controls whether or not the external reference clock remains enabled when
EREFSTEN the MCG enters stop mode.
1 External reference clock stays enabled in stop if ERCLKEN is set or if MCG is in FEE, FBE, PEE, PBE, or
BLPE mode before entering stop
0 External reference clock is disabled in stop
MCF51MM256 Series Devices Reference Manual, Rev. 3
17-10
Freescale Semiconductor
Multipurpose Clock Generator (S08MCGV3)
17.3.3
MCG Trim Register (MCGTRM)
7
R
6
5
4
3
2
1
0
TRIM1
W
Figure 17-10. MCG Trim Register (MCGTRM)
1
A value for TRIM is loaded during reset from a factory programmed location when not in any BDM mode. If in a BDM
mode, a default value of 0x80 is loaded.
Table 17-10. MCG Trim Register Field Descriptions
Field
Description
7:0
TRIM
MCG Trim Setting — Controls the internal reference clock frequency by controlling the internal reference clock
period. The TRIM bits are binary weighted (i.e., bit 1 will adjust twice as much as bit 0). Increasing the binary
value in TRIM will increase the period, and decreasing the value will decrease the period.
An additional fine trim bit is available in MCGSC as the FTRIM bit.
If a TRIM[7:0] value stored in nonvolatile memory is to be used, it’s the user’s responsibility to copy that value
from the nonvolatile memory location to this register.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
17-11
Multipurpose Clock Generator (S08MCGV3)
17.3.4
MCG Status and Control Register (MCGSC)
R
7
6
5
4
3
LOLS
LOCK
PLLST
IREFST
0
0
0
1
2
CLKST
1
OSCINIT
0
FTRIM1
W
Reset:
0
0
0
Figure 17-11. MCG Status and Control Register (MCGSC)
1
A value for FTRIM is loaded during reset from a factory programmed location when not in any BDM mode. If in a BDM
mode, a default value of 0x0 is loaded.
Table 17-11. MCG Status and Control Register Field Description
Field
Description
7
LOLS
Loss of Lock Status — This bit is a sticky indication of lock status for the FLL or PLL. LOLS is set when lock
detection is enabled and after acquiring lock, the FLL or PLL output frequency has fallen outside the lock exit
frequency tolerance, Dunl. LOLIE determines whether an interrupt request is made when set. LOLS is cleared by
reset or by writing a logic 1 to LOLS when LOLS is set. Writing a logic 0 to LOLS has no effect.
0 FLL or PLL has not lost lock since LOLS was last cleared.
1 FLL or PLL has lost lock since LOLS was last cleared.
6
LOCK
Lock Status — Indicates whether the FLL or PLL has acquired lock. Lock detection is disabled when both the
FLL and PLL are disabled. If the lock status bit is set, changing the value of DMX32, DRS[1:0] and IREFS bits in
FBE, FBI, FEE and FEI modes; DIV32 bit in FBE and FEE modes; TRIM[7:0] bits in FBI and FEI modes;
RDIV[2:0] bits in FBE, FEE, PBE and PEE modes; VDIV[3:0] bits in PBE and PEE modes; and PLLS bit, causes
the lock status bit to clear and stay clear until the FLL or PLL has reacquired lock. Entry into BLPI, BLPE or stop
mode also causes the lock status bit to clear and stay cleared until the exit of these modes and the FLL or PLL
has reacquired lock.
0 FLL or PLL is currently unlocked.
1 FLL or PLL is currently locked.
5
PLLST
PLL Select Status — The PLLST bit indicates the current source for the PLLS clock. The PLLST bit does not
update immediately after a write to the PLLS bit due to internal synchronization between clock domains.
0 Source of PLLS clock is FLL clock.
1 Source of PLLS clock is PLL clock.
4
IREFST
Internal Reference Status — The IREFST bit indicates the current source for the reference clock. The IREFST
bit does not update immediately after a write to the IREFS bit due to internal synchronization between clock
domains.
0 Source of reference clock is external reference clock (oscillator or external clock source as determined by the
EREFS bit in the MCGC2 register).
1 Source of reference clock is internal reference clock.
3:2
CLKST
Clock Mode Status — The CLKST bits indicate the current clock mode. The CLKST bits do not update
immediately after a write to the CLKS bits due to internal synchronization between clock domains.
00 Encoding 0 — Output of FLL is selected.
01 Encoding 1 — Internal reference clock is selected.
10 Encoding 2 — External reference clock is selected.
11 Encoding 3 — Output of PLL is selected.
MCF51MM256 Series Devices Reference Manual, Rev. 3
17-12
Freescale Semiconductor
Multipurpose Clock Generator (S08MCGV3)
Table 17-11. MCG Status and Control Register Field Description (Continued)
Field
Description
1
OSCINIT
OSC Initialization — If the external reference clock is selected by ERCLKEN or by the MCG being in FEE, FBE,
PEE, PBE, or BLPE mode, and if EREFS is set, then this bit is set after the initialization cycles of the crystal
oscillator clock have completed. This bit is only cleared when either EREFS is cleared or when the MCG is in
either FEI, FBI, or BLPI mode and ERCLKEN is cleared.
0
FTRIM
MCG Fine Trim — Controls the smallest adjustment of the internal reference clock frequency. Setting FTRIM will
increase the period and clearing FTRIM will decrease the period by the smallest amount possible.
If an FTRIM value stored in nonvolatile memory is to be used, it’s the user’s responsibility to copy that value from
the nonvolatile memory location to this register’s FTRIM bit.
17.3.5
MCG Control Register 3 (MCGC3)
7
6
5
4
3
LOLIE
PLLS
CME
DIV32
0
0
0
0
2
1
0
0
1
R
VDIV
W
Reset:
0
0
Figure 17-12. MCG PLL Register (MCGPLL)
Table 17-12. MCG PLL Register Field Descriptions
Field
Description
7
LOLIE
Loss of Lock Interrupt Enable — Determines if an interrupt request is made following a loss of lock indication.
The LOLIE bit only has an effect when LOLS is set.
0 No request on loss of lock.
1 Generate an interrupt request on loss of lock.
6
PLLS
PLL Select — Controls whether the PLL or FLL is selected. If the PLLS bit is clear, the PLL is disabled in all
modes. If the PLLS is set, the FLL is disabled in all modes.
1 PLL is selected
0 FLL is selected
5
CME
Clock Monitor Enable — Determines if a reset request is made following a loss of external clock indication. The
CME bit should only be set to a logic 1 when either the MCG is in an operational mode that uses the external
clock (FEE, FBE, PEE, PBE, or BLPE) or the external reference is enabled (ERCLKEN=1 in the MCGC2
register). Whenever the CME bit is set to a logic 1, the value of the RANGE bit in the MCGC2 register should not
be changed. If the external reference clock is set to be disabled when the MCG enters STOP mode
(EREFSTEN=0), then the CME bit should be set to a logic 0 before the MCG enters STOP mode. Otherwise a
reset request may occur while in STOP mode.
0 Clock monitor is disabled.
1 Generate a reset request on loss of external clock.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
17-13
Multipurpose Clock Generator (S08MCGV3)
Table 17-12. MCG PLL Register Field Descriptions (Continued)
Field
Description
4
DIV32
Divide-by-32 Enable — Controls an additional divide-by-32 factor to the external reference clock for the FLL
when RANGE bit is set. When the RANGE bit is 0, this bit has no effect. Writes to this bit are ignored if PLLS bit
is set.
0 Divide-by-32 is disabled.
1 Divide-by-32 is enabled when RANGE=1.
3:0
VDIV
VCO Divider — Selects the amount to divide down the VCO output of PLL. The VDIV bits establish the
multiplication factor (M) applied to the reference clock frequency.
0000 Encoding 0 — Reserved.
0001 Encoding 1 — Multiply by 4.
0010 Encoding 2 — Multiply by 8.
0011 Encoding 3 — Multiply by 12.
0100 Encoding 4 — Multiply by 16.
0101 Encoding 5 — Multiply by 20.
0110 Encoding 6 — Multiply by 24.
0111 Encoding 7 — Multiply by 28.
1000 Encoding 8 — Multiply by 32.
1001 Encoding 9 — Multiply by 36.
1010 Encoding 10 — Multiply by 40.
1011 Encoding 11 — Multiply by 44.
1100 Encoding 12 — Multiply by 48.
1101 Encoding 13 — Reserved (default to M=48).
111x Encoding 14-15 — Reserved (default to M=48).
17.3.6
MCG Control Register 4 (MCGC4)
R
7
6
0
0
5
4
3
2
0
0
0
1
0
DRST
DMX32
W
Reset:
DRS
0
0
0
0
0
0
0
0
Figure 17-13. MCG Control Register 4 (MCGC4)
MCF51MM256 Series Devices Reference Manual, Rev. 3
17-14
Freescale Semiconductor
Multipurpose Clock Generator (S08MCGV3)
Table 17-13. MCG Test and Control Register Field Descriptions
Field
7:6
5
DMX32
4:2
1:0
DRST
DRS
Description
Reserved for test, user code should not write 1’s to these bits.
DCO Maximum frequency with 32.768 kHz reference — The DMX32 bit controls whether or not the DCO
frequency range is narrowed to its maximum frequency with a 32.768 kHz reference. See Table 17-14.
0 DCO has default range of 25%.
1 DCO is fined tuned for maximum frequency with 32.768 kHz reference.
Reserved for test, user code should not write 1’s to these bits.
DCO Range Status — The DRST read bits indicate the current frequency range for the FLL output, DCOOUT.
See Table 17-14. The DRST bits do not update immediately after a write to the DRS field due to internal
synchronization between clock domains. The DRST bits are not valid in BLPI, BLPE, PBE or PEE mode and it
reads zero regardless of the DCO range selected by the DRS bits.
DCO Range Select — The DRS bits select the frequency range for the FLL output, DCOOUT. Writes to the DRS
bits while either the LP or PLLS bit is set are ignored.
00Low range.
01Mid range.
10High range.
11Reserved
Table 17-14. DCO frequency range1
DRS
DMX32
00
0
31.25 - 39.0625 kHz
512
16 - 20 MHz
1
32.768 kHz
608
19.92 MHz
01
0
31.25 - 39.0625 kHz
1024
32 - 40 MHz
1
32.768 kHz
1216
39.85 MHz
0
31.25 - 39.0625 kHz
1536
48-60 MHz
1
32.768 kHz
1824
59.77 MHz
10
Reference range
11
1
17.3.7
FLL factor
DCO range
Reserved
The resulting bus clock frequency should not exceed the maximum specified bus
clock frequency of the device.
MCG Test Register (MCGT)
Table 17-15. MCG Test Register Field Descriptions
Field
7:6
5
4:1
0
Description
Reserved for test, user code should not write 1’s to these bits.
Reserved, user code should not write 1’s to these bits
Reserved for test, user code should not write 1’s to these bits.
Reserved, user code should not write 1’s to these bits
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
17-15
Multipurpose Clock Generator (S08MCGV3)
17.4
Functional Description
17.4.1
MCG Modes of Operation
The MCG operates in one of the modes described in Table 17-16.
NOTE
The MCG restricts transitions between modes. For the permitted transitions,
see Section 17.4.2, “MCG Mode State Diagram.”
Table 17-16. MCG Modes of Operation
Mode
Related field values
Description
FLL Engaged
Internal (FEI)
• MCGC1[IREFS] = 1
• MCGC1[CLKS] = 00
• MCGC3[PLLS] = 0
Default. MCGOUT is derived from the FLL clock, which is controlled by
the internal reference clock. The FLL clock frequency locks to a
multiplication factor, as selected by the DRS[1:0] and DMX32 bits, times
the internal reference frequency. MCGLCLK is derived from the FLL, and
the PLL is disabled in a low-power state.
FLL Engaged
External (FEE)
• MCGC1[IREFS] = 0
• MCGC1[CLKS] = 00
• MCGC1[RDIV] is programmed
to divide the reference clock to
be within the range of 31.2500
to 39.0625 kHz.
• MCGC3[PLLS] = 0
MCGOUT is derived from the FLL clock, which is controlled by the
external reference clock. The external reference clock that is enabled
can be produced by an external crystal, ceramic resonator, or another
external clock source connected to the required crystal oscillator
(XOSC). The FLL clock frequency locks to a multiplication factor, as
selected by the DRS[1:0] and DMX32 bits, times the external reference
frequency, as specified by MCGC1[RDIV], MCGC2[RANGE], and
MCGC3[DIV32]. MCGLCLK is derived from the FLL, and the PLL is
disabled in a low-power state.
FLL Bypassed
Internal (FBI)
• MCGC1[IREFS] = 1
• MCGC1[CLKS] = 01
• MCGC2[LP] = 0 (or the BDM is
enabled)
• MCGC3[PLLS] = 0
MCGOUT is derived from the internal reference clock; the FLL is
operational, but its output clock is not used. This mode is useful to allow
the FLL to acquire its target frequency while the MCGOUT clock is driven
from the internal reference clock.
MCGOUT is derived from the internal reference clock. The FLL clock is
controlled by the internal reference clock, and the FLL clock frequency
locks to a multiplication factor, as selected by the DRS[1:0] and DMX32
bits, times the internal reference frequency. MCGLCLK is derived from
the FLL, and the PLL is disabled in a low-power state.
FLL Bypassed
External (FBE)
• MCGC1[IREFS] = 0
• MCGC1[CLKS] = 10
• MCGC1[RDIV] is programmed
to divide the reference clock to
be within the range of 31.2500
to 39.0625 kHz
• MCGC2[LP] = 0 (or the BDM is
enabled)
• MCGC3[PLLS] = 0
MCGOUT is derived from the external reference clock; the FLL is
operational, but its output clock is not used. This mode is useful to allow
the FLL to acquire its target frequency while MCGOUT is driven from the
external reference clock.
MCGOUT is derived from the external reference clock. The external
reference clock that is enabled can be produced by an external crystal,
ceramic resonator, or another external clock source connected to the
required crystal oscillator (XOSC).The FLL clock is controlled by the
external reference clock, and the FLL clock frequency locks to a
multiplication factor, as selected by the DRS[1:0] and DMX32 bits, times
the external reference frequency, as selected by MCGC1[RDIV],
MCGC2[RANGE], and MCGC3[DIV32]. MCGLCLK is derived from the
FLL, and the PLL is disabled in a low-power state.
MCF51MM256 Series Devices Reference Manual, Rev. 3
17-16
Freescale Semiconductor
Multipurpose Clock Generator (S08MCGV3)
Table 17-16. MCG Modes of Operation (Continued)
Mode
Related field values
Description
PLL Engaged
External (PEE)
• MCGC1[IREFS] = 0
• MCGC1[CLKS] = 00
• MCGC1[RDIV] is programmed
to divide the reference clock to
be within the range of 1 to
2 MHz.
• PLLS = 1
MCGOUT is derived from the PLL clock, which is controlled by the
external reference clock. The external reference clock that is enabled
can be produced by an external crystal, ceramic resonator, or another
external clock source connected to the required crystal oscillator
(XOSC). The PLL clock frequency locks to a multiplication factor, as
specified by MCGC3[VDIV], times the external reference frequency, as
specified by MCGC1[RDIV], MCGC2[RANGE], and MCGC3[DIV32]. If
the BDM is enabled, MCGLCLK is derived from the DCO (open-loop
mode) divided by two. If the BDM is not enabled, the FLL is disabled in a
low-power state.
In this mode, MCGT[DRST] is read as a 0 regardless of the value of
MCGT[DRS].
PLL Bypassed
External (PBE)
• MCGC1[IREFS] = 0
• MCGC1[CLKS] = 10
• MCGC1[RDIV] is programmed
to divide the reference clock to
be within the range of 1 to
2 MHz.
• MCGC2[LP] = 0
• MCGC3[PLLS] = 1
MCGOUT is derived from the external reference clock; the PLL is
operational, but its output clock is not used. This mode is useful to allow
the PLL to acquire its target frequency while MCGOUT is driven from the
external reference clock.
MCGOUT is derived from the external reference clock. The external
reference clock that is enabled can be produced by an external crystal,
ceramic resonator, or another external clock source connected to the
required crystal oscillator (XOSC). The PLL clock frequency locks to a
multiplication factor, as specified by MCGC3[VDIV], times the external
reference frequency, as specified by MCGC1[RDIV], MCGC2[RANGE],
and MCGC3[DIV32]. If the BDM is enabled, MCGLCLK is derived from
the DCO (open-loop mode) divided by two. If the BDM is not enabled, the
FLL is disabled in a low-power state.
In this mode, MCGT[DRST] is read as a 0 regardless of the value of
MCGT[DRS].
Bypassed Low
Power Internal
(BLPI)
• MCGC1[IREFS] = 1
• MCGC1[CLKS] =
01MCGC3[PLLS] = 0
• MCGC2[LP] = 1 (and the BDM
is disabled)
MCGOUT is derived from the internal reference clock.
The PLL and FLL are disabled, and MCGLCLK is not available for BDC
communications. If the BDM becomes enabled, the mode switches to
FLL bypassed internal (FBI) mode.
In this mode, MCGT[DRST] is read as a 0 regardless of the value of
MCGT[DRS].
Bypassed Low
Power External
(BLPE)
• MCGC1[IREFS] = 0
• MCGC1[CLKS] = 10
• MCGC2[LP] = 1 (and the BDM
is disabled)
MCGOUT is derived from the external reference clock. The external
reference clock that is enabled can be produced by an external crystal,
ceramic resonator, or another external clock source connected to the
required crystal oscillator (XOSC).
The PLL and FLL are disabled, and MCGLCLK is not available for BDC
communications. If the BDM becomes enabled, the mode switches to
one of the bypassed external modes as determined by the state of
MCGC3[PLLS].
In this mode, MCGT[DRST] is read as a 0 regardless of the value of
MCGT[DRS].
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
17-17
Multipurpose Clock Generator (S08MCGV3)
Table 17-16. MCG Modes of Operation (Continued)
Mode
Stop
17.4.2
Related field values
—
Description
Entered whenever the MCU enters a Stop state. The FLL and PLL are
disabled, and all MCG clock signals are static except in the following
cases:
MCGIRCLK is active in Stop mode when all the following conditions
become true:
• MCGC1[IRCLKEN] = 1
• MCGC1[IREFSTEN] = 1
MCGERCLK is active in Stop mode when all the following conditions
become true:
• MCGC2[ERCLKEN] = 1
• MCGC2[EREFSTEN] = 1
MCG Mode State Diagram
Figure 17-15 shows the MCG’s mode state diagram. The arrows indicate the permitted mode transitions.
FEI
FEE
FBI
FBE
BLPE
BLPI
PBE
PEE
Entered from any state when
the MCU enters Stop mode
Stop
Returns to the state that was active before
the MCU entered Stop mode, unless a
reset occurs while in Stop mode.
Figure 17-15. MCG Mode State Diagram
17.4.3
Mode Switching
The IREFS bit can be changed at anytime, but the actual switch to the newly selected clock is shown by
the IREFST bit. When switching between engaged internal and engaged external modes, the FLL or PLL
will begin locking again after the switch is completed.
MCF51MM256 Series Devices Reference Manual, Rev. 3
17-18
Freescale Semiconductor
Multipurpose Clock Generator (S08MCGV3)
The CLKS bits can also be changed at anytime, but the actual switch to the newly selected clock is shown
by the CLKST bits. If the newly selected clock is not available, the previous clock will remain selected.
The DRS bits can be changed at anytime except when LP bit is 1. If the DRS bits are changed while in
FLL engaged internal (FEI) or FLL engaged external (FEE), the bus clock remains at the previous DCO
range until the new DCO starts. When the new DCO starts the bus clock switches to it. After switching to
the new DCO the FLL remains unlocked for several reference cycles. Once the selected DCO startup time
is over, the FLL is locked. The completion of the switch is shown by the DRST bits.
For details see Figure 17-15.
17.4.4
Bus Frequency Divider
The BDIV bits can be changed at anytime and the actual switch to the new frequency will occur
immediately.
17.4.5
Low Power Bit Usage
The low power bit (LP) is provided to allow the FLL or PLL to be disabled and thus conserve power when
these systems are not being used. The DRS bit can not be written while LP bit is 1.However, in some
applications it may be desirable to enable the FLL or PLL and allow it to lock for maximum accuracy
before switching to an engaged mode. Do this by writing the LP bit to 0.
17.4.6
Internal Reference Clock
When IRCLKEN is set the internal reference clock signal will be presented as MCGIRCLK, which can be
used as an additional clock source. The MCGIRCLK frequency can be re-targeted by trimming the period
of the internal reference clock. This can be done by writing a new value to the TRIM bits in the MCGTRM
register. Writing a larger value will decrease the MCGIRCLK frequency, and writing a smaller value to
the MCGTRM register will increase the MCGIRCLK frequency. The TRIM bits will effect the MCGOUT
frequency if the MCG is in FLL engaged internal (FEI), FLL bypassed internal (FBI), or bypassed low
power internal (BLPI) mode. The TRIM and FTRIM value is initialized by POR but is not affected by
other resets.
Until MCGIRCLK is trimmed, programming low reference divider (RDIV) factors may result in
MCGOUT frequencies that exceed the maximum chip-level frequency and violate the chip-level clock
timing specifications (see the Device Overview chapter).
If IREFSTEN and IRCLKEN bits are both set, the internal reference clock will keep running during stop
mode in order to provide a fast recovery upon exiting stop.
17.4.7
External Reference Clock
The MCG module can support an external reference clock with frequencies between 31.25 kHz to 40 MHz
in all modes. When ERCLKEN is set, the external reference clock signal will be presented as
MCGERCLK, which can be used as an additional clock source. When IREFS = 1, the external reference
clock will not be used by the FLL or PLL and will only be used as MCGERCLK. In these modes, the
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
17-19
Multipurpose Clock Generator (S08MCGV3)
frequency can be equal to the maximum frequency the chip-level timing specifications will support (see
the Device Overview chapter).
If EREFSTEN and ERCLKEN bits are both set or the MCG is in FEE, FBE, PEE, PBE or BLPE mode,
the external reference clock will keep running during stop mode in order to provide a fast recovery upon
exiting stop.
If CME bit is written to 1, the clock monitor is enabled. If the external reference falls below a certain
frequency (floc_high or floc_low depending on the RANGE bit in the MCGC2), the MCU will reset. The
LOC bit in the System Reset Status (SRS) register will be set to indicate the error.
17.4.8
Fixed Frequency Clock
The MCG presents the divided reference clock as MCGFFCLK for use as an additional clock source. The
MCGFFCLK frequency must be no more than 1/4 of the MCGOUT frequency to be valid.
17.4.9
MCGPLLSCLK Operation
This clock is intended for use in systems which include a USB interface. It allows the MCG to supply a
48MHz clock to the USB. This same clock can be used to derive MCGOUT. Alternately, MCGOUT can
be derived from either internal or external reference clock. This allows the CPU to run at a lower frequency
(to conserve power) while the USB continues to monitor traffic.
Note that the FLL can not be used for generation of the system clocks while the PLL is supplying
MCGPLLSCLK.
MCF51MM256 Series Devices Reference Manual, Rev. 3
17-20
Freescale Semiconductor
Multipurpose Clock Generator (S08MCGV3)
17.5
Initialization / Application Information
This section describes how to initialize and configure the MCG module in application. The following
sections include examples on how to initialize the MCG and properly switch between the various available
modes.
17.5.1
MCG Module Initialization Sequence
The MCG comes out of reset configured for FEI mode with the BDIV set for divide-by-2. The internal
reference will stabilize in tirefst microseconds before the FLL can acquire lock. As soon as the internal
reference is stable, the FLL will acquire lock in tfll_acquire milliseconds.
NOTE
If the internal reference is not already trimmed, the BDIV value should not
be changed to divide-by-1 without first trimming the internal reference.
Failure to do so could result in the MCU running out of specification.
17.5.1.1
Initializing the MCG
Because the MCG comes out of reset in FEI mode, the only MCG modes which can be directly switched
to upon reset are FEE, FBE, and FBI modes (see Figure 17-15). Reaching any of the other modes requires
first configuring the MCG for one of these three initial modes. Care must be taken to check relevant status
bits in the MCGSC register reflecting all configuration changes within each mode.
To change from FEI mode to FEE or FBE modes, follow this procedure:
1. Enable the external clock source by setting the appropriate bits in MCGC2.
2. If the RANGE bit (bit 5) in MCGC2 is set, set DIV32 in MCGC3 to allow access to the proper
RDIV values.
3. Write to MCGC1 to select the clock mode.
— If entering FEE mode, set RDIV appropriately, clear the IREFS bit to switch to the external
reference, and leave the CLKS bits at %00 so that the output of the FLL is selected as the
system clock source.
— If entering FBE, clear the IREFS bit to switch to the external reference and change the CLKS
bits to %10 so that the external reference clock is selected as the system clock source. The
RDIV bits should also be set appropriately here according to the external reference frequency
because although the FLL is bypassed, it is still on in FBE mode.
— The internal reference can optionally be kept running by setting the IRCLKEN bit. This is
useful if the application will switch back and forth between internal and external modes. For
minimum power consumption, leave the internal reference disabled while in an external clock
mode.
4. Once the proper configuration bits have been set, wait for the affected bits in the MCGSC register
to be changed appropriately, reflecting that the MCG has moved into the proper mode.
— If ERCLKEN was set in step 1 or the MCG is in FEE, FBE, PEE, PBE, or BLPE mode, and
EREFS was also set in step 1, wait here for the OSCINIT bit to become set indicating that the
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
17-21
Multipurpose Clock Generator (S08MCGV3)
external clock source has finished its initialization cycles and stabilized. Typical crystal startup
times are given in Appendix A, “Electrical Characteristics”.
— If in FEE mode, check to make sure the IREFST bit is cleared and the LOCK bit is set before
moving on.
— If in FBE mode, check to make sure the IREFST bit is cleared, the LOCK bit is set, and the
CLKST bits have changed to %10 indicating the external reference clock has been
appropriately selected. Although the FLL is bypassed in FBE mode, it is still on and will lock
in FBE mode.
5. Write to the MCGC4 register to determine the DCO output (MCGOUT) frequency range. Make
sure that the resulting bus clock frequency does not exceed the maximum specified bus clock
frequency of the device.
— By default, with DMX32 cleared to 0, the FLL multiplier for the DCO output is 512. For greater
flexibility, if a mid-range FLL multiplier of 1024 is desired instead, set the DRS[1:0] bits to
%01 for a DCO output frequency of 33.55 MHz. If a high-range FLL multiplier of 1536 is
desired instead, set the DRS[1:0] bits to %10 for a DCO output frequency of 50.33 MHz.
— When using a 32.768 kHz external reference, if the maximum low-range DCO frequency that
can be achieved with a 32.768 kHz reference is desired, set the DRS[1:0] bits to %00 and set
the DMX32 bit to 1. The resulting DCO output (MCGOUT) frequency with the new multiplier
of 608 will be 19.92 MHz.
— When using a 32.768 kHz external reference, if the maximum mid-range DCO frequency that
can be achieved with a 32.768 kHz reference is desired, set the DRS[1:0] bits to %01 and set
the DMX32 bit to 1. The resulting DCO output (MCGOUT) frequency with the new multiplier
of 1216 will be 39.85 MHz.
— When using a 32.768 kHz external reference, if the maximum high-range DCO frequency that
can be achieved with a 32.768 kHz reference is desired, set the DRS[1:0] bits to %10 and set
the DMX32 bit to 1. The resulting DCO output (MCGOUT) frequency with the new multiplier
of 1824 will be 59.77 MHz.
6. Wait for the LOCK bit in MCGSC to become set, indicating that the FLL has locked to the new
multiplier value designated by the DRS and DMX32 bits.
NOTE
Setting DIV32 (bit 4) in MCGC3 is strongly recommended for FLL external
modes when using a high frequency range (RANGE = 1) external reference
clock. The DIV32 bit is ignored in all other modes.
To change from FEI clock mode to FBI clock mode, follow this procedure:
1. Change the CLKS bits in MCGC1 to %01 so that the internal reference clock is selected as the
system clock source.
2. Wait for the CLKST bits in the MCGSC register to change to %01, indicating that the internal
reference clock has been appropriately selected.
MCF51MM256 Series Devices Reference Manual, Rev. 3
17-22
Freescale Semiconductor
Multipurpose Clock Generator (S08MCGV3)
17.5.2
Using a 32.768 kHz Reference
In FEE and FBE modes, if using a 32.768 kHz external reference, at the default FLL multiplication factor
of 512, the DCO output (MCGOUT) frequency is 16.78 MHz at high-range. If the DRS[1:0] bits are set
to %01, the multiplication factor is doubled to 1024, and the resulting DCO output frequency is 33.55 Mhz
at mid-range. If the DRS[1:0] bits are set to %10, the multiplication factor is set to 1536, and the resulting
DCO output frequency is 50.33 Mhz at high-range. Make sure that the resulting bus clock frequency does
not exceed the maximum specified bus clock frequency of the device.
Setting the DMX32 bit in MCGC4 to 1 increases the FLL multiplication factor to allow the 32.768 kHz
reference to achieve its maximum DCO output frequency. When the DRS[1:0] bits are set to %00, the
32.768 kHz reference can achieve a high-range maximum DCO output of 19.92 MHz with a multiplier of
608. When the DRS[1:0] bits are set to %01, the 32.768 kHz reference can achieve a mid-range maximum
DCO output of 39.85 MHz with a multiplier of 1216. When the DRS[1:0] bits are set to %10, the 32.768
kHz reference can achieve a high-range maximum DCO output of 59.77 MHz with a multiplier of 1824.
Make sure that the resulting bus clock frequency does not exceed the maximum specified bus clock
frequency of the device.
In FBI and FEI modes, setting the DMX32 bit is not recommended. If the internal reference is trimmed to
a frequency above 32.768 kHz, the greater FLL multiplication factor could potentially push the
microcontroller system clock out of specification and damage the part.
17.5.3
MCG Mode Switching
When switching between operational modes of the MCG, certain configuration bits must be changed in
order to properly move from one mode to another. Each time any of these bits are changed (PLLS, IREFS,
CLKS, or EREFS), the corresponding bits in the MCGSC register (PLLST, IREFST, CLKST, or
OSCINIT) must be checked before moving on in the application software.
Additionally, care must be taken to ensure that the reference clock divider (RDIV) is set properly for the
mode being switched to. For instance, in PEE mode, if using a 4 MHz crystal, RDIV must be set to %001
(divide-by-2) or %010 (divide -by-4) in order to divide the external reference down to the required
frequency between 1 and 2 MHz.
If switching to FBE or FEE mode, first setting the DIV32 bit will ensure a proper reference frequency is
sent to the FLL clock at all times.
In FBE, FEE, FBI, and FEI modes, at any time, the application can switch the FLL multiplication factor
between 512, 1024, and 1536 with the DRS[1:0] bits in MCGC4. Writes to the DRS[1:0] bits will be
ignored if LP=1 or PLLS=1.
The RDIV and IREFS bits should always be set properly before changing the PLLS bit so that the FLL or
PLL clock has an appropriate reference clock frequency to switch to. The table below shows MCGOUT
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
17-23
Multipurpose Clock Generator (S08MCGV3)
frequency calculations using RDIV, BDIV, and VDIV settings for each clock mode. The bus frequency is
equal to MCGOUT divided by 2.
Table 17-17. MCGOUT Frequency Calculation Options
fMCGOUT1
Clock Mode
Note
FEI (FLL engaged internal)
(fint * F ) / B
Typical fMCGOUT = 16 MHz
immediately after reset.
FEE (FLL engaged external)
(fext / R *F) / B
fext / R must be in the range of
31.25 kHz to 39.0625 kHz
FBE (FLL bypassed external)
fext / B
fext / R must be in the range of
31.25 kHz to 39.0625 kHz
FBI (FLL bypassed internal)
fint / B
Typical fint = 32 kHz
PEE (PLL engaged external)
[(fext / R) * M] / B
fext / R must be in the range of 1
MHz to 2 MHz
PBE (PLL bypassed external)
fext / B
fext / R must be in the range of 1
MHz to 2 MHz
BLPI (Bypassed low power internal)
fint / B
BLPE (Bypassed low power external)
fext / B
1R
is the reference divider selected by the RDIV bits, B is the bus frequency divider selected by the BDIV bits,
F is the FLL factor selected by the DRS[1:0] and DMX32 bits, and M is the multiplier selected by the VDIV
bits.
This section will include 3 mode switching examples using an 8 MHz external crystal. If using an external
clock source less than 1 MHz, the MCG should not be configured for any of the PLL modes (PEE and
PBE).
17.5.3.1
Example 1: Moving from FEI to PEE Mode: External Crystal = 8 MHz, Bus
Frequency = 16 MHz
In this example, the MCG will move through the proper operational modes from FEI to PEE mode until
the 8 MHz crystal reference frequency is set to achieve a bus frequency of 16 MHz. Because the MCG is
in FEI mode out of reset, this example also shows how to initialize the MCG for PEE mode out of reset.
First, the code sequence will be described. Then a flowchart will be included which illustrates the
sequence.
1. First, FEI must transition to FBE mode:
a) MCGC2 = 0x36 (%00110110)
– BDIV (bits 7 and 6) set to %00, or divide-by-1
– RANGE (bit 5) set to 1 because the frequency of 8 MHz is within the high frequency range
– HGO (bit 4) set to 1 to configure the crystal oscillator for high gain operation
– EREFS (bit 2) set to 1, because a crystal is being used
– ERCLKEN (bit 1) set to 1 to ensure the external reference clock is active
MCF51MM256 Series Devices Reference Manual, Rev. 3
17-24
Freescale Semiconductor
Multipurpose Clock Generator (S08MCGV3)
b) Loop until OSCINIT (bit 1) in MCGSC is 1, indicating the crystal selected by the EREFS bit
has been initialized.
c) Because RANGE = 1, set DIV32 (bit 4) in MCGC3 to allow access to the proper RDIV bits
while in an FLL external mode.
d) MCGC1 = 0x98 (%10011000)
– CLKS (bits 7 and 6) set to %10 in order to select external reference clock as system clock
source
– RDIV (bits 5-3) set to %011, or divide-by-256 because 8MHz / 256 = 31.25 kHz which is
in the 31.25 kHz to 39.0625 kHz range required by the FLL
– IREFS (bit 2) cleared to 0, selecting the external reference clock
e) Loop until IREFST (bit 4) in MCGSC is 0, indicating the external reference is the current
source for the reference clock
f) Loop until CLKST (bits 3 and 2) in MCGSC is %10, indicating that the external reference
clock is selected to feed MCGOUT
2. Then, FBE must transition either directly to PBE mode or first through BLPE mode and then to
PBE mode:
a) BLPE: If a transition through BLPE mode is desired, first set LP (bit 3) in MCGC2 to 1.
b) BLPE/PBE: MCGC3 = 0x58 (%01011000)
– PLLS (bit 6) set to 1, selects the PLL. At this time, with an RDIV value of %011, the FLL
reference divider of 256 is switched to the PLL reference divider of 8 (see Table 17-8),
resulting in a reference frequency of 8 MHz/ 8 = 1 MHz. In BLPE mode,changing the PLLS
bit only prepares the MCG for PLL usage in PBE mode
– DIV32 (bit 4) still set at 1. Because the MCG is in a PLL mode, the DIV32 bit is ignored.
Keeping it set at 1 makes transitions back into an FLL external mode easier.
– VDIV (bits 3-0) set to %1000, or multiply-by-32 because 1 MHz reference * 32= 32MHz.
In BLPE mode, the configuration of the VDIV bits does not matter because the PLL is
disabled. Changing them only sets up the multiply value for PLL usage in PBE mode
c) BLPE: If transitioning through BLPE mode, clear LP (bit 3) in MCGC2 to 0 here to switch to
PBE mode
d) PBE: Loop until PLLST (bit 5) in MCGSC is set, indicating that the current source for the
PLLS clock is the PLL
e) PBE: Then loop until LOCK (bit 6) in MCGSC is set, indicating that the PLL has acquired lock
3. Lastly, PBE mode transitions into PEE mode:
a) MCGC1 = 0x18 (%00011000)
– CLKS (bits7 and 6) in MCGSC1 set to %00 in order to select the output of the PLL as the
system clock source
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
17-25
Multipurpose Clock Generator (S08MCGV3)
b) Loop until CLKST (bits 3 and 2) in MCGSC are %11, indicating that the PLL output is selected
to feed MCGOUT in the current clock mode
– Now, With an RDIV of divide-by-8, a BDIV of divide-by-1, and a VDIV of multiply-by-32,
MCGOUT = [(8 MHz / 8) * 32] / 1 = 32 MHz, and the bus frequency is MCGOUT / 2, or
16 MHz
MCF51MM256 Series Devices Reference Manual, Rev. 3
17-26
Freescale Semiconductor
Multipurpose Clock Generator (S08MCGV3)
START
IN FEI MODE
MCGC3 = $58
MCGC2 = $36
IN
BLPE MODE ?
(LP=1)
CHECK
NO
NO
YES
OSCINIT = 1 ?
MCGC2 = $36
(LP = 0)
YES
MCGC3 = $11
(DIV32 = 1)
MCGC1 = $98
CHECK
PLLST = 1?
NO
YES
CHECK
NO
IREFST = 0?
CHECK
LOCK = 1?
YES
CHECK
CLKST = %10?
NO
NO
YES
MCGC1 = $18
YES
ENTER
BLPE MODE ?
YES
MCGC2 = $3E
(LP = 1)
NO
CHECK
CLKST = %11?
NO
YES
CONTINUE
IN PEE MODE
Figure 17-16. Flowchart of FEI to PEE Mode Transition using an 8 MHz crystal
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
17-27
Multipurpose Clock Generator (S08MCGV3)
17.5.3.2
Example 2: Moving from PEE to BLPI Mode: Bus Frequency =16 kHz
In this example, the MCG will move through the proper operational modes from PEE mode with an 8MHz
crystal configured for an 16 MHz bus frequency (see previous example) to BLPI mode with a 16 kHz bus
frequency.First, the code sequence will be described. Then a flowchart will be included which illustrates
the sequence.
1. First, PEE must transition to PBE mode:
a) MCGC1 = 0x98 (%10011000)
– CLKS (bits 7 and 6) set to %10 in order to switch the system clock source to the external
reference clock
b) Loop until CLKST (bits 3 and 2) in MCGSC are %10, indicating that the external reference
clock is selected to feed MCGOUT
2. Then, PBE must transition either directly to FBE mode or first through BLPE mode and then to
FBE mode:
a) BLPE: If a transition through BLPE mode is desired, first set LP (bit 3) in MCGC2 to 1
b) BLPE/FBE: MCGC3 = 0x18(%00011000)
– PLLS (bit 6) clear to 0 to select the FLL. At this time, with an RDIV value of %011, the PLL
reference divider of 8 is switched to an FLL divider of 256 (see Table 17-7), resulting in a
reference frequency of 8 MHz / 256 = 31.25 kHz. If RDIV was not previously set to %011
(necessary to achieve required 31.25-39.06 kHz FLL reference frequency with an 8 MHz
external source frequency), it must be changed prior to clearing the PLLS bit. In BLPE
mode,changing this bit only prepares the MCG for FLL usage in FBE mode. With PLLS =
0, the VDIV value does not matter.
– DIV32 (bit 4) set to 1 (if previously cleared), automatically switches RDIV bits to the proper
reference divider for the FLL clock (divide-by-256)
c) BLPE: If transitioning through BLPE mode, clear LP (bit 3) in MCGC2 to 0 here to switch to
FBE mode
d) FBE: Loop until PLLST (bit 5) in MCGSC is clear, indicating that the current source for the
PLLS clock is the FLL
e) FBE: Optionally, loop until LOCK (bit 6) in the MCGSC is set, indicating that the FLL has
acquired lock. Although the FLL is bypassed in FBE mode, it is still enabled and running.
3. Next, FBE mode transitions into FBI mode:
a) MCGC1 = 0x5C (%01011100)
– CLKS (bits7 and 6) in MCGSC1 set to %01 in order to switch the system clock to the
internal reference clock
MCF51MM256 Series Devices Reference Manual, Rev. 3
17-28
Freescale Semiconductor
Multipurpose Clock Generator (S08MCGV3)
– IREFS (bit 2) set to 1 to select the internal reference clock as the reference clock source
– RDIV (bits 5-3) remain unchanged because the reference divider does not affect the internal
reference.
b) Loop until IREFST (bit 4) in MCGSC is 1, indicating the internal reference clock has been
selected as the reference clock source
c) Loop until CLKST (bits 3 and 2) in MCGSC are %01, indicating that the internal reference
clock is selected to feed MCGOUT
4. Lastly, FBI transitions into BLPI mode.
a) MCGC2 = 0x08 (%00001000)
– LP (bit 3) in MCGSC is 1
– RANGE, HGO, EREFS, ERCLKEN, and EREFSTEN bits are ignored when the IREFS bit
(bit2) in MCGC is set. They can remain set, or be cleared at this point.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
17-29
Multipurpose Clock Generator (S08MCGV3)
START
IN PEE MODE
MCGC1 = $98
CHECK
PLLST = 0?
CHECK
NO
CLKST = %10 ?
YES
ENTER
NO
YES
OPTIONAL:
CHECK LOCK
= 1?
NO
NO
BLPE MODE ?
YES
MCGC1 = $5C
YES
MCGC2 = $3E
(LP = 1)
CHECK
IREFST = 0?
MCGC3 = $18
IN
BLPE MODE ?
(LP=1)
NO
YES
NO
CHECK
CLKST = %01?
NO
YES
YES
MCGC2 = $36
(LP = 0)
MCGC2 = $08
CONTINUE
IN BLPI MODE
Figure 17-17. Flowchart of PEE to BLPI Mode Transition using an 8 MHz crystal
MCF51MM256 Series Devices Reference Manual, Rev. 3
17-30
Freescale Semiconductor
Multipurpose Clock Generator (S08MCGV3)
17.5.3.3
Example 3: Moving from BLPI to FEE Mode: External Crystal = 8 MHz,
Bus Frequency = 16 MHz
In this example, the MCG will move through the proper operational modes from BLPI mode at a 16 kHz
bus frequency running off of the internal reference clock (see previous example) to FEE mode using an
8MHz crystal configured for a 16 MHz bus frequency. First, the code sequence will be described. Then a
flowchart will be included which illustrates the sequence.
1. First, BLPI must transition to FBI mode.
a) MCGC2 = 0x00 (%00000000)
– LP (bit 3) in MCGSC is 0
b) Optionally, loop until LOCK (bit 6) in the MCGSC is set, indicating that the FLL has acquired
lock. Although the FLL is bypassed in FBI mode, it is still enabled and running.
2. Next, FBI will transition to FEE mode.
a) MCGC2 = 0x36 (%00110110)
– RANGE (bit 5) set to 1 because the frequency of 8 MHz is within the high frequency range
– HGO (bit 4) set to 1 to configure the crystal oscillator for high gain operation
– EREFS (bit 2) set to 1, because a crystal is being used
– ERCLKEN (bit 1) set to 1 to ensure the external reference clock is active
b) Loop until OSCINIT (bit 1) in MCGSC is 1, indicating the crystal selected by the EREFS bit
has been initialized.
c) MCGC1 = 0x18 (%00011000)
– CLKS (bits 7 and 6) set to %00 in order to select the output of the FLL as system clock
source
– RDIV (bits 5-3) remain at %011, or divide-by-256 for a reference of 8 MHz / 256 = 31.25
kHz.
– IREFS (bit 1) cleared to 0, selecting the external reference clock
d) Loop until IREFST (bit 4) in MCGSC is 0, indicating the external reference clock is the current
source for the reference clock
e) Optionally, loop until LOCK (bit 6) in the MCGSC is set, indicating that the FLL has
reacquired lock.
f) Loop until CLKST (bits 3 and 2) in MCGSC are %00, indicating that the output of the FLL is
selected to feed MCGOUT
g) Now, with a 31.25 kHz reference frequency, a fixed DCO multiplier of 512, and a bus divider
of 1, MCGOUT = 31.25 kHz * 512 / 1 = 16 MHz. Therefore, the bus frequency is 8 MHz.
h) At this point, by default, the DRS[1:0] bits in MCGC4 are set to %00 and DMX32 in MCGC4
is cleared to 0. If a bus frequency of 16MHz is desired instead, set the DRS[1:0] bits to $01 to
switch the FLL multiplication factor from 512 to 1024 and loop until LOCK (bit 6) in MCGSC
is set, indicating that the FLL has reacquired LOCK. To return the bus frequency to 8 MHz, set
the DRS[1:0] bits to %00 again, and the FLL multiplication factor will switch back to 512.
Then loop again until the LOCK bit is set.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
17-31
Multipurpose Clock Generator (S08MCGV3)
START
IN BLPI MODE
CHECK
NO
IREFST = 0?
MCGC2 = $00
YES
OPTIONAL:
CHECK LOCK
= 1?
NO
OPTIONAL:
CHECK LOCK
= 1?
NO
YES
YES
MCGC2 = $36
CHECK
CLKST = %00?
CHECK
NO
NO
YES
OSCINIT = 1 ?
CONTINUE
YES
IN FEE MODE
MCGC1 = $18
Figure 17-18. Flowchart of BLPI to FEE Mode Transition using an 8 MHz crystal
17.5.4
Calibrating the Internal Reference Clock (IRC)
The IRC is calibrated by writing to the MCGTRM register first, then using the FTRIM bit to “fine tune”
the frequency. We will refer to this total 9-bit value as the trim value, ranging from 0x000 to 0x1FF, where
the FTRIM bit is the LSB.
The trim value after reset is the factory trim value unless the device resets into any BDM mode in which
case it is 0x800. Writing a larger value will decrease the frequency and smaller values will increase the
frequency. The trim value is linear with the period, except that slight variations in wafer fab processing
produce slight non-linearities between trim value and period. These non-linearities are why an iterative
MCF51MM256 Series Devices Reference Manual, Rev. 3
17-32
Freescale Semiconductor
Multipurpose Clock Generator (S08MCGV3)
trimming approach to search for the best trim value is recommended. In Example 4: Internal Reference
Clock Trim later in this section, this approach will be demonstrated.
If a user specified trim value has been found for a device (to replace the factory trim value), this value can
be stored in FLASH memory to save the value. If power is removed from the device, the IRC can easily
be re-trimmed to the user specified value by copying the saved value from FLASH to the MCG registers.
Freescale identifies recommended FLASH locations for storing the trim value for each MCU. Consult the
memory map in the data sheet for these locations.
17.5.4.1
Example 4: Internal Reference Clock Trim
For applications that require a user specified tight frequency tolerance, a trimming procedure is provided
that will allow a very accurate internal clock source. This section outlines one example of trimming the
internal oscillator. Many other possible trimming procedures are valid and can be used.
In the example below, the MCG trim will be calibrated for the 9-bit MCGTRM and FTRIM collective
value. This value will be referred to as TRMVAL.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
17-33
Multipurpose Clock Generator (S08MCGV3)
Initial conditions:
1) Clock supplied from ATE has 500 sec duty period
2) MCG configured for internal reference with 8MHz bus
START TRIM PROCEDURE
TRMVAL = $100
n=1
MEASURE
INCOMING CLOCK WIDTH
(COUNT = # OF BUS CLOCKS / 8)
COUNT < EXPECTED = 500
(RUNNING TOO SLOW)
.
CASE STATEMENT
COUNT = EXPECTED = 500
COUNT > EXPECTED = 500
(RUNNING TOO FAST)
TRMVAL =
TRMVAL - 256/ (2**n)
(DECREASING TRMVAL
INCREASES THE FREQUENCY)
TRMVAL =
TRMVAL + 256/ (2**n)
(INCREASING TRMVAL
DECREASES THE FREQUENCY)
STORE MCGTRM AND
FTRIM VALUES IN
NON-VOLATILE MEMORY
CONTINUE
n = n+1
IS n > 9?
YES
NO
Figure 17-19. Trim Procedure
In this particular case, the MCU has been attached to a PCB and the entire assembly is undergoing final
test with automated test equipment. A separate signal or message is provided to the MCU operating under
user provided software control. The MCU initiates a trim procedure as outlined in Figure 17-19 while the
tester supplies a precision reference signal.
If the intended bus frequency is near the maximum allowed for the device, it is recommended to trim using
a reference divider value (RDIV setting) of twice the final value. After the trim procedure is complete, the
reference divider can be restored. This will prevent accidental overshoot of the maximum clock frequency.
MCF51MM256 Series Devices Reference Manual, Rev. 3
17-34
Freescale Semiconductor
Chapter 18
Mini-FlexBus
18.1
Introduction
This chapter describes external bus data transfer operations and error conditions. It describes transfers
initiated by the ColdFire processor (or any other bus master) and includes detailed timing diagrams
showing the interaction of signals in supported bus operations.
The Mini-FlexBus is a subset of the FlexBus module found on other ColdFire microprocessors. The
Mini-FlexBus minimizes package pin-outs while maintaining a high level of configurability and
functionality.
•
18.1.1
NOTE
In this chapter, unless otherwise noted, clock refers to the FB_CLK used
for the external bus (fsys).
Overview
A multi-function external bus interface called the Mini-FlexBus interface controller is provided on the
device with basic functionality of interfacing to slave-only devices. It can be directly connected to the
following asynchronous or synchronous devices with little or no additional circuitry:
• External ROMs
• Flash memories
• Programmable logic devices
• Other simple target (slave) devices
For asynchronous devices, a simple chip-select based interface can be used.
The Mini-FlexBus interface has up to two general purpose chip-selects, FB_CS[1:0]. The actual number
of chip selects available depends upon the device and its pin configuration.
18.1.2
Features
Key Mini-FlexBus features include:
• Two independent, user-programmable chip-select signals (FB_CS[1:0]) that can interface with
external SRAM, PROM, EPROM, EEPROM, flash, and other peripherals
• 8- and 16-bit port sizes with configuration for multiplexed or non-multiplexed address and data
buses
• Byte-, word-, longword-, and 16-byte line-sized transfers
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
18-1
Mini-FlexBus
•
•
Programmable address-setup time with respect to the assertion of chip select
Programmable address-hold time with respect to the negation of chip select and transfer direction
18.1.3
Modes of Operation
The external interface is a configurable multiplexed bus set to one of the following modes:
•
Up to a 20-bit address (non-multiplexed) with 8-bit data
•
Up to a 20-bit address (multiplexed) with 16-bit data (write masking of upper/lower bytes not
supported)
•
Up to a 20-bit address (multiplexed) with 8-bit data
18.1.4
Module Configuration
A subset of the Mini-FlexBus signals can be repositioned under software control using
SOPT3[MB_DATA] as shown in Table 18-1. This functionality allows the 81-pin MAPBGA and 80-pin
LQFP devices a minimal functionality data bus to interface with slave devices. SOPT3[MB_DATA]
selects which general-purpose I/O ports are associated with Mini-FlexBus operation.
Table 18-1. Mini-FlexBus Position Options
SOPT3[MB_DATA]
FB_D0
FB_D2
FB_D3
FB_D4
FB_D5
FB_D6
FB_D7
FB_R/W
FB_OE
0 (default)
PTH1
PTH7
PTH6
PTH5
PTH4
PTH3
PTH2
PTG5
PTH0
1
PTC1
PTA0
PTF5
PTF4
PTF3
PTA3
PTE5
PTE6
PTC0
18.1.5
Mini-FlexBus Security Level
SOPT1[MBSL] controls the Mini-FlexBus security level. This bit has no effect if security is not enabled.
If security is enabled and MBSL is set, off-chip opcode accesses via the Mini-FlexBus are disallowed,
while data accesses are allowed.
18.1.6
Mini-FlexBus Clock Gating
The bus clock to the Mini-FlexBus can be gated on and off using SCGC2[MFB]. This bit is set after any
reset, which enables the bus clock to this module. When this module is not in use, clear the MFB bit t o
disable the clock and conserve power. See Section 5.6, “Peripheral Clock Gating,” for details.
MCF51MM256 Series Devices Reference Manual, Rev. 3
18-2
Freescale Semiconductor
Mini-FlexBus
Figure 18-1. Block Diagram with FlexBus Module Highlighted
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
18-3
Mini-FlexBus
18.2
External Signals
This section describes the external signals involved in data-transfer operations.
Table 18-2. Mini-FlexBus Signal Summary
18.2.1
Signal Name
I/O
Description
FB_A[19:0]
I/O
In a non-multiplexed configuration, this is the address bus. In a multiplexed
configuration this bus is the address/data bus, FB_AD[19:0].
FB_D[7:0]
I/O
In a non-multiplexed configuration, this is the data bus. In multiplexed
configurations, this bus is not used.
FB_CS[1:0]
O
General purpose chip-selects. In multiplexed mode, only FB_CS0 is
available. FB_CS1 is multiplexed with FB_ALE on a configurable package
pin.
FB_OE
O
Output enable
FB_R/W
O
Read/write. 1 = Read, 0 = Write
FB_ALE
O
Address latch enable. This signal is multiplexed with FB_CS1 on a
configurable package pin.
Address and Data Buses (FB_A[19:0], FB_D[7:0], FB_AD[ 19:0])
In non-multiplexed mode, the FB_A[19:0] and FB_D[7:0] buses carry the address and data, respectively.
In multiplexed mode, the FB_AD[ 19 :0] bus carries the address and data. The full 20 -bit address is driven
on the first clock of a bus cycle (address phase). Following the first clock, the data is driven on the bus
(data phase). During the data phase, the address continues driving on the pins not used for data. For
example, in 16-bit mode the address continues driving on FB_AD[19 :16 ] and in 8-bit mode the address
continues driving on FB_AD[ 19 :8 ].
18.2.2
Chip Selects (FB_CS[1:0])
The chip-select signal indicates which device is selected. A particular chip-select asserts when the transfer
address is within the device’s address space, as defined in the base- and mask-address registers. The actual
number of chip selects available depends upon the pin configuration.
18.2.3
Output Enable (FB_OE)
The output enable signal (FB_OE) is sent to the interfacing memory and/or peripheral to enable a read
transfer. FB_OE is only asserted during read accesses when a chip select matches the current address
decode.
18.2.4
Read/Write (FB_R/W)
The processor drives the FB_R/W signal to indicate the current bus operation direction. It is driven high
during read bus cycles and low during write bus cycles.
MCF51MM256 Series Devices Reference Manual, Rev. 3
18-4
Freescale Semiconductor
Mini-FlexBus
18.2.5
Address Latch Enable (FB_ALE)
The assertion of FB_ALE indicates that the device has begun a bus transaction and the address and
attributes are valid. FB_ALE is asserted for one bus clock cycle. FB_ALE may be used externally to
capture the bus transfer address (Figure 18-8).
18.3
Memory Map/Register Definition
The following tables describe the registers and bit meanings for configuring chip-select operation.
Table 18-3 shows the chip-select register memory map.
The actual number of chip select registers available depends upon the device and its pin configuration. If
the device does not support certain chip select signals or the pin is not configured for a chip-select function,
then that corresponding set of chip-select registers has no effect on an external pin.
NOTE
You must set CSMR0[V] before the chip select registers take effect.
Table 18-3. Mini-FlexBus Chip Select Memory Map
Offset
Width
Access
(bits)
Register
Reset Value
Section/
Page
0x00
0x0C
Chip-Select Address Register (CSARn)
n=0–1
32
R/W
0x0000_0000
18.3.1/18-5
0x04
0x10
Chip-Select Mask Register (CSMRn)
n=0–1
32
R/W
0x0000_0000
18.3.2/18-6
0x08
0x14
Chip-Select Control Register (CSCRn)
n=0–1
32
R/W
See Section
18.3.3/18-7
18.3.1
Chip-Select Address Registers (CSAR0 – CSAR1)
The CSARn registers specify the chip-select base addresses.
NOTE
The only applicable address range for which the chip-selects can be active
are 0x(00)40_0000 – 0x(00)7F_FFFF. Set the CSARn and CSMRn registers
appropriately before accessing this region.
Address: 0x00 (CSAR0)
0x0C (CSAR1)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
BA
8
7
6
5
4
3
2
1
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 18-2. Chip-Select Address Registers (CSARn)
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
18-5
Mini-FlexBus
Table 18-4. CSARn Field Descriptions
Field
Description
31–16
BA
Base address. Defines the base address for memory dedicated to chip-select FB_CSn. BA is compared to
bits 31–16 on the internal address bus to determine if chip-select memory is being accessed.
15–0
Reserved, must be cleared.
18.3.2
Chip-Select Mask Registers (CSMR0 – CSMR1)
CSMRn registers specify the address mask and allowable access types for the respective chip-selects.
Address: 0x04 (CSMR0)
0x10 (CSMR1)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
BAM
W
0 0 0 0 0 0 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
8
WP
0
7
6
5
4
3
2
1
0 0 0 0 0 0 0
0
V
0 0 0 0 0 0 0 0
Figure 18-3. Chip-Select Mask Registers (CSMRn)
Table 18-5. CSMRn Field Descriptions
Field
31–16
BAM
Description
Base address mask. Defines the chip-select block size by masking address bits. Setting a BAM bit causes the
corresponding CSAR bit to be a don’t care in the decode.
0 Corresponding address bit is used in chip-select decode.
1 Corresponding address bit is a don’t care in chip-select decode.
The block size for FB_CSn is 2n; n = (number of bits set in respective CSMR[BAM]) + 16.
For example, if CSAR0 equals 0x0040 and CSMR0[BAM] equals 0x000, FB_CS0 addresses two discontinuous
64 KB memory blocks: one from 0x40_0000 – 0x40_FFFF and one from 0x48_0000 – 0x48_FFFF.
Likewise, for FB_CS0 to access 2 MB of address space starting at location 0x40_0000, FB_CS1 must begin at the
next byte after FB_CS0 for a 1 MB address space. Therefore, CSAR0 equals 0x0040,
CSMR0[BAM] equals 0x001F, CSAR1 equals 0x0060, and CSMR1[BAM] equals 0x000F.
15–9
Reserved, must be cleared.
8
WP
Write protect. Controls write accesses to the address range in the corresponding CSAR. Attempting to write to the
range of addresses for which CSARn[WP] is set results in a bus error termination of the internal cycle and no external
cycle.
0 Read and write accesses are allowed
1 Only read accesses are allowed
7–1
Reserved, must be cleared.
0
V
Valid bit. Indicates whether the corresponding CSAR, CSMR, and CSCR contents are valid. Programmed
chip-selects do not assert until V bit is set. Reset clears each CSMRn[V].
Note: At reset, no chip-select can be used until the CSMR0[V] is set. Afterward, FB_CS[1:0] functions as
programmed.
0 Chip-select invalid
1 Chip-select valid
MCF51MM256 Series Devices Reference Manual, Rev. 3
18-6
Freescale Semiconductor
Mini-FlexBus
18.3.3
Chip-Select Control Registers (CSCR0 – CSCR1)
Each CSCRn controls the auto-acknowledge, address setup and hold times, port size, and number of wait
states.
Address: 0x08 (CSCR0)
0x14 (CSCR1)
Access: User read/write
31
30
29
28
27
26
25
24
23
22
0
0
0
0
0
0
0
0
0
0
Reset: CSCR0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
Reset: CSCR1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
R
21
WS
W
MUX
AA
PS
19
18
RDAH
ASET
W
R
20
17
16
WRAH
5
4
3
2
1
0
0
0
0
0
0
0
Reset: CSCR0
1
1
1
1
1
1
0
1
0
1
0
0
0
0
0
0
Reset: CSCR1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 18-4. Chip-Select Control Registers (CSCRn)
Table 18-6. CSCRn Field Descriptions
Field
Description
31–22
Reserved, must be cleared
21–20
ASET
Address setup. This field controls the assertion of the chip-select with respect to assertion of a valid address and
attributes. The address and attributes are considered valid at the same time FB_ALE asserts.
00 Assert FB_CSn on first rising clock edge after address is asserted. (Default FB_CS1)
01 Assert FB_CSn on second rising clock edge after address is asserted.
10 Assert FB_CSn on third rising clock edge after address is asserted.
11 Assert FB_CSn on fourth rising clock edge after address is asserted. (Default FB_CS0)
19–18
RDAH
Read address hold or deselect. This field controls the address and attribute hold time after the termination during a
read cycle that hits in the chip-select address space.
Note: The hold time applies only at the end of a transfer. Therefore, during a transfer to a port size smaller than the
transfer size, the hold time is only added after the last bus cycle.
The number of cycles the address and attributes are held after FB_CSn negation depends on the value of
CSCRn[AA] as shown below.
RDAH
AA = 1
00
(FB_CS1 Default)
0 cycles
01
1 cycles
10
2 cycles
11
(FB_CS0 Default)
3 cycles
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
18-7
Mini-FlexBus
Table 18-6. CSCRn Field Descriptions (Continued)
Field
Description
17–16
WRAH
Write address hold or deselect. This field controls the address, data, and attribute hold time after the termination of
a write cycle that hits in the chip-select address space.
Note: The hold time applies only at the end of a transfer. Therefore, during a transfer to a port size smaller than the
transfer size, the hold time is only added after the last bus cycle.
00 Hold address and attributes one cycle after FB_CSn negates on writes. (Default FB_CS1)
01 Hold address and attributes two cycles after FB_CSn negates on writes.
10 Hold address and attributes three cycles after FB_CSn negates on writes.
11 Hold address and attributes four cycles after FB_CSn negates on writes. (Default FB_CS0)
15–10
WS
Wait states. The number of wait states inserted after FB_CSn asserts and before an internal transfer acknowledge
is generated (WS = 0 inserts zero wait states, WS = 0x3F inserts 63 wait states).
9
MUX
Multiplexed mode. Selects between multiplexed and non-multiplexed address/data bus.
0 Non-multiplexed configuration. Address information is driven on FB_ADn and data is read/written on FB_dn.
1 Non-multiplexed configuration. Address information is driven on FB_ADn, and low-order address lines
(FB_AD[7:0] for byte port size or FB_AD[15:0] for word port size) must be latched using the falling edge of FB_ALE
as the latch enable. Data is read/written on FB_AD[7:0] for byte port size and FB_AD[15:0] for word port size.
8
AA
Auto-acknowledge enable. Determines the assertion of the internal transfer acknowledge for accesses specified by
the chip-select address. This bit must be set.
0 Reserved
1 Internal transfer acknowledge is asserted as specified by WS
Note: This bit must be set, since only internal termination is supported by the Mini-FlexBus.
7–6
PS
Port size. Specifies the data port width associated with each chip-select. It determines where data is driven during
write cycles and where data is sampled during read cycles.
00 Reserved
01 8-bit port size. Valid data sampled and driven on FB_D[7:0]
1x 16-bit port size. Valid data sampled and driven on FB_AD[15:0]. Only supported in multiplexed mode.
5–0
Reserved, must be cleared.
18.4
18.4.1
Functional Description
Chip-Select Operation
Each chip-select has a dedicated set of registers for configuration and control:
• Chip-select address registers (CSARn) control the base address space of the chip-select. See
Section 18.3.1, “Chip-Select Address Registers (CSAR0 – CSAR1).”
• Chip-select mask registers (CSMRn) provide 16-bit address masking and access control. See
Section 18.3.2, “Chip-Select Mask Registers (CSMR0 – CSMR1).”
• Chip-select control registers (CSCRn) provide port size, wait-state generation, address setup and
hold times, and automatic acknowledge generation features. See Section 18.3.3, “Chip-Select
Control Registers (CSCR0 – CSCR1).”
MCF51MM256 Series Devices Reference Manual, Rev. 3
18-8
Freescale Semiconductor
Mini-FlexBus
18.4.1.1
General Chip-Select Operation
When a bus cycle is routed to the Mini-FlexBus, the device first compares its address with the base address
and mask configurations programmed for chip-selects 0 and 1 (configured in CSCR0 – CSCR1). The
results depend on if the address matches or not as shown in Table 18-7.
Table 18-7. Results of Address Comparison
Address Matches
CSARn?
Result
Yes,
one CSAR
The appropriate chip-select is asserted, generating an external bus cycle as defined in the chip-select
control register.
If CSMR[WP] is set and a write access is performed, the internal bus cycle terminates with a bus error,
no chip select is asserted, and no external bus cycle is performed.
No
The internal bus cycle terminates with a bus error, no chip select is asserted, and no external bus cycle
is performed.
Yes,
multiple CSARs
The internal bus cycle terminates with a bus error, no chip select is asserted, and no external bus cycle
is performed.
18.4.1.2
8- and 16-Bit Port Sizing
Static bus sizing is programmable through the port size bits, CSCR[PS]. The processor always drives a
20-bit address on the FB_AD bus regardless of the external device’s address size. The external device must
connect its address lines to the appropriate FB_AD bits from FB_AD0 upward. Its data bus must be
connected to FB_AD[7:0] in non-multiplexed mode (CSCR[MUX] = 0) or FB_AD0 to FB_ADn in
multiplexed mode (CSCR[MUX] = 1) where n = 15 if CSCR[PS] = 1x or n = 7 if CSCR[PS] = 01. No bit
ordering is required when connecting address and data lines to the FB_AD bus. For example, a full 16-bit
address/16-bit data device connects its addr[15:0] to FB_AD[16:1] and data[15:0] to FB_AD[15:0]. See
Figure 18-5 for a graphical connection.
18.4.2
Data Transfer Operation
Data transfers between the chip and other devices involve these signals:
•
Address/data bus (FB_AD[19:0])
•
Control signals (FB_ALE, FB_CSn, FB_OE)
•
Attribute signals (FB_R/W)
The address, write data, FB_ALE, FB_CSn, and all attribute signals change on the rising edge of the
Mini-FlexBus clock (FB_CLK). Read data is latched into the device on the rising edge of the clock.
The Mini-FlexBus supports byte-, word-, longword-, and 16-byte (line) operand transfers and allows
accesses to 8- and 16-bit data ports.Transfer parameters (address setup and hold, port size, the number of
wait states for the external device being accessed, automatic internal transfer termination enable or
disable) are programmed in the chip-select control registers (CSCRs). See Section 18.3.3, “Chip-Select
Control Registers (CSCR0 – CSCR1).”
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
18-9
Mini-FlexBus
18.4.3
Data Byte Alignment and Physical Connections
The device aligns data transfers in Mini-FlexBus byte lanes with the number of lanes depending on the
data port width. Figure 18-5 shows the byte lanes that external memory connects to and the sequential
transfers of a longword transfer for the supported port sizes . For example, an 8-bit memory connects to
the single lane FB_AD[7:0]. A longword transfer through this 8-bit port takes four transfers, starting with
the MSB to the LSB.
Non-multiplexed Mode
Multiplexed Mode
External
Data Bus
16-Bit Port
Memory
8-Bit Port
Memory
FB_AD[15:8]
FB_AD[7:0]
Byte 0
Byte 1
Byte 2
Byte 3
External
Data Bus
FB_D[7:0]
8-Bit Port
Memory
Byte 0
Byte 1
Byte 2
Byte 0
Driven with
address
values
Byte 3
Byte 1
Byte 2
Byte 3
Figure 18-5. Connections for External Memory Port Sizes
18.4.4
Address/Data Bus Multiplexing
The interface supports a single 20 -bit wide multiplexed address and data bus (FB_AD[ 19 :0]). The full
20 -bit address is always driven on the first clock of a bus cycle. During the data phase, the FB_AD[ 15 :0]
lines used for data are determined by the programmed port size for the corresponding chip select. The
device continues to drive the address on any FB_AD[ 15 :0] lines not used for data.
The table below lists the supported combinations of address and data bus widths.
Table 18-9. Mini-FlexBus Multiplexed Operating Modes
FB_AD
Port Size & Phase
18.4.5
16-bit
Address phase
8-bit
[19:16]
Address phase
Data phase
Data phase
[15:8]
[7:0]
Address
Address
Data
Address
Address
Data
Bus Cycle Execution
As shown in Figure 18-8 and Figure 18-10, basic bus operations occur in four clocks:
1. S0: At the first clock edge, the address, attributes, and FB_ALE are driven.
2. S1: FB_CSn is asserted at the second rising clock edge to indicate the device selected; by that time,
the address and attributes are valid and stable. FB_ALE is negated at this edge.
MCF51MM256 Series Devices Reference Manual, Rev. 3
18-10
Freescale Semiconductor
Mini-FlexBus
For a write transfer, data is driven on the bus at this clock edge and continues to be driven until one
clock cycle after FB_CSn negates. For a read transfer, data is also driven into the device during this
cycle.
3. S2: Read data is sampled on the third clock edge. After this edge read data can be tri-stated.
4. S3: FB_CSn is negated at the fourth rising clock edge. This last clock of the bus cycle uses what
would be an idle clock between cycles to provide hold time for address, attributes, and write data.
18.4.5.1
Data Transfer Cycle States
An on-chip state machine controls the data-transfer operation in the device. Figure 18-6 shows the
state-transition diagram for basic read and write cycles.
Next Cycle
S0
Wait States
S3
S1
S2
Figure 18-6. Data-Transfer-State-Transition Diagram
Table 18-10 describes the states as they appear in subsequent timing diagrams.
Table 18-10. Bus Cycle States
State
Cycle
Description
S0
All
The read or write cycle is initiated. On the rising clock edge, the device places a valid address on
FB_AD[19:0], asserts FB_ALE, and drives FB_R/W high for a read and low for a write.
S1
All
FB_ALE is negated on the rising edge of FB_CLK, and FB_CSn is asserted. Data is driven on
FB_AD[X:0] for writes, and FB_AD[X:0] is tristated for reads. Address continues to be driven on
the FB_AD pins that are unused for data.
Read
Data is driven by the external device before the next rising edge of FB_CLK (the rising edge that
begins S2).
S2
All
Read
S3
All
FB_CSn is negated and the internal system bus transfer is completed.
The processor latches data on the rising clock edge entering S2. The external device can stop
driving data after this edge. However, data can be driven until the end of S3 or any additional
address hold cycles.
Address, data, and FB_R/W go invalid off the rising edge of FB_CLK at the beginning of S3,
terminating the read or write cycle.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
18-11
Mini-FlexBus
18.4.6
18.4.6.1
Mini-FlexBus Timing Examples
Basic Read Bus Cycle
During a read cycle, the ColdFire device receives data from memory or a peripheral device. Figure 18-7
is a read cycle flowchart.
NOTE
Throughout this chapter FB_AD[X:0] indicates a 16-, or 8-bit wide data bus.
FB_AD[ 19:X+1 ] is an address bus that can be 12-, or 4 -bits in width.
ColdFire device
System
1. Set FB_R/W to read.
2. Place address on FB_AD[19:0].
3. Assert FB_ALE.
1. Decode address.
1. Negate FB_ALE.
2. Assert FB_CSn.
1. Mini-FlexBus asserts internal transfer
acknowledge (auto-acknowledge).
1. Select the appropriate slave device.
2. Drive data on FB_AD[X:0].
1. Start next cycle.
Figure 18-7. Read Cycle Flowchart
The read cycle timing diagram is shown in Figure 18-8.
NOTE
The processor drives the data lines during the first clock cycle of the transfer
with the full 20-bit address. This may be ignored by standard connected
devices using non-multiplexed address and data buses. However, some
applications may find this feature beneficial.
MCF51MM256 Series Devices Reference Manual, Rev. 3
18-12
Freescale Semiconductor
Mini-FlexBus
S0
S1
S2
S3
S0
FB_CLK
FB_AD[19:X+1]
ADDR[19:X+1]
Mux’d Bus
FB_AD[X:0]
ADDR[X:0]
FB_A[19:0]
DATA
ADDR[19:0]
Non-Mux’d Bus
FB_D[7:0]
DATA
FB_R/W
FB_ALE
FB_CSn, FB_OE
Figure 18-8. Basic Read-Bus Cycle
18.4.6.2
Basic Write Bus Cycle
During a write cycle, the device sends data to memory or to a peripheral device. Figure 18-9 shows the
write cycle flowchart.
ColdFire device
System
1. Set FB_R/W to write.
2. Place address on FB_AD[19:0].
3. Assert FB_ALE.
1. Decode address.
1. Negate FB_ALE.
2. Assert FB_CSn.
3. Drive data.
1. Mini-FlexBus asserts internal transfer
acknowledge (auto-acknowledge).
1. Select the appropriate slave device.
2. Latch data on FB_AD[X:0].
1. Start next cycle.
Figure 18-9. Write-Cycle Flowchart
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
18-13
Mini-FlexBus
Figure 18-10 shows the write cycle timing diagram.
S0
S1
S2
S3
S0
FB_CLK
ADDR[19:X+1]
FB_AD[19:X+1]
Mux’d Bus
FB_AD[X:0]
FB_A[19:0]
DATA
ADDR[X:0]
ADDR[19:0]
Non-Mux’d Bus
FB_D[7:0]
DATA
FB_R/W
FB_ALE
FB_CSn
FB_OE
Figure 18-10. Basic Write-Bus Cycle
18.4.6.3
Bus Cycle Sizing
This section shows timing diagrams for various port size scenarios. Figure 18-11 illustrates the basic byte
read transfer to an 8-bit device with no wait states. The address is driven on the full FB_AD[19:8] bus in
MCF51MM256 Series Devices Reference Manual, Rev. 3
18-14
Freescale Semiconductor
Mini-FlexBus
the first clock. The device tristates FB_AD[7:0] on the second clock and continues to drive address on
FB_AD[ 19:8 ] throughout the bus cycle. The external device returns the read data on FB_AD[7:0].
S0
S1
S2
S3
S0
FB_CLK
FB_AD[19:8]
ADDR[19:8]
Mux’d Bus
FB_AD[7:0]
ADDR[7:0]
FB_A[19:0]
DATA[7:0]
ADDR[19:0]
Non-Mux’d Bus
FB_D[7:0]
DATA[7:0]
FB_R/W
FB_ALE
FB_CSn, FB_OE
Figure 18-11. Single Byte-Read Transfer
Figure 18-12 shows the similar configuration for a write transfer. The data is driven from the second clock
on FB_AD[7:0].
S0
S1
S2
S3
S0
FB_CLK
ADDR[19:8]
FB_AD[19:8]
Mux’d Bus
FB_AD[7:0]
FB_A[19:0]
ADDR[7:0]
DATA[7:0]
ADDR[19:0]
Non-Mux’d Bus
FB_D[7:0]
DATA[7:0]
FB_R/W
FB_ALE
FB_CSn
FB_OE
Figure 18-12. Single Byte-Write Transfer
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
18-15
Mini-FlexBus
Figure 18-13 illustrates the basic word read transfer to a 16-bit device with no wait states. The address is
driven on the full FB_AD[19:0] bus in the first clock. The device tristates FB_AD[15:0] on the second
clock and continues to drive the address on FB_AD[ 19:16 ] throughout the bus cycle. The external device
returns the read data on FB_AD[15:0].
NOTE
In non-multiplexed mode, the Mini-FlexBus does not support connection to
a 16-bit device.
S0
S1
S2
S3
S0
FB_CLK
FB_AD[19:16]
ADDR[19:16]
Mux’d Bus
FB_AD[15:0]
ADDR[15:0]
DATA[15:0]
FB_R/W
FB_ALE
FB_CSn, FB_OE
Figure 18-13. Single Word-Read Transfer
Figure 18-14 shows the similar configuration for a write transfer. The data is driven from the second clock
on FB_AD[15:0].
NOTE
In non-multiplexed mode, the Mini-FlexBus does not support connection to
a 16-bit device.
MCF51MM256 Series Devices Reference Manual, Rev. 3
18-16
Freescale Semiconductor
Mini-FlexBus
S0
S1
S2
S3
S0
FB_CLK
FB_AD[19:16]
ADDR[19:16]
Mux’d Bus
FB_AD[15:0]
ADDR[15:0]
DATA[15:0]
FB_R/W
FB_ALE
FB_CSn
FB_OE
Figure 18-14. Single Word-Write Transfer
18.4.6.4
Timing Variations
The Mini-FlexBus module has several features that can change the timing characteristics of a basic reador write-bus cycle to provide additional address setup, address hold, and time for a device to provide or
latch data.
18.4.6.4.1
Wait States
Wait states can be inserted before each beat of a transfer by programming the CSCRn registers. Wait states
can give the peripheral or memory more time to return read data or sample write data.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
18-17
Mini-FlexBus
Figure 18-15 and Figure 18-16 show the basic read and write bus cycles (also shown in Figure 18-8 and
Figure 18-13) with the default of no wait states.
S0
S1
S2
S3
S0
FB_CLK
FB_AD[19:X+1]
ADDR[19:X+1]
Mux’d Bus
FB_AD[X:0]
ADDR[X:0]
FB_A[19:0]
DATA
ADDR[19:0]
Non-Mux’d Bus
FB_D[7:0]
DATA
FB_R/W
FB_ALE
FB_CSn, FB_OE
Figure 18-15. Basic Read-Bus Cycle (No Wait States)
S0
S1
S2
S3
S0
FB_CLK
ADDR[19:X+1]
FB_AD[19:X+1]
Mux’d Bus
FB_AD[X:0]
FB_A[19:0]
ADDR[X:0]
DATA
ADDR[19:0]
Non-Mux’d Bus
FB_D[7:0]
DATA
FB_R/W
FB_ALE
FB_CSn
FB_OE
Figure 18-16. Basic Write-Bus Cycle (No Wait States)
MCF51MM256 Series Devices Reference Manual, Rev. 3
18-18
Freescale Semiconductor
Mini-FlexBus
If wait states are used, the S1 state repeats continuously until the the chip-select auto-acknowledge unit
asserts internal transfer acknowledge. Figure 18-17 and Figure 18-18 show a read and write cycle with one
wait state.
S0
S1
WS
S2
S3
S0
FB_CLK
FB_AD[19:X+1]
ADDR[19:X+1]
Mux’d Bus
FB_AD[X:0]
ADDR[X:0]
DATA
FB_A[19:0]
ADDR[19:0]
Non-Mux’d Bus
FB_D[7:0]
DATA
FB_R/W
FB_ALE
FB_CSn, FB_OE
Figure 18-17. Read-Bus Cycle (One Wait State)
S0
S1
WS
S2
S3
S0
FB_CLK
FB_AD[19:X+1]
ADDR[19:X+1]
Mux’d Bus
FB_AD[X:0]
FB_A[19:0]
ADDR[X:0]
DATA
ADDR[19:0]
Non-Mux’d Bus
FB_D[7:0]
DATA
FB_R/W
FB_ALE
FB_CSn
FB_OE
Figure 18-18. Write-Bus Cycle (One Wait State)
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
18-19
Mini-FlexBus
18.4.6.4.2
Address Setup and Hold
The timing of the assertion and negation of the chip selects, byte selects, and output enable can be
programmed on a chip-select basis. Each chip-select can be programmed to assert one to four clocks after
address-latch enable (FB_ALE) is asserted. Figure 18-19 and Figure 18-20 show read- and write-bus
cycles with two clocks of address setup.
S0
AS
S1
S2
S3
S0
FB_CLK
FB_AD[19:X+1]
ADDR[19:X+1]
Mux’d Bus
ADDR[X:0]
FB_AD[X:0]
DATA
FB_A[19:0]
ADDR[19:0]
Non-Mux’d Bus
FB_D[7:0]
DATA
FB_R/W
FB_ALE
FB_CSn, FB_OE
Figure 18-19. Read-Bus Cycle with Two-Clock Address Setup (No Wait States)
S0
AS
S1
S2
S3
S0
FB_CLK
FB_AD[19:X+1]
ADDR[19:X+1]
Mux’d Bus
FB_AD[X:0]
FB_A[19:0]
DATA
ADDR[X:0]
ADDR[19:0]
Non-Mux’d Bus
FB_D[7:0]
DATA
FB_R/W
FB_ALE
FB_CSn
FB_OE
Figure 18-20. Write-Bus Cycle with Two Clock Address Setup (No Wait States)
MCF51MM256 Series Devices Reference Manual, Rev. 3
18-20
Freescale Semiconductor
Mini-FlexBus
In addition to address setup, a programmable address hold option for each chip select exists. Address and
attributes can be held one to four clocks after chip-select, byte-selects, and output-enable negate.
Figure 18-21 and Figure 18-22 show read and write bus cycles with two clocks of address hold.
S0
S1
S2
AH
S3
S0
FB_CLK
FB_AD[19:8]
ADDR[19:8]
Mux’d Bus
FB_AD[X:0]
ADDR[X:0]
DATA
FB_A[19:0]
ADDR[19:8]
FB_D[7:0]
DATA
Non-Mux’d Bus
FB_R/W
FB_ALE
FB_CSn, FB_OE
Figure 18-21. Read Cycle with Two-Clock Address Hold (No Wait States)
S0
S1
S2
AH
S3
S0
FB_CLK
FB_AD[19:X+1]
ADDR[19:X+1]
Mux’d Bus
FB_AD[X:0]
FB_A[19:0]
ADDR[X:0]
DATA
ADDR[19:0]
Non-Mux’d Bus
FB_D[7:0]
DATA
FB_R/W
FB_ALE
FB_CSn
FB_OE
Figure 18-22. Write Cycle with Two-Clock Address Hold (No Wait States)
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
18-21
Mini-FlexBus
Figure 18-23 shows a bus cycle using address setup, wait states, and address hold.
S0
AS
S1
WS
S2
AH
S3
S0
FB_CLK
FB_AD[19:X+1]
ADDR[19:X+1]
Mux’d Bus
FB_AD[X:0]
FB_A[19:0]
ADDR[X:0]
DATA
ADDR[19:0]
Non-Mux’d Bus
FB_D[7:0]
DATA
FB_R/W
FB_ALE
FB_CSn
FB_OE
Figure 18-23. Write Cycle with Two-Clock Address Setup and
Two-Clock Hold (One Wait State)
18.4.7
Bus Errors
There are certain accesses to the Mini-FlexBus that cause the system bus to hang. It is important to have
a good access-error handler to manage these conditions.
One such access is if CSCRn[AA] is cleared, the system hangs. Four other types of accesses cause the
access to terminate with a bus error.
• Mini-Flexbus module disabled using the platform peripheral power management control.
Mini-FlexBus accesses cause an error termination on the bus and prohibit the access to the
Mini-FlexBus.
• Attempted writes to space defined as write protected (CSMRn[WP] is set) are terminated with an
error response and the access is inhibited to the Mini-FlexBus.
• Mini-FlexBus access not hitting in either chip select region is terminated with an error response
and the access is inhibited to the Mini-FlexBus.
• Mini-FlexBus access hitting in both chip select regions is terminated with an error response and
the access is inhibited to the Mini-FlexBus
MCF51MM256 Series Devices Reference Manual, Rev. 3
18-22
Freescale Semiconductor
Chapter 19
General Purpose Operational Amplifier (OPAMP)
19.1
Introduction
The general purpose amplifier (OPAMP) block is a CMOS single supply, low input offset voltage, low
input offset and bias current amplifier that is designed for low-voltage, low-power operation over an input
voltage range of 1.8 V to 3.6 V. The OPAMP also has several timing and control settings that can be
software configured depending on the applications requirements. Timing and control consists of registers
and control logic for:
• Amplifier gain programmable
• Operation in low-power modes
The devices contain two OPAMP modules. These modules can be configured to perform many different
OPAMP configurations. The output of the OPAMP modules can be routed to the ADC for signal analysis.
Figure 19-1 shows the block diagram with the OPAMP highlighted.
19.1.1
OPAMP Clock Gating
The bus clock to the OPAMPx can be gated on and off using the OPAMPx bit in SCGC3. These bits are
set after any reset, which enables the bus clock to this module. To conserve power, these bits can be cleared
to disable the clock to this module when not in use. See Section 5.6, “Peripheral Clock Gating,” for details.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
19-1
General Purpose Operational Amplifier (OPAMP)
Figure 19-1. Block Diagram with the OPAMP Module Highlighted
MCF51MM256 Series Devices Reference Manual, Rev. 3
19-2
Freescale Semiconductor
General Purpose Operational Amplifier (OPAMP)
19.1.2
Features
The General Purpose Operational Amplifier (OPAMP) module features include:
• 1.8 V-3.6 V VDD operation
• Programmable voltage gain
• On-chip generation of bias voltages
• Low-power, low-voltage CMOS technology
• Low-input offset voltage1
• Low-input offset current1
• Low-input bias current1
• Low-current consumption1
19.1.3
Modes of Operation
The OPAMP module supports the following operation modes
• STOP2 — is disabled and not powered.
• STOP3 — is disabled and not powered when GAMPEN is low.
• WAIT — is disabled and not powered when GAMPEN is low.
1. Please refer to data sheet for latest characterization data.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
19-3
General Purpose Operational Amplifier (OPAMP)
19.1.4
Block Diagram
Figure 19-2 is a block diagram of the OPAMP module.
AMPNSEL[2:0]
AMPRF[2:0]
vo
INPx-
MUX
1R
1R
2R
2R
3R
4R
Rf101
Rf100
MUX
DAC5BIT
Rf011
floating
Reserved
Rf001
gpamp
OUT2
Rf010
OUT1
4R
Rin01
Rin00
gpamp
VDD
buffer
DAC12BIT
MUX
AMPRI[1:0]
INPx+
OUT1
OUT2
VINN
DAC5BIT
–
AMP
MUX
Reserved
VINP
+
DAC12BIT
ACMP
ADC
VOUT
VDD
PAD
AMPPSEL[2:0]
Figure 19-2. OPAMP Block Diagram
Table 19-1. Signal Properties
MODE1
MODE0
AMPRI[1:0] AMPRF[2:0]
Buffer
gpamp
Gain
Function
0
0
xx
xxx
1
0
—
Buffer Mode
1
0
xx
xxx
0
1
—
General Amplifier Mode
0
1
00
000
x
x
—
Inverting PGA Mode
0
1
00
001
x
x
3
Inverting PGA Mode
0
1
00
010
x
x
5
Inverting PGA Mode
0
1
00
011
x
x
8
Inverting PGA Mode
0
1
00
100
x
x
12
Inverting PGA Mode
0
1
00
101
x
x
16
Inverting PGA Mode
0
1
00
110
x
x
—
Inverting PGA Mode
0
1
00
111
x
x
—
Inverting PGA Mode
0
1
01
000
x
x
—
Inverting PGA Mode
0
1
01
001
x
x
1
Inverting PGA Mode
MCF51MM256 Series Devices Reference Manual, Rev. 3
19-4
Freescale Semiconductor
General Purpose Operational Amplifier (OPAMP)
Table 19-1. Signal Properties (Continued)
MODE1
MODE0
Buffer
gpamp
Gain
Function
0
1
01
010
x
x
2
Inverting PGA Mode
0
1
01
011
x
x
7/2
Inverting PGA Mode
0
1
01
100
x
x
11/2
Inverting PGA Mode
0
1
01
101
x
x
15/2
Inverting PGA Mode
0
1
01
110
x
x
—
Inverting PGA Mode
0
1
01
111
x
x
—
Inverting PGA Mode
1
1
00
000
x
x
—
Non-inverting PGA Mode
1
1
00
001
x
x
4
Non-inverting PGA Mode
1
1
00
010
x
x
6
Non-inverting PGA Mode
1
1
00
011
x
x
9
Non-inverting PGA Mode
1
1
00
100
x
x
13
Non-inverting PGA Mode
1
1
00
101
x
x
17
Non-inverting PGA Mode
1
1
00
110
x
x
—
Non-inverting PGA Mode
1
1
00
111
x
x
—
Non-inverting PGA Mode
1
1
01
000
x
x
—
Non-inverting PGA Mode
1
1
01
001
x
x
2
Non-inverting PGA Mode
1
1
01
010
x
x
3
Non-inverting PGA Mode
1
1
01
011
x
x
9/2
Non-inverting PGA Mode
1
1
01
100
x
x
13/2
Non-inverting PGA Mode
1
1
01
101
x
x
17/2
Non-inverting PGA Mode
1
1
01
110
x
x
—
Non-inverting PGA Mode
1
1
01
111
x
x
—
Non-inverting PGA Mode
19.2
AMPRI[1:0] AMPRF[2:0]
Signal Description
Table 19-2. Signal Properties
1
Name
Direction
Source/
Destination
INPx-
INPUT
PAD
Amplifier negative input terminal — This is an analog input
terminal. The leakage and offset current of the pad should be
significantly small.1
INPx+
INPUT
PAD
Amplifier positive input terminal — This is an analog input
terminal. The leakage and offset current of the pad should be
significantly small.1
VOUTx
OUTPUT
PAD
Amplifier output terminal — This is an analog output terminal.
Description
See the Data Sheet for the value of input offset current and input bias current.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
19-5
General Purpose Operational Amplifier (OPAMP)
19.3
Memory Map and Registers
This section provides a detailed description of all memory and registers.
19.3.1
Module Memory Map
The memory map for the OPAMP module is given in Table 19-3. The address listed for each register is the
address offset. The total address for each register is the sum of the base address for the OPAMP module
and the address offset for each register.
Table 19-3. Module Memory Map
19.3.2
Address
Use
Access
0x00
GPAMP Control Register 0 (GPAMPxC0)
Read/Write
0x01
GPAMP Control Register 1 (GPAMPxC1)
Read/Write
0x02
GPAMP Control Register 2 (GPAMPxC2)
Read/Write
Register Descriptions
This section consists of register descriptions. Each description includes a standard register diagram.
Details of register bit and field function follow the register diagrams, in bit order.
19.3.2.1
GPAMP Control Register 0 (GPAMPxC0)
7
6
GPAMPEN
0
5
4
3
2
1
0
LPEN
MODE1
MODE0
0
0
0
R
W
Reset
Figure 19-3. GPAMP Control Register 0 (GPAMPxC0)
Table 19-4. GPAMPxC0 Field Descriptions
Field
Description
7
GPAMPEN
OPAMP Enable — The GPAMPEN bit enables General Purpose Operational Amplifier.
0 The OPAMP is disabled and not powered. This mode of operation is available in any of the modes the MCU
operates.
1 OPAMP is enabled. In this mode the amplifier is powered and enabled. This mode of operation is available
when the MCU is in modes other than Stop1 and Stop2 mode.
6
LPEN
Low-Power Mode Enable
0 The OPAMP is working in high-speed mode.
1 The OPAMP is working in low-power mode.
MCF51MM256 Series Devices Reference Manual, Rev. 3
19-6
Freescale Semiconductor
General Purpose Operational Amplifier (OPAMP)
Table 19-4. GPAMPxC0 Field Descriptions (Continued)
Field
5:2
1:0
MODE
19.3.2.2
Description
Reserved
PGA Gain Setting — Selects the OPAMP gain.
00 Buffer
10 General purpose
01 Inverting PGA
11 Non-inverting PGA
GPAMP Control Register 1 (GPAMPxC1)
7
6
5
4
3
2
1
0
AMPRF2
AMPRF1
AMPRF0
AMPRI1
AMPRI0
0
0
0
0
0
2
1
0
R
W
Reset
Figure 19-4. GPAMP Control Register 1 (GPAMPxC1)
Table 19-5. GPAMPxC1 Field Descriptions
Field
7:5
Description
Reserved
4:2
AMPRF
OPAMP Gains Selector
see Table 19-1
1:0
AMPR
OPAMP Gains Selector
see Table 19-1
19.3.2.3
GPAMP Control Register 2 (GPAMPxC2)
7
6
5
4
3
AMPPSEL2
AMPPSEL1
AMPPSEL0
AMPNSEL2
AMPNSEL1
AMPNSEL0
0
0
0
0
0
0
R
W
Reset
Figure 19-5. GPAMP Control Register 2 (GPAMPxC2)
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
19-7
General Purpose Operational Amplifier (OPAMP)
Table 19-6. GPAMPxC2 Field Descriptions
Field
Description
7
Reserved
6–4
AMPPSEL
3
Reserved
2–0
AMPNSEL
19.4
Amplifier Positive Input Terminal Selector
000 INPx+
001 OUT1
010 OUT2
011 Reserved
100 DAC5BIT
101 DAC12BIT
110 VDD
111 GND
Amplifier Negative Input Terminal Selector
000 INPx001 OUT1
010 OUT2
011 Reserved
100 DAC5BIT
101 DAC12BIT
110 VDD
111 GND
Functional Description
This section provides a complete functional description of the General Purpose Operational Amplifier
(OPAMP) block, detailing the operation of the design from the end-user perspective.
MCF51MM256 Series Devices Reference Manual, Rev. 3
19-8
Freescale Semiconductor
General Purpose Operational Amplifier (OPAMP)
19.4.1
OPAMP Configuration
The following is a block diagram of the OPAMP module in general purpose mode.
AMPNSEL[2:0]
AMPRF[2:0]
vo
INPx-
MUX
DAC5BIT
1R
1R
2R
2R
3R
4R
Rf101
Rf100
Rf011
Rf010
floating
MUX
Reserved
Rf001
OUT2
gpamp
OUT1
4R
AMPRI[1:0]
buffer
Rin01
gpamp
VDD
Rin00
DAC12BIT
MUX
INPx+
OUT1
OUT2
DAC5BIT
VINN
MUX
Reserved
DAC12BIT
–
AMP
VINP
+
ACMP
ADC
VOUT
VDD
PAD
AMPPSEL[2:0]
Figure 19-6. Operational Amplifier (OPAMP) Block Diagram in General Purpose Mode
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
19-9
General Purpose Operational Amplifier (OPAMP)
19.4.2
Buffer Configuration
The following is a block diagram of the OPAMP module in buffer configuration mode.
AMPNSEL[2:0]
AMPRF[2:0]
INPx-
MUX
DAC5BIT
1R
1R
2R
2R
3R
4R
Rf101
Rf100
Rf011
Rf010
floating
MUX
Reserved
Rf001
OUT2
gpamp
OUT1
4R
AMPRI[1:0]
buffer
Rin01
gpamp
VDD
Rin00
DAC12BIT
MUX
INPx+
OUT1
OUT2
DAC5BIT
VINN
MUX
Reserved
DAC12BIT
–
AMP
VINP
+
ACMP
ADC
VOUT
VDD
PAD
AMPPSEL[2:0]
Figure 19-7. Operational Amplifier (OPAMP) Block Diagram in Buffered Configuration Mode
MCF51MM256 Series Devices Reference Manual, Rev. 3
19-10
Freescale Semiconductor
General Purpose Operational Amplifier (OPAMP)
19.4.3
Inverting PGA Configuration
The following is a block diagram of the OPAMP module in inverting PGA configuration.
AMPNSEL
AMPRF[2:0]
INPx-
MUX
DAC5BIT
1R
1R
2R
2R
3R
4R
Rf101
Rf100
Rf011
Rf010
floating
MUX
Reserved
Rf001
OUT2
gpamp
OUT1
4R
AMPRI[1:0]
buffer
Rin01
gpamp
VDD
Rin00
DAC12BIT
MUX
INPx+
OUT1
OUT2
DAC5BIT
VINN
MUX
Reserved
DAC12BIT
–
AMP
VINP
+
ACMP
ADC
VOUT
VDD
AMPPSEL
PAD
Note: AMPPSEL must be set to select GND
Figure 19-8. Operational Amplifier (OPAMP) Block Diagram in Inverting PGA Mode
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
19-11
General Purpose Operational Amplifier (OPAMP)
19.4.4
Non-Inverting PGA Configuration
The following is a block diagram of the OPAMP module in non-inverting PGA configuration.
AMPNSEL[2:0]
AMPRF[2:0]
INPx-
MUX
DAC5BIT
1R
1R
2R
2R
3R
4R
Rf101
Rf100
Rf011
Rf010
floating
MUX
Reserved
Rf001
OUT2
gpamp
OUT1
4R
AMPRI[1:0]
buffer
Rin01
gpamp
VDD
Rin00
DAC12BIT
MUX
INPx+
OUT1
OUT2
DAC5BIT
VINN
MUX
Reserved
DAC12BIT
–
AMP
VINP
+
ACMP
ADC
VOUT
VDD
AMPPSEL
PAD
Note: AMPNSEL must be set to select GND
Figure 19-9. Operational Amplifier (OPAMP) Block Diagram in Non-Inverting PGA Mode
MCF51MM256 Series Devices Reference Manual, Rev. 3
19-12
Freescale Semiconductor
Chapter 20
Programmable Delay Block (PDB)
20.1
Introduction
The Programmable Delay Block (PDB) is a key component in the measurement engine. This simple timer
is used to control the hardware triggering of the ADC and the DAC so that precise timing between DAC
updates and ADC conversions can be achieved.
NOTE
This device has eight (8) PDB channels where n is mentioned as 0 to 7 in
this chapter. However, the corresponding PDBDLYn registers are labeled as
PDBDLYA to PDBDLYH in the memory map.
20.1.1
Overview
Many applications need to synchronize the time at which multiple ADC samples are taken with respect to
an external trigger or event. The Programmable Delay Block provides controllable delays from either an
external trigger or a programmable interval tick to the sample trigger input of one or more ADCs. The PDB
also can generate a hardware trigger to the DAC. This signal can be used to advance the DAC Buffer
pointer in order to change sensor biasing while ADC conversions are being triggered.
20.1.2
PDB Trigger Inputs
The PDB on these devices has three input trigger sources that initiate the PDB operation. The three sources
are:
• ACMP output (ACMPO)
• ADC flag ADCSC1A_COCO
• Software
To select the input trigger source, set the TRIGSEL bits in the PDBC1 register as described in the
following table.
Table 20-1. Selecting the PDB Input Trigger Source
Input Trigger Source
PDBC1 Register Value for
TRIGSEL bits
Connected to
ACMPO
0b001
TRIGGERIN1
ADCSC1A_COCO
0b000
TRIGGERIN0
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
20-1
Programmable Delay Block (PDB)
Table 20-1. Selecting the PDB Input Trigger Source
20.2
Input Trigger Source
PDBC1 Register Value for
TRIGSEL bits
Connected to
Software Trigger
0b111
—
ADC Hardware Triggers and Selects
The following table explains the ADHWT and ADHWTSn source as referenced in the ADC chapter.
Table 20-2. ADC Hardware Triggers and Selects
PDB Pre-Trigger
Conversion
ADHWT
This triggers the ADC conversion.
PDB Pre-Trigger 0
ADHWTSA
This selects ADCSC1A.
PDB Pre-Trigger 1
ADHWTSB
This selects ADCSC1B.
PDB Pre-Trigger 2
ADHWTSC
This selects ADCSC1C.
PDB Pre-Trigger 3
ADHWTSD
This selects ADCSC1D.
PDB Pre-Trigger 4
ADHWTSE
This selects ADCSC1E.
PDB Pre-Trigger 5
ADHWTSF
This selects ADCSC1F.
PDB Pre-Trigger 6
ADHWTSG
This selects ADCSC1G.
PDB Pre-Trigger 7
ADHWTSH
This selects ADCSC1H.
PDB Trigger 0
20.2.1
Trigger/Select
PDB Trigger Acknowledgement Inputs
The PDB Trigger Acknowledgement inputs in back-to-back operation mode are connected to the
ADCSC1n_COCO flag. ADCSC1B_COCO to ADCSC1H_COCO acknowledge PDB channel 1 to 7
respectively.
MCF51MM256 Series Devices Reference Manual, Rev. 3
20-2
Freescale Semiconductor
Programmable Delay Block (PDB)
Figure 20-1. Block Diagram with the PDB Module Highlighted
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
20-3
Programmable Delay Block (PDB)
20.2.2
•
•
•
•
•
•
•
•
•
Features
Eight channels
— Each channel supplies a single trigger output event
— Each trigger output is independently enabled and individually controlled
— Each channel can be triggered from a programmed delay or from previous channel
acknowledgment
All channel trigger outputs can be ORed together to schedule multiple conversions from one input
trigger event
Prescaler options to support divided-by-1 up to divided-by-2560
DAC Trigger Interval Register (16-bit) that is used to place the interval count between DAC
hardware trigger output signals
Multiple sources for PDB input triggering
— Single software trigger input
— Up to 7 trigger inputs from either on-chip or off-chip sources
Positive transition of trigger_in will initiate the PDB primary counter
Continuous trigger or single shot mode supported
Bypass mode supported
One programmable interrupt
20.2.3
Modes of Operation
Modes of operation include:
Disabled
Counter is off and all trigger outputs are low.
Enabled OneShot
Counter is enabled and restarted at count zero upon receiving a positive edge on
the trigger input. Each Trigger output asserts once per input trigger.
Enabled Continuous Counter is enabled and restarted at count zero. The counter will be rolled over to
zero again when the count reaches the value specified in the MOD internal buffer,
and counting restarts. This enables a continuous stream of triggers out as a result
of a single trigger input.
Enabled Back-to-BackThe PDB trigger logic initiates triggers based on the Triggern acknowledgment
detect signal. This signal comes from the conversion complete flag of the
ADCSCn. With this configuration, ADC conversions can occur back to back.
Enabled Bypassed
The input trigger bypasses the PDB logic entirely. It is possible to bypass all or
only one of the trigger outputs; Therefore this mode can be used in conjunction
with any of the above.
•
NOTE
For all of the Enabled modes, if the DAC hardware trigger output is
enabled each time the count reaches the DAC interval count value, a
trigger signal is sent to the DAC.
MCF51MM256 Series Devices Reference Manual, Rev. 3
20-4
Freescale Semiconductor
Programmable Delay Block (PDB)
•
In Enabled OneShot and Enabled Continuous modes, the outputs of the
channel comparators can be combined in such a way that all the ADC
events can be triggered from a single input event. These are referred to
as AllShot and Continuous AllShot modes.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
20-5
Programmable Delay Block (PDB)
20.2.4
Block Diagram
(not used)
BB0 (not used- force to 0)
TOS
1
CH0DELAY
PDBDLY0H
Trigger0
F2
=
0
F1
PDBDLY0L
Pre-Trigger0
Trigger0 Ack
Trigger0
Ack Detect
PDB Channel 0
BB1
TOS
1
CH1DELAY
PDBDLY1H
Trigger1
F2
=
0
F1
PDBDLY1L
Pre-Trigger1
Trigger1 Ack
Trigger1
Ack Detect
PDB Channel 1
....
....
....
....
BBn
Triggern
F2
=
PDBDLYnH
TOS
1
CHnDELAY
F1
0
PDBDLYnL
Pre-Triggern
Triggern
Ack Detect
PDB Channel n
Triggern Ack
(not used)
DACINTH:DACINTL
DAC Trigger
=
DAC COUNT
F3
CountReset
PDBMODH PDBMODL
=
PRESCALER
Counter
PDBCNTH
CONT
PDBCNTL
count complete
Control Logic
IDELAY
TRIGSEL
TriggerIn0
TriggerIn1
TriggerIn2
TriggerIn3
TriggerIn4
TriggerIn5
TriggerIn6
SWTRIG
....
Pre-Triggern
Pre-Trigger0
Pre-Trigger1
Modulus
PDBIDLYH PDBIDLYL
=
Interrupt
Logic
IE
Figure 20-2. PDB Block Diagram
MCF51MM256 Series Devices Reference Manual, Rev. 3
20-6
Freescale Semiconductor
Programmable Delay Block (PDB)
Figure 20-2. illustrates the basic structure of the PDB block. It contains a primary counter whose output is
compared against several different digital values.
Each channel output delay (PDBDLYnH:L) determines the time between assertion of the trigger input
(software or hardware trigger) to the point at which the associated ADC trigger output signals are
generated. These times are defined as:
• Trigger input to Pre-Triggern = (PRESCALER x PDBDLYnH:L) + 1 peripheral bus clock cycle
• Add one additional peripheral bus clock cycle to determine the time at which the trigger output
pulses for 1 peripheral bus clock cycle.
Pre-Trigger outputs are used to precondition interfacing logic one peripheral bus clock period prior to the
actual event trigger. When interfacing to ADC blocks with multiple control and result registers,
Pre-Trigger outputs provide select control for these registers, allowing them to operate in a ping-pong
fashion, sequencing through conversions between multiple analog sources without reconfiguration of the
ADC.
The signals shown in Figure 20-3. would be used to operate the ADC to sample signal A and sample single
B in OneShot mode. The trigger delays for the ADC are independently set via the Delay 0 and Delay 1
parameters placed in the PDBDLYnH:L. The PDB input trigger signal from a separate module or software
can initiate the PDB to trigger the ADC twice with two different delays. But the time between Trigger0
and Trigger1 must be longer than the ADC conversion time, then the second trigger signal can take effect.
NOTE
PDB timing for trigger input to Pre-Triggern = (PRESCALER x
PDBDLYnH:L) + 1 peripheral bus clock cycle. Add one additional
peripheral bus clock cycle to determine the time at which the trigger output
pulses for 1 peripheral bus clock cycle.
PDB trigger input
Pre-Trigger0
Trigger0
Delay 0
Delay 1
Pre-Trigger1
Trigger1
Figure 20-3. Decoupled Channel Trigger Generation
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
20-7
Programmable Delay Block (PDB)
The third digital value, modulus, resets the counter to zero at the end of the count. If the CONT bit in the
PDBC1 is set, the counter resumes a new count. Otherwise, the timer operation will cease until the next
trigger input event occurs.
The DAC Interval Register (DACINTH:L) determines the time between DAC hardware trigger pulses. If
the DAC trigger output is enabled (DACTOE is set) each time the PDB counter register increments the
number of counts placed in the DACINTH:L registers, the PDB will output a DAC trigger pulse.
Together the DAC trigger pulse and the ADC trigger pulses allow precise timing of DAC updates and ADC
measurements.
The following 16-bit registers impact PDB operation:
• Channel Delay register (PDBDLYnH:L)
• Modulus register (PDBMODH:L)
• Interrupt Delay register (PDBIDLYH:L)
• DAC Trigger Interval register (DACINTH:L)
Like all 16-bit registers, these internal registers are buffered and any values written to them are written first
to their buffer registers. The circumstances that cause these registers to be updated with the values from
their buffer registers are summarized in the following table according to the current operation mode.
Table 20-3. Updating the registers that impact PDB operation
PDBSC Register
Operation Mode
Value Updates
LDOK bit
LDMOD bit
Any mode
Write 1
0
Immediately after
write 1 to LDOK.
Continuous
Write 1
1
Immediately after
counter rolls over.
OneShot
Write 1
1
Immediately after
trigger signal
received.
Values written to any of these registers after a logic 1 is written to the LDOK bit, are ignored and the
associated buffer register is not updated until the existing values in the buffer registers are loaded into the
internal registers. Read the LDOK bit to determine if the values in buffer registers have been loaded into
internal registers and have taken effect.
The PDB 16-bit counter operates on up count mode. The two read-only counter registers contain the high
and low bytes of the value in the PDB counter. Reading either byte latches the contents of both bytes into
a buffer where they remain latched until another read of either bytes is performed. Odd-numbered reads
return new data from the counter. Even-numbered reads return latched data.
The following figures are examples of the LDMOD bit effects. The PDB Counter is configured in
continuous mode where it repeats counting up and rolling over to 0 after matching a fixed PDB Modulus
(PDBMOD) register value. The black arrows represent Pre-Triggers based on previous PDB delay
registers value. The red arrows represent Pre-Triggers based on new effective PDB delay registers value.
MCF51MM256 Series Devices Reference Manual, Rev. 3
20-8
Freescale Semiconductor
Programmable Delay Block (PDB)
Symbol

Description
Attempts to write a new value to PDB delay (PDBDLY) registers.

Pre-Triggers based on previous PDB delay registers value.

Pre-Triggers based on new effective PDB delay registers value.

Pre-Triggers are asserted when the PDB Counter reaches the corresponding effective PDBDLY value.
Figure 20-4. Registers Update with LDMOD bit = 0 in Continuous Mode
In Figure 20-4, new values for PDBDLY registers do not become effective until after the LDOK is written
to 1. The new values become effective immediately after LDOK is written to 1.
Symbol

Description
Attempts to write a new value to PDB delay (PDBDLY) registers.

Pre-Triggers based on previous PDB delay registers value.

Pre-Triggers based on new effective PDB delay registers value.

Pre-Triggers are asserted when the PDB Counter reaches the corresponding effective PDBDLY value.
Figure 20-5. Registers Update with LDMODE Bit = 1 in Continuous Mode
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
20-9
Programmable Delay Block (PDB)
In Figure 20-5, new values for PDBDLY registers do not become effective until after the LDOK is written
to 1 and PDB Counter rolls over to 0. The LDOK bit is held at high until PDB Counter rolls over to 0. This
bit can be used to indicate when the new delay registers value become effective.
MCF51MM256 Series Devices Reference Manual, Rev. 3
20-10
Freescale Semiconductor
Programmable Delay Block (PDB)
20.3
Memory Map and Registers
20.3.1
Memory Map
Offset
Register
Description
0x00
PDBSC
PDB Status and Control Register
0x01
PDBC1
PDB Control Register 1
0x02
PDBC2
PDB Control Register 2
0x03
PDBCHEN
PDB Channel Enable
0x04
PDBMODH
PDB Modulus Register High
0x05
PDBMODL
PDB Modulus Register Low
0x06
PDBCNTH
PDB Counter Register High
0x07
PDBCNTL
PDB Counter Register Low
0x08
PDBIDLYH
PDB Interrupt Delay Register High
0x09
PDBIDLYL
PDB Interrupt Delay Register Low
0x0A
DACINTH
DAC Trigger Interval Register High
0x0B
DACINTL
DAC Trigger Interval Register Low
0x0C + (n x 2)
PDBDLYnH
PDB Delay n Register High
0x0D + (n x 2)
PDBDLYnL
PDB Delay n Register Low
Note: This device has eight (8) PDB channels where n is mentioned as 0 to 7 in this chapter. However, the
corresponding PDBDLYn registers are labeled as PDBDLYA to PDBDLYH in the memory map.
20.3.2
Registers Descriptions
20.3.2.1
PDB Status and Control Register (PDBSC)
This register contains status and control bits for the Programmable Delay Block.
R
W
RESET:
7
6
5
4
PDBEN
PDBIF
PDBIE
LDMOD
0
0
0
0
3
2
TOS
0
0
1
0
DACTOE
LDOK
0
0
= Reserved or unused
Figure 20-6. PDB Status and Control Register (PDBSC)
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
20-11
Programmable Delay Block (PDB)
Table 20-4. PDBSC Register Field Descriptions
Field
Description
7
PDBEN
PDB module Enable
0 Counter is off and all trigger signals are disabled.
1 Counter is enabled.
6
PDBIF
PDB Interrupt Flag
This bit is set when a successful compare of value of counter and the IDELAY internal buffer occurs. Clear this
bit by writing logic one to it.
5
PDBIE
PDB Interrupt Enable
0 Interrupt requests disabled
1 Interrupt requests enabled
4
LDMOD
Load Mode Select
0 Internal registers of PDBDLYnH:L, PDBMODH:L, PDBIDLYH:L and DACINTH:L are updated with values of
their buffer registers and take effect immediately after logic 1 is written into LDOK bit
1 Internal registers of PDBDLYnH:L, PDBMODH:L, PDBIDLYH:L, and DACINTH:L are updated with values of
their buffer registers and take effect when the counter rolls over in continuous mode or trigger signal is received
in one shot mode after logic 1 is written into LDOK bit
3:2
TOS
Trigger Output Select
00 Counter delay is bypassed
01 Trigger A is function of Channel A Delay only
10 Trigger n is OR function of all available channel outputs. This setting is required for back-to-back or multiple
channel delays operation.
11 Reserved
1
DACTOE
0
LDOK
DAC Trigger Output Enable
0 No DAC trigger output
1 DAC interval register defines the number of PDB counts between DAC trigger outputs.
Load OK — Writing logic 1 to this bit loads values in buffer registers of PDBDLYnH:L, PDBMODH:L, PDBIDLYH:L
and DACINTH:L into their internal registers. The internal delay registers, modulus value, interrupt delay and DAC
trigger interval value will take effect immediately if LDMOD = 0, or when the counter rolls over in continuous mode
or trigger signal is received in one shot mode if LDMOD = 1.
Any value written to any one of the above registers, after a logic 1 being written to LDOK bit, will be ignored and
buffer register will not be updated until the values in buffer registers are loaded into the internal registers. This bit
is cleared when the values in buffer registers are loaded into internal registers. Writing logic “0” to this bit has no
effect.
Reading this bit can determine if the values in buffer registers are loaded into internal registers and take effect.
MCF51MM256 Series Devices Reference Manual, Rev. 3
20-12
Freescale Semiconductor
Programmable Delay Block (PDB)
20.3.2.2
PDB Control Register 1 (PDBC1)
This register contains control bits for the Programmable Delay Block.
7
R
W
RESET:
6
5
4
3
PRESCALER
0
0
2
TRIGSEL
0
0
0
0
1
0
CONT
MULT
0
0
= Reserved or unused
Figure 20-7. PDB Control Register 1 (PDBC1)
Table 20-5. PDBC1 Register Field Descriptions
Field
Description
7:5
Clock Prescaler Select
PRESCALER 000 timer uses peripheral clock
001 timer uses peripheral clock / 2
010 timer uses peripheral clock / 4
011 timer uses peripheral clock / 8
100 timer uses peripheral clock / 16
101 timer uses peripheral clock / 32
110 timer uses peripheral clock / 64
111 timer uses peripheral clock / 128
4:2
TRIGSEL
Input Trigger Select
000 TriggerIn0 is ADCSC1A_COCO.
001 TriggerIn1 is ACMPO.
111 SWTRIG is selected.
1
CONT
Continuous Mode Enable
0 Module is in OneShot mode.
1 Module is in continuous mode.
0
MULT
Multiply Prescaler bit
0 Prescale factor is defined by the prescaler select bits.
1 Prescale factor is defined by the value selected by the prescaler bits multiplied by 20.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
20-13
Programmable Delay Block (PDB)
20.3.2.3
PDB Control Register 2 (PDBC2)
This register is used to enable each of the acknowledgment detect input for each of the channels.
R
W
RESET:
7
6
5
4
3
2
1
BB7
BB6
BB5
BB4
BB3
BB2
BB1
0
0
0
0
0
0
0
0
SWTRIG
0
= Reserved or unused
Figure 20-8. PDB Control Register (PDBC2)
Table 20-6. PDBC2 Register Field Descriptions
Field
Description
7:1
BB7-BB1
Back-to-Back Enable
0 Trigger acknowledge signals are not used
1 Trigger acknowledge signals are used to allow the next trigger to be set for back to back operation
0
SWTRIG
Software Trigger— When TRIGSEL = 3’b111 and the module is enabled, writing a one to this field triggers a
reset and restart of the counter.
MCF51MM256 Series Devices Reference Manual, Rev. 3
20-14
Freescale Semiconductor
Programmable Delay Block (PDB)
20.3.2.4
PDB Channel Enable Register (PDBCHEN)
This register is used to enable or disable each of the trigger outputs associated with channel 0 to 7.
R
W
RESET:
7
6
5
4
3
2
1
0
CHEN7
CHEN6
CHEN5
CHEN4
CHEN3
CHEN2
CHEN1
CHEN0
1
1
1
1
1
1
1
1
= Reserved or unused
Figure 20-9. PDB Channel Enable Register (PDBCHEN)
Table 20-7. PDBCHEN Register Field Descriptions
Field
Description
7:0
CHEN7 CHEN0
PDB channel enable bits
0 Channel n trigger outputs are disabled and held low.
1 Channel n trigger outputs are enabled.
NOTE
Only trigger 0 is used as the hardware trigger to the ADC, so channel 0
enable (CHEN0) must be set for the PDB to trigger ADC conversions. If
channel 0 enable (CHEN0) is cleared, any other PDB delays will not trigger
ADC conversions.
20.3.2.5
PDB Modulus Registers (PDBMODH:PDBMODL)
These registers specify the period of the counter in terms of peripheral bus clock cycles. When the counter
reaches this value, it will be reset back to all zeroes. If the PDBCS_CONT is set, the count will begin anew.
Reads of these registers will return the value of internal registers that is taking affect for the current period
of the PDB.
7
R
W
RESET:
6
5
4
3
2
1
0
1
1
1
1
MOD[15:8]
1
1
1
1
= Reserved or unused
Figure 20-10. PDB Modulus Register High (PDBMODH)
7
R
W
RESET:
6
5
4
3
2
1
0
1
1
1
1
MOD[7:0]
1
1
1
1
= Reserved or unused
Figure 20-11. PDB Modulus Register Low (PDBMODL)
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
20-15
Programmable Delay Block (PDB)
20.3.2.6
PDB Counter Registers (PDBCNTH:PDBCNTL)
This is a 16-bit counter which operates on up-count mode. The two read-only counter registers contain the
high and low bytes of the value in the PDB counter. Reading either byte latches the contents of both bytes
into a buffer where they remain latched until PDBCNTH or PDBCNTL is read.
R
W
RESET:
7
6
5
4
3
COUNT[15:8]
2
1
0
0
0
0
0
0
0
0
0
= Reserved or unused
Figure 20-12. PDB Counter Register High (PDBCNTH)
R
W
RESET:
7
6
5
4
3
COUNT[7:0]
2
1
0
0
0
0
0
0
0
0
0
= Reserved or unused
Figure 20-13. PDB Counter Register Low (PDBCNTL)
20.3.2.7
PDB Interrupt Delay Register (PDBIDLYH:PDBIDLYL)
These registers can be used to read and write the value to schedule the PDB interrupt. This feature can be
used to schedule an independent interrupt at some point in the PDB cycle. Reads of these registers return
the value of internal registers that is taking affect for the current period of the PDB.
7
R
W
RESET:
6
5
4
3
2
1
0
1
1
1
2
1
0
1
1
1
IDELAY[15:8]
1
1
1
1
1
= Reserved or unused
Figure 20-14. PDB Interrupt Delay Register High (PDBIDLYH)
7
R
W
RESET:
6
5
4
3
IDELAY[7:0]
1
1
1
1
1
= Reserved or unused
Figure 20-15. PDB Interrupt Delay Register Low (PDBIDLYL)
PDBSC_IE must be set in order for an interrupt to be issued as a result of the count value equaling
IDELAY. However, PDBSC_IF is set whenever the count value equals IDELAY.
20.3.2.8
DAC Interval Registers (DACINTH:DACINTL)
These registers specify the time between DAC hardware trigger pulses. If the DAC trigger output is
enabled (DACTOE) each time the PDB counter register increments the number of counts placed in the
MCF51MM256 Series Devices Reference Manual, Rev. 3
20-16
Freescale Semiconductor
Programmable Delay Block (PDB)
DACINTH:L registers, the PDB outputs a DAC trigger pulse. Reads of these registers return the value of
internal registers that is taking affect for the current period of the PDB.
7
R
W
RESET:
6
5
4
3
2
1
0
0
0
0
2
1
0
0
0
0
DACINT[15:8]
0
0
0
0
0
= Reserved or unused
Figure 20-16. DAC Interval Register High (DACINTH)
7
R
W
RESET:
6
5
4
3
DACINT[7:0]
0
0
0
0
0
= Reserved or unused
Figure 20-17. DAC Interval Register Low (DACINTL)
20.3.2.9
PDB Delay Registers (PDBDLYnH:PDBDLYnL)
These registers are used to specify the delay from assertion of TriggerIn to assertion of the Trigger outputs.
The delay is only applicable if the module is enabled and the associated output trigger has not been
bypassed. The delay is in terms of peripheral clock cycles. Reads of these registers will return the value of
internal registers that is taking affect for the current period of the PDB.
NOTE
When PDB channel delays are used as the trigger of the ADC conversion,
the application code must ensure that the interval of the delay is longer than
the ADC conversion time so that the ADC conversion results are properly
handled and loaded to each of the result registers and that the CHEN0 bit is
set to allow channel delays other than channel delay 0 to trigger the ADC
coversions.
7
R
W
RESET:
6
5
4
3
2
1
0
0
0
0
2
1
0
0
0
0
DELAY[15:8]
0
0
0
0
0
= Reserved or unused
Figure 20-18. PDB Delay n Register High (PDBDLYnH)
7
R
W
RESET:
6
5
4
3
DELAY[7:0]
0
0
0
0
0
= Reserved or unused
Figure 20-19. PDB Delay n Register Low (PDBDLYnL)
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
20-17
Programmable Delay Block (PDB)
20.3.3
Functional Description
20.3.3.1
Impact of Using the Prescaler on Timing Resolution
Use of prescalers greater than 1 limit the count/delay accuracy in terms of peripheral clock cycles (to the
modulus of the prescaler value). If the prescaler is set to div 2, then the only values of total peripheral
clocks that can be detected are even values; if div is set to 4, then the only values of total peripheral clocks
that can be decoded as detected are mod (4) and so forth. If the users want to set a really long delay value
and used div 128, then they would be limited to an resolution of 128 bus clocks.
Therefore, use the lowest possible prescaler for a given application.
20.4
Resets
This module has a single reset input, corresponding to the chip-wide peripheral reset. After reset, all
registers are set to their reset values.
20.5
Clocks
This module has a single clock input, the peripheral bus clock.
20.6
Interrupts
This module has one interrupt source. When a successful comparison of the counter value and the IDELAY
internal buffer occurs, the PDBIF is set. If the PDBIE is set, an interrupt is generated. Write a 1 to the
PDBIF bit to clear the interrupt.
MCF51MM256 Series Devices Reference Manual, Rev. 3
20-18
Freescale Semiconductor
Chapter 21
Serial Communication Interface (S08SCIV4)
21.1
Introduction
The SCI allows asynchronous serial communications with peripheral devices and other CPUs.
NOTE
Ignore any references to stop1 low-power mode in this chapter, because this
device does not support it.
For details on low-power mode operation, refer to Table 3-4 in Chapter 3,
“Modes of Operation”.
21.1.1
SCIx Clock Gating
The bus clock to the SCIx can be gated on and off using the SCIx bit in SCGC1. This bit is set after any
reset, which enables the bus clock to this module. To conserve power, the SCIx bit can be cleared to disable
the clock to this module when not in use. See Section 5.7.7, “System Clock Gating Control 1 Register
(SCGC1),” for details.
21.1.2
Module Configuration
The SCI1 and SCI2 module pins can be repositioned via software-control using SCIxPS in SOPT3 as
shown in Table 21-1 and Table 21-2. SCIxPS in SOPT3 selects which general-purpose I/O ports are
associated with SCI operation.
Table 21-1. SCI1 Position Options
SCI1PS in SOPT3
Port Pin for TX1
Port Pin for RX1
0 (default)
PTA1
PTA2
1
PTD6
PTD7
Table 21-2. SCI2 Position Options
SCI2PS in SOPT3
Port Pin for TX2
Port Pin for RX2
0 (default)
PTE5
PTE6
1
PTF2
PTF1
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
21-19
Serial Communication Interface (S08SCIV4)
21.1.3
Module Block Diagram
Figure 21-1 shows a block diagram of the SCIx module.
Figure 21-1. Block Diagram with the SCI Module highlighted
MCF51MM256 Series Devices Reference Manual, Rev. 3
21-20
Freescale Semiconductor
Serial Communication Interface (S08SCIV4)
21.1.4
Interfacing the SCIs to Off-Chip Opto-Isolators
SCI1 is designed with twice the normal I/O drive capability on the TX1 pin. The RX pin can either be fed
directly from the digital I/O buffer, or those signals can be pre-conditioned using the comparators as shown
in Figure 21-2 Similarly, the TX output can be modulated with the output of one of the timers before being
passed off chip.
SIMIPS[RX1IN]
Internal or external reference
-
+
analog
comparator
opto
RX1
isolator
RX
digital
buffer
SCI1
TX
0
opto
TX1
isolator
1
TPM Ch0 Output
TPM Ch1 Output
SIMIPS[MODTX1]
SIMIPS[MTBASE1]
On-Chip Components
Off-Chip Opto-Isolators
Figure 21-2. On-Chip Signal Conditioning Associated with SCI1 RX and TX Pins
Controls for the circuitry shown in Figure 21-2 are discussed in Section 5.7.13, “SIM Internal Peripheral
Select Register (SIMIPS).”
21.1.5
Features
Features of SCI module include:
• Full-duplex, standard non-return-to-zero (NRZ) format
• Double-buffered transmitter and receiver with separate enables
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
21-21
Serial Communication Interface (S08SCIV4)
•
•
•
•
•
•
•
Programmable baud rates (13-bit modulo divider)
Interrupt-driven or polled operation:
— Transmit data register empty and transmission complete
— Receive data register full
— Receive overrun, parity error, framing error, and noise error
— Idle receiver detect
— Active edge on receive pin
— Break detect supporting LIN
Hardware parity generation and checking
Programmable 8-bit or 9-bit character length
Receiver wakeup by idle-line or address-mark
Optional 13-bit break character generation / 11-bit break character detection
Selectable transmitter output polarity
21.1.6
Modes of Operation
See Section 21.3, “Functional Description,” for details concerning SCI operation in the following modes:
• 8- and 9-bit data modes
• Stop mode operation
• Loop mode
• Single-wire mode
MCF51MM256 Series Devices Reference Manual, Rev. 3
21-22
Freescale Semiconductor
Serial Communication Interface (S08SCIV4)
21.1.7
Block Diagram
Figure 21-3 shows the transmitter portion of the SCI.
INTERNAL BUS
(WRITE-ONLY)
LOOPS
SCID – Tx BUFFER
RSRC
LOOP
CONTROL
STOP
M
START
11-BIT TRANSMIT SHIFT REGISTER
8
7
6
5
4
3
2
1
0
TO TxD PIN
L
LSB
H
1  BAUD
RATE CLOCK
TO RECEIVE
DATA IN
SHIFT DIRECTION
PT
BREAK (ALL 0s)
PARITY
GENERATION
PREAMBLE (ALL 1s)
PE
SHIFT ENABLE
T8
LOAD FROM SCIxD
TXINV
SCI CONTROLS TxD
TE
SBK
TRANSMIT CONTROL
TXDIR
TxD DIRECTION
TO TxD
PIN LOGIC
BRK13
TDRE
TIE
TC
Tx INTERRUPT
REQUEST
TCIE
Figure 21-3. SCI Transmitter Block Diagram
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
21-23
Serial Communication Interface (S08SCIV4)
Figure 21-4 shows the receiver portion of the SCI.
INTERNAL BUS
(READ-ONLY)
16  BAUD
RATE CLOCK
DIVIDE
BY 16
SCID – Rx BUFFER
LBKDE
H
DATA RECOVERY
WAKE
ILT
8
7
6
5
4
3
2
1
START
FROM RxD PIN
RXINV
M
LSB
RSRC
11-BIT RECEIVE SHIFT REGISTER
MSB
SINGLE-WIRE
LOOP CONTROL
ALL 1s
LOOPS
STOP
FROM
TRANSMITTER
0
L
SHIFT DIRECTION
WAKEUP
LOGIC
RWU
RWUID
ACTIVE EDGE
DETECT
RDRF
RIE
IDLE
ILIE
LBKDIF
Rx INTERRUPT
REQUEST
LBKDIE
RXEDGIF
RXEDGIE
OR
ORIE
FE
FEIE
NF
ERROR INTERRUPT
REQUEST
NEIE
PE
PT
PARITY
CHECKING
PF
PEIE
Figure 21-4. SCI Receiver Block Diagram
MCF51MM256 Series Devices Reference Manual, Rev. 3
21-24
Freescale Semiconductor
Serial Communication Interface (S08SCIV4)
21.2
Register Definition
The SCI has eight 8-bit registers to control baud rate, select SCI options, report SCI status, and for
transmit/receive data.
Refer to the direct-page register summary in the Memory chapter of the MCF51MM256 series Reference
Manual for the absolute address assignments for all SCI registers. This section refers to registers and
control bits only by their names. A Freescale-provided equate or header file is used to translate these names
into the appropriate absolute addresses.
21.2.1
SCI Baud Rate Registers (SCIxBDH, SCIxBDL)
This pair of registers controls the prescale divisor for SCI baud rate generation. To update the 13-bit baud
rate setting [SBR12:SBR0], first write to SCIxBDH to buffer the high half of the new value and then write
to SCIxBDL. The working value in SCIxBDH does not change until SCIxBDL is written.
SCIxBDL is reset to a non-zero value, so after reset the baud rate generator remains disabled until the first
time the receiver or transmitter is enabled (RE or TE bits in SCIxC2 are written to 1).
7
6
5
LBKDIE
RXEDGIE
0
0
R
4
3
2
1
0
SBR12
SBR11
SBR10
SBR9
SBR8
0
0
0
0
0
0
W
Reset
0
= Unimplemented or Reserved
Figure 21-5. SCI Baud Rate Register (SCIxBDH)
Table 21-3. SCIxBDH Field Descriptions
Field
7
LBKDIE
Description
LIN Break Detect Interrupt Enable (for LBKDIF)
0 Hardware interrupts from LBKDIF disabled (use polling).
1 Hardware interrupt requested when LBKDIF flag is 1.
6
RXEDGIE
RxD Input Active Edge Interrupt Enable (for RXEDGIF)
0 Hardware interrupts from RXEDGIF disabled (use polling).
1 Hardware interrupt requested when RXEDGIF flag is 1.
4:0
SBR[12:8]
Baud Rate Modulo Divisor — The 13 bits in SBR[12:0] are referred to collectively as BR, and they set the
modulo divide rate for the SCI baud rate generator. When BR = 0, the SCI baud rate generator is disabled to
reduce supply current. When BR = 1 to 8191, the SCI baud rate = BUSCLK/(16BR). See also BR bits in
Table 21-4.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
21-25
Serial Communication Interface (S08SCIV4)
7
6
5
4
3
2
1
0
SBR7
SBR6
SBR5
SBR4
SBR3
SBR2
SBR1
SBR0
0
0
0
0
0
1
0
0
R
W
Reset
Figure 21-6. SCI Baud Rate Register (SCIxBDL)
Table 21-4. SCIxBDL Field Descriptions
Field
7:0
SBR[7:0]
21.2.2
Description
Baud Rate Modulo Divisor — These 13 bits in SBR[12:0] are referred to collectively as BR, and they set the
modulo divide rate for the SCI baud rate generator. When BR = 0, the SCI baud rate generator is disabled to
reduce supply current. When BR = 1 to 8191, the SCI baud rate = BUSCLK/(16BR). See also BR bits in
Table 21-3.
SCI Control Register 1 (SCIxC1)
This read/write register is used to control various optional features of the SCI system.
7
6
5
4
3
2
1
0
LOOPS
SCISWAI
RSRC
M
WAKE
ILT
PE
PT
0
0
0
0
0
0
0
0
R
W
Reset
Figure 21-7. SCI Control Register 1 (SCIxC1)
Table 21-5. SCIxC1 Field Descriptions
Field
Description
7
LOOPS
Loop Mode Select — Selects between loop back modes and normal 2-pin full-duplex modes. When LOOPS = 1,
the transmitter output is internally connected to the receiver input.
0 Normal operation — RxD and TxD use separate pins.
1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See
RSRC bit that follows.) RxD pin is not used by SCI.
6
SCISWAI
SCI Stops in Wait Mode
0 SCI clocks continue to run in wait mode so the SCI can be the source of an interrupt that wakes up the CPU.
1 SCI clocks freeze while CPU is in wait mode.
5
RSRC
4
M
Receiver Source Select — This bit has no meaning or effect unless the LOOPS bit is set to 1. When
LOOPS = 1, the receiver input is internally connected to the TxD pin and RSRC determines whether this
connection is also connected to the transmitter output.
0 Provided LOOPS = 1, RSRC = 0 selects internal loop back mode and the SCI does not use the RxD pins.
1 Single-wire SCI mode where the TxD pin is connected to the transmitter output and receiver input.
9-Bit or 8-Bit Mode Select
0 Normal — start + 8 data bits (LSB first) + stop.
1 Receiver and transmitter use 9-bit data characters
start + 8 data bits (LSB first) + 9th data bit + stop.
MCF51MM256 Series Devices Reference Manual, Rev. 3
21-26
Freescale Semiconductor
Serial Communication Interface (S08SCIV4)
Table 21-5. SCIxC1 Field Descriptions (Continued)
Field
3
WAKE
Description
Receiver Wakeup Method Select — Refer to Section 21.3.3.2, “Receiver Wakeup Operation” for more
information.
0 Idle-line wakeup.
1 Address-mark wakeup.
2
ILT
Idle Line Type Select — Setting this bit to 1 ensures that the stop bit and logic 1 bits at the end of a character
do not count toward the 10 or 11 bit times of logic high level needed by the idle line detection logic. Refer to
Section 21.3.3.2.1, “Idle-Line Wakeup” for more information.
0 Idle character bit count starts after start bit.
1 Idle character bit count starts after stop bit.
1
PE
Parity Enable — Enables hardware parity generation and checking. When parity is enabled, the most significant
bit (MSB) of the data character (eighth or ninth data bit) is treated as the parity bit.
0 No hardware parity generation or checking.
1 Parity enabled.
0
PT
Parity Type — Provided parity is enabled (PE = 1), this bit selects even or odd parity. Odd parity means the total
number of 1s in the data character, including the parity bit, is odd. Even parity means the total number of 1s in
the data character, including the parity bit, is even.
0 Even parity.
1 Odd parity.
21.2.3
SCI Control Register 2 (SCIxC2)
This register can be read or written at any time.
7
6
5
4
3
2
1
0
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
0
0
0
0
0
0
0
0
R
W
Reset
Figure 21-8. SCI Control Register 2 (SCIxC2)
Table 21-6. SCIxC2 Field Descriptions
Field
7
TIE
6
TCIE
Description
Transmit Interrupt Enable (for TDRE)
0 Hardware interrupts from TDRE disabled (use polling).
1 Hardware interrupt requested when TDRE flag is 1.
Transmission Complete Interrupt Enable (for TC)
0 Hardware interrupts from TC disabled (use polling).
1 Hardware interrupt requested when TC flag is 1.
5
RIE
Receiver Interrupt Enable (for RDRF)
0 Hardware interrupts from RDRF disabled (use polling).
1 Hardware interrupt requested when RDRF flag is 1.
4
ILIE
Idle Line Interrupt Enable (for IDLE)
0 Hardware interrupts from IDLE disabled (use polling).
1 Hardware interrupt requested when IDLE flag is 1.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
21-27
Serial Communication Interface (S08SCIV4)
Table 21-6. SCIxC2 Field Descriptions (Continued)
Field
Description
3
TE
Transmitter Enable
0 Transmitter off.
1 Transmitter on.
TE must be 1 in order to use the SCI transmitter. When TE = 1, the SCI forces the TxD pin to act as an output
for the SCI system.
When the SCI is configured for single-wire operation (LOOPS = RSRC = 1), TXDIR controls the direction of
traffic on the single SCI communication line (TxD pin).
TE also can be used to queue an idle character by writing TE = 0 then TE = 1 while a transmission is in progress.
Refer to Section 21.3.2.1, “Send Break and Queued Idle” for more details.
When TE is written to 0, the transmitter keeps control of the port TxD pin until any data, queued idle, or queued
break character finishes transmitting before allowing the pin to revert to a general-purpose I/O pin.
2
RE
Receiver Enable — When the SCI receiver is off, the RxD pin reverts to being a general-purpose port I/O pin. If
LOOPS = 1 the RxD pin reverts to being a general-purpose I/O pin even if RE = 1.
0 Receiver off.
1 Receiver on.
1
RWU
Receiver Wakeup Control — This bit can be written to 1 to place the SCI receiver in a standby state where it
waits for automatic hardware detection of a selected wakeup condition. The wakeup condition is either an idle
line between messages (WAKE = 0, idle-line wakeup), or a logic 1 in the most significant data bit in a character
(WAKE = 1, address-mark wakeup). Application software sets RWU and (normally) a selected hardware
condition automatically clears RWU. Refer to Section 21.3.3.2, “Receiver Wakeup Operation” for more details.
0 Normal SCI receiver operation.
1 SCI receiver in standby waiting for wakeup condition.
0
SBK
Send Break — Writing a 1 and then a 0 to SBK queues a break character in the transmit data stream. Additional
break characters of 10 or 11 (13 or 14 if BRK13 = 1) bit times of logic 0 are queued as long as SBK = 1.
Depending on the timing of the set and clear of SBK relative to the information currently being transmitted, a
second break character may be queued before software clears SBK. Refer to Section 21.3.2.1, “Send Break and
Queued Idle” for more details.
0 Normal transmitter operation.
1 Queue break character(s) to be sent.
21.2.4
SCI Status Register 1 (SCIxS1)
This register has eight read-only status flags. Writes have no effect. Special software sequences (which do
not involve writing to this register) clear these status flags.
R
7
6
5
4
3
2
1
0
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
1
1
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 21-9. SCI Status Register 1 (SCIxS1)
MCF51MM256 Series Devices Reference Manual, Rev. 3
21-28
Freescale Semiconductor
Serial Communication Interface (S08SCIV4)
Table 21-7. SCIxS1 Field Descriptions
Field
Description
7
TDRE
Transmit Data Register Empty Flag — TDRE is set out of reset and when a transmit data value transfers from
the transmit data buffer to the transmit shifter, leaving room for a new character in the buffer. To clear TDRE, read
SCIxS1 with TDRE = 1 and then write to the SCI data register (SCIxD).
0 Transmit data register (buffer) full.
1 Transmit data register (buffer) empty.
6
TC
Transmission Complete Flag — TC is set out of reset and when TDRE = 1 and no data, preamble, or break
character is being transmitted.
0 Transmitter active (sending data, a preamble, or a break).
1 Transmitter idle (transmission activity complete).
TC is cleared automatically by reading SCIxS1 with TC = 1 and then doing one of the following three things:
• Write to the SCI data register (SCIxD) to transmit new data
• Queue a preamble by changing TE from 0 to 1
• Queue a break character by writing 1 to SBK in SCIxC2
5
RDRF
Receive Data Register Full Flag — RDRF becomes set when a character transfers from the receive shifter into
the receive data register (SCIxD). To clear RDRF, read SCIxS1 with RDRF = 1 and then read the SCI data
register (SCIxD).
0 Receive data register empty.
1 Receive data register full.
4
IDLE
Idle Line Flag — IDLE is set when the SCI receive line becomes idle for a full character time after a period of
activity. When ILT = 0, the receiver starts counting idle bit times after the start bit. So if the receive character is
all 1s, these bit times and the stop bit time count toward the full character time of logic high (10 or 11 bit times
depending on the M control bit) needed for the receiver to detect an idle line. When ILT = 1, the receiver doesn’t
start counting idle bit times until after the stop bit. So the stop bit and any logic high bit times at the end of the
previous character do not count toward the full character time of logic high needed for the receiver to detect an
idle line.
To clear IDLE, read SCIxS1 with IDLE = 1 and then read the SCI data register (SCIxD). After IDLE has been
cleared, it cannot become set again until after a new character has been received and RDRF has been set. IDLE
will get set only once even if the receive line remains idle for an extended period.
0 No idle line detected.
1 Idle line was detected.
3
OR
Receiver Overrun Flag — OR is set when a new serial character is ready to be transferred to the receive data
register (buffer), but the previously received character has not been read from SCIxD yet. In this case, the new
character (and all associated error information) is lost because there is no room to move it into SCIxD. To clear
OR, read SCIxS1 with OR = 1 and then read the SCI data register (SCIxD).
0 No overrun.
1 Receive overrun (new SCI data lost).
2
NF
Noise Flag — The advanced sampling technique used in the receiver takes seven samples during the start bit
and three samples in each data bit and the stop bit. If any of these samples disagrees with the rest of the samples
within any bit time in the frame, the flag NF is set at the same time as the RDRF flag is set for the character. To
clear NF, read SCIxS1 and then read the SCI data register (SCIxD).
0 No noise detected.
1 Noise detected in the received character in SCIxD.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
21-29
Serial Communication Interface (S08SCIV4)
Table 21-7. SCIxS1 Field Descriptions (Continued)
Field
Description
1
FE
Framing Error Flag — FE is set at the same time as RDRF when the receiver detects a logic 0 where the stop
bit was expected. This suggests the receiver was not properly aligned to a character frame. To clear FE, read
SCIxS1 with FE = 1 and then read the SCI data register (SCIxD).
0 No framing error detected. This does not guarantee the framing is correct.
1 Framing error.
0
PF
Parity Error Flag — PF is set at the same time as RDRF when parity is enabled (PE = 1) and the parity bit in
the received character does not agree with the expected parity value. To clear PF, read SCIxS1 and then read
the SCI data register (SCIxD).
0 No parity error.
1 Parity error.
21.2.5
SCI Status Register 2 (SCIxS2)
This register contains one read-only status flag.
7
6
5
LBKDIF
RXEDGIF
0
0
R
4
3
2
1
RXINV
RWUID
BRK13
LBKDE
0
0
0
0
0
0
RAF
W
Reset
0
0
= Unimplemented or Reserved
Figure 21-10. SCI Status Register 2 (SCIxS2)
Table 21-8. SCIxS2 Field Descriptions
Field
Description
7
LBKDIF
LIN Break Detect Interrupt Flag — LBKDIF is set when the LIN break detect circuitry is enabled and a LIN break
character is detected. LBKDIF is cleared by writing a “1” to it.
0 No LIN break character has been detected.
1 LIN break character has been detected.
6
RXEDGIF
RxD Pin Active Edge Interrupt Flag — RXEDGIF is set when an active edge (falling if RXINV = 0, rising if
RXINV=1) on the RxD pin occurs. RXEDGIF is cleared by writing a “1” to it.
0 No active edge on the receive pin has occurred.
1 An active edge on the receive pin has occurred.
4
RXINV1
Receive Data Inversion — Setting this bit reverses the polarity of the received data input.
0 Receive data not inverted
1 Receive data inverted
3
RWUID
Receive Wake Up Idle Detect— RWUID controls whether the idle character that wakes up the receiver sets the
IDLE bit.
0 During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character.
1 During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character.
2
BRK13
Break Character Generation Length — BRK13 selects a longer transmitted break character length. The state
of this bit does not affect the detection of a framing error.
0 Break character is transmitted with length of 10 bit times (11 if M = 1)
1 Break character is transmitted with length of 13 bit times (14 if M = 1)
MCF51MM256 Series Devices Reference Manual, Rev. 3
21-30
Freescale Semiconductor
Serial Communication Interface (S08SCIV4)
Table 21-8. SCIxS2 Field Descriptions (Continued)
1
Field
Description
1
LBKDE
LIN Break Detection Enable— LBKDE selects a longer break character detection length. While LBKDE is set,
framing error (FE) and receive data register full (RDRF) flags are prevented from setting.
0 Break character is detected at length of 10 bit times (11 if M = 1).
1 Break character is detected at length of 11 bit times (12 if M = 1).
0
RAF
Receiver Active Flag — RAF is set when the SCI receiver detects the beginning of a valid start bit, and RAF is
cleared automatically when the receiver detects an idle line. This status flag can be used to check whether an
SCI character is being received before instructing the MCU to go to stop mode.
0 SCI receiver idle waiting for a start bit.
1 SCI receiver active (RxD input not idle).
Setting RXINV inverts the RxD input for all cases: data bits, start and stop bits, break, and idle.
When using an internal oscillator in a LIN system, it is necessary to raise the break detection threshold by
one bit time. Under the worst case timing conditions allowed in LIN, it is possible that a 0x00 data
character can appear to be 10.26 bit times long at a slave running 14% faster than the master. This would
trigger normal break detection circuitry designed to detect a 10 bit break symbol. When the LBKDE bit is
set, framing errors are inhibited and the break detection threshold changes from 10 bits to 11 bits,
preventing false detection of a 0x00 data character as a LIN break symbol.
21.2.6
SCI Control Register 3 (SCIxC3)
7
R
6
5
4
3
2
1
0
T8
TXDIR
TXINV
ORIE
NEIE
FEIE
PEIE
0
0
0
0
0
0
0
R8
W
Reset
0
= Unimplemented or Reserved
Figure 21-11. SCI Control Register 3 (SCIxC3)
Table 21-9. SCIxC3 Field Descriptions
Field
Description
7
R8
Ninth Data Bit for Receiver — When the SCI is configured for 9-bit data (M = 1), R8 can be thought of as a ninth
receive data bit to the left of the MSB of the buffered data in the SCIxD register. When reading 9-bit data, read
R8 before reading SCIxD because reading SCIxD completes automatic flag clearing sequences which could
allow R8 and SCIxD to be overwritten with new data.
6
T8
Ninth Data Bit for Transmitter — When the SCI is configured for 9-bit data (M = 1), T8 may be thought of as a
ninth transmit data bit to the left of the MSB of the data in the SCIxD register. When writing 9-bit data, the entire
9-bit value is transferred to the SCI shift register after SCIxD is written so T8 should be written (if it needs to
change from its previous value) before SCIxD is written. If T8 does not need to change in the new value (such
as when it is used to generate mark or space parity), it need not be written each time SCIxD is written.
5
TXDIR
TxD Pin Direction in Single-Wire Mode — When the SCI is configured for single-wire half-duplex operation
(LOOPS = RSRC = 1), this bit determines the direction of data at the TxD pin.
0 TxD pin is an input in single-wire mode.
1 TxD pin is an output in single-wire mode.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
21-31
Serial Communication Interface (S08SCIV4)
Table 21-9. SCIxC3 Field Descriptions (Continued)
Field
4
TXINV1
1
Description
Transmit Data Inversion — Setting this bit reverses the polarity of the transmitted data output.
0 Transmit data not inverted
1 Transmit data inverted
3
ORIE
Overrun Interrupt Enable — This bit enables the overrun flag (OR) to generate hardware interrupt requests.
0 OR interrupts disabled (use polling).
1 Hardware interrupt requested when OR = 1.
2
NEIE
Noise Error Interrupt Enable — This bit enables the noise flag (NF) to generate hardware interrupt requests.
0 NF interrupts disabled (use polling).
1 Hardware interrupt requested when NF = 1.
1
FEIE
Framing Error Interrupt Enable — This bit enables the framing error flag (FE) to generate hardware interrupt
requests.
0 FE interrupts disabled (use polling).
1 Hardware interrupt requested when FE = 1.
0
PEIE
Parity Error Interrupt Enable — This bit enables the parity error flag (PF) to generate hardware interrupt
requests.
0 PF interrupts disabled (use polling).
1 Hardware interrupt requested when PF = 1.
Setting TXINV inverts the TxD output for all cases: data bits, start and stop bits, break, and idle.
21.2.7
SCI Data Register (SCIxD)
This register is actually two separate registers. Reads return the contents of the read-only receive data
buffer and writes go to the write-only transmit data buffer. Reads and writes of this register are also
involved in the automatic flag clearing mechanisms for the SCI status flags.
7
6
5
4
3
2
1
0
R
R7
R6
R5
R4
R3
R2
R1
R0
W
T7
T6
T5
T4
T3
T2
T1
T0
0
0
0
0
0
0
0
0
Reset
Figure 21-12. SCI Data Register (SCIxD)
21.3
Functional Description
The SCI allows full-duplex, asynchronous, NRZ serial communication among the MCU and remote
devices, including other MCUs. The SCI comprises a baud rate generator, transmitter, and receiver block.
The transmitter and receiver operate independently, although they use the same baud rate generator.
During normal operation, the MCU monitors the status of the SCI, writes the data to be transmitted, and
processes received data. The following describes each of the blocks of the SCI.
21.3.1
Baud Rate Generation
As shown in Figure 21-13, the clock source for the SCI baud rate generator is the bus-rate clock.
MCF51MM256 Series Devices Reference Manual, Rev. 3
21-32
Freescale Semiconductor
Serial Communication Interface (S08SCIV4)
MODULO DIVIDE BY
(1 THROUGH 8191)
BUSCLK
SBR12:SBR0
BAUD RATE GENERATOR
OFF IF [SBR12:SBR0] = 0
DIVIDE BY
16
Tx BAUD RATE
Rx SAMPLING CLOCK
(16  BAUD RATE)
BAUD RATE =
BUSCLK
[SBR12:SBR0]  16
Figure 21-13. SCI Baud Rate Generation
SCI communications require the transmitter and receiver (which typically derive baud rates from
independent clock sources) to use the same baud rate. Allowed tolerance on this baud frequency depends
on the details of how the receiver synchronizes to the leading edge of the start bit and how bit sampling is
performed.
The MCU resynchronizes to bit boundaries on every high-to-low transition. In the worst case, there are no
such transitions in the full 10- or 11-bit time character frame so any mismatch in baud rate is accumulated
for the whole character time. For a SCI system whose bus frequency is driven by a crystal, the allowed
baud rate mismatch is about ±4.5 % for 8-bit data format and about ±4 % for 9-bit data format. Although
baud rate modulo divider settings do not always produce baud rates that exactly match standard rates, it is
normally possible to get within a few percent, which is acceptable for reliable communications.
21.3.2
Transmitter Functional Description
This section describes the overall block diagram for the SCI transmitter, as well as specialized functions
for sending break and idle characters. The transmitter block diagram is shown in Figure 21-3.
The transmitter output (TxD) idle state defaults to logic high (TXINV = 0 following reset). The transmitter
output is inverted by setting TXINV = 1. The transmitter is enabled by setting the TE bit in SCIxC2. This
queues a preamble character that is one full character frame of the idle state. The transmitter then remains
idle until data is available in the transmit data buffer. Programs store data into the transmit data buffer by
writing to the SCI data register (SCIxD).
The central element of the SCI transmitter is the transmit shift register that is 10 or 11 bits long depending
on the setting in the M control bit. For the remainder of this section, assume M = 0, selecting the normal
8-bit data mode. In 8-bit data mode, the shift register holds a start bit, eight data bits, and a stop bit. When
the transmit shift register is available for a new SCI character, the value waiting in the transmit data register
is transferred to the shift register (synchronized with the baud rate clock) and the transmit data register
empty (TDRE) status flag is set to indicate another character can be written to the transmit data buffer at
SCIxD.
If no new character is waiting in the transmit data buffer after a stop bit is shifted out the TxD pin, the
transmitter sets the transmit complete flag and enters an idle mode, with TxD high, waiting for more
characters to transmit.
Writing 0 to TE does not immediately release the pin to be a general-purpose I/O pin. Any transmit activity
in progress must first be completed. This includes data characters in progress, queued idle characters, and
queued break characters.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
21-33
Serial Communication Interface (S08SCIV4)
21.3.2.1
Send Break and Queued Idle
The SBK control bit in SCIxC2 sends break characters originally used to gain the attention of old teletype
receivers. Break characters are a full character time of logic 0 (10 bit times including the start and stop
bits). A longer break of 13 bit times can be enabled by setting BRK13 = 1. Normally, a program would
wait for TDRE to become set to indicate the last character of a message has moved to the transmit shifter,
then write 1 and then write 0 to the SBK bit. This action queues a break character to be sent as soon as the
shifter is available. If SBK remains 1 when the queued break moves into the shifter (synchronized to the
baud rate clock), an additional break character is queued. If the receiving device is another Freescale
Semiconductor SCI, the break characters are received as 0s in all eight data bits and a framing error
(FE = 1) occurs.
When idle-line wakeup is used, a full character time of idle (logic 1) is needed between messages to wake
up any sleeping receivers. Normally, a program would wait for TDRE to become set to indicate the last
character of a message has moved to the transmit shifter, then write 0 and then write 1 to the TE bit. This
action queues an idle character to be sent as soon as the shifter is available. As long as the character in the
shifter does not finish while TE = 0, the SCI transmitter never actually releases control of the TxD pin. If
there is a possibility of the shifter finishing while TE = 0, set the general-purpose I/O controls so the pin
shared with TxD is an output driving a logic 1. This ensures that the TxD line looks like a normal idle line
even if the SCI loses control of the port pin between writing 0 and then 1 to TE.
The length of the break character is affected by the BRK13 and M bits as shown below.
Table 21-10. Break Character Length
21.3.3
BRK13
M
Break Character Length
0
0
10 bit times
0
1
11 bit times
1
0
13 bit times
1
1
14 bit times
Receiver Functional Description
In this section, the receiver block diagram (Figure 21-4) is a guide for the overall receiver functional
description. Next, the data sampling technique used to reconstruct receiver data is described in more detail.
Finally, two variations of the receiver wakeup function are explained.
Set RXINV = 1 to invert the receiver input. Set the RE bit in SCIxC2 to enable the receiver. Character
frames consist of a start bit of logic 0, eight (or nine) data bits (LSB first), and a stop bit of logic 1. For
information about 9-bit data mode, refer to Section •, “8- and 9-bit data modes.” For the remainder of this
discussion, assume the SCI is configured for normal 8-bit data mode.
After receiving the stop bit into the receive shifter, and provided the receive data register is not already
full, the data character is transferred to the receive data register and the receive data register full (RDRF)
status flag is set. If RDRF was already set indicating the receive data register (buffer) was already full, the
overrun (OR) status flag is set and the new data is lost. Because the SCI receiver is double-buffered, the
program has one full character time after RDRF is set before the data in the receive data buffer must be
read to avoid a receiver overrun.
MCF51MM256 Series Devices Reference Manual, Rev. 3
21-34
Freescale Semiconductor
Serial Communication Interface (S08SCIV4)
When a program detects that the receive data register is full (RDRF = 1), it reads SCIxD to get the data
from the receive data register. The RDRF flag is cleared automatically when the program that handles
receive data issues a 2-step sequence. Refer to Section 21.3.4, “Interrupts and Status Flags” for more
details about flag clearing.
21.3.3.1
Data Sampling Technique
The SCI receiver uses a 16 baud rate clock for sampling. To search for a falling edge on the RxD serial
data input pin, the receiver starts taking logic level samples at 16 times the baud rate. A falling edge is
defined as a logic 0 sample after three consecutive logic 1 samples. The 16 baud rate clock divides the
bit time into 16 segments labeled RT1 through RT16. When a falling edge is located, three more samples
are taken at RT3, RT5, and RT7 to make sure this was a real start bit and not merely noise. If at least two
of these three samples are 0, the receiver assumes it is synchronized to a receive character.
The receiver then samples each bit time, including the start and stop bits, at RT8, RT9, and RT10 to
determine the logic level for that bit. The logic level is interpreted to be that of the majority of the samples
taken during the bit time. In the case of the start bit, the bit is assumed to be 0 if at least two of the samples
at RT3, RT5, and RT7 are 0 even if one or all of the samples taken at RT8, RT9, and RT10 are 1s. If any
sample in any bit time (including the start and stop bits) in a character frame fails to agree with the logic
level for that bit, the noise flag (NF) is set when the received character is transferred to the receive data
buffer.
The falling edge detection logic continuously looks for falling edges. If an edge is detected, the sample
clock is resynchronized to bit times. This improves the reliability of the receiver in the presence of noise
or mismatched baud rates. It does not improve worst case analysis because some characters do not have
any extra falling edges anywhere in the character frame.
In the case of a framing error, provided the received character was not a break character, the sampling logic
that searches for a falling edge is filled with three logic 1 samples so that a new start bit can be detected
almost immediately.
In the case of a framing error, the receiver is inhibited from receiving any new characters until the framing
error flag is cleared. The receive shift register continues to function, but a complete character cannot
transfer to the receive data buffer if FE remains set.
21.3.3.2
Receiver Wakeup Operation
Receiver wakeup is a hardware mechanism that allows an SCI receiver to ignore the characters in a
message intended for a different SCI receiver. In such a system, all receivers evaluate the first character(s)
of each message, and as soon as they determine the message is intended for a different receiver, they write
logic 1 to the receiver wake up (RWU) control bit in SCIxC2. When RWU bit is set, the status flags
associated with the receiver (with the exception of the idle bit, IDLE, when RWUID bit is set) are inhibited
from setting. This eliminates the need for software overhead to handle unimportant message characters.
At the end of a message, or at the beginning of the next message, all receivers automatically force RWU
to 0 so all receivers wake up in time to look at the first character(s) of the next message.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
21-35
Serial Communication Interface (S08SCIV4)
21.3.3.2.1
Idle-Line Wakeup
When WAKE = 0, the receiver is configured for idle-line wakeup. In this mode, RWU is cleared
automatically when the receiver detects a full character time of the idle-line level. The M control bit selects
8-bit or 9-bit data mode that determines how many bit times of idle are needed to constitute a full character
time (10 or 11 bit times because of the start and stop bits).
When RWU is one and RWUID is zero, the idle condition that wakes up the receiver does not set the IDLE
flag. The receiver wakes up and waits for the first data character of the next message which sets the RDRF
flag and generate an interrupt if enabled. When RWUID is one, any idle condition sets the IDLE flag and
generates an interrupt if enabled, regardless of whether RWU is zero or one.
The idle-line type (ILT) control bit selects one of two ways to detect an idle line. When ILT = 0, the idle
bit counter starts after the start bit so the stop bit and any logic 1s at the end of a character count toward
the full character time of idle. When ILT = 1, the idle bit counter does not start until after a stop bit time,
so the idle detection is not affected by the data in the last character of the previous message.
21.3.3.2.2
Address-Mark Wakeup
When WAKE = 1, the receiver is configured for address-mark wakeup. In this mode, RWU is cleared
automatically when the receiver detects a logic 1 in the most significant bit of a received character (eighth
bit in M = 0 mode and ninth bit in M = 1 mode).
Address-mark wakeup allows messages to contain idle characters, but requires the MSB be reserved for
use in address frames. The logic 1 MSB of an address frame clears the RWU bit before the stop bit is
received and sets the RDRF flag. In this case, the character with the MSB set is received even though the
receiver was sleeping during most of this character time.
21.3.4
Interrupts and Status Flags
The SCI system has three separate interrupt vectors to reduce the amount of software needed to isolate the
cause of the interrupt. One interrupt vector is associated with the transmitter for TDRE and TC events.
Another interrupt vector is associated with the receiver for RDRF, IDLE, RXEDGIF and LBKDIF events.
A third vector is used for OR, NF, FE, and PF error conditions. Local interrupt enable masks can separately
mask each of these ten interrupt sources. Software can still poll the flags when the local masks are cleared
to disable generation of hardware interrupt requests.
The SCI transmitter has two status flags that can generate hardware interrupt requests. Transmit data
register empty (TDRE) indicates available room in the transmit data buffer to write another transmit
character to SCIxD. If the transmit interrupt enable (TIE) bit is set, a hardware interrupt is requested when
TDRE = 1. Transmit complete (TC) indicates that the transmitter is finished transmitting all data,
preamble, and break characters and is idle with TxD at the inactive level. This flag is often used in systems
with modems to determine when it is safe to turn off the modem. If the transmit complete interrupt enable
(TCIE) bit is set, a hardware interrupt will be requested whenever TC = 1. Instead of hardware interrupts,
software polling may be used to monitor the TDRE and TC status flags if the corresponding TIE or TCIE
local interrupt masks are 0s.
MCF51MM256 Series Devices Reference Manual, Rev. 3
21-36
Freescale Semiconductor
Serial Communication Interface (S08SCIV4)
When a program detects that the receive data register is full (RDRF = 1), it gets the data from the receive
data register by reading SCIxD. The RDRF flag is cleared by reading SCIxS1 while RDRF = 1 and then
reading SCIxD.
When polling is used, this sequence is naturally satisfied in the normal course of the user program. If
hardware interrupts are used, SCIxS1 must be read in the interrupt service routine (ISR). Normally, this is
done in the ISR anyway to check for receive errors, so the sequence is automatically satisfied.
The IDLE status flag includes logic that prevents it from getting set repeatedly when the RxD line remains
idle for an extended period of time. IDLE is cleared by reading SCIxS1 while IDLE = 1 and then reading
SCIxD. After IDLE has been cleared, it cannot become set again until the receiver has received at least
one new character and has set RDRF.
If the associated error was detected in the received character that caused RDRF to be set, the error flags —
noise flag (NF), framing error (FE), and parity error flag (PF) — are set at the same time as RDRF. These
flags are not set in overrun cases.
If RDRF was already set when a new character is ready to be transferred from the receive shifter to the
receive data buffer, the overrun (OR) flag is set instead of the data along with any associated NF, FE, or
PF condition is lost.
At any time, an active edge on the RxD serial data input pin causes the RXEDGIF flag to set. The
RXEDGIF flag is cleared by writing a “1” to it. This function does depend on the receiver being enabled
(RE = 1).
21.3.5
Additional SCI Functions
The following sections describe additional SCI functions.
21.3.5.1
8- and 9-Bit Data Modes
The SCI system (transmitter and receiver) can be configured to operate in 9-bit data mode by setting the
M control bit in SCIxC1. In 9-bit mode, there is a ninth data bit to the left of the MSB of the SCI data
register. For the transmit data buffer, this bit is stored in T8 in SCIxC3. For the receiver, the ninth bit is
held in R8 in SCIxC3.
For coherent writes to the transmit data buffer, write to the T8 bit before writing to SCIxD.
If the bit value to be transmitted as the ninth bit of a new character is the same as for the previous character,
it is not necessary to write to T8 again. When data is transferred from the transmit data buffer to the
transmit shifter, the value in T8 is copied at the same time data is transferred from SCIxD to the shifter.
Typically, use the 9-bit data mode in conjunction with parity to allow eight bits of data plus the parity in
the ninth bit. Or use it with address-mark wakeup so the ninth data bit can serve as the wakeup bit. In
custom protocols, the ninth bit can also serve as a software-controlled marker.
21.3.5.2
Stop Mode Operation
During all stop modes, clocks to the SCI module are halted.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
21-37
Serial Communication Interface (S08SCIV4)
In stop2 modes, all SCI register data is lost and must be re-initialized upon recovery from these two stop
modes. No SCI module registers are affected in stop3 mode.
The receive input active edge detect circuit remains active in stop3 mode, but not in stop2. An active edge
on the receive input brings the CPU out of stop3 mode if the interrupt is not masked (RXEDGIE = 1).
Note, because the clocks are halted, the SCI module resumes operation upon exit from stop (only in stop3
mode). Software should ensure stop mode is not entered while there is a character being transmitted out of
or received into the SCI module.
21.3.5.3
Loop Mode
When LOOPS = 1, the RSRC bit in the same register chooses between loop mode (RSRC = 0) or
single-wire mode (RSRC = 1). Loop mode is sometimes used to check software, independent of
connections in the external system, to help isolate system problems. In this mode, the transmitter output is
internally connected to the receiver input and the RxD pin is not used by the SCI, so it reverts to a
general-purpose port I/O pin.
21.3.5.4
Single-Wire Operation
When LOOPS = 1, the RSRC bit in the same register chooses between loop mode (RSRC = 0) or
single-wire mode (RSRC = 1). Single-wire mode is used to implement a half-duplex serial connection.
The receiver is internally connected to the transmitter output and to the TxD pin. The RxD pin is not used
and reverts to a general-purpose port I/O pin.
In single-wire mode, the TXDIR bit in SCIxC3 controls the direction of serial data on the TxD pin. When
TXDIR = 0, the TxD pin is an input to the SCI receiver and the transmitter is temporarily disconnected
from the TxD pin so an external device can send serial data to the receiver. When TXDIR = 1, the TxD pin
is an output driven by the transmitter. In single-wire mode, the internal loop back connection from the
transmitter to the receiver causes the receiver to receive characters that are sent out by the transmitter.
MCF51MM256 Series Devices Reference Manual, Rev. 3
21-38
Freescale Semiconductor
Chapter 22
16-bit Serial Peripheral Interface (S08SPI16V5)
22.1
Introduction
The SPI1 in these devices is a 16-bit serial peripheral interface (SPI) module with FIFO.
NOTE
There are two SPI modules on this device. Replace SPIx with the
appropriate peripheral designation (SPI1 or SPI2), depending upon your
use:
•
•
22.1.1
SPI1 — for the 16-bit SPI with FIFO module.
SPI2 — for the 8-bit SPI module.
SPI1 Clock Gating
The bus clock to the SPI1 can be gated on and off using the SPI1 bit in SCGC2. These bits are set after any
reset, which enables the bus clock to this module. To conserve power, these bits can be cleared to disable
the clock to this module when not in use. See Section 5.7.8, “System Clock Gating Control 2 Register
(SCGC2),” for details.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
22-1
16-bit Serial Peripheral Interface (S08SPI16V5)
Figure 22-1. Block Diagram with SPI1 Module Highlighted
MCF51MM256 Series Devices Reference Manual, Rev. 3
22-2
Freescale Semiconductor
16-bit Serial Peripheral Interface (S08SPI16V5)
22.1.2
Features
The SPI includes these distinctive features:
• Master mode or slave mode operation
• Full-duplex or single-wire bidirectional mode
• Programmable transmit bit rate
• Double-buffered transmit and receive data register
• Serial clock phase and polarity options
• Slave select output
• Mode fault error flag with CPU interrupt capability
• Control of SPI operation during wait mode
• Selectable MSB-first or LSB-first shifting
• Programmable 8- or 16-bit data transmission length
• Receive data buffer hardware match feature
• 64-bit FIFO mode for high speed/large amounts of data transfers.
22.1.3
Modes of Operation
The SPI functions in three modes, run, wait, and stop.
• Run Mode
This is the basic mode of operation.
• Wait Mode
SPI operation in wait mode is a configurable low-power mode, controlled by the SPISWAI bit
located in the SPIxC2 register. In wait mode, if the SPISWAI bit is clear, the SPI operates like in
Run Mode. If the SPISWAI bit is set, the SPI goes into a power conservative state, with the SPI
clock generation turned off. If the SPI is configured as a master, any transmission in progress stops,
but is resumed after CPU goes into Run Mode. If the SPI is configured as a slave, reception and
transmission of a byte continues, so that the slave stays synchronized to the master.
• Stop Mode
The SPI is inactive in stop3/stop4 mode for reduced power consumption. If the SPI is configured
as a master, any transmission in progress stops, but is resumed after the CPU goes into Run Mode.
If the SPI is configured as a slave, reception and transmission of a data continues, so that the slave
stays synchronized to the master.
The SPI is completely disabled in all other stop modes. When the CPU wakes from these stop modes, all
SPI register content will be reset.
This is a high level description only, detailed descriptions of operating modes are contained in section
Section 22.4.10, “Low-power Mode Options.”
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
22-3
16-bit Serial Peripheral Interface (S08SPI16V5)
22.1.4
Block Diagrams
This section includes block diagrams showing SPI system connections, the internal organization of the SPI
module, and the SPI clock dividers that control the master mode bit rate.
22.1.4.1
SPI System Block Diagram
Figure 22-2 shows the SPI modules of two MCUs connected in a master-slave arrangement. The master
device initiates all SPI data transfers. During a transfer, the master shifts data out (on the MOSI pin) to the
slave while simultaneously shifting data in (on the MISO pin) from the slave. The transfer effectively
exchanges the data that was in the SPI shift registers of the two SPI systems. The SPSCK signal is a clock
output from the master and an input to the slave. The slave device must be selected by a low level on the
slave select input (SS pin). In this system, the master device has configured its SS pin as an optional slave
select output.
SLAVE
MASTER
MOSI
MOSI
SPI SHIFTER
SPI SHIFTER
8 OR 16 BITS
MISO
SPSCK
CLOCK
GENERATOR
SS
MISO
8 OR 16 BITS
SPSCK
SS
Figure 22-2. SPI System Connections
22.1.4.2
SPI Module Block Diagram
Figure 22-3 is a block diagram of the SPI module. The central element of the SPI is the SPI shift register.
Data is written to the double-buffered transmitter (write to SPIxDH:SPIxDL) and gets transferred to the
SPI shift register at the start of a data transfer. After shifting in 8 or 16 bits (as determined by SPIMODE
bit) of data, the data is transferred into the double-buffered receiver where it can be read (read from
SPIxDH:SPIxDL). Pin multiplexing logic controls connections between MCU pins and the SPI module.
Additionally there is an 8-byte receive FIFO and an 8-byte transmit FIFO that once enabled provide
features to allow less CPU interrupts to occur when transmitting/receiving high volume/high speed data.
When FIFO mode is enabled, the SPI can still function in either 8-bit or 16-bit mode (as per SPIMODE
bit) and 3 additional flags help monitor the FIFO status and two of these flags can provide CPU interrupts.
MCF51MM256 Series Devices Reference Manual, Rev. 3
22-4
Freescale Semiconductor
16-bit Serial Peripheral Interface (S08SPI16V5)
When the SPI is configured as a master, the clock output is routed to the SPSCK pin, the shifter output is
routed to MOSI, and the shifter input is routed from the MISO pin.
When the SPI is configured as a slave, the SPSCK pin is routed to the clock input of the SPI, the shifter
output is routed to MISO, and the shifter input is routed from the MOSI pin.
In the external SPI system, simply connect all SPSCK pins to each other, all MISO pins together, and all
MOSI pins together. Peripheral devices often use slightly different names for these pins.
PIN CONTROL
M
Tx FIFO (8-byte deep)
SPE
MOSI
(MOMI)
S
Tx BUFFER (WRITE SPIxDH:SPIxDL)
ENABLE
SPI SYSTEM
M
SPI SHIFT REGISTER
SHIFT
OUT
SHIFT
IN
8 OR 16 Rx BUFFER (READ SPIxDH:SPIxDL)
BIT MODE
SPIMODE
FIFOMODELSBFE
SHIFT
CLOCK
Rx BUFFER
FULL
S
SPC0
Rx FIFO (8-byte deep)
SHIFT
DIRECTION
BIDIROE
Tx BUFFER
EMPTY
MASTER CLOCK
BUS RATE
CLOCK
CLOCK
LOGIC
SPIBR
CLOCK GENERATOR
SLAVE CLOCK
MASTER/SLAVE
MSTR
MISO
(SISO)
M
SPSCK
S
MASTER/
SLAVE
MODE SELECT
MODFEN
SSOE
MODE FAULT
DETECTION
16-BIT COMPARATOR
SPIxMH:SPIxML
16-BIT LATCH
RNFULLF
RNFULLIEN
SPRF
TNEAREF
SS
SPMF
SPMIE
SPTEF
SPTIE
TNEARIEN
MODF
SPIE
SPI
INTERRUPT
REQUEST
Figure 22-3. SPI Module Block Diagram
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
22-5
16-bit Serial Peripheral Interface (S08SPI16V5)
22.2
External Signal Description
The SPI optionally shares four port pins. The function of these pins depends on the settings of SPI control
bits. When the SPI is disabled (SPE = 0), these four pins revert to being general-purpose port I/O pins that
are not controlled by the SPI.
22.2.1
SPSCK — SPI Serial Clock
When the SPI is enabled as a slave, this pin is the serial clock input. When the SPI is enabled as a master,
this pin is the serial clock output.
22.2.2
MOSI — Master Data Out, Slave Data In
When the SPI is enabled as a master and SPI pin control zero (SPC0) is 0 (not bidirectional mode), this
pin is the serial data output. When the SPI is enabled as a slave and SPC0 = 0, this pin is the serial data
input. If SPC0 = 1 to select single-wire bidirectional mode, and master mode is selected, this pin becomes
the bidirectional data I/O pin (MOMI). Also, the bidirectional mode output enable bit determines whether
the pin acts as an input (BIDIROE = 0) or an output (BIDIROE = 1). If SPC0 = 1 and slave mode is
selected, this pin is not used by the SPI and reverts to being a general-purpose port I/O pin.
22.2.3
MISO — Master Data In, Slave Data Out
When the SPI is enabled as a master and SPI pin control zero (SPC0) is 0 (not bidirectional mode), this
pin is the serial data input. When the SPI is enabled as a slave and SPC0 = 0, this pin is the serial data
output. If SPC0 = 1 to select single-wire bidirectional mode, and slave mode is selected, this pin becomes
the bidirectional data I/O pin (SISO) and the bidirectional mode output enable bit determines whether the
pin acts as an input (BIDIROE = 0) or an output (BIDIROE = 1). If SPC0 = 1 and master mode is selected,
this pin is not used by the SPI and reverts to being a general-purpose port I/O pin.
22.2.4
SS — Slave Select
When the SPI is enabled as a slave, this pin is the low-true slave select input. When the SPI is enabled as
a master and mode fault enable is off (MODFEN = 0), this pin is not used by the SPI and reverts to being
a general-purpose port I/O pin. When the SPI is enabled as a master and MODFEN = 1, the slave select
output enable bit determines whether this pin acts as the mode fault input (SSOE = 0) or as the slave select
output (SSOE = 1).
22.3
Register Definition
The SPI has above 8-bit registers to select SPI options, control baud rate, report SPI status, hold an SPI
data match value, and for transmit/receive data.
Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address
assignments for all SPI registers. This section refers to registers and control bits only by their names, and
a Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
MCF51MM256 Series Devices Reference Manual, Rev. 3
22-6
Freescale Semiconductor
16-bit Serial Peripheral Interface (S08SPI16V5)
22.3.1
SPI Control Register 1 (SPIxC1)
This read/write register includes the SPI enable control, interrupt enables, and configuration options.
7
6
5
4
3
2
1
0
SPIE
SPE
SPTIE
MSTR
CPOL
CPHA
SSOE
LSBFE
0
0
0
0
0
1
0
0
R
W
Reset
Figure 22-4. SPI Control Register 1 (SPIxC1)
Table 22-1. SPIxC1 Field Descriptions
Field
7
SPIE
Description
FIFOMODE=0
SPI Interrupt Enable (for SPRF and MODF) — This is the interrupt enable for SPI receive buffer full (SPRF)
and mode fault (MODF) events.
0 Interrupts from SPRF and MODF inhibited (use polling)
1 When SPRF or MODF is 1, request a hardware interrupt
FIFOMODE=1
SPI Read FIFO Full Interrupt Enable — This bit when set enables the SPI to interrupt the CPU when the
Receive FIFO is full. An interrupt will occur when SPRF flag is set or MODF is set.
0 Read FIFO Full Interrupts are disabled
1 Read FIFO Full Interrupts are enabled
6
SPE
SPI System Enable — This bit enables the SPI system and dedicates the SPI port pins to SPI system functions.
If SPE is cleared, SPI is disabled and forced into idle state, and all status bits in the SPIxS register are reset.
0 SPI system inactive
1 SPI system enabled
5
SPTIE
SPI Transmit Interrupt Enable —
FIFOMODE=0
This is the interrupt enable bit for SPI transmit buffer empty (SPTEF). An interrupt occurs when the SPI transmit
buffer is empty (SPTEF is set)
FIFOMODE=1
This is the interrupt enable bit for SPI transmit FIFO empty (SPTEF). An interrupt occurs when the SPI transmit
FIFO is empty (SPTEF is set)
0 Interrupts from SPTEF inhibited (use polling)
1 When SPTEF is 1, hardware interrupt requested
4
MSTR
Master/Slave Mode Select — This bit selects master or slave mode operation.
0 SPI module configured as a slave SPI device
1 SPI module configured as a master SPI device
3
CPOL
Clock Polarity — This bit selects an inverted or non-inverted SPI clock. To transmit data between SPI modules,
the SPI modules must have identical CPOL values.
This bit effectively places an inverter in series with the clock signal from a master SPI or to a slave SPI device.
Refer to Section 22.4.6, “SPI Clock Formats” for more details.
0 Active-high SPI clock (idles low)
1 Active-low SPI clock (idles high)
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
22-7
16-bit Serial Peripheral Interface (S08SPI16V5)
Table 22-1. SPIxC1 Field Descriptions (Continued)
Field
Description
2
CPHA
Clock Phase — This bit selects one of two clock formats for different kinds of synchronous serial peripheral
devices. Refer to Section 22.4.6, “SPI Clock Formats” for more details.
0 First edge on SPSCK occurs at the middle of the first cycle of a data transfer
1 First edge on SPSCK occurs at the start of the first cycle of a data transfer
1
SSOE
Slave Select Output Enable — This bit is used in combination with the mode fault enable (MODFEN) bit in
SPIxC2 and the master/slave (MSTR) control bit to determine the function of the SS pin as shown in Table 22-2.
0
LSBFE
LSB First (Shifter Direction) — This bit does not affect the position of the MSB and LSB in the data register.
Reads and writes of the data register always have the MSB in bit 7 (or bit 15 in 16-bit mode).
0 SPI serial data transfers start with most significant bit
1 SPI serial data transfers start with least significant bit
Table 22-2. SS Pin Function
22.3.2
MODFEN
SSOE
Master Mode
Slave Mode
0
0
General-purpose I/O (not SPI)
Slave select input
0
1
General-purpose I/O (not SPI)
Slave select input
1
0
SS input for mode fault
Slave select input
1
1
Automatic SS output
Slave select input
SPI Control Register 2 (SPIxC2)
This read/write register is used to control optional features of the SPI system. Bits 5 and 2 are not
implemented and always read 0.
7
6
5
SPMIE
SPIMODE
0
0
R
4
3
MODFEN
BIDIROE
0
0
0
2
1
0
SPISWAI
SPC0
0
0
0
W
Reset
0
0
= Unimplemented or Reserved
Figure 22-5. SPI Control Register 2 (SPIxC2)
MCF51MM256 Series Devices Reference Manual, Rev. 3
22-8
Freescale Semiconductor
16-bit Serial Peripheral Interface (S08SPI16V5)
Table 22-3. SPIxC2 Register Field Descriptions
Field
7
SPMIE
Description
SPI Match Interrupt Enable — This is the interrupt enable for the SPI receive data buffer hardware match
(SPMF) function.
0 Interrupts from SPMF inhibited (use polling).
1 When SPMF = 1, requests a hardware interrupt.
6
SPIMODE
SPI 8- or 16-bit Mode — This bit allows the user to select either an 8-bit or 16-bit SPI data transmission length.
In master mode, a change of this bit will abort a transmission in progress, force the SPI system into idle state,
and reset all status bits in the SPIxS register. Refer to section Section 22.4.5, “Data Transmission Length,” for
details.
0 8-bit SPI shift register, match register, and buffers.
1 16-bit SPI shift register, match register, and buffers.
4
MODFEN
Master Mode-Fault Function Enable — When the SPI is configured for slave mode, this bit has no meaning or
effect. (The SS pin is the slave select input.) In master mode, this bit determines how the SS pin is used (refer to
Table 22-2 for details)
0 Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI
1 Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output
3
BIDIROE
Bidirectional Mode Output Enable — When bidirectional mode is enabled by SPI pin control 0 (SPC0) = 1,
BIDIROE determines whether the SPI data output driver is enabled to the single bidirectional SPI I/O pin.
Depending on whether the SPI is configured as a master or a slave, it uses either the MOSI (MOMI) or MISO
(SISO) pin, respectively, as the single SPI data I/O pin. When SPC0 = 0, BIDIROE has no meaning or effect.
0 Output driver disabled so SPI data I/O pin acts as an input
1 SPI I/O pin enabled as an output
1
SPISWAI
SPI Stop in Wait Mode — This bit is used for power conservation while in wait.
0 SPI clocks continue to operate in wait mode
1 SPI clocks stop when the MCU enters wait mode
0
SPC0
SPI Pin Control 0 — This bit enables bidirectional pin configurations as shown in Table 22-4.
0 SPI uses separate pins for data input and data output.
1 SPI configured for single-wire bidirectional operation.
Table 22-4. Bidirectional Pin Configurations
Pin Mode
SPC0
BIDIROE
MISO
MOSI
Master Mode of Operation
Normal
0
X
Master In
Master Out
Bidirectional
1
0
MISO not used by SPI
Master In
1
Master I/O
Slave Mode of Operation
Normal
0
X
Slave Out
Slave In
Bidirectional
1
0
Slave In
MOSI not used by SPI
1
Slave I/O
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
22-9
16-bit Serial Peripheral Interface (S08SPI16V5)
22.3.3
SPI Baud Rate Register (SPIxBR)
This register is used to set the prescaler and bit rate divisor for an SPI master. This register may be read or
written at any time.
7
R
6
5
4
3
2
1
0
SPPR2
SPPR1
SPPR0
SPR3
SPR2
SPR1
SPR0
0
0
0
0
0
0
0
0
W
Reset
0
= Unimplemented or Reserved
Figure 22-6. SPI Baud Rate Register (SPIxBR)
Table 22-5. SPIxBR Register Field Descriptions
Field
Description
6:4
SPPR[2:0]
SPI Baud Rate Prescale Divisor — This 3-bit field selects one of eight divisors for the SPI baud rate prescaler
as shown in Table 22-6. The input to this prescaler is the bus rate clock (BUSCLK). The output of this prescaler
drives the input of the SPI baud rate divider (see Figure 22-19). See Section 22.4.7, “SPI Baud Rate Generation,”
for details.
3:0
SPR[3:0]
SPI Baud Rate Divisor — This 4-bit field selects one of nine divisors for the SPI baud rate divider as shown in
Table 22-7. The input to this divider comes from the SPI baud rate prescaler (see Figure 22-19). See Section
22.4.7, “SPI Baud Rate Generation,” for details.
Table 22-6. SPI Baud Rate Prescaler Divisor
SPPR2:SPPR1:SPPR0
Prescaler Divisor
0:0:0
1
0:0:1
2
0:1:0
3
0:1:1
4
1:0:0
5
1:0:1
6
1:1:0
7
1:1:1
8
MCF51MM256 Series Devices Reference Manual, Rev. 3
22-10
Freescale Semiconductor
16-bit Serial Peripheral Interface (S08SPI16V5)
Table 22-7. SPI Baud Rate Divisor
22.3.4
SPR3:SPR2:SPR1:SPR0
Rate Divisor
0:0:0:0
2
0:0:0:1
4
0:0:1:0
8
0:0:1:1
16
0:1:0:0
32
0:1:0:1
64
0:1:1:0
128
0:1:1:1
256
1:0:0:0
512
All other combinations
Reserved
SPI Status Register (SPIxS)
This register has eight read-only status bits. Writes have no meaning or effect.
R
7
6
5
4
3
2
1
0
SPRF
SPMF
SPTEF
MODF
RNFULLF
TNEAREF
TXFULLF
RFIFOEF
0
0
1
0
0
01
0
01
W
Reset
= Unimplemented or Reserved
Figure 22-7. SPI Status Register (SPIxS)
1
Note: PoR values of TNEAREF and RFIFOEF is 0. If status register is reset due to change of SPIMODE, FIFOMODE or SPE
than, if FIFOMODE = 1, TNEAREF and RFIFOEF resets to 1 else if FIFOMODE = 0, TNEAREF and RFIFOEF resets to 0
This register has 4 additional flags RNFULLF, TNEARF, TXFULLF and RFIFOEF which provide
mechanisms to support an 8-byte FIFO mode. When in 8-byte FIFO mode, the function of SPRF and
SPTEF differ slightly from the normal buffered modes, mainly in how these flags are cleared by the
amount available in the transmit and receive FIFOs.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
22-11
16-bit Serial Peripheral Interface (S08SPI16V5)
Table 22-8. SPIxS Register Field Descriptions
Field
Description
7
SPRF
SPI Read Buffer Full Flag — SPRF is set at the completion of an SPI transfer to indicate that received data may
be read from the SPI data register (SPIxDH:SPIxDL). SPRF is cleared by reading SPRF while it is set, then
reading the SPI data register.
0 No data available in the receive data buffer.
1 Data available in the receive data buffer.
FIFOMODE=1
SPI Read FIFO FULL Flag — This bit indicates the status of the Read FIFO when FIFOMODE enabled. The
SPRF is set when the read FIFO has received 64bits (4 words or 8 bytes) of data from the shifter and there has
been no CPU reads of SPIxDH:SPIxDL. SPRF is cleared by reading the SPI Data Register, which empties the
FIFO, assuming another SPI message is not received.
0 Read FIFO is not Full
1 Read FIFO is Full.
6
SPMF
SPI Match Flag — SPMF is set after SPRF = 1 when the value in the receive data buffer matches the value in
SPIxMH:SPIxML. To clear the flag, read SPMF when it is set, then write a 1 to it.
0 Value in the receive data buffer does not match the value in SPIxMH:SPIxML registers.
1 Value in the receive data buffer matches the value in SPIxMH:SPIxML registers.
5
SPTEF
SPI Transmit Buffer Empty Flag — This bit is set when the transmit data buffer is empty. It is cleared by reading
SPIxS with SPTEF set, followed by writing a data value to the transmit buffer at SPIxDH:SPIxDL. SPIxS must be
read with SPTEF = 1 before writing data to SPIxDH:SPIxDL or the SPIxDH:SPIxDL write will be ignored. SPTEF
is automatically set when all data from the transmit buffer transfers into the transmit shift register. For an idle SPI,
data written to SPIxDH:SPIxDL is transferred to the shifter almost immediately so SPTEF is set within two bus
cycles allowing a second data to be queued into the transmit buffer. After completion of the transfer of the data
in the shift register, the queued data from the transmit buffer will automatically move to the shifter and SPTEF will
be set to indicate there is room for new data in the transmit buffer. If no new data is waiting in the transmit buffer,
SPTEF simply remains set and no data moves from the buffer to the shifter.
0 SPI transmit buffer not empty
1 SPI transmit buffer empty
FIFOMODE=1
SPI Transmit FIFO Empty Flag — This bit when in FIFOMODE now changed to provide status of the FIFO
rather than an 8or16-bit buffer. This bit is set when the Transmit FIFO is empty. It is cleared by writing a data value
to the transmit FIFO at SPIxDH:SPIxDL. SPTEF is automatically set when all data from transmit FIFO transfers
into the transmit shift register. For an idle SPI, data written to SPIxDH:SPIxDL is transferred to the shifter almost
immediately so SPTEF is set within two bus cycles, a second write of data to the SPIxDH:SPIxDL will clear this
SPTEF flag. After completion of the transfer of the data in the shift register, the queued data from the transmit
FIFO will automatically move to the shifter and SPTEF will be set only when all data written to the transmit FIFO
has been transferred to the shifter. If no new data is waiting in the transmit FIFO, SPTEF simply remains set and
no data moves from the buffer to the shifter.
0 SPI FIFO not empty
1 SPI FIFO empty
4
MODF
Master Mode Fault Flag — MODF is set if the SPI is configured as a master and the slave select input goes low,
indicating some other SPI device is also configured as a master. The SS pin acts as a mode fault error input only
when MSTR = 1, MODFEN = 1, and SSOE = 0; otherwise, MODF will never be set. MODF is cleared by reading
MODF while it is 1, then writing to SPI control register 1 (SPIxC1).
0 No mode fault error
1 Mode fault error detected
MCF51MM256 Series Devices Reference Manual, Rev. 3
22-12
Freescale Semiconductor
16-bit Serial Peripheral Interface (S08SPI16V5)
Table 22-8. SPIxS Register Field Descriptions
Field
Description
3
RNFULLF
Receive FIFO Nearly Full Flag — This flag is set when more than three16bit words or six 8bit bytes of data
remain in the receive FIFO provided SPIxC3[4] = 0 or when more than two 16bit words or four 8bit bytes of data
remain in the receive FIFO provided SPIxC3[4] = 1. It has no function if FIFOMODE=0.
0 Receive FIFO has received less than 48bits/32bits (See SPIxC3[4]).
1 Receive FIFO has received 48bits/32bits(See SPIxC3[4]) or more.
2
TNEAREF
Transmit FIFO Nearly Empty Flag — This flag is set when only one 16bit word or 2 8bit bytes of data remain in
the transmit FIFO provided SPIxC3[5] = 0 or when only two 16bit words or 4 8bit bytes of data remain in the
transmit FIFO provided SPIxC3[5] =1. If FIFOMODE is not enabled this bit should be ignored.
0 Transmit FIFO has more than 16bits/32bits (See SPIxC3[5]) left to transmit.
1 Transmit FIFO has 16bits/32 bits (See SPIxC3[5])or less left to transmit
1
TXFULLF
Transmit FIFO Full Flag - This bit indicates status of transmit FIFO when FIFO mode is enabled. This flag is set
when there are 8 bytes in transmit FIFO. If FIFOMODE is not enabled this bit should be ignored.
0 Transmit FIFO has less than 8 bytes.
1 Transmit FIFO has 8 bytes of data.
0
RFIFOEF
SPI Read FIFO Empty Flag — This bit indicates the status of the Read FIFO when FIFOMODE enabled. If
FIFOMODE is not enabled this bit should be ignored.
0 Read FIFO has data. Reads of the SPIxDH:SPIxDL registers in 16-bit mode or SPIxDL register in 8-bit mode
will empty the Read FIFO.
1 Read FIFO is empty.
For FIFO management there are two other important flags that are used to help make the operation more
efficient when transferring large amounts of data. These are the Receive FIFO Nearly Full Flag
(RNFULLF) and the Transmit FIFO Nearly Empty Flag (TNEAREF). Both these flags provide a
“watermark” feature of the FIFOs to allow continuous transmissions of data when running at high speed.
The RNFULLF flag can generate an interrupt if the RNFULLIEN bit in the SPIxC3 Register is set which
allows the CPU to start emptying the Receive FIFO without delaying the reception of subsequent bytes.
The user can also determine if all data in Receive FIFO has been read by monitoring the RFIFOEF flag.
The TNEAREF flag can generate an interrupt if the TNEARIEN bit n the SPIxC3 Register is set which
allows the CPU to start filling the Transmit FIFO before it is empty and thus provide a mechanism to have
no breaks in SPI transmission.
NOTE
SPIxS and both TX and RX FIFOs gets reset due to change in SPIMODE,
FIFOMODE or SPE. PoR values of SPIxS are show in Figure 22-7 and
Figure 22-8.
Figure 22-7 and Figure 22-8 shows the reset values due to change of modes after PoR.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
22-13
16-bit Serial Peripheral Interface (S08SPI16V5)
R
7
6
5
4
3
2
1
0
SPRF
SPMF
SPTEF
MODF
RNFULLF
TNEAREF
TXFULLF
RFIFOEF
0
0
1
0
0
0
0
0
W
Reset
Figure 22-8. Reset values of SPIxS after PoR with FIFOMODE = 0
R
7
6
5
4
3
2
1
0
SPRF
SPMF
SPTEF
MODF
RNFULLF
TNEAREF
TXFULLF
RFIFOEF
0
0
1
0
0
1
0
1
W
Reset
Figure 22-9. Reset values of SPIxS after PoR with FIFOMODE = 1
22.3.5
SPI Data Registers (SPIxDH:SPIxDL)
7
6
5
4
3
2
1
0
Bit 15
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
0
R
W
Reset
Figure 22-10. SPI Data Register High (SPIxDH)
7
6
5
4
3
2
1
0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 22-11. SPI Data Register Low (SPIxDL)
The SPI data registers (SPIxDH:SPIxDL) are both the input and output register for SPI data. A write to
these registers writes to the transmit data buffer, allowing data to be queued and transmitted.
When the SPI is configured as a master, data queued in the transmit data buffer is transmitted immediately
after the previous transmission has completed.
The SPI transmit buffer empty flag (SPTEF) in the SPIxS register indicates when the transmit data buffer
is ready to accept new data. SPIxS must be read when SPTEF is set before writing to the SPI data registers,
or the write will be ignored.
MCF51MM256 Series Devices Reference Manual, Rev. 3
22-14
Freescale Semiconductor
16-bit Serial Peripheral Interface (S08SPI16V5)
Data may be read from SPIxDH:SPIxDL any time after SPRF is set and before another transfer is finished.
Failure to read the data out of the receive data buffer before a new transfer ends causes a receive overrun
condition and the data from the new transfer is lost.
In 8-bit mode, only SPIxDL is available. Reads of SPIxDH will return all 0s. Writes to SPIxDH will be
ignored.
In 16-bit mode, reading either byte (SPIxDH or SPIxDL) latches the contents of both bytes into a buffer
where they remain latched until the other byte is read. Writing to either byte (SPIxDH or SPIxDL) latches
the value into a buffer. When both bytes have been written, they are transferred as a coherent 16-bit value
into the transmit data buffer.
22.3.6
SPI Match Registers (SPIxMH:SPIxML)
These read/write registers contain the hardware compare value, which sets the SPI match flag (SPMF)
when the value received in the SPI receive data buffer equals the value in the SPIxMH:SPIxML registers.
In 8-bit mode, only SPIxML is available. Reads of SPIxMH will return all 0s. Writes to SPIxMH will be
ignored.
In 16-bit mode, reading either byte (SPIxMH or SPIxML) latches the contents of both bytes into a buffer
where they remain latched until the other byte is read. Writing to either byte (SPIxMH or SPIxML) latches
the value into a buffer. When both bytes have been written, they are transferred as a coherent value into
the SPI match registers.
7
6
5
4
3
2
1
0
Bit 15
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
0
R
W
Reset
Figure 22-12. SPI Match Register High (SPIxMH)
7
6
5
4
3
2
1
0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 22-13. SPI Match Register Low (SPIxML)
22.3.7
SPI Control Register 3 (SPIxC3) — enable FIFO feature
The SPI Control Register 3 introduces a 64-bit FIFO function on both transmit and receive buffers to be
utilized on the SPI. Utilizing this FIFO feature allows the SPI to provide high speed transfers of large
amounts of data without consuming large amounts of the CPU bandwidth.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
22-15
16-bit Serial Peripheral Interface (S08SPI16V5)
Enabling this FIFO function will effect the behavior of some of the Read/Write Buffer flags in the SPIxS
register namely:
• The SPRF of the SPIxS register will be set when the Receive FIFO is filled and will interrupt the
CPU if the SPIE in the SPIxC1 register is set.
and
•
The SPTEF of the SPIxS register will be set when the Transmit FIFO is empty, and will interrupt
the CPU if the SPTIE bit is set in the SPIxC1 register. See SPIxC1 and SPIxS registers.
FIFO mode is enabled by setting the FIFOMODE bit, and provides the SPI with an 8-byte receive FIFO
and an 8-byte transmit FIFO to reduce the amount of CPU interrupts for high speed/high volume data
transfers.
Two interrupt enable bits TNEARIEN and RNFULLIEN provide CPU interrupts based on the
“watermark” feature of the TNEARF and RNFULLF flags of the SPIxS register.
Note: This register has six read/write control bits. Bits 7 through 6 are not implemented and always read 0. Writes have no
meaning or effect. Write to this register happens only when FIFOMODE bit is 1.
R
7
6
5
4
3
2
1
0
0
0
TNEAREF
MARK
RNFULL
MARK
INTCLR
TNEARIEN
RNFULLIEN
FIFOMODE
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 22-14. SPI Control Register (SPIxC3S)
Table 22-9. SPIxC3S Register Field Descriptions
Field
Description
5
TNEAREF
MARK
Transmit FIFO Nearly Empty Water Mark — This bit selects the mark after which TNEAREF flag is asserted.
0 TNEAREF is set when Transmit FIFO has16bits or less.
1 TNEAREF is set when Transmit FIFO has 32bits or less.
4
RNFULLF
MARK
Receive FIFO Nearly Full Water Mark — This bit selects the mark for which RNFULLF flag is asserted
0 RNFULLF is set when Receive FIFO has 48bits or more
1 RNFULLF is set when Receive FIFO has 32bits or more.
3
INTCLR
Interrupt Clearing Mechanism Select — This bit selects the mechanism by which SPRF, SPTEF, TNEAREF,
RNFULLF interrupts gets cleared.
0 Interrupts gets cleared when respective flags gets cleared depending on the state of FIFOs
1 Interrupts gets cleared by writing to the SPIxCI respective bits.
2
TNEARIEN
Transmit FIFO Nearly Empty Interrupt Enable — Writing to this bit enables the SPI to interrupt the CPU when
the TNEAREF flag is set. This is an additional interrupt on the SPI and will only interrupt the CPU if SPTIE in the
SPIxC1 register is also set. This bit is ignored and has no function if FIFOMODE=0.
0 No interrupt on Transmit FIFO Nearly Empty Flag being set.
1 Enable interrupts on Transmit FIFO Nearly Empty Flag being set.
MCF51MM256 Series Devices Reference Manual, Rev. 3
22-16
Freescale Semiconductor
16-bit Serial Peripheral Interface (S08SPI16V5)
Table 22-9. SPIxC3S Register Field Descriptions
Field
Description
1
Receive FIFO Nearly Full Interrupt Enable — Writing to this bit enables the SPI to interrupt the CPU when the
RNFULLIEN RNEARFF flag is set. This is an additional interrupt on the SPI and will only interrupt the CPU if SPIE in the
SPIxC1 register is also set. This bit is ignored and has no function if FIFOMODE=0.
0 No interrupt on RNEARFF being set.
1 Enable interrupts on RNEARFF being set.
0
SPI FIFO Mode Enable — This bit enables the SPI to utilize a 64bit FIFO (8 bytes 4 16-bit words) for both
FIFOMODE transmit and receive buffers.
0 Buffer mode disabled.
1 Data available in the receive data buffer.
22.3.8
SPI Clear Interrupt Register (SPIxCI)
The SPI Clear Interrupt register has 4 bits dedicated for clearing the interrupts. Writing 1 to these bits clears
the respective interrupts if INTCLR bit in SPIxCR3 is set.
It also have 2 bits to indicate the transmit FIFO and receive FIFO overrun conditions. When receive FIFO
is full and a data is received RXFOF flag is set. Similarly, when transmit FIFO is full and write happens
to SPIDR TXFOF is set. These flags get cleared when a read happens to this register with the flags set.
There are two more bits to indicate the error flags. These flags gets set when due to some spurious reasons
entries in FIFO becomes greater than 8. At this point all the flags in status register gets reset and entries in
FIFO are flushed with respective error flags set. These flags are cleared when a read happen at SPIxCI with
the error flags set.
Note: Bits [7:4] are read-only bits. These bits gets cleared when a read happens to this register with the flags set. Bits [3:0] are
clear interrupts bits which clears the interrupts by writing 1 to respective bits. Reading these bits always return 0.
R
7
6
5
4
3
TXFERR
RXFERR
TXFOF
RXFOF
2
TNEAREFCI RNFULLFCI
1
0
SPTEFCI
SPRFCI
0
0
W
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
Table 22-10. SPIxCI Register Field Descriptions
Field
Description
7
TXFERR
Transmit FIFO Error Flag- This flag indicates that TX FIFO error occurred because entries in FIFO goes above
8.
0 No TX FIFO error occurred.
1 TX FIFO error occurred.
6
RXFERR
Receive FIFO Error Flag- This flag indicates that RX FIFO error occurred because entries in FIFO goes above 8.
0 No RX FIFO error occurred.
1 RX FIFO error occurred.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
22-17
16-bit Serial Peripheral Interface (S08SPI16V5)
Table 22-10. SPIxCI Register Field Descriptions
Field
Description
5
TXFOF
TX FIFO Overflow Flag- This Flag indicates that TX FIFO overflow condition has occurred.
0 TX FIFO overflow condition has not occurred.
1 TX FIFO overflow condition occurred.
4
RXFOF
RX FIFO Overflow Flag - This Flag indicates that RX FIFO overflow condition has occurred.
0 RX FIFO overflow condition has not occurred.
1 RX FIFO overflow condition occurred.
3
Transmit FIFO Nearly Empty Flag Clear Interrupt Register — Write of 1 clears the TNEAREF interrupt
TNEAREFCI provided SPIxC3[3] is set.
2
Receive FIFO Nearly Full Flag Clear Interrupt Register — Write of 1 clears the RNFULLF interrupt provided
RNFULLFCI SPIxC3[3] is set.
1
SPTEFCI
Transmit FIFO Empty Flag Clear Interrupt Register — Write of 1 clears the SPTEF interrupt provided
SPIxC3[3] is set.
0
SPRFCI
Receive FIFO Full Flag Clear Interrupt Register — Write of 1 clears the TNEAREF interrupt provided
SPIxC3[3] is set.
22.4
22.4.1
Functional Description
General
The SPI system is enabled by setting the SPI enable (SPE) bit in SPI Control Register 1. While the SPE
bit is set, the four associated SPI port pins are dedicated to the SPI function as:
• Slave select (SS)
• Serial clock (SPSCK)
• Master out/slave in (MOSI)
• Master in/slave out (MISO)
An SPI transfer is initiated in the master SPI device by reading the SPI status register (SPIxS) when
SPTEF = 1 and then writing data to the transmit data buffer (write to SPIxDH:SPIxDL). When a transfer
is complete, received data is moved into the receive data buffer. The SPIxDH:SPIxDL registers act as the
SPI receive data buffer for reads and as the SPI transmit data buffer for writes.
The clock phase control bit (CPHA) and a clock polarity control bit (CPOL) in the SPI Control Register 1
(SPIxC1) select one of four possible clock formats to be used by the SPI system. The CPOL bit simply
selects a non-inverted or inverted clock. The CPHA bit is used to accommodate two fundamentally
different protocols by sampling data on odd numbered SPSCK edges or on even numbered SPSCK edges.
The SPI can be configured to operate as a master or as a slave. When the MSTR bit in SPI control register
1 is set, master mode is selected, when the MSTR bit is clear, slave mode is selected.
22.4.2
Master Mode
The SPI operates in master mode when the MSTR bit is set. Only a master SPI module can initiate
transmissions. A transmission begins by reading the SPIxS register while SPTEF = 1 and writing to the
MCF51MM256 Series Devices Reference Manual, Rev. 3
22-18
Freescale Semiconductor
16-bit Serial Peripheral Interface (S08SPI16V5)
master SPI data registers. If the shift register is empty, the byte immediately transfers to the shift register.
The data begins shifting out on the MOSI pin under the control of the serial clock.
• SPSCK
The SPR3, SPR2, SPR1, and SPR0 baud rate selection bits in conjunction with the SPPR2, SPPR1, and
SPPR0 baud rate preselection bits in the SPI Baud Rate register control the baud rate generator and
determine the speed of the transmission. The SPSCK pin is the SPI clock output. Through the SPSCK pin,
the baud rate generator of the master controls the shift register of the slave peripheral.
• MOSI, MISO pin
In master mode, the function of the serial data output pin (MOSI) and the serial data input pin (MISO) is
determined by the SPC0 and BIDIROE control bits.
• SS pin
If MODFEN and SSOE bit are set, the SS pin is configured as slave select output. The SS output becomes
low during each transmission and is high when the SPI is in idle state.
If MODFEN is set and SSOE is cleared, the SS pin is configured as input for detecting mode fault error.
If the SS input becomes low this indicates a mode fault error where another master tries to drive the MOSI
and SPSCK lines. In this case, the SPI immediately switches to slave mode, by clearing the MSTR bit and
also disables the slave output buffer MISO (or SISO in bidirectional mode). So the result is that all outputs
are disabled and SPSCK, MOSI and MISO are inputs. If a transmission is in progress when the mode fault
occurs, the transmission is aborted and the SPI is forced into idle state.
This mode fault error also sets the mode fault (MODF) flag in the SPI Status Register (SPIxS). If the SPI
interrupt enable bit (SPIE) is set when the MODF flag gets set, then an SPI interrupt sequence is also
requested.
When a write to the SPI Data Register in the master occurs, there is a half SPSCK-cycle delay. After the
delay, SPSCK is started within the master. The rest of the transfer operation differs slightly, depending on
the clock format specified by the SPI clock phase bit, CPHA, in SPI Control Register 1 (see Section 22.4.6,
“SPI Clock Formats).
NOTE
A change of the bits CPOL, CPHA, SSOE, LSBFE, MODFEN, SPC0,
BIDIROE with SPC0 set, SPIMODE, FIFOMODE, SPPR2-SPPR0 and
SPR3-SPR0 in master mode will abort a transmission in progress and force
the SPI into idle state. The remote slave cannot detect this, therefore the
master has to ensure that the remote slave is set back to idle state.
22.4.3
Slave Mode
The SPI operates in slave mode when the MSTR bit in SPI Control Register1 is clear.
• SPSCK
In slave mode, SPSCK is the SPI clock input from the master.
• MISO, MOSI pin
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
22-19
16-bit Serial Peripheral Interface (S08SPI16V5)
In slave mode, the function of the serial data output pin (MISO) and serial data input pin (MOSI) is
determined by the SPC0 bit and BIDIROE bit in SPI Control Register 2.
• SS pin
The SS pin is the slave select input. Before a data transmission occurs, the SS pin of the slave SPI must
be low. SS must remain low until the transmission is complete. If SS goes high, the SPI is forced into idle
state.
The SS input also controls the serial data output pin, if SS is high (not selected), the serial data output pin
is high impedance, and, if SS is low the first bit in the SPI Data Register is driven out of the serial data
output pin. Also, if the slave is not selected (SS is high), then the SPSCK input is ignored and no internal
shifting of the SPI shift register takes place.
Although the SPI is capable of duplex operation, some SPI peripherals are capable of only receiving SPI
data in a slave mode. For these simpler devices, there is no serial data out pin.
NOTE
When peripherals with duplex capability are used, take care not to
simultaneously enable two receivers whose serial outputs drive the same
system slave’s serial data output line.
As long as no more than one slave device drives the system slave’s serial data output line, it is possible for
several slaves to receive the same transmission from a master, although the master would not receive return
information from all of the receiving slaves.
If the CPHA bit in SPI Control Register 1 is clear, odd numbered edges on the SPSCK input cause the data
at the serial data input pin to be latched. Even numbered edges cause the value previously latched from the
serial data input pin to shift into the LSB or MSB of the SPI shift register, depending on the LSBFE bit.
If the CPHA bit is set, even numbered edges on the SPSCK input cause the data at the serial data input pin
to be latched. Odd numbered edges cause the value previously latched from the serial data input pin to shift
into the LSB or MSB of the SPI shift register, depending on the LSBFE bit.
When CPHA is set, the first edge is used to get the first data bit onto the serial data output pin. When CPHA
is clear and the SS input is low (slave selected), the first bit of the SPI data is driven out of the serial data
output pin. After the eighth (SPIMODE = 0) or sixteenth (SPIMODE = 1) shift, the transfer is considered
complete and the received data is transferred into the SPI data registers. To indicate transfer is complete,
the SPRF flag in the SPI Status Register is set.
NOTE
A change of the bits CPOL, CPHA, SSOE, LSBFE, MODFEN, SPC0 and
BIDIROE with SPC0 set FIFOMODE and SPIMODE in slave mode will
corrupt a transmission in progress and has to be avoided.
MCF51MM256 Series Devices Reference Manual, Rev. 3
22-20
Freescale Semiconductor
16-bit Serial Peripheral Interface (S08SPI16V5)
22.4.4
SPI FIFO MODE
IPBus (ips_rdata[7:0])
Read Access
SPI_REG_BLOCK
spidh:l_rx_reg
SPI Data Register
FIFO depth = 8 bytes
RX- FIFO
FIFO Ctrlr
SPI_CORE_SHFR
Load
Control
shfr_rx_reg
Figure 22-15. SPIH:L read side structural overview in FIFO mode
IPBus (ips_rdata[7:0])
Read Access
SPI_REG_BLOCK
SPI Data Register
spidh:l_tx_reg
TX- FIFO
FIFO Ctrlr
FIFO depth = 8 bytes
SPI_CORE_SHFR
Read
Control
shfr_tx_reg
Figure 22-16. SPIH:L write side structural overview in FIFO mode
SPI works in FIFO mode when SPIxC3[0] bit is set. When in FIFO mode SPI RX buffer and SPI TX buffer
is replaced by a 8 byte deep FIFO as shown in figure above.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
22-21
16-bit Serial Peripheral Interface (S08SPI16V5)
22.4.5
Data Transmission Length
The SPI can support data lengths of 8 or 16 bits. The length can be configured with the SPIMODE bit in
the SPIxC2 register.
In 8-bit mode (SPIMODE = 0), the SPI Data Register is comprised of one byte: SPIxDL. The SPI Match
Register is also comprised of only one byte: SPIxML. Reads of SPIxDH and SPIxMH will return zero.
Writes to SPIxDH and SPIxMH will be ignored.
In 16-bit mode (SPIMODE = 1), the SPI Data Register is comprised of two bytes: SPIxDH and SPIxDL.
Reading either byte (SPIxDH or SPIxDL) latches the contents of both bytes into a buffer where they
remain latched until the other byte is read. Writing to either byte (SPIxDH or SPIxDL) latches the value
into a buffer. When both bytes have been written, they are transferred as a coherent 16-bit value into the
transmit data buffer.
In 16-bit mode, the SPI Match Register is also comprised of two bytes: SPIxMH and SPIxML. There is no
buffer mechanism for the reading of SPIxMH and SPIxML since they can only be changed by writing at
CPU side. Writing to either byte (SPIxMH or SPIxML) latches the value into a buffer. When both bytes
have been written, they are transferred as a coherent 16-bit value into the transmit data buffer.
Any switching between 8- and 16-bit data transmission length (controlled by SPIMODE bit) in master
mode will abort a transmission in progress, force the SPI system into idle state, and reset all status bits in
the SPIxS register. To initiate a transfer after writing to SPIMODE, the SPIxS register must be read with
SPTEF = 1, and data must be written to SPIxDH:SPIxDL in 16-bit mode (SPIMODE = 1) or SPIxDL in
8-bit mode (SPIMODE = 0).
In slave mode, user software should write to SPIMODE only once to prevent corrupting a transmission in
progress.
NOTE
Data can be lost if the data length is not the same for both master and slave
devices.
22.4.6
SPI Clock Formats
To accommodate a wide variety of synchronous serial peripherals from different manufacturers, the SPI
system has a clock polarity (CPOL) bit and a clock phase (CPHA) control bit to select one of four clock
formats for data transfers. CPOL selectively inserts an inverter in series with the clock. CPHA chooses
between two different clock phase relationships between the clock and data.
Figure 22-17 shows the clock formats when SPIMODE = 0 (8-bit mode) and CPHA = 1. At the top of the
figure, the eight bit times are shown for reference with bit 1 starting at the first SPSCK edge and bit 8
ending one-half SPSCK cycle after the eighth SPSCK edge. The MSB first and LSB first lines show the
order of SPI data bits depending on the setting in LSBFE. Both variations of SPSCK polarity are shown,
but only one of these waveforms applies for a specific transfer, depending on the value in CPOL. The
SAMPLE IN waveform applies to the MOSI input of a slave or the MISO input of a master. The MOSI
waveform applies to the MOSI output pin from a master and the MISO waveform applies to the MISO
output from a slave. The SS OUT waveform applies to the slave select output from a master (provided
MODFEN and SSOE = 1). The master SS output goes to active low one-half SPSCK cycle before the start
MCF51MM256 Series Devices Reference Manual, Rev. 3
22-22
Freescale Semiconductor
16-bit Serial Peripheral Interface (S08SPI16V5)
of the transfer and goes back high at the end of the eighth bit time of the transfer. The SS IN waveform
applies to the slave select input of a slave.
BIT TIME #
(REFERENCE)
1
2
...
6
7
8
BIT 7
BIT 0
BIT 6
BIT 1
...
...
BIT 2
BIT 5
BIT 1
BIT 6
BIT 0
BIT 7
SPSCK
(CPOL = 0)
SPSCK
(CPOL = 1)
SAMPLE IN
(MISO OR MOSI)
MOSI
(MASTER OUT)
MSB FIRST
LSB FIRST
MISO
(SLAVE OUT)
SS OUT
(MASTER)
SS IN
(SLAVE)
Figure 22-17. SPI Clock Formats (CPHA = 1)
When CPHA = 1, the slave begins to drive its MISO output when SS goes to active low, but the data is not
defined until the first SPSCK edge. The first SPSCK edge shifts the first bit of data from the shifter onto
the MOSI output of the master and the MISO output of the slave. The next SPSCK edge causes both the
master and the slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the
third SPSCK edge, the SPI shifter shifts one bit position which shifts in the bit value that was just sampled,
and shifts the second data bit value out the other end of the shifter to the MOSI and MISO outputs of the
master and slave, respectively. When CPHA = 1, the slave’s SS input is not required to go to its inactive
high level between transfers.
Figure 22-18 shows the clock formats when SPIMODE = 0 and CPHA = 0. At the top of the figure, the
eight bit times are shown for reference with bit 1 starting as the slave is selected (SS IN goes low), and bit
8 ends at the last SPSCK edge. The MSB first and LSB first lines show the order of SPI data bits depending
on the setting in LSBFE. Both variations of SPSCK polarity are shown, but only one of these waveforms
applies for a specific transfer, depending on the value in CPOL. The SAMPLE IN waveform applies to the
MOSI input of a slave or the MISO input of a master. The MOSI waveform applies to the MOSI output
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
22-23
16-bit Serial Peripheral Interface (S08SPI16V5)
pin from a master and the MISO waveform applies to the MISO output from a slave. The SS OUT
waveform applies to the slave select output from a master (provided MODFEN and SSOE = 1). The master
SS output goes to active low at the start of the first bit time of the transfer and goes back high one-half
SPSCK cycle after the end of the eighth bit time of the transfer. The SS IN waveform applies to the slave
select input of a slave.
BIT TIME #
(REFERENCE)
1
2
BIT 7
BIT 0
BIT 6
BIT 1
...
6
7
8
BIT 2
BIT 5
BIT 1
BIT 6
BIT 0
BIT 7
SPSCK
(CPOL = 0)
SPSCK
(CPOL = 1)
SAMPLE IN
(MISO OR MOSI)
MOSI
(MASTER OUT)
MSB FIRST
LSB FIRST
...
...
MISO
(SLAVE OUT)
SS OUT
(MASTER)
SS IN
(SLAVE)
Figure 22-18. SPI Clock Formats (CPHA = 0)
When CPHA = 0, the slave begins to drive its MISO output with the first data bit value (MSB or LSB
depending on LSBFE) when SS goes to active low. The first SPSCK edge causes both the master and the
slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the second SPSCK
edge, the SPI shifter shifts one bit position which shifts in the bit value that was just sampled and shifts the
second data bit value out the other end of the shifter to the MOSI and MISO outputs of the master and
slave, respectively. When CPHA = 0, the slave’s SS input must go to its inactive high level between
transfers.
22.4.7
SPI Baud Rate Generation
As shown in Figure 22-19, the clock source for the SPI baud rate generator is the bus clock. The three
prescale bits (SPPR2:SPPR1:SPPR0) choose a prescale divisor of 1, 2, 3, 4, 5, 6, 7, or 8. The three rate
select bits (SPR3:SPR2:SPR1:SPR0) divide the output of the prescaler stage by 2, 4, 8, 16, 32, 64, 128,
256 or 512 to get the internal SPI master mode bit-rate clock.
MCF51MM256 Series Devices Reference Manual, Rev. 3
22-24
Freescale Semiconductor
16-bit Serial Peripheral Interface (S08SPI16V5)
The baud rate generator is activated only when the SPI is in the master mode and a serial transfer is taking
place. In the other cases, the divider is disabled to decrease IDD current.
The baud rate divisor equation is as follows except those reserved combinations in Table 22-7:
BaudRateDivisor =  SPPR + 1   2
 SPR + 1 
The baud rate can be calculated with the following equation:
Baud Rate = BusClock  BaudRateDivisor
BUS CLOCK
PRESCALER
BAUD RATE DIVIDER
DIVIDE BY
1, 2, 3, 4, 5, 6, 7, or 8
DIVIDE BY
2, 4, 8, 16, 32, 64, 128, 256 or 512
SPPR2:SPPR1:SPPR0
SPR3:SPR2:SPR1:SPR0
MASTER
SPI
BIT RATE
Figure 22-19. SPI Baud Rate Generation
22.4.8
22.4.8.1
Special Features
SS Output
The SS output feature automatically drives the SS pin low during transmission to select external devices
and drives it high during idle to deselect external devices. When SS output is selected, the SS output pin
is connected to the SS input pin of the external device.
The SS output is available only in master mode during normal SPI operation by asserting the SSOE and
MODFEN bits as shown in Table 22-2.
The mode fault feature is disabled while SS output is enabled.
NOTE
Care must be taken when using the SS output feature in a multi-master
system since the mode fault feature is not available for detecting system
errors between masters.
22.4.8.2
Bidirectional Mode (MOMI or SISO)
The bidirectional mode is selected when the SPC0 bit is set in SPI Control Register 2 (see Section
Table 22-11., “Normal Mode and Bidirectional Mode.”) In this mode, the SPI uses only one serial data pin
for the interface with external device(s). The MSTR bit decides which pin to use. The MOSI pin becomes
the serial data I/O (MOMI) pin for the master mode, and the MISO pin becomes serial data I/O (SISO) pin
for the slave mode. The MISO pin in master mode and MOSI pin in slave mode are not used by the SPI.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
22-25
16-bit Serial Peripheral Interface (S08SPI16V5)
Table 22-11. Normal Mode and Bidirectional Mode
When SPE = 1
Master Mode MSTR = 1
Serial Out
Normal Mode
SPC0 = 0
SPI
SPI
Serial Out
MISO
Serial Out
SPI
MOSI
Serial In
MOSI
Serial In
Bidirectional Mode
SPC0 = 1
Slave Mode MSTR = 0
MOMI
MISO
Serial In
BIDIROE
SPI
BIDIROE
Serial In
Serial Out
SISO
.
The direction of each serial I/O pin depends on the BIDIROE bit. If the pin is configured as an output,
serial data from the shift register is driven out on the pin. The same pin is also the serial input to the shift
register.
The SPSCK is output for the master mode and input for the slave mode.
The SS is the input or output for the master mode, and it is always the input for the slave mode.
The bidirectional mode does not affect SPSCK and SS functions.
NOTE
In bidirectional master mode, with mode fault enabled, both data pins MISO
and MOSI can be occupied by the SPI, though MOSI is normally used for
transmissions in bidirectional mode and MISO is not used by the SPI. If a
mode fault occurs, the SPI is automatically switched to slave mode, in this
case MISO becomes occupied by the SPI and MOSI is not used. This has to
be considered, if the MISO pin is used for another purpose.
22.4.9
Error Conditions
The SPI has one error condition:
• Mode fault error
22.4.9.1
Mode Fault Error
If the SS input becomes low while the SPI is configured as a master, it indicates a system error where more
than one master may be trying to drive the MOSI and SPSCK lines simultaneously. This condition is not
MCF51MM256 Series Devices Reference Manual, Rev. 3
22-26
Freescale Semiconductor
16-bit Serial Peripheral Interface (S08SPI16V5)
permitted in normal operation, and the MODF bit in the SPI status register is set automatically provided
the MODFEN bit is set.
In the special case where the SPI is in master mode and MODFEN bit is cleared, the SS pin is not used by
the SPI. In this special case, the mode fault error function is inhibited and MODF remains cleared. In case
the SPI system is configured as a slave, the SS pin is a dedicated input pin. Mode fault error doesn’t occur
in slave mode.
If a mode fault error occurs the SPI is switched to slave mode, with the exception that the slave output
buffer is disabled. So SPSCK, MISO and MOSI pins are forced to be high impedance inputs to avoid any
possibility of conflict with another output driver. A transmission in progress is aborted and the SPI is
forced into idle state.
If the mode fault error occurs in the bidirectional mode for a SPI system configured in master mode, output
enable of the MOMI (MOSI in bidirectional mode) is cleared if it was set. No mode fault error occurs in
the bidirectional mode for the SPI system configured in slave mode.
The mode fault flag is cleared automatically by a read of the SPI Status Register (with MODF set) followed
by a write to SPI Control Register 1. If the mode fault flag is cleared, the SPI becomes a normal master or
slave again.
22.4.10 Low-power Mode Options
22.4.10.1 SPI in Run Mode
In run mode with the SPI system enable (SPE) bit in the SPI control register clear, the SPI system is in a
low-power, disabled state. SPI registers can still be accessed, but clocks to the core of this module are
disabled.
22.4.10.2 SPI in Wait Mode
SPI operation in wait mode depends upon the state of the SPISWAI bit in SPI Control Register 2.
• If SPISWAI is clear, the SPI operates normally when the CPU is in wait mode
• If SPISWAI is set, SPI clock generation ceases and the SPI module enters a power conservation
state when the CPU is in wait mode.
— If SPISWAI is set and the SPI is configured for master, any transmission and reception in
progress stops at wait mode entry. The transmission and reception resumes when the SPI exits
wait mode.
– If SPISWAI is set and the SPI is configured as a slave, any transmission and reception in
progress continues if the SPSCK continues to be driven from the master. This keeps the slave
synchronized to the master and the SPSCK.
If the master transmits data while the slave is in wait mode, the slave will continue to send out
data consistent with the operation mode at the start of wait mode (i.e., if the slave is currently
sending its SPIxDH:SPIxDL to the master, it will continue to send the same byte. Otherwise,
if the slave is currently sending the last data received byte from the master, it will continue to
send each previously receive data from the master byte).
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
22-27
16-bit Serial Peripheral Interface (S08SPI16V5)
NOTE
Care must be taken when expecting data from a master while the slave is in
wait or stop3 mode. Even though the shift register will continue to operate,
the rest of the SPI is shut down (i.e. a SPRF interrupt will not be generated
until exiting stop or wait mode). Also, the data from the shift register will
not be copied into the SPIxDH:SPIxDL registers until after the slave SPI has
exited wait or stop mode. A SPRF flag and SPIxDH:SPIxDL copy is only
generated if wait mode is entered or exited during a tranmission. If the slave
enters wait mode in idle mode and exits wait mode in idle mode, neither a
SPRF nor a SPIxDH:SPIxDL copy will occur.
22.4.10.3 SPI in Stop Mode
Stop3 mode is dependent on the SPI system. Upon entry to stop3 mode, the SPI module clock is disabled
(held high or low). If the SPI is in master mode and exchanging data when the CPU enters stop mode, the
transmission is frozen until the CPU exits stop mode. After stop, data to and from the external SPI is
exchanged correctly. In slave mode, the SPI will stay synchronized with the master.
The stop mode is not dependent on the SPISWAI bit.
In all other stop modes, the SPI module is completely disabled. After stop, all registers are reset to their
default values, and the SPI module must be re-initialized.
22.4.10.4 Reset
The reset values of registers and signals are described in Section 22.3, “Register Definition.” which details
the registers and their bit-fields.
• If a data transmission occurs in slave mode after reset without a write to SPIxDH:SPIxDL, it will
transmit garbage, or the data last received from the master before the reset.
• Reading from the SPIxDH:SPIxDL after reset will always read zeros.
22.4.10.5 Interrupts
The SPI only originates interrupt requests when the SPI is enabled (SPE bit in SPIxC1 set). The following
is a description of how the SPI makes a request and how the MCU should acknowledge that request. The
interrupt vector offset and interrupt priority are chip dependent.
22.4.11 SPI Interrupts
There are four flag bits, three interrupt mask bits, and one interrupt vector associated with the SPI system.
The SPI interrupt enable mask (SPIE) enables interrupts from the SPI receiver full flag (SPRF) and mode
fault flag (MODF). The SPI transmit interrupt enable mask (SPTIE) enables interrupts from the SPI
transmit buffer empty flag (SPTEF). The SPI match interrupt enable mask bit (SPIMIE) enables interrupts
from the SPI match flag (SPMF). When one of the flag bits is set, and the associated interrupt mask bit is
set, a hardware interrupt request is sent to the CPU. If the interrupt mask bits are cleared, software can poll
the associated flag bits instead of using interrupts. The SPI interrupt service routine (ISR) should check
MCF51MM256 Series Devices Reference Manual, Rev. 3
22-28
Freescale Semiconductor
16-bit Serial Peripheral Interface (S08SPI16V5)
the flag bits to determine what event caused the interrupt. The service routine should also clear the flag
bit(s) before returning from the ISR (usually near the beginning of the ISR).
22.4.11.1 MODF
MODF occurs when the master detects an error on the SS pin. The master SPI must be configured for the
MODF feature (see Table 22-2). Once MODF is set, the current transfer is aborted and the following bit is
changed:
• MSTR=0, The master bit in SPIxC1 resets.
The MODF interrupt is reflected in the status register MODF flag. Clearing the flag will also clear the
interrupt. This interrupt will stay active while the MODF flag is set. MODF has an automatic clearing
process which is described in Section 22.3.4, “SPI Status Register (SPIxS).”
22.4.11.2 SPRF
SPRF occurs when new data has been received and copied to the SPI receive data buffer. In 8-bit mode,
SPRF is set only after all 8 bits have been shifted out of the shift register and into SPIxDL. In 16-bit mode,
SPRF is set only after all 16 bits have been shifted out of the shift register and into SPIxDH:SPIxDL.
Once SPRF is set, it does not clear until it is serviced. SPRF has an automatic clearing process which is
described in Section 22.3.4, “SPI Status Register (SPIxS).” In the event that the SPRF is not serviced
before the end of the next transfer (i.e. SPRF remains active throughout another transfer), the latter
transfers will be ignored and no new data will be copied into the SPIxDH:SPIxDL.
22.4.11.3 SPTEF
SPTEF occurs when the SPI transmit buffer is ready to accept new data. In 8-bit mode, SPTEF is set only
after all 8 bits have been moved from SPIxDL into the shifter. In 16-bit mode, SPTEF is set only after all
16 bits have been moved from SPIxDH:SPIxDL into the shifter.
Once SPTEF is set, it does not clear until it is serviced. SPTEF has an automatic clearing process which is
described in Section 22.3.4, “SPI Status Register (SPIxS).
22.4.11.4 SPMF
SPMF occurs when the data in the receive data buffer is equal to the data in the SPI match register. In 8-bit
mode, SPMF is set only after bits 8–0 in the receive data buffer are determined to be equivalent to the value
in SPIxML. In 16-bit mode, SPMF is set after bits 15–0 in the receive data buffer are determined to be
equivalent to the value in SPIxMH:SPIxML.
22.4.11.5 TNEAREF
TNEAREF flag is set when only one 16bit words or 2 8bit bytes of data remain in the transmit FIFO
provided SPIxC3[5] = 0 or when only two 16bit words or 4 8bit bytes of data remain in the transmit FIFO
provided SPIxC3[5] =1. If FIFOMODE is not enabled this bit should be ignored.
MCF51MM256 Series Devices Reference Manual, Rev. 3
Freescale Semiconductor
22-29
16-bit Serial Peripheral Interface (S08SPI16V5)
Clearing of this interrupts depends on state of SPIxC3[3] and the status of TNEAREF as described Section
22.3.4, “SPI Status Register (SPIxS)
22.4.11.6 RNFULLF
RNFULLF is set when more than three16bit words or six 8bit bytes of data remain in the receive FIFO
provided SPIxC3[4] = 0 or when more than two 16bit words or four 8bit bytes of data remain in the receive
FIFO provided SPIxC3[4] = 1.
Clearing of this interrupts depends on state of SPIxC3[3] and the status of RNFULLF as described Section
22.3.4, “SPI Status Register (SPIxS)
22.5
Initialization/Application Information
22.5.1
22.5.1.1
SPI Module Initialization Example
Initialization Sequence
Before the SPI module can be used for communication, an initialization procedure must be carried out, as
follows:
1. Update control register 1 (SPIxC1) to enable the SPI and to control interrupt enables. This register
also sets the SPI as master or slave, determines clock phase and polarity, and configures the main
SPI options.
2. Update co