Features • Minimal External Circuitry Requirements, no RF Components on the PC Board Except • • • • • • • • • • • • Matching to the Receiver Antenna High Sensitivity, Especially at Low Data Rates SSO20 and SO20 package Fully Integrated VCO Supply Voltage 4.5 V to 5.5 V, Operating Temperature Range -40°C to 105°C Single-ended RF Input for Easy Adaptation to l/4 Antenna or Printed Antenna on PCB Low-cost Solution Due to High Integration Level Various Types of Protocols Supported (i.e., PWM, Manchester and Biphase) Distinguishes the Signal Strength of Several Transmitters via RSSI (Received Signal Strength Indicator) ESD Protection According to MIL-STD. 883 (4KV HBM) High Image Frequency Suppression Due to 1 MHz IF in Conjunction with a SAW Frontend Filter, up to 40 dB is thereby Achievable with Newer SAWs Power Management (Polling) is Possible by Means of a Separate Pin via the Microcontroller Receiving Bandwidth BIF = 600 kHz UHF ASK Receiver T5744 Description The T5744 is a PLL receiver device for the receiving range of f 0 = 300 MHz to 450 MHz. It is developed for the demands of RF low-cost data communication systems with low data rates and fits for most types of modulation schemes including Manchester, Biphase and most PWM protocols. Its main applications are in the areas of telemetering, security technology and keyless-entry systems. Figure 1. System Block Diagram UHF ASK/FSK Remote control transmitter 1 Li cell UHF ASK Remote control receiver T5744 U2741B Data interface Demod. Keys Encoder M44Cx9x 1...3 µC PLL IF Amp Antenna Antenna XTO VCO Power amp. PLL LNA XTO VCO Rev. 4521B–RKE–01/03 1 Pin Configuration DVCC XTO LFGND LF LFVCC 14 13 12 11 7 8 9 n.c. 10 MODE 16 5 15 RSSI 17 4 6 TEST 18 3 LNA_IN LNAGND MIXVCC DGND AGND AVCC CDEM BR_1 BR_0 1 T5744 ENABLE 19 2 20 DATA Figure 2. Pinning SO20 and SSO20 Pin Description 2 Pin Symbol Function 1 BR_0 Baud rate select LSB 2 BR_1 Baud rate select MSB 3 CDEM Lower cut-off frequency data filter 4 AVCC Analog power supply 5 AGND Analog ground 6 DGND Digital ground 7 MIXVCC Power supply mixer 8 LNAGND High-frequency ground LNA and mixer 9 LNA_IN 10 n.c. RF input 11 LFVCC 12 LF 13 LFGND 14 XTO 15 DVCC Digital power supply 16 MODE Selecting 433.92 MHz /315 MHz Low: 315 MHz (USA) High: 433.92 MHz (Europe) 17 RSSI Output of the RSSI amplifier 18 TEST Test pin, during operation at GND 19 ENABLE 20 DATA Not connected Power supply VCO Loop filter Ground VCO Crystal oscillator Selecting operation mode Low: sleep mode High: receiving mode Data output T5744 4521B–RKE–01/03 T5744 Figure 3. Block Diagram BR_0 BR_1 CDEM ASKDemodulator and data filter RSSI RSSI AVCC Dem_out RSSI IF Amp Data interface DATA Test TEST AGND MODE 4. Order DGND DVCC ENABLE LPF 3 MHz MIXVCC LFGND Standby logic LFVCC IF Amp LPF 3 MHz LNAGND VCO XTO XTO f LNA_IN LF LNA 64 RF Front End The RF front end of the receiver is a heterodyne configuration that converts the input signal into a 1-MHz IF signal. According to Figure 3, the front end consists of an LNA (Low-Noise Amplifier), LO (Local Oscillator), a mixer and RF amplifier. The LO generates the carrier frequency for the mixer via a PLL synthesizer. The XTO (crystal oscillator) generates the reference frequency fXTO. The VCO (Voltage-Controlled Oscillator) generates the drive voltage frequency fLO for the mixer. fLO is dependent on the voltage at Pin LF. fLO is divided by factor 64. The divided frequency is compared to fXTO by the phase frequency detector. The current output of the phase frequency detector is connected to a passive loop filter and thereby generates the control voltage VLF for the VCO. By means of that configuration, VLF is controlled in a way that fLO/64 is equal to fXTO. If fLO is determined, fXTO can be calculated using the following formula: fXTO = fLO/64 The XTO is a one-pin oscillator that operates at the series resonance of the quartz crystal. According to Figure 4, the crystal should be connected to GND via a capacitor CL. The value of that capacitor is recommended by the crystal supplier. The value of CL should be optimized for the individual board layout to achieve the exact value of fXTO and hereby of fLO. When designing the system in terms of receiving bandwidth, the accuracy of the crystal and the XTO must be considered. 3 4521B–RKE–01/03 Figure 4. PLL Peripherals VS DVCC CL XTO R1 = 820 W C9 = 4.7 nF C10 = 1 nF LFGND LF LFVCC VS R1 C10 C9 The passive loop filter connected to Pin LF is designed for a loop bandwidth of BLoop = 100 kHz. This value for BLoop exhibits the best possible noise performance of the LO. Figure 4 shows the appropriate loop filter components to achieve the desired loop bandwidth fLO is determined by the RF input frequency fRF and the IF frequency fIF using the following formula: fLO = fRF - fIF To determine fLO, the construction of the IF filter must be considered at this point. The nominal IF frequency is fIF = 1 MHz. To achieve a good accuracy of the filter's corner frequencies, the filter is tuned by the crystal frequency fXTO. This means that there is a fixed relation between fIF and fLO that depends on the logic level at pin mode. This is described by the following formulas: MODE = 0 USA fIF = fLO/314 MODE = 1 Europe fIF = fLO/432.92 The relation is designed to achieve the nominal IF frequency of fIF = 1 MHz for most applications. For applications where fRF = 315 MHz, MODE must be set to '0'. In the case of fRF = 433.92 MHz, MODE must be set to '1'. For other RF frequencies, fIF is not equal to 1 MHz. fIF is then dependent on the logical level at Pin MODE and on fRF. Table 1 summarizes the different conditions. The RF input either from an antenna or from a generator must be transformed to the RF input Pin LNA_IN. The input impedance of that pin is provided in the electrical parameters. The parasitic board inductances and capacitances also influence the input matching. The RF receiver T5744 exhibits its highest sensitivity at the best signal-tonoise ratio in the LNA. Hence, noise matching is the best choice for designing the transformation network. A good practice when designing the network, is to start with power matching. From that starting point, the values of the components can be varied to some extent to achieve the best sensitivity. If a SAW is implemented into the input network a mirror frequency suppression of D P Ref = 40 dB can be achieved. There are SAWs available that exhibit a notch at Df = 2 MHz. These SAWs work best for an intermediate frequency of IF = 1 MHz. The selectivity of the receiver is also improved by using a SAW. In typical automotive applications, a SAW is used. 4 T5744 4521B–RKE–01/03 T5744 Figure 5 shows a typical input matching network for f RF = 315 MHz and f RF = 433.92 MHz using a SAW. Figure 6 illustrates the input matching to 50 W without a SAW. The input matching networks shown in Figure 6 are the reference networks for the parameters given in the electrical characteristics. Table 1. Calculation of LO and IF Frequency Conditions Local Oscillator Frequency Intermediate Frequency fRF = 315 MHz, MODE = 0 fLO = 314 MHz fIF = 1 MHz fRF = 433.92 MHz, MODE = 1 fLO = 432.92 MHz fIF = 1 MHz 300 MHz < fRF < 365 MHz, MODE = 0 f RF f LO = ------------------1 1 + ---------314 365 MHz < fRF < 450 MHz, MODE = 1 f RF f LO = --------------------------1 1 + -----------------432.92 f LO f IF = --------314 f LO f IF = ----------------432.92 Figure 5. Input Matching Network with SAW Filter 8 8 LNAGND LNAGND T5744 9 C3 L 22p 25n C16 100p fRF = 433.92 MHz L2 TOKO LL2012 F33NJ RFIN C2 8.2p 33n 1 IN 9 C3 L 47p 25n L3 B3555 8.2p 100p fRF = 315 MHz TOKO LL2012 F27NJ OUT OUT_GND IN_GND CASE_GND 3,4 7,8 LNA_IN C16 C17 27n 2 T5744 LNA_IN 5 6 L2 TOKO LL2012 F82NJ RFIN C2 10p 82n C17 L3 47n 1 2 IN B3551 22p TOKO LL2012 F47NJ OUT OUT_GND IN_GND CASE_GND 3,4 7,8 5 6 5 4521B–RKE–01/03 Figure 6. Input Matching Network without SAW Filter fRF = 433.92 MHz 8 LNAGND fRF = 315 MHz 8 T5744 9 25n C3 15p T5744 9 LNA_IN RFIN LNAGND 25n C3 33p LNA_IN RFIN 3.3p 3.3p 100p 22n TOKO LL2012 F22NJ 100p 39n TOKO LL2012 F39NJ Please note that for all coupling conditions (see Figure 5 and Figure 6), the bond wire inductivity of the LNA ground is compensated. C3 forms a series resonance circuit together with the bond wire. L = 25 nH is a feed inductor to establish a DC path. Its value is not critical but must be large enough not to detune the series resonance circuit. For cost reduction, this inductor can be easily printed on the PCB. This configuration improves the sensitivity of the receiver by about 1 dB to 2 dB. Analog Signal Processing IF Amplifier The signals coming from the RF front end are filtered by the fully integrated 4th-order IF filter. The IF center frequency is fIF = 1 MHz for applications where fRF = 315 MHz or fRF = 433.92 MHz is used. For other RF input frequencies, refer to Table 1 to determine the center frequency. The receiver T5744 employs an IF bandwidth of B IF = 600 kHz and can be used together with the U2741B in ASK mode. RSSI Amplifier The subsequent RSSI amplifier enhances the output signal of the IF amplifier before it is fed into the demodulator. The dynamic range of this amplifier is DRRSSI = 60 dB. If the RSSI amplifier is operated within its linear range, the best S/N ratio is maintained. If the dynamic range is exceeded by the transmitter signal, the S/N ratio is defined by the ratio of the maximum RSSI output voltage and the RSSI output voltage due to a disturber. The dynamic range of the RSSI amplifier is exceeded if the RF input signal is about 60 dB higher compared to the RF input signal at full sensitivity. Pin RSSI The output voltage of the RSSI amplifier (VRSSI) is available at Pin RSSI. Using the RSSI output signal, the signal strength of different transmitters can be distinguished. The usable input power range PRef is -100 dBm to -55 dBm. Since different RF input networks may exhibit slightly different values for the LNA gain, the sensitivity values given in the electrical characteristics refer to a specific input matching. This matching is illustrated in Figure 6 and exhibits the best possible sensitivity. 6 T5744 4521B–RKE–01/03 T5744 Figure 7. RSSI Characteristics 3.0 2.8 max. 2.6 Tamb = 40°C VRRSI (V) 2.4 25°C 2.2 2.0 105°C 1.8 1.6 min. 1.4 1.2 1.0 -130.0 -110.0 -90.0 -70.0 -50.0 -30.0 PRef (dBm) ASK Demodulator and Data Filter The signal coming from the RSSI amplifier is converted into the raw data signal by the ASK demodulator. An automatic threshold control circuit (ATC) is employed to set the detection reference voltage to a value where a good signal-to-noise ratio is achieved. This circuit also implies the effective suppression of any kind of inband noise signals or competing transmitters. If the S/N ratio exceeds 10 dB, the data signal can be detected properly. The output signal of the demodulator is filtered by the data filter before it is fed into the digital signal processing circuit. The data filter improves the S/N ratio as its passband can be adopted to the characteristics of the data signal. The data filter consists of a 1storder highpass and a 1st-order lowpass filter. The highpass filter cut-off frequency is defined by an external capacitor connected to Pin CDEM. The cut-off frequency of the highpass filter is defined by the following formula: 1 fcu_DF = ------------------------------------------------2 ´ p ´ R 1 ´ CDEM Recommended values for CDEM are given in the electrical characteristics. The cut-off frequency of the lowpass filter is defined by the selected baudrate range (BR_Range). BR_Range is defined by the Pins BR_0 and BR_1. BR_Range must be set in accordance to the used baudrate. BR_1 BR_0 BR_Range 0 0 0 0 1 1 1 0 2 1 1 2 Each BR_Range is defined by a minimum and a maximum edge-to-edge time (tee_sig). These limits are defined in the electrical characteristics. They should not be exceeded to maintain full sensitivity of the receiver. 7 4521B–RKE–01/03 Receiving Characteristics The RF receiver T5744 can be operated with and without a SAW front-end filter. In a typical automotive application, a SAW filter is used to achieve better selectivity. The selectivity with and without a SAW front-end filter is illustrated in Figure 7. Note that the mirror frequency is reduced by 40 dB. The plots are printed relatively to the maximum sensitivity. If a SAW filter is used, an insertion loss of about 4 dB must be considered. When designing the system in terms of receiving bandwidth, the LO deviation must be considered as it also determines the IF center frequency. The total LO deviation is calculated to be the sum of the deviation of the crystal and the XTO deviation of the T5744. Low-cost crystals are specified to be within ±100 ppm. The XTO deviation of the T5744 is an additional deviation due to the XTO circuit. This deviation is specified to be ±30 ppm. If a crystal of ±100 ppm is used, the total deviation is ±130 ppm in that case. Note that the receiving bandwidth and the IF-filter bandwidth are equivalent. Figure 8. Receiving Frequency Response 0.0 without SAW dP (dB) -20.0 -40.0 -60.0 -80.0 -100.0 -6.0 with SAW -5.0 -4.0 -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 df (MHz) Basic Clock Cycle of the Digital Circuitry The complete timing of the digital circuitry and the analog filtering is derived from one clock. According to Figure 9, this clock cycle TClk is derived from the crystal oscillator (XTO) in combination with a divider. The division factor is controlled by the logical state at Pin MODE. According to chapter 'RF Front End', the frequency of the crystal oscillator (fXTO) is defined by the RF input signal (fRFin) which also defines the operating frequency of the local oscillator (fLO). Figure 9. Generation of the Basic Clock Cycle T Clk MODE Divider :14/:10 f XTO 16 L : USA(:10) H: Europe(:14) DVCC 15 XTO XTO 8 14 T5744 4521B–RKE–01/03 T5744 Pin MODE can now be set in accordance with the desired clock cycle TClk. TClk controls the following application-relevant parameters: Timing of the analog and digital signal processing IF filter center frequency (fIF0) Most applications are dominated by two transmission frequencies: fSend = 315 MHz is mainly used in USA, fSend = 433.92 MHz in Europe. In order to ease the usage of all TClkdependent parameters, the electrical characteristics display three conditions for each parameter. • Application USA (fXTO = 4.90625 MHz, MODE = L, TClk = 2.0383 µs) • Application Europe (fXTO = 6.76438 MHz, MODE = H, TClk = 2.0697 µs) • Other applications (TClk is dependent on fXTO and on the logical state of Pin MODE. The electrical characteristic is given as a function of TClk). The clock cycle of some function blocks depends on the selected baud rate range (BR_Range) which is defined by the Pins BR_0 and BR_1. This clock cycle T XClk is defined by the following formulas for further reference: BR_Range = BR_Range0: BR_Range1: BR_Range2: BR_Range3: Pin ENABLE TXClk = 8 ´ TClk TXClk = 4 ´ TClk TXClk = 2 ´ TClk TXClk = 1 ´ TClk Via the Pin ENABLE the operating mode of the receiver can be selected (see Figure 10 and Figure 11). If the Pin ENABLE is held to Low, the receiver remains in sleep mode. All circuits for signal processing are disabled and only the XTO is running in that case. The current consumption is IS = ISoff in that case. During the sleep mode the receiver is not sensitive to a transmitter signal. To activate the receiver, the Pin ENABLE must be held to High. During the start-up period, TStartup, all signal processing circuits are enabled and settled. The duration of the start-up period depends on the selected baud-rate range (BR_Range). After the start-up period, all circuits are in a stable condition and the receiver is in the receiving mode. In receiving mode, the internal data signal (Dem_out) is switched to Pin DATA. To avoid incorrect timing at the begin of the data stream, the begin is synchronized to a falling edge of the incoming data signal. The receiver stays in the receiving mode until it is switched back to sleep mode via Pin ENABLE. During start-up and receiving mode, the current consumption is IS = ISon. 9 4521B–RKE–01/03 Figure 10. Enable Timing (1) Dem_out tee_sig ENABLE DATA Sleep mode Start-up mode I S = I Soff I S = I Son Receiving mode I S = I Son TStart-up Figure 11. Enable Timing (2) Dem_out tee_sig ENABLE DATA Sleep mode I S = I Soff Digital Signal Processing Start-up mode Receiving mode I S = I Son TStart-up I S = I Son The data from the ASK demodulator (Dem_out) is digitally processed in different ways and as a result converted into the output signal DATA. This processing depends on the selected baudrate range (BR_Range). Figure 12 illustrates how Dem_out is synchronized by the extended basic clock cycle TXClk. Data can change its state only after TXClk has elapsed. The edge-to-edge time period tee_sig of the DATA signal as a result is always an integral multiple of TXClk. The minimum time period between two edges of the data signal is limited to tee_sig ³ TDATA_min. This implies an efficient suppression of spikes at the DATA output. At the same time it limits the maximum frequency of edges at DATA. This eases the interrupt handling of a connected microcontroller. 10 T5744 4521B–RKE–01/03 T5744 Figure 12. Synchronization of the Demodulator Output TXClk Dem_out Data_out (DATA) tee_sig Figure 13. Debouncing of the Demodulator Output Dem_out DATA tDATA_min tDATA_min tee tDATA_min tee tee Absolute Maximum Ratings Parameters Symbol Min. Max. Unit Supply voltage VS 6 V Power dissipation Ptot 450 mW Juntion temperature Tj 150 °C Storage temperature Tstg -55 +125 °C Tamb -40 +105 °C 10 dBm Ambient temperature Maximum input level, input matched to 50 W Pin_max Thermal Resistance Parameters Symbol Value Unit Junction ambient SO20 package RthJA 100 K/W Junction ambient SSO20 package RthJA 100 K/W 11 4521B–RKE–01/03 Electrical Characteristics All parameters refer to GND, Tamb = -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5 V, Tamb = 25°C) Parameters Test Conditions 6.76438 MHz Osc. (MODE:1) Symbol Min. Typ. Max. 4.90625 MHz Osc. (MODE:0) Min. Typ. Variable Oscillator Unit Max. Min. Typ. Max. 2.0383 2.0383 1/(fxto/10) 1/(fxto/14) 1/(fxto/10) 1/(fxto/14) µs µs Basic Clock Cycle of the Digital Circuitry Basic clock cycle MODE = 0 (USA) MODE = 1 (Europe) Extended basic clock cycle BR_Range0 BR_Range1 BR_Range2 BR_Range3 Start-up time (see Figure 10 and Figure 11) BR_Range0 BR_Range1 BR_Range2 BR_Range3 TClk TXClk TStartup 2.0697 2.0697 16.6 8.3 4.1 2.1 16.6 8.3 4.1 2.1 16.3 8.2 4.1 2.0 16.3 8.2 4.1 2.0 8 ´ TClk 4 ´ TClk 2 ´ TClk 1 ´ TClk 8 ´ TClk 4 ´ TClk 2 ´ TClk 1 ´ TClk µs µs µs µs 1855 1061 1061 663 1855 1061 1061 663 1827 1045 1045 653 1827 1045 1045 653 896.5 512.5 512.5 320.5 ´ TClk 896.5 512.5 512.5 320.5 ´ TClk µs µs µs µs µs Receiving Mode Intermediate frequency MODE=0 (USA) MODE=1 (Europe) Minimum time period between edges at Pin DATA BR_Range0 BR_Range1 BR_Range2 BR_Range3 (Figure 13) Edge to edge time period of the data signal for full sensitivity BR_Range0 BR_Range1 BR_Range2 BR_Range3 (Figure 10) fIF TDATA_min fXTO ´ 64 / 314 fXTO ´ 64 / 432.92 1.0 1.0 MHz MHz 165 83 41.4 20.7 165 83 41.4 20.7 163 81 40.7 20.4 163 81 40.7 20.4 10 ´ TXClk 10 ´ TXCl 10´ TXClk 10 ´ TXClk 10 ´ TXClk 10 ´ TXCl 10´ TXClk 10 ´ TXClk 400 200 100 50 8479 8479 8479 8479 400 200 100 50 8350 8350 8350 8350 BR_Range ´ 2 µs/TCLK 4097 ´ TCLK tee_sig µs µs µs µs µs µs µs µs Electrical Characteristics (continued) Parameters Test Conditions Typ. Max. Unit Current consumption Sleep mode (XTO active) Symbol ISoff Min. 190 276 µA IC active (startup-, receiving mode) Pin DATA = H ISon 7.1 8.7 mA LNA/ mixer/ IF amplifier input matched according to Figure 6 IIP3 -28 ISLORF -73 NF 7 dB ZiLNA_IN 1.0 || 1.56 1.3 || 1.0 kW || pF kW || pF IP1db -40 dBm LNA Mixer Third-order intercept point LO spurious emission at RFIn Input matched according to Figure 6, required according to I-ETS 300220 Noise figure LNA and mixer (DSB) Input matching according to Figure 6 LNA_IN input impedance at 433.92 MHz at 315 MHz 1 dB compression point (LNA, mixer, IF amplifier) Input matched according to Figure 6, referred to RFin 12 dBm -57 dBm T5744 4521B–RKE–01/03 T5744 Electrical Characteristics (continued) Parameters Test Conditions Maximum input level Input matched according to Figure 6, BER £ 10-3 Symbol Min. Typ. Max. Unit -20 dBm 449 MHz -93 -113 -90 -110 dBC/Hz dBC/Hz -55 -47 dBC Pin_max Local Oscillator Operating frequency range VCO Phase noise VCO / LO Spurious of the VCO fVCO fosc = 432.92 MHz at 1 MHz at 10 MHz For best LO noise (design parameter) R1 = 820 W C9 = 4.7 nF C10 = 1 nF Capacitive load at Pin LF XTO operating frequency L (fm) at ± fXTO VCO gain Loop bandwidth of the PLL KVCO 190 MHz/V BLoop 100 kHz CLF_tot XTO crystal frequency, appropriate load capacitance must be connected to XTAL fXTAL = 6.764375 MHz (EU) 10 nF 6.764375 +30 ppm 4.90625 +30 ppm MHz RS 150 220 W W Co 6.5 pF fXTO fXTAL = 4.90625 MHz (US) Series resonance resistor of the crystal 299 fXTO = 6.764 MHz 4.906 MHz Static capacitance of the crystal 6.764375 -30 ppm 4.90625 -30 ppm 6.764375 4.90625 MHz Analog Signal Processing Input sensitivity Input matched according to Figure 6 ASK (level of carrier) BER £ 10-3 (Manchester), fin = 433.92 MHz/ 315 MHz T = 25°C, VS = 5 V, fIF = 1 MHz BR_Range0 (1 kBd) -107 -110 -112 dBm BR_Range1 (2 kBd) -105 -108 -110 dBm BR_Range2 (4kBd) -103 -106 -108 dBm BR_Range3 (8 kBd) -101 -104 -106 dBm +2.5 -1.5 dB +5.5 +7.5 -1.5 -1.5 dB dB 12 dB Sensitivity variation for the full operating range compared to Tamb = 25°C, VS = 5 V fin = 433.92 MHz/ 315 MHz fIF = 1 MHz PASK = PRef_ASK + DPRef Sensitivity variation for full operating range including IF filter compared to Tamb = 25°C, VS = 5 V fin = 433.92 MHz/ 315 MHz fIF = 0.79 MHz to 1.21 MHz fIF = 0.73 MHz to 1.27 MHz PASK = PRef_ASK + DPRef S/N ratio to suppress inband noise signals PRef_ASK DPRef DPRef SNR 10 13 4521B–RKE–01/03 Electrical Characteristics (continued) Parameters Test Conditions Dynamic range RSSI amplifier Symbol RSSI output voltage range VRSSI GRSSI 1 fcu_DF = -------------------------------------------------2 ´ p ´ R 1 ´ CDEM Recommended CDEM for best performance BR_Range0 BR_Range1 BR_Range2 BR_Range3 Upper cut-off frequency data filter Upper cut-off frequency BR_Range0 BR_Range1 BR_Range2 BR_Range3 RI Typ. Max. Unit 60 DRRSSI RSSI gain RI of Pin CDEM for cut-off frequency calculation Min. 1.0 dB 3.0 V 20 28 40 mV/dB kW 55 33 18 10 6.8 CDEM nF nF nF nF 1.75 3.5 7.0 14.0 2.2 4.4 8.8 17.6 2.65 5.3 10.6 21.2 kHz kHz kHz kHz VOI RPup 39 0.08 50 0.3 65 V kW 0.2 ´ VS V V 0.2 ´ VS V V 0.2 ´ VS V V 0.2 ´ VS V V 0.2 ´ VS V fu Digital Ports Data output - Saturation voltage LOW - Internal pull-up resistor Iol = 1 mA ENABLE input - Low-level input voltage - High-level input voltage Sleep mode Receiving mode VIl VIh 0.8 ´ VS MODE input - Low-level input voltage - High-level input voltage Division factor = 10 Division factor = 14 VIl VIh 0.8 ´ VS BR_0 input - Low-level input voltage - High-level input voltage VIl VIh 0.8 ´ VS BR_1 input - Low-level input voltage - High-level input voltage VIl VIh 0.8 ´ VS TEST input - Low-level input voltage 14 Test input must always be set to LOW VIl T5744 4521B–RKE–01/03 T5744 Figure 14. Application Circuit: fRF = 433.92 MHz, without SAW Filter VS C7 2.2uF 10% C6 10nF 10% T5744 C14 39nF 5% GND C13 10nF 10% 1 2 3 BR_0 BR_1 CDEM 4 5 6 AVCC AGND DGND 7 MIXVCC 8 LNAGND 9 LNA_IN 10 NC C3 15pF 5% np0 20 19 18 17 16 DVCC 15 XTO 14 LFGND LF LFVCC 13 12 11 RSSI Q1 C11 12pF 6.76438MHz 2% np0 C8 150pF 10% C16 C17 3.3pF 5% np0 DATA ENABLE C12 10nF 10% C15 150pF 10% KOAX DATA ENABLE TEST RSSI MODE R1 820 5% 100pF 5% np0 L2 TOKO LL2012 F22NJ 22nH 5% C9 4.7nF 5% C10 1nF 5% Figure 15. Application Circuit: fRF = 315 MHz, without SAW Filter VS C7 2.2uF 10% C6 10nF 10% T5744 C14 39nF 5% GND C13 10nF 10% C3 33pF 5% np0 1 2 3 BR_0 BR_1 CDEM 4 5 6 AVCC AGND DGND 7 MIXVCC XTO 8 9 10 LNAGND LNA_IN NC LFGND LF LFVCC C15 150pF 10% C16 KOAX C17 3.3pF 5% np0 100pF 5% np0 L2 TOKO LL2012 F39NJ 39nH 5% DATA ENABLE TEST RSSI MODE DVCC 20 19 18 17 16 15 DATA ENABLE RSSI Q1 C11 14 13 12 11 4.90625MHz C12 10nF 10% 15pF 2% np0 C8 150pF 10% R1 820 5% C9 4.7nF 5% C10 1nF 5% 15 4521B–RKE–01/03 Figure 16. Application Circuit: fRF = 433.92 MHz, with SAW Filter VS C7 2.2uF 10% C6 10nF 10% T5744 C14 39nF 5% GND C13 10nF 10% 1 2 3 BR_0 BR_1 CDEM 4 5 6 AVCC AGND DGND 7 MIXVCC 8 LNAGND 9 LNA_IN 10 NC C3 22pF 5% np0 C15 150pF 10% C16 C17 DATA ENABLE TEST RSSI MODE 20 19 18 17 16 DVCC 15 XTO 14 LFGND LF LFVCC 13 12 11 33nH 5% C2 8.2pF 5% np0 1 2 IN IN_GND 3 4 CASE_GND CASE_GND OUT OUT_GND 5 6 CASE_GND CASE_GND 7 8 Q1 C11 6.76438MHz 12pF 2% np0 C8 150pF 10% R1 820 5% L2 TOKO LL2012 F33NJ KOAX RSSI C12 10nF 10% 8,2pF 5% np0 L3 TOKO LL2012 F27 NJ 27nH 5% 100pF 5% np0 DATA ENABLE C9 4.7nF 5% C10 1nF 5% B3555 Figure 17. Application Circuit: fRF = 315 MHz, witht SAW Filter VS C7 2.2uF 10% C6 10nF 10% T5744 C14 39n F 5% GND C13 10nF 10% C3 47pF 5% np0 C15 150pF 10% 1 2 3 BR_0 BR_1 CDEM DATA ENABLE TEST RSSI MODE 20 19 18 17 16 4 5 6 AVCC AGND DGND 7 DVCC 15 MIXVCC XTO 14 8 9 10 LNAGND LNA_IN NC LFGND LF LFVCC 13 12 11 C16 100pF 5% np0 C17 C2 82nH 10pF 5% 5% np0 1 2 IN IN_GND 3 4 CASE_GND CASE_GND OUT OUT_GND 5 6 CASE_GND CASE_GND 7 8 RSSI Q1 C11 15pF 4.90625MHz 2% np0 C8 150pF 10% C12 10nF 10% 22pF 5% np0 L3 TOKO LL2012 F47NJ 47nH 5% L2 TOKO LL2012 F82NJ KOAX DATA ENABLE R1 820 5% C9 4.7nF 5% C10 1nF 5% B3551 16 T5744 4521B–RKE–01/03 T5744 Ordering Information Extended Type Number Package Remarks T5744-TKS SSO20 Tube T5744-TKQ SSO20 T5744-TGS SO20 Tube T5744-TGQ SO20 Taped and reeled Taped and reeled Package Information 9.15 8.65 Package SO20 Dimensions in mm 12.95 12.70 7.5 7.3 2.35 0.25 0.25 0.10 0.4 10.50 10.20 1.27 11.43 20 11 technical drawings according to DIN specifications 1 10 17 4521B–RKE–01/03 5.7 5.3 Package SSO20 Dimensions in mm 6.75 6.50 4.5 4.3 1.30 0.15 0.05 0.25 0.65 5.85 20 0.15 6.6 6.3 11 technical drawings according to DIN specifications 1 18 10 T5744 4521B–RKE–01/03 Atmel Headquarters Atmel Operations Corporate Headquarters Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards Zone Industrielle 13106 Rousset Cedex, France TEL (33) 4-42-53-60-00 FAX (33) 4-42-53-60-01 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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