1/4 STRUCTURE Silicon Monolithic Integrated Circuit NAME OF PRODUCT DC-AC Inverter Control IC TYPE ＢＤ９２１７Ｆ /ＢＤ９２１７ＦＶ FUNCTION ・ ・ ・ ・ ・ ・ ・ ・ ・ 20V High voltage process 1ch control with Full-Bridge Lamp current and voltage sense feed back control Sequencing easily achieved with Soft Start Control Short circuit protection with Timer Latch Under Voltage Lock Out Mode-selectable the operating or stand-by mode by stand-by pin Automatic Judge function for External synchronization of lamp oscillation BURST mode controlled by PWM and DC input ○Absolute Maximum Ratings（Ｔａ＝２５℃） Parameter Supply Voltage REG PIN Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Power Dissipation Symbol Limits Unit VCC 20 V VREG Topr 15 -40～+85 V ℃ Tstg -55～+150 ℃ Tjmax +150 ℃ ※１ Pd 1024(BD9217FV) 688(BD9217F) ※2 mW *1 Pd derate at 8.2mW/℃ for temperature above Ta = 25℃ (When mounted on a PCB 70.0mm×70.0mm×1.6mm) *2 Pd derate at 5.5mW/℃ for temperature above Ta = 25℃ (When mounted on a PCB 70.0mm×70.0mm×1.6mm) 〇Operating condition Parameter Supply voltage oscillation frequency BCT oscillation frequency Symbol Limits VCC 7.5 ～ 19.5 V FOUT 30 ～ 90 kHz FBCT REV. C 0.05 ～ 1.00 Unit kHz 2/4 ○Electric Characteristics（Ta=25℃，VCC=12V） Limits Parameter Symbol Unit MIN. TYP. Conditions MAX. （（WHOLE DEVICE）） Operating current Icc1 － 8.0 16 mA Stand-by current Icc2 － 10 30 uA FOUT=60kHz, FB=GND （（STAND BY CONTROL）） Stand-by voltage H VstH 2.0 - VCC V System ON Stand-by voltage L VstL －0.3 - 0.8 V System OFF （（UVLO BLOCK）） Operating voltage (VCC) Vuvlo 6.65 7.00 7.35 V Hesteresis width (VCC) ⊿Vuvlo 0.37 0.50 0.63 V Operating voltage (UVLO) Vvlo_u 2.4 2.5 2.6 V Hesteresis width (UVLO) ⊿Vvlo_u 0.075 0.100 0.125 V REG output voltage VREG 7.35 7.50 7.65 V REG source current IREG 20 － － mA （（REG BLOCK）） VCC > 8.5V Source current （（SOFT START BLOCK）） Soft start current SS_COMP detect voltage Iss 1.5 2.0 2.5 uA VSS 2.3 2.5 2.7 V VRT 1.05 1.50 1.95 V RSRT - 100 200 Ω （（OSC BLOCK）） RT Output Voltage STR ON Resistor value （（BOSC BLOCK）） BOSC Max voltage VBCTH 1.94 2.00 2.06 V fBCT=0.3kHz BOSC Min voltage VBCTL 0.40 0.50 0.60 V fBCT=0.3kHz BOSC constant current IBCT 1.35/BRT 1.50/BRT 1.65/BRT A BOSC frequency FBCT 291 300 309 Hz V (BRT=36.2KΩ, BCT=0.047uF) （（FEED BACK BLOCK）） IS threshold voltage Vis 1.225 1.250 1.275 VS threshold voltage Vvs 1.220 1.250 1.280 V IS source current 1 Iis1 － － 0.9 uA DUTY=2.0V IS source current 2 Iis2 40 50 60 uA DUTY=0V, IS=1.0V VS source current Ivs － － 0.9 uA VISCOMP 0.64 0.66 0.68 V N output sink resistance Rsink_N 1.8 3.5 7.0 Ω N output source resistance Rsource_N 4.5 9.0 18.0 Ω P output sink resistance Rsink_P 1.8 3.5 7.0 Ω P output source resistance Rsource_P 4.5 9.0 18.0 Ω IS COMP detect voltage （（OUTPUT BLOCK）） Drive output frequency MAX DUTY OFF period Fout 57.9 60.0 62.1 kHz MAX DUTY - 48.0 - % TOFF 100 200 400 ns RT=28.5kΩ, FB=0V FOUT=60kHz （（ CT SYNCHRONOUS BLOCK ）） Input High voltage range VCT_CLKIN_H 2.5 － 5.0 V Input Low voltage range VCT_CLKIN_L -0.3 － 0.5 V FAIL High voltage VFAIL_H 2.95 3.1 3.25 V FAIL Low voltage VFAIL_L -0.3 - 0.3 V （（FAIL BLOCK）） （（SEL BLOCK）） Input High voltage range VSEL_H 5.0 - 15 V Input Low voltage range VSEL_L -0.3 - 0.3 V （（TIMER LATCH BLOCK） CP timer latch detect voltage VCP 1.91 2.00 2.09 V CP timer latch charge current ICP 0.85 1.05 1.25 uA （（COMP BLOCK）） COMP over voltage detect voltage VCOMP 3.88 4.00 4.12 V Hysteresis width （COMP） ⊿Vcomp 0.138 0.185 0.232 V (This product is not designed to be radiation-resistant.) REV. C VSS > 2.4V 3/4 〇Package Dimensions DEVICE MARK BD9217F BD9217FV Lot No. SOP24(unit:mm) SSOP-B24(unit:mm) 〇Block Diagram VCC REG SEL BRT BCT OSC BLOCK REG BLOCK STB RT CLKIN DUTY DUTY BLOCK BOSC BLOCK SYSTEM ON/OFF STB BLOCK REG SS P1 FB N1 F/B BLOCK IS VS SS CT LOGIC BLOCK PWM BLOCK OUTPUT BLOCK P2 N2 PGND PROTECT BLOCK GND UVLO ブロック VCC COMP CP SRT FAIL UVLO ○Pin Description PIN No. PIN NAME PIN No. FUNCTION PIN NAME FUNCTION 1 2 PGND Power Ground for FET drivers External capacitor between CP and GND for timer latch NMOS FET driver (Channel 2 side) 13 14 CP N2 FAIL 3 P2 PMOS FET driver (Channel 2 side) 15 SEL 4 5 UVLO Input of Under Voltage Lock Out 16 17 VS Error Indication output pin Normal : H, Error : L Selector pin for external syncro-mode frequency REG(Pin 20) : Pull-up fin=Fout(DUTY=50%), Gnd-short : fin=Fout x 2 Error amplifier input 1 IS Error amplifier input 2 6 RT 18 FB Error amplifier output 7 SRT 19 SS 8 GND 20 REG External capacitor between SS and GND for Soft Start Control and detect the time of Soft Start regulator output 9 BCT 21 COMP Input of over voltage detector 10 BRT 22 VCC Power supply input with UVLO Protection 11 12 DUTY 23 24 P1 N1 PMOS FET driver (Channel 1 side) CLKIN STB CT Synchronous signal input External resistor between RT and GND for adjustment frequency of saw tooth wave。 External resistor between SRT and RT for adjustment frequency of kick-off Ground External capacitor between BCT and GND for adjusting the BURST triangle oscillator External resistor between BRT and GND for adjustment frequency of Burst dimming Control Burst-dimming by PWM signal or DC Stand-by switch REV. C NMOS FET driver (Channel 1 side) 4/4 〇NOTE FOR USE １. When designing the external circuit, including adequate margins for variation between external devices and IC. Use adequate margins for steady state and transient characteristics. ２. The circuit functionality is guaranteed within of ambient temperature operation range as long as it is within recommended operating range. The standard electrical characteristic values cannot be guaranteed at other voltages in the operating ranges, however the variation will be small. ３. Mounting failures, such as misdirection or miscounts, may harm the device. ４. A strong electromagnetic field may cause the IC to malfunction. ５. The GND pin should be the location within ±0.3V compared with the PGND pin. ６. If the voltage between VCC and I/O pins or GND and I/O pins is in opposite from the normal potential difference, unusual current flow into pins may occur which can destroy the IC. To avoid such occurrence it is recommended to place protection diodes for prevention against backward current flow. ７. BD9217F/BD9217FV incorporate a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is designed only to shut the IC off to prevent runaway thermal operation. It is not designed to protect the IC or guarantee its operation of the thermal shutdown circuit is assumed. ８. Absolute maximum ratings are those values that, if exceeded, may cause the life of a device to become significantly shortened. Moreover, the exact failure mode caused by short or open is not defined. Physical countermeasures, such as a fuse, need to be considered when using a device beyond its maximum ratings. ９. About the external FET, the parasitic Capacitor may cause the gate voltage to change, when the drain voltage is switching. Make sure to leave adequate margin for this IC variation. １０. By STB voltage, BD9217FV are changed to 2 states. Therefore, do not input STB pin voltage between one state and the other state (0.8～ 2.0V). １１. The pin connected a connector need to connect to the resistor for electrical surge destruction. １２．This IC is a monolithic IC which (as shown is Fig.1)has P+ substrate and between the various pins. A P-N junction is formed from this P layer of each pin. For example, the relation between each potential is as follows, ○(When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.) ○(When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.) Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits as well as operation faults and physical damage. Accordingly you must not use methods by which parasitic diodes operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin. Transistor (NPN) Resistance (PinA) (PinB) B E C Ｃ GND P P＋ N P＋ N Ｎ P substrate GND Parasitic diode N Ｎ N P substrate GND Parasitic diode (PinB) (PinA) B CＣ Ｂ EＥ Parasitic diode GND GND Other adjacent components Parasitic diode Fig.1 Simplified structure of a Bipolar IC REV. C Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. 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