ATMEL ATF1502SEL-15

Features
• 2nd Generation EE PROM-based Complex Programmable Logic Devices
•
•
•
•
•
•
•
•
•
•
– VCCIO of 5.0V or 3.3V with 3.3V Operation being 5V Tolerant
– 32 - 256 Macrocells with Enhanced Features
– Pin-compatible with Industry Standard Devices
– Speeds to 5 ns Maximum Pin-to-pin Delay
– Registered Operation to 250 MHz
Enhanced Macrocells with Logic Doubling™ Features
– Bury Either Register or COM while Using the Other for Output
– Dual Independent Feedback Allows Multiple Latch Functions per Macrocell
– 5 Product Terms per Macrocell, expandable to 40 per Macrocell with Cascade
Logic, Plus 15 more with Foldback Logic
– D/T/Latch Configurable Flip-flops plus Transparent Latches
– Global and/or per Macrocell Register Control Signals
– Global and/or per Macrocell Output Enable
– Programmable Output Slew Rate per Macrocell
– Programmable Output Open Collector Option per Macrocell
– Fast Registered Input from Product Term
Enhanced Connectivity
– Single Level Switch Matrix for Maximum Routing Options
– Up to 40 Inputs per Logic Block
Advanced Power Management Features
– ITD (Input Transition Detection) Available Individually on Global Clocks, Inputs and
I/O for µA Level Standby Current for “L” Versions
– Pin-controlled 1 mA Standby Mode
– Reduced-power Option per Macrocell
– Automatic Power Down of Unused Macrocells
– Programmable Pin-keeper Inputs and I/Os
Available in Commercial and Industrial Temperature Ranges
Available in All Popular Packages Including PLCC, PQFP and TQFP
EE PROM Technology
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 20 Year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
JTAG Boundary-scan Testing Port per IEEE 1149.1-1990 and 1149.1a-1993
– Pull-up Option on JTAG Pins TMS and TDI
IEEE 1532 Compatibility for Fast In-System Programmability (ISP) via JTAG
PCI-compliant
Security Fuse Feature
ATF15xxSE
Family
Datasheet
ATF1502SE(L)
ATF1504SE(L)
ATF1508SE(L)
ATF1516SE(L)
Preliminary
Rev. 2401D–PLD–09/02
1
General
Description
Beginning with the introduction of the 100% connected ATF1500 with 32 enhanced macrocells
in 1996, Atmel’s CPLD products have delivered extra IO connectivity and logic reusability.
Atmel’s commitment to efficient, flexible architecture has continued with the current Atmel
ATF15xxSE Family of industry-standard, pin-compatible CPLDs. Atmel’s Logic Doubling
architecture consists of wider fan-in, additional routing and clock options, combined with
sophisticated, proprietary device fitters, extend CPLD place and route efficiency. Atmel
enhanced macrocell includes double independent buried feedback that allows designers to
pack more logic (particularly shifters and latches) into a smaller CPLD or leave spare room for
later revisions. The Atmel ATF15xxSE family delivers enhanced functionality and flexibility
with no additional design effort and is highly cost effective.
The Atmel ATF15xxSE Family includes all popular configurations and speeds.
Table 1. ATF15xxSE Family Device Features
Feature
ATF1502SE(L)
ATF1504SE(L)
ATF1508SE(L)
ATF1516SE(L)
Usable Gates
750
1500
3000
6000
Macrocells
32
64
128
256
Logic Blocks
2
4
8
16
Max. # Pins
44
100
256
256
Max. User I/Os
36
68
100
164
TPD Grades (ns)
5, 6, 7, 10(15)
5, 6, 7, 10(15)
6, 7, 10(15)
7, 10(15)
The Atmel ATF15xxSE Family includes pin-compatible products in all popular packages.
Table 2. ATF15xxSE Family Device Packages and Number of Signal Pins(1)(2)
Packages
ATF1502SE(L)
ATF1504SE(L)
44-pin PLCC
36
36
44-pin TQFP
36
36
84-pin PLCC
68
68
100-pin TQFP
68
84
100-pin PQFP
84
160-pin PQFP
100
ATF1516SE(L)
208-pin PQFP
164
208-pin RQFP
164
Notes:
2
ATF1508SE(L)
1. Contact Atmel for up-to-date information on device and package availability.
2. When the JTAG port is used for In System Programming (ISP) or Boundary-scan Testing
(BST), the four associated pins become JTAG pins and are unavailable for user I/O.
ATF15xxSE Family
2401D–PLD–09/02
ATF15xxSE Family
Functional
Description
The ATF15xxSE Family of 5.0 Volt supply, high-performance, high-density complex programmable logic devices (CPLDs) utilizes Atmel’s proven electrically erasable non-volatile
technology. With up to 512 macrocells, they easily integrate logic from several TTL, SSI, MSI,
LSI and classic PLDs. The ATF15xxSE Family’s enhanced macrocell architecture, switch
matrices and routing increase usable gate count for new designs and increase odds of successful pin-locked design modifications while maintaining pin-compatibility with industry
standard CPLDs.
The ATF15xxSE Family devices have four dedicated input pins and depending on the type of
device and package, up to 208 bi-directional I/O pins. Each dedicated input pin can also serve
as a global control signal, register clock, register reset or output enable. Each of these control
signals can be selected for use individually within each macrocell. Each input and I/O pin also
feeds into the global bus.
The macrocells are organized into groups of sixteen called logic blocks. The switch matrix in
each logic block selects 40 individual signals from the global bus. Macrocells within a given
logic block may share their sixteen foldback signals on a regional foldback bus. Cascade logic
between macrocells in the Logic Block allows fast, efficient generation of complex logic functions. All macrocells are capable of being I/Os, however, the actual number of I/O pins
depends on the device and package type. The ATF15xxSE Family members contain two, four,
eight, sixteen or thirty-two such logic blocks, each capable of creating sum term logic with a
fan-in of 40 inputs from the switch matrix having access to up to 80 product terms.
Unused macrocells are automatically disabled by the fitter software to decrease power consumption. A security fuse, when programmed, protects the contents of the other fuses. Two
bytes (16 bits) of User Signature are accessible to the user for purposes such as storing
project name, part number, revision or date. The User Signature is accessible regardless of
the state of the security fuse.
The ATF15xxSE Family devices are in-system programmable (ISP) devices. They use the
industry-standard 4-pin JTAG interface (IEEE Std. 1149.1), and are fully-compliant with
JTAG’s Boundary-scan Description Language (BSDL). ISP allows the device to be programmed without removing it from the printed circuit board. In addition to simplifying the
manufacturing flow, ISP also allows design modifications to be made in the field via software.
Global Bus/Switch
Matrix
The global bus (Figure 1) contains all input and I/O pin signals as well as the buried feedback
signals from all macrocells. The switch matrix in each logic block receives as its inputs all signals from the global bus. Up to 40 of these signals can be selected as inputs to the individual
logic blocks by the fitter software. Atmel’s ATF15xx Family of CPLDs use a single level switch
matrix signal distribution structure, where each logic block input has access to the same number of global bus inputs, maximizing the number of possible ways to route a global bus signal.
This single level structure is in contrast with split switch matrix structures used by others in
which routing a particular global bus input to a particular logic block input makes that signal
unavailable to some other logic blocks, thus greatly limiting the available opportunities to
route.
The ATF15xxSE Family macrocell, shown in Figure 2, consists of five sections: product terms
and product term select multiplexer, OR/XOR/CASCADE logic, foldback bus, a flip-flop and
output buffer. Extra fan-in and signal routing are provided throughout. Each macrocell can
generate a foldback logic term from the product term mux and a buried feedback with extra
routing that go to the global bus.
3
2401D–PLD–09/02
Figure 1. ATF15xxSE Family Typical Block Diagram
6 to 16
N
6 to 16
N-1
4
ATF15xxSE Family
2401D–PLD–09/02
ATF15xxSE Family
Figure 2. ATF15xxSE Family Macrocell with Enhanced Features In Red
SWITCH REGIONAL
MATRIX FOLDBACK
OUTPUTS
BUS
SWITCH
MATRIX
80
16
CASIN
LOGIC
FOLDBACK
40
PT1
GOE[0:5]
PT2
3
4
Product Term MUX
2
6
PT3
1
Q
!Q
AP
I/O Pin
GOE SWITCH
MATRIX
Q
I/O Pin
CK/CK/LE
GCK[0:2]
GOE [0:5]
D/T*/L
3
SLEW
RATE
CE
5
PT4
AR
!Q
OPEN
COLLECTOR
PT5
GCLEAR
GLOBAL BUS
Reduced Power Option
CASOUT
* T flip-flop synthesised
Product Terms and
Select Mux
Within each macrocell are five product terms. Each product term may receive as its inputs any
combination of the signals from the switch matrix or regional foldback bus. The product term
select multiplexer (PTMUX) allocates the five product terms as needed to the macrocell logic
gates and control signals. The PTMUX programming is determined by the fitter software,
which selects the optimum macrocell configuration.
OR/XOR/
CASCADE Logic
Within a single macrocell, all the product terms can be routed to the OR gate, creating a 5input AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can
be expanded to as many as 40 product terms with little additional delay.
The macrocell’s XOR gate allows efficient implementation of compare and arithmetic functions. One input to the XOR comes from the OR sum term. The other XOR input can be a
product term or a fixed high- or low-level. For combinatorial outputs, the fixed level input
allows polarity selection. For registered functions, the fixed levels allow DeMorgan minimization of product terms. The XOR gate may be fed from the flip-flop output to emulate T- and JKtype flip-flops, or fed to the buried feedback to synthesize an extra latch.
Foldback Bus
Each macrocell can also generate a foldback product term. This signal goes to the regional
bus and is available to the 16 macrocells in a given logic block. The foldback is an inverse
polarity of one of the macrocell’s product terms. Although Cascade Logic is the preferred
method for expanding the number of macrocell inputs to as many as 40, the 16 foldback terms
in each region can also generate additional fan-in sum terms with nominal additional delay.
5
2401D–PLD–09/02
Flip-flop
The ATF15xxSE Family’s flip-flop has very flexible data and control functions. The data input
can come from either the XOR gate, from a separate product term or directly from the I/O pin.
Selecting the separate product term allows creation of a buried registered feedback within a
combinatorial output or vice-versa. (This enhanced function is automatically implemented by
the fitter software). The flip-flop can be configured for D, T, JK and SR operation, and changes
state on the clock’s rising edge. It can also be configured as a flow-through latch. In this mode,
data passes through when the clock is high and is latched when the clock is low.
When a GCK signal is used as the clock, one of the macrocell product terms can be selected
as a clock enable. When the clock enable function is active and the enable signal (product
term) is low, all clock edges are ignored. The flip-flop has asynchronous reset and preset. The
flip-flop’s asynchronous reset signal (AR) can be either the Global Clear (GCLEAR), a product
term, or always off. AR can also be a logic OR of GCLEAR with a product term. The asynchronous preset (AP) can be a product term or always off.
Extra Feedback
The ATF15xxSE Family macrocell output can be selected as registered or combinatorial. The
extra buried feedback signal can be either combinatorial or registered signal regardless of
whether the output is combinatorial or registered. (This enhanced function is automatically
implemented by the fitter software) Feedback of a buried combinatorial output allows the creation of a second latch within a macrocell.
I/O Control
The output enable multiplexer (MOE) controls the output enable signal. Each I/O can be individually configured as an input, output or for bi-directional operation. The output enable for
each macrocell can be selected from the true or compliment of the two output enable pins, a
subset of the I/O pins, or a subset of the I/O macrocells. This selection is automatically done
by the fitter software when the I/O is configured as an input, all macrocell resources are still
available, including the buried feedback, expander and cascade logic.
The buffer has a fast/slow slew rate option to control EMI and an open-collector option which
enables the device to provide control signals such as an interrupt that can be asserted by any
of the several devices.
Programmable
Pin-keeper Option
for Inputs and I/Os
6
The ATF15xxSE Family offers the option of programming all input and I/O pins with pin-keeper
circuits enabled. When any pin is driven high or low and then subsequently left floating, the pin
keeper circuit will hold it at that previous high or low-level. This circuitry prevents unused input
and I/O lines from floating to intermediate voltage levels, which causes unnecessary power
consumption and system noise. The pin-keeper circuits eliminate the need for external pull-up
resistors and eliminate their DC power consumption.
ATF15xxSE Family
2401D–PLD–09/02
ATF15xxSE Family
Input Diagram
PROGRAMMABLE
OPTION (PIN KEEPER)
I/O Diagram
PROGRAMMABLE
OPTION (PIN KEEPER)
Speed/Power
Management
The ATF15xxSE Family has several speed and power management features.
Multiple Power
Supplies, Power
Sequencing and
Hot-Socketing
Because the ATF15xxSE Family can be used in a system with mixture of power supplies, it
has been designed to function with the V CCINT and V CCIO power supplies applied in any
sequence. Also, until the power up sequence completes, the input/output buffers are kept in a
high impedance state, and so may be driven but do not drive power out.
7
2401D–PLD–09/02
Power-on Reset
The ATF15xx Family devices are designed with a power-on reset, a feature critical for state
machine initialization. At a point delayed slightly from VCC crossing VRST, all registers will be
initialized, and the state of each output will depend on the polarity of its buffer. However, due
to the asynchronous nature of reset and uncertainty of how VCC actually rises in the system,
the following conditions are required:
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup times must be met before driving the
clock pin high, and,
3. The clock must remain stable during TD.
The ATF15xx Family has two options for the hysteresis about the reset level, VRST, Small and
Large. In applications where the supply voltage may drop below 4.0V, Atmel recommends that
during the fitting process users configure the device with the Power-on Reset hysteresis set to
Large to ensure a robust operating environment.
Power Down of
Unused
Macrocells
To conserve power, Atmel fitters automatically power down all unused macrocells.
Input Transition
Detection/
Automatic Power
Down
The ATF15xxSEL versions provide automatic power-down to µA level stand-by power (the “L”
suffix indicates “Low” power) through Atmel’s patented Input Transition Detection (ITD) circuitry on Global Clocks, Inputs and I/O. These ITD circuits automatically put the device into a
low-power standby mode when no logic transitions are occurring. This reduces power consumption during inactive periods, and so provides proportional power savings for most
applications running at system speeds below fCRITICAL (~5 MHz).
In clocked applications, where the device is operated at a frequency high enough to keep the
device from going into stand-by (above fCRITICAL), the device will perform at the faster speeds
given in the next faster speed column. These higher speeds can be achieved in combinatorial
designs as well, as long as once activated by an initial input transition, the device continues to
receive input transitions often enough to keep the device from going into standby mode again.
That is, the time between input transitions is less than 1/fCRITICAL.
Reduced-Power
per Macrocell
To further reduce power, each ATF15xxSE Family macrocell has a reduced-power bit feature.
With this feature the designer can reduce power by 50% or more for logic that does not need
to operate at the maximum switching speed. The reduced-power bit may be activated by
changing the default OFF to ON for any or all macrocells. For macrocells in reduced-power
mode (reduced-power bit turned on), the reduced- power adder, tRPA, must be added to the
AC parameters, which include the data paths tLAD, tLAC, tIC, tACL, tACH and tSEXP. All power-down
AC characteristic parameters are computed from external input or I/O pins, with the reducedpower bit turned on.
Slew Rate Control
Each output also has individual slew rate control. This may be used to reduce system noise by
slowing down outputs that do not need to operate at maximum speed. Outputs default to slow
switching. The slew rate option is selected in the design source file.
Pin Controlled
Power-down
All ATF15xx Family devices also have an optional pin-controlled power-down mode. When
activated, one or both of two pins, PD1 and PD2, can act as power-down pins. The device
goes into power-down when either PD1 or PD2 pins (or both) are high, and the device supply
current is reduced to less than 1 mA. Also, all internal logic signals are latched and held, as
are any enabled outputs. Therefore, all registered and combinatorial output data remain valid.
Any outputs that were in a high-Z state at the onset will remain at high-Z. Input and I/O hold
8
ATF15xxSE Family
2401D–PLD–09/02
ATF15xxSE Family
latches remain active to ensure that pins do not float to indeterminate levels, further reducing
system power. All pin transitions are ignored until the PD pin is brought low. When the powerdown feature is enabled for PD1 or PD2, that pin cannot be used as a logic input or output.
However, the pin’s macrocell may still be used to generate buried foldback and cascade logic
signals. The power-down option is selected in the design source file.
Power
Consumption
Estimates
An estimate of power consumption can be made based on typical designs and operation conditions, but because it is sensitive to these factors, power consumption must be verified with
actual pattern and operation conditions. The equations given below are based on a pattern of
16-bit up/down counters in each logic block and may be used to estimate power consumption
for both operating modes.
Standby Power
1. Pstandby = Iccstandby x Vsupply
Where:
Iccstandby = the standby current given for the particular device and standby mode (e.g. pin controlled Power Down)
Vsupply= the power supply voltage
Active Power
2. Pactive = Pinternal + Pload = Iccinternal x Vsupply + Pload
Where:
Iccinternal = the internal current estimated from equation 3 below
Vsupply= the power supply voltage
Pload = depends on the device output load capacitance and switching frequency on each output pin.
Pload and additional power savings at low frequencies using Atmel Input Transition Detection
(“L” versions) can be estimated according to the methods discussed in the Atmel Application
Note “Saving Power with Atmel PLDs”
3. Iccinternal = [K1 x (MCinuse – MCreducedpower )] + (K2 x MCreducedpower) + (K3 x MCinuse x fop x
NS)
Where:
MCreducedpower = the number of macrocells operating at reduced power (from fitter report file)
MCinuse= the number of macrocells in use (from fitter report file. Unused macrocells are powered down.)
NS = the proportion of logic nodes switching (typically 10-20%)
fop = the switching frequency
K1, K2,and K3 = device constants given in the table below.
Device
K1 (mA/MC)
K2 (mA/MC)
K3 (mA/MC · MHz)
ATF1502SE
0.6
0.3
0.015
ATF1504SE
0.6
0.3
0.015
ATF1508SE
0.6
0.3
0.015
ATF1516SE
0.6
0.3
0.015
Note:
Shaded data is preliminary and subject to change without notice.
9
2401D–PLD–09/02
Design
Software
Atmel ATF15xxSE Family fitters allow logic synthesis using a variety of high-level description
languages and formats. ATF15xxSE Family designs are supported by Atmel specific design
tools as well as by several third-party tools. Free conversion software is also offered for industry standard devices. Check the Atmel web site or contact your authorized Atmel sales
representative for up-to-date design software information.
Programming
ATF15xxSE Family devices can be programmed using standard third-party programmers.
With third-party programmers, the JTAG ISP port can be disabled thereby allowing four additional I/O pins to be used for logic. Check the Atmel web site, contact your authorized Atmel
sales representative or Atmel PLD Applications for details of third-party programmers.
ATF15xxSE Family devices are in-system programmable (ISP) devices utilizing the 4-pin
JTAG protocol. This capability eliminates package handling normally required for programming and facilitates rapid design iterations and field changes. Atmel provides ISP hardware
and software to allow programming of the ATF15xxSE Family via the PC. ISP is performed by
using either a download cable, a compatible board tester or a simple microprocessor interface.
It is most common to devote the JTAG pins to ISP, but it is possible to use ISP to program the
part through the JTAG pins, and set these four pins I/O pins. However, this will effectively disable further ISP and the device will need to be erased on a programmer to re-enable ISP.
Contact Atmel PLD Applications by email at pld@atmel.com or call our Hotline at (408) 4364333 for details.
To allow ISP programming support by the Automated Test Equipment (ATE) vendors, Serial
Vector Format (SVF) files can be created by the Atmel ISP software. Conversion to other ATE
tester formats is also possible. Check the Atmel web site for up-to-date programming and software support information.
ISP
Programming
Protection
The ATF15xxSE Family also incorporates a protection feature that locks the device and prevents the inputs and I/O from driving if the programming process is interrupted for any reason.
The inputs and I/O default to high-Z state during such a condition. In addition the pin-keeper
option preserves the former state during device programming.
All ATF15xxSE Family devices are initially shipped in the erased state thereby making them
ready to use for ISP.
For more information refer to the “Designing for In-System Programmability with Atmel
CPLDs” application note.
Security Fuse
Usage
10
A single fuse is provided to prevent unauthorized copying of the ATF15xxSE Family fuse patterns. Once programmed, fuse verify is inhibited. However, the User Signature and device ID
remain accessible.
ATF15xxSE Family
2401D–PLD–09/02
ATF15xxSE Family
JTAG-BST
Overview
The JTAG-BST (JTAG boundary-scan testing) is controlled by the Test Access Port (TAP)
controller. The boundary-scan technique involves the inclusion of a shift-register stage (contained in a boundary-scan cell) adjacent to each component so that signals at component
boundaries can be controlled and observed using scan testing principles. Each input pin and
I/O pin has its own Boundary-scan Cell (BSC) in order to support boundary-scan testing. The
ATF15xxSE Family does not currently include a Test Reset (TRST) input pin because the TAP
controller is automatically reset at power-up. The ATF15xxSE Family implements six BST
instructions, and seven Atmel-defined In System Programming (ISP) instructions. All ATF15xx
Family BST and ISP instructions have a length of 10 bits.
JTAG BST Instructions
Description
SAMPLE/PRELOAD
Captures signals at the device pins for later examination,
or loads a data pattern prior to an EXTEST instruction.
EXTEST
Allows testing of off-chip circuitry and interconnections
by forcing a pattern on the output pins or capturing
signals from the input pins.
BYPASS
Places a single shift register stage between TDI and
TDO, allowing test BST data to pass through a particular
device in a chain of devices.
IDCODE
Places the 32-bit IDCODE register between TDI and
TDO, allowing the IDCODE data to be shifted out of
TDO.
UESCODE
Places the 16-bit user electronic signature register
between TDI and TDO, allowing the UESCODE data to
be shifted out of TDO.
HIGHZ
Places the BYPASS register between TDI and TDO in a
high impedance mode, protecting the device from
damage from externally applied test signals.
7 ISP instructions
These seven instructions allow in-system programming
via the four JTAG pins.
The ATF15xxSE Family BST implementation complies with the Boundary-scan Definition Language (BSDL) described in the JTAG specification (IEEE Standard 1149.1). Any third-party
tool that supports the BSDL format can be used to perform BST on the ATF15xxSE Family.
The ATF15xxSE Family also has the option of using four JTAG-standard I/O pins for in-system
programming (ISP). The ATF15xxSE Family is programmable through the four JTAG pins
using programming-compatible with the IEEE JTAG Standard 1149.1. Programming is performed by using 5V TTL-level programming signals from the JTAG ISP interface. The JTAG
feature is a programmable option. If JTAG (BST or ISP) is not needed, then the four JTAG
control pins are available as I/O pins. Refer to Atmel Application Note “Designing for In-System Programmability with Atmel CPLDs for more details.
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2401D–PLD–09/02
JTAG
Boundary-scan
Cell (BSC)
Testing
The ATF15xxSE Family has four dedicated input pins and a number of I/O pins depending on
the device type and package type selected. Each input pin and I/O pin has a boundary-scan
cell (BSC) which supports boundary-scan testing as described in detail by IEEE Standard
1149.1. A typical BSC consists of three capture registers or scan registers and up to two
update registers. There are two types of BSCs, one for input or I/O pin, and one for the macrocells. The BSCs in the device are chained together through the (BST) capture registers. Input
to the capture register chain is fed in from the TDI pin while the output is directed to the TDO
pin. Capture registers are used to capture active device data signals, to shift data in and out of
the device and to load data into the update registers. Control signals are generated internally
by the JTAG TAP controller.
Boundary-Scan
Register Length
Device
12
LSB
ATF1502SE
96
0000,0001,0101,0100,0010,0000,0011,1111
ATF1504SE
192
0000,0001,0101,0100,0100,0000,0011,1111
ATF1508SE
352
0000,0001,0101,0100,1000,0000,0011,1111
ATF1516SE
672
0000,0001,0101,0101,0000,0000,0011,1111
Note:
Boundary-scan
Definition
Language
(BSDL) Models
IDCODE
MSB
Shaded data is preliminary and subject to change without notice.
These are now available in all package types via the Atmel web site. These models conform to
the IEEE 1149.1 standard and can be used for Boundary-scan Test Operation of the
ATF15xxSE Family.
The BSC configuration for the input and I/O pins and macrocells are shown on page 13.
ATF15xxSE Family
2401D–PLD–09/02
ATF15xxSE Family
BSC
Configuration
for Pins (Except
JTAG TAP Pins)
BSC
Configuration
for Macrocell
TDO
OEJ
0
0
1
D Q
D Q
1
OUTJ
0
0
Pin
1
D Q
D Q
Capture
Register
Update
Register
1
Mode
TDI
Shift
Clock
Macrocell BSC
13
2401D–PLD–09/02
PCI Voltage-toCurrent Curves for
+5V Signaling in
Pull-up Mode
The ATF15xx Family also supports peripheral component interconnect (PCI) interface standard in PCI-based designs and specifications. The PCI interface calls for high current drivers,
which are much larger than the traditional TTL drivers.
Pull Up
VCC
Test Point
Voltage
PCI Compliance
2.4
DC
drive point
1.4
AC drive
point
-44 Current (mA) -178
-2
Pull Down
VCC
AC drive
point
Voltage
PCI Voltage-toCurrent Curves for
+5V Signaling in
Pull-down Mode
2.2
DC
drive point
0.55
Test Point
3,6
14
95 Current (mA) 380
ATF15xxSE Family
2401D–PLD–09/02
ATF15xxSE Family
PCI DC Characteristics
Symbol
Parameter
VCC
Conditions
Min
Max
Units
Supply Voltage
4.75
5.25
V
VIH
Input High Voltage
2.0
VCC + 0.5
V
VIL
Input Low Voltage
-0.5
0.8
V
IIH
Input High Leakage Current
VIN = 2.7V
70
µA
IIL
Input Low Leakage Current
VIN = 0.5V
-70
µA
VOH
Output High Voltage
IOUT = -2 mA
VOL
Output Low Voltage
IOUT = 3 mA, 6 mA
CIN
2.4
V
0.55
V
Input Pin Capacitance
10
pF
CCLK
CLK Pin Capacitance
12
pF
CIDSEL
IDSEL Pin Capacitance
8
pF
LPIN
Pin Inductance
20
nH
Note:
Leakage current is without pin-keeper off.
PCI AC Characteristics
Symbol
Parameter
Conditions
Min
IOH(AC)
Switching
0 < VOUT ≤ 1.4
-44
mA
1.4 < VOUT < 2.4
-44+(VOUT - 1.4)/0.024
mA
Current High
IOL(AC)
Max
Units
3.1 < VOUT < V CC
Equation A
mA
(Test High)
VOUT = 3.1V
-142
µA
Switching
VOUT > 2.2V
95
mA
2.2 > VOUT > 0
VOUT/0.023
mA
Current Low
0.1 > VOUT > 0
Equation B
mA
(Test Point)
VOUT = 0.71
206
mA
ICL
Low Clamp Current
-5 < VIN ≤ -1
-25+(VIN + 1)/0.015
SLEWR
Output Rise Slew Rate
0.4V to 2.4V load
0.5
3.0
V/ns
SLEWF
Output Fall Slew Rate
2.4V to 0.4V load
0.5
3.0
V/ns
Notes:
mA
1. Equation A: IOH = 11.9 (VOUT - 5.25) * (VOUT + 2.45) for VCC > VOUT > 3.1V.
2. Equation B: IOL = 78.5 * VOUT * (4.4 - VOUT ) for 0V < VOUT < 0.71V.
15
2401D–PLD–09/02
Absolute Maximum Ratings*
Ambient Temperature Under Bias.................. -65°C to +135°C
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Storage Temperature ..................................... -65°C to +150°C
Junction Temperature ..............................................150°C(MAX)
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V(1)
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
Note:
1. For currents less than 100 mA, minimum voltage
is -0.6 VDC and maximum voltage is VCC +
0.75 VDC. Pulses of less than 20µs may undershoot to -2.0V or overshoot to 7.0V.
DC Output Current per Pin ................................ -25 to +25 mA
DC and AC Operating Conditions
Commercial
Industrial
0°C - 70°C
-40°C - 85°C
–
–
VCCINT (5.0V) Power Supply
5V ± 5%
5V ± 10%
VCCIO (5.0V) Power Supply
5V ± 5%
5V ± 10%
VCCIO (3.3V) Power Supply
3.0 - 3.6
3.0 - 3.6
-0.5 - VCCINT + .5
-0.5 - V CCINT + .5
0 - VCCIO
0 - VCCIO
tR
40 ns Max
40 ns Max
tF
40 ns Max
40 ns Max
Operating Temperature (Ambient), TA
(1)
Junction Temperature, TJ
VI Input Voltage
VO Output Voltage
Note:
16
1. Junction temperature is package and device dependant and can be calculated as follows: TJ(MAX) = TA(MAX) + (θJA|Air Flow =
0*P(MAX)). For more information see “Thermal Characteristics of Atmel Packages.”
ATF15xxSE Family
2401D–PLD–09/02
ATF15xxSE Family
DC Characteristics(1) ATFxxSE Family
Symbol
Parameter
Condition
IIL
Input or I/O Low Leakage Current
VIN = VCC
IIH
Input or I/O High Leakage Current
IOZ
Tri-State Output Off-State Current
Power Supply Current, Standby
ICC1
Min
VO = VCC or GND
VCC = Max
VIN = 0, VCC
ICC3(2)
Power Supply Current,
Power-down Mode
VCC = Max
VIN = 0, VCC
Reduced-power Mode Supply
Current, Standby
VCC = Max
VIN = 0, VCC
Min
Unit
-2
-10
µA
2
10
µA
40
µA
-40
Std Mode
“ITD”
Mode
ICC2
Typ
Com.
(3)
mA
Ind.
(3)
mA
Com.
1
mA
Ind.
1
mA
PD Mode
Std Mode
0.1
1
mA
Com.
(3)
mA
Ind.
(3)
mA
VIL
Input Low Voltage
-0.3
0.8
V
VIH
Input High Voltage
2.0
VCCINT
+0.5
V
VOL
5.0V Output Low Voltage (TTL)
IOL = 12 mA, V CCIO = 4.75V
0.45
V
3.3V Output Low Voltage (TTL)
IOL = 12 mA, V CCIO = 3.0V
0.45
V
3.3V Output Low Voltage (CMOS)
IOL = 0.1 mA, VCCIO = 3.0V
0.2
V
5.0V Output High Voltage (TTL)
IOH = -4 mA, V CCIO = 4.75V
2.4
V
3.3V Output High Voltage (TTL)
IOH = -4 mA, V CCIO = 3.0V
2.4
V
3.3V Output High Voltage (CMOS)
IOH = -0.1 mA, VCCIO = 3.0V
VCCIO – 0.2
V
VOH
Notes:
1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
2. ICC3 refers to the current in the reduced-power mode when macrocell reduced-power is turned ON.
3. See characteristic curves for each device.
Power-down AC Characteristics(1) ATFxxSE Family
-5
Symbol
tIVDH
tGVDH
Parameter
Min
Valid 1, I/O before PD High
Valid 1, OE
(2)
Max
Min
Max
Min
-15
Max
Min
Max
Unit
7.0
10
15
ns
before PD High
5.0
6.0
7.0
10
15
ns
(2)
5.0
6.0
7.0
10
15
ns
tDHIX
I, I/O Don’t Care after PD High
OE
Min
-10
6.0
Valid 1, Clock
tDHGX
Max
-7
5.0
tCVDH
(2)
-6
before PD High
9.0
10.0
12
15.0
25
ns
Don’t Care after PD High
9.0
10.0
12
15.0
25
ns
(2)
9.0
10.0
12
15.0
25
ns
tDHCX
Clock
tDLIV
PD Low to Valid I, I/O
1.0
1.0
1.0
1.0
1.0
µs
tDLGV
PD Low to Valid OE, (Pin or Term)
1.0
1.0
1.0
1.0
1.0
µs
tDLCV
PD Low to Valid Clock, (Pin or Term)
1.0
1.0
1.0
1.0
1.0
µs
tDLOV
PD Low to Valid Output
1.0
1.0
1.0
1.0
1.0
µs
Notes:
Don’t Care after PD High
1. For slow slew outputs, add tSSO.
2. Pin or product term.
17
2401D–PLD–09/02
Timing Model
U
Pin Capacitance
Typ(1)
Max
Units
CIN
8
10
pF
VIN = 0V; f = 1.0 MHz
CI/O
8
10
pF
VOUT = 0V; f = 1.0 MHz
Note:
Condition
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. The OGI pin (high-voltage
pin during programming) has a maximum capacitance of 12 pF.
Input Test
Waveforms and
Measurement
Levels
Output AC Test
Loads
5.0V
(3.3V)
464
(703 )
250
(8060 )
18
C = CL
ATF15xxSE Family
2401D–PLD–09/02
ATF1502SE
AC Characteristics(1) ATF1502SE(L)
SE -5
Symbol
Parameter
Min
SE -6
Max
Min
Max
SE -7
Min
Max
SE -10
Min
Max
SEL -15(6)
Min
Max
Unit
tPD1
Input or Feedback to Nonregistered Output
5.0
6.0
7.5
10
15
ns
tPD2
I/O Input or Feedback to Nonregistered Feedback
5.0
6.0
7.5
10
12
ns
tSU
Global Clock Setup Time
2.9
4.0
5.0
7.0
11
ns
tH
Global Clock Hold Time
0.0
0.0
0.0
0.0
0.0
ns
tFSU
Global Clock Setup Time of Fast
Input
2.5
2.5
2.5
3.0
3.0
ns
tFH
Global Clock Hold of Fast Input
0.0
0.0
0.0
0.0
1.0
ns
tCO1
Global Clock to Output Delay
tCH
Global Clock High Time
2.0
2.5
3.0
4.0
5.0
ns
tCL
Global Clock Low Time
2.0
2.5
3.0
4.0
5.0
ns
tASU
Array Clock Setup Time
0.7
0.9
1.1
2.0
4.0
ns
tAH
Array Clock Hold Time
1.8
2.1
2.7
3.0
4.0
ns
3.2
3.5
4.3
5.0
8.0
ns
tACO1
Array Clock Output Delay
tACH
Array Clock High Time
2.5
2.5
3.0
4.0
6.0
ns
tACL
Array Clock Low Time
2.5
2.5
3.0
4.0
6.0
ns
tCNT
Minimum Clock Global Period
fCNT(3)
Maximum Internal Global Clock
Frequency
tACNT
Minimum Array Clock Period
fACNT
(4)
Maximum Internal Array Clock
Frequency
5.4
5.4
5.7
175.4
6.6
7.0
143
5.7
8.2
8.6
117
7.0
15
10.0
100
8.6
13
77 or
100(6)
10.0
ns
ns
MHz
13
ns
175.4
143
117
100
77 or
100(6)
MHz
250
200
167
125
80 or
125(6)
MHz
fMAX(5)
Maximum Clock Frequency
tIN
Input Pad and Buffer Delay
0.2
0.2
0.3
0.5
1.0
ns
tIO
I/O Input Pad and Buffer Delay
0.2
0.2
0.3
0.5
1.0
ns
tFIN
Fast Input Delay
2.2
2.1
2.5
1.0
1.5
ns
tSEXP
Foldback Term Delay
3.1
3.8
4.6
5.0
8.0
ns
tPEXP
Cascade Logic Delay
0.9
1.1
1.4
0.8
1.0
ns
tLAD
Logic Array Delay
2.6
3.3
4.0
5.0
6.0
ns
tLAC
Logic Control Delay
2.5
3.3
4.0
5.0
6.0
ns
tIOE
Internal Output Enable Delay
0.7
0.8
1.0
2.0
3.0
ns
tOD1
Output Buffer and Pad Delay
(slow slew rate = OFF; VCCIO =
5V; CL= 35 pF)
0.2
0.3
0.4
1.5
2.5
ns
19
2401D–PLD–09/02
AC Characteristics(1) ATF1502SE(L) (Continued)
SE -5
Symbol
Min
Max
Min
Max
SE -7
Min
Max
SE -10
Min
Max
SEL -15(6)
Min
Max
Unit
tOD2
Output Buffer and Pad Delay
(slow slew rate = OFF; VCCIO =
3.3V; CL= 35 pF)
0.7
0.8
0.9
2.0
3.0
ns
tOD3
Output Buffer and Pad Delay
(slow slew rate = ON; VCCIO = 5V
or 3.3V; CL= 35 pF)
5.2
5.3
5.4
5.5
6.0
ns
tZX1
Output Buffer Enable Delay
(slow slew rate = OFF; VCCIO =
5V; CL= 35 pF)
4.0
4.0
4.0
5.0
7.0
ns
tZX2
Output Buffer Enable Delay
(slow slew rate = OFF; VCCIO =
3.3V; CL= 35 pF)
4.5
4.5
4.5
5.5
7.0
ns
tZX3
Output Buffer Enable Delay
(slow slew rate = ON; VCCIO = 5V
or 3.3V;
CL= 35 pF)
9.0
9.0
9.0
9.0
10
ns
tXZ
Output Buffer Disable Delay
(CL= 5 pF)
4.0
4.0
4.0
5.0
6.0
ns
tSU
Register Setup Time
0.8
1.0
1.3
2.0
4.0
ns
tH
Register Hold Time
1.7
2.0
2.5
3.0
4.0
ns
tFSU
Register Setup Time of Fast
Input
1.9
1.7
1.7
3.0
5.0
ns
tFH
Register Hold Time of Fast Input
0.6
0.7
0.8
0.5
2.0
ns
tRD
Register Delay
1.2
1.6
1.2
2.0
2.0
ns
Combinatorial Delay
0.9
1.1
1.0
2.0
2.0
ns
tIC
Array Clock Delay
2.7
3.4
2.0
5.0
7.0
ns
tEN
Register Enable Time
2.6
3.3
1.0
5.0
7.0
ns
tGLOB
Global Control Delay
1.6
1.4
1.3
1.0
1.0
ns
tPRE
Register Preset Time
2.0
2.4
1.9
3.0
5.0
ns
tCLR
Register Clear Time
2.0
2.4
3.0
3.0
5.0
ns
tUIM
Switch Matrix Delay
1.1
1.1
1.4
1.0
2.0
ns
tCOMB
tRPA(2)
Notes:
20
Parameter
SE -6
Reduced Power Adder
8
9
10
11
13
ns
1. See ordering Information for valid part numbers.
2. The tRPA parameter must be added to the tLAD, tLAC, tIC, tACL and tSEXP parameters for macrocells running in the reducedpower mode.
3. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable, and a PIA fan-out of one
logic block (16 macrocells). fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG.
4. fACNT is the fastest 16-bit counter frequency available, using the internal array clock, local feedback when applicable and a
PIA fan-out of one logic block (16 macrocells).
5. fMAX is the fastest available frequency for pipelined data.
6. For clocked applications and frequencies above fCRITICAL, OR, non-clocked applications with dormant times less than 1/fCRITICAL, the device will achieve the speeds of the –10 column. See “Input Transition Detection/ Automatic Power Down” on page
8.
ATF1502SE
2401D–PLD–09/02
ATF1502SE
STAND-BY ICC VS.
NORMALIZED ICC VS. TEMP
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.4
TBD
4.5
4.8
5.0
1.2
NORMALIZED Icc
ICC (µA)
SUPPLY VOLTAGE (TA = 25°C)
5.3
1.0
TBD
0.8
0.6
0.4
-40.0
5.5
SUPPLY VOLTAGE (V)
25.0
75.0
TEMPERATURE (C)
SUPPLY CURRENT VS.
INPUT FREQUENCY (VCC = 5.0V, T A = 25°C)
SUPPLY CURRENT VS.
INPUT FREQUENCY (V CC = 5.0V, TA = 25°C)
1.000
120.000
0.800
ICC (mA)
140.000
100.000
ICC (mA)
0.0
80.000
0.600
TBD
0.400
TBD
0.200
60.000
0.000
40.000
0.0
0.5
2.5
5.0
20.000
7.5
10.0
25.0
37.5
50.0
FREQUENCY (MHz)
0.000
0.0
0.5
2.5
5.0
7.5
10.0
FREQUENCY (MHz)
25.0
37.5
50.0
OUTPUT SOURCE CURRENT VS.
SUPPLY VOLTAGE (VOH = 2.4V)
0
0.0
-10.0
-10
-20.0
-20
TBD
-30
IOH (mA)
IOH (mA)
OUTPUT SOURCE CURRENT VS.
OUTPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
-40
-50
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
5.5
-30.0
-40.0
TBD
-50.0
-60.0
-70.0
6.0
-80.0
-90.0
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
4.50
5.00
VOH (V)
OUTPUT SINK CURRENT VS.
SUPPLY VOLTAGE (VOL = 0.5V)
48
OUTPUT SINK CURRENT VS.
OUTPUT VOLTAGE (V CC = 5.0V, TA = 25°C)
140.0
120.0
44
42
100.0
TBD
IOL (mA)
Iol (mA)
46
40
38
80.0
TBD
60.0
40.0
36
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
5.5
6.0
20.0
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
21
2401D–PLD–09/02
INPUT CLAMP CURRENT VS.
INPUT VOLTAGE (V CC = 5.0V, TA = 35°C)
40
INPUT CURRENT
(uA)
INPUT CURRENT
(mA)
0
-20
-40
TBD
-60
-80
-100
-120
0.0
-0.2
-0.4
-0.6
INPUT VOLTAGE (V)
INPUT CURRENT VS.
INPUT VOLTAGE (VCC = 5.0V, T A = 25°C)
-0.8
30
20
10
TBD
0
-10
-20
-30
-1.0
0.0
NORMALIZED TPD VS. VCC
NORMALIZED TPD
NORMALIZED TPD
1.1
TBD
1.0
0.9
4.5
4.8
5.0
5.3
TBD
0.9
0.8
-40.0
5.5
NORMALIZED TCO VS. VCC
0.0
25.0
TEMPERATURE (C)
75.0
NORMALIZED T CO VS. TEMP
1.1
NORMALIZED TCO
NORMALIZED TCO
6.0
1.0
SUPPLY VOLTAGE (V)
1.2
1.1
TBD
1.0
0.9
4.5
4.8
5.0
SUPPLY VOLTAGE (V)
5.3
1.0
TBD
0.9
0.8
-40.0
0.8
5.5
0.0
25.0
75.0
TEMPERATURE (V)
NORMALIZED TSU VS. VCC
NORMALIZED TSU VS. TEMP
1.2
1.2
NORMALIZED TCO
NORMALIZED TSU
5.0
1.1
0.8
1.1
TBD
1.0
0.9
0.8
4.5
22
2.0
3.0
4.0
INPUT VOLTAGE (V)
NORMALIZED T PD VS. TEMP
1.2
1.3
1.0
4.8
5.0
SUPPLY VOLTAGE (V)
5.3
5.5
1.1
1.0
TBD
0.9
0.8
-40.0
0.0
25.0
75.0
TEMPERATURE (C)
ATF1502SE
2401D–PLD–09/02
ATF1502SE
DELTA TPD VS.
OUTPUT LOADING
8
8.00
7.00
DELTA T CO (ns)
6
DELTA T PD (ns)
DELTA TCO VS.
OUTPUT LOADING
4
TBD
2
0
6.00
5.00
TBD
4.00
3.00
2.00
1.00
-2
0.00
0
50
100
150
200
250
300
50
100
OUTPUT LOADING (PF)
150
200
250
300
NUMBER OF OUTPUTS LOADING
DELTA TCO VS. # OF OUTPUT SWITCHING
DELTA TPD VS. # OF OUTPUT SWITCHING
DELTA TCO (ns)
DELTA TPD (ns)
0.0
0.0
-0.1
-0.2
TBD
-0.3
-0.1
TBD
-0.2
-0.4
-0.3
-0.5
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
NUMBER OF OUTPUTS SWITCHING
9.0
10.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
NUMBER OF OUTPUTS SWITCHING
23
2401D–PLD–09/02
ATF1502SE(L) Pinouts
ATF1502SE(L)
ATF1504SE(L)
39
38
37
36
35
34
33
32
31
30
29
18
19
20
21
22
23
24
25
26
27
28
7
8
9
10
11
12
13
14
15
16
17
I/O
I/O/TDO
I/O
I/O
VCC
I/O
I/O
I/O/TCK
I/O
GND
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
PD2/I/O
I/O
I/O
I/O
TDI/I/O
I/O
I/O
GND
PD1/I/O
I/O
I/O/TMS
I/O
VCC
I/O
I/O
6
5
4
3
2
1
44
43
42
41
40
I/O
I/O
I/O
VCC
GCK2/OE2/I
GCLR/I
OE1/I
GCK1/I
GND
I/O/GCLK3
I/O
44-lead TQFP - Top View
44
43
42
41
40
39
38
37
36
35
34
I/O
I/O
I/O
VCC
I/OE2/GCK2
GCLR/I
I/OE1
GCK1/I
GND
GCK3
I/O
44-lead PLCC - Top View
1
2
3
4
5
6
7
8
9
10
11
ATF1502SE(L)
ATF1504SE(L)
33
32
31
30
29
28
27
26
25
24
23
I/O
I/O/TDO
I/O
I/O
VCC
I/O
I/O
I/O/TCK
I/O
GND
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
PD2/I/O
I/O
I/O
I/O
12
13
14
15
16
17
18
19
20
21
22
I/O/TDI
I/O
I/O
GND
PD1/I/O
I/O
TMS/I/O
I/O
VCC
I/O
I/O
24
ATF1502SE
2401D–PLD–09/02
ATF1502SE
ATF1502SE(L) Dedicated Pinouts
Dedicated Pin
44-PLCC
J-lead
44-lead
TQFP
INPUT/GCLK1
43
37
INPUT/GCLR
1
39
INPUT/OE1
44
38
INPUT/OE2/GCLK2
2
40
I/O/GCLK3
41
35
I/O/PD (1,2)
11, 25
5, 19
I/O/TDI (JTAG)
7
1
I/O/TMS (JTAG)
13
7
I/O/TCK (JTAG)
32
26
I/O/TDO (JTAG)
38
32
GNDINT
22, 42
16, 36
GNDIO
10, 30
4, 24
VCCINT
3, 23
17, 41
VCCIO
15, 35
9, 29
# of Signal Pins
36
36
# User I/O Pins
32
32
OE (1, 2) Global OE pins
GCLR Global Clear pin
GCLK (1, 2, 3) Global Clock pins
PD (1, 2) Power-down pins
TDI, TMS, TCK, TDO JTAG pins used for boundary-scan testing or in-system programming
GNDINT Ground pins for the internal device logic
GNDIO Ground pins for the I/O drivers
VCCINT VCC pins for the internal device logic (+3.3V)
VCCIO VCC for the I/O drivers
25
2401D–PLD–09/02
ATF1502SE(L) I/O Pinouts
26
MC
PLC
44-lead PLCC
44-lead TQFP
1
A
4
42
2
A
5
43
3
A
6
44
4/TDI
A
7
1
5
A
8
2
6
A
9
3
7/PD1
A
11
5
8
A
12
6
9/TMS
A
13
7
10
A
14
8
11
A
16
10
12
A
17
11
13
A
18
12
14
A
19
13
15
A
20
14
16
A
21
15
17
B
41
35
18
B
40
34
19
B
39
33
20/TDO
B
38
32
21
B
37
31
22
B
36
30
23
B
34
28
24
B
33
27
25/TCK
B
32
26
26
B
31
25
27
B
29
23
28
B
28
22
29
B
27
21
30
B
26
20
31/PD2
B
25
19
32
B
24
18
ATF1502SE
2401D–PLD–09/02
ATF1502SE
ATF1502SE(L) Ordering Information
tPD
(ns)
tCO1
(ns)
FMAX
(MHz)
5.0
3.2
6.0
7.5
10
15
Ordering Code
Package
Operation Range
250
ATF1502SE-5 AC44
ATF1502SE-5 JC44
44A
44J
Commercial
(0°C to 70°C)
3.5
200
ATF1502SE-6 AC44
ATF1502SE-6 JC44
44A
44J
Commercial
(0°C to 70°C)
4.3
167
ATF1502SE-7 AC44
ATF1502SE-7 JC44
44A
44J
Commercial
(0°C to 70°C)
ATF1502SE-7 AI44
ATF1502SE-7 JI44
44A
44J
Industrial
(-40°C to +85°C)
ATF1502SE-10 AC44
ATF1502SE-10 JC44
44A
44J
Commercial
(0°C to 70°C)
ATF1502SE-10 AI44
ATF1502SE-10 JI44
44A
44J
Industrial
(-40°C to +85°C)
ATF1502SEL-15 AC44
ATF1502SEL-15 JC44
44A
44J
Commercial
(0°C to 70°C)
5.0
8.0
125
77
Using “C” Product for Industrial
To use commercial product for industrial temperature ranges, downgrade one speed grade from the “I” to the “C” device,
and de-rate power by 30%.
Package Type
44A
44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)
44J
44-lead, Plastic J-leaded Chip Carrier (PLCC)
27
2401D–PLD–09/02
AC Characteristics(1) ATF1504SE(L)
SE -5
Symbol
Parameter
Min
Max
SE -6
Min
Max
SE -7
Min
Max
SE -10
Min
Max
SEL -15(6)
Min
Max
Unit
tPD1
Input or Feedback to Nonregistered Output
5.0
6.0
7.5
10
15
ns
tPD2
I/O Input or Feedback to Nonregistered Feedback
5.0
6.0
7.5
10
12
ns
tSU
Global Clock Setup Time
2.9
3.6
6.0
7.0
11
ns
tH
Global Clock Hold Time
0.0
0.0
0.0
0.0
0.0
ns
tFSU
Global Clock Setup Time of Fast
Input
2.5
2.5
3.0
3.0
3.0
ns
tFH
Global Clock Hold of Fast Input
0.0
0.0
0.5
0.5
1.0
ns
tCO1
Global Clock to Output Delay
tCH
Global Clock High Time
2.0
2.5
3.0
4.0
5.0
ns
tCL
Global Clock Low Time
2.0
2.5
3.0
4.0
5.0
ns
tASU
Array Clock Setup Time
0.7
0.9
2.0
2.0
5.0
ns
tAH
Array Clock Hold Time
1.8
2.9
2.0
3.0
4.0
ns
3.2
4.0
4.5
5.0
9.0
ns
tACO1
Array Clock Output Delay
tACH
Array Clock High Time
2.5
2.5
3.0
4.0
6.0
ns
tACL
Array Clock Low Time
2.5
2.5
3.0
4.0
6.0
ns
tCNT
Minimum Clock Global Period
fCNT(3)
Maximum Internal Global Clock
Frequency
tACNT
Minimum Array Clock Period
5.4
6.7
5.7
176
7.5
7.1
141
5.7
10.0
8.0
125
7.1
15
10
100
8.0
13
77
10
ns
ns
MHz
13
ns
fACNT(4)
Maximum Internal Array Clock
Frequency
176
141
125
100
77
MHz
fMAX(5)
Maximum Clock Frequency
250
200
167
125
77
MHz
tIN
Input Pad and Buffer Delay
0.2
0.2
0.5
0.5
1.0
ns
tIO
I/O Input Pad and Buffer Delay
0.2
0.2
0.5
0.5
1.0
ns
tFIN
Fast Input Delay
2.2
2.6
1.0
1.0
2.0
ns
tSEXP
Foldback Term Delay
3.1
3.8
4.0
5.0
8.0
ns
tPEXP
Cascade Logic Delay
0.9
1.1
0.8
0.8
1.0
ns
tLAD
Logic Array Delay
2.6
3.2
3.0
5.0
6.0
ns
tLAC
Logic Control Delay
2.5
3.2
3.0
5.0
6.0
ns
tIOE
Internal Output Enable Delay
0.7
0.8
2.0
2.0
3.0
ns
tOD1
Output Buffer and Pad Delay
(slow slew rate = OFF; VCCIO =
5V; C L= 35 pF)
0.2
0.3
2.0
1.5
2.5
ns
28
ATF1504SE(L)
2401D–PLD–09/02
ATF1504SE(L)
AC Characteristics(1) ATF1504SE(L) (Continued)
SE -5
Symbol
Parameter
Min
Max
SE -6
Min
Max
SE -7
Min
Max
SE -10
Min
Max
SEL -15(6)
Min
Max
Unit
tOD2
Output Buffer and Pad Delay
(slow slew rate = OFF; VCCIO =
3.3V; CL= 35 pF)
0.7
0.8
2.5
2.0
3.0
ns
tOD3
Output Buffer and Pad Delay
(slow slew rate = ON; VCCIO = 5V
or 3.3V; C L= 35 pF)
5.2
5.3
7.0
5.5
6.0
ns
tZX1
Output Buffer Enable Delay
(slow slew rate = OFF; VCCIO =
5V; C L= 35 pF)
4.0
4.0
4.0
5.0
7.0
ns
tZX2
Output Buffer Enable Delay
(slow slew rate = OFF; VCCIO =
3.3V; CL= 35 pF)
4.5
4.5
4.5
5.5
7.0
ns
tZX3
Output Buffer Enable Delay
(slow slew rate = ON; VCCIO = 5V
or 3.3V; C L= 35 pF)
9.0
9.0
9.0
9.0
10
ns
tXZ
Output Buffer Disable Delay
(CL= 5 pF)
4.0
4.0
4.0
5.0
6.0
ns
tSU
Register Setup Time
0.8
1.0
3.0
2.0
5.0
ns
tH
Register Hold Time
1.7
2.0
2.0
3.0
4.0
ns
tFSU
Register Setup Time of Fast
Input
1.9
1.8
3.0
3.0
5.0
ns
tFH
Register Hold Time of Fast Input
0.6
0.7
0.5
0.5
2.0
ns
tRD
Register Delay
1.2
1.6
1.0
2.0
2.0
ns
Combinatorial Delay
0.9
1.0
1.0
2.0
2.0
ns
tIC
Array Clock Delay
2.7
3.3
3.0
5.0
6.0
ns
tEN
Register Enable Time
2.6
3.2
3.0
5.0
6.0
ns
tGLOB
Global Control Delay
1.6
1.9
1.0
1.0
2.0
ns
tPRE
Register Preset Time
2.0
2.4
2.0
3.0
4.0
ns
tCLR
Register Clear Time
2.0
2.4
2.0
3.0
4.0
ns
tUIM
Switch Matrix Delay
1.1
1.3
1.0
1.0
2.0
ns
tCOMB
Reduced Power Adder
8.0
9.0
1.0
11
13
ns
tRPA(2)
Notes: 1. See ordering Information for valid part numbers.
2. The tRPA parameter must be added to the tLAD, tLAC, tIC, tACL and tSEXP parameters for macrocells running in the reducedpower mode.
3. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable, and a PIA fan-out of one
logic block (16 macrocells). fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG.
4. fACNT is the fastest 16-bit counter frequency available, using the internal array clock, local feedback when applicable and a
PIA fan-out of one logic block (16 macrocells).
5. fMAX is the fastest available frequency for pipelined data.
6. For clocked applications and frequencies above fCRITICAL, OR, non-clocked applications with dormant times less than 1/fCRITICAL, the device will achieve the speeds of the –10 column. See “Input Transition Detection/ Automatic Power Down” on page
8.
29
2401D–PLD–09/02
STAND-BY ICC VS.
NORMALIZED ICC VS. TEMP
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.4
TBD
4.5
4.8
5.0
1.2
NORMALIZED Icc
ICC (µA)
SUPPLY VOLTAGE (TA = 25°C)
5.3
1.0
TBD
0.8
0.6
0.4
-40.0
5.5
SUPPLY VOLTAGE (V)
25.0
75.0
TEMPERATURE (C)
SUPPLY CURRENT VS.
INPUT FREQUENCY (VCC = 5.0V, T A = 25°C)
SUPPLY CURRENT VS.
INPUT FREQUENCY (VCC = 5.0V, TA = 25°C)
1.000
120.000
0.800
ICC (mA)
140.000
100.000
ICC (mA)
0.0
80.000
0.600
TBD
0.400
TBD
0.200
60.000
0.000
40.000
0.0
0.5
2.5
5.0
20.000
7.5
10.0
25.0
37.5
50.0
FREQUENCY (MHz)
0.000
0.0
0.5
2.5
5.0
7.5
10.0
FREQUENCY (MHz)
25.0
37.5
50.0
OUTPUT SOURCE CURRENT VS.
SUPPLY VOLTAGE (VOH = 2.4V)
0
0.0
-10.0
-10
-20.0
-20
TBD
-30
IOH (mA)
IOH (mA)
OUTPUT SOURCE CURRENT VS.
OUTPUT VOLTAGE (VCC = 5.0V, T A = 25°C)
-40
-50
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
5.5
-30.0
-40.0
TBD
-50.0
-60.0
-70.0
6.0
-80.0
-90.0
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
4.50
5.00
VOH (V)
OUTPUT SINK CURRENT VS.
SUPPLY VOLTAGE (VOL = 0.5V)
48
OUTPUT SINK CURRENT VS.
OUTPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
140.0
120.0
44
42
100.0
TBD
IOL (mA)
Iol (mA)
46
40
38
80.0
TBD
60.0
40.0
36
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
5.5
6.0
20.0
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
30
ATF1504SE(L)
2401D–PLD–09/02
ATF1504SE(L)
INPUT CLAMP CURRENT VS.
INPUT VOLTAGE (V CC = 5.0V, TA = 35°C)
40
INPUT CURRENT
(uA)
INPUT CURRENT
(mA)
0
-20
-40
TBD
-60
-80
-100
-120
0.0
-0.2
-0.4
-0.6
INPUT VOLTAGE (V)
INPUT CURRENT VS.
INPUT VOLTAGE (VCC = 5.0V, T A = 25°C)
-0.8
30
20
10
TBD
0
-10
-20
-30
-1.0
0.0
NORMALIZED TPD VS. VCC
NORMALIZED TPD
NORMALIZED TPD
5.0
6.0
NORMALIZED T PD VS. TEMP
1.1
TBD
1.0
0.9
0.8
4.5
4.8
5.0
SUPPLY VOLTAGE (V)
5.3
1.0
TBD
0.9
0.8
-40.0
5.5
NORMALIZED TCO VS. VCC
1.3
0.0
25.0
TEMPERATURE (C)
75.0
NORMALIZED T CO VS. TEMP
1.1
NORMALIZED TCO
NORMALIZED TCO
2.0
3.0
4.0
INPUT VOLTAGE (V)
1.1
1.2
1.2
1.1
TBD
1.0
0.9
4.5
4.8
5.0
SUPPLY VOLTAGE (V)
5.3
1.0
TBD
0.9
0.8
-40.0
0.8
5.5
0.0
25.0
75.0
TEMPERATURE (V)
NORMALIZED TSU VS. VCC
NORMALIZED TSU VS. TEMP
1.2
1.2
NORMALIZED TCO
NORMALIZED TSU
1.0
1.1
TBD
1.0
0.9
0.8
4.5
4.8
5.0
SUPPLY VOLTAGE (V)
5.3
5.5
1.1
1.0
TBD
0.9
0.8
-40.0
0.0
25.0
75.0
TEMPERATURE (C)
31
2401D–PLD–09/02
DELTA TPD VS.
OUTPUT LOADING
8
8.00
7.00
DELTA T CO (ns)
6
DELTA T PD (ns)
DELTA TCO VS.
OUTPUT LOADING
4
TBD
2
0
6.00
5.00
TBD
4.00
3.00
2.00
1.00
-2
0.00
0
50
100
150
200
250
300
50
100
OUTPUT LOADING (PF)
DELTA TCO (ns)
DELTA TPD (ns)
250
300
0.0
-0.1
-0.2
TBD
-0.3
-0.4
-0.1
TBD
-0.2
-0.3
-0.5
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
NUMBER OF OUTPUTS SWITCHING
32
200
DELTA TCO VS. # OF OUTPUT SWITCHING
DELTA TPD VS. # OF OUTPUT SWITCHING
0.0
150
NUMBER OF OUTPUTS LOADING
9.0
10.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
NUMBER OF OUTPUTS SWITCHING
ATF1504SE(L)
2401D–PLD–09/02
ATF1504SE(L)
ATF1504SE(L) Pinouts
44
43
42
41
40
39
38
37
36
35
34
I/O
I/O
I/O
VCC
I/OE2/GCK2
GCLR/I
I/OE1
GCK1/I
GND
GCK3
I/O
44-lead TQFP – Top View
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
ATF1502SE(L)
ATF1504SE(L)
I/O
I/O/TDO
I/O
I/O
VCC
I/O
I/O
I/O/TCK
I/O
GND
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
PD2/I/O
I/O
I/O
I/O
12
13
14
15
16
17
18
19
20
21
22
I/O/TDI
I/O
I/O
GND
PD1/I/O
I/O
TMS/I/O
I/O
VCC
I/O
I/O
ATF1502SE(L)
ATF1504SE(L)
39
38
37
36
35
34
33
32
31
30
29
18
19
20
21
22
23
24
25
26
27
28
7
8
9
10
11
12
13
14
15
16
17
I/O
I/O/TDO
I/O
I/O
VCC
I/O
I/O
I/O/TCK
I/O
GND
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
PD2/I/O
I/O
I/O
I/O
TDI/I/O
I/O
I/O
GND
PD1/I/O
I/O
I/O/TMS
I/O
VCC
I/O
I/O
6
5
4
3
2
1
44
43
42
41
40
I/O
I/O
I/O
VCC
GCK2/OE2/I
GCLR/I
OE1/I
GCK1/I
GND
I/O/GCLK3
I/O
44-lead PLCC – Top View
33
2401D–PLD–09/02
11
10
9
8
7
6
5
4
3
2
1
84
83
82
81
80
79
78
77
76
75
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
VCCINT
INPUT/OE2/GCLK2
INPUT/GCLR
INPUT/OE1
INPUT/GCLK1
GND
I/O/GCLK3
I/O
I/O
VCCIO
I/O
I/O
I/O
84-lead PLCC – Top View
ATF1504SE(L)
ATF1508SE(L)
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
I/O
I/O
GND
I/O/TDO
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O/TCK
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
GND
VCCINT
I/O
I/O/PD2
I/O
GND
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O/PD1
VCCIO
I/O/TDI
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O/TMS
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
GND
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
VCCINT
INPUT/OE2/GCLK2
INPUT/GCLR
INPUT/OE1
INPUT/GCLK1
GND
I/O/GCLK3
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
100-lead TQFP – Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
ATF1508SE(L)
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O
GND
I/O/TDO
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O/TCK
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
GND
VCCINT
I/O
I/O/PD2
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
26
27
28
29
30
31
33
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
I/O/PD1
I/O
VCCIO
I/O/TDI
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O/TMS
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
34
ATF1504SE(L)
2401D–PLD–09/02
ATF1504SE(L)
ATF1504SE(L) Dedicated Pinouts
Dedicated Pin
44-lead
TQFP
44-lead
PLCC
84-lead
PLCC
100-lead
TQFP
INPUT/GCLK1
37
43
83
87
INPUT/GCLR
39
1
1
89
INPUT/OE1
38
44
84
88
INPUT/OE2/GCLK2
40
2
2
90
I/O /GCLK3
35
41
81
85
I/O/PD (1,2)
5, 19
11, 25
20, 46
12, 42
I/O/TDI (JTAG)
1
7
14
4
I/O/TMS (JTAG)
7
13
23
15
I/O/TCK (JTAG)
26
32
62
62
I/O/TDO (JTAG)
32
38
71
73
GNDINT
16, 36
22, 44
42, 82
38, 86
GNDIO
4, 24
10, 30
7, 18, 32,47, 69, 72
11, 26, 43,
59, 74, 95
VCCINT
17, 41
3, 23
3, 43
39, 91
VCCIO
9, 29
15, 35
13, 26, 33,
53, 66, 78
3, 18, 34,
51, 66, 82
-
-
-
1, 2, 5, 7, 22,
24, 27, 28, 49,
50, 53, 55, 70,
72, 77, 78
# of Signal Pins
36
36
68
68
# User I/O Pins
32
32
64
64
N/C
OE (1, 2) Global OE pins
GCLR Global Clear pin
GCLK (1, 2, 3) Global Clock pins
PD (1, 2) Power-down pins
TDI, TMS, TCK, TDO JTAG pins used for boundary-scan testing or in-system programming
GNDINT Ground pins for the internal device logic
GNDIO Ground pins for the I/O pins
VCCINT VCC pins for the internal device logic
VCCIO VCC for the I/O drivers
35
2401D–PLD–09/02
ATF1504SE(L) I/O Pinouts
MC
PLC
44-lead
PLCC
44-lead
TQFP
84-lead
PLCC
100-lead
TQFP
MC
PLC
44-lead
PLCC
44-lead
TQFP
84-lead
PLCC
100-lead
TQFP
1
A
12
6
22
14
33
C
24
18
44
40
2
A
-
-
21
13
34
C
-
-
45
41
3
A/
PD1
11
5
20
12
35
C/
PD2
25
19
46
42
4
A
9
3
18
10
36
C
26
20
48
44
5
A
8
2
17
9
37
C
27
21
49
45
6
A
-
-
16
8
38
C
-
-
50
46
7
A
-
-
15
6
39
C
-
-
51
47
8/
TDI
A
7
1
14
4
40
C
28
22
52
48
9
A
-
-
12
100
41
C
29
23
54
52
10
A
-
-
11
99
42
C
-
-
55
54
11
A
6
44
10
98
43
C
-
-
56
56
12
A
-
-
9
97
44
C
-
-
57
57
13
A
-
-
8
96
45
C
-
-
58
58
14
A
5
43
6
94
46
C
31
25
60
60
15
A
-
-
5
93
47
C
-
-
61
61
C
32
26
62
62
D
33
27
63
63
16
A
4
42
4
92
48/
TCK
17
B
21
15
41
37
49
18
B
-
-
40
36
50
D
-
-
64
64
19
B
20
14
39
35
51
D
34
28
65
65
20
B
19
13
37
33
52
D
36
30
67
67
21
B
18
12
36
32
53
D
37
31
68
68
22
B
-
-
35
31
54
D
-
-
69
69
23
B
-
-
34
30
55
D
-
-
70
71
24
B
17
11
33
29
56/
TDO
D
38
32
71
73
25
B
16
10
31
25
57
D
39
33
73
75
26
B
-
-
30
23
58
D
-
-
74
76
27
B
-
-
29
21
59
D
-
-
75
79
28
B
-
-
28
20
60
D
-
-
76
80
29
B
-
-
27
19
61
D
-
-
77
81
30
B
14
8
25
17
62
D
40
34
79
83
31
B
-
-
24
16
63
D
-
-
80
84
64
D/
GCLK3
41
35
81
85
32/
TMS
36
B
13
7
23
15
ATF1504SE(L)
2401D–PLD–09/02
ATF1504SE(L)
ATF1504SE(L) Ordering Information
tPD
(ns)
tCO1
(ns)
fMAX
(MHz)
5.0
3.2
6.0
7.5
10
15
Ordering Code
Package
250
ATF1504SE-5
ATF1504SE-5
ATF1504SE-5
ATF1504SE-5
AC44
JC44
JC84
AC100
44A
44J
84J
100A
Commercial
(0°C to 70°C)
4.0
200
ATF1504SE-6
ATF1504SE-6
ATF1504SE-6
ATF1504SE-6
AC44
JC44
JC84
AC100
44A
44J
84J
100A
Commercial
(0°C to 70°C)
4.5
167
ATF1504SE-7
ATF1504SE-7
ATF1504SE-7
ATF1504SE-7
AC44
JC44
JC84
AC100
44A
44J
84J
100A
Commercial
(0°C to 70°C)
ATF1504SE-7
ATF1504SE-7
ATF1504SE-7
ATF1504SE-7
AI44
JI44
J84
AI100
44A
44J
84J
100A
Industrial
(-40°C to +85°C)
ATF1504SE-10 AC44
ATF1504SE-10 JC44
ATF1504SE-10 JC84
ATF1504SE-10 AC100
44A
44J
84J
100A
Commercial
(0°C to 70°C)
ATF1504SE-10 AI44
ATF1504SE-10 JI44
ATF1504SE-10 JI84
ATF1504SE-10 AI100
44A
44J
84J
100A
Industrial
(-40°C to +85°C)
ATF1504SEL-15 AC44
ATF1504SEL-15 JC44
ATF1504SEL-15 JC84
ATF1504SEL-15 AC100
44A
44J
84J
100A
Commercial
(0°C to 70°C)
5.0
9.0
125
77
Operation Range
Using “C” Product for Industrial
To use commercial product for industrial temperature ranges, down grade one speed grade from the “I” to the “C” device,
and de-rate power by 30%.
Package Type
44A
44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)
44J
44-lead, Plastic J-leaded Chip Carrier (PLCC)
84J
84-lead, Plastic J-leaded Chip Carrier (PLCC)
100A
100-lead, Very Thin Plastic Gull Wing Quad Flatpack (TQFP)
37
2401D–PLD–09/02
AC Characteristics(1) ATF1508SE(L)
SE -6
Symbol
Parameter
Min
SE -7
Max
Min
Max
SE -10
Min
SEL -15(6)
Max
Min
Max
Unit
tPD1
Input or Feedback to Non-registered Output
6
7.5
10
15
ns
tPD2
I/O Input or Feedback to Non-registered Feedback
6
7.5
10
15
ns
tSU
Global Clock Setup Time
3.4
6.0
7.0
11
ns
tH
Global Clock Hold Time
0.0
0.0
0.0
0.0
ns
tFSU
Global Clock Setup Time of Fast Input
2.5
3.0
3.0
3.0
ns
tFH
Global Clock Hold of Fast Input
0
0.5
0.5
1
ns
tCO1
Global Clock to Output Delay
tCH
Global Clock High Time
3
3.0
4.0
5.0
ns
tCL
Global Clock Low Time
3
3.0
4.0
5.0
ns
tASU
Array Clock Setup Time
0.9
3.0
2.0
4.0
ns
tAH
Array Clock Hold Time
1.8
2.0
5.0
4.0
ns
4.0
4.5
5.0
8.0
ns
tACO1
Array Clock Output Delay
tACH
Array Clock High Time
3.0
3
4.0
6.0
ns
tACL
Array Clock Low Time
3.0
3
4.0
6.0
ns
tCNT
Minimum Clock Global Period
fCNT(3)
Maximum Internal Global Clock Frequency
tACNT
Minimum Array Clock Period
6.5
7.5
6.8
150
10
8.0
125
6.8
15
10
100
8.0
13
77
10
ns
ns
MHz
13
ns
fACNT(4)
Maximum Internal Array Clock Frequency
150
125
100
77
MHz
fMAX(5)
Maximum Clock Frequency
167
167
125
100
MHz
tIN
Input Pad and Buffer Delay
0.2
0.5
0.5
2.0
ns
tIO
I/O Input Pad and Buffer Delay
0.2
0.5
0.5
2.0
ns
tFIN
Fast Input Delay
2.6
1.0
1.0
2.0
ns
tSEXP
Foldback Term Delay
3.7
4.0
5.0
8.0
ns
tPEXP
Cascade Logic Delay
1.1
0.8
0.0
1.0
ns
tLAD
Logic Array Delay
3.0
3.0
5.0
6.0
ns
tLAC
Logic Control Delay
3.0
3.0
5.0
6.0
ns
tIOE
Internal Output Enable Delay
0.7
2.0
2.0
3.0
ns
tOD1
Output Buffer and Pad Delay
(slow slew rate = OFF; VCCIO = 5V; CL= 35 pF)
0.4
2.0
1.5
4.0
ns
tOD2
Output Buffer and Pad Delay
(slow slew rate = OFF; VCCIO = 3.3V; CL= 35 pF)
0.9
2.5
2.0
5.0
ns
tOD3
Output Buffer and Pad Delay
(slow slew rate = ON; VCCIO = 5V or 3.3V;
C L= 35 pF)
5.4
7.0
5.5
8.0
ns
tZX1
Output Buffer Enable Delay
(slow slew rate = OFF; VCCIO = 5V; CL= 35 pF)
4.0
4.0
5
6.0
ns
38
ATF1508SE(L)
2401D–PLD–09/02
ATF1508SE(L)
AC Characteristics(1) ATF1508SE(L) (Continued)
SE -6
Symbol
Parameter
tZX2
Output Buffer Enable Delay
(slow slew rate = OFF; VCCIO = 3.3V; CL= 35 pF)
tZX3
Min
SE -7
Max
Min
SE -10
Max
Min
Max
SEL -15(6)
Min
Max
Unit
4.5
4.5
5.5
7.0
ns
Output Buffer Enable Delay
(slow slew rate = ON; VCCIO = 5V or 3.3V;
C L= 35 pF)
9
9
9
10.0
ns
tXZ
Output Buffer Disable Delay (C L= 5 pF)
4
4
5
6.0
ns
tSU
Register Setup Time
1.0
3.0
2.0
4.0
ns
tH
Register Hold Time
1.7
2.0
5.0
4.0
ns
tFSU
Register Setup Time of Fast Input
1.9
3.0
3.0
2.0
ns
tFH
Register Hold Time of Fast Input
0.6
0.5
0.5
1.0
ns
tRD
Register Delay
1.4
1.0
2.0
1.0
ns
Combinatorial Delay
1.0
1.0
2.0
1.0
ns
tIC
Array Clock Delay
3.1
3.0
5.0
6.0
ns
tEN
Register Enable Time
3.0
3.0
5.0
6.0
ns
tGLOB
Global Control Delay
2.0
1.0
1.0
1.0
ns
tPRE
Register Preset Time
2.4
2.0
3.0
4.0
ns
tCLR
Register Clear Time
2.4
2.0
3.0
4.0
ns
tUIM
Switch Matrix Delay
1.4
1.0
1.0
2.0
ns
tCOMB
tRPA(2)
Reduced Power Adder
10
10
11
13
ns
Notes: 1. See ordering Information for valid part numbers.
2. The tRPA parameter must be added to the tLAD, tLAC, tIC, tACL and tSEXP parameters for macrocells running in the reducedpower mode.
3. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable, and a PIA fan-out of one
logic block (16 macrocells). fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG.
4. fACNT is the fastest 16-bit counter frequency available, using the internal array clock, local feedback when applicable and a
PIA fan-out of one logic block (16 macrocells).
5. fMAX is the fastest available frequency for pipelined data.
6. For clocked applications and frequencies above fCRITICAL, OR, non-clocked applications with dormant times less than 1/fCRITICAL, the device will achieve the speeds of the –10 column. See “Input Transition Detection/ Automatic Power Down” on page
8.
39
2401D–PLD–09/02
STAND-BY ICC VS.
NORMALIZED ICC VS. TEMP
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.4
TBD
4.5
4.8
5.0
1.2
NORMALIZED Icc
ICC (µA)
SUPPLY VOLTAGE (TA = 25°C)
5.3
1.0
TBD
0.8
0.6
0.4
-40.0
5.5
SUPPLY VOLTAGE (V)
0.0
25.0
75.0
TEMPERATURE (C)
SUPPLY CURRENT VS.
INPUT FREQUENCY (VCC = 5.0V, TA = 25°C)
SUPPLY CURRENT VS.
INPUT FREQUENCY (VCC = 5.0V, TA = 25°C)
140.000
1.000
120.000
0.800
ICC (mA)
ICC (mA)
100.000
80.000
TBD
0.600
TBD
0.400
60.000
0.200
40.000
0.000
20.000
0.0
0.5
2.5
5.0
7.5
10.0
25.0
37.5
50.0
FREQUENCY (MHz)
0.000
0.0
0.5
2.5
5.0
7.5
10.0
FREQUENCY (MHz)
25.0
37.5
50.0
OUTPUT SOURCE CURRENT VS.
SUPPLY VOLTAGE (V OH = 2.4V)
0
OUTPUT SOURCE CURRENT VS.
OUTPUT VOLTAGE (VCC = 5.0V, T A = 25°C)
0.0
-10.0
-20.0
-20
IOH (mA)
IOH (mA)
-10
TBD
-30
-40
-30.0
-40.0
TBD
-50.0
-60.0
-70.0
-50
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
5.5
-80.0
6.0
-90.0
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
4.50
5.00
VOH (V)
OUTPUT SINK CURRENT VS.
OUTPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
OUTPUT SINK CURRENT VS.
SUPPLY VOLTAGE (V OL = 0.5V)
48
140.0
120.0
44
100.0
42
IOL (mA)
Iol (mA)
46
TBD
40
38
80.0
TBD
60.0
40.0
36
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
5.5
6.0
20.0
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
40
ATF1508SE(L)
2401D–PLD–09/02
ATF1508SE(L)
INPUT CLAMP CURRENT VS.
INPUT VOLTAGE (V CC = 5.0V, TA = 35°C)
40
INPUT CURRENT
(uA)
INPUT CURRENT
(mA)
0
-20
-40
TBD
-60
-80
-100
-120
0.0
-0.2
-0.4
-0.6
INPUT VOLTAGE (V)
INPUT CURRENT VS.
INPUT VOLTAGE (V CC = 5.0V, TA = 25°C)
-0.8
30
20
10
TBD
0
-10
-20
-30
-1.0
0.0
NORMALIZED TPD VS. VCC
NORMALIZED TPD
NORMALIZED TPD
5.0
6.0
1.1
1.1
TBD
1.0
0.9
0.8
4.5
4.8
5.0
SUPPLY VOLTAGE (V)
5.3
1.0
TBD
0.9
0.8
-40.0
5.5
NORMALIZED TCO VS. VCC
1.3
0.0
25.0
TEMPERATURE (C)
75.0
NORMALIZED TCO VS. TEMP
1.1
NORMALIZED TCO
NORMALIZED TCO
2.0
3.0
4.0
INPUT VOLTAGE (V)
NORMALIZED TPD VS. TEMP
1.2
1.2
1.1
TBD
1.0
0.9
4.5
4.8
5.0
SUPPLY VOLTAGE (V)
5.3
1.0
TBD
0.9
0.8
-40.0
0.8
5.5
0.0
25.0
75.0
TEMPERATURE (V)
NORMALIZED TSU VS. VCC
NORMALIZED TSU VS. TEMP
1.2
1.2
NORMALIZED TCO
NORMALIZED TSU
1.0
1.1
1.0
TBD
0.9
0.8
4.5
4.8
5.0
SUPPLY VOLTAGE (V)
5.3
5.5
1.1
1.0
TBD
0.9
0.8
-40.0
0.0
25.0
75.0
TEMPERATURE (C)
41
2401D–PLD–09/02
DELTA TPD VS.
OUTPUT LOADING
8
8.00
7.00
DELTA T CO (ns)
6
DELTA T PD (ns)
DELTA TCO VS.
OUTPUT LOADING
4
TBD
2
0
6.00
5.00
TBD
4.00
3.00
2.00
1.00
-2
0.00
0
50
100
150
200
250
300
50
100
OUTPUT LOADING (PF)
150
200
250
300
NUMBER OF OUTPUTS LOADING
DELTA TCO VS. # OF OUTPUT SWITCHING
DELTA TPD VS. # OF OUTPUT SWITCHING
DELTA TCO (ns)
DELTA TPD (ns)
0.0
0.0
-0.1
-0.2
TBD
-0.3
TBD
-0.2
-0.4
-0.3
-0.5
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
NUMBER OF OUTPUTS SWITCHING
42
-0.1
9.0
10.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
NUMBER OF OUTPUTS SWITCHING
ATF1508SE(L)
2401D–PLD–09/02
ATF1508SE(L)
ATF1508SE(L) Pinouts
11
10
9
8
7
6
5
4
3
2
1
84
83
82
81
80
79
78
77
76
75
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
VCCINT
INPUT/OE2/GCLK2
INPUT/GCLR
INPUT/OE1
INPUT/GCLK1
GND
I/O/GCLK3
I/O
I/O
VCCIO
I/O
I/O
I/O
84-lead PLCC – Top View
ATF1504SE(L)
ATF1508SE(L)
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
I/O
I/O
GND
I/O/TDO
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O/TCK
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
GND
VCCINT
I/O
I/O/PD2
I/O
GND
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O/PD1
VCCIO
I/O/TDI
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O/TMS
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
GND
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
VCCINT
INPUT/OE2/GCLK2
INPUT/GCLR
INPUT/OE1
INPUT/GCLK1
GND
I/O/GCLK3
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
100-lead TQFP – Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
ATF1508SE(L)
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O
GND
I/O/TDO
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O/TCK
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
GND
VCCINT
I/O
I/O/PD2
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
26
27
28
29
30
31
33
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
I/O/PD1
I/O
VCCIO
I/O/TDI
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O/TMS
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
43
2401D–PLD–09/02
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
I/O
I/O
I/O
GND
I/O
I/O
I/O
VCCINT
INPUT/OE2/GCLK2
INPUT/GCLR
INPUT/OE1
INPUT/GCLK1
GND
I/O/GCLK3
I/O
I/O
VCCIO
I/O
I/O
I/O
100-lead PQFP – Top View
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
NC
NC
I/O
I/O
GND
I/O/TDO
NC
I/O
NC
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O/TCK
I/O
I/O
GND
I/O
I/O
I/O
NC
I/O
NC
I/O
VCCIO
NC
NC
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
GND
VCCINT
I/O
I/O
I/O/PD2
GND
I/O
I/O
I/O
I/O
I/O
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC
NC
I/O
I/O
VCCIO
I/O/TDI
NC
I/O
NC
I/O
I/O
I/O
GND
I/O/PD1
I/O
I/O
I/O/TMS
I/O
I/O
VCCIO
I/O
I/O
I/O
NC
I/O
NC
I/O
GND
NC
NC
141
160
160-lead TQFP – Top View
120
1
101
80
41
44
60
ATF1508SE(L)
20
ATF1508SE(L)
2401D–PLD–09/02
ATF1508SE(L)
ATF1508SE(L) Dedicated Pinouts
Dedicated Pin
84-PLCC JLead
100-pin TQFP
100-pin PQFP
160-lead PQFP
INPUT/GCLK1
83
87
89
139
INPUT/GCLR
1
89
91
141
INPUT/OE1
84
88
90
140
INPUT/OE2/GCK2
2
90
92
142
I/O/GCLK3
81
85
87
137
I/O PD (1,2)
12, 45
1,41
3, 43
63,159
TDI (JTAG)
14
4
6
9
TMS (JTAG)
23
15
17
22
TCK (JTAG)
62
62
64
99
TDO (JTAG)
71
73
75
112
GNDINT
42, 82
38,86
40,88
60,138
GNDIO
7, 19, 32, 47,
59, 72
11, 26, 43, 59,
74, 95
13, 28, 61,
76, 45, 97
17, 42,113, 66, 95,148
VCCINT
3, 43
39, 91
41,93
61,143
VCCIO
13, 26, 38, 53,
66, 78
3, 18, 34, 51,
66, 82
5,20,36,53,68,84
8,26,55,79,104,133
-
-
–
1,2,3,4,5,6,7,34,35,36,
37,38,39,40,44,45,46,
47,74,75,76,77,81,82,
83,84,85,86,87,114,
115,116,117,118,119,
120,124,125,126,127,
154,155,156,157
No Connect
# of Signal pins
68
84
84
100
# of User I/O pins
64
80
80
96
OE (1,2) Global OE pins.
GCLR Global Clear pin.
GCLK (1,2,3) Global Clock pins.
TDI, TMS, TCK, TDO JTAG pins used for In System Programming or Boundary-scan Testing.
GNDINT Ground pins for the internal device logic.
GNDIO Ground pins for the I/O drivers.
VCCINT VCC pins for the internal device logic.
VCCIO VCC pins for the I/O drivers.
45
2401D–PLD–09/02
ATF1508SE(L) I/O Pinouts
46
MC
PLB
84-PLCC
J-lead
100-lead
PQFP
100-lead
TQFP
160-lead
PQFP
MC
PLB
84-PLCC
J-lead
100-lead
PQFP
100-lead
TQFP
160-lead
PQFP
1
A
–
4
2
160
33
C
–
27
25
41
2
A
–
–
–
–
34
C
–
–
–
–
3/PD1
A
12
3
1
159
35
C
31
26
24
33
4
A
–
–
–
158
36
C
–
–
–
32
5
A
11
2
100
153
37
C
30
25
23
31
6
A
10
1
99
152
38
C
29
24
22
30
7
A
–
–
–
–
39
C
–
–
–
–
8
A
9
100
98
151
40
C
28
23
21
29
9
A
–
99
97
150
41
C
–
22
20
28
10
A
–
–
–
–
42
C
–
–
–
–
11
A
8
98
96
149
43
C
27
21
19
27
12
A
–
–
–
147
44
C
–
–
–
25
13
A
6
96
94
146
45
C
25
19
17
24
14
A
5
95
93
145
46
C
24
18
16
23
15
A
–
–
–
–
47
C
–
–
–
–
16
A
4
94
92
144
48/TMS
C
23
17
15
22
17
B
22
16
14
21
49
D
41
39
37
59
18
B
–
–
–
–
50
D
–
–
–
–
19
B
21
15
13
20
51
D
40
38
36
58
20
B
–
–
–
19
52
D
–
–
–
57
21
B
20
14
12
18
53
D
39
37
35
56
22
B
–
12
10
16
54
D
–
35
33
54
23
B
–
–
–
–
55
D
–
–
–
–
24
B
18
11
9
15
56
D
37
34
32
53
25
B
17
10
8
14
57
D
36
33
31
52
26
B
–
–
–
–
58
D
–
–
–
–
27
B
16
9
7
13
59
D
35
32
30
51
28
B
–
–
–
12
60
D
–
–
–
50
29
B
15
8
6
11
61
D
34
31
29
49
30
B
–
7
5
10
62
D
–
30
28
48
31
B
–
–
–
–
63
D
–
–
–
–
32/
TDI
B/
14
6
4
9
64
D
33
29
27
43
ATF1508SE(L)
2401D–PLD–09/02
ATF1508SE(L)
ATF1508SE(L) I/O Pinouts (Continued)
MC
PLB
84-PLCC
J-lead
100-lead
PQFP
100-lead
TQFP
160-lead
PQFP
MC
PLB
84-PLCC
J-lead
100-lead
PQFP
100-lead
TQFP
160-lead
PQFP
65
E
44
42
40
62
97
G
63
65
63
100
66
E
–
–
–
–
98
G
–
–
–
–
45
43
41
63
99
G
64
66
64
101
67/PD2
E
68
E
–
–
–
64
100
G
–
–
–
102
69
E
46
44
42
65
101
G
65
67
65
103
70
E
–
46
44
67
102
G
–
69
67
105
71
E
–
–
–
–
103
G
–
–
–
–
72
E
48
47
45
68
104
G
67
70
68
106
73
E
49
48
46
69
105
G
68
71
69
107
74
E
–
–
–
–
106
G
–
–
–
–
75
E
50
49
47
70
107
G
69
72
70
108
76
E
–
–
–
71
108
G
–
–
–
109
77
E
51
50
48
72
109
G
70
73
71
110
78
E
–
51
49
73
110
G
–
74
72
111
79
E
–
–
–
–
111
G
–
–
–
–
80
E
52
52
50
78
112/TDO
G
71
75
73
112
81
F
–
54
52
80
113
H
–
77
75
121
82
F
–
–
–
–
114
H
–
–
–
–
83
F
54
55
53
88
115
H
73
78
76
122
84
F
–
–
–
89
116
H
–
–
–
123
85
F
55
56
54
90
117
H
74
79
77
128
86
F
56
57
55
91
118
H
75
80
78
129
87
F
–
–
–
–
119
H
–
–
–
–
88
F
57
58
56
92
120
H
76
81
79
130
89
F
–
59
57
93
121
H
–
82
80
131
90
F
–
–
–
–
122
H
–
–
–
–
91
F
58
60
58
94
123
H
77
83
81
132
92
F
–
–
–
96
124
H
–
–
–
134
93
F
60
62
60
97
125
H
79
85
83
135
94
F
61
63
61
98
126
H
80
86
84
136
95
F
–
–
–
–
127
H
–
–
–
–
96
F/
TCK
62
64
62
99
128/GCLK3
H
81
87
85
137
47
2401D–PLD–09/02
ATF1508SE(L) Ordering Information
tPD
(ns)
tCO1
(ns)
fMAX
(MHz)
6.0
4.0
7.5
4.5
10
15
5.0
8.0
Ordering Code
Package
167
ATF1508SE-5
ATF1508SE-5
ATF1508SE-5
ATF1508SE-5
JC84
AC100
QC100
QC160
84J
100A
100Q4
160Q1
Commercial
(0°C to 70°C)
167
ATF1508SE-7
ATF1508SE-7
ATF1508SE-7
ATF1508SE-7
JC84
AC100
QC100
QC160
84J
100A
100Q4
160Q1
Commercial
(0°C to 70°C)
ATF1508SE-7
ATF1508SE-7
ATF1508SE-7
ATF1508SE-7
JI84
AI100
QI100
QI160
84J
100A
100Q4
160Q1
Industrial
(-40°C to +85°C)
ATF1508SE-10 JC84
ATF1508SE-10 AC100
ATF1508SE-10 QC100
ATF1508SE-10 QC160
84J
100A
100Q4
160Q1
Commercial
(0°C to 70°C)
ATF1508SE-10 JI84
ATF1508SE-10 AI100
ATF1508SE-10 QI100
ATF1508SE-10 QI160
84J
100A
100Q4
160Q1
Industrial
(-40°C to +85°C)
ATF1508SEL-15 JC84
ATF1508SEL-15 AC100
ATF1508SEL-15 QC100
ATF1508SEL-15 QC160
84J
100A
100Q4
160Q1
Commercial
(0°C to 70°C)
125
100
Operation Range
Using “C” Product for Industrial
To use commercial product for industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device
and de-rate power by 30%.
Package Type
84J
84-lead, Plastic J-leaded Chip Carrier (PLCC)
100A
100-lead, Very Thin Plastic Gull Wing Quad Flatpack (TQFP)
100Q4
100-lead, Plastic Quad Pin Flat Package (PQFP)
160Q1
160-lead, Plastic Quad Pin Flat Package (PQFP)
48
ATF1508SE(L)
2401D–PLD–09/02
ATF1516SE(L)
AC Characteristics(1) ATF1516SE(L)
SE -7
Symbol
Parameter
Min
SEL -15(6)
SE -10
Max
Min
Max
Min
Max
Unit
tPD1
Input or Feedback to Non-registered Output
7.5
10
15
ns
tPD2
I/O Input or Feedback to Non-registered Feedback
7.5
10
12
ns
tSU
Global Clock Setup Time
3.9
7.0
11
ns
tH
Global Clock Hold Time
0.0
0.0
0.0
ns
tFSU
Global Clock Setup Time of Fast Input
3.9
3.0
3.0
ns
tFH
Global Clock Hold of Fast Input
0.0
0.5
1
ns
tCO1
Global Clock to Output Delay
tCH
Global Clock High Time
3.0
4.0
5.0
ns
tCL
Global Clock Low Time
3.0
4.0
5
ns
tASU
Array Clock Setup Time
0.8
2.0
4.0
ns
tAH
Array Clock Hold Time
1.9
3.0
4.0
ns
4.7
5.0
8.0
ns
tACO1
Array Clock Output Delay
tACH
Array Clock High Time
3.0
4
6
ns
tACL
Array Clock Low Time
3.0
4
6
ns
tCNT
Minimum Clock Global Period
fCNT(3)
Maximum Internal Global Clock Frequency
tACNT
Minimum Array Clock Period
7.3
1
7.8
130
10
15
10
100
7.8
13
77
10
ns
ns
MHz
13
ns
fACNT(4)
Maximum Internal Array Clock Frequency
130
100
77
MHz
fMAX(5)
Maximum Clock Frequency
167
125
100
MHz
tIN
Input Pad and Buffer Delay
0.3
0.5
2.0
ns
tIO
I/O Input Pad and Buffer Delay
0.3
0.5
2.0
ns
tFIN
Fast Input Delay
3.4
1.0
2.0
ns
tSEXP
Foldback Term Delay
3.9
5.0
8.0
ns
tPEXP
Cascade Logic Delay
1.1
0.8
1.0
ns
tLAD
Logic Array Delay
2.6
5.0
6.0
ns
tLAC
Logic Control Delay
2.6
5.0
6.0
ns
tIOE
Internal Output Enable Delay
0.8
2.0
3.0
ns
tOD1
Output Buffer and Pad Delay
(slow slew rate = OFF; VCCIO = 5V; CL= 35 pF)
0.5
1.5
4.0
ns
tOD2
Output Buffer and Pad Delay
(slow slew rate = OFF; VCCIO = 3.3V; CL= 35 pF)
1.0
2.0
5.0
ns
tOD3
Output Buffer and Pad Delay
(slow slew rate = ON; VCCIO = 5V or 3.3V;
C L= 35 pF)
5.5
5.5
8.0
ns
tZX1
Output Buffer Enable Delay
(slow slew rate = OFF; VCCIO = 5V; CL= 35 pF)
4.0
5.0
6.0
ns
49
2401D–PLD–09/02
AC Characteristics(1) ATF1516SE(L) (Continued)
SE -7
Symbol
Parameter
Min
SEL -15(6)
SE -10
Max
Min
Max
Min
Max
Unit
tZX2
Output Buffer Enable Delay
(slow slew rate = OFF; VCCIO = 3.3V; CL= 35 pF)
4.5
5.5
7.0
ns
tZX3
Output Buffer Enable Delay
(slow slew rate = ON; VCCIO = 5V or 3.3V; CL= 35
pF)
9.0
9.0
10.0
ns
tXZ
Output Buffer Disable Delay (C L= 5 pF)
4.0
5.0
6.0
ns
tSU
Register Setup Time
1.1
2.0
4.0
ns
tH
Register Hold Time
1.6
3.0
4.0
ns
tFSU
Register Setup Time of Fast Input
2.4
3.0
2.0
ns
tFH
Register Hold Time of Fast Input
0.6
0.5
1.0
ns
tRD
Register Delay
1.1
2.0
1.0
ns
Combinatorial Delay
1.1
2.0
1.0
ns
tIC
Array Clock Delay
2.9
5.0
6.0
ns
tEN
Register Enable Time
2.6
5.0
6.0
ns
tGLOB
Global Control Delay
2.8
1.0
1.0
ns
tPRE
Register Preset Time
2.7
3.0
4.0
ns
tCLR
Register Clear Time
2.7
3.0
4.0
ns
tUIM
Switch Matrix Delay
3.0
1.0
2.0
ns
tCOMB
(2)
tRPA
Reduced Power Adder
10
11
13
ns
Notes: 1. See ordering Information for valid part numbers.
2. The tRPA parameter must be added to the tLAD, tLAC, tIC, tACL and tSEXP parameters for macrocells running in the reducedpower mode.
3. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable, and a PIA fan-out of one
logic block (16 macrocells). fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG.
4. fACNT is the fastest 16-bit counter frequency available, using the internal array clock, local feedback when applicable and a
PIA fan-out of one logic block (16 macrocells).
5. fMAX is the fastest available frequency for pipelined data.
6. For clocked applications and frequencies above fCRITICAL, OR, non-clocked applications with dormant times less than 1/fCRITICAL, the device will achieve the speeds of the –10 column. See “Input Transition Detection/ Automatic Power Down” on page
8.
50
ATF1516SE(L)
2401D–PLD–09/02
ATF1516SE(L)
STAND-BY ICC VS.
NORMALIZED ICC VS. TEMP
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.4
TBD
4.5
4.8
5.0
1.2
NORMALIZED Icc
ICC (µA)
SUPPLY VOLTAGE (TA = 25°C)
5.3
1.0
TBD
0.8
0.6
0.4
-40.0
5.5
SUPPLY VOLTAGE (V)
25.0
75.0
TEMPERATURE (C)
SUPPLY CURRENT VS.
INPUT FREQUENCY (VCC = 5.0V, TA = 25°C)
SUPPLY CURRENT VS.
INPUT FREQUENCY (V CC = 5.0V, TA = 25°C)
1.000
120.000
0.800
ICC (mA)
140.000
100.000
ICC (mA)
0.0
80.000
0.600
TBD
0.400
TBD
0.200
60.000
0.000
40.000
0.0
0.5
2.5
5.0
20.000
7.5
10.0
25.0
37.5
50.0
FREQUENCY (MHz)
0.000
0.0
0.5
2.5
5.0
7.5
10.0
FREQUENCY (MHz)
25.0
37.5
50.0
OUTPUT SOURCE CURRENT VS.
SUPPLY VOLTAGE (V OH = 2.4V)
0
0.0
-10.0
-10
-20.0
-20
TBD
-30
IOH (mA)
IOH (mA)
OUTPUT SOURCE CURRENT VS.
OUTPUT VOLTAGE (VCC = 5.0V, T A = 25°C)
-40
-50
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
5.5
-30.0
-40.0
TBD
-50.0
-60.0
-70.0
6.0
-80.0
-90.0
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
4.50
5.00
VOH (V)
OUTPUT SINK CURRENT VS.
SUPPLY VOLTAGE (V OL = 0.5V)
48
OUTPUT SINK CURRENT VS.
OUTPUT VOLTAGE (V CC = 5.0V, TA = 25°C)
140.0
120.0
44
42
100.0
TBD
IOL (mA)
Iol (mA)
46
40
38
80.0
TBD
60.0
40.0
36
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
5.5
6.0
20.0
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
51
2401D–PLD–09/02
INPUT CLAMP CURRENT VS.
INPUT VOLTAGE (VCC = 5.0V, T A = 35°C)
40
INPUT CURRENT
(uA)
INPUT CURRENT
(mA)
0
-20
-40
TBD
-60
-80
-100
-120
0.0
-0.2
-0.4
-0.6
INPUT VOLTAGE (V)
INPUT CURRENT VS.
INPUT VOLTAGE (VCC = 5.0V, T A = 25°C)
-0.8
30
20
10
TBD
0
-10
-20
-30
-1.0
0.0
NORMALIZED TPD VS. VCC
NORMALIZED TPD
NORMALIZED TPD
1.1
TBD
1.0
0.9
4.5
5.0
SUPPLY VOLTAGE (V)
5.3
6.0
1.0
TBD
0.9
0.8
-40.0
5.5
NORMALIZED TCO VS. VCC
0.0
25.0
TEMPERATURE (C)
75.0
NORMALIZED T CO VS. TEMP
1.1
NORMALIZED TCO
NORMALIZED TCO
4.8
1.2
1.1
TBD
1.0
0.9
4.5
4.8
5.0
SUPPLY VOLTAGE (V)
5.3
1.0
TBD
0.9
0.8
-40.0
0.8
5.5
0.0
25.0
75.0
TEMPERATURE (V)
NORMALIZED TSU VS. VCC
NORMALIZED TSU VS. TEMP
1.2
1.2
NORMALIZED TCO
NORMALIZED TSU
5.0
1.1
0.8
1.1
1.0
TBD
0.9
0.8
4.5
52
2.0
3.0
4.0
INPUT VOLTAGE (V)
NORMALIZED T PD VS. TEMP
1.2
1.3
1.0
4.8
5.0
SUPPLY VOLTAGE (V)
5.3
5.5
1.1
1.0
TBD
0.9
0.8
-40.0
0.0
25.0
75.0
TEMPERATURE (C)
ATF1516SE(L)
2401D–PLD–09/02
ATF1516SE(L)
DELTA TPD VS.
OUTPUT LOADING
8
8.00
7.00
DELTA T CO (ns)
6
DELTA T PD (ns)
DELTA TCO VS.
OUTPUT LOADING
4
TBD
2
0
6.00
5.00
TBD
4.00
3.00
2.00
1.00
-2
0.00
0
50
100
150
200
250
300
50
100
OUTPUT LOADING (PF)
150
200
250
300
NUMBER OF OUTPUTS LOADING
DELTA TCO VS. # OF OUTPUT SWITCHING
DELTA TPD VS. # OF OUTPUT SWITCHING
DELTA TCO (ns)
DELTA TPD (ns)
0.0
0.0
-0.1
-0.2
TBD
-0.3
-0.1
TBD
-0.2
-0.4
-0.3
-0.5
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
NUMBER OF OUTPUTS SWITCHING
9.0
10.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
NUMBER OF OUTPUTS SWITCHING
53
2401D–PLD–09/02
ATF1516SE(L) Dedicated Pinouts
183
131
104
53
54
156
ATF1516SE(L)
26
78
1
208
208-lead PQFP and RQFP – Top View
ATF1516SE(L)
2401D–PLD–09/02
ATF1516SE(L)
ATF1516SE(L) Dedicated Pinouts
Dedicated Pin
208-pin PQFP
208-pin RQFP
INPUT/GCLK1
184
184
INPUT/GCLR
182
182
INPUT/OE1
183
183
INPUT/OE2/GCK2
181
181
I/O/GCLK3
TBD
TBD
I/O PD (1,2)
TBD
TBD
TDI (JTAG)
176
176
TMS (JTAG)
127
127
TCK (JTAG)
30
30
TDO (JTAG)
189
189
GNDINT
75, 82, 180, 185
75, 82, 180, 185
GNDIO
14, 32, 50, 72, 94, 116, 134, 152, 174,
200
14, 32, 50, 72, 94, 116, 134, 152, 174,
200
VCCINT
74, 83, 179, 186
74, 83, 179, 186
VCCIO
5, 23, 41, 63, 85, 107, 125, 143, 165, 191
5, 23, 41, 63, 85, 107, 125, 143, 165, 191
1,2, 51, 52, 53, 54, 103, 104, 105, 106,
155, 156, 157, 158, 207, 208
1,2, 51, 52, 53, 54, 103, 104, 105, 106,
155, 156, 157, 158, 207, 208
# of Signal pins
164
164
# of User I/O pins
160
160
No Connect
OE (1,2) Global OE pins.
GCLR Global Clear pin.
GCLK (1,2,3) Global Clock pins.
TDI, TMS, TCK, TDO JTAG pins used for In System Programming or Boundary-scan Testing.
GNDINT Ground pins for the internal device logic.
GNDIO Ground pins for the I/O drivers.
VCCINT VCC pins for the internal device logic.
VCCIO VCC pins for the I/O drivers.
55
2401D–PLD–09/02
ATF1516SE(L) I/O Pinouts
56
MC
PLB
208-pin PQFP
208-pin RQRP
MC
PLB
208-pin PQFP
208-pin RQFP
1
A
153
153
33
C
108
108
2
A
-
-
34
C
-
-
3
A
154
154
35
C
109
109
4
A
-
-
36
C
-
-
5
A
159
159
37
C
110
110
6
A
160
160
38
C
111
111
7
A
-
-
39
C
-
-
8
A
161
161
40
C
112
112
9
A
162
162
41
C
113
113
10
A
-
-
42
C
-
-
11
A
163
163
43
C
114
114
12
A
-
-
44
C
-
-
13
A
164
164
45
C
115
115
14
A
166
166
46
C
117
117
15
A
-
-
47
C
-
-
16
A
167
167
48
C
118
118
17
B
141
141
49
D
92
92
18
B
-
-
50
D
-
-
19
B
142
142
51
D
93
93
20
B
-
-
52
D
-
-
21
B
144
144
53
D
95
95
22
B
145
145
54
D
96
96
23
B
-
-
55
D
-
-
24
B
146
146
56
D
97
97
25
B
147
147
57
D
98
98
26
B
-
-
58
D
-
-
27
B
148
148
59
D
99
99
28
B
-
-
60
D
-
-
29
B
149
149
61
D
100
100
30
B
150
150
62
D
101
101
31
B
-
-
63
D
-
-
32
B
151
151
64
D
102
102
ATF1516SE(L)
2401D–PLD–09/02
ATF1516SE(L)
ATF1516SE(L) I/O Pinouts (Continued)
MC
PLB
208-pin PQFP
208-pin RQRP
MC
PLB
208-pin PQFP
208-pin RQFP
65
E
168
168
97
G
119
119
66
E
-
-
98
G
-
-
67
E
169
169
99
G
120
120
68
E
-
-
100
G
-
-
69
E
170
170
101
G
121
121
70
E
171
171
102
G
122
122
71
E
-
-
103
G
-
-
72
E
172
172
104
G
123
123
73
E
173
173
105
G
124
124
74
E
-
-
106
G
-
-
75
E
175
175
107
G
126
126
76
E
-
-
108
G
-
-
77
E
176
176
109
G
127
127
78
E
177
177
110
G
128
128
79
E
-
-
111
G
-
-
80
E
178
178
112
G
129
129
81
F
130
130
113
H
79
79
82
F
-
-
114
H
-
-
83
F
131
131
115
H
80
80
84
F
-
-
116
H
-
-
85
F
132
132
117
H
81
81
86
F
133
133
118
H
84
84
87
F
-
-
119
H
-
-
88
F
135
135
120
H
86
86
89
F
136
136
121
H
87
87
90
F
-
-
122
H
-
-
91
F
137
137
123
H
88
88
92
F
-
-
124
H
-
-
93
F
138
138
125
H
89
89
94
F
139
139
126
H
90
90
95
F
-
-
127
H
-
-
96
F
140
140
128
H
91
91
57
2401D–PLD–09/02
ATF1516SE(L) I/O Pinouts (Continued)
58
MC
PLB
208-pin PQFP
208-pin RQRP
MC
PLB
208-pin PQFP
208-pin RQFP
129
I
197
197
161
K
38
38
130
I
-
-
162
K
-
-
131
I
196
196
163
K
37
37
132
I
-
-
164
K
-
-
133
I
195
195
165
K
36
36
134
I
194
194
166
K
35
35
135
I
-
-
167
K
-
-
136
I
193
193
168
K
34
34
137
I
192
192
169
K
33
33
138
I
-
-
170
K
-
-
139
I
190
190
171
K
31
31
140
I
-
-
172
K
-
-
141
I
189
189
173
K
30
30
142
I
188
188
174
K
29
29
143
I
-
-
175
K
-
-
144
I
187
187
176
K
28
28
145
J
27
27
177
L
78
78
146
J
-
-
178
L
-
-
147
J
26
26
179
L
77
77
148
J
-
-
180
L
-
-
149
J
25
25
181
L
76
76
150
J
24
24
182
L
73
73
151
J
-
-
183
L
-
-
152
J
22
22
184
L
71
71
153
J
21
21
185
L
70
70
154
J
-
-
186
L
-
-
155
J
20
20
187
L
69
69
156
J
-
-
188
L
-
-
157
J
19
19
189
L
68
68
158
J
18
18
190
L
67
67
159
J
-
-
191
L
-
-
160
J
17
17
192
L
66
66
ATF1516SE(L)
2401D–PLD–09/02
ATF1516SE(L)
ATF1516SE(L) I/O Pinouts (Continued)
MC
PLB
208-pin PQFP
208-pin RQRP
MC
PLB
208-pin PQFP
208-pin RQFP
193
M
4
4
225
O
49
49
194
M
-
-
226
O
-
-
195
M
3
3
227
O
48
48
196
M
-
-
228
O
-
-
197
M
206
206
229
O
47
47
198
M
205
205
230
O
46
46
199
M
-
-
231
O
-
-
200
M
204
204
232
O
45
45
201
M
203
203
233
O
44
44
202
M
-
-
234
O
-
-
203
M
202
202
235
O
43
43
204
M
-
-
236
O
-
-
205
M
201
201
237
O
42
42
206
M
199
199
238
O
40
40
207
M
-
-
239
O
-
-
208
M
198
198
240
O
39
39
209
N
16
16
241
P
65
65
210
N
-
-
242
P
-
-
211
N
15
15
243
P
64
64
212
N
-
-
244
P
-
-
213
N
13
13
245
P
62
62
214
N
12
12
246
P
61
61
215
N
-
-
247
P
-
-
216
N
11
11
248
P
60
60
217
N
10
10
249
P
59
59
218
N
-
-
250
P
-
-
219
N
9
9
251
P
58
58
220
N
-
-
252
P
-
-
221
N
8
8
253
P
57
57
222
N
7
7
254
P
56
56
223
N
-
-
255
P
-
-
224
N
6
6
256
P
55
55
59
2401D–PLD–09/02
ATF1516SE(L) Ordering Information
tPD
(ns)
tCO1
(ns)
fMAX
(MHz)
7.5
4.7
167
10
15
5.0
8.0
125
100
Ordering Code
Package
Operation Range
ATF1516SE-7 QC208
ATF1516SE-7 RC208
208Q1
208Q2
Commercial
(0°C to 70°C)
ATF1516SE-7 QI208
ATF1516SE-7 RI208
208Q1
208Q2
Industrial
(-40°C to +85°C)
ATF1516SE-10 QC208
ATF1516SE-10 RC208
208Q1
208Q2
Commercial
(0°C to 70°C)
ATF1516SE-10 QI208
ATF1516SE-10 RI208
208Q1
208Q2
Industrial
(-40°C to +85°C)
ATF1516SEL-15 QC208
ATF1516SEL-15 RC208
208Q1
208Q2
Commercial
(0°C to 70°C)
Using “C” Product for Industrial
To use commercial product for industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device,
and de-rate power by 30%.
Package Type
208Q1
208-lead, 28 x 28 mm Body, 2.6 Form Opt., Plastic Quad Flatpack (PQFP)
208Q2
208-lead, 28 x 28 mm Body, 2.6 Form Opt., Plastic Quad Flatpack with Heat Spreader (PQFP)
60
ATF1516SE(L)
2401D–PLD–09/02
ATF1516SE(L)
Package Information
44A – TQFP
PIN 1
B
PIN 1 IDENTIFIER
E1
e
E
D1
D
C
0˚~7˚
A1
A2
A
L
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10 mm maximum.
SYMBOL
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
11.75
12.00
12.25
D1
9.90
10.00
10.10
E
11.75
12.00
12.25
E1
9.90
10.00
10.10
B
0.30
–
0.45
C
0.09
–
0.20
L
0.45
–
0.75
e
NOTE
Note 2
Note 2
0.80 TYP
10/5/2001
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
DRAWING NO.
REV.
44A
B
61
2401D–PLD–09/02
44J – PLCC
1.14(0.045) X 45°
PIN NO. 1
1.14(0.045) X 45°
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
E1
D2/E2
B1
E
B
e
A2
D1
A1
D
A
0.51(0.020)MAX
45° MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AC.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
SYMBOL
MIN
NOM
MAX
A
4.191
–
4.572
A1
2.286
–
3.048
A2
0.508
–
–
D
17.399
–
17.653
D1
16.510
–
16.662
E
17.399
–
17.653
E1
16.510
–
16.662
D2/E2
14.986
–
16.002
B
0.660
–
0.813
B1
0.330
–
0.533
e
NOTE
Note 2
Note 2
1.270 TYP
10/04/01
R
62
2325 Orchard Parkway
San Jose, CA 95131
TITLE
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO.
REV.
44J
B
ATF1516SE(L)
2401D–PLD–09/02
ATF1516SE(L)
84J – PLCC
1.14(0.045) X 45°
PIN NO. 1
1.14(0.045) X 45°
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
E1
D2/E2
B1
E
B
e
A2
D1
A1
D
A
0.51(0.020)MAX
45° MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AF.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
SYMBOL
MIN
NOM
MAX
A
4.191
–
4.572
A1
2.286
–
3.048
A2
0.508
–
–
D
30.099
–
30.353
D1
29.210
–
29.413
E
30.099
–
30.353
E1
29.210
–
29.413
D2/E2
27.686
–
28.702
B
0.660
–
0.813
B1
0.330
–
0.533
e
NOTE
Note 2
Note 2
1.270 TYP
10/04/01
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
84J, 84-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO.
REV.
84J
B
63
2401D–PLD–09/02
100A – TQFP
PIN 1
B
PIN 1 IDENTIFIER
E1
e
E
D1
D
C
0˚~7˚
A1
A2
A
L
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-026, Variation AED.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.08 mm maximum.
SYMBOL
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
15.75
16.00
16.25
D1
13.90
14.00
14.10
E
15.75
16.00
16.25
E1
13.90
14.00
14.10
B
0.17
–
0.27
C
0.09
–
0.20
L
0.45
–
0.75
e
NOTE
Note 2
Note 2
0.50 TYP
10/5/2001
R
64
2325 Orchard Parkway
San Jose, CA 95131
TITLE
100A, 100-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,
0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
DRAWING NO.
100A
REV.
C
ATF1516SE(L)
2401D–PLD–09/02
ATF1516SE(L)
100Q4 – PQFP
D1
D
E
E1
Top View
Bottom View
A2
A1
e
b
L1
COMMON DIMENSIONS
(Unit of Measure = mm)
Side View
SYMBOL
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing
MS-022, Variation GC-1, for additional information.
2. To be determined at seating plane.
3. Regardless of the relative size of the upper and lower body sections,
dimensions D1 and E1 are determined at the largest feature of the body
exclusive of mold Flash and gate burrs, but including any mismatch
between the upper and lower sections of the molded body.
4. Dimension b does not include Dambar protrusion. The Dambar
protrusion(s) shall not cause the lead width to exceed b maximum by more
than 0.08 mm. Dambar cannot be located on the lower radius or the lead
foot.
5. A1 is defined as the distance from the seating plane to the lowest
point of the package body.
MIN
NOM
MAX
NOTE
5
A1
0.25
–
0.50
A2
2.50
2.70
2.90
D
23.20 BSC
2
D1
20.00 BSC
3
E
17.20 BSC
2
E1
14.00 BSC
3
e
b
0.65 BSC
0.22
L1
0.40
4
1.60 REF
3/29/02
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
100Q4, 100-lead, 14 x 20 mm Body, 3.2 Form Opt.,
Plastic Quad Flat Pack (PQFP)
DRAWING NO.
100Q4
REV.
A
65
2401D–PLD–09/02
160Q1 – PQFP
D1
D
E
E1
Top View
Bottom View
A2
A1
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
L1
SYMBOL
Side View
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing
MS-022, Variation DD-1, for additional information.
2. To be determined at seating plane.
3. Regardless of the relative size of the upper and lower body sections,
dimensions D1 and E1 are determined at the largest feature of the body
exclusive of mold Flash and gate burrs, but including any mismatch
between the upper and lower sections of the molded body.
4. Dimension b does not include Dambar protrusion. The Dambar
protrusion(s) shall not cause the lead width to exceed b maximum by more
than 0.08 mm. Dambar cannot be located on the lower radius or the lead
foot.
5. A1 is defined as the distance from the seating plane to the lowest point of
the package body.
MIN
NOM
MAX
A1
0.25
–
0.50
A2
3.20
3.40
3.60
D
31.20 BSC
NOTE
5
2
D1
28.00 BSC
3
E
31.20 BSC
2
E1
28.00 BSC
3
e
0.65 BSC
b
0.22
L1
–
0.40
4
1.60 REF
3/28/02
R
66
2325 Orchard Parkway
San Jose, CA 95131
TITLE
160Q1, 160-lead, 28 x 28 mm Body, 3.2 Form Opt.,
Plastic Quad Flat Pack (PQFP)
DRAWING NO.
160Q1
REV.
A
ATF1516SE(L)
2401D–PLD–09/02
ATF1516SE(L)
208Q1 – PQFP
D1
A2
L1
A1
Side View
E1
e
b
Top View
D
COMMON DIMENSIONS
(Unit of Measure = mm)
E
SYMBOL
MIN
NOM
MAX
A1
0.25
–
0.50
A2
3.20
3.40
3.60
D
30.60 BSC
D1
28.00 BSC
E
30.60 BSC
E1
28.00 BSC
e
b
NOTE
2, 3
2, 3
0.50 BSC
0.17
L1
–
0.27
4
1.30 REF
Bottom View
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-129, Variation FA-1, for proper dimensions, tolerances, datums, etc.
2. The top package body size may be smaller than the bottom package size by as much as 0.15 mm.
3. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 are maximum plastic
body size dimensions including mold mismatch.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall not cause the lead width to exceed the maximum b
dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion
and an adjacent lead is 0.07 mm.
07/23/02
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
208Q1, 208-lead (28 x 28 mm Body, 2.6 Form Opt.),
Plastic Quad Flat Pack (PQFP)
DRAWING NO.
208Q1
REV.
B
67
2401D–PLD–09/02
208Q2 – PQFP
D1
A2
L1
A1
Side View
E1
e
b
Top View
D
COMMON DIMENSIONS
(Unit of Measure = mm)
E
SYMBOL
MIN
NOM
MAX
A1
0.05
–
0.25
A2
3.20
3.40
3.60
D
30.60 BSC
D1
28.00 BSC
E
30.60 BSC
E1
28.00 BSC
e
b
NOTE
2, 3
2, 3
0.50 BSC
0.17
L1
–
0.27
4
1.30 REF
Bottom View
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-129, Variation FA-2, for proper dimensions, tolerances, datums, etc.
2. The top package body size may be smaller than the bottom package size by as much as 0.15 mm.
3. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 are maximum plastic
body size dimensions including mold mismatch.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall not cause the lead width to exceed the maximum b
dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion
and an adjacent lead is 0.07 mm.
07/23/02
R
68
2325 Orchard Parkway
San Jose, CA 95131
TITLE
208Q2, 208-lead (28 x 28 mm Body, 2.6 Form Opt.),
Plastic Quad Flat Pack (PQFP)
DRAWING NO.
208Q2
REV.
A
ATF1516SE(L)
2401D–PLD–09/02
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© Atmel Corporation 2002.
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2401D–PLD–09/02
xM