W27E257 32K × 8 ELECTRICALLY ERASABLE EPROM GENERAL DESCRIPTION The W27E257 is a high-speed, low-power Electrically Erasable and Programmable Read Only Memory organized as 32768 × 8 bits that operates on a single 5 volt power supply. The W27E257 provides an electrical chip erase function. This part was the same EPROM Writer's utilities as the W27E256. FEATURES • High speed access time: • • • • 100/120/150 nS (max.) Read operating current: 15 mA (typ.) Erase/Programming operating current 1 mA (typ.) Standby current: 5 µA (typ.) Single 5V power supply PIN CONFIGURATIONS • +14V erase/+12V programming voltage • Fully static operation • All inputs and outputs directly TTL/CMOS compatible • Three-state outputs • Available packages: 28-pin 600 mil DIP and 32-pin PLCC BLOCK DIAGRAM VPP 1 28 VCC A12 2 27 A14 A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 A3 7 A2 8 A1 9 20 A0 10 19 CE Q7 Q0 11 18 Q6 VCC Q1 12 17 Q5 Q2 13 16 Q4 GND VPP GND 14 15 Q3 28-pin DIP 23 A11 22 OE A10 21 CE A6 A5 A4 A3 A2 A1 A0 NC Q0 5 6 7 8 9 10 11 12 1 13 4 1 3 2 3 1 32-pin PLCC 1 5 1 6 1 1 7 8 Q Q G N 1 2 N C D 1 9 3 0 29 28 27 26 25 24 23 22 2 0 21 OUTPUT BUFFER OE Q0 . . Q7 A0 . . DECODER CORE ARRAY A14 PIN DESCRIPTION A V V A A A 1 P N C 1 1 7 2 P C C 4 3 4 3 2 CONTROL SYMBOL A0−A14 Q0−Q7 A8 A9 A11 NC OE A10 CE Q7 Q6 CE OE VPP VCC GND NC Q Q Q 3 4 5 -1- DESCRIPTION Address Inputs Data Inputs/Outputs Chip Enable Output Enable Program/Erase Supply Voltage Power Supply Ground No Connection Publication Release Date: January 1997 Revision A3 W27E257 FUNCTIONAL DESCRIPTION Read Mode Like conventional UVEPROMs, the W27E257 has two control functions, both of which produce data at the outputs. CE is for power control and chip select. OE controls the output buffer to gate data to the output pins. When addresses are stable, the address access time (TACC) is equal to the delay from CE to output (TCE), and data are available at the outputs TOE after the falling edge of OE, if TACC and TCE timings are met. Erase Mode The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs, which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an hour), the W27E257 uses electrical erasure. Generally, the chip can be erased within 100 mS by using an EPROM writer with a special erase algorithm. Erase mode is entered when VPP is raised to VPE (14V), VCC = VCE (5V), OE = VIH (2V or above but lower than VCC), A9 = VHH (14V), A0 = VIL (0.8V or below but higher than GND), and all other address pins equal VIL and data input pins equal VIH. Pulsing CE low starts the erase operation. Erase Verify Mode After an erase operation, all of the bytes in the chip must be verified to check whether they have been successfully erased to "1" or not. The erase verify mode automatically ensures a substantial erase margin. This mode will be entered after the erase operation if VPP = VPE (14V), CE = VIH, and OE = VIL. Program Mode Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only way to change cell data from "1" to "0." The program mode is entered when VPP is raised to VPP (12V), VCC = VCP (5V), OE = VIH, the address pins equal the desired address, and the input pins equal the desired inputs. Pulsing CE low starts the programming operation. Program Verify Mode All of the bytes in the chip must be verified to check whether or not they have been successfully programmed with the desired data. Hence, after each byte is programmed, a program verify operation should be performed. The program verify mode automatically ensures a substantial program margin. This mode will be entered after the program operation if VPP = VPP (12V), CE = VIH, and OE = VIL. Erase/Program Inhibit Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different data. When CE = VIH, erasing or programming of non-target chips is inhibited, so that except for the CE and OE pins, the W27E257 may have common inputs. -2- W27E257 Standby Mode The standby mode significantly reduces VCC current. This mode is entered when CE = VIH. In standby mode, all outputs are in a high impedance state, independent of OE. Two-line Output Control Since EPROMs are often used in large memory arrays, the W27E257 provides two control inputs for multiple memory connections. Two-line control provides for lowest possible memory power dissipation and ensures that data bus contention will not occur. System Considerations EPROM power switching characteristics require careful device decoupling. System designers are interested in three supply current issues: standby current levels (ISB), active current levels (ICC), and transient current peaks produced by the falling and rising edges of CE. Transient current magnitudes depend on the device output's capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 µ F ceramic capacitor connected between its VCC and GND. This high frequency, low inherentinductance capacitor should be placed as close as possible to the device. Additionally, for every eight devices, a 4.7 µF electrolytic capacitor should be placed at the array's power supply connection between VCC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductances. TABLE OF OPERATING MODES (VPP = 12V, VPE = 14V, VHH = 12V, VCP = 5V, X = VIH or VIL) MODE PINS CE OE A0 A9 VCC VPP Read VIL VIL X X VCC VCC DOUT Output Disable VIL VIH X X VCC VCC High Z Standby (TTL) VIH X X X VCC VCC High Z VCC ±0.3V X X X VCC VCC High Z Program VIL VIH X X VCP VPP DIN Program Verify VIH VIL X X VCP VPP DOUT Program Inhibit VIH VIH X X VCP VPP High Z Erase VIL VIH VIL VPE VCC VPE DIH Erase Verify VIH VIL X X VCC VPE DOUT Erase Inhibit VIH VIH X X VCP VPP High Z Product Identifier-manufacturer VIL VIL VIL VHH VCC VCC DA (Hex) Product Identifier-device VIL VIL VIH VHH VCC VCC 02 (Hex) Standby (CMOS) -3- OUTPUTS Publication Release Date: January 1997 Revision A3 W27E257 DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER RATING UNIT Ambient Temperature with Power Applied -55 to +125 °C Storage Temperature -65 to +125 °C -0.5 to VCC +0.5 V Voltage on VPP Pin with Respect to Ground -0.5 to +14.5 V Voltage on A9 Pin with Respect to Ground -0.5 to +14.5 V Voltage on VCC Pin with Respect to Ground -0.5 to +7 V Voltage on all pins with Respect to Ground Except VPP, A9 and VCC pins Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. DC Erase Characteristics (TA = 25° C ±5° C, VCC = 5.0V ±10%) PARAMETER SYM. CONDITIONS LIMITS UNIT MIN. TYP. MAX. -10 - 10 µA Input Load Current ILI VIN = VIL or VIH VCC Erase Current ICP CE = VIL - - 30 mA VPP Erase Current IPP CE = VIL - - 30 mA Input Low Voltage VIL - -0.3 - 0.8 V Input High Voltage VIH - 2.4 - 5.5 V Output Low Voltage (Verify) VOL IOL = 2.1 mA - - 0.45 V Output High Voltage (Verify) VOH IOH = -0.4 mA 2.4 - - - A9 Erase Voltage VID - 13.75 14 14.25 V VPP Erase Voltage VPE - 13.75 14 14.25 V VCC Supply Voltage (Erase) VCE - 4.5 5.0 5.5 V Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. CAPACITANCE (VCC = 5V, TA = 25° C, f = 1 MHz) PARAMETER SYMBOL CONDITIONS Input Capacitance CIN Output Capacitance COUT -4- MAX. UNIT VIN = 0V 6 pF VOUT = 0V 12 pF W27E257 AC CHARACTERISTICS AC Test Conditions PARAMETER CONDITIONS Input Pulse Levels 0.45V to 2.4V Input Rise and Fall Times 10 nS Input and Output Timing Reference Level 0.8V/2.0V Output Load CL = 100 pF, IOH/IOL = -0.4 mA/2.1 mA AC Test Load and Waveform +1.3V (IN914) 3.3K ohm DOUT 100 pF (Including Jig and Scope) Input Output Test Points 2.4V 0.45V Test Points 2.0V 2.0V 0.8V 0.8V -5- Publication Release Date: January 1997 Revision A3 W27E257 READ OPERATION DC CHARACTERISTICS (VCC = 5.0V ±10%, TA = 0 to 70° C) (W27E257-10, S-10, K-10, P-10: VCC, min. = 3.0V and max. = 5.5V) PARAMETER SYM. CONDITIONS LIMITS UNIT MIN. TYP. MAX. Input Load Current ILI VIN = 0V to VCC -5 - 5 µA Output Leakage Current ILO VOUT = 0V to VCC -10 - 10 µA VCC Standby Current ISB CE = VIH - - 1.0 mA ISB1 CE = VCC ±0.2V - 5 100 µA VCC Operating Current ICC CE = VIL IOUT = 0 mA f = 5 MHz - - 30 mA VPP Operating Current IPP VPP = VCC - - 100 µA Input Low Voltage VIL - -0.3 - 0.8 V Input High Voltage VIH - 2.0 - VCC +0.5 V Output Low Voltage VOL IOL = 2.1 mA - - 0.45 V Output High Voltage VOH IOH = -0.4 mA 2.4 - - V VPP Operating Voltage VPP VCC -0.7 - VCC V - READ OPERATION AC CHARACTERISTICS (VCC = 5.0V ±10%, TA = 0 to 70° C) PARAMETER SYM. W27E257-10 W27E257-12 W27E257-15 MIN. MAX. MIN. MAX. MIN. MAX. UNIT Read Cycle Time TRC 100 - 120 - 150 - nS Chip Enable Access Time TCE - 100 - 120 - 150 nS Address Access Time TACC - 100 - 120 - 150 nS Output Enable Access Time TOE - 50 - 60 - 70 nS OE High to High-Z Output TDF - 30 - 30 - 50 nS Output Hold from Address Change TOH 0 - 0 - 0 - nS Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. -6- W27E257 DC PROGRAMMING CHARACTERISTICS (VCC = 5.0V ±10%, TA = 25° C ±5° C) PARAMETER SYM. CONDITIONS LIMITS UNIT MIN. TYP. MAX. -10 - 10 µA Input Load Current ILI VIN = VIL or VIH VCC Program Current ICP CE = VIL - - 30 mA VPP Program Current IPP CE = VIL - - 30 mA Input Low Voltage VIL - -0.3 - 0.8 V Input High Voltage VIH - 2.4 - 5.5 V Output Low Voltage (Verify) VOL IOL = 2.1 mA - - 0.45 V Output High Voltage (Verify) VOH IOH = -0.4 mA 2.4 - - V A9 Silicon I.D. Voltage VID - 11.5 12.0 12.5 V VPP Program Voltage VPP - 11.75 12.0 12.25 V VCC Supply Voltage (Program) VCP - 4.5 5.0 5.5 V AC PROGRAMMING/ERASE CHARACTERISTICS (VCC = 5.0V ±10%, TA = 25° C ±5° C) PARAMETER SYM. LIMITS UNIT MIN. TYP. MAX. VPP Setup Time TVPS 2.0 - - µS Address Setup Time TAS 2.0 - - µS Data Setup Time TDS 2.0 - - µS CE Program Pulse Width TPWP 95 100 105 µS CE Erase Pulse Width TPWE 95 100 105 mS Data Hold Time TDH 2.0 - - µS OE Setup Time TOES 2.0 - - µS Data Valid from OE TOEV - - 150 nS OE High to Output High Z TDFP 0 - 130 nS Address Hold Time TAH 0 - - µS Address Hold Time after CE High (Erase) TAHC 2.0 - - µS Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. -7- Publication Release Date: January 1997 Revision A3 W27E257 TIMING WAVEFORMS AC Read Waveform VIH Address Valid Address VIL VIH CE VIL TCE VIH OE TDF VIL TOE TOH TACC High Z Outputs Valid Output High Z Erase Waveform Read Read Manufacturer Device SID SID A9 = 12.0V Address A0= V IH Others = VIL VIH VIL Chip Erase A9 = 14.0V Others = VIL Address Stable A0 = VIL Others = VIL TACC Data TACC DA Blank Check Read Verify Erase Verify TAS 02 TARC Address Stable Address Stable TACC TDFP DOUT Data All One TDS DOUT DOUT TAH TAHC 14.0V 5V 5.0V TVPS VPP VIH CE TCE VIL TOE TOE TPWE TOES TOE VIH OE VIL TOEV -8- W27E257 Timing Waveforms, continued Programming Waveform Program Verify Program Read Verify VIH Address Stable Address Address Stable Address Valid VIL TDFP TAS Data Data In Stable TDS DOUT TACC DOUT DOUT TAH TDH 12.0V VPP 5.0V 5V TVPS VIH CE VIL VIH OE VIL TOE TPWP TOES TOEV -9- Publication Release Date: January 1997 Revision A3 W27E257 SMART PROGRAMMING ALGORITHM Start Address = First Location Vcc = 5V Vpp = 12V X=0 Program One 100 µS Pulse Increment X Yes X = 25? No Fail Verify One Byte Verify One Byte Pass Increment Address No Fail Pass Last Address? Yes Vcc = 5V Vpp = 5V Compare All Bytes to Original Data Fail Pass Fail Device Pass Device - 10 - W27E257 SMART ERASE ALGORITHM Start X=0 Vcc = 5V Vpp = 14V A9 = 14V; A0 = VIL Chip Erase 100 mS Pulse Address = First Location Increment X No Erase Verify Fail X = 20? Pass Yes Increment Address No Last Address? Yes Vcc = 5V Vpp = 5V Compare All Bytes to FFs (HEX) Fail Pass Pass Device Fail Device - 11 - Publication Release Date: January 1997 Revision A3 W27E257 ORDERING INFORMATION PART NO. ACCESS TIME (nS) POWER SUPPLY CURRENT MAX. (mA) STANDBY VCC CURRENT MAX. (µA) PACKAGE W27E257-10 100 30 100 600 mil DIP W27E257-12 120 30 100 600 mil DIP W27E257-15 150 30 100 600 mil DIP W27E257P-10 100 30 100 32-pin PLCC W27E257P-12 120 30 100 32-pin PLCC W27E257P-15 150 30 100 32-pin PLCC Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. - 12 - W27E257 PACKAGE DIMENSIONS 28-pin P-DIP Symbol A A1 A2 B B1 c D E E1 e1 L D 28 15 a E1 eA S Notes: 1 14 c Base Plane A A2 A1 L Seating Plane B e1 eA a Dimension in mm Min. Nom. Max. Min. Nom. Max. 5.33 0.210 0.010 0.25 0.150 0.155 0.160 3.81 3.94 4.06 0.016 0.018 0.022 0.41 0.46 0.56 0.058 0.060 0.064 1.47 1.52 1.63 0.008 0.010 0.014 0.20 0.25 0.36 1.460 1.470 37.08 37.34 0.590 0.600 0.610 14.99 15.24 15.49 0.540 0.545 0.550 13.72 13.84 13.97 0.100 0.110 2.29 2.54 2.79 0.130 0.140 3.05 3.30 3.56 15 0 0.670 16.00 16.51 17.02 0.090 0.120 0 0.630 0.650 15 0.090 2.29 1. Dimension D Max. & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimension D & E1 include mold mismatch and are determined at the mold parting line. 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec. E S Dimension in Inches B1 32-pin PLCC HE E 4 1 32 30 Symbol 5 29 GD D HD 21 13 14 c 20 A A1 A2 b1 b c D E e GD GE HD HE L y θ Dimension in Inches Min. Nom. Max. Dimension in mm Min. Nom. Max. 3.56 0.140 0.50 0.020 0.105 0.110 0.115 2.67 2.80 2.93 0.026 0.028 0.032 0.66 0.71 0.81 0.016 0.018 0.022 0.41 0.46 0.56 0.008 0.010 0.014 0.20 0.25 0.35 0.547 0.550 0.553 13.89 13.97 14.05 11.51 0.447 0.450 0.453 11.35 11.43 0.044 0.050 0.056 1.12 1.27 1.42 0.490 0.51 0 0.410 0.530 12.45 13.46 0.430 9.91 12.9 5 10.41 0.585 0.590 0.595 14.86 14.99 15.11 0.485 0.49 0 0.090 0.495 12.32 12.45 12.57 0.095 1.91 2.29 2.41 0.390 0.075 0.004 0° 10° 10.92 0.10 0° 10° Notes: L A2 θ e b b1 Seating Plane 1. Dimension D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches. 4. General appearance spec. should be based on final visual inspection sepc. A A1 y GE - 13 - Publication Release Date: January 1997 Revision A3 W27E257 Headquarters Winbond Electronics (H.K.) Ltd. No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5792647 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-7197006 Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 Note: All data and specifications are subject to change without notice. - 14 - Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2730 Orchard Parkway, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668