CY2077 High-accuracy EPROM Programmable Single-PLL Clock Generator Features ■ Sixteen selectable post-divide options, using either PLL or reference oscillator/external clock ■ Programmable PWR_DWN or OE pin, with asynchronous or synchronous modes ■ High-accuracy PLL with 12-bit multiplier and 10-bit divider ■ EPROM programmability ■ 3.3 V or 5 V operation ■ ■ Operating frequency ❐ 390 kHz–133 MHz at 5 V ❐ 390 kHz–100 MHz at 3.3 V Low jitter outputs typically ❐ 80 ps at 3.3 V/5 V ■ Controlled rise and fall times and output slew rate ■ Available in both commercial and industrial temperature ranges Reference input from either a 10–30 MHz fundamental toned crystal or a 1–75 MHz external clock ■ Factory programmable device options ■ ■ EPROM selectable TTL or CMOS duty cycle levels For a complete list of related documentation, click here. Logic Block Diagram XTALIN or external clock Q 10 bits Phase Detector XTALOUT[1] Crystal Oscillator PWR_DWN or OE Charge Pump Configuration EPROM VCO P 12 bits HIGH ACCURACY PLL MUX / 1, 2, 4, 8, 16, 32, 64, 128 CLKOUT Note 1. When using an external clock source, leave XTALOUT floating. Cypress Semiconductor Corporation Document Number: 38-07210 Rev. *I • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 20, 2015 CY2077 Contents Pinouts .............................................................................. 3 Functional Description ..................................................... 3 EPROM Configuration Block ........................................... 3 PLL Output Frequency ..................................................... 3 Power Management Features .......................................... 4 Absolute Maximum Ratings ............................................ 4 Operating Conditions for Commercial Temperature Device ................................... 4 Electrical Characteristics................................................. 5 Output Clock Switching Characteristics Commercial Over the Operating Range ............................................... 6 Operating Conditions for Industrial Temperature Device ....................................... 7 Electrical Characteristics ................................................. 7 Output Clock Switching Characteristics Industrial Over the Operating Range ............................................... 8 Document Number: 38-07210 Rev. *I Switching Waveforms ..................................................... 9 Typical Rise/Fall Time Trends for CY2077 ................... 10 Typical Duty Cycle Trends for CY2077 ......................... 11 Typical Jitter Trends for CY2077 ................................... 12 Programming Procedures ............................................. 13 Ordering Information ...................................................... 13 Package Diagrams .......................................................... 14 Document History Page ................................................. 16 Sales, Solutions, and Legal Information ...................... 17 Worldwide Sales and Design Support ....................... 17 Products .................................................................... 17 PSoC® Solutions ...................................................... 17 Cypress Developer Community ................................. 17 Technical Support ..................................................... 17 Page 2 of 17 CY2077 Pinouts Figure 1. Pin Diagram - 8 Pin Top View VDD XTALOUT XTALIN PD/OE 1 2 3 4 8 7 6 5 CLKOUT VSS VSS VSS Table 1. Pin Definition - 8 Pin Pin Name Pin # Pin Description VDD 1 VSS 5,6,7 XD 2 Crystal output (leave this pin floating when external reference is used) XG 3 Crystal input or external input reference PWR_DWN / OE 4 EPROM programmable power down or output enable pin. PWR_DWN is active low. OE is active high. Weak pull up. CLKOUT 8 Clock output. Weak pull down Voltage supply Ground (all the pins must be grounded) Functional Description CY2077 is an EPROM-programmable, high-accuracy, general-purpose, PLL-based design for use in applications such as modems, disk drives, CD-ROM drives, video CD players, DVD players, games, set-top boxes, and data/telecommunications. CY2077 can generate a clock output up to 133 MHz at 5 V or 100 MHz at 3.3 V. It has been designed to give the customer a very accurate and stable clock frequency with little to zero PPM error. CY2077 contains a 12-bit feedback counter divider and 10-bit reference counter divider to obtain a very high resolution to meet the needs of stringent design specifications. Furthermore, there are eight output divide options of /1, /2, /4, /8, /16, /32, /64, and /128. The output divider can select between the PLL and crystal oscillator output/external clock, providing a total of 16 different options to add more flexibility in designs. TTL or CMOS duty cycles can be selected. Power management with the CY2077 is also very flexible. The user can choose either a PWR_DWN, or an OE feature with which both have integrated pull up resistors. PWR_DWN and OE signals can be programmed to have asynchronous and synchronous timing with respect to the output signal. There is a weak pull down on the output that pulls CLKOUT LOW when either the PWR_DWN or OE signal is LOW. This weak pull down can easily be overridden by another clock signal in designs where multiple clock signals share a signal path. Multiple options for output selection, better power distribution layout, and controlled rise and fall times enable the CY2077 to be used in applications that require low jitter and accurate reference frequencies. EPROM Configuration Block Table 2. EPROM Adjustable Features EPROM Adjustable Features Adjust Freq. Feedback counter value (P) Reference counter value (Q) Output divider selection Duty cycle levels (TTL or CMOS) Power management mode (OE or PWR_DWN) Power management timing (synchronous or asynchronous) PLL Output Frequency CY2077 contains a high-resolution PLL with 12-bit multiplier and 10-bit divider.[2] The output frequency of the PLL is determined by the following formula: 2 P + 5 F PLL = --------------------------- F REF Q + 2 where P is the feedback counter value and Q is the reference counter value. P and Q are EPROM programmable values. The calculation of P and Q values for a given PLL output frequency is handled by the CyberClocks software. Refer to ““Programming Procedures” on page 13” for details. Note 2. When using CyClocks, note that the PLL frequency range is from 50 MHz to 250 MHz for 5 V VDD supply, and 50 MHz to 180 MHz for 3 V VDD supply. The output frequency is determined by the selected output divider. Document Number: 38-07210 Rev. *I Page 3 of 17 CY2077 Power Management Features Additionally, PWR_DWN and OE can be configured to occur asynchronously or synchronously with respect to CLKOUT. In asynchronous mode, PWR_DWN or OE disables CLKOUT immediately (allowing for logic delays), without respect to the current state of CLKOUT. Synchronous mode prevents output glitches by waiting for the next falling edge of CLKOUT after PWR_DWN, or OE becomes asserted. In either asynchronous or synchronous setting, the output is always enabled synchronously by waiting for the next falling edge of CLKOUT. PWR_DWN and OE options are configurable by EPROM programming for the CY2077. In PWR_DWN mode, all active circuits are powered down when the control pin is set LOW. When the control pin is set back HIGH, both the PLL and oscillator circuit must relock. In the case of OE, the output is three-stated and weakly pulled down when the control pin is set LOW. The oscillator and PLL are still active in this state, which leads to a quick clock output return when the control pin is set back HIGH. Table 3. Device Functionality: Output Frequencies Symbol Fo Description Output frequency Condition Min Max Unit VDD = 4.5–5.5 V 0.39 133 MHz VDD = 3.0–3.6 V 0.39 100 MHz Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature (non-condensing)...... –55°C to +150°C Supply voltage ................................................. –0.5 to +7.0 V Static discharge voltage.......................................... > 2000 V (per MIL-STD-883, method 3015) Input voltage ......................................... –0.5 V to VDD +0.5 V Junction temperature.................................................. 150°C Operating Conditions for Commercial Temperature Device Parameter Description Min Max Unit VDD Supply voltage 3.0 5.5 V TA Operating temperature, ambient 0 +70 °C CTTL Max. capacitive load on outputs for TTL levels VDD = 4.5 – 5.5 V, output frequency = 1 – 40 MHz VDD = 4.5 – 5.5 V, output frequency = 40 – 125 MHz VDD = 4.5 – 5.5 V, output frequency = 125 – 133 MHz – – – 50 25 15 pF pF pF CCMOS Max. capacitive load on outputs for CMOS levels VDD = 4.5 – 5.5 V, output frequency = 1 – 40 MHz VDD = 4.5 – 5.5 V, output frequency = 40 – 125 MHz VDD = 4.5 – 5.5 V, output frequency = 125 – 133 MHz VDD = 3.0 – 3.6 V, output frequency = 1 – 40 MHz VDD = 3.0 – 3.6 V, output frequency = 40 – 100 MHz – – – – – 50 25 15 30 15 pF pF pF pF pF Reference frequency, input crystal with Cload = 10 pF 10 30 MHz Reference frequency, external clock source 1 75 MHz 0.05 50 ms XREF tPU Power up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) Document Number: 38-07210 Rev. *I Page 4 of 17 CY2077 Electrical Characteristics TA = 0°C to +70°C Parameter Description Test Conditions Min Typ Max Unit VIL Low-level input voltage VDD = 4.5 – 5.5 V VDD = 3.0 – 3.6 V – – – – 0.8 0.2 VDD V V VIH High-level input voltage VDD = 4.5 – 5.5 V VDD = 3.0 – 3.6 V 2.0 0.7 VDD – – – – V V VOL Low-level output voltage VDD = 4.5 – 5.5 V, IOL= 16 mA VDD = 3.0 – 3.6 V, IOL= 8 mA – – – – 0.4 0.4 V V VOHCMOS High-level output voltage CMOS levels VDD = 4.5 – 5.5 V, IOH= –16 mA VDD = 3.0 – 3.6 V, IOH= –8 mA VDD – 0.4 VDD – 0.4 – – – – V V 2.4 – – V – – 10 A VOHTTL High-level output voltage TTL levels VDD = 4.5 – 5.5 V, IOH= –8 mA IIL Input low current VIN = 0 V IIH Input high current VIN = VDD – – 5 A IDD Power supply current Unloaded VDD = 4.5 – 5.5 V, output frequency <= 133 MHz VDD = 3.0 – 3.6 V, output frequency <= 100 MHz – – 45 mA – – 25 mA – – 25 10 100 50 A A 1.1 50 3.0 100 8.0 200 M k – 20 – A IDDS[3] Stand-by current (PD = 0) VDD = 4.5 – 5.5 V VDD = 3.0 – 3.6 V RUP Input pull up resistor VDD = 4.5 – 5.5 V, VIN = 0 V VDD = 4.5 – 5.5 V, VIN = 0.7 VDD IOE_CLKOUT CLKOUT pull down current VDD = 5.0 Note 3. If external reference is used, it is required to stop the reference (set reference to LOW) during power down. Document Number: 38-07210 Rev. *I Page 5 of 17 CY2077 Output Clock Switching Characteristics Commercial Over the Operating Range[4] Parameter Description Test Conditions Min Typ Max Unit t1w Output duty cycle at 1.4 V, 1 – 40 MHz, CL <= 50 pF VDD = 4.5 – 5.5 V 40 – 125 MHz, CL <= 25 pF t1w = t1A t1B 125 – 133 MHz, CL <= 15 pF 45 45 45 – – – 55 55 55 % % % t1x Output duty cycle at VDD/2, 1 – 40 MHz, CL <= 50 pF VDD = 4.5 – 5.5 V 40 – 125 MHz, CL <= 25 pF t1x = t1A t1B 125 – 133 MHz, CL <= 15 pF 45 45 45 – – – 55 55 55 % % % t1y Output duty cycle at VDD/2, 1 – 40 MHz, CL <= 30 pF VDD = 3.0 – 3.6 V 40 – 100 MHz, CL <= 15 pF t1y = t1A t1B 45 40 – – 55 60 % % t2 Output clock rise time Between 0.8 – 2.0 V, VDD = 4.5 V – 5.5 V, CL = 50 pF Between 0.8 – 2.0 V, VDD = 4.5 V – 5.5 V, CL = 25 pF Between 0.8 – 2.0 V, VDD = 4.5 V – 5.5 V, CL = 15 pF Between 0.2 VDD – 0.8 VDD, VDD= 4.5 V – 5.5 V, CL = 50 pF Between 0.2 VDD – 0.8 VDD, VDD= 3.0 V – 3.6 V, CL = 30 pF Between 0.2 VDD – 0.8 VDD, VDD= 3.0 V – 3.6 V, CL = 15 pF – – – – – – – – – – – – 1.8 1.2 0.9 3.4 4.0 2.4 ns ns ns ns ns ns t3 Output clock fall time Between 0.8 V –2.0 V, VDD = 4.5 V – 5.5 V, CL = 50 pF Between 0.8 – 2.0 V, VDD = 4.5 V – 5.5 V, CL = 25 pF Between 0.8 – 2.0 V, VDD = 4.5 V – 5.5 V, CL = 15 pF Between 0.2 VDD – 0.8 VDD, VDD= 4.5 V – 5.5 V, CL = 50 pF Between 0.2 VDD – 0.8 VDD, VDD= 3.0 V – 3.6 V, CL = 30 pF Between 0.2 VDD – 0.8 VDD, VDD= 3.0 V – 3.6 V, CL = 15 pF – – – – – – – – – – – – 1.8 1.2 0.9 3.4 4.0 2.4 ns ns ns ns ns ns t4 Startup time out of power PWR_DWN pin LOW to HIGH[5] down – 1 2 ms t5a Power down delay time (synchronous setting) PWR_DWN pin LOW to output LOW (T= period of output CLK) – T/2 T + 10 ns t5b Power down delay time (asynchronous setting) PWR_DWN pin LOW to output LOW – 10 15 ns t6 Power up time From power on[5] – 1 2 ms t7a Output disable time (synchronous setting) OE pin LOW to output high-Z (T= period of output CLK) – T/2 T + 10 ns t7b Output disable time (asynchronous setting) OE pin LOW to output high-Z – 10 15 ns t8 Output enable time (always synchronous enable) OE pin LOW to HIGH (T= period of output CLK) – T 1.5T+ 25ns ns t9 Peak-to-peak period jitter VDD = 3.0 V – 3.6 V, 4.5 V – 5.5 V, Fo > 33 MHz, VCO > 100 MHz VDD = 3.0 V – 5.5 V, Fo < 33 MHz – – 80 0.3% 150 1% ps % of FO Notes 4. Not all parameters measured in production testing. 5. Oscillator start time can not be guaranteed for all crystal types. This specification is for operation with AT cut crystals with ESR < 70 Document Number: 38-07210 Rev. *I Page 6 of 17 CY2077 Operating Conditions for Industrial Temperature Device Parameter Description Min Max Unit VDD Supply voltage 3.0 5.5 V TA Operating temperature, ambient –40 +85 °C CTTL Max. capacitive load on outputs for TTL levels VDD = 4.5 – 5.5 V, output frequency = 1 – 40 MHz VDD = 4.5 – 5.5 V, output frequency = 40 – 125 MHz VDD = 4.5 – 5.5 V, output frequency = 125 – 133 MHz – – – 35 15 10 pF pF pF CCMOS Max. capacitive load on outputs for CMOS levels VDD = 4.5 – 5.5 V, output frequency = 1 – 40 MHz VDD = 4.5 – 5.5 V, output frequency = 40 – 125 MHz VDD = 4.5 – 5.5 V, output frequency = 125 – 133 MHz VDD = 3.0 – 3.6 V, output frequency = 1 – 40 MHz VDD = 3.0 – 3.6 V, output frequency = 40 – 100 MHz – – – – – 35 15 10 20 10 pF pF pF pF pF XREF Reference frequency, input crystal with Cload = 10 pF 10 30 MHz Reference frequency, external clock source 1 75 MHz 0.05 50 ms tPU Power up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) Electrical Characteristics TA = –40°C to +85°C Parameter Description Test Conditions Min Typ Max Unit VIL Low-level input voltage VDD = 4.5 – 5.5 V VDD = 3.0 – 3.6 V – – – – 0.8 0.2 VDD V V VIH High-level input voltage VDD = 4.5 – 5.5 V VDD = 3.0 – 3.6 V 2.0 0.7 VDD – – – – V V VOL Low-level output voltage VDD = 4.5 – 5.5 V, IOL= 16 mA VDD = 3.0 – 3.6 V, IOL= 8 mA – – – – 0.4 0.4 V V VOHCMOS High-level output voltage, VDD = 4.5 – 5.5 V, IOH= –16 mA CMOS levels VDD = 3.0 – 3.6 V, IOH= –8 mA VDD – 0.4 VDD – 0.4 – – – – V V VOHTTL High-level output voltage, VDD = 4.5 – 5.5 V, IOH= –8 mA TTL levels 2.4 – – V IIL Input low current VIN = 0 V – – 10 A IIH Input high current VIN = VDD – – 5 A IDD Power supply current, Unloaded VDD = 4.5 – 5.5 V, output frequency <= 133 MHz VDD = 3.0 – 3.6 V, output frequency <= 100 MHz – – 45 mA – – 25 mA – – 25 10 100 50 A 1.1 50 3.0 100 8.0 200 M k – 20 – A IDDS[3] Stand-by current (PD = 0) VDD = 4.5 – 5.5 V VDD = 3.0 – 3.6 V RUP Input pull up resistor VDD = 4.5 – 5.5 V, VIN = 0 V VDD = 4.5 – 5.5 V, VIN = 0.7 VDD IOE_CLKOUT CLKOUT pull down current VDD = 5.0 Document Number: 38-07210 Rev. *I Page 7 of 17 CY2077 Output Clock Switching Characteristics Industrial Over the Operating Range[4] Parameter Description Test Conditions Min Typ. Max Unit t1w Output duty cycle at 1.4 V, VDD = 4.5 – 5.5 V t1w = t1A t1B 1 – 40 MHz, CL <= 35 pF 40 – 125 MHz, CL <= 15 pF 125 – 133 MHz, CL <= 10 pF 45 45 45 55 55 55 % % % t1x Output duty cycle at 1 – 40 MHz, CL <= 35 pF VDD/2, VDD = 4.5 – 5.5 V 40 – 125 MHz, CL <= 15 pF t1x = t1A t1B 125 – 133 MHz, CL <= 10 pF 45 45 45 55 55 55 % % % t1y Output duty cycle at 1– 40 MHz, CL <= 20 pF VDD/2, VDD = 3.0 – 3.6 V 40 – 100 MHz, CL <= 10 pF t1y = t1A t1B 45 40 55 60 % % t2 Output clock rise time Between 0.8 – 2.0 V, VDD = 4.5 V – 5.5 V, CL = 35 pF Between 0.8 – 2.0 V, VDD = 4.5 V – 5.5 V, CL = 15 pF Between 0.8 – 2.0 V, VDD = 4.5 V – 5.5 V, CL = 10 pF Between 0.2 VDD – 0.8 VDD, VDD= 4.5 V – 5.5 V, CL = 35 pF Between 0.2 VDD – 0.8 VDD, VDD= 3.0 V – 3.6 V, CL = 20 pF Between 0.2 VDD – 0.8 VDD, VDD= 3.0 V – 3.6 V, CL = 10 pF – – – – – – 1.8 1.2 0.9 3.4 4.0 2.4 ns ns ns ns ns ns t3 Output clock fall time Between 0.8 V – 2.0 V, VDD = 4.5 V – 5.5 V, CL = 35 pF Between 0.8 – 2.0 V, VDD = 4.5 V – 5.5 V, CL = 15 pF Between 0.8 – 2.0 V, VDD = 4.5 V – 5.5 V, CL = 10 pF Between 0.2 VDD – 0.8 VDD, VDD= 4.5 V – 5.5 V, CL = 35 pF Between 0.2 VDD – 0.8 VDD, VDD= 3.0 V – 3.6 V, CL = 20 pF Between 0.2 VDD – 0.8 VDD, VDD= 3.0 V – 3.6 V, CL = 10 pF – – – – – – 1.8 1.2 0.9 3.4 4.0 2.4 ns ns ns ns ns ns t4 Startup time out of Power PWR_DWN pin LOW to HIGH[5] down – 1 2 ms t5a Power down delay time (synchronous setting) PWR_DWN pin LOW to output LOW (T= period of output clk) – T/2 T+10 ns t5b Power down delay time (asynchronous setting) PWR_DWN pin LOW to output LOW – 10 15 ns t6 Power up time From power on[5] – 1 2 ms t7a Output Disable time (synchronous setting) OE pin LOW to output high-Z (T= period of output clk) – T/2 T + 10 ns t7b Output Disable time (asynchronous setting) OE pin LOW to output high-Z – 10 15 ns t8 Output Enable time (always synchronous enable) OE pin LOW to HIGH (T = period of output clk) – T 1.5T + 25ns ns t9 Peak-to-peak period jitter VDD = 3.0 V – 3.6 V, 4.5 V – 5.5 V, Fo > 33 MHz, VCO > 100 MHz VDD = 3.0 V – 5.5 V, Fo < 33 MHz – 80 150 ps – 0.3% 1% % of FO Document Number: 38-07210 Rev. *I Page 8 of 17 CY2077 Switching Waveforms Figure 2. Duty Cycle Timing (t1w, t1x, t1y) t1B t1A OUTPUT Figure 3. Output Rise/Fall Time VDD OUTPUT 0V t2 t3 Figure 4. Power down Timing (synchronous and asynchronous modes) POWER DOWN VDD VIH VIL t4 0V CLKOUT (synchronous[6]) T t5a 1/f CLKOUT (asynchronous[7]) 1/f t5b Figure 5. Power up Timing VDD POWER UP VDD – 10% t6 0V min 30 s max 30 ms CLKOUT 1/f Figure 6. Output Enable Timing (synchronous and asynchronous modes) OUTPUT ENABLE VDD VIH VIL 0V T CLKOUT High Impedance (synchronous[6]) t7a CLKOUT t8 High Impedance (asynchronous[7]) t7b t8 Notes 6. In synchronous mode, the power down or output three-state is not initiated until the next falling edge of the output clock. 7. In asynchronous mode, the power down or output three-state occurs within 25 ns regardless of position in the output clock cycle. Document Number: 38-07210 Rev. *I Page 9 of 17 CY2077 Typical Rise/Fall Time[8] Trends for CY2077 Figure 7. Rise/Fall Time vs. VDD over Temperatures Rise Time vs. VDD -- CMOS duty Cycle Cload = 15pF Rise Time (ns) 2.00 1.80 -40C 25C 85C 1.60 1.40 1.20 Fall Time (ns) Fall Time vs. VDD -- CMOS duty Cycle Cload = 15pF 1.00 2.7 3.0 3.3 3.6 2.00 1.80 1.60 1.40 1.20 1.00 -40C 25C 85C 2.7 3.9 3.0 0.70 0.60 0.50 0.40 0.30 0.20 -40C 25C 85C 5.0 3.9 Fall Time vs. VDD -- TTL duty Cycle Cload = 15pF 5.5 Fall Time (ns) Rise Time (ns) Rise Time vs. VDD -- TTL duty Cycle Cload = 15pF 4.5 3.6 VDD (V) VDD (V) 4.0 3.3 0.70 0.60 0.50 0.40 0.30 0.20 6.0 -40C 25C 85C 4.0 4.5 VDD (V) 5.0 5.5 6.0 VDD (V) Figure 8. Rise/Fall Time vs. Output Loads over Temperatures Fall Time vs. CLoad over Temperature VDD = 3.3v, CMOS output 2.50 -40C 25C 85C 2.00 1.50 1.00 10 15 20 25 Cload (pF) 30 35 Fall Time (ns) Rise Time (ns) Rise Time vs. CLoad over Temperature VDD = 3.3v, CMOS output 2.00 -40C 25C 85C 1.50 1.00 10 15 20 25 30 35 Cload (pF) Note 8. Rise/Fall time for CMOS output is measured between 1.2 VDD and 0.8 VDD. Rise/Fall time for TTL output is measured between 0.8 V and 2.0 V. Document Number: 38-07210 Rev. *I Page 10 of 17 CY2077 Typical Duty Cycle[9] Trends for CY2077 Figure 9. Duty Cycle vs. VDD over Temperatures 55.00 53.00 51.00 49.00 47.00 45.00 Duty Cycle vs. VDD over Temperature (CMOS Duty Cycle Ouput, Fout=50MHz, Cload=50pF) -40C 25C 85C 4.0 4.5 5.0 5.5 Duty Cycle (%) Duty Cycle (%) Duty Cycle vs. VDD over Temperature (TTL Duty Cycle Output, Fout=50MHz, Cload = 50pF) 55.00 53.00 51.00 49.00 47.00 45.00 6.0 -40C 25C 85C 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) VDD (v) Figure 10. Duty Cycle vs. Output Load Duty Cycle (%) Duty Cycle vs. CLoad with Various VDD (Fout = 50MHz, Temp = 25C) 55.00 53.00 51.00 49.00 47.00 45.00 VDD=4.5V VDD=5.0V VDD=5.5V 10 15 20 25 30 35 40 45 50 55 Cload (pF) Output DC (%) Figure 11. Duty Cycle vs. Output Frequency over Temperatures Output Duty Cycle vs. Fout over Temperature (Vdd = 5V, Cload = 15pF) 55.00% 54.00% 53.00% 25C 52.00% 85C 51.00% -40C 50.00% 20 30 40 50 60 70 80 Output Frequency (MHz) Note 9. Duty cycle is measured at 1.4 V for TTL output and 0.5 VDD for CMOS output. Document Number: 38-07210 Rev. *I Page 11 of 17 CY2077 Typical Jitter Trends for CY2077 Figure 12. Period Jitter (pk-pk) vs. VDD over Temperatures Period Jitter (pk-pk) vs. VDD over Temperatures (Fout=40MHz, Cload = 30pF) Period JItter (ps) 100 80 60 -40C 40 25C 20 85C 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) Figure 13. Period Jitter (pk-pk) vs. Output Frequency over Temperatures Output Jitter (pk-pk) vs. Output Frequency (VDD=3.3V, Cload=15pf, CMOS output) 100 Jitter (ps) 80 25C 60 -40C 40 85C 20 0 0 20 40 60 80 100 120 140 Output frequency (MHz) Output Jitter(pk-pk) vs. Output Frequency (VDD=5.0V, Cload=15pf, CMOS output) 100 Jitter (ps) 80 25C 60 -40C 40 85C 20 0 0 20 40 60 80 100 120 140 Output frequency (MHz) Document Number: 38-07210 Rev. *I Page 12 of 17 CY2077 Programming Procedures Currently the CY2077 is available only as a field-programmable device, as indicated by an “F” in the ordering code. Devices may be programmed using the CY3672-USB programmer, or through programmers available from third party programmer manufacturers such as Hi-Lo Systems and BP Micro. Programming services are also available from third parties, including some Cypress distribution partners. To generate a JEDEC format programming file, customers must use CyClocks software. This software automatically calculates the output frequencies that can be generated by CY2077 devices. The CyClocks software is a subset of the larger software tool CyberClocks, which is available free of charge from the Cypress web site (http://www.cypress.com). CyberClocks is installed on a PC and must not be confused with the web-based application CyberClocks Online. For high volume designs, factory programming of customer-specific configurations is available on other 8-pin devices such as the CY22180, CY22801 and CY22381. Factory programming is no longer offered for new designs using the CY2077. Ordering Information Order Code[11] Package Name Package Type Operating Temp. Range Operating Voltage Pb-Free CY2077FSXC S8 8-pin SOIC Commercial (T = 0 °C to 70 °C) 3.3 V or 5 V CY2077FSXCT S8 8-pin SOIC–Tape and Reel Commercial (T = 0 °C to 70 °C) 3.3 V or 5 V CY2077FZZ Z8 8-pin TSSOP Commercial (T = 0 °C to 70 °C) 3.3 V or 5 V CY2077FZXI Z8 8-pin TSSOP Industrial (T = –40 °C to 85 °C) 3.3 V or 5 V CY2077FZXIT Z8 8-pin TSSOP–Tape and Reel Industrial (T = –40 °C to 85 °C) 3.3 V or 5 V Programmer CY3672-USB Programming Kit CY3696 Socket adapter board, for programming CY2077FS (SOIC Package) CY3697 Socket adapter board, for programming CY2077FZ (TSSOP Package) Table 4. Obsolete or Not For New Designs Original Device Order Code[10, 11] Replacement Device Description Order Code CY2077SC-xxx none CY2077SC-xxxT none CY2077SI-xxx none CY2077SI-xxxT none CY2077SXC-xxx none CY2077SXC-xxxT none CY2077ZC-xxx none CY2077ZC-xxxT none CY2077ZI-xxx none CY2077ZI-xxxT none CY2077ZXC-xxx none CY2077ZXC-xxxT none Description CY2077FSI SOIC, Industrial (T = –40 °C to 85 °C) CY2077FSXC Pb-free SOIC, Commercial CY2077FZ TSSOP, Commercial (T = 0 °C to 70 °C) CY2077FZZ Pb-free TSSOP, Commercial CY2077FZI TSSOP, Industrial (T = –40 °C to 85 °C) CY2077FZXI Pb-free TSSOP, Industrial Notes 10. The CY2077SC-xxx(T), CY2077SI-xxx(T), CY2077SXC-xxx(T), CY2077ZC-xxx(T), CY2077ZI-xxx(T) andCY2077ZXC-xxx(T), are factory programmed configurations. Factory programming is available for high-volume design opportunities. For more details, contact your local Cypress FAE or Cypress Sales Representative. 11. The CY2077F are field programmable. For more details, contact your local Cypress FAE or Cypress Sales Representative. Document Number: 38-07210 Rev. *I Page 13 of 17 CY2077 Package Diagrams Figure 14. 8-pin (150 mil Body) SOIC (Small Outline IC) 51-85066 *G Document Number: 38-07210 Rev. *I Page 14 of 17 CY2077 Figure 15. 8-pin (4.40-mm Body) TSSOP (Thin Shrunk Small Outline Package) 51-85093 *E Document Number: 38-07210 Rev. *I Page 15 of 17 CY2077 Document History Page Document Title: CY2077 High-accuracy EPROM Programmable Single-PLL Clock Generator Document Number: 38-07210 ECN Orig. of Change ** 111727 DSG 02/07/02 Convert from Spec number: 38-01009 to 38-07210 *A 114938 CKN 07/24/02 Added table and notes to page 11 Revision Sumbission Date Description of Change *B 121843 RBI 12/14/02 Power up requirements added to Operating Conditions Information *C 2104546 PYG/KVM /AESA See ECN Updated Ordering Information table Replaced the “Custom Configuration Request Procedure” section with “Programming Procedures” Updated package diagrams *D 2631183 KVM/AESA 01/06/09 Updated template. CY2077FS removed from the active part number table. Added CY2077FZXI and CY2077FZXIT to the Ordering Information table. Corrected wording on p. 2 about when the weak output pull-down is active. Added to Table 1 to indicate that PWR_DWN is active low and OE is active high. *E 2905892 CXQ 04/07/10 Removed inactive part CY2077FS from Table 4. Updated package diagrams. *F 3388539 MNSB/ PURU 09/29/11 Replaced “CY3670” with “CY3672-USB” under Programming Procedures on page 13. Updated Ordering Information on page 13 to include correct programmer part numbers and socket adapters. *G 3514611 PURU 02/01/2012 Removed benefits section Updated Package Diagrams *H 4575273 PURU 11/20/2014 Added related documentation hyperlink in page 1. Updated package diagrams. *I 4694396 TAVA 03/20/2015 Updated Package Diagrams: spec 51-85066 – Changed revision from *F to *G. Updated to new template. Document Number: 38-07210 Rev. *I Page 16 of 17 CY2077 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive cypress.com/go/automotive Clocks & Buffers Interface Lighting & Power Control Memory cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions Technical Support cypress.com/go/support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2002-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-07210 Rev. *I Revised March 20, 2015 Page 17 of 17 PSoC Designer™ is a trademark and PSoC® and CapSense® are registered trademarks of Cypress Semiconductor Corporation. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. All products and company names mentioned in this document may be the trademarks of their respective holders.