CYWBDVK002ABCYWBDVK002AB West Bridge® Astoria™ Development Kit Guide Doc. # 001-47358 Rev. *D Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone (USA): 800.858.1810 Phone (Intnl): 408.943.2600 http://www.cypress.com Copyrights Copyright © Cypress Semiconductor Corporation, 2008-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. West Bridge® and Astoria™ are trademarks of Cypress Semiconductor Corporation (Cypress), along with Cypress® and Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are the property of their respective owners. Flash Code Protection Cypress products meet the specifications contained in their particular Cypress Data Sheets. Cypress believes that its family of products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress, that can breach the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as ‘unbreakable’. Cypress is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress are committed to continuously improving the code protection features of our products. 2 West Bridge Astoria Development Kit Guide, Doc. # 001-47358 Rev. *D Contents 1. Introduction 1.1 1.2 1.3 Components ................................................................................................................5 1.1.1 Development Board .........................................................................................5 1.1.2 Kit Contents......................................................................................................5 1.1.3 Supported OS Platforms ..................................................................................5 1.1.4 Product Documentation....................................................................................5 1.1.5 Astoria Software Development Kit (SDK).........................................................6 1.1.6 Diagnostics Modules for Linux .........................................................................6 Document Revision History ........................................................................................6 Documentation Conventions........................................................................................6 2. Astoria Board 2.1 5 7 Development Board .....................................................................................................7 2.1.1 Power Supply ...................................................................................................8 2.1.2 Crystal Oscillator ..............................................................................................8 2.1.3 USB Connector ................................................................................................8 2.1.4 P-Port Interfaces ..............................................................................................9 2.1.5 EEPROM Boot Mode .....................................................................................10 2.1.6 S-port Memory Interfaces...............................................................................10 2.1.7 Astoria Processor Port ...................................................................................12 2.1.8 Astoria Storage Port .......................................................................................14 2.1.9 Reset Switch ..................................................................................................14 3. Interconnection to Astoria Board 15 4. Diagnostics Module 17 4.1 4.2 4.3 Compiling Linux Diagnostics Module .........................................................................17 4.1.1 Running the Linux Diagnostics Test ...............................................................17 Test Description and Troubleshooting .......................................................................19 4.2.1 Register Read and Write ................................................................................19 4.2.2 Interrupt Testing .............................................................................................20 4.2.3 Firmware Download .......................................................................................20 4.2.4 Storage Connectivity ......................................................................................20 4.2.5 Mailbox Loopback ..........................................................................................20 Additional HAL Functions Required ...........................................................................21 Appendix 23 Schematic 23 Board Overview 23 Board Layouts 30 Bill of Materials (BOM) 32 West Bridge Astoria Development Kit Guide, Doc. # 001-47358 Rev. *D 3 Contents 4 West Bridge Astoria Development Kit Guide, Doc. # 001-47358 Rev. *D 1. Introduction The West Bridge® Astoria™ Development Kit (DVK) introduces system designers to Astoria and demonstrates its capabilities and performance. The DVK is equipped with all components to integrate the Astoria software into the customer’s platform. This document explains the DVK components. It describes the development board, explains the interconnection scheme, and also discusses signal integrity simulations and concepts for connectivity testing. 1.1 Components 1.1.1 Development Board The development board is a platform for software development. The P-port connector provides interconnection to the controller. It contains an SD slot for SD or MMC storage devices, and two 8-bit NAND slots. West Bridge Astoria firmware does not support NAND flash memories anymore. The slots of the two 8-bit NAND will be unused. 1.1.2 Kit Contents The Astoria Kit contains the following items 1.1.3 ■ CYWBDVK002AB DVK board ■ Power supply ■ USB A-B cable ■ One SD card (4GB) ■ CD with documents and software Supported OS Platforms The Astoria DVK supports the following operating systems: Windows XP (32- and 64-bit), Vista (32and 64-bit) and Windows 7 (32- and 64-bit). 1.1.4 Product Documentation Product documentation includes: ■ Astoria datasheet ■ Application notes: ■ ❐ Interfacing to West Bridge® Astoria's Pseudo-NAND Processor Port - AN46712 ❐ Schematic Review Checklist For West Bridge® Astoria™ - AN46860 ❐ High-speed USB PCB Layout Recommendations - AN1168 User guide (this document) West Bridge Astoria Development Kit Guide, Doc. # 001-47358 Rev. *D 5 Introduction 1.1.5 Astoria Software Development Kit (SDK) The Astoria software development kit provides Astoria API source code, firmware, API reference documentation, and example hardware abstraction layer (HAL) layers and drivers. The kit and all documentation are included with the SDK executable and are available at http://www.cypress.com/ go/CYWBDVK002AB. 1.1.6 Diagnostics Modules for Linux The diagnostic module is provided for Linux in the form of a loadable kernel module. The module goes through a series of tests to diagnose problems with register read and write, interrupt testing, firmware download, and storage connectivity. Chapter 4. Diagnostics Module on page 17 provides details on the implementation of this module and how to run it. 1.2 Document Revision History Revision 1.3 PDF Creation Date Origin of Change Description of Change ** 10/21/2008 OSG/AESA *A 04/19/2011 EYZ New reference design guide for West Bridge Astoria. *B 06/02/2011 ROSM Added ‘Handling TSOP Packets’ section in the Appendix chapter. *C 03/05/2012 NMMA Content updates throughout the document *D 10/31/2012 NMMA No change; sunset review Added Appendix chapter. Documentation Conventions Table 1-1. Documentation Conventions for User Guides Convention 6 Usage Courier New Displays file locations, user entered text, and source code: C:\ ...cd\icc\ Italics Displays file names and reference documentation: Read about the sourcefile.hex file in the PSoC Designer User Guide. [Bracketed, Bold] Displays keyboard commands in procedures: [Enter] or [Ctrl] [C] File > Open Represents menu paths: File > Open > New Project Bold Displays commands, menu paths, and icon names in procedures: Click the File icon and then click Open. Times New Roman Displays an equation: 2+2=4 No text, gray table cell Represents a reserved bit in register tables. West Bridge Astoria Development Kit Guide, Doc. # 001-47358 Rev. *D 2. Astoria Board 2.1 Development Board Figure 2-1. Block Diagram West Bridge Astoria Development Kit Guide, Doc. # 001-47358 Rev. *D 7 Astoria Board 2.1.1 Power Supply The hardware can be powered from the USB host or from an external 5-V power supply. Use J78 to select the mode. Select 1-2 for an external power supply and 2-3 for power from the VBUS. Figure 2-2. Power Supply The 5-V supply is regulated by three regulators connected to the Astoria and storage devices. The following table shows how Astoria power domains are configured. Table 2-1. Power Supply Routing Power Domain Description Supply Level VDD Core supply 1.8 V AVDDQ Analog supply 1.8 V GVDDQ General purpose I/Os 1.8 V XVDDQ Clocks supply 3.3 V UVDDQ USB supply 3.3 V SSVDDQ SD supply 3.3 V SNVDDQ GPIF supply 3.3 V PVDDQ Processor supply 1.8, 2.5, 3.3 V Astoria processor interface I/Os are configurable and are capable of handling 1.8, 2.5, or 3.3 V supply levels. The SD device is powered by 3.3 V supply. 2.1.2 Crystal Oscillator A 19.2 MHz crystal oscillator is connected to the crystal input of Astoria. The internal PLL produces the core, as well as SD and USB clocks. Crystal select pins are configured to support the frequency input. 2.1.3 USB Connector A standard B type USB connector is provided to attach a USB cable. VBUS is passed to J78 to enable powering the board from the USB host. It is also connected to Astoria and the processor connector for host connectivity detection. GPIO<0> or SD_WP can be used to detect VBUS. Load J55 and then select J12 1-2 to connect VBUS to GPIO<0>, or 2- 3 to connect to SD_WP. A standard A type USB connector is provided to allow access to the internal USB switch D+/D–. 8 West Bridge Astoria Development Kit Guide, Doc. # 001-47358 Rev. *D Astoria Board 2.1.4 P-Port Interfaces Astoria supports multiple interfaces on the processor for easy connectivity. The P-Port on the Astoria DVK provides different interface options. To set up the required configurations on the development kit, use switches SW6 and SW4. When the switch is ON, the corresponding line is tied to ground. When the switch is OFF, the line is pulled up to PVDDQ with a 10-K resistor. Table 2-2 and Table 2-3 show the pins connected to each of the switches. Table 2-4 shows the pin logic required for the interface modes. Table 2-2. SW6 P-port Interface Control Switch Switch Pin 1 WAKE 2 TEST[0] 3 TEST[1] 4 TEST[2] Note Wake must always be in the OFF position unless you want to force Astoria into standby mode. Table 2-3. SW4 P-port Extended Interface Control Switch Switch Pin 1 A[2] 2 A[3] 3 A[7] 4 NULL Table 2-4. P-port Configuration Interface Modes TEST[2] TEST[1] TEST[0] VMTYPE A[7] A[3] A[2] 0 0 1 x x x x Modes Debug mode Use Extended Debug mode with EIM (Required for Interface Mode (EIM) EEPROM) 1 1 x 0 0 0 101 x x x Normal (Non ADM Pseudo CRAM Mode) 0 0 0 111 x x x Normal (SRAM Mode) 0 1 0 x 1 0 0 PNAND Mode - Small Block Device 0 1 0 x 0 0 0 PNAND Mode - Large Block Device 0 1 0 x 1 1 0 PSPI Mode 0 1 0 x 1 0 1 ADM Mode EIM 0 The Debug mode is a helpful tool that works with the CyConsole and Cypress download utility to allow firmware download from USB. In the Debug mode, Astoria automatically enumerates when connected to a USB host and Cypress USB driver is installed. To install a driver: 1. Configure Astoria DVK board in Debug mode. 2. Connect a USB cable to the board and a USB host. Put J18 in ON position. 3. After the Hardware Update Wizard comes up, select Yes, this time only. 4. Select Install Hardware from <Install_Directory>:\Cypress\West Bridge Astoria\ <version>\USB Drivers depending on the operating system and architecture (32/64-bit). The device enumerates as “Cypress Astoria – DEBUG MODE PID=0x00A2”. West Bridge Astoria Development Kit Guide, Doc. # 001-47358 Rev. *D 9 Astoria Board Use the browser to find the folder containing cyusb.inf. It is available on the DVK CD in the USB Drivers folder. Select the INF file for the operating system platform being used. The wxp folder has the drivers for Windows-XP (32- and 64-bit); wlh-wv folder has the drivers for Windows-Vista (32and 64-bit); wlh-ws folder has the drivers for Windows-7 (32- and 64-bit). 2.1.5 EEPROM Boot Mode An additional features of Astoria is the ability to boot without the assistance of the processor, by loading its firmware from an EEPROM. The EEPROM boot mode cannot work if the processor voltage is set to 1.8 V. If J13 is in position 2-3, the EEPROM mode cannot function; therefore, set J13 in position 1-2. To program the EEPROM, route A[5] and A[6] to the I2C pins on the EEPROM, by switching SW5 to the OFF position. 2.1.5.1 EEPROM Firmware All tools and firmware required to program the EEPROM are included in the EEPROM directory of the DVK CD. 2.1.5.2 Flashing Procedure for EEPROM 1. Set P-port Interface to debug mode with EIM. The EIM selected has no impact on the EEPROM functionality, but EEPROM cannot function outside of EIM. See Table 2-4 on page 9. 2. Launch the CyConsole utility from <Install_Directory>:\Cypress\West Bridge Astoria\ <version>\EEPROM. 3. CyConsole uses the internal SIE to boot and enumerate in Debug mode. If EEPROM is preprogrammed with a boot code, the EEPROM booting must be disabled to allow SIE boot in Debug mode. To disable EEPROM boot, set SW5 to ON. 4. Power the DVK board and connect the USB cable to the host PC. Windows must recognize the Cypress USB device connection. CYConsole must show Astoria enumeration. If Astoria does not enumerate, then recheck all board settings. If the EEPROM is disconnected after enumeration, it can be reconnected now by switching SW5. 5. From the Options menu in CYConsole, select EZ USB Interface. 6. Press the LgEEPROM button. A file browser opens. 7. Navigate to the location of the .iic file (<Install_Directory>:\\Cypress\West Bridge Astoria\<version>\EEPROM). Select the file based on memory configuration. See S-port Memory Interfaces on page 10. Now, the board can be set to nondebug EIM, but this is not required. After the EEPROM is programmed, power cycle the board. When powering up, the Astoria now loads its firmware from the EEPROM. 2.1.6 S-port Memory Interfaces Astoria is designed to accept multiple types of memory configurations. The development kit supports most of the possible configurations. This section describes the memory configurations supported by the development board and how each memory configuration is implemented. 10 West Bridge Astoria Development Kit Guide, Doc. # 001-47358 Rev. *D Astoria Board There are two SD slots and two NAND sockets on the development board. The following table shows how the memory sockets are designated. Table 2-5. Memory Socket Designations Name SD1 SD2 Location Board label SD slot on the top of the board J2 SD slot on the bottom of the board J37 NAND1 a Closest NAND socket to the power switch U2 NAND2 a Closest NAND socket to the serial port U5 a. NAND flash sockets are unused because the Astoria firmware no longer supports the NAND flash memories. Three switch arrays are provided to separate the NAND bus and the SD Card bus. Because the NAND flash memories are no longer supported by Astoria firmware, these switches must always be in OFF position. The three switch arrays on the development board are labeled SW2, SW3, and SW7. The following table lists the switch array controls. Table 2-6. Switch Array Designation Switch Array SW2 SW3 SW7 Function Off Disconnects SD_IO[7:0] from NAND_IO[15:8] On Connects SD_IO[7:0] to NAND_IO[15:8] Off Disconnects NAND_SD2_IO[7:0] from NAND_IO[7:0] On Connects NAND_SD2_IO[7:0] to NAND_IO[7:0] Off Disconnects SD2 control from NAND control On Connects SD2 control to NAND control Relates SD1, NAND2 SD2, NAND1 SD2, NAND1, NAND2 The S-Port of the Astoria development kit supports the following memory interfaces. ■ Single SD/MMC ■ Dual SD/MMC ■ Single SD/MMC and GPIF ■ Single SD/MMC and GPIO ■ GPIF and GPIO Following is the demonstration of the first two types of memory configuration listed. For other memory interfaces, contact Cypress Support at http://www.cypress.com/support. 2.1.6.1 Single SD When implementing a single SD, use only J2. When running demo firmware, the card detection is done using SD_IO[3]. However, if running other firmware that use GPIO detection, J75 must be connected. To configure the board for single SD operation, turn off SW2. Firmware: cyastfw_sd_mmc_rel_nopport 2.1.6.2 Dual SD Use SD1 and SD2 when implementing the dual SD configuration. When you run firmware that uses GPIO card detection, connect J75 and J30. To configure the board for dual SD operation, turn off SW2, SW3, and SW7, and install a jumper on J29. Firmware: cyastfw_dual_sdio_sd_mmc_rel_nopport.hex West Bridge Astoria Development Kit Guide, Doc. # 001-47358 Rev. *D 11 Astoria Board 2.1.7 Astoria Processor Port The Astoria processor port is connected to J15, a Samtec QSH06001LDA connector, for interconnection with the controller. Samtec QTH06001LDA is the matting connector. See the Astoria datasheet for expected controller timing. J14 and J16 contain the entire processor port interface for interconnection and debugging purposes. Figure 2-3. J16 Debug Header Figure 2-4. J14 Debug Header 12 West Bridge Astoria Development Kit Guide, Doc. # 001-47358 Rev. *D Astoria Board Figure 2-5. J15 Processor Connector West Bridge Astoria Development Kit Guide, Doc. # 001-47358 Rev. *D 13 Astoria Board 2.1.8 Astoria Storage Port Figure 2-6. J16 NAND Debug Connector Figure 2-7. J3 SD Debug Connector 2.1.9 Reset Switch SW1 is the main reset circuit for Astoria. To reset the NAND or SD, recycle the board power. 14 West Bridge Astoria Development Kit Guide, Doc. # 001-47358 Rev. *D 3. Interconnection to Astoria Board The Astoria DVK hardware is designed to interconnect to a processor development platform. The optimal method to work with Astoria is to create a board with Astoria directly next to the processor. The interconnection scheme uses the DVK board with a small adapter board to bring the processor interface to a connector that matches the controller platform expansion connector. Flex cables can be used to connect the two boards. If there are no flex cables available to match the connector at the controller side, use two adapter boards for the interconnection. Cypress recommends using Samtec HFEM020T05.00-SE flex cables with the QSH06001LDA connector on one adapter board and the QTH06001LDA on the other adapter board. Interconnection causes signal integrity challenges. Cypress recommends simulating the interconnection topology before manufacturing the adapter boards. In most cases, adding termination resistors at the controller and selecting the correct termination value at Astoria can resolve reflections caused by mismatches. In some cases, buffering is required. To run the signal integrity (SI) simulation, Cypress provides: ■ Astoria IBIS model ■ Trace information for the Astoria development board To run the SI simulation, customers require: ■ Processor IBIS model ■ The I/Os type used for interconnection with Astoria ■ Trace information on the controller board The combination of these components can be used to simulate signal integrity. Simulation software, such as Hyperlynx from Mentor Graphics or SigXplorer from Cadence, can be used with the previous information to determine how to improve signal integrity. These tools provide pass/fail results to the simulation. In addition, the system designer must judge which scheme provides the optimal solution. To demonstrate the importance of this simulation, two example simulations are provided. One example is with termination and another without. In the first simulation, the waveform in black is the signal at the receiver side and blue is the transmitter side. As shown in Figure 3-1, there is minimal reflection and no glitches. In this simulation, proper termination resistors are used to arrive to this form. In the second simulation, shown in Figure 3-2, the same termination resistors are removed. The red waveform is the signal at the receiver. The reflection is much higher and there are glitches near the VIH level. This is an unacceptable waveform and can cause many system glitches. West Bridge Astoria Development Kit Guide, Doc. # 001-47358 Rev. *D 15 Interconnection to Astoria Board Figure 3-1. SI Simulation with Termination Figure 3-2. Simulation with no Termination 16 West Bridge Astoria Development Kit Guide, Doc. # 001-47358 Rev. *D 4. Diagnostics Module After implementing the hardware abstraction layer (HAL), ensure there is hardware access to Astoria. The primary goal of the diagnostics module is to test and verify HAL functionality and hardware connectivity for various interfaces of Astoria. This helps diagnose any problems that are identified. 4.1 Compiling Linux Diagnostics Module Compile the diagnostics source file that generates the diagnostics loadable kernel module. The testing must be bundled in this format for the tests to acquire access to the platform hardware. The HAL functions required to run the diagnostics module are described in Additional HAL Functions Required on page 21. Compilation can be done on the target platform or on a Linux PC using a cross-tool compiler. In Figure 4-1, the command make CYCONFIG=linux_kernel_debug CYHAL=platform_hal is used to execute the cross-tool compiler. In this case, linux_kernel_debug is the configuration used and platform_hal is replaced with omap_kernel to indicate the specific HAL implementation used. Figure 4-1 to Figure 4-4 uses the TI OMAP processor as an example. Figure 4-1. Compile Linux Diagnostics Module 4.1.1 Running the Linux Diagnostics Test Navigate to the directory where the diagnostics module is saved, usually (ASTORIA SDK ROOT)\sdk\drivers\diag\(CYCONFIG). In the following example, the directory is Astoria/ sdk/drivers/diag/linux_kernel_debug. Enter the Linux command klogd -c 8 to execute the klogd system daemon that intercepts and logs Linux kernel messages, allowing them to be printed to the console. Figure 4-2. Run Linux Diagnostics Test Enter the Linux command insmod cyasdiag_module.ko. This loads and runs the diagnostics module and displays the resulting messages to the console through the klogd daemon. Figure 4-3 West Bridge Astoria Development Kit Guide, Doc. # 001-47358 Rev. *D 17 Diagnostics Module and Figure 4-4 show an example of the diagnostics module output. Figure 4-3. Linux Diagnostics Output 18 West Bridge Astoria Development Kit Guide, Doc. # 001-47358 Rev. *D Diagnostics Module Figure 4-4. Linux Diagnostics Output (continued) 4.2 Test Description and Troubleshooting This section describes the basic tests performed in diagnostics and what it means if they fail. 4.2.1 Register Read and Write This test checks whether the CRAM control signals and address and data buses are correctly connected. The processor memory interface configuration and the memory range assigned to Astoria are also checked. This test is done by reading the silicon ID of the attached West Bridge chip and comparing it to the known, default value. It also writes and reads back several writable registers (mailboxes) on the attached chip to do additional verification of the data buses, and ensure that writes are succeeding. To troubleshoot these failures, it is usually necessary to monitor the P-Port interface using a logic analyzer. For example, if the memory range assigned to Astoria is incorrect, CS is not asserted. If the processor memory interface is incorrectly configured, the timing of the control signals being generated by the processor is incorrect. Possible error outputs: ■ ERROR: ADDR, DQ, CE, OE, ADV, or TEST pins are not correctly connected. The read values are: ❐ RESULT -> ERROR: exp 3, act ❐ RESULT -> ERROR: exp 2, act West Bridge Astoria Development Kit Guide, Doc. # 001-47358 Rev. *D 19 Diagnostics Module 4.2.2 ❐ RESULT -> ERROR: exp 1, act ❐ RESULT -> ERROR: WE not connected or DQ not fully connected Interrupt Testing This test checks if the INT# line is physically connected and if its assertion triggers the execution of an ISR. It is done by forcing the assertion of the interrupt signals through writing an override register within Astoria. The level of the INT line is pulled through an access similar to the GPIO before and after the forced assertion, to determine the presence of a physical connection. After this connection is verified, a diagnostics local ISR is registered and the module verifies that the assertion of the INT# line causes the execution of the ISR. Possible error outputs: 4.2.3 ■ RESULT -> ERROR: INT# is not connected or incorrectly mapped ■ RESULT -> ERROR: INT# did not fire processor ISR Firmware Download This test ensures that the DMA functionality of the HAL layer is correctly implemented. Firmware is downloaded through a series of DMA transactions. If the DMA handling for these transactions is not correct, the firmware download fails and outputs an error code. Possible error outputs: 4.2.4 ■ <1> CyAsDiag: Cannot Start Interrupt Monitor. Reason code: ■ <1> CyAsDiag: Cannot download the astoria firmware. Reason code: Storage Connectivity This test ensures that the applicable signals between Astoria and the attached storage are correctly connected. This is done by executing some basic storage queries through the Astoria API. Possible error outputs: 4.2.5 ■ <1>CyAsDiag: SD storage media was not found ■ <1>CyAsDiag: Nand storage media was not found Mailbox Loopback This test ensures that mailbox interactions between the processor and Astoria are reliable. To run this test, a custom firmware image is downloaded to Astoria that provides mailbox loopback functionality. 20 West Bridge Astoria Development Kit Guide, Doc. # 001-47358 Rev. *D Diagnostics Module A message is written by the processor through the diagnostics to the MCU Mailbox registers (F8FB), which is then read by the 8051 and written back to the P0 Mailbox registers (F0 -F3). This is again read by the processor and verified. Figure 4-5. Mailbox Loopback Diagram IN T F0 F1 F3 8051 P ro c e s s o r F2 M a ilb o x R e g is te r s IN T F8 F9 FA FB 4.3 Additional HAL Functions Required The diagnostics module relies on implementing a set of HAL functions in a specific way with a predefined naming convention. This can be changed, but the corresponding diagnostics test must also change accordingly. ■ int CyAnHalStart (CyAsHalDeviceTag *tag) - This function makes the call to start the HAL layer in a system agnostic fashion and passes back any necessary pointers. ■ int CyAnHalStop (CyAsHalDeviceTag *tag) - This function makes the call to stop the HAL layer system agnostic, so that a standard function can be called. ■ int CyAsHalGetIntVal(void) - Returns the current value of INT# signal using GPIO-like access. ■ int CyAsStartInterruptHandler(CyAsHalDeviceTag tag) - Registers standard HAL interrupt routines. ■ int CyAsHalDiagConfigInt(int asInterrupt,void *dev_p, CyAsInthandlers inthandler) - Allows local diagnostic ISR to be registered with the HAL. ■ int CyAsHalDiagReleaseInt(int asInterrupt,void *dev_p) - Releases the IRQs, unregisters the ISR. West Bridge Astoria Development Kit Guide, Doc. # 001-47358 Rev. *D 21 Diagnostics Module 22 West Bridge Astoria Development Kit Guide, Doc. # 001-47358 Rev. *D A. Appendix A.1 Schematic A.1.1 Board Overview 4 1 SD_D1 D9 SD_D2 E10 A0 SD_D3 E9 IN 1 2 3 4 1 K2 A1 SD_D4 F10 2 K3 A2 SD_D5 F9 J1 A3 SD_D6 G10 4 J3 A4 SD_D7 G9 5 H1 A5 SD_CLK F8 6 H2 A6 SD_CMD G8 7 H3 A7 SD_POW H8 SD_WP H10 NAND_IO0 J10 NAND_IO1 K10 NAND_IO2 H9 NAND_IO3 J9 NAND_IO4 K9 NAND_IO5 J8 NAND_IO6 K8 3 PVDDQ CTS 218-4LPST CTS218_8 10K 1 10K 1 4C6<> 4C3<> R59 2 R26 2 P_DQ<15..0> BI 0 1 1 1 2 1 3 1 4 1 5 1 6 R4 R6 R5 2 2 2 PROV PROV PROV 1 1 IN 4C6> IN 4D3< 1 10 1 11 1 12 1 13 1 14 1 15 1 P_INT_L P_DRQ_L OUT 4C3< 1 9 P_ADV_L P_OE_L P_WE_L IN 4C6> 1 8 1 R3 R1 2 2 2 1 PROV 7 PROV PROV 1 1 4C3> R2 PVDDQ 1 OUT P_DACK_L 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 R9 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 B2 DQ0 B1 DQ1 C3 DQ2 C2 DQ3 C1 DQ4 D3 DQ5 D2 DQ6 D1 DQ7 NAND_IO7 K7 E3 DQ8 E2 DQ9 NAND_CLE K6 E1 DQ10 NAND_ALE J6 F3 DQ11 NAND_CE# J5 F2 DQ12 NAND_RE# K4 F1 DQ13 NAND_WE# H6 G3 DQ14 NAND_WP# J7 NAND_R/B# J4 NAND_CLE_SD2_CLK NAND_ALE_SD2_CMD NAND_CE_L_SD2_POW NAND_RE_L NAND_WE_L NAND_WP_L NAND_RB_L NAND_CE2# K5 NAND_CE2_L_SD2_WP D+ A5 D- A6 G2 DQ15 A1 ADV# B3 OE# A2 WE# A3 INT# A4 DRQ B4 UVALID NC_VDD3 A7 A10 USB1_P USB1_N USB2_P 5D2<> 5D2<> BI 5D2<> BI 5D2<> BI 5D2<> BI BI OUT BI NAND_SD2_IO<0> NAND_SD2_IO<1> NAND_SD2_IO<2> NAND_SD2_IO<3> NAND_SD2_IO<4> NAND_SD2_IO<5> NAND_SD2_IO<6> NAND_SD2_IO<7> 5D2<> 5D2<> 5D7< 5D7<> OUT 5E8< IN 5C7> BI BI BI BI BI BI BI BI OUT OUT OUT OUT OUT OUT IN OUT BI 3F3<> BI 3F3<> BI 3D3<> NC_VDD3 5D2<> BI BI VCC_3_3 2 1 0 DACK VCC_1_8 R101 12PF 19.2 MHZ C2 2 HC49US 2 C1 7F8<> 5D1< OUT 4C6<> 4C3<> BI 4C6<> 4C3<> BI IN B10 RESETOUT D8 GPI0 C9 GPI1 C7 C6 TEST0 D7 TEST1 C8 TEST2 E8 2 NANDCFG USB2_N BI 10K RESET_N R94 XTALOUT 3D3<> 1 XTALIN B8 R93 A8 C10 C5 2 IN C4 XTALSLC1 10K 12PF 4D3> XTALSLC0 GND 1 1 1 2 CONFIG XTALOUT RESETIN RESETOUT GPIO<0> GPIO<1> WAKEUP Y1 1 OTHERS 1 IN 22 BI 2 3 5 CE# K1 PROV P_CE_L P_ADDR<7..0> SD_IO<0> SD_IO<1> SD_IO<2> SD_IO<3> SD_IO<4> SD_IO<5> SD_IO<6> SD_IO<7> SD_CLK SD_CMD SD_POW SD_WP R95 6 SD_D0 G1 0 IN IN S PORT 1 2 CLK D10 J2 U PORT SMT POS-4 7 R10 10K 4C3<> CLK P PORT GND 8 CYWB01AB 1 R37 R60 R61 2 10K 4C6> SW4 8 7 6 5 LENGTH <= 1.94 IINCHS U1 GND 1 2 2 2 10K 10K 10K 1 1 R58 PVDDQ 1 PROV 2 2 R8 PVDDQ WAKEUP VCC_1_8 GND R99 10K 2 GND 1 R92 2 10K 1 R91 R90 2 2 10K 10K 1 1 1 10K 2 R77 GND SW6 8 7 6 5 GND 8 SMT POS-4 1 7 2 6 3 5 4 1 2 3 4 CTS 218-4LPST CTS218_8 West Bridge Astoria Development Kit Guide, Doc. # 001-47358 Rev. *D 23 VCC_3_3D VCC_1_8D VCC_3_3D VCC_1_8D PVDDQ U1 CYWB01AB 16E1> 6D8> 5A8<> D12 GPIO<0> IN 2 3B1< 5F3< 4.99K 16C8< PVDDQ[1..0] J12 SNVDDQ D6 GVDDQ B9 AVDDQ B7 XVDDQ B5 UVDDQ 2 2 3 A9 4D4< 3E4< 3B3< 6E8> 2 SOD-523 SD_WP IN GND 1 1 BI 2C3<> BI USB1_N USB1_P D13 1 R44 1 2 2 1 FERRITE GND LN1 2C3<> diode_pgb0603 10K AVSSQ 2 2 B6 DIODE 1 2 3 1 2 UVSSQ 2 SSVDDQ H5 1 1 HEADER3 VGND[6..0] H7 diode_pgb0603 1 R43 D1 VDD[5..0] GND RN65 2 1 CN78 1 VCC_1_8D 1 1M GND 1 GND 4 2 VCC_3_3D 2 VCC_3_3D 1 2 HEADER2 J55 VCC_1_8D GND CN51 2 TP1 1 2 1 2 1 1 HEADER2 R96 TP2 2 2 VCC_1_8D VCC_1_8 0.1UF 0.1UF HEADER_1 1 1 J56 HEADER_1 3 CN60 CN59 2 1 2 1 1 0.1UF 2 2 VCC_2_5D J13 1 2 3 2 CN58 2 2 2 1 CN57 0.1UF 2 1 2 0.1UF VCC_1_8D HEADER3 1 1 CN56 VCC_3_3D 0.02UF 0.02UF 2 2 0.1UF CN54 CN53 0.02UF 2 2 2 1 CN55 1 1 CN52 0.02UF 2 1 2 1 1 1 0.02UF 2 2 1 1 CN50 0.02UF 1 2 CN49 1 1 1 1 1 PVDDQ 1 1 1 2C3<> BI 2C3<> BI USB2_N USB2_P TP3 2 1 1 HEADER_1 VCC_1_8D RN66 2 1 CN79 VCC_3_3D VCC_3_3 1 CN61 1 2 1 1 2 1 1 HEADER_1 1 1 CN76 2 2 2 1 CN64 CN77 2.2UF 0.1UF 2 1 CN62 0.1UF GND 1 CN74 2 1 2 2 1 0.02UF 1 1 VCC_3_3D 2 2 1 HEADER_1 GND CN63 0.02UF 0.02UF TP5 1 1 1 1 GN 4.7 NF 2 2 1M 1 R97 TP4 VCC_3_3D PVDDQ 0.1UF 2 1 CN72 CN70 R98 TP6 0.1UF 0.02UF 2 2 2 1 0.1UF 0.02UF 1 1 CN68 HEADER_1 1 1 1 1 2 2 2 CN66 1 1 GND 2 1 2 2 2 1 VCC_2_5 2 GND GND 1 CN71 CN69 CN73 CN75 0.1UF 2 2 2 GND 1 0.02UF 0.1UF 0.02UF 2 1 1 1 1 2 CN67 0.1UF 2 2 2 1 2 CN65 0.02UF 2 PVDDQ 2 1 2 1 1 VCC_3_3D 1 1 VCC_3_3D DRAWING TITLE GND GND GND CYPRESS SEMICONDUCTOR THIS DOCUMENT CONTAINS INFORMATION PROPRIETARY 24 ASTORIA SIZE C C REV. *.* West Bridge Astoria Development Kit Guide, Doc. # 001-47358 Rev. *D PVDDQ PVDDQ J15 CLK IN 1 1 2 2 P_DQ<0> P_DQ<3> 3 3 4 4 P_DQ<2> P_DQ<5> 5 5 6 6 P_DQ<4> P_DQ<7> 7 7 8 8 P_DQ<6> P_DQ<9> 9 10 10 P_DQ<8> P_DQ<11> 11 11 12 12 P_DQ<10> P_DQ<13> 13 13 14 14 P_DQ<12> P_DQ<15> 15 15 16 16 P_DQ<14> 17 17 18 18 19 19 20 20 9 HEADER_2X10 2C7< 2C7< OUT OUT P_OE_L P_WE_L 2F7< 2E7<> OUT BI P_CE_L P_DQ<0> 2E7<> 2E7<> BI BI P_DQ<1> P_DQ<2> 2E7<> 2E7<> BI BI P_DQ<3> P_DQ<4> 2E7<> 2E7<> BI BI P_DQ<5> P_DQ<6> 2E7<> 2E7<> BI BI P_DQ<7> P_DQ<12> 2E7<> 2E7<> BI BI 2E7<> BI P_DQ<13> P_DQ<14> P_DQ<15> QSH06001LDA 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 RESETIN P_INT_L OUT IN 2C7< 2C7> P_DACK_L P_DRQ_L OUT IN 2C7> P_ADV_L OUT 2D7< P_ADDR<0> P_ADDR<1> BI BI 2E7< 2E7< P_ADDR<2> P_ADDR<3> BI BI 2E7< 2E7< P_ADDR<4> P_ADDR_S<5> BI BI 4B4< 4B4< P_ADDR_S<6> P_ADDR<7> BI BI 2E7< 2E7< P_DQ<8> P_DQ<9> BI BI 2E7<> 2E7<> P_DQ<10> P_DQ<11> BI BI 2E7<> 2E7<> J16 RESETIN 1 1 2 2 P_INT_L P_DACK_L P_DRQ_L 3 3 4 4 P_ADV_L 5 5 6 6 P_ADDR<0> P_ADDR<1> 7 7 8 8 P_ADDR<2> P_ADDR<3> 9 9 10 10 P_ADDR<4> P_ADDR<6> P_ADDR<5> 11 11 12 12 P_ADDR<7> 13 13 14 14 WAKEUP 15 15 16 16 CLK P_OE_L 17 17 18 18 P_WE_L P_CE_L 19 19 20 20 HEADER_2X10 121 122 123 124 125 126 127 128 VBUS 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 122 123 124 125 126 127 128 WAKEUP IN J14 P_DQ<1> 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 GND PVDDQ TP8 WP 2 SW5 2K I2C_SDA I2C_SCL IN IN 4B4< 4B4< R82 4E3> IN 4B5< 4E3> IN IN 4B5< IN P_ADDR_S<5> I2C_SCL P_ADDR_S<6> I2C_SDA 1 1 3 4 3 6 6 4 2 2 P_ADDR<5> OUT 3E7< 5 5 P_ADDR<6> OUT 3E7< CAS-220TB R83 0 10K 1 A2 5 6 7 1 SCL GND SDA 4 10K HEADER_1 2 24AA256 A0 A1 2 2 1 VCC R81 1 2 3 1 R80 8 U9 2K 10K R78 2 2 1 R79 1 1 1 TP9 1 1 HEADER_1 GND West Bridge Astoria Development Kit Guide, Doc. # 001-47358 Rev. *D 25 TP10 VCC_3_3 C3 1 1 C5 C4 0.1UF 1 1 1 1 1 1 HEADER_1 1 + 0.02UF 0.1UF 1 C6 GND VCC_3_3 10UF VCC_3_3 R36 R35 R7 2 10K 1 R34 2 2 2 10K 10K R30 R32 R31 2 2 10K 10K 1 1 1 SD_IO<7..0> SD+MMC+MMC4.0 CONN WP_SW 2 CD_SW GPIO<0> OUT HEADER2 1 2 3 DAT2 15 DAT3 14 DAT4 13 DAT5 11 DAT6 7 DAT7 5 SD_IO<0> SD_IO<1> SD_IO<2> SD_IO<3> SD_IO<4> SD_IO<5> SD_IO<6> SD_IO<7> 2E3<> BI 2F3<> 0 1 2 J3 3 SD_IO<0> SD_IO<2> SD_IO<4> SD_IO<6> SD_CMD SD_POW GPIO<0> GPIO<1> 4 5 6 7 101-00565-64 1 J75 4 2 1 DAT0 DAT1 470K CLK R33 2C6> 1 SD_WP OUT CMD 8 VSS1 VSS2 GND0 GND1 2D2< VDD 12 GND2 GND3 IN 2E3< J2 SD_CMD SD_CLK BI 2E3> 10 6 16 17 18 19 2E3<> 1 1 9 1 1 10K 2 10K 2 R29 R28 1K 10K R27 2 GND 2 VCC_3_3 10K 2 2 2 1 2 2 2 2 2 GND 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 SD_IO<1> SD_IO<3> SD_IO<5> SD_IO<7> SD_CLK SD_WP RESETOUT IN 2E6< 7F8<> HEADER_2X8 GND C36 1 1 C38 C37 0.1UF 1 1 1 1 1 VCC_3_3 0.1UF 1 + 0.02UF C39 VCC_3_3 10UF VCC_3_3 R71 R67 R68 R70 2 2 10K 1 1 2 2 R66 R69 10K 10K 10K 1 1 2 2 2 10K 10K 10K 1 NAND_SD2_IO<7..0> VDD CLK HEADER2 1 2 J29 1 2D2< 2C6> OUT GPIO<1> 2 HEADER2 1 2 CD_SW 4 DAT1 3 DAT2 15 DAT3 14 DAT4 13 DAT5 11 DAT6 7 DAT7 5 NAND_SD2_IO<0> NAND_SD2_IO<1> NAND_SD2_IO<2> NAND_SD2_IO<3> NAND_SD2_IO<4> NAND_SD2_IO<5> NAND_SD2_IO<6> NAND_SD2_IO<7> 101-00565-64 2E3<> 2F3<> 2 J6 3 4 5 6 7 GND GND 26 BI 0 1 1 10 6 16 17 18 19 J30 WP_SW DAT0 2 CMD 470K 8 R72 IN OUT J37 12 SD+MMC+MMC4.0 CONN 2E3< NAND_ALE_SD2_CMD NAND_CLE_SD2_CLK NAND_CE2_L_SD2_WP VSS1 VSS2 GND0 GND1 2E3> BI GND2 GND3 2E3<> 1 1 9 1 2 R63 1K 10K R62 2 1 GND 1 R64 10K 2 VCC_3_3 R65 2 2 2 2 2 2 2 2 2D3> IN 2D3> IN NAND_SD2_IO<0> 1 NAND_SD2_IO<2> 3 NAND_SD2_IO<4> 5 NAND_SD2_IO<6> 7 NAND_ALE_SD2_CMD9 11 NAND_CE_L_SD2_POW NAND_RE_L 13 NAND_WP_L 15 NAND_SD2_IO<1> NAND_SD2_IO<3> NAND_SD2_IO<5> 8NAND_SD2_IO<7> NAND_CLE_SD2_CLK 10 12 NAND_CE2_L_SD2_WP NAND_RB_L 14 NAND_WE_L 16 1 2 2 3 4 4 5 6 6 7 8 9 10 11 12 13 14 15 16 OUT IN 2D3> 2D2< 2D3< HEADER_2X8 West Bridge Astoria Development Kit Guide, Doc. # 001-47358 Rev. *D 1 1 VCC5 D11 2 2 2 VCC_1_8 LM317M R55 2 2 1 INPUT 1 HEADER_1 FMMT3904 C28 4 TAB 1UF + LED 0.1UF 1% 2 2 1 2 ADJUST GND D7 R48 GND 1 3 R45 2 1 121 2 2 2 1UF C34 TANTALUM 2 1 1 C26 2 TP11 1 Q3 D2 110 R57 1 2 1 1 1K 1 1 OUTPUT VCC_1_8 31 U6 VCC5 1 100 VCC5 LED_1206 GREEN +5V 2 LED GREEN LED_1206 D4 1 GND GND 1 1% 2 GND 1 53.6 R50 1UF C31 VCC5 1 2 2 VCC_3_3 1 2 U7 VCC5 3 2 VBUS IN 1 D5 1 100 9C2> D10 GREEN LED_1206 2 LM317 R54 1K 1 2 OUTPUT 1 2 VCC_3_3 Q2 TP12 1 GND 1 2 3 LED 3 HEADER3 1 2 3 GND GND 2 J78 1 R56 3 3 VCC5_POWER 1 1 31 2 2 1 J18 VCC5_MAIN spdt_switch PJ-002AH VCC5 2 POWER JACK 2.1MM/5.5MM INPUT SUPPLY: 0-5.5V J17 INPUT FMMT3904 1 2 1 C29 0.1UF 4 TAB 1UF + 1 2 ADJUST D8 1 121 R49 GND 3 2 TO261 HEADER_1 GND 2 TANTALUM 2 1 1UF C35 2 C27 1% 2 1 1 TP13 GND + 1 33UF + 1UF C32 33UF 1 1 HEADER_1 VCC5 1 33UF HEADER_1 1 200 + 1 1 1 33UF 1 TP14 R51 + 1 DISTRIBUTE AROUND BOARD AREA GND 1% 2 BULK DECOUPLING 1 VCC5 C22 TANTALUM 1 TANTALUM 2 2 2 C20 TANTALUM 2 C19 TANTALUM 2 C18 D9 GND VCC_2_5 GREEN LED_1206 GND 2 2 U4 R53 VCC5 100 2 1 2 GND D3 GND LED DISTRIBUTE AROUND BOARD AREA 31 VCC_2_5 LM317M R52 1 2 1K 2 TP15 1 Q1 1 1 OUTPUT INPUT 1 HEADER_1 FMMT3904 1 + 0.1UF TAB 1UF 4 TANTALUM 2 ADJUST GND D6 R46 2 GND 3 1 121 2 2 1UF C33 2 C24 C25 1 1 1% 2 1 2 1 1% 2 GND 1 GND 121 R47 1UF DRAWING TITLE 1 C30 2 CYPRESS SEMICONDUCTOR GND GND THIS DOCUMENT CONTAINS INFORMATION PROPRIETARY TO CYPRESS SEMICONDUCTOR. USE OR DISCLOSURE WITHOUT THE WRITTEN PERMISSION OF AN OFFICER OF CYPRESS IS EXPRESSLY FORBIDDEN. West Bridge Astoria Development Kit Guide, Doc. # 001-47358 Rev. *D ASTORIA DVK BOARD SIZE C C ENGINEER REV. *.* Thu Nov 24 14:39:55 DATE. <ENGINEER> <ENGINEER2> PAGE 6 2011 OF 9 27 VCC_3_3 VCC_3_3 VCC_3_3 VCC_3_3 VCC_3_3 VCC_3_3 10K 2 HEADER2 9E5> 4B6> 1 10K NC_1 NC_48 48 2 NC_2 NC_47 47 3 NC_3 NC_46 46 4 NC_4 NC_45 45 5 NC_5 I/O_7 44 6 NC_GND_RB2_6 I/O_6 43 7 R/B_L I/O_5 42 8 RE_L 9 CE_L NAND_RB_L NAND_RE_L OUT IN 10 8B8< 3B6< 9E5> 4B6> NAND_CE2_L IN 1 C7 1 1 1 1 C8 1 C10 C9 0.1UF 0.02UF 0.1UF 0.02UF 8B7< 3B6< 9D7> 4B6> IN 8B7< 3B6< 9D7> 4B6> IN 8B7< 3B6< 9E5> 3D4> IN 8B7< 3B6< 9E5> 3D4> IN NAND_CLE NAND_ALE NAND_WE_L NAND_WP_L NC_CE2_10 11 NC_11 12 NAND_8_BIT I/O_4 41 NC_40 40 NC_39 39 NC_PRE_38 38 NAND_IO<7> NAND_IO<6> NAND_IO<5> NAND_IO<4> BI 4B6<> 9E4<> 9E7<> 3B8< BI 4C6<> 9E4<> 9E7<> 3B8< BI 4C6<> 9E4<> 9E7<> 3A8< BI 4C6<> 9E7<> 9F4<> 3A8< 2 2 2 2 2 2 2 1 9E5> 8C6> 3C1< 3B6< 9E5> 3D4> 8C6< 3B6< NAND_CE_L IN 1 2 10K 10K 3B6< R39 1 1 8C8< R40 2 R38 2 1 2 1 U2 R41 J7 VCC_3_3 1 2 RESETOUT BI GND GND 37 VCC_12 VCC_37 13 VSS_13 VSS_36 36 14 NC_14 NC_35 35 15 NC_15 NC_34 34 16 CLE NC_33 33 17 ALE I/O_3 32 18 WE_L I/O_2 31 19 WP_L I/O_1 30 20 NC_20 I/O_0 29 21 NC_21 NC_28 28 22 NC_22 NC_27 27 23 NC_23 NC_26 26 24 NC_24 NC_25 25 GND GND NAND_IO<3> NAND_IO<2> NAND_IO<1> NAND_IO<0> 4C6<> 9E7<> BI 4C6<> 9E7<> BI 4D6<> 9E7<> BI 4D6<> 9E7<> BI 9F4<> 3A8< 9F4<> 3A8< 9F4<> 3A8< 9F4<> 3A8< GND VCC_3_3 VCC_3_3 VCC_3_3 VCC_3_3 VCC_3_3 VCC_3_3 2 9E5> 3C1< 8C6> 3B6< OUT 8B8< 3B6< 3B6< 9E5> 9E5> 4B6> 4B6> IN IN 46 NC_45 45 1 9E5> NAND_CE_L IN NAND_RE_L NAND_CE2_L 8B7< 3B6< 9D7> 4B6> IN 8B7< 3B6< 9D7> 4B6> IN 8B7< 3B6< 9E5> 3D4> IN 8B7< 3B6< 9E5> 3D4> IN NAND_CLE NAND_ALE NAND_WE_L NAND_WP_L NC_5 I/O_7 44 6 NC_GND_RB2_6 I/O_6 43 7 R/B_L I/O_5 42 8 RE_L I/O_4 41 9 CE_L NC_40 40 NC_39 39 NC_PRE_38 38 10 NC_CE2_10 11 NC_11 12 VCC_12 VCC_37 37 13 VSS_13 VSS_36 36 14 NC_14 NC_35 35 15 NC_15 NC_34 34 16 CLE NC_33 33 17 ALE I/O_3 32 18 WE_L I/O_2 31 19 WP_L I/O_1 30 20 NC_20 I/O_0 29 21 NC_21 NC_28 28 22 NC_22 NC_27 27 23 NC_23 NC_26 26 24 NC_24 NC_25 25 NAND_8_BIT NAND_IO<15> NAND_IO<14> NAND_IO<13> NAND_IO<12> 2 1 3D4> 8C6< 5 1 C40 4B6<> 9E4<> 9E7<> 3B8< 4C6<> 9E4<> 9E7<> 3B8< BI 4C6<> 9E4<> 9E7<> 3A8< BI 4C6<> 9E7<> 9F4<> 3A8< BI BI 1 C41 1 C43 C42 0.1UF 0.02UF 0.1UF 0.02UF 2 2 1 47 NC_46 NC_4 2 2 GND 2 48 NC_47 NC_3 4 1 NC_48 NC_2 3 1 NC_1 2 2 1 10K 1 2 10K NAND_RB_L 3B6< 8C8< R75 1 1 10K R73 2 1 2 R74 2 10K J31 HEADER2 1 U5 R76 VCC_3_3 2 BI RESETOUT GND GND NAND_IO<11> NAND_IO<10> NAND_IO<9> NAND_IO<8> 9E7<> 9F4<> 3A8< BI 4C6<> 9E7<> 9F4<> 3A8< BI 4D6<> 9E7<> 9F4<> 3A8< BI 4D6<> 9E7<> 9F4<> 3A8< BI 4C6<> DRAWING TITLE GND GND CYPRESS SEMICONDUCTOR THIS DOCUMENT CONTAINS INFORMATION PROPRIETARY 28 ASTORIA DVK BOARD SIZE C C REV. *.* Thu Nov 24 14:39:55 DATE. 2011 West Bridge Astoria Development Kit Guide, Doc. # 001-47358 Rev. *D 1 VCC_1_8 0.1UF VCC_1_8 10K 4 2 2 C46 R42 1 MR* 2 1 GND VCC 3 1 RESET* PB_SWITCH ON/OFF 0.1UF C13 5A3< OUT MAX6386XS17D3-T 2 2 2 GND GND 1 GND 0.1UF C12 RESETIN 15 1 0.02UF C14 2 2 2 MAX6386 1 0.1UF C11 2 GND 1 I24 1 U12 1 SW1 1 1 VCC_1_8 C1+ 4 C1- 5 C2+ V+ 3 V- 7 1 2 2 VCC 2 1 U3 1 1 0.1UF GPIO<0> GPIO<1> 2 2 2 J9 11 T1OUT TIN 9 R1OUT 1 EN#* R1IN GND 13 GND 8 VCC_1_8 J10 16 FORCEOFF* 12 FORCEON INVALID* RS232_TX_OUT 10 J11 1 2 3 4 5 6 7 8 9 14 WRT TO ANTIOCH MAX3221 RS232_RX_IN 1 2 3 4 5 6 7 DB9_CONN IN OUT C2- 2 GND TX RX 6 11 22 5A8<> 3B1< 5A8<> HEADER2 16E1> 6D8> 9C5< 5F3< 5F3< 3B1< 16D1> 7C7> HEADER2 C16 0.1UF C15 8 10 9 11 10 11 GND GND_EARTH GND SW2 NAND_IO<8> NAND_IO<9> NAND_IO<10> NAND_IO<11> NAND_IO<12> NAND_IO<13> NAND_IO<14> NAND_IO<15> BI BI BI BI BI BI BI BI 1 1 16 16 2 2 15 15 3 3 14 14 4 4 13 13 SMT POS-8 5 5 12 12 6 6 11 11 7 7 10 10 8 8 9 9 SD_IO<0> SD_IO<1> SD_IO<2> SD_IO<3> SD_IO<4> SD_IO<5> SD_IO<6> SD_IO<7> BI BI BI BI BI BI BI BI CTS 218-8LPST CTS218_16 SW3 NAND_IO<0> NAND_IO<1> NAND_IO<2> NAND_IO<3> NAND_IO<4> NAND_IO<5> NAND_IO<6> NAND_IO<7> OUT OUT OUT OUT BI BI BI BI 1 1 16 16 2 2 15 15 3 3 14 14 4 4 13 13 SMT POS-8 5 5 12 12 6 6 11 11 7 7 10 10 8 8 9 9 NAND_SD2_IO<0> NAND_SD2_IO<1> NAND_SD2_IO<2> NAND_SD2_IO<3> NAND_SD2_IO<4> NAND_SD2_IO<5> NAND_SD2_IO<6> NAND_SD2_IO<7> OUT BI OUT IN BI BI BI BI CTS 218_8LPST CTS218_16 BI BI BI BI NAND_CLE NAND_ALE NAND_CE_L NAND_CE2_L SW7 8 7 6 5 8 SMT POS-4 1 7 2 6 3 5 4 CTS 218-4LPST CTS218_8 1 2 3 4 NAND_CLE_SD2_CLK NAND_ALE_SD2_CMD NAND_CE_L_SD2_POW NAND_CE2_L_SD2_WP West Bridge Astoria Development Kit Guide, Doc. # 001-47358 Rev. *D BI BI BI BI 29 A.2 Board Layouts Figure A-1. Top View 30 West Bridge Astoria Development Kit Guide, Doc. # 001-47358 Rev. *D Figure A-2. Bottom View West Bridge Astoria Development Kit Guide, Doc. # 001-47358 Rev. *D 31 A.3 Bill of Materials (BOM) Sl.No. Qty. Reference Description Manufacturer Manufacturer Part No. 21 C5,C7,C9,C14,C38,C40, C42,CN49, CN54, CN61, Capacitor, 10nF, 10%, 16V, ceramic, AVX CN63,CN65,CN66, CN69, X7R, SMD 0402 CN70,CN73, CN74 0402YC103KAT 2 31 C3,C4,C8,C10, C13, C15, C16,C24,C26,C27,C36,C 37,C41,C43,C46,CN55, Capacitor, 0.1uF, 10%, 10V, ceramic, AVX CN60, CN62,CN64,CN67, X5R, SMD 0402 CN68,CN71,CN72,CN75, CN76 0402ZD104KAT 3 2 C6,C39 Capacitor, 10uF, 16V, 20%,electrolytic, SMD Panasonic EEV-FK1C100R 4 6 D3-D8 Diode General Purpose 100V 1A DO41 Fairchild 1N4002 5 6 C30-C35 Capacitor, 1uF, 10%, 50V, ceramic, X7R, SMD 1210 AVX 12105C105KAT 6 3 C25,C28,C29 Capacitor, 1uF, Tantalum, 20V 10% 1206 SMD Kemet T491A105K020AS 7 1 U9 Socket, 8Pin, MS TIN/TIN .300 Mill-Max 110-99-308-41-001000 8 1 CN77 Capacitor, 2.2uF, 10%, 25V, ceramic, AVX X7R, SMD 1210 12103C225KAT 9 4 C18, C20,C22 Capacitor, 33uF, 20%, 10V, Tantalum, Kemet 1311 SMD, low ESR T520B336M010ASE070 10 1 JN1 Connector, USB Receptacle, Type B Amp/Tyco PCB 787780-1 11 2 C1,C2 Capacitor, 12pf, 50V COG 5% 0402 SMD TDK Corporation C1005C0G1H120J 12 1 SW5 SLIDE SWITCH DPDT GULLWING, SMT Copal ElectronCAS-220TB ics 13 1 Y1 CRYSTAL 12.5PF 24.00MHZ 50/ 50PPM -40-85C, SMD Gentech Crystals GCE-SMD-HC/49US-A-112.5-24.00MHZ-EXT-50/ 50PPM 14 1 U1 CYWB01AB_Socket, VFBGA_100 - - 15 1 J11 Connector, DB9, Female .318" RA Met Shell Norcomp Inc. 182-009-212-181 16 1 D1 DIODE SCHOTTKY 40V 150MW SOD-523 Diodes IncorpoSDM03U40 rated 17 2 D12,D13 SUPPRESSOR ESD 24VDC 0603 SMD LITTLE FUSE PGB0010603MR 18 2 SW2,SW3 Switch, DIP, 8 position, half size, SMD CTS Corporation 218-8LPST 1 32 West Bridge Astoria Development Kit Guide, Doc. # 001-47358 Rev. *D Sl.No. Qty. Reference Description Manufacturer Manufacturer Part No. 20 2 CN78,CN79 Capacitor, 4.7NF 250VAC Ceramic SMD Panasonic ECK-TBC472MF 21 1 LN1 Ferrite bead, 100 ohm, 3A, SMD 1206 Laird-Signal HI1206N101R-00 22 3 Q1-Q3 TRANS GP NPN 40V 200MA SOT23Zetex 3 FMMT3904TA 23 9 J7,J9,J10,J29, J31, J55, J56,J75 Header, 2-pos, 0.100" Sullins PTC36SAAN 24 3 J12,J13,J78 Header, 3-pos, 0.100" Sullins PTC36SAAN 25 2 J14,J16 - - - 26 2 J3,J6 - - - 27 4 D2,D9-D11 LED 565NM GREEN DIFF 1206 SMD Lumex SML-LX1206GW-TR 28 1 U7 3-Terminal Adjustable Regulator, DCY Package, SOT-223-4 Texas Instruments LM317MDCY 29 2 U4,U6 3-Terminal Adjustable Regulator, DCY Package , SOT-223-4 Texas Instruments LM317MDCY 30 1 U3 IC, RS232 Transceiver, 16-SSOP, SMD,120KBPS Maxim MAX3221CAE 31 1 U12 IC, single supply supervisor, O/D reset_n, 1.67V, 140mS, SMD Maxim MAX6386XS17D3-T 32 2 U2,U5 Socket, TSOP 48 Position, w/Alignment Pins, SMD Emulation TechS-TSO-SM-048-A nology 33 1 SW1 Switch, Pushbutton, RA PCB mount, C&K SPST-NO 0.4VA 20V TP11SH8ABE 34 1 J17 Connector, Power Jack 2.1 mm x 5.5 CUI Inc mm High Current PJ-002AH 35 1 J15 QSH Series, 120 positions connector, Samtec SMD QSH-060-01-L-D-A-K-TR 36 8 R1-R6,R10,R95 - - - 37 2 R83,R101 Resistor, 0.0 (ZERO) ohm, 1/10W, 0402 SMD Panasonic ERJ-2GE0R00X 38 16 R9,R11-R25 Resistor, 22 OHM, 1/10W, 5%, 0402 Panasonic SMD ERJ-2GEJ220X 39 44 R7,R8,R26,R27,R29, R32,R34-R42,R58, R62, R64-R71,R73, R78,R81, R82,R90-R94,R99 Resistor, 10K ohm, 1/10W, 5%, 0402 Panasonic SMD ERJ-2GEJ103X 40 5 R28,R52,R54,R55,R63 Resistor, 1.0K ohm, 1/10W, 5%, 0402 Panasonic SMD ERJ-2GEJ102X 41 2 R33,R72 Resistor, 470K ohm, 1/16W, 5%, 0402 SMD West Bridge Astoria Development Kit Guide, Doc. # 001-47358 Rev. *D Yageo America 9C04021A4703JLHF3 33 Sl.No. Qty. Reference Description Manufacturer Manufacturer Part No. 42 1 R45 Resistor, 110 ohm, 1/10W, 5%, 0402 Panasonic SMD ERJ-2GEJ111X 43 3 R53,R56,R57 Resistor, 100 ohm, 1/10W, 5%, 0402 Panasonic SMD ERJ-2GEJ101X 44 2 R79,R80 Resistor, 2.0K OHM, 1/10W, 5%, 0402 SMD ERJ-2GEJ202X 45 1 R43 Resistor, 4.99KOhm, 1/8W, 1%, 0805 Rohm SMD MCR10EZHF4991 46 1 R44 Resistor, 10KOhm, 1/8W, 5%, 0805 SMD CRCW080510K0JNEA 47 2 RN65,RN66 Resistor, 1 Meg, 1/8W 5% 0805 SMD Panasonic 48 3 R96-R98 Resistor, 1ohm, 1/4W, 1%, 1206 SMD Yageo America RC1206FR-071RL 49 4 R46-R49 Resistor, 121 OHM, 1/10W, 1%, 0402 Panasonic SMD ERJ-2RKF1210X 50 1 R50 Resistor, 53.6 ohm, 1/10W, 1%, 0402 Panasonic SMD ERJ-2RKF53R6X 51 1 R51 Resistor, 200 ohm, 1/10W, 1%, 0402 Panasonic SMD ERJ-2RKF2000X 52 2 J2,J37 CONN SD/MMC/MMC 15POS PCB GOLD Amphenol 101-00565-64 53 1 J18 Switch, Slide Miniature SPDT, OnNone-On C&K 1101M2S3CQE2 54 3 SW4,SW6,SW7 Switch, DIP, 4 position, half size, SMD CTS Corporation 218-4LPST 55 11 TP1-TP7,TP10,TP13TP15 - - - 56 2 TP11,TP12 - - - 57 2 TP8,TP9 - - - 58 1 JN2 1010BLF USB S/D RECEPT LF FCI 87520-1010BLF 59 1 Astoria DVK Board - Pactron 305-PD-11-0748 34 Panasonic Vishay/Dale ERJ-6GEYJ105V West Bridge Astoria Development Kit Guide, Doc. # 001-47358 Rev. *D