ATMEL T7906E

Features
• Besides the serial IEEE-1355 link, the T7906E provides several different interface
types:
– Host interface
The host interface provides 8 multiplexed data and address lines to program
and control the T7906E locally
– FIFO interface
The FIFO interface provides the control signals FULL, WRITE, EMPTY and READ
depending on the direction of the data flow (receive / transmit)
– ADC interface
The ADC interface allows to connect an ADC with a width of up to 16 bits directly
to the T7906E
– DAC interface
The DAC interface provides up to 16 bits data lines and the required control
signals. The data to be sent to the DAC are stored until a command “start DAC”
is received
– RAM interface
The RAM interface provides a 16-bit data bus and a 16-bit address bus. Four
chip select allow to address 4 different memory partitions. The memory interface
can be programmed to use up to 7 wait states
– UART interface
Two independent UART interfaces are included. One UART uses dedicated I/O
lines whereas the second UART is sharing its pins with the GPIO port
– General purpose I/O
This general Purpose Interface provides up to 24 bidirectional signal lines. The
direction of each GPIO line can be set individually via register
– Timer / Event Counter
Two 32-Bit on-chip timers are available. Each timer provides a 32-Bit counter
and a 32-Bit reload register. The two timers can be operated independently or
cascaded
– JTAG (IEEE 1149.1)
For testing purposes, a standard IEEE 1149.1 interface is provided. It supports
the JTAG function Bypass, Extest, Sample/preload, All-tristate and IDCode
• Designed on Atmel MG1090E sea of gates matrix and packaged into MQFPF100
• Also called SMCS Lite (or SMCS116)
Single Point to
Point IEEE 1355
High Speed
Controller
T7906E
Description
The T7906E provides one IEEE-1355 serial communication link with 0 to 200 Mbit/s
data transmit rate. It supports both the standard IEEE-1355 link protocol (transparent
mode) as well as the header generation required for the enhanced transaction layer of
the TSS901E. This protocol uses specific protocol headers that can be generated by
the T7906E without requiring an external host controller. These headers are stored in
specific header registers which allows headers with a length of 0 (equaling the transparent mode) to eight bytes per packet. Packetization of data sent by the T7906E over
the link is also done automatically according to the settings of a packet length register.
Another feature provided by the transaction layer supported by the T7906E is an automatic checksum generation on the link. This is generated and checked automatically
by the T7906E without requiring support from a host or other external source. Errors
on the link are flagged and a special error packet is sent over the link to signal the
error condition.
Programming the T7906E internal registers is done via the IEEE-1355 link. All internal
registers are 8-bit wide addressable. Two simple commands (read and write) suffice
to access all functions and registers of the T7906E.
Rev. A – 27-Aug.-01
1
T7906E
The interfaces of the T7906E such as the FIFO, UART, ADC/DAC and memory interface are accessed by a simple read or write operation to the corresponding interface
address. In the case of FIFO, Host, UART and memory interface, a packet oriented
access is also possible (meaning transferring multiple bytes with a single command). In
case a communication memory
is connected to the T7906E, this can be read and written to via the link specific registers.
The IEEE-1355 links can support a range of communication speeds, which are programmed by writing to registers. At reset all links are configured to run at the base
speed of 10 Mbits/sec. Only the transmission speed of a link is programmed as reception is asynchronous. This means that links running at different speeds can be
connected, provided that each device is capable of receiving at the speed of the connected transmitter.
Introduction
Connecting a non-intelligent node to a processing element requires not only the communication controller, but usually a controlling instance for the communication circuitry. The
latter has to be configured for settings like bit rate, packet sizes, handshake protocols
etc. Should the non-intelligent node require remote control via commands, usually a
second link, dedicated for commands is introduced. Using an IEEE-1355 link for that
purpose eliminates the need for separate data and control paths, since the communication controller can differentiate between the two entities. In addition, it can be remotely
configured, can execute simple commands and provides special I/O pins to control the
interface unit.
The T7906E provides one IEEE-1355 serial communication link together with additional
features to support non-intelligent nodes as well as to control ADC and DAC converters.
The T7906E is targeted at two main applications areas:
•
Embedded systems
•
Communication device for processor systems
Embedded systems
The main application targets of the T7906E are modules and units without any built-in
communication features, such as special image compression chips, application specific
programmable logic or mass memory. The T7906E is perfectly suited to be used on
"non-intelligent" modules such as A/D-converter or sensor interfaces, due to its "control
by link" feature and system control facilities. In addition, its fault tolerance feature make
the device very interesting for many critical industrial measurement and control systems.
Example applications of the T7906E as communication and system controller on an
interface node consisting of an ADC and DAC and one where the T7906E is connected
to four banks of memory are given in the figures below:
2
Rev. A – 27-Aug.-01
Figure 1. Example applications
3
T7906E
Rev. A – 27-Aug.-01
T7906E
Communication device for microprocessors
Many applications require a link front end providing one link, but no controller instance
on that unit. Due to the communication memory interface of the SMCSlite, it is also satisfying the requirements of these applications. Due to its small package and low power
consumption it is an excellent alternative to FPGA based solutions. A system using the
SMCSlite as a communication front-end for a microcontroller is shown in the figure
below:
Figure 2. Example application
Interfaces
FIFO interface
The FIFO interface provides the control signals full, write, empty and read, depending
on the direction of the data flow (receive/transmit).
Data received from the FIFO interface is sent over the IEEE-1355 link grouped in packets. The length of a packet (in bytes) can be specified either by setting an internal
counter or by external signals. This interface can be programmed to use 0 to 7 wait
states.
ADC/DAC interface
The ADC interface allows to connect an ADC with a width of up to 16 bits directly to the
T7906E. The AD conversion can be started by request via link or in a cyclic manner triggered by the on-chip timers. When the AD conversion is ready, this is recognized by an
external signal like "ready" or by an internal trigger, for example from the on-chip timer.
After reading the sample from the ADC it is then sent over the link. An 8-bit address generator is provided to allow multiplexing of analog signals. The address generator will
start at a pre-programmed start address and will be incremented after each conversion.
The DAC interface is very similar to the ADC interface. It provides up to 16 data lines
and the required control signals. The data to be sent to the DAC is received from the link
and is stored in a register until the command "start DAC" is received. After that command the register values will be put to the DAC.
4
Rev. A – 27-Aug.-01
Block Diagram
5
8
2
GPIO
JTAG
2
UART
Internal control
data bus
ADC
I/F
I/F
address/command
bus
DAC
I/F
RAM
I/F
Internal
Controller
12
Control Bus
4
transmit/receive
data bus
Link
Interface
28
FIFO
I/F
Host
Interface
system
util.
Data Bus
Internal control
bus & data control
Timer
2
16
2
Memory Interface
The RAM interface provides a 16-bit data bus and 16-bit address bus. Four chip select
lines allow to address four different memory partitions (banks). This partitioning into different banks is done using 4 internal address boundary registers. These are 8 bit wide
and provide a minimum page size of 1024 words. The memory interface can be programmed to use 0 to 7 wait states.
GPIO Interface
The general purpose I/O (GPIO Interface) provides up to 24 bidirectional signal lines.
The direction (input or output) of each GPIO line can be set individually via register.
Data to/from the GPIO lines is written/read via the GPIO data register. The GPIO provides 8 dedicated I/O lines, the remaining 16 lines of the port are shared with the ADC
address and host data bus. These GPIO lines are available when the corresponding unit
(e.g. the host data bus) of the T7906Eis not being used (disabled).
UART interface
Two independent UARTs are included in the T7906E as well. One UART uses dedicated I/O lines whereas the second UART is sharing its pins with the GPIO port. The
transmit rate of the UARTs in bps can be programmed via a 12-bit wide register with a
maximum bit rate of about 780 kbit/s. The UARTs can optionally use hardware handshake (rts/cts).
Host Interface
Although the T7906E is primarily designed to be remotely controlled, it can nevertheless
be programmed and controlled by a local host if required. For that purpose a host interface provides 8 multiplexed data and address lines.
Timers / Event Counter
Two 32-bit on-chip timers are available on the T7906E. Each timer provides a 32 bit
counter and a 32 bit reload register. The two timers can be operated independently or
5
T7906E
Rev. A – 27-Aug.-01
T7906E
cascaded. The timers can also be used to set an external signal when the timeout value
is reached.
Configuration
After a chip reset the T7906E is configured by the internal controller. This can be either
by receiving the configuration data from the IEEE-1355 link or by an external controller
connected to the host port of the T7906E.
Shared I/O
Some of the functions of the T7906E presented above share the same I/O pins. This
means, that some functions are mutually exclusive. As an example, the GPIO port
shares some of its I/O pins with the host interface. If the host interface is not used, these
pins are available for GPIO, otherwise they are used as the host address and data bus.
The selection of which functions are being used is made by programming the appropriate registers after a chip reset. A short overview of the pin allocation and combinations
of functions is given in the table below:
Interface Type
Example Mode
Interface Type
Example Mode
1
2
3
Host / GPIO2
•
•
•
Timer1
•
•
•
Timer2
•
•
•
UART1
•
•
•
UART2
•
•
•
GPIO0
GPIO7-0
-
GPIO7-0
GPIO1
IOB7-0
FIFO
active mode
-
passive mode
RAM
-
•
-
ADC
•
-
-
DAC
•
-
-
Note:
JTAG interface
IOB7-0
If the passive FIFO mode is used on the T7906E, the ADC and DAC interfaces can then
not be used.
For testing purposes a standard IEEE 1149.1 interface is provided. It supports the JTAG
functions Bypass, Extest, Sample/Preload, All-Tristate and IDCode.
6
Rev. A – 27-Aug.-01
Programming the T7906E
Programming the T7906E internal registers is done via a simple protocol over the IEEE1355 link or directly via the host interface. The link protocol consists of a command byte
and, if necessary, one or more data bytes.
All internal registers are 8-bit wide addressable. Two commands (read and write) suffice
to access all registers of the T7906E.
The T7906E provides registers and ports; a register contains exactly one byte (read /
write), whereas a port (e.g. a FIFO interface) behaves like a FIFO, meaning that multiple
data bytes can be read or written from/to the port.
The ports of the T7906E such as the FIFO, UART, ADC and RAM interface are
accessed by a read/write command to the corresponding port address. In the case of
FIFO, Host, UART and memory interface, a packet oriented access is also possible
(meaning transferring multiple data bytes with a single command).
The read/write selection of a command is done by setting bit7 (msb) of the first byte to
one (read) or zero (write).
Signal Description
Signal
HSEL*
This section describes the signals of the T7906E. Groups of signals represent busses
where the highest number is the MSB.
Direction
I
HWRnRD
I
Description
max. output load
Signal
[mA]
[pF]
3
50
3
50
3
50
when low, the external host selects the T7906E host
interface
host interface write/read signal
if HWRnRD is high during HSEL* low, the host writes
data to the address register or to the T7906E
registers.
if HWRnRD is low during HSEL* low, the host reads
data from the address register or the T7906E
registers.
host interface data/address signal
if HDATnADR is high during read, the host
HDATnADR
I
reads/writes data from/to the internal T7906E
(data) registers.
if HDATnADR is low during read, the host
reads/writes address from/to the address register.
T7906E data bus.
This data lines will be used to access
HDATA(7:0)
I/O
the T7906E registers.
HDATA(7:0) can also be used as GPIO(2), if
Host interface is disabled.
HINTR*
O
host interrupt request line
TMR1_CLK
I
timer1 clock (max. 12.5 MHz)
TMR1_EXP
O
timer1 expired. Asserted for one cycle
if the value of counter1 is equal to the
content of register TPERIOD1(3:0).
7
T7906E
Rev. A – 27-Aug.-01
T7906E
Signal
Direction
TMR2_CLK
I
TMR2_EXP.
O
Description
max. output load
Signal
[mA]
[pF]
timer2 clock (max. 12.5 MHz)
timer2 expired. Asserted for one cycle
if the value of counter2 is equal to the
3
50
3
50
content of register TPERIOD2(3:0)
RxD1
I
receive data to UART1
TxD1
O
transmit data from UART1
LDI
I
Link Data Input
LSI
I
Link Strobe Input
LDO
O
Link Data Output
12
25
LSO
O
Link Strobe Output
12
25
DATA(15:0)
I/O
common T7906E data bus
3
25
GPIO(7:0)
I/O
General purpose input/output lines.
3
25
IOB(27:0)
I/O
Control bus. The T7906E controls the connected
interface via these lines. The function of each control
signal is described in a separate table.
see note (1)
25
3
50
TRST*
I
Test Reset. Resets the test state machine.
TCK
I
Test Clock. Provides an asynchronous clock for JTAG
boundary scan
TMS
I
Test Mode Select. Used to control the test state
machine. This input should be left unconnected or tied
to ground during normal operation!
TDI
I
Test Data Input. Provides serial data for the boundary
scan logic
TDO
O/Z
Test Data Output. Serial scan output of the boundary
scan path
RESET*
I
T7906E Reset. Sets the T7906E to a known state.
This input must be asserted (low) at power-up. The
minimum width of RESET low is 2 cycles when CLK is
running
CLK
I
External clock input to T7906E (max. 5 MHz)
PLLOUT
O
Output of internal PLL. Used to connect a network of
external RC devices
VCC
Power Supply
GND
Ground
Note:
1. IOB15-0, IOB21-18: 6 mA
IOB17-16: 8mA
IOB24-22: 3mA
IOB27-25: input only
All inputs have an internal pull-up resistor, with the following exceptions, which have an
internal pull-down resistor: LDI, LSI, TRST*, TMS.
8
Rev. A – 27-Aug.-01
IOB Control Bus
Signal
The allocation of the I/O busses is shown in the table below:
Function
Signal
Function
Signal
Function
RAM Interface
I/O
ADC/DAC/FIFO Interface
I/O
GPIO
GPIO1[7:0]
IOB[7:0]
RAM_ADDR[7:0]
O
ADC_ADDR[7:0]
O
IOB8
RAM_ADDR8
O
ADC_CS*
O
IOB9
RAM_ADDR9
O
ADC_R/C*
O
IOB10
RAM_ADDR10
O
DAC_WR*
O
IOB11
RAM_ADDR11
O
DAC_ADDR0
O
IOB12
RAM_ADDR12
O
DAC_ADDR1
O
IOB13
RAM_ADDR13
O
DAC_ADDR2
O
IOB14
RAM_ADDR14
O
FIFO_TRM_EOP_ACK
O
IOB15
RAM_ADDR15
O
FIFO_RCV_PAR
O
IOB16
RAM_WR*
O
FIFO_RCV_EOP1
O
IOB17
RAM_RD*
O
FIFO_RCV_EOP2
O
IOB18
RAM_CS0*
O
FIFO_RD*
B
IOB19
RAM_CS1*
O
FIDO_WR*
B
IOB20
RAM_CS2*
O
FIFO_EMPTY*
B
IOB21
RAM_CS3*
O
FIFO_FULL*
B
IOB22
RAM_TEST
O
ADC:_RDY
I
IOB23
RAM_ TRM_RDY
O
ADC_TRIG
I
IOB24
RAM_RCV_RDY
O
FIFO_TRM_EOP1
I
IOB25
RAM_BUS_REQ*
I
FIFO_TRM_EOP2
I
IOB26
RAM_START_TRM
I
FIFO_RCV_EOP_ACK
I
IOB27
RAM_START_RCV
I
FIFO_TRM_PAR
I
GPIO Signals
9
The pins GPIO0 to GPIO7 are either mapped on register GPIO0 (0x63 / 0x64) or miscellaneous I/O signals, depending on the register settings as shown in the table below:
Pin
Mapped to
I/O
Register
GPIO0
RTS1*UART1
O
UART1_CTRL (0x59): D7
GPIO1
CTS1*UART1
I
UART1_CTRL (0x59): D 7
GPIO2
EXT_IREQ0*
I
IFCONF (0x01): D6
GPIO3
EXT_IREQ1*
I
IFCONF (0x01): D 6
GPIO4
TxD2UART2
O
IFCONF (0x01): D7
GPIO5
RxD2UART2
I
IFCONF (0x01): D7
GPIO6
RTS2*UART2
O
UART2_CTRL (0x72): D7
GPIO7
CTS2*UART2
I
UART2_CTRL (0x72): D7
T7906E
Rev. A – 27-Aug.-01
T7906E
ELECTRICAL Specifications
This data is given for information only. For guaranteed values refer to Atmelk procurement specifications.
Table 1. Absolute Maximum Ratings
Parameter
Supply Voltage
Symbol
Value
Unit
VCC
-0,5 to +7
V
-0,5 to Vcc+0,5
V
I/O Voltage
Operating Temperature Range (Ambient)
TA
-55 to +125
°C
Junction Temperature
TJ
Tj < TA+20
°C
Storage Temperature Range
Tstg
-65 to +150
°C
Thermal Resistance
Rthje
1
°C/W
Rthja
35
Stresses above those listed may cause permanent damage to the device.
DC Electrical Characteristics
Table 2. DC Characteristics
Specified at VCC = + 5 V ± 10%
Parameter
Symbol
Min.
Max.
Unit
Operating Voltage
VCC
4,5
5,5
V
Input HIGH Voltage (TTL)
VIH
2,0
Input LOW Voltage (TTL)
VIL
Output HIGH Voltage
VOH
Output LOW Voltage
VOL
Output Short circuit current
IOS
Note:
Power Consumption
Conditions
V
0,8
2,4
V
V
max. output current (1)
0,4
V
max. output current (1)
160
mA
VOUT = VCC
130
mA
VOUT = GND
see also the signal description in section 4.
Although specified for TTL outputs, all T7906E outputs are CMOS compatible and will
drive VCC and GND assuming no DC loads.
The max. power consumption figures (at 5,5V, -55×C) are:
Operating Mode
Symbol
Max.
Unit
at Reset
I
15
mA
in Idle
I
50
mA
operating
I
80
mA
10
Rev. A – 27-Aug.-01
PLL-Filter
The pin PLLOUT should be connected as shown below:
T7906E
PLLOUT
R1
C1
•
•
•
C2
R1 = 249_ ± 5%, ¼W
C1 = 1nF, ± 5%, 200V
C2 = 15nF, ± 5%, 200V
Power and Ground Guidelines
To achieve its fast cycle time, the T7906E is designed with high speed drivers on output
pins. Large peak currents may pass through a circuit board’s ground and power lines,
especially when many output drivers are simultaneously charging or discharging their
load capacitances. These transient currents can cause disturbances on the power and
ground lines. To minimize these effects, the T7906E provides separate supply pins for
its internal logic and for its external drivers.
All GND pins should have a low impedance path to ground. A ground plane is required
in T7906E systems to reduce this impedance, minimizing noise.
The VCC pins should be bypassed to the ground plane using 8 high-frequency capacitors (0.1 mF ceramic). Keep each capacitor’s lead and trace length to the pins as short
as possible. This low inductive path provides the T7906E with the peak currents
required when its output drivers switch. The capacitors’ ground leads should also be
short and connect directly to the ground plane. This provides a low impedance return
path for the load capacitance of the T7906E output drivers.
The following pins must have a capacitor: 1, 4, 16, 27, 56, 61, 88 and 99.
11
T7906E
Rev. A – 27-Aug.-01
T7906E
Timing Parameters
Clock
Description
Symbol
Min.
Max.
Unit
CLK period
tCLK
1)
1)
ns
CLK width high
tCLKH
80
120
ns
CLK width low
tCLKL
80
120
ns
Note:
1) Nominal 5MHz
Reset
Description
Symbol
Min.
Max.
RESET* setup before CLK high
tRSTS
10
ns
RESET* low pulse width
tRSTW
2*tCLK
ns
Output disable after CLK high
tOUTD
38
Unit
ns
12
Rev. A – 27-Aug.-01
Host write address
Description
13
Symbol
Min.
Max.
HSEL* active low pulse width
tHSL
150
ns
HSEL* inactive high pulse width
tHSH
60
ns
HWRnRD setup before HSEL* active low
tHWnRS
5
ns
HDATnADR setup before HSEL* active low
tHWnRH
5
ns
HWRnRD hold after HSEL* inactive high
tHWnRH
0
ns
HDATnADR hold after HSEL* inactive high
tHDnAH
0
ns
HDATA valid after HSEL active low and HWRnRD high
tHDWV
HDATA hold after HSEL inactive high
tHDWH
25
0
Unit
ns
ns
T7906E
Rev. A – 27-Aug.-01
T7906E
Host write data
Description
Symbol
Min.
Max.
HSEL* active low pulse width
tHSL
150
ns
HSEL* inactive high pulse width
tHSH
60
ns
HWRnRD setup before HSEL* active low
tHWnRS
5
ns
HDATnADR setup before HSEL* active low
tHWnRH
5
ns
HWRnRD hold after HSEL* inactive high
tHWnRH
0
ns
HDATnADR hold after HSEL* inactive high
tHDnAH
0
ns
HDATA valid after HSEL active low and HWRnRD high
tHDWV
HDATA hold after HSEL inactive high
tHDWH
25
0
Unit
ns
ns
14
Rev. A – 27-Aug.-01
Host read address
Description
15
Symbol
Min.
HSEL* active low pulse width
tHSL
150
ns
HSEL* inactive high pulse width
tHSH
60
ns
HWRnRD setup before HSEL* active low
tHWnRS
5
ns
HDATnADR setup before HSEL* active low
tHWnRH
5
ns
HWRnRD hold after HSEL* inactive high
tHWnRH
0
ns
HDATnADR hold after HSEL* inactive high
tHDnAH
0
ns
HDATA enable after HSEL* active low and HWRnRD low
tHDE
4
HDATA valid after HSEL* active low and HWRnRD low
tHDV
HDATA hold after HSEL* inactive high
tHDH
4
Max.
Unit
18
ns
125
ns
18
ns
T7906E
Rev. A – 27-Aug.-01
T7906E
Host read data
Description
Symbol
Min.
HSEL* active low pulse width
tHSL
150
ns
HSEL* inactive high pulse width
tHSH
60
ns
HWRnRD setup before HSEL* active low
tHWnRS
5
ns
HDATnADR setup before HSEL* active low
tHWnRH
5
ns
HWRnRD hold after HSEL* inactive high
tHWnRH
0
ns
HDATnADR hold after HSEL* inactive high
tHDnAH
0
ns
HDATA enable after HSEL* active low and HWRnRD low
tHDE
4
HDATA valid after HSEL* active low and HWRnRD low
tHDV
HDATA hold after HSEL* inactive high
tHDH
4
Max.
Unit
18
ns
125
ns
18
ns
16
Rev. A – 27-Aug.-01
RAM interface write
Description
Symbol
Min.
Max.
Unit
1)
RAM I/F write access time
tRWA
120
120+ws *40
ns
CS0-3*, WR* active low pulse width
tRWL
40+ws1)*40
42+ws1)*40
ns
Address ADDR0-15 valid before CS0*, WR* active low
tRWAS
38
42
ns
Address ADDR0-15 hold after CS0-3*, WR* inactive high
tRWAH
38
42
ns
DATA0-15 enable after CS0-3*, WR* active low
tRWDE
0
6
ns
DATA0-15 valid before CS0-3*, WR* inactive high
tRWDV
32
DATA0-15 hold after CS0-3*, WR* inactive high
tRWDH
20
Note:
17
ns
26
ns
ws = wait states (0 - 7)
T7906E
Rev. A – 27-Aug.-01
T7906E
RAM interface read
Description
Symbol
Min.
Max.
Unit
CS0-3*, WR*, RD* and ADDR valid active low pulse width
tRRL
40+ws1)*40
42+ws1)*40
ns
CS0-3*, WR*, RD* and ADDR valid inactive high pulse width
tRRH
38
40
ns
ADDRESS change2)
tRRA
40+ws1)*40
42+ws1)*40
ns
DATA0-15 setup before CS0-3*, RD* high or new address on ADDR0-15 valid
tRDS
14
tRDH
0
DATA hold after CS0-3*, RD* high or new address on
ADDR0-15
Notes:
ns
40
ns
1. ws = wait states (0 - 7)
2. Internal clock runs at 25 MHz, ticlk = 40 ns
18
Rev. A – 27-Aug.-01
RAM interface external bus request
Description
19
Symbol
Min.
Max.
Unit
CS0-3*, WR*, RD*, ADDR0-15 and DATA0-15 disable
after BUS_REQ* active low
tRBRS
40
160
ns
CS0-3*, WR*, RD*, ADDR0-15 and DATA0-15 enable
after BUS_REQ inactive high
tRBRA
20
65
ns
T7906E
Rev. A – 27-Aug.-01
T7906E
RAM interface external control read
Description
Symbol
Min.
START_TRM high active pulse width
tRETH
47
ns
START_TRM low inactive pulse width
tRETL
47
ns
first read access (CS0-3* / RD* low active) after
START_TRM high
tRETC
120
1)
ns
TRM_RDY (transmit ready) high active after the last read
from memory
tRETR
160
1)
ns
time between the rising edge of TRM_RDY and the next
start (rising edge from START_TRM)
tRETS
0
TRM_RDY hold after START_TRM high
tRETD
Note:
Max.
Unit
ns
170
ns
1) depends on:
- data bandwidth over the IEEE-1355 link
- simultaneous read from the memory with wait states
20
Rev. A – 27-Aug.-01
RAM interface external control write
Description
Symbol
Min.
START_RCV high active pulse width
tRERH
47
ns
START_RCV low inactive pulse width
tRERL
47
ns
first write access (CS0-3* / WR* low active) after
START_RCV high
tRERC
120
1)
ns
RCV_RDY (receive ready) high inactive after the last
write to memory
tRERR
160
170
ns
time between the rising edge of RCV_RDY and the
next start (rising edge from START_RCV)
tRERS
0
RCV_RDY hold after START_RCV high
tRERD
Note:
21
Max.
Unit
ns
170
ns
1) depends on
- data bandwidth over the IEEE-1355 link
- simultaneous write to the memory with wait states
- internal write to fifo full
T7906E
Rev. A – 27-Aug.-01
T7906E
FIFO interface write
Description
Symbol
Min.
Max.
Unit
WR* active low pulse width
tFWL
40+ws1)*40
42+ws1)*40
ns
WR* inactive high pulse width
tFWH
38
40
ns
tFWACK
120
ns
tFFS
8
ns
RCVEOP1, RCVEOP2 high after last write and WR*
high
tFWEOP
40
RCV_EOP_ACK active high pulse width
tFWEOPA
49
RCVEOP1, RCVEOP2 low after RCV_EOP_ACK high
tFWEOPH
WR* active low after RCV_EOP_ACK high
FIFO_FULL* setup before WR* high
2)
ns
ns
128
ns
6
ns
DATA0-7 enable after WR* low
tFWDE
0
DATA0-7 valid before WR* high
tFWDV
32
ns
DATA0-7 hold after WR* high
tFWDH
2
ns
Notes:
1. ws = wait states (0 - 7)
2. depends on:
- data bandwidth over the IEEE-1355 link
22
Rev. A – 27-Aug.-01
FIFO interface read
Description
Symbol
Min.
Max.
Unit
RD* active low pulse width
tFRL
40+ws1)*4
0
42+ws1)*4
0
ns
RD* inactive high pulse width
tFRH
38
40
ns
FIFO_EMPTY* setup before RD* high
tFES
8
TRM_EOP_ACKnowledge active high after TRMEOP1,
TRMEOP2 high AND FIFO_EMPTY active low
tFREOPA
160
TRMEOP1, TRMEOP2 hold after TRM_EOP_ACK high
tFREOPH
0
TRM_EOP_ACK hold after TRMEOP1, TRMEOP2 low
tFRACKH
122
DATA0-7 setup before RD* inactive high
tFRDV
9
ns
DATA0-7 hold after RD* inactive high
tFRDH
0
ns
Notes:
23
ns
2)
ns
ns
128
ns
1. ws = wait states (0 - 7)
2. depends on:
- data bandwidth over the IEEE-1355 link
T7906E
Rev. A – 27-Aug.-01
T7906E
ADC interface
Description
Symbol
Min.
Max.
Unit
ADC_CS* low pulse width
tADCCS
40+ws*40
42+ws*40
ns
ADC_RDY high pulse width
tADCRDY
45
ns
ADC_RDY high to ADC_R/C* high
tADCR
200
ns
ADC_R/C* setup before ADC_CS* low
tADCS
40+ws*40
ADC_TRIG high pulse width
tADCTRIG
45
ns
ADC_TRIG high to ADC_CS* low
tADCTCS
200+ws*40
ns
DATA 0-15 setup to ADC_CS* high
tADCDS
19
ns
DATA 0-15 hold after ADC_CS* high
tADCDH
0
ns
Note:
42+ws*40
ns
ws = wait states (0 to 15)
DAC interface
Description
DAC_ADDR 0-2 and DATA 0-15 setup before DAC_WR*
low
DAC_WR* low pulse width
DATA 0-15 hold after DAC_WR* high
Note:
Symbol
Min.
Max.
Unit
tDACS
40+ws*40
42+ws*40
ns
tDACWR
40+ws*40
42+ws*40
ns
tDACH
38
42
ns
ws = wait states (0 to 15)
24
Rev. A – 27-Aug.-01
Timer
Description
25
Symbol
Min.
Max.
Unit
TMRx_CLK period
tTCLK
80
TMRx_CLK width high
tTCLKH
35
45
ns
TMRx_CLK width low
tTCLKL
35
45
ns
TMRx_EXP low / high after TMRx_CLK high
tTEXP
9
24
ns
ns
T7906E
Rev. A – 27-Aug.-01
T7906E
External Interrupt
Description
EXT_IREQx low pulse width
Symbol
Min.
tEXINT
10
Max.
Unit
ns
26
Rev. A – 27-Aug.-01
Links
Description
Symbol
Min.
Bit Period
tLBITP
4
LDOx, LSOx output skew 1)
tLOUTS
Data/Strobe edge separation
Note:
27
tLDSI
Max.
ns
0.5
1
Unit
ns
ns
1) Output skew includes jitter
T7906E
Rev. A – 27-Aug.-01
T7906E
Test Port (JTAG)
Description
Symbol
Min.
Max.
Unit
TCK period
tTCK
100
ns
TCK width high
tTCKH
40
ns
TCK width low
tTCKL
40
ns
TMS, TDI setup before TCK high
tTIS
8
ns
TMS, TDI hold after TCK high
tTIH
8
TDO delay after TCK low
tTDO
SMCS Inputs setup before TCK high
tSYSS
8
ns
SMCS Inputs hold after TCK high
tSYSM
8
ns
SMCS Outputs delay after TCK low
tSYSO
17
27
ns
28
Rev. A – 27-Aug.-01
Test Port Reset
Description
29
Symbol
TDO disable after TRST* active low
tTDOZ
TRST* pulse width
tTRST
Min.
2 * tTCK
Max.
Unit
5
ns
ns
T7906E
Rev. A – 27-Aug.-01
T7906E
Mechanical Data
Package Dimensions
Figure 3. 100-Pin Ceramic Quad Flat Pack (MQFPF)
MILLIMETERS
INCHES
Symbol
MIN
MAX
MIN
MAX
A
2.21
2.67
0.087
0.105
C
0.15
0.2
0.006
0.008
D
3 1.8
32.8
1.252
1.291
D1
18.8
19.3
0.74
0.76
E
31.8
32.8
1.252
1.45
E1
18.8
19.3
0.74
0.76
e
0.635 typ
0.025 typ
e
0.635 typ
f
0.254 ref
0.010 ref
f
0.254 ref
A1
1.83
2.24
0.072
0.088
A2
0.203 ref
0.008 ref
A2
0.203 ref
L
6.5
6.75
0.256
0.266
N1, N2
25
25
30
Rev. A – 27-Aug.-01
Pin Assignment
31
The table below lists the pins and their function.
Pin Number
Name
Pin Number
Name
Pin Number
Name
1
VCC
35
IOB16
69
GPIO2
2
GND
36
IOB17
70
GPIO3
3
GND
37
IOB18
71
GPIO4
4
VCC
38
IOB19
72
GPIO5
5
LD0
39
IOB20
73
GPIO6
6
LS0
40
IOB21
74
GPIO7
7
LDI
41
IOB22
75
TMR1_CLK
8
LSI
42
IOB23
76
TMR2_CLK
9
GND
43
IOB24
77
RxD1
10
TCK
44
IOB25
78
TMR1_EXP
11
TMS
45
IOB26
79
TMR2_EXP
12
TDI
46
IOB27
80
TxD1
13
TRST*
47
DATA0
81
HDATA0
14
TD0
48
DATA1
82
HDATA1
15
GND
49
DATA2
83
HDATA2
16
VCC
50
DATA3
84
HDATA3
17
IOB0
51
DATA4
85
HDATA4
18
IOB1
52
DATA5
86
HDATA5
19
IOB2
53
DATA6
87
HDATA6
20
IOB3
54
DATA7
88
VCC
21
IOB4
55
DATA8
89
GND
22
IOB5
56
VCC
90
HDATA7
23
IOB6
57
GND
91
HDATNADR
24
IOB7
58
DATA9
92
HSEL*
25
IOB8
59
DATA10
93
HWRNRD
26
IOB9
60
DATA11
94
HINTR*
27
VCC
61
VCC
95
RESET*
28
GND
62
GND
96
CLK
29
IOB10
63
DATA12
97
GND
30
IOB11
64
DATA13
98
GND
31
IOB12
65
DATA14
99
VCC
32
IOB13
66
DATA15
100
PLLOUT
33
IOB14
67
GPIO0
34
IOB15
68
GPIO1
T7906E
Rev. A – 27-Aug.-01
T7906E
Glossary
BSDLBoundary Scan Description Language
CPU Central Processing Unit
DPRAMDual-Port RAM
DSM Ds-link Macrocell
DSP Digital Signal Processor
EOP End Of Packet
GPIO General Purpose Input/Output
FIFO First In, First Out
HOCI Host Control Interface
HW
Hardware
JTAG Joint Test Action Group
LSB Least Significant Bit (or Byte)
MSB Most Significant Bit (or Byte)
PLL Phase Locked Loop
SIC
Simple Interprocessor Communication
SMCSScalable Multichannel Communication Subsystem
UARTUniversal Asynchronous Receiver Transmitter
Ordering Information
Part-Number
Temperature Range
Package
Quality
+25°C
MQFPF100
Engineering Samples
T7906EKT
-55° to +125°C
MQFPF100
MIL
T7906EKT/SC
-55° to +125°C
MQFPF100
SCC B
T7906EKT/SB
-55° to +125°C
MQFPF100
SCC C
T7906EKT/883*
-55° to +125°C
MQFPF100
MIL 883 B
T7906EKST/883*
-55° to +125°C
MQFPF100
MIL 883 S
T7906EKTMQ
-55° to +125°C
MQFPF100
QML Q
T7906EKTSV
-55° to +125°C
MQFPF100
QML V
T7906EDD-E
+25°C
Die
Engineering Samples
T7906EDDMQ
-55° to +125°C
Die
QML Q
T7906EDDSV
-55° to +125°C
Die
QML V
T7906EKT-E
Note:
(*)contact factory.
32
Rev. A – 27-Aug.-01
Appendix
-- BSDL for SMCSlite
-- Uses HP’s BSDL format and compiles correctly using HP’s
-- parser or compiler of JTAG Technologies
-- Author Paul Rastetter, Astrium GmbH
-- Tel.: +49-89-607-25015, Fax: +49-89-607-28964
-- e-mail: paul.rastetter@astrium-space.com
-- date: 24-11-00
entity SMCSLITE is
generic (PHYSICAL_PIN_MAP : string := "UNDEFINED");
PORT (BYPPLL : IN bit;
CLK :
IN bit;
HDATNADR : IN bit;
HWRNRD : IN bit;
LDI :
IN bit;
LSI :
IN bit;
NHSEL : IN bit;
NRESET : IN bit;
TRST : IN bit;
RXD :
IN bit;
TCK :
IN bit;
TDI :
IN bit;
TMR1_CLK : IN bit;
TMR2_CLK : IN bit;
TMS :
IN bit;
iob25 : IN bit;
iob26 : IN bit;
iob27 : IN bit;
LDO :
OUT bit;
LSO :
OUT bit;
NHINTR : OUT bit;
TDO :
OUT bit;
TMR1_EXP : OUT bit;
TMR2_EXP : OUT bit;
TXD :
OUT bit;
IOB8 : OUT bit;
IOB9 : OUT bit;
iob10 : OUT bit;
iob11 : OUT bit;
iob12 : OUT bit;
iob13 : OUT bit;
iob14 : OUT bit;
iob15 : OUT bit;
iob16 : OUT bit;
iob17 : OUT bit;
33
T7906E
Rev. A – 27-Aug.-01
T7906E
DATA : INOUT bit_vector(0 TO 15);
GPIO : INOUT bit_vector(0 TO 7);
HDATA : INOUT bit_vector(0 TO 7);
IOB0 : INOUT bit;
iob1 : INOUT bit;
iob2 : INOUT bit;
iob3 : INOUT bit;
iob4 : INOUT bit;
iob5 : INOUT bit;
iob6 : INOUT bit;
iob7 : INOUT bit;
iob18 : INOUT bit;
iob19 : INOUT bit;
iob20 : INOUT bit;
iob21 : INOUT bit;
iob22 : INOUT bit;
iob23 : INOUT bit;
iob24 : INOUT bit;
VDD :
linkage bit_vector(0 to 7);
GND :
linkage bit_vector(0 to 7);
NC :
linkage bit_vector(0 to 1) );
use STD_1149_1_1990.all;
attribute PIN_MAP of SMCSLITE : entity is PHYSICAL_PIN_MAP;
constant MCQFP_PACKAGE : PIN_MAP_STRING :=
"LDO:
5," &
"LSO:
6," &
"LDI:
7," &
"LSI:
8," &
"TCK: 10," &
"TMS: 11," &
"TDI: 12," &
"TRST: 13," &
"TDO: 14," &
"IOB0: 17," &
"IOB1: 18," &
"IOB2: 19," &
"IOB3: 20," &
"IOB4: 21," &
"IOB5: 22," &
"IOB6: 23," &
"IOB7: 24," &
"IOB8: 25," &
"IOB9: 26," &
"IOB10: 29," &
"IOB11: 30," &
"IOB12: 31," &
34
Rev. A – 27-Aug.-01
"IOB13: 32," &
"IOB14: 33," &
"IOB15: 34," &
"IOB16: 35," &
"IOB17: 36," &
"IOB18: 37," &
"IOB19: 38," &
"IOB20: 39," &
"IOB21: 40," &
"IOB22: 41," &
"IOB23: 42," &
"IOB24: 43," &
"IOB25: 44," &
"IOB26: 45," &
"IOB27: 46," &
"DATA: (47,48,49,50,51,52,53,54,55,58,59,60,63,64,65,66)," &
"GPIO: (67,68,69,70,71,72,73,74)," &
"TMR1_CLK:75," &
"TMR2_CLK:76," &
"RXD: 77," &
"TMR1_EXP:78," &
"TMR2_EXP:79," &
"TXD: 80," &
"HDATA: (81,82,83,84,85,86,87,90)," &
"HDATNADR:91," &
"NHSEL: 92," &
"HWRNRD: 93," &
"NHINTR: 94," &
"NRESET: 95," &
"CLK: 96," &
"BYPPLL: 97," &
"VDD: (1,4,16,27,56,61,88,99)," &
"GND: (2,3,15,28,57,62,89,98)," &
"NC:
(9,100)"; -- for completeness: scan_en, pllout,
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_RESET of TRST : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6, BOTH);
attribute INSTRUCTION_LENGTH of SMCSLITE : entity is 3;
attribute INSTRUCTION_OPCODE of SMCSLITE : entity is
"BYPASS (111,110,101,100)," &
"EXTEST (000)," &
"SAMPLE (001)," &
35
T7906E
Rev. A – 27-Aug.-01
T7906E
"IDCODE (010)," &
"HIGHZ
(011)";
attribute INSTRUCTION_CAPTURE of SMCSLITE : entity is
"101";
attribute INSTRUCTION_DISABLE of SMCSLITE : entity is
"HIGHZ";
attribute IDCODE_REGISTER of SMCSLITE : entity is
"0001" &
-- Version
"0101001101001100" & -- Part number 534C = SL
"00001011000" &
-- ID of manufacturer; MATRA MHS is 58 hex
"1";
-- required by IEEE Std 1149.1-1990 (LSB)
attribute REGISTER_ACCESS of SMCSLITE : entity is
"BSREG (EXTEST, SAMPLE)," &
"BOUNDARY (EXTEST, SAMPLE),"&
-- "IDREG (IDCODE)," &
"BYPASS (BYPASS, HIGHZ)";
-- "BPREG (BYPASS, HIGHZ)";
--
attribute BOUNDARY_CELLS of SMCSLITE : entity is
"BC_1";
-- BC_1: output, control; BC_1: input;
attribute BOUNDARY_LENGTH of SMCSLITE : entity is 155;
attribute BOUNDARY_REGISTER of SMCSLITE : entity is
-- num cell port
"
"
"
"
"
"
"
"
"
"
"
"
func safe [ccell disval rslt]
0 (BC_1, LSI,
input, X)," &
1 (BC_1, LDI,
input, X)," &
2 (BC_1, LSO,
output2, X)," &
3 (BC_1, LDO,
output2, X)," &
4 (BC_1, BYPPLL, input, X)," &
5 (BC_1, CLK,
input, X)," &
6 (BC_1, NRESET, input, X)," &
7 (BC_1, NHINTR, output2, X)," & -- output2 for internal tristate
8 (BC_1, HWRNRD, input, X)," &
9 (BC_1, NHSEL,
input, X)," &
10 (BC_1, HDATNADR, input, X)," &
11 (BC_1, *
, control, 0)," & -- HOCI Data Output Enable7
36
Rev. A – 27-Aug.-01
" 12 (BC_1, HDATA(7), output3, X, 11,
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
37
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
0,
Z)," &
(BC_1, HDATA(7), input, X)," &
(BC_1, *
, control, 0)," & -- HOCI Data Output Enable6
(BC_1, HDATA(6), output3, X, 14, 0,
Z)," &
(BC_1, HDATA(6), input, X)," &
(BC_1, *
, control, 0)," & -- HOCI Data Output Enable5
(BC_1, HDATA(5), output3, X, 17, 0,
Z)," &
(BC_1, HDATA(5), input, X)," &
(BC_1, *
, control, 0)," & -- HOCI Data Output Enable4
(BC_1, HDATA(4), output3, X, 20, 0,
Z)," &
(BC_1, HDATA(4), input, X)," &
(BC_1, *
, control, 0)," & -- HOCI Data Output Enable3
(BC_1, HDATA(3), output3, X, 23, 0,
Z)," &
(BC_1, HDATA(3), input, X)," &
(BC_1, *
, control, 0)," & -- HOCI Data Output Enable2
(BC_1, HDATA(2), output3, X, 26, 0,
Z)," &
(BC_1, HDATA(2), input, X)," &
(BC_1, *
, control, 0)," & -- HOCI Data Output Enable1
(BC_1, HDATA(1), output3, X, 29, 0,
Z)," &
(BC_1, HDATA(1), input, X)," &
(BC_1, *
, control, 0)," & -- HOCI Data Output Enable0
(BC_1, HDATA(0), output3, X, 32, 0,
Z)," &
(BC_1, HDATA(0), input, X)," &
(BC_1, TXD,
output2, X)," & -- output2 for internal tristate
(BC_1, TMR2_EXP, output2, X)," & -- output2 for internal tristate
(BC_1, TMR1_EXP, output2, X)," & -- output2 for internal tristate
(BC_1, RXD,
input, X)," &
(BC_1, TMR2_CLK, input, X)," &
(BC_1, TMR1_CLK, input, X)," &
(BC_1, *
, control, 0)," & -- GPIO Output Enable7
(BC_1, GPIO(7), output3, X, 41, 0,
Z)," &
(BC_1, GPIO(7), input, X)," &
(BC_1, *
, control, 0)," & -- GPIO Output Enable6
(BC_1, GPIO(6), output3, X, 44, 0,
Z)," &
(BC_1, GPIO(6), input, X)," &
(BC_1, *
, control, 0)," & -- GPIO Output Enable5
(BC_1, GPIO(5), output3, X, 47, 0,
Z)," &
(BC_1, GPIO(5), input, X)," &
(BC_1, *
, control, 0)," & -- GPIO Output Enable4
(BC_1, GPIO(4), output3, X, 50, 0,
Z)," &
(BC_1, GPIO(4), input, X)," &
(BC_1, *
, control, 0)," & -- GPIO Output Enable3
(BC_1, GPIO(3), output3, X, 53, 0,
Z)," &
(BC_1, GPIO(3), input, X)," &
(BC_1, *
, control, 0)," & -- GPIO Output Enable2
(BC_1, GPIO(2), output3, X, 56, 0,
Z)," &
(BC_1, GPIO(2), input, X)," &
(BC_1, *
, control, 0)," & -- GPIO Output Enable1
(BC_1, GPIO(1), output3, X, 59, 0,
Z)," &
(BC_1, GPIO(1), input, X)," &
(BC_1, *
, control, 0)," & -- GPIO Output Enable0
T7906E
Rev. A – 27-Aug.-01
T7906E
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
(BC_1, GPIO(0), output3, X, 62, 0,
Z)," &
(BC_1, GPIO(0), input, X)," &
(BC_1, *
, control, 0)," & -- DATA Output Enable
(BC_1, DATA(15), output3, X, 65, 0,
Z)," &
(BC_1, DATA(15), input, X)," &
(BC_1, DATA(14), output3, X, 65, 0,
Z)," &
(BC_1, DATA(14), input, X)," &
(BC_1, DATA(13), output3, X, 65, 0,
Z)," &
(BC_1, DATA(13), input, X)," &
(BC_1, DATA(12), output3, X, 65, 0,
Z)," &
(BC_1, DATA(12), input, X)," &
(BC_1, DATA(11), output3, X, 65, 0,
Z)," &
(BC_1, DATA(11), input, X)," &
(BC_1, DATA(10), output3, X, 65, 0,
Z)," &
(BC_1, DATA(10), input, X)," &
(BC_1, DATA(9), output3, X, 65, 0,
Z)," &
(BC_1, DATA(9), input, X)," &
(BC_1, DATA(8), output3, X, 65, 0,
Z)," &
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
81 (BC_1, DATA(8), input, X)," &
82 (BC_1, DATA(7), output3, X, 65, 0,
Z)," &
83 (BC_1, DATA(7), input, X)," &
84 (BC_1, DATA(6), output3, X, 65, 0,
Z)," &
85 (BC_1, DATA(6), input, X)," &
86 (BC_1, DATA(5), output3, X, 65, 0,
Z)," &
87 (BC_1, DATA(5), input, X)," &
88 (BC_1, DATA(4), output3, X, 65, 0,
Z)," &
89 (BC_1, DATA(4), input, X)," &
90 (BC_1, DATA(3), output3, X, 65, 0,
Z)," &
91 (BC_1, DATA(3), input, X)," &
92 (BC_1, DATA(2), output3, X, 65, 0,
Z)," &
93 (BC_1, DATA(2), input, X)," &
94 (BC_1, DATA(1), output3, X, 65, 0,
Z)," &
95 (BC_1, DATA(1), input, X)," &
96 (BC_1, DATA(0), output3, X, 65, 0,
Z)," &
97 (BC_1, DATA(0), input, X)," &
98 (BC_1, IOB27,
input, X)," &
99 (BC_1, IOB26,
input, X)," &
100 (BC_1, IOB25,
input, X)," &
101 (BC_1, *
, control, 0)," & -- IOB Output Enable
102 (BC_1, IOB24,
output3, X, 101, 0,
Z)," &
103 (BC_1, IOB24,
input, X)," &
104 (BC_1, IOB23,
output3, X, 101, 0,
Z)," &
105 (BC_1, IOB23,
input, X)," &
106 (BC_1, IOB22,
output3, X, 101, 0,
Z)," &
107 (BC_1, IOB22,
input, X)," &
108 (BC_1, *
, control, 0)," & -- IOB Output Enable
109 (BC_1, IOB21,
output3, X, 108, 0,
Z)," &
110 (BC_1, IOB21,
input, X)," &
111 (BC_1, *
, control, 0)," & -- IOB Output Enable
112 (BC_1, IOB20,
output3, X, 111, 0,
Z)," &
113 (BC_1, IOB20,
input, X)," &
38
Rev. A – 27-Aug.-01
" 114 (BC_1, *
, control, 0)," & -- IOB Output Enable
" 115 (BC_1, IOB19,
output3, X, 114, 0,
Z)," &
" 116 (BC_1, IOB19,
input, X)," &
" 117 (BC_1, *
, control, 0)," & -- IOB Output Enable
" 118 (BC_1, IOB18,
output3, X, 117, 0,
Z)," &
" 119 (BC_1, IOB18,
input, X)," &
" 120 (BC_1, *
, control, 0)," & -- IOB Output Enable
" 121 (BC_1, IOB17,
output3, X, 120, 0,
Z)," &
" 122 (BC_1, IOB16,
output3, X, 120, 0,
Z)," &
" 123 (BC_1, IOB15,
output3, X, 120, 0,
Z)," &
" 124 (BC_1, IOB14,
output3, X, 120, 0,
Z)," &
" 125 (BC_1, IOB13,
output3, X, 120, 0,
Z)," &
" 126 (BC_1, IOB12,
output3, X, 120, 0,
Z)," &
" 127 (BC_1, IOB11,
output3, X, 120, 0,
Z)," &
" 128 (BC_1, IOB10,
output3, X, 120, 0,
Z)," &
" 129 (BC_1, IOB9,
output3, X, 120, 0,
Z)," &
" 130 (BC_1, IOB8,
output3, X, 120, 0,
Z)," &
" 131 (BC_1, *
, control, 0)," & -- IOB Output Enable
" 132 (BC_1, IOB7,
output3, X, 131, 0,
Z)," &
" 133 (BC_1, IOB7,
input, X)," &
" 134 (BC_1, *
, control, 0)," & -- IOB Output Enable
" 135 (BC_1, IOB6,
output3, X, 134, 0,
Z)," &
" 136 (BC_1, IOB6,
input, X)," &
" 137 (BC_1, *
, control, 0)," & -- IOB Output Enable
" 138 (BC_1, IOB5,
output3, X, 137, 0,
Z)," &
" 139 (BC_1, IOB5,
input, X)," &
" 140 (BC_1, *
, control, 0)," & -- IOB Output Enable
" 141 (BC_1, IOB4,
output3, X, 140, 0,
Z)," &
" 142 (BC_1, IOB4,
input, X)," &
" 143 (BC_1, *
, control, 0)," & -- IOB Output Enable
" 144 (BC_1, IOB3,
output3, X, 143, 0,
Z)," &
" 145 (BC_1, IOB3,
input, X)," &
" 146 (BC_1, *
, control, 0)," & -- IOB Output Enable
" 147 (BC_1, IOB2,
output3, X, 146, 0,
Z)," &
" 148 (BC_1, IOB2,
input, X)," &
" 149 (BC_1, *
, control, 0)," & -- IOB Output Enable
" 150 (BC_1, IOB1,
output3, X, 149, 0,
Z)," &
" 151 (BC_1, IOB1,
input, X)," &
" 152 (BC_1, *
, control, 0)," & -- IOB Output Enable
" 153 (BC_1, IOB0,
output3, X, 152, 0,
Z)," &
" 154 (BC_1, IOB0,
input, X)";
end SMCSLITE;
39
T7906E
Rev. A – 27-Aug.-01
T7906E
40
Rev. A – 27-Aug.-01
41
T7906E
Rev. A – 27-Aug.-01
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Web site
http://www.atmel-wm.com
© Atmel Nantes SA, 2001.
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which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
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