TI TNETE100

ThunderLAN TNETE100
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS017B – APRIL 1995 – REVISED AUGUST 1996
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Single-Chip Ethernet Adapter for the
Peripheral Component Interconnect (PCI)
Local Bus
– 32-Bit PCI† Glueless Host Interface
– Compliant With PCI Local-Bus
Specification (Revision 2.0)
– 0-MHz to 33-MHz Operation
– 3-V or 5-V Input/Output (I/O) Operation
– Adaptive Performance Optimization
(APO) by Texas Instruments (TI ) for
Highest Available PCI Bandwidth
– High-Performance Bus Master
Architecture With Byte-Aligning Direct
Memory Access (DMA) Controller for
Low Host CPU and Bus Utilization
– Plug-and-Play Compatible
Supports 32-Bit Data Streaming on PCI Bus
– Time Division Multiplexed Static
Random-Access Memory (SRAM)
– 2-Gbps Internal Bandwidth
Driver Compatible With All Previous
ThunderLAN Components
Switched-Ethernet Compatible
Full-Duplex Compatible
– Independent Transmit and Receive
Channels
– Two Transmit Channels for Demand
Priority
Supports Multiple Protocols With a Single
Driver Suite
– Optimized Shared Interrupts
No On-Board Memory Required
Auto-Negotiation (N-Way) Compatible
Multimedia-Ready Architecture
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Integrated 10 Base-T and 10 Base-5
Attachment Unit Interface (AUI) Physical
Layer Interface
– Single-Chip IEEE 802.3 and Blue Book
Ethernet-Compliant Solution
– DSP-Based Digital Phase-Locked Loop
(PLL)
– Smart Squelch Allows for Transparent
Link Testing
– Transmission Waveshaping
– Autopolarity (Reverse Polarity
Correction)
– External/Internal Loopback Including
Twisted Pair and AUI
– 10 Base-2 Supported via AUI Interface
Media-Independent Interface (MII) for
Connecting 100-Mbps External
Transceivers
– Compliant MII for IEEE 802.3u
Transceivers
– Supports 100 Base-Tx, 100 Base-T4, and
100 Base-Fx
– Super Set Supports IEEE 802.12
Transceivers
– Supports Ethernet and Token-Ring
Framing Formats for 100VG-AnyLAN
– Link-Pulse Detection for Determining
Wire Rate
Low-Power CMOS Technology
– Green PC Compatible
– Microsoft Advanced Power
Management
EEPROM Interface Supports Jumperless
Design and Autoconfiguration
Hardware Statistics Registers for
Management Information Base (MIB)
DMTF (Desktop Management Task Force)
Compatible
IEEE Standard 1149.1‡ Test-Access Port
144-Pin Quad Flat Package (PCE Suffix)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
† The PCI Local-Bus Specification, Revision 2.0 should be used as a reference with this document.
‡ IEEE Standard 1149.1 – 1990, IEEE Standard Test-Access Port and Boundary-Scan Architecture.
AnyLAN is a trademark of the Hewlett-Packard Company.
ThunderLAN, Adaptive Performance Optimization, and TI are trademarks of Texas Instruments Incorporated.
Ethernet is a trademark of Xerox Corporation.
Microsoft is a registered trademark of Microsoft Corp.
Copyright  1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
1
ThunderLAN TNETE100
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS017B – APRIL 1995 – REVISED AUGUST 1996
pin assignments
109
113
112
111
110
117
116
115
114
121
120
119
118
125
124
123
122
129
128
127
126
133
132
131
130
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
69
70
71
72
65
66
67
68
61
62
63
64
57
58
59
60
53
54
55
56
49
50
51
52
45
46
47
48
PAD9
PAD8
VSSI
PC/BE0
PAD7
PAD6
VSSL
PAD5
PAD4
PAD3
V DDI
PAD2
PAD1
PAD0
VSSI
PCLKRUN
EAD7
EAD6
EAD5
EAD4
VDDL
EAD3
EAD2
EAD1
EAD0
VSSL
EOE
EALE
EXLE
VSSI
EDCLK
EDIO
VDDL
MTCLK
MTXD0
40
41
42
43
44
36
VDDL
2
137
136
135
134
1
2
37
38
39
PAD24
PC/BE3
VSSI
PIDSEL
PAD23
VDDI
PAD22
PAD21
PAD20
VSSI
PAD19
PAD18
PAD17
VDDI
PAD16
PC/BE2
PFRAME
VSSL
PIRDY
PTRDY
PDEVSEL
VDDL
PSTOP
PPERR
PSERR
VSSI
PPAR
PC/BE1
PAD15
PAD14
VSSI
PAD13
PAD12
VDDI
PAD11
PAD10
141
140
139
138
144
143
142
PAD25
PAD26
VDDI
PAD27
PAD28
VSSI
PAD29
PAD30
VDDI
PAD31
PREQ
VSSL
PGNT
PCLK
VDDL
PRST
PINTA
VSSI
TDI
TDO
TCLK
TMS
VDDI
TRST
FONLY
VSSVCO
FATEST
VDDVCO
FIREF
VDDOSC
FXTL2
FXTL1
VSSOSC
ACOLN
VSSR
ACOLP
PCE PACKAGE
( TOP VIEW )
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
ARCVN
VDDR
ARCVP
FRCVN
VDDR
FRCVP
VSSR
VSST
AXMTN
AXMTP
FXMTN
FXMTP
VDDT
MRST
VDDL
MDIO
VSSL
MDCLK
MRXER
MRXDV
VSSI
MRXD3
MRXD2
MRXD1
VDDL
MRXD0
MRCLK
MCRS
MCOL
VDDL
MTXER
MTXEN
MTXD3
VSSL
MTXD2
MTXD1
ThunderLAN TNETE100
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS017B – APRIL 1995 – REVISED AUGUST 1996
description
ThunderLAN is a high-speed networking architecture that provides a complete PCI-to-10 Base-T/AUI Ethernet
solution with the flexibility to handle 100-Mbps Ethernet protocols as the user’s networking demands grow.
FIFO
Registers
PCI
Bus
PCI
Bus Master
Control
Multiplexed
SRAM
FIFO
Ethernet
LAN
Controller
10 / 100 Mbps
10 Base-T
Physical
Layer
Interface
10 Base-T
Ethernet
10 Base-5
(AUI)
MediaIndependent
Interface
Figure 1. ThunderLAN Architecture
The TNETE100, an implementation of the ThunderLAN architecture, is an intelligent-network protocol interface.
The ThunderLAN SRAM FIFO-based architecture eliminates the need for external memory and offers a
single-chip glueless PCI-to-10 Base-T/AUI (IEEE 802.3) solution with an on-board physical layer interface.
Modular support for 100 Base-T (IEEE 802.3u) and 100VG-AnyLAN (IEEE 802.12) is provided by a superset
of the industry-standard Media Independent Interface (MII). ThunderLAN uses a single driver suite to support
multiple networking protocols.
The glueless PCI interface supports 32-bit streaming, operates at speeds up to 33 MHz and is capable of
internal data transfer rates up to 2 Gbps, taking full advantage of all available PCI bandwidth. The TNETE100
offers jumperless autoconfiguration using PCI configuration read / write cycles. Customizable configuration
registers, which can be autoloaded from an external serial EEPROM, allow designers of TNETE100-based
systems to give their systems a unique identification code. The TNETE100 PCI interface, developed in
conjunction with other leaders in the semiconductor and computer industries, has been tested vigorously on
multiple platforms to ensure compatibility across a wide array of available PCI products. In addition, the
ThunderLAN drivers and ThunderLAN architecture use TI’s patented Adaptive Performance Optimization
(APO) technology to adjust dynamically critical parameters for minimum latency, minimum host CPU utilization,
and maximum system performance. This technology ensures that the maximum capabilities of the PCI interface
are used by automatically tuning the adapter to the specific system in which it is operating.
The MII, an industry-standard interface for connecting a variety of external IEEE 802.3u physical layer
interfaces, is supported fully by the TNETE100. In addition, the TNETE100 features an IEEE 802.12-compliant
superset of the MII to allow for support of 100VG-AnyLAN physical layer interfaces. This allows
TNETE100-based systems to support 100 Base-Tx, 100 Base-T4, and 100VG-AnyLAN cabling schemes for
maximum flexibility as each new physical layer interface becomes available in the marketplace.
An intelligent protocol handler (PH) implements the serial protocols of the network. The PH is designed for
minimum overhead related to multiple protocols, using common state machines to implement 95% of the total
protocol handler. On transmit, the PH serializes data, adds framing and cyclic redundancy check (CRC) fields,
and interfaces to the network physical layer (PHY) chip. On receive, it provides address recognition, CRC and
error checking, frame disassembly, and deserialization. Data for multiple channels is passed to and from the
PH by way of circular buffer pointers in the FIFO SRAM.
ThunderLAN is the first multimedia-ready architecture and is capable of handling prioritized data regardless of
the selected protocol. The demand-priority protocol supports two priorities of frames: normal and priority. The
two transmit channels provide independent host channels for these two frame types. Carrier-sense multiple
access with collision detection (CSMA / CD) protocols only support a single priority of frame, but the two
channels can be used to prioritize network access. All received frames pass through the single receive channel.
Compliant with IEEE Standard 1149.1 (JTAG), the TNETE100 provides a 5-pin test-access port that is used for
boundary-scan testing.
The TNETE100 is available in a 144-pin quad flat package.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
3
ThunderLAN TNETE100
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS017B – APRIL 1995 – REVISED AUGUST 1996
functional block diagram
TNETE100
( ThunderLAN)
TRST
IEEE
1149.1
TestAccess
Port
TCLK
TDO
AXMTN
Test-Access
Port
(TAP)
ARCVP
ARCVN
TDI
EDCLK
Config
EEPROM
Interface
EAD[7 :0]
BIOS ROM
and
LED I/F
EXLE
EALE
EOE
ACOLN
10-Mbps
Ethernet
Physical
Layer
(PHY)
Interface
Config
& I/O
Memory
Registers
EDIO
AUI
Interface
ACOLP
PCI
Interface
(PCIIF)
Configuration
EEPROM
Interface
AXMTP
TMS
FXMTP
FXMTN
FRCVP
FRCVN
FXTL1
10 Base-T
Interface
FXTL2
S
l
a
v
e
FIREF
FATEST
FPREGs
(FIFO
Pointer
Registers)
BIOS
ROM / LED
Driver
Interface
MTCLK
MTXEN
MTXER
MCOL
PAD[31 :0]
MTXD[3 : 0]
Address
and Data
FSRAM
(FIFO SRAM)
PC/BE[3 : 0]
PPAR
64
PTRDY
1.5K-Byte
Rx Buffer
64
PIRDY
PSTOP
PDEVSEL
PIDSEL
M
a
DMA
Controller s
t
e
r
Bus
Arbitration
MRXDV
MRXER
0.75K-Byte
Tx Buffer
MRST
PSERR
PREQ
PGNT
PCLKRUN
PRST
PINTA
4
MRCLK
MDCLK
PCLK
System
Control
MII
0.75K-Byte
Tx Buffer
PPERR
Error
Reporting
MRXD[3 : 0]
MCRS
3 128Byte List
PFRAME
Interface
Control
Protocol
Handler
(PH)
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
MDIO
MII
ThunderLAN TNETE100
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS017B – APRIL 1995 – REVISED AUGUST 1996
Pin Functions
PIN
NAME
NO.
TYPE†
DESCRIPTION
TEST PORT
TCLK
124
I
Test clock. TCLK is used to clock state information and test data into and out of the device during
operation of the test port.
TDI
126
I
Test data input. TDI is used to shift serially test data and test instructions into the device during
operation of the test port.
TDO
125
O
Test data output. TDO is used to shift serially test data and test instructions out of the device during
operation of the test port.
TMS
123
I
Test mode select. TMS is used to control the state of the test port controller within TNETE100.
TRST
121
I
Test reset. TRST is used for asynchronous reset of the test port controller.
PCI INTERFACE
PAD31
135
PAD30
137
PAD29
138
PAD28
140
PAD27
141
PAD26
143
PAD25
144
PAD24
1
PAD23
5
PAD22
7
PAD21
8
PAD20
9
PAD19
11
PAD18
12
PAD17
13
PAD16
15
PAD15
29
PAD14
30
PAD13
32
PAD12
33
PAD11
35
PAD10
36
PAD9
38
I/O
PCI address / data bus.
bus Byte 3 (most significant) of the PCI address / data bus
I/O
PCI address / data bus.
bus Byte 2 of the PCI address / data bus
I/O
PCI address / data bus.
bus Byte 1 of the PCI address / data bus
PAD8
39
† I = input, O = output, I / O = 3-state input / output
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
5
ThunderLAN TNETE100
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS017B – APRIL 1995 – REVISED AUGUST 1996
Pin Functions (Continued)
PIN
NAME
NO.
TYPE†
DESCRIPTION
PCI INTERFACE (CONTINUED)
PAD7
42
PAD6
43
PAD5
45
PAD4
46
PAD3
47
PAD2
49
PAD1
50
PAD0
51
PCLK
131
I
PCI clock. PCLK is the clock reference for all PCI bus operations. All other PCI pins except PRST and
PINTA are sampled on the rising edge of PCLK. All PCI bus timing parameters are defined with respect
to this edge.
PCLKRUN
53
I/O‡
Clock run control. PCLKRUN is the active-low PCI clock request /grant signal that allows the TNETE100
to indicate when an active PCI clock is required. (This is an open drain.)
PC / BE3
PC / BE2
PC / BE1
PC / BE0
2
16
28
41
I/O
PCI bus command and byte enables: PC / BE3 enables byte 3 (MSbyte) of the PCI address/data bus.
PC / BE2 enables byte 2 of the PCI address / data bus.
PC / BE1 enables byte 1 of the PCI address / data bus.
PC / BE0 enables byte 0 (LSbyte) of the PCI address / data bus.
I/O
PCI address / data bus.
bus Byte 0 (least significant) of the PCI address / data bus
PDEVSEL
21
I/O
PCI device select. PDEVSEL indicates that the driving device has decoded one of its addresses as the
target of the current access. The TNETE100 drives PDEVSEL when it decodes an access to one of its
registers. As a bus master, the TNETE100 monitors PDEVSEL to detect accesses to illegal memory
addresses.
PFRAME
17
I/O
PCI cycle frame. PFRAME is driven by the active bus master to indicate the beginning and duration of
an access. It is asserted to indicate the start of a bus transaction. PFRAME remains asserted during
the transaction, and is deasserted only in the final data phase.
PGNT
132
I
PCI bus grant. PGNT is asserted by the system arbiter to indicate that the TNETE100 has been granted
control of the PCI bus.
4
I
PCI initialization device select. PIDSEL is the chip select for access to the PCI configuration registers.
128
O/D
PCI interrupt. PINTA is the interrupt request from the TNETE100. PCI interrupts are shared, so this is
an open-drain (wired-OR) output.
PIDSEL
PINTA
PIRDY
19
I/O
PCI initiator ready. PIRDY is driven by the active bus master to indicate that it is ready to complete the
current data phase of a transaction. A data phase is not completed until both PIRDY and PTRDY are
sampled asserted. When the TNETE100 is a bus master, it uses PIRDY to align incoming data on reads
or outgoing data on writes with its internal RAM access synchronization (maximum one cycle at the
beginning of burst). When the TNETE100 is a bus slave, it extends the access appropriately until both
PIRDY and PTRDY are asserted.
PTRDY
20
I/O
PCI target ready. PTRDY is driven by the selected device (bus slave or target) to indicate that it is ready
to complete the current data phase of a transaction. A data phase is not completed until both PIRDY
and PTRDY are sampled asserted.
ThunderLAN uses PTRDY to ensure every direct I/O (DIO) operation is interlocked correctly.
PPAR
27
I/O
PCI parity. PPAR carries even parity across PAD[31:0] and PC / BE[3:0]. It is driven by the TNETE100
during all address and write cycles as a bus master and during all read cycles as a bus slave.
PPERR
24
I/O
PCI parity error. PPERR indicates a data parity error on all PCI transactions except special cycles.
† I = input, I / O = 3-state input / output, O / D = open-drain output
‡ Open drain
6
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
ThunderLAN TNETE100
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS017B – APRIL 1995 – REVISED AUGUST 1996
Pin Functions (Continued)
PIN
NAME
NO.
TYPE†
DESCRIPTION
PCI INTERFACE (CONTINUED)
I/O
PCI bus request. PREQ is asserted by the TNETE100 to request control of the PCI bus. This is not a
shared signal.
PREQ
134
PRST
129
I
PSERR
25
O/D
PCI system error. PSERR indicates parity errors or special-cycle data-parity errors.
PSTOP
23
I/O
PCI stop. PSTOP indicates the current target is requesting the master to stop the current transaction.
PCI reset signal
BIOS ROM / LED DRIVER INTERFACE
EAD7
EAD6
EAD5
EAD4
EAD3
EAD2
EAD1
EAD0
54
55
56
57
59
60
61
62
I/O
EPROM address / data. EAD[7:0] is a multiplexed byte bus that is used to address and read data from
an external BIOS ROM.
• On the cycle when EXLE is asserted low, EAD[7:0] is driven with the high byte of the
address.
• On the cycle when EALE is asserted low, EAD[7:0] is driven with the low byte of the
address.
• When EOE is asserted, BIOS ROM data should be placed on the bus.
These pins can be used also to drive external status LEDs. Low-current (2 – 5 mA) LEDs can be
connected directly (through appropriate resistors). High-current LEDs can be driven through buffers
or from the BIOS ROM address latches.
EALE
65
O
EPROM address latch enable. EALE is driven low to latch the low (least significant) byte of the BIOS
ROM address from EAD[0 :7].
EOE
64
O
EPROM output enable. When EOE is active (low), EAD[0 :7] is 3-stated, and the output of the BIOS
ROM should be placed on EAD[0 :7].
EXLE
66
O
EPROM extended address-latch enable. EXLE is driven low to latch the high (most significant) byte
of the BIOS ROM address from EAD[0 :7].
CONFIGURATION EEPROM INTERFACE
EDCLK
68
O
EEPROM data clock. EDCLK transfers serial clocked data to the 2K-bit serial EEPROMs (24C02) (see
Note 1).
EDIO
69
I/O
EEPROM data I / O. EDIO is the bidirectional serial data / address line to the 2K-bit serial EEPROM
(24C02). EDIO requires an external pullup for EEPROM operation. Tying EDIO to ground disables the
EEPROM interface and prevents autoconfiguration of the PCI configuration register.
MEDIA-INDEPENDENT INTERFACE (100-Mbps CSMA / CD AND DEMAND PRIORITY)
MCOL
80
I
Collision sense
• In CSMA / CD mode, assertion of MCOL indicates a network collision.
• In demand-priority mode, MCOL (active low) is used to acknowledge a transmission request.
The TNETE100 begins frame transmission 50 MTCLK cycles after the assertion (low) of MCOL.
MCRS
81
I
Carrier sense. MCRS indicates a frame-carrier signal is being received.
MDCLK
91
O
Management data clock. MDCLK is part of the serial management interface to physical-media
independent (PMI) / PHY chip.
MDIO
93
I/O
Management data I / O. MDIO is part of the serial management interface to PMI / PHY chip.
MRCLK
82
I
Receive clock. MRCLK is the receive clock source from the attached PHY and PMI device.
MRST
95
O
MII reset. MRST is the reset signal to the PMI / PHY front-end (active low).
† I = input, O = output, I / O = 3-state input / output, O / D = open-drain output
NOTE 1: This pin should be tied to VDD with a 4.7-kW – 10-kW pullup resistor.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
7
ThunderLAN TNETE100
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS017B – APRIL 1995 – REVISED AUGUST 1996
Pin Functions (Continued)
PIN
NAME
NO.
TYPE†
DESCRIPTION
MEDIA-INDEPENDENT INTERFACE (100-Mbps CSMA / CD AND DEMAND PRIORITY) (CONTINUED)
MRXD0
MRXD1
MRXD2
MRXD3
83
85
86
87
I
Receive data. MRXD[3 : 0] is the nibble that receives data from the physical-media-dependent (PMD)
front end. In demand-priority mode, ThunderLAN reads the frame priority of incoming frames on these
pins on the cycle before assertion of MRXDV (the cycle before frame reception begins).
• MRXD1 indicates the transmission priority of the received frame. A value of zero indicates
normal transmission, and a value of one indicates priority transmission.
Data on these pins is always synchronous to MRCLK.
MRXDV
89
I
Receive data valid. MRXDV indicates data on MRXD[3 : 0] is valid.
MRXER
90
I
Receive error. MRXER indicates reception of a coding error on received data.
MTCLK
71
I
Transmit clock. MTCLK is the transmit clock source from the attached PHY and PMI device.
MTXD0
MTXD1
MTXD2
MTXD3
72
73
74
76
O
Transmit data. MTXD[3 : 0] is the nibble that transmits data from TNETE100. When MTXEN is asserted,
these pins carry data to be transmitted. In demand-priority mode, the TNETE100 drives the request
state of the adapter on these pins when MTXEN is not asserted (frame transmission not in progress).
• MTXD0 asserted indicates the TNETE100 is requesting frame transmission.
• MTXD1 indicates the transmission priority required. A value of zero indicates normal
transmission, and a value of one indicates high-priority transmission.
Data on these pins is always synchronous to MTCLK.
MTXER
78
O
Transmit error. MTXER allows coding errors to be propagated across the MII.
MTXEN
77
O
Transmit enable. MTXEN indicates valid transmit data on MTXD[3 : 0].
ACOLN
ACOLP
111
109
A
AUI receive pair. ACOLN and ACOLP are differential line receiver inputs and connect to receive pair
through transformer isolation, etc.
ARCVN
ARCVP
108
106
A
AUI receive pair. ARCVN and ARCVP are differential line receiver inputs and connect to receive pair
through transformer isolation, etc.
AXMTP
AXMTN
99
100
A
AUI transmit pair. AXMTP and AXMTN are differential line transmitter outputs.
FATEST
118
A
Analog test pin. FATEST provides access to the filter of the reference PLL. This pin should be left as
a “no connect.”
FIREF
116
A
Current reference. FIREF is used to set a current reference for the analog circuitry.
FONLY
120
A
Front-end only pin. When FONLY is tied high, all TNETE100 functions other than the on-chip front end
are disabled. The MII interface pins allow the PHY to be used as a stand-alone 10 Base-T front end.
FRCVN
FRCVP
105
103
A
10 Base-T receive pair. FRCVN and FRCVP are differential line receiver inputs and connect to receive
pair through transformer isolation, etc.
FXTL1
FXTL2
113
114
A
Crystal oscillator pins. Drive FXTL1 from a 20-MHz crystal oscillator module
NETWORK INTERFACE (10 Base-T AND AUI)
FXMTP
97
A
FXMTN
98
† I = input, O = output, A = Analog
8
10 Base-T transmit pair. FXMTP and FXMTN are differential line transmitter outputs.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
ThunderLAN TNETE100
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS017B – APRIL 1995 – REVISED AUGUST 1996
Pin Functions (Continued)
PIN
NAME
NO.
TYPE†
DESCRIPTION
POWER
VDDI
6, 14,
34, 48,
122, 136,
142
PWR
PCI VDD pins. VDDI pins provide power for the PCI I/O pin drivers. Connect VDDI pins to a 5-V power
supply when using 5-V signals on the PCI bus. Connect VDDI pins to a 3-V power supply when using
3-V signals on the PCI bus
VDDL
22, 37,
58, 70,
79, 84,
94, 130
PWR
Logic VDD pins (5 V). VDDL pins provide power for internal TNETE100 logic, and they should always
be connected to a 5-V power supply.
VDDOSC
115
PWR
Analog power pin. VDDOSC is the 5-V power for the crystal oscillator circuit.
VDDR
104
107
PWR
Analog power pin. VDDR is the 5-V power for the receiver circuitry.
96
PWR
Analog power pin. VDDT is the 5-V power for the transmitter circuitry.
VDDT
VDDVCO
117
PWR
Analog power pin. VDDVCO is the 5-V power for the voltage controller oscillator (VCO) and filter input.
VSSI
3, 10, 26,
31, 40,
52, 67,
88, 127,
139
PWR
PCI I / O ground pins
VSSL
18, 44,
63, 75,
92, 133
PWR
Logic ground pins
VSSOSC
112
PWR
Analog power pin. Ground for crystal oscillator circuit
VSSR
102
110
PWR
Analog power pin. Ground for receiver circuitry
VSST
101
PWR
Analog power pin. Ground for transmitter circuitry
119
PWR
Analog power pin. Ground for VCO and filter input
VSSVCO
† PWR = power
architecture
The major blocks of the TNETE100 include the PCI interface (PCIIF), protocol handler (PH), physical layer
(PHY), FIFO pointer registers (FPREGS), FIFO SRAM (FSRAM), and a test-access port (TAP). The
functionality of these blocks is described in the following sections.
PCI interface (PCIIF)
The TNETE100 PCIIF contains a byte-aligning DMA controller that allows frames to be fragmented into any byte
length and transferred to any byte address while supporting 32-bit data streaming. For multipriority networks,
it can provide multiple data channels, each with separate lists, commands, and status. Data for the channels
is passed to and from the PH by way of circular buffer FIFOs in the SRAM, controlled through FIFO registers.
The configuration EEPROM interface, BIOS ROM /LED driver interface, configuration and I / O memory
registers, and DMA controller are subblocks of the PCIIF. The features of these subblocks are described in the
following subsections.
configuration EEPROM interface (CEI)
The CEI provides a means for autoconfiguration of the PCI configuration registers. Certain registers in the PCI
configuration space can be loaded using the CEI. Autoconfiguration allows builders of TNETE100-based
systems to customize the contents of these registers to identify their own system, rather than to use the TI
defaults. The EEPROM is read at power up and can then be read from, and written to, under program control.
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PCI interface (PCIIF) (continued)
BIOS ROM/LED driver interface (BRI)
The BRI addresses and reads data from an external BIOS ROM through a multiplexed byte-wide bus. The ROM
address/ data pins can also be multiplexed to drive external status LEDs.
configuration and I/O memory registers (CIOREGS)
The CIOREGS reside in the configuration space, which is 256 bytes in length. The first 64 bytes of the
configuration space is the header region, which is defined explicitly by the PCI standard.
DMA controller (DMAC)
The DMAC is responsible for coordinating TNETE100 requests for mastership of the PCI bus. The DMAC
provides byte-aligning DMA control, allowing byte-size fragmented frames to be transferred to any byte address
while supporting 32-bit data streaming.
protocol handler (PH)
The PH implements the serial protocols of the network. On transmit, it serializes data, adds framing and CRC
fields, and interfaces to the network PHY. On receive, it provides address recognition, CRC and error checking,
frame disassembly, and deserialization. Data for multiple channels is passed to and from the PH by way of
circular buffer FIFOs in the FSRAM controlled through FPREGS. The PH supports a MII that is compatible with
the IEEE 802.12 and IEEE 802.3u logic.
media-independent interface (MII)
The MII provides both MAC-level 100 Base-T (IEEE 802.3u) and 100VG-AnyLAN (IEEE 802.12) controller
functions to external PHY chips that handle the PHY functions for 100-Mbps CSMA / CD and demand priority.
The MII also is used to communicate with the on-chip 10 Base-T PHY.
10 Base-T physical layer (PHY)
The PHY acts as an on-chip front-end providing physical layer functions for both 10 Base-5 (AUI) and 10 Base-T
(twisted pair). The PHY provides Manchester encoding / decoding from MII nibble format data, smart squelch,
jabber detection, link pulse detection, autopolarity control, 10 Base-T transmission waveshaping, and
antialiasing filtering. Connection to the AUI drop cable for the 10 Base-T twisted pair is made through simple
isolation transformers (see Figure 2) and no external filter networks are required. Suitable external termination
components allow the use of either shielded or unshielded twisted-pair cable (150 W or 100 W). Some of the
key features of the on-chip PHY are listed below.
D
D
D
D
D
D
D
D
10
Integrated filters
Integrated MII including encoder / decoder
10 Base-T transceiver
AUI transceiver
Autopolarity (reverse polarity correction)
Loopback for twisted pair and AUI
Full-duplex mode for simultaneous 10 Base-T transmission and reception
Low power
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10 Base-T physical layer (continued)
FXMTP
PCI
TNETE100
FXMTN
RJ-45
FRCVP
FRCVN
Figure 2. Schematic for 10 Base-T Network Interface Using TNETE100
FIFO pointer registers (FPREGS)
The FPREGS are used to implement circular buffer FIFOs in the SRAM. They are a collection of pointer and
counter registers used to maintain the FIFO operation. Both the PCIIF and PH use FPREGS to determine where
to read or write data in the SRAM and to determine how much data the FIFO contains. Unique receive and
transmit FIFO registers are needed for each data channel supported.
FIFO SRAM (FSRAM)
The FSRAM is a conventional SRAM array accessed synchronously to the PCI bus clock. Access to the RAM
is allocated on a time-division multiplexed (TDM) basis, rather than through a conventional shared bus. This
removes the need for bus arbitration and provides guaranteed bandwidth. Half the RAM accesses (every other
cycle) are allocated to the PCI controller. It has a 64-bit access port to the RAM, giving it 1 Gbps of bandwidth,
sufficient to support 32-bit data streaming on the PCI bus. The PH has one-quarter the RAM accesses, and its
port may be up to 64 bits wide. A 64-bit port for the PH provides 512 Mbps of bandwidth, more than sufficient
for a full-duplex 100-Mbps network. The remaining RAM accesses can be allocated toward providing even more
PH bandwidth. The RAM is also accessible (for diagnostic purposes) from the TNETE100 internal data bus.
Host DIO (mapped I / O) accesses are used by the host to access internal TNETE100 registers and for adapter
test.
D
D
3.375K bytes of FSRAM
– 1.5K-byte FIFO for receive
– Two 0.75K-byte FIFOs for the two transmit channels
– Three 128-byte lists
In one-channel mode, the two transmit channels are combined giving a single 1.5K-byte FIFO for a single
transmit channel.
Supporting 1.5K bytes of FIFO per channel allows full frame buffering of Ethernet frames. PCI latency is such
that a minimum of 500 bytes of storage is required to support 100-Mbps LANs.
test-access port (TAP)
Compliant with IEEE Standard 1149.1, the TAP is comprised of five pins that are used to interface serially with
the device and with the board on which it is installed for boundary-scan testing.
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absolute maximum ratings over operating case temperature range (unless otherwise noted)†
Supply voltage range, VDD (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Input voltage range (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 W
Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 95°C
Junction-to-ambient package thermal impedance, airflow = 0 lfpm, TJA(0) . . . . . . . . . . . . . . . . . . . . 28.8°C/W
Junction-to-ambient package thermal impedance, airflow = 100 lfpm, TJA(100) . . . . . . . . . . . . . . . . 24.8°C/W
Junction-to-case package thermal impedance, TJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 2: Voltage values are with respect to VSS, and all VSS pins should be routed so as to minimize inductance to system ground.
The recommended operating conditions and the electrical characteristics tables are divided into groups,
depending on pin function:
D
D
D
PCI interface pins
Logic pins
Physical layer pins
The PCI signal pins may be operated in one of two modes shown in the PCI tables.
D
D
5-V signal mode
3-V signal mode
recommended operating conditions (PCI interface pins only) (see Note 3)
3-V SIGNALING
OPERATION
VDD
VIH
VIL
IOH
Supply voltage (PCI)
High-level input voltage
0.5
Low-level input voltage, TTL-level signal (see Note 4)
High-level output current
MIN
NOM
3
3.3
VDD‡
– 0.5‡
5-V SIGNALING
OPERATION
MAX
MIN
NOM
3.6
4.75
5
VDD + 0.5‡
0.5‡
TTL outputs
– 0.5
2.0
– 0.5
UNIT
MAX
5.25
V
VDD + 0.5
0.8
V
–2
V
mA
IOL
Low-level output current (see Note 5)
TTL outputs
1.5
6
mA
‡ Assured by design SPICE IV Curve (See PCI specification revision 2.1 section 4.2 paragraph 2 for explanation.)
NOTES: 3. PCI interface pins include VDDI, PCLKRUN, PFRAME, PTRDY, PIRDY, PSTOP, PDEVSEL, PIDSEL, PPERR, PSERR, PREQ,
PGNT, PCLK, PPAR, PRST, PINTA, PAD[31 : 0], and PC/BE[3 : 0].
4. The algebraic convention, where the more negative (less positive) limit is designated as a minimum, is used for logic-voltage levels
only.
5. Output current of 2 mA is sufficient to drive five low-power Schottky TTL loads or ten advanced low-power Schottky TTL loads (worst
case).
12
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electrical characteristics over recommended ranges of supply voltage (unless otherwise noted)
(PCI interface pins)
3-V SIGNALING
OPERATION
TEST CONDITIONS †
PARAMETER
MIN
VOH
High-level output voltage, TTL-level signal
(see Note 6)
VOL
Low-level output voltage, TTL-level signal
IOZ
High impedance output current
High-impedance
II
Ci
Input current, any input or input / output
Input capacitance, any input§
Co
Output capacitance, any output or
input / output§
VDD = MIN,
IOH = MAX
2.4‡
VDD = MAX,
VDD = MAX,
IOL = MAX
VO = 0 V
‡
VDD = MAX,
VO = VDD
VI = VSS to VDD
MAX
5-V SIGNALING
OPERATION
MIN
UNIT
MAX
2.4
V
0.45
0.5
10
10
– 10
– 10
V
µA
" 10
" 10
µA
f = 1 MHz,
Others at 0 V
10
10
pF
f = 1 MHz,
Others at 0 V
10
10
pF
† For conditions shown as MIN / MAX, use the appropriate value specified under the recommended operating conditions.
‡ Assured by SPICE IV Curve (See PCI specification revision 2.1 section 4.2 paragraph 2 for explanation.)
§ Assured by design
NOTE 6: The following signals require an external pullup resistor: PSERR, PINTA.
recommended operating conditions (logic pins) (see Note 4)
VDD
VIH
Supply voltage (5 V only)
VIL
IOH
Low-level input voltage, TTL-level signal (see Note 5)
MIN
NOM
4.75
5
High-level input voltage
2
High-level output current
– 0.3
MAX
UNIT
5.25
V
VDD + 0.3
0.8
V
TTL outputs
–4
V
mA
IOL
Low-level output current (see Note 7)
TTL outputs
4
mA
NOTES: 4. The algebraic convention, where the more negative (less positive) limit is designated as a minimum, is used for logic-voltage levels
only.
5. Output current of 2 mA is sufficient to drive five low-power Schottky TTL loads or ten advanced low-power Schottky TTL loads (worst
case).
7. Logic pins include VDDL, EAD[7:0], EXLE, EALE, EOE, EDCLK, EDIO, FONLY, MTCLK, MTXEN, MTXER, MCOL, MTXD[3:0],
MRXD[3:0], MCRS, MRCLK, MRXDV, MRXER, MDCLK, MDIO, MRST.
electrical characteristics over recommended ranges of supply voltage (unless otherwise noted)
(logic pins)
TEST CONDITIONS †
PARAMETER
VOH
VOL
High-level output voltage, TTL-level signal
IOZ
High impedance output current
High-impedance
II
IDD
Input current
Supply current
VI = VSS to VDD
VDD = MAX
Ci
Input capacitance, any input§
f = 1 MHz,
Low-level output voltage, TTL-level signal
VDD = MIN,
VDD = MAX,
IOH = MAX
IOL = MAX
VDD = MIN,
VDD = MIN,
VO = VDD
VO = 0 V
Output capacitance, any output or input / output§
MIN
Others at 0 V
Co
f = 1 MHz,
Others at 0 V
† For conditions shown as MIN / MAX, use the appropriate value specified under the recommended operating conditions.
§ Assured by design
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MAX
2.4
UNIT
V
0.5
10
– 10
V
µA
"10
µA
320
mA
10
pF
10
pF
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recommended operating conditions (physical layer pins) (see Note 8)
JEDEC
SYMBOL
MIN
NOM
MAX
UNIT
VDD
Supply voltage
4.75
5
5.25
V
NOTE 8: Physical layer pins include VDDOSC, VDDR, VDDT, VDDVCO, ACOLN, ACOLP, ARCVN, ARCVP, AXMTP, AXMTN, FATEST, FIREF,
FRCVN, FRCVP, FXTL1, FXTL2, FXMTP, and FXMTN.
recommended operating conditions (10 Base-T receiver input pins)
JEDEC
SYMBOL
VI(DIFF) Differential input voltage†
I(CM)
Common-mode current†
† Recommended operating conditions
VID
IIC
MIN
MAX
0.6
2.8
4
UNIT
V
mA
recommended operating conditions (AUI receiver input pins)
JEDEC
SYMBOL
VI(DIFF)1
Differential input voltage 1†
VID(1)
†
VI(DIFF)2
Differential input voltage 2
VID(2)
† Recommended operating conditions
NOTES: 9. Common-mode frequency range: 0 Hz to 40 kHz
10. Common-mode frequency range: 40 kHz to 10 MHz
TEST CONDITIONS
MIN
MAX
See Note 9
0
3
See Note 10
0
100
UNIT
V
mV
electrical characteristics over recommended ranges of supply voltage (unless otherwise noted)
(physical layer pins)
10 Base-T receiver input (FRCVP, FRCVN)
JEDEC
SYMBOL
PARAMETER
VSQ+
VSQ –
TEST CONDITIONS
Rising input pair squelch threshold
VCM = VSB,
See Note 11
Falling input pair squelch threshold
VCM = VSB,
See Note 11
MIN
MAX
UNIT
270
mV
– 270
mV
NOTE 11: VSB is the self-bias voltage of the input FRCVP and FRCVN.
10 Base-T transmitter drive characteristics (FXMTP, FXMTN)
JEDEC
SYMBOL
PARAMETER
VSLW
VO(CM)
Differential voltage at specified slew rate
VO(DIFF)
VO(I)
Differential voltage output
Common-mode output voltage
Output idle differential voltage
VOD(SLEW)
VOC
VOD
VOD(IDLE)
TEST CONDITIONS
See Figure 3 (d) and 3 (e)
Into open circuit
IO(FC)
Output current, fault condition‡
‡ Assured by design
IO(FC)
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MIN
MAX
UNIT
"2.2
"2.8
V
0
4
V
5.25
V
"50
mV
300
mA
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electrical characteristics over recommended ranges of supply voltage (unless otherwise noted)
(physical interface pins) (continued)
AUI receiver input (ARCVP, ARCVN, ACOLP, ACOLN)
JEDEC
SYMBOL
PARAMETER
VSQ–
TEST CONDITIONS
Falling input pair squelch threshold
MIN
MAX
– 325
UNIT
mV
AUI transmitter drive characteristics (AXMTP, AXMTN)
JEDEC
SYMBOL
PARAMETER
VO(DIFF)1
Differential output voltage
VOD(1)
VOI(DIFF)
Output idle differential voltage†
VOD(IDLE)
VOI(DIFF)U
Output differential undershoot‡
TEST CONDITIONS
See Note 12
MIN
MAX
"500 "1315
"40†
UNIT
mV
mV
100‡
mV
150‡
mA
MIN
MAX
UNIT
VOD(IDLE)U
IO(FC)
Output current, fault condition ‡
IO(FC)
† Assured by design
‡ Characterized but not tested
NOTE 12: The differential voltage is measured as per Figure 3(b) on page 17.
crystal oscillator characteristics
JEDEC
SYMBOL
PARAMETER
VSB(FXTL1)
Input self-bias voltage
TEST CONDITIONS
VIB
IOH(FXTL2)
High-level output current (see Note 4)
IOH
V(FXTL2) = VSB(FXTL1)
V(FXTL1) = VSB(FXTL1) + 0.5 V
IOL(FXTL2)
Low-level output current
IOL
V(FXTL2) = VSB(FXTL1)
V(FXTL1) = VSB(FXTL1) – 0.5 V
1.7
2.8
V
– 1.3
–5
mA
0.4
1.5
mA
NOTE 4: The algebraic convention, where the more negative (less positive) limit is designated as a minimum, is used for logic-voltage levels only.
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PARAMETER MEASUREMENT INFORMATION
Outputs are driven to a minimum high-logic level of 2.4 V and to a maximum low-logic level of 0.6 V. These levels
are compatible with TTL devices.
Output transition times are specified as follows: For a high-to-low transition on either an input or output signal,
the level at which the signal is said to be no longer high is 2 V and the level at which the signal is said to be low
is 0.8 V. For a low-to-high transition, the level at which the signal is said to be no longer low is 0.8 V and the level
at which the signal is said to be high is 2 V, as shown below.
The rise and fall times are not specified but are assumed to be those of standard TTL devices, which are typically
1.5 ns.
2 V (high)
0.8 V (low)
test measurement
The test-load circuit shown in Figure 3 represents the programmable load of the tester pin electronics that are
used to verify timing parameters of the TNETE100 output signals.
16
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IOL
50 Ω
Test
Point
AXMTP
Test
Point
VLOAD
CL
TTL
Output
Under
Test
50 Ω
78 Ω
AXMTN
X1
IOH
(b) AXMTP AND AXMTN TEST LOAD (AC TESTING)
X1 – Fil – Mag 23Z90 (1:1)
(a) TTL OUTPUT TEST LOAD
50 Ω
25 Ω
Test
Point
FXMTP
50 Ω
FIREF
25 Ω
180 Ω
FXMTN
X2
(d) FXMTP AND FXMTN TEST LOAD (AC TESTING)
X2 – Fil – Mag 23Z128 (1: √2)
(c) FIREF TEST CIRCUIT
50 Ω
Test
Point
FXMTP
50 Ω
50 Ω
Test
Point
FXMTN
50 Ω
(e) FXMTP AND FXMTN TEST LOAD (DC TESTING)
Where: IOL
IOH
VLOAD
CL
= Refer to IOL in recommended operating conditions
= Refer to IOH in recommended operating conditions
= 1.5 V, typical dc-level verification or
0.7 V, typical timing verification
= 18 pF, typical load-circuit capacitance
Figure 3. Test and Load Circuit
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switching characteristics for PCI 5-V and 3.3-V (see Note 13 and Figure 4)
PARAMETER
tVAL
Delay time, PCLK to bused signals valid (see Notes 14 and 15)
tVAL(PTP) Delay time, PCLK to bused signals valid point-to-point (see Notes 14 and 15)
ton
Float to active delay
MIN
MAX
2
11
ns
2
12
ns
2
UNIT
ns
toff
Active to float delay
28
ns
NOTES: 13. Some of the timing symbols in this table are not currently listed with EIA or JEDEC standards for semiconductor symbology but are
consistent with the PCI Local-Bus Specification, Revision 2.0.
14. Minimum times are measured with a 0-pF equivalent load; maximum times are measured with a 50-pF equivalent load. Actual test
capacitance may vary, but results should be correlated to these specifications.
15. PREQ and PGNT are point-to-point signals and have different output valid delay and input setup times than do bused signals. PGNT
has a setup time of 10 ns; PREQ has a setup time of 12 ns. All other signals are bused.
timing requirements for PCI 5-V and 3.3-V (see Note 13 and Figure 4)
MIN
tsu
tsu(PTP)
Setup time, bused signals valid to PCLK (see Note 15)
th
Input hold time from PCLK
Setup time to PCLK—point-to-point (see Note 15)
MAX
UNIT
7
ns
10, 12
ns
0
100 Mbps
30
10 Mbps
30
ns
50†
500†
ns
tc
Cycle time,
time PCLK (see Note 16)
tw(H)
tw(L)
Pulse duration, PCLK high
12
ns
Pulse duration, PCLK low
12
ns
ns
tslew
Slew rate, PCLK (see Note 17)
1
4
V/ns
† Characterized by design and system specifications.
NOTES: 13. Some of the timing symbols in this table are not currently listed with EIA or JEDEC standards for semiconductor symbology but are
consistent with the PCI Local-Bus Specification, Revision 2.0.
15. PREQ and PGNT are point-to-point signals and have different output valid delay and input setup times than do bused signals. PGNT
has a setup time of 10 ns; PREQ has a setup time of 12 ns. All other signals are bused.
16. As a requirement for frame transmission /reception, the minimum PCLK frequency varies with network speed. The clock can only
be stopped in a low state.
17. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum
peak-to-peak portion of the clock waveform.
18
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timing requirements for PCI 5-V and 3.3-V (continued)
2V
1.5 V
0.8 V
5-V Clock
tc
tw(H)
tw(L)
0.475 × VDD
0.4 × VDD
0.325 × VDD
3.3-V Clock
tVAL
Output
Delay
3-State
Output
ton
toff
th
tsu
Inputs
Valid
Input
Vmax
Figure 4. PCI 5-V and 3.3-V Timing
POST OFFICE BOX 1443
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19
ThunderLAN TNETE100
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS017B – APRIL 1995 – REVISED AUGUST 1996
timing requirements for MII receive (see Figure 5)†
MIN
tsu(MRX pins)
th(MRX pins)
MAX
UNIT
Setup time, MRXD[3:0], MRXDV, MRXER (see Note 18)
10
ns
Hold time, MTX[3:0], MRXDV, MRXER (see Note 18)
10
ns
switching characteristics for MII transmit (see Figure 5)†
PARAMETER
MIN
MAX
UNIT
td(MTX pins)
Delay time, MTCLK to MTXD[3:0], MTXEN, and MTXER outputs (see Note 19)
0
25
ns
† Both MCRS and MCOL are driven asynchronously by the PHY.
NOTES: 18. MRXD[3:0] is driven by the PHY on the falling edge of MRCLK. It is sampled by the reconciliation sublayer synchronous to the edge
of MRCLK. MRXD[3:0] timing must be met during clock periods where MRXDV is asserted. MRXDV is asserted and deasserted
by the PHY on the falling edge of MRCLK. It is sampled by the reconciliation sublayer synchronous to the rising edge of MRCLK.
MRXER is driven by the PHY on the falling edge of MRCLK. It is sampled by the reconciliation sublayer synchronous to the rising
edge of MRCLK. MRXER timing must be met during clock periods when MRXDV is asserted.
19. MTXD[3:0] is driven by the reconciliation sublayer synchronous to the MTCLK. MTXEN is asserted and deasserted by the
reconciliation sublayer synchronous to the MTCLK rising edge. MTXER is driven synchronous to the rising edge of MTCLK.
MTCLK
MTXD[3:0],
MTXEN,
MTXER
td(MTX pins)
MRCLK
MRXD[3:0],
MRXDV,
MRXER
tsu(MRX pins)
th(MRX pins)
Figure 5. MII Transmit and Receive Timing
20
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
ThunderLAN TNETE100
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS017B – APRIL 1995 – REVISED AUGUST 1996
timing requirements for MDIO (see Figure 6)
ta(MDCLKH-MDIOV)
Access time, MDIO valid from MDCLK high (see Note 20)
MIN
MAX
UNIT
0
300
ns
MIN
MAX
UNIT
switching characteristics for MDIO (see Figure 7)
PARAMETER
td(MDIOV-MDCLKH)
td(MDCLKH-MDIOX)
Delay time, MDIO valid to MDCLK high (see Note 21)
10
ns
Delay time, MDCLK high to MDIO changing (see Note 21)
10
ns
NOTES: 20. When the MDIO signal is sourced by the PMI /PHY, it is sampled by TNETE100 synchronous to the rising edge of MDCLK.
21. MDIO is a bidirectional signal that can be sourced by TNETE100 or the PMI /PHY. When TNETE100 sources the MDIO signal,
TNETE100 asserts MDIO synchronous to the rising edge of MDCLK.
MDCLK
MDIO
ta(MDCLKH-MDIOV)
Figure 6. Management Data I/O Timing (Sourced by PHY)
MDCLK
MDIO
td(MDIOV-MDCLKH)
td(MDCLKH-MDIOX)
Figure 7. Management Data I/O Timing (Sourced by TNETE100)
POST OFFICE BOX 1443
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21
ThunderLAN TNETE100
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS017B – APRIL 1995 – REVISED AUGUST 1996
timing requirements for BIOS ROM and LED interface (see Figure 8)†
MIN
tsu
th
Setup time, data
Hold time, data
MAX
UNIT
250
ns
0
ns
switching characteristics for BIOS ROM and LED interface (see Figure 8)†
PARAMETER
MIN
MAX
UNIT
td(EADV-EXLEL)
Delay time, address high byte valid to EXLE low (address high byte setup time for external
latch)
0
ns
td(EXLEL-EADZ)
Delay time, EXLE low to address high byte invalid (address high byte hold time for external
latch)
10
ns
Delay time, address low byte valid to EALE low (address low byte setup time for external latch)
0
ns
Delay time, EALE low to address low byte invalid (address low byte hold time for external latch)
10
ns
ta
Access time, address
288
† The EPROM interface, consisting of 11 pins, requires only two TTL ’373 latches to latch the high and low addresses.
ns
td(EADV-EALEL)
td(EALEL-EADZ)
EAD[7:0]
High
Address
Low
Address
Data
td(EADV-EXLEL)
td(EADV-EALEL)
td(EXLEL-EADZ)
td(EALEL-EADZ)
EXLE
EALE
ta
EOE
tsu
Figure 8. BIOS ROM and LED Interface Timing
22
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
th
ThunderLAN TNETE100
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS017B – APRIL 1995 – REVISED AUGUST 1996
switching characteristics for configuration EEPROM interface (see Figure 9)
PARAMETER
MIN
MAX
UNIT
0
100
kHz
EDCLK low to EDIO data in valid
0.3
3.5
µs
Time the bus must be free before a new transmission can start
4.7
µs
4
µs
4.7
µs
fCLK(EDCLK)
td(EDCLKL-EDIOV)
Clock frequency, EDCLK
td(EDIO free)
td(EDIOV-EDCLKL)
tw(L)
tw(H)
Low period, clock
High period, clock
4
µs
td(EDCLKH-EDIOV)
td(EDCLKL-EDIOX)
Delay time, EDCLK high to EDIO valid (start condition setup time)
4.7
µs
0
µs
td(EDIOV-EDCLKH)
tr
Delay time, EDIO valid to EDCLK high (data out setup time)
250
ns
tf
td(EDCLKH-EDIOH)
Fall time, EDIO and EDCLK
Delay time, EDCLK high to EDIO high (stop condition setup time)
4.7
µs
td(EDCLKL-EDIOX)
Delay time, EDCLK low to EDIO changing (data in hold time)
300
ns
Delay time, EDIO valid after EDCLK low (start condition hold time for EEPROM)
Delay time, EDCLK low to EDIO changing (data out hold time)
Rise time, EDIO and EDCLK
tf
tw(H)
1
µs
300
ns
tr
tw(L)
EDCLK
td(EDCLKL-EDIOX)
td(EDCLKH-EDIOV)
td(EDCLKH-EDIOH)
td(EDIOV-EDCLKL)
td(EDIOV-EDCLKH)
EDIO (OUT)
td(EDIO free)
td(EDCLKL-EDIOX)
td(EDCLKL-EDIOV)
EDIO (IN)
Figure 9. Configuration EEPROM Interface Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
23
ThunderLAN TNETE100
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS017B – APRIL 1995 – REVISED AUGUST 1996
timing requirements for crystal oscillator (see Figure 10)†
MIN
td(VDDH–FXTL1V)
TYP
Delay time from minimum VDD high level to first valid FXTL1V full swing period
(see Note 22)
tw(H)
tw(L)
Pulse duration at FXTL1 high
13
Pulse duration at FXTL1 low
13
tt
tc
Transition time of FXTL1
Cycle time, FXTL1
UNIT
100
ms
ns
ns
7
ns
50
ns
"0.01
Tolerance of FXTL1 input frequency
MAX
%
† The FXTL signal may be implemented by either connecting a 20-MHz crystal across the FXTL1 and FXTL2 pins or by driving the FXTL1 from
a 20-MHz crystal oscillator module.
NOTE 22: This specification is provided as an aid to board design. This specification is not guaranteed during manufacturing testing.
Minimum VDD High Level
VDD
tc
tw(H)
td(VDDH–FXTL1V)
tt
FXTL1
tw(L)
Figure 10. Crystal Oscillator Timing
24
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
tt
ThunderLAN TNETE100
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS017B – APRIL 1995 – REVISED AUGUST 1996
MECHANICAL DATA
PCE (S-PQFP-G***)
PLASTIC QUAD FLATPACK
144 PIN SHOWN
108
73
109
NO. OF
PINS***
A
144
22,75 TYP
160
25,35 TYP
72
0,38
0,22
0,13 M
0,65
37
144
1
0,16 NOM
36
Gage Plane
A
28,20
SQ
27,80
31,45
SQ
30,95
0,25
0,25 MIN
0°– 7°
1,03
0,73
3,60
3,20
Seating Plane
0,10
4,10 MAX
4040237 / B 10/94
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Thermally enhanced molded plastic package with a heat spreader (HSP)
Falls within JEDEC MS-022
The 144 PCE is identical to the 160 PCE except that four leads per corner are removed.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
25
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