WED3EG7233S-D3 -JD3 White Electronic Designs ADVANCED* 256MB – 2x16Mx72 DDR SDRAM UNBUFFERED FEATURES DESCRIPTION Double-data-rate architecture DDR200 and DDR266 The WED3EG7233S is a 2x16Mx72 Double Data Rate SDRAM memory module based on 128Mb DDR SDRAM component. The module consists of eighteen 16Mx8 DDR SDRAMs in 66 pin TSOP packages mounted on a 184 pin FR4 substrate. • JEDEC design specified Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input. Auto and self refresh Serial presence detect Dual Rank Power supply: 2.5V ± 0.20V JEDEC standard 184 pin DIMM package Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. * This product is under development, is not qualified or characterized and is subject to change or cancellation without notice. • JD3 PCB height: 30.48mm (1.20") NOTE: Consult factory for availability of: • RoHS compliant products • Vendor source control options • Industrial temperature option OPERATING FREQUENCIES DDR266 @CL=2 DDR266 @CL=2.5 DDR200 @CL=2 Clock Speed 133MHz 133MHz 100MHz CL-tRCD-tRP 2-2-2 2.5-3-3 2-2-2 White Electronic Designs Corp. reserves the right to change products or specifications without notice. May, 2005 Rev. 0 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED3EG7233S-D3 -JD3 ADVANCED PIN CONFIGURATION PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 SYMBOL VREF DQ0 VSS DQ1 DQS0 DQ2 VCC DQ3 NC NC VSS DQ8 DQ9 DQS1 VCCQ CK1 CK1# VSS DQ10 DQ11 CKE0 VCCQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VCCQ DQ19 A5 DQ24 VSS DQ25 DQS3 A4 VCC DQ26 DQ27 A2 VSS A1 CB0 CB1 VCC PIN 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 SYMBOL DQS8 A0 CB2 VSS CB3 BA1 DQ32 VCCQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 VCCQ WE# DQ41 CAS# VSS DQS5 DQ42 DQ43 VCC NC/CS2* DQ48 DQ49 VSS CK2# CK2 VCCQ DQS6 DQ50 DQ51 VSS VCCID DQ56 DQ57 VCC DQS7 DQ58 DQ59 VSS NC SDA SCL PIN 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 SYMBOL VSS DQ4 DQ5 VCCQ DQM0 DQ6 DQ7 VSS NC NC A13* VCCQ DQ12 DQ13 DQM1 VCC DQ14 DQ15 CKE1 VCCQ NC DQ20 A12 VSS DQ21 A11 DQM2 VCC DQ22 A8 DQ23 VSS A6 DQ28 DQ29 VCCQ DQM3 A3 DQ30 VSS DQ31 CB4 CB5 VCCQ CK0 CK0# PIN NAMES PIN 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 A0-A13 BA0-BA1 DQ0-DQ63 CB0-CB7 DQS0-DQS8 CK0, CK1, CK2 CK0#, CK1#, CK2# CKE0, CKE1 CS0#, CS1# RAS# CAS# WE# DQM0-DQM8 VCC VCCQ VSS VREF VCCSPD SDA SCL SA0-SA2 VCCID NC SYMBOL VSS DQM8 A10 CB6 VCCQ CB7 VSS DQ36 DQ37 VCC DQM4 DQ38 DQ39 VSS DQ44 RAS# DQ45 VCCQ CS0# CS1# DQM5 VSS DQ46 DQ47 CS3# VCCQ DQ52 DQ53 NC VCC DQM6 DQ54 DQ55 VCCQ NC DQ60 DQ61 VSS DQM7 DQ62 DQ63 VCCQ SA0 SA1 SA2 VCCSPD Address input (Multiplexed) Bank Select Address Data Input/Output Check bits Data Strobe Input/Output Clock Input Clock Input Clock Enable input Chip Select Input Row Address Strobe Column Address Strobe Write Enable Data-in-mask Power Supply Power Supply for DQS Ground Power Supply for Reference Serial EEPROM Power Supply Serial data I/O Serial clock Address in EEPROM VCC Indentification Flag No Connect * Not used White Electronic Designs Corp. reserves the right to change products or specifications without notice. May, 2005 Rev. 0 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED3EG7233S-D3 -JD3 White Electronic Designs ADVANCED FUNCTIONAL BLOCK DIAGRAM CS1# CS0# DQS4 DQM4 DQS0 DQM0 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 I/O I/O I/O I/O I/O I/O I/O I/O CS# DQS DM I/O I/O I/O I/O I/O I/O I/O I/O 7 6 1 0 5 4 3 2 CS# DQS DM 0 1 6 7 2 3 4 5 DQS1 DQM1 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 I/O I/O I/O I/O I/O I/O I/O I/O DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 I/O I/O I/O I/O I/O I/O I/O I/O DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 I/O I/O I/O I/O I/O I/O I/O I/O DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 I/O I/O I/O I/O I/O I/O I/O I/O DM CS# DQS I/O I/O I/O I/O I/O I/O I/O I/O 7 6 1 0 5 4 3 2 CS# DQS 0 1 6 7 2 3 4 5 DQS5 DQM5 DM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 I/O I/O I/O I/O I/O I/O I/O I/O CS# DQS DM I/O I/O I/O I/O I/O I/O I/O I/O 7 6 1 0 5 4 3 2 CS# DQS DM 0 1 6 7 2 3 4 5 DQS2 DQM2 DM CS# DQS I/O I/O I/O I/O I/O I/O I/O I/O 7 6 1 0 5 4 3 2 CS# DQS 0 1 6 7 2 3 4 5 DQS6 DQM6 DM DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 I/O I/O I/O I/O I/O I/O I/O I/O CS# DQS DM I/O I/O I/O I/O I/O I/O I/O I/O 7 6 1 0 5 4 3 2 CS# DQS DM 0 1 6 7 2 3 4 5 DQS3 DM CS# DQS I/O I/O I/O I/O I/O I/O I/O I/O 7 6 1 0 5 4 3 2 CS# DQS 0 1 6 7 2 3 4 5 DQS7 DQM7 DQM3 DM DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 I/O I/O I/O I/O I/O I/O I/O I/O CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 I/O I/O I/O I/O I/O I/O I/O I/O CS# DQS DM I/O I/O I/O I/O I/O I/O I/O I/O 7 6 1 0 5 4 3 2 CS# DQS DM 0 1 6 7 2 3 4 5 DM CS# DQS I/O I/O I/O I/O I/O I/O I/O I/O 7 6 1 0 5 4 3 2 CS# DQS 0 1 6 7 2 3 4 5 DQS8 DQM8 DM BA0 - BA1 A0 - A12 CS# DQS 7 6 1 0 5 4 3 2 DM I/O I/O I/O I/O I/O I/O I/O I/O CS# DQS Serial PD 0 1 6 7 2 3 4 5 SCL SDA WP A0 A1 A2 SA0 SA1 SA2 BA0-BA1 : DDR SDRAMs A0-A12 : DDR SDRAMs RAS# RAS# : DDR SDRAMs CAS# CAS# : DDR SDRAMs CKE1 CKE1 : DDR SDRAMs CKE0 CKE0 : DDR SDRAMs WE# W E # : DDR SDRAMs VCCSPD SPD VCC / VCCQ DDR SDRAMs V REF DDR SDRAMs VSS DDR SDRAMs Clock Input SDRAMs CK0 / CKO# CK1 / CK1# CK2 / CK2# 6 SDRAMs 6 SDRAMs 6 SDRAMs NOTE: All resistor values are 22 ohms unless otherwise specified. White Electronic Designs Corp. reserves the right to change products or specifications without notice. May, 2005 Rev. 0 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED3EG7233S-D3 -JD3 White Electronic Designs ADVANCED ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Units Voltage on any pin relative to VSS VIN, VOUT -0.5 to 3.6 V Voltage on VCC supply relative to VSS VCC, VCCQ -1.0 to 3.6 V TSTG -55 to +150 °C Power Dissipation PD 18 W Short Circuit Current IOS 50 mA Storage Temperature Note: Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC CHARACTERISTICS 0°C ≤ TA ≤ 70°C, VCC = 2.5V ± 0.2V Parameter Symbol Min Max Unit Supply Voltage VCC 2.3 2.7 V Supply Voltage VCCQ 2.3 2.7 V Reference Voltage VREF 1.15 1.35 V Termination Voltage VTT 1.15 1.35 V Input High Voltage VIH VREF + 0.15 VCCQ + 0.3 V Input Low Voltage VIL -0.3 VREF -0.15 V Output High Voltage VOH VTT + 0.76 — V Output Low Voltage VOL — VTT-0.76 V CAPACITANCE TA = 25°C. f = 1MHz, VCC = 2.5V ± 0.2V Parameter Symbol Max Unit Input Capacitance (A0-A12) CIN1 59 pF Input Capacitance (RAS#,CAS#,WE#) CIN2 59 pF Input Capacitance (CKE0) CIN3 32 pF Input Capacitance (CK0#,CK0) CIN4 56 pF Input Capacitance (CS0#) CIN5 32 pF Input Capacitance (DQM0-DQM8) CIN6 13 pF Input Capacitance (BA0-BA1) CIN7 59 pF Data input/output capacitance (DQ0-DQ63)(DQS) COUT 13 pF Data input/output capacitance (CB0-CB7) COUT 13 pF White Electronic Designs Corp. reserves the right to change products or specifications without notice. May, 2005 Rev. 0 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED3EG7233S-D3 -JD3 White Electronic Designs ADVANCED IDD SPECIFICATIONS AND TEST CONDITIONS Recommended operating conditions, 0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V Includes DDR SDRAM component only Parameter Symbol Conditions DDR266@CL=2.0 Max DDR266@CL=2.5 Max DDR200@CL=2 Max Units Operating Current IDD0 One device bank; Active - Precharge; tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. TBD 1845 1845 mA Operating Current IDD1 One device bank; Active-ReadPrecharge Burst = 2; tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA; Address and control inputs changing once per clock cycle. TBD 2205 2205 mA Precharge PowerDown Standby Current IDD2P All device banks idle; Power-down mode; tCK=tCK (MIN); CKE=(low) TBD 72 72 rnA Idle Standby Current IDD2F CS# = High; All device banks idle; tCK=tCK (MIN); CKE = high; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM. TBD 810 810 mA Active Power-Down Standby Current IDD3P One device bank active; Power-Down mode; tCK (MIN); CKE=(low) TBD 450 450 mA Active Standby Current IDD3N CS# = High; CKE = High; One device bank; Active-Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. TBD 900 900 mA Operating Current IDD4R Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; TCK= TCK (MIN); lOUT = 0mA. TBD 2250 2250 mA Operating Current IDD4W Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle. TBD 2115 2115 rnA Auto Refresh Current IDD5 tRC = tRC (MIN) TBD 3015 3015 mA Self Refresh Current IDD6 CKE ≤ 0.2V TBD 72 72 mA Operating Current IDD7A Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK (MIN); Address and control inputs change only during Active Read or Write commands. TBD 4050 4050 mA White Electronic Designs Corp. reserves the right to change products or specifications without notice. May, 2005 Rev. 0 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED3EG7233S-D3 -JD3 ADVANCED DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A IDD1 : OPERATING CURRENT : ONE BANK IDD7A : OPERATING CURRENT : FOUR BANKS 1. Typical Case : VCC=2.5V, T=25°C 1. Typical Case : VCC=2.5V, T=25°C 2. Worst Case : VCC=2.7V, T=10°C 2. Worst Case : VCC=2.7V, T=10°C 3. Only one bank is accessed with tRC (min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. IOUT = 0mA 3. Four banks are being interleaved with tRC (min), Burst Mode, Address and Control inputs on NOP edge are not changing. Iout=0mA 4. Timing Patterns : 4. Timing Patterns : • DDR200 (100 MHz, CL=2) : tCK=10ns, CL2, BL=4, tRCD=2*tCK, tRAS=5*tCK Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst • DDR266 (133MHz, CL=2.5) : tCK=7.5ns, CL=2.5, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst • DDR266 (133MHz, CL=2) : tCK=7.5ns, CL=2, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst • DDR200 (100 MHz, CL=2) : tCK=10ns, CL2, BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst • DDR266 (133MHz, CL=2.5) : tCK=7.5ns, CL=2.5, BL=4, tRRD=3*tCK, tRCD=3*tCK Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst • DDR266 (133MHz, CL=2) : tCK=7.5ns, CL2=2, BL=4, tRRD=2*tCK, tRCD=2*tCK Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst Legend: A = Activate, R = Read, W = Write, P = Precharge, N = NOP A (0-3) = Activate Bank 0-3 R (0-3) = Read Bank 0-3 White Electronic Designs Corp. reserves the right to change products or specifications without notice. May, 2005 Rev. 0 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED3EG7233S-D3 -JD3 White Electronic Designs ADVANCED DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS 0°C ≤ TA ≤ +70°C; VCC = +2.5V ± 0.2V, VCCQ = +2.5V ± 0.2V AC Characteristics 262 Parameter 265, 202 Symbol Min Max Min Max Units Access window of DQs from CK, CK# tAC -0.75 +0.75 -0.75 +0.75 ns CK high-level width tCH 0.45 0.55 0.45 0.55 tCK 16 CK low-level width tCL 0.45 0.55 0.45 0.55 tCK 16 CL=2.5 tCK (2.5) 7.5 13 7.5 13 ns 22 CL=2 tCK (2) 7.5 13 10 13 ns 22 DQ and DM input hold time relative to DQS tDH 0.5 0.5 ns 14,17 DQ and DM input setup time relative to DQS tDS 0.5 0.5 ns 14,17 ns 17 Clock cycle time DQ and DM input pulse width (for each input) tDIPW 1.75 Access window of DQS from CK, CK# tDQSCK -0.75 1.75 +0.75 -0.75 +0.75 ns DQS input high pulse width tDQSH 0.35 0.35 DQS input low pulse width tDQSL 0.35 0.35 DQS-DQ skew, DQS to last DQ valid, per group, per access tDQSQ Write command to first DQS latching transition tDQSS 0.75 DQS falling edge to CK rising - setup time tDSS 0.2 0.2 tCK DQS falling edge from CK rising - hold time tDSH 0.2 0.2 tCK Half clock period tHP tCH, tCL Data-out high-impedance window from CK, CK# tHZ 0.5 1.25 0.75 tCK tCK 0.5 ns 1.25 tCK tCH, tCL +0.75 Notes +0.75 13,14 ns 18 ns 8,19 Data-out low-impedance window from CK, CK# tLZ -0.75 -0.75 ns 8,20 Address and control input hold time (fast slew rate) tIHf 0.90 0.90 ns 6 Address and control input set-up time (fast slew rate) tISf 0.90 0.90 ns 6 Address and control input hold time (slow slew rate) tIHs 1 1 ns 6 6 Address and control input setup time (slow slew rate) tISs 1 1 ns Address and control input pulse width (for each input) tIPW 2.2 2.2 ns LOAD MODE REGISTER command cycle time tMRD 15 15 ns tHP-tQHS DQ-DQS hold, DQS to first DQ to go non-valid, per access tQH Data hold skew factor tQHS tHP-tQHS ACTIVE to PRECHARGE command tRAS 45 ACTIVE to READ with Auto precharge command tRAP 20 20 ns ACTIVE to ACTIVE/AUTO REFRESH command period tRC 65 65 ns AUTO REFRESH command period tRFC 75 75 ns 0.75 120,000 45 ns 0.75 ns 120,000 ns 13,14 15 21 White Electronic Designs Corp. reserves the right to change products or specifications without notice. May, 2005 Rev. 0 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED3EG7233S-D3 -JD3 White Electronic Designs ADVANCED DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (continued) 0°C ≤ TA ≤ +70°C; VCC = +2.5V ± 0.2V, VCCQ = +2.5V ± 0.2V AC Characteristics Parameter ACTIVE to READ or WRITE delay PRECHARGE command period 262 Symbol Min tRCD 20 265, 202 Max Min Max 20 Units Notes ns tRP 20 DQS read preamble tRPRE 0.9 1.1 0.9 1.1 tCK DQS read postamble tRPST 0.4 0.6 0.4 0.6 tCK ACTIVE bank a to ACTIVE bank b command tRRD 15 15 ns DQS write preamble tWPRE 0.25 0.25 tCK DQS write preamble setup time tWPRES 0 0 ns 10,11 DQS write postamble tCK 9 tWPST 0.4 Write recovery time tWR 15 Internal WRITE to READ command delay tWTR 1 Data valid output window NA REFRESH to REFRESH command interval tREFC 20 0.6 ns 0.4 0.6 15 ns 1 tQH-tDQSQ tCK tQH-tDQSQ 70.3 7.8 ns 13 70.3 μs 12 7.8 μs 12 Average periodic refresh interval tREFI Terminating voltage delay to VCC tVTD Exit SELF REFRESH to non-READ command tXSNR 75 75 ns Exit SELF REFRESH to READ command tXSRD 200 200 tCK 0 0 19 ns White Electronic Designs Corp. reserves the right to change products or specifications without notice. May, 2005 Rev. 0 8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED3EG7233S-D3 -JD3 White Electronic Designs ADVANCED ORDERING INFORMATION FOR JD3 Part Number Speed CAS Latency tRCD tRP Height* WED3EG7233S262JD3 133MHz/266Mb/s 2 2 2 30.48 (1.20") WED3EG7233S265JD3 133MHz/266Mb/s 2.5 3 3 30.48 (1.20") WED3EG7233S202JD3 100MHz/200Mb/s 2 2 2 30.48 (1.20") NOTES: • Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant) • Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) • Consult factory for availability of industrial temperature (-40°C to 85°C) option PACKAGE DIMENSIONS FOR JD3 133.48 (5.255" MAX.) 131.34 (5.171") 128.95 (5.077") 3.81 (0.150) MAX 3.99 (0.157 (2x)) 30.48 (1.20) MAX 17.78 (0.700) 10.01 (0.394) 6.35 (0.250) 64.77 (2.550) 6.35 (0.250) 49.53 (1.950) 1.27 (0.050 TYP.) 1.78 (0.070) 3.99 (0.157) (MIN) 2.31 (0.091) (2x) 3.00 (0.118) (4x) 1.27 ± 0.10 (0.050 ± 0.004) * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) White Electronic Designs Corp. reserves the right to change products or specifications without notice. May, 2005 Rev. 0 9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED3EG7233S-D3 -JD3 White Electronic Designs ADVANCED ORDERING INFORMATION FOR D3 Part Number Speed CAS Latency tRCD tRP Height* WED3EG7233S262D3 133MHz/266Mb/s 2 2 2 30.48 (1.20") WED3EG7233S265D3 133MHz/266Mb/s 2.5 3 3 30.48 (1.20") WED3EG7233S202D3 100MHz/200Mb/s 2 2 2 30.48 (1.20") NOTES: • Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant) • Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) • Consult factory for availability of industrial temperature (-40°C to 85°C) option PACKAGE DIMENSIONS FOR D3 133.48 (5.255" MAX.) 131.34 (5.171") 128.95 (5.077") 3.81 (0.150) MAX 3.99 (0.157 (2x)) 30.48 (1.20) MAX 17.78 (0.700) 10.01 (0.394) 6.35 (0.250) 64.77 (2.550) 6.35 (0.250) 49.53 (1.950) 1.27 (0.050 TYP.) 1.78 (0.070) 3.99 (0.157) (MIN) 2.31 (0.091) (2x) 3.00 (0.118) (4x) 1.27 ± 0.10 (0.050 ± 0.004) * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) White Electronic Designs Corp. reserves the right to change products or specifications without notice. May, 2005 Rev. 0 10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED3EG7233S-D3 -JD3 White Electronic Designs ADVANCED Document Title 256MB – 2x16Mx72 DDR SDRAM UNBUFFERED Revision History Rev # History Release Date Status Rev A Created Datasheet 5-22-02 Advanced 0.1 Updated all specs (IDD, CAP, AC's) 5-05 Preliminary Rev 0 0.2 Added JEDEC standard PCB (JD3) option 0.3 D3 PCB option is "NOT RECOMMENDED FOR NEW DESIGNS" 0.4 Moved from Advanced to Preliminary White Electronic Designs Corp. reserves the right to change products or specifications without notice. May, 2005 Rev. 0 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com