White Electronic Designs WV3EG264M72ESFR-D4 ADVANCED* 1GB – 2x64Mx72 DDR SDRAM REGISTERED, w/PLL FEATURES DESCRIPTION 200-pin SO-DIMM, dual in-line memory module Fast data transfer rates: PC2100 and PC2700 Utilizes 266 and 333 Mb/s DDR SDRAM components The WV3EG264M72ESFR is a 2x64Mx72 Double Data Rate DDR SDRAM high density module. This memory module consists of eighteen 64Mx8 bit with 4 banks DDR Synchronous DRAMs in FBGA packages, mounted on a 200-pin SO-DIMM FR4 substrate. VCC = VCCQ = 2.5V ±0.2V Bidirectional data strobe (DQS) option Differential clock inputs (CK and CK#) DLL to align DQ and DQS transitions with CK Programmable burst: length (2, 4, 8) Programmable READ# latency (CL): 2 and 2.5 (clock) Serial Presence Detect (SPD) with EEPROM Auto and self refresh: 64ms/ 8,192 cycle refresh Gold edge contacts Dual Rank Package option * This product is under development, is not qualified or characterized and is subject to change or cancellation without notice. NOTE: Consult factory for availability of: • RoHS compliant products • Vendor source control options • Industrial temperature option • 200 Pin SO-DIMM • PCB – 31.75mm (1.25") Max OPERATING FREQUENCIES August 2005 Rev. 0 DDR333@CL = 2.5 DDR266@CL = 2 DDR266@CL = 2.5 Clock Speed 166MHz 133MHz 133MHz CL-tRCD-tRP 2.5-3-3 2-2-2 2.5-3-3 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3EG264M72ESFR-D4 ADVANCED PIN CONFIGURATION PIN NAMES Pin No. Symbol Pin No. Symbol Pin No. Symbol Pin No. Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VREF VREF VSS VSS DQ0 DQ4 DQ1 DQ5 VCC VCC DQS0 DM0 DQ2 DQ6 VSS VSS DQ3 DQ7 DQ8 DQ12 VCC VCC DQ9 DQ13 DQS1 DM1 VSS VSS DQ10 DQ14 DQ11 DQ15 VCC VCC CK0 VCC CK0# VSS VSS VSS DQ16 DQ20 DQ17 DQ21 VCC VCC DQS2 DM2 DQ18 DQ22 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 VSS VSS DQ19 DQ23 DQ24 DQ28 VCC VCC DQ25 DQ29 DQS3 DM3 VSS VSS DQ26 DQ30 DQ27 DQ31 VCC VCC CB0 CB4 CB1 CB5 VSS VSS DQS8 DM8 CB2 CB6 VCC VCC CB3 CB7 NC RESET# VSS VSS NC VSS NC VCC VCC VCC CKE1 CKE0 NC NC A12 A11 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 A9 A8 VSS VSS A7 A6 A5 A4 A3 A2 A1 A0 VCC VCC A10/AP BA1 BA0 RAS# WE# CAS# CS0# CS1# NC NC VSS VSS DQ32 DQ36 DQ33 DQ37 VCC VCC DQS4 DM4 DQ34 DQ38 VSS VSS DQ35 DQ39 DQ40 DQ44 VCC VCC DQ41 DQ45 DQS5 DM5 VSS VSS 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 DQ42 DQ46 DQ43 DQ47 VCC VCC VCC NC VSS NC VSS VSS DQ48 DQ52 DQ49 DQ53 VCC VCC DQS6 DM6 DQ50 DQ54 VSS VSS DQ51 DQ55 DQ56 DQ60 VCC VCC DQ57 DQ61 DQS7 DM7 VSS VSS DQ58 DQ62 DQ59 DQ63 VCC VCC SDA SA0 SCL SA1 VCCSPD SA2 NC NC August 2005 Rev. 0 Pin Name A0-A12 BA0, BA1 DQ0-DQ63 CB0-CB7 DQS0-DQS8 CK0,CK0# CKE0, CKE1 CS0#, CS1# RAS# CAS# WE# VCC VCCQ VSS SA0-SA2 SDA VREF DM0-DM8 VCCSPD SCL RESET# NC 2 Function Address Inputs SDRAM Bank Address Data Input/Output Check Bits Data strobes Clock inputs, positive/negative Clock enable input Chip select input Row Address Strobe Column Address Strobe Write Enable Core Power I/O Power Ground EEPROM address Serial Data Input/Output Input/Output Reference Data-in mask Serial EEPROM power supply Serial Presence Detect(SPD) Clock Input Reset enable Spare pins, No connect White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3EG264M72ESFR-D4 ADVANCED FUNCTIONAL BLOCK DIAGRAM CS1# CS0# DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS DM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS DM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS DM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS DM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 S0# S0# S0# S0# DQS DM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 DQS DM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 DQS DM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 DQS DM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 S1# S1# S1# S1# DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS DM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 DQS5 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS DM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS DM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 DQS7 DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQS DM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 DQS8 DM8 DM CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 CS# DQS DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DM DQ DQ DQ DQ DQ DQ DQ DQ RAS# CAS# CKE0 CKE1 WE# PCK PCK# T E R DQS DM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 S0# DQS DM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 S0# SCL WP 0 1 2 3 4 5 6 7 S1# S1# S1# SDA A0 A1 A2 SA1 SA2 120 Ohms R E G I S DQS DM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 S0# S1# Serial PD CS# DQS CK0 CK0# CS0# CS1# BA0-BA1 A0-A12 DQS DM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 S0# RCS0# RCS1# RBA0-RBA1 RA0-RA12 BA0-BA1: DDR SDRAMs A0-A12: DDR SDRAMs RRAS# RCAS# RCKE0 RCKE1 RWE# RAS#: DDR SDRAMs CAS#: DDR SDRAMs CKE: DDR SDRAMs CKE: DDR SDRAMs WE#: DDR SDRAMs RESET# VCCSPD PLL DDR SDRAM X 2 DDR SDRAM X 2 DDR SDRAM X 2 DDR SDRAM X 2 DDR SDRAM X 2 DDR SDRAM X 2 DDR SDRAM X 2 DDR SDRAM X 2 DDR SDRAM X 2 REGISTER X 2 SPD VCCQ/VCC DDR SDRAMs VREF DDR SDRAMs VSS DDR SDRAMs NOTE: All resistor values are 22 ohms unless otherwise specified. August 2005 Rev. 0 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3EG264M72ESFR-D4 ADVANCED DC OPERATING CONDITIONS 0°C TA 70°C Parameter Supply voltage (for device with a nominal VCC of 2.5V) I/O Supply voltage I/O Reference voltage I/O Termination voltage (system) Input logic high voltage Input logic low voltage Input Voltage Level, CK and CK# inputs Input Differential Voltage, CK and CK# inputs Input leakage current Output leakage current Output High Current(Normal strengh driver); VOUT = VTT + 0.84V Output High Current(Normal strengh driver); VOUT = VTT - 0.84V Output High Current(Half strengh driver); VOUT = VTT + 0.45V Output High Current(Half strengh driver); VOUT = VTT - 0.45V Symbol VCC VCCQ VREF VTT VIH(DC) VIL(DC) VIN(DC) VID(DC) II IOZ IOH IOL IOH IOL Min 2.3 2.3 0.49*VCCQ VREF-0.04 VREF+0.15 -0.3 -0.3 0.3 -2 -5 -16.8 16.8 -9 9 Max 2.7 2.7 0.51*VCCQ VREF+0.04 VCCQ+0.3 VREF-0.15 VCCQ+0.3 VCCQ+0.6 2 5 Unit Note V V V V V V V uA uA mA mA mA mA 1 2 4 4 3 Notes: 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled to VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of ≤ 3nH. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on CK#. 4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHz. ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to VSS Voltage on VCC & VCCQ pin relative to VSS Storage Temperature Operating Temperature Power dissipation – 1GB single mezzanine memory Short circuit current Symbol VIN, VOUT VCC, VCCQ TSTG TA PD IOS Value -0.5 ~ 3.3 -1.0 ~ 3.6 -55 ~ +150 0 ~ +70 18 50 Unit V V °C °C W mA NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. CAPACITANCE VCC 2.5V, VCCQ = 2.5V ±0.2V, TA = 25°C, f = 1MHz Parameter Input capacitance (A0 ~ A12, BA0 ~ BA1,RAS#,CAS#, WE# ) Input capacitance (CKE0, CKE1) Input capacitance ( CS0#, CS1#) Input capacitance ( CLK0, CLK0#) Input capacitance ( DM0 ~ DM8) Data & DQS input/output capacitance (DQ0~DQ63) Data input/output capacitance (CB0 ~ CB7) August 2005 Rev. 0 Symbol CIN1 CIN2 CIN3 CIN4 CIN5 COUT1 COUT2 4 Min 9 9 9 11 10 10 10 Max 11 11 11 12 11 11 11 Units pF pF pF pF pF pF pF White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3EG264M72ESFR-D4 ADVANCED DDR IDD SPECIFICATIONS AND CONDITIONS 0°C ≤ TCASE < +70°C; VCCQ = +2.5V ± 0.2V, VCC = +2.5V ± 0.2V Symbol Conditions 335 262 265 Unit IDD0 Operating current - One bank Active-Precharge; tRC = tRC(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ, DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 1,215 1,215 1,080 mA IDD1 Operating current - One bank operation; One bank open, BL = 4, Reads - Refer to the following page for detailed test condition 1,485 1,485 1,350 mA IDD2P Percharge power-down standby current; All banks idle; power - down mode; CKE = <VIL(max); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; VIN = VREF for DQ, DQS and DM 90 90 90 mA IDD2F Precharge Floating standby current; CS# > = VIH(min);All banks idle; CKE > = VIH(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM 810 810 720 mA IDD3P Active power - down standby current; one bank active; power-down mode; CKE = < VIL(max); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; VIN = VREF for DQ, DQS and DM 630 630 540 mA IDD3N Active standby current; CS# > = VIH(min); CKE> = VIH(min); one bank active; active - precharge; tRC = tRASmax; tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ, DQS and DM inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle 900 900 810 mA IDD4R Operating current - burst read; Burst length = 2; reads; continguous burst; One bank active; address and control inputs changing once per clock cycle; CL = 2 at tCK = 100Mhz for DDR200, CL = 2 at tCK = 133Mhz for DDR266A, CL = 2.5 at tCK = 133Mhz for DDR266B ; 50% of data changing at every burst; lOUT = 0 m A 1.530 1.530 1,350 mA IDD4W Operating current - burst write; Burst length = 2; writes; continuous burst; One bank active address and control inputs changing once per clock cycle; CL = 2 at tCK = 100Mhz for DDR200, CL = 2 at tCK = 133Mhz for DDR266A, CL = 2.5 at tCK = 133Mhz for DDR266B ; DQ, DM and DQS inputs changing twice per clock cycle, 50% of input data changing at every burst 1,440 1,440 1,260 mA IDD5 Auto refresh current; tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for DDR266A & DDR266B at 133Mhz; distributed refresh 5,220 5,220 5,040 mA IDD6 Self refresh current; CKE = < 0.2V; External clock should be on; tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B 90 90 90 mA IDD7A Orerating current - Four bank operation; Four bank interleaving with BL = 4 -Refer to the following page for detailed test condition 3,690 3,645 3,195 mA Typical case: VCC = 2.5V, T = 25°C Worst case: VCC = 2.7V, T = 10°C Note: IDD specifications are based on Micron components. Other DRAM manufacturers specificaitons may be different. August 2005 Rev. 0 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3EG264M72ESFR-D4 ADVANCED AC TIMING PARAMETERS 0°C ≤ TCASE < +70°C; VCCQ = +2.5V ± 0.2V, VCC = +2.5V ± 0.2V Parameter Symbol Row cycle time Refresh row cycle time Row active time RAS# to CAS# delay Row precharge time Row active to Row active Write recovery time Last data in to Read command Col. address to Col. address Clock cycle time Clock high level width Clock low level width DQS-out access time from Output data access time Data strobe edge to ouput Read Preamble Read Postamble CK to valid DQS-in DQS-in setup time DQS-in hold time DQS falling edge to CK risDQS falling edge from CK DQS-in high level width DQS-in low level width DQS-in cycle time Address and Control Input Address and Control Input Address and Control Input Address and Control Input Data-out high impedence time from CK/CK# Data-out low impedence time from CK/CK# Input Slew Rate (for input) Input Slew Rate (for I/O pins) Output Slew Rate (x4,x8) Output Slew Rate Matching tRC tRFC tRAS tRCD tRP tRRD tWR tWTR tCCD CL=2.0 CL=2.5 tCK tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRE tWPRE tDSS tDSH tDQSH tDQSL tDSC tIS tIH tIS tIH tHZ tLZ tSL(I) tSL(IO) tSL(O) tSLMR 335 Min 60 72 42 18 18 12 15 1 1 7.5 6 0.45 0.45 -0.6 -0.7 — 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.75 0.75 0.8 0.8 -0.7 0.5 0.5 1.0 0.67 262 Max 70K 12 12 0.55 0.55 +0.6 +0.7 0.4 1.1 0.6 1.25 1.1 +0.7 +0.7 4.5 1.5 Min 65 75 45 20 20 15 15 1 1 7.5 7.5 0.45 0.45 -0.75 -0.75 — 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 0.9 1.0 1.0 -0.75 0.5 0.5 1.0 0.67 265 Max 120K 12 12 0.55 0.55 +0.75 +0.75 0.5 1.1 0.6 1.25 1.1 +0.75 +0.75 4.5 1.5 Min 65 75 45 20 20 15 15 1 1 10 7.5 0.45 0.45 -0.75 -0.75 — 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 0.9 1.0 1.0 -0.75 0.5 0.5 1.0 0.67 Max 120K 12 12 0.55 0.55 +0.75 +0.75 0.5 1.1 0.6 1.25 1.1 +0.75 +0.75 4.5 1.5 Unit ns ns ns ns ns ns ns tCK tCK ns ns tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK tCK tCK ns ns ns ns ns ns V/ns V/ns V/ns Note: AC specifications are based on Micron components. Other DRAM manufacturers specificaitons may be different. August 2005 Rev. 0 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3EG264M72ESFR-D4 ADVANCED AC TIMING PARAMETERS 0°C ≤ TCASE < +70°C; VCCQ = +2.5V ± 0.2V, VCC = +2.5V ± 0.2V 335 Parameter 262 265 Symbol Unit Min Max Min Max Min Max tMRD 12 15 15 ns DQ & DM setup time to DQS tDS 0.45 0.5 0.5 ns DQ & DM hold time to DQS tDH 0.45 0.5 0.5 ns Mode register set cycle time Control & Address input tIPW 2.2 2.2 2.2 ns DQ & DM input pulse width tDIPW 1.75 1.75 1.75 ns Power down exit time tPDEX 6 7.5 7.5 ns Exit self refresh to non-Read tXSNR 75 75 75 ns 200 200 200 Exit self refresh to read command tXSRD Refresh interval time tREFI Output DQS valid window tQH tHP-tQHS — tHP-tQHS tHP tCLmin or tCHmin — tCLmin or tCHmin 0.6 Clock half period 7.8 tCK 7.8 tHP-tQHS — ns — tCLmin or tCHmin — ns Data hold skew factor tQHS tWPST 0.4 Active to Read with Auto precharge command tRAP 15 15 20 Autoprecharge write recovery + Precharge time tDAL (tWR/tCK) + (tRP/tCK) (tWR/tCK) + (tRP/tCK) (tWR/tCK) + (tRP/tCK) 0.75 0.4 us — DQS write postamble time 0.5 7.8 0.6 0.4 0.75 ns 0.6 tCK tCK Note: AC specifications are based on Micron components. Other DRAM manufacturers specificaitons may be different. SERIAL PRESENT DETECT INFORMATION Byte # Function described Function Supported 265 262 335 Hex value 265 262 0 Defines # of Bytes written into serial memory at module manufacturer 1 Total # of Bytes of SPD memory device 2 Fundamental memory type 3 # of row address on this assembly 4 # of column address on this assembly 5 # of module Rows on this assembly 6 Data width of this assembly 64 bits 48h 7 Data width of this assembly — 00h 8 VDDQ and interface standard of this assembly 9 DDR SDRAM cycle time at CAS Latency =2.5 7.5ns 7ns 6ns 75h 70h 60h 10 DDR SDRAM Access time from clock at CL=2.5 ±0.75 ±0.75 ±0.7 75h 75h 70h 11 DIMM configuration type(Non-parity, Parity, ECC) 12 Refresh rate & type August 2005 Rev. 0 128bytes 80h 256bytes (2K-bit) 08h 335 SDRAM DDR 07h 13 0Dh 11 0Bh 2 Row 02h SSTL 2.5V 7 04h ECC 02h 7.8us & Self refresh 82h White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3EG264M72ESFR-D4 ADVANCED SERIAL PRESENT DETECT INFORMATION (cont'd) Byte # Function described Function Supported 265 262 Hex value 335 265 262 13 Primary DDR SDRAM width x8 08h 14 Error checking DDR SDRAM data width x8 08h 15 Minimum clock delay for back-to-back random column address 16 DDR SDRAM device attributes: Burst lengths supported tCCD = 1CLK 01h 2,4,8 0Eh 17 DDR SDRAM device attributes: # of banks on each DDR SDRAM 4 banks 04h 18 DDR SDRAM device attributes: CAS Latency supported 2,2.5 0Ch 19 DDR SDRAM device attributes: CS Latency 0CLK 01h 20 DDR SDRAM device attributes: WE Latency 1CLK 02h 21 DDR SDRAM module attributes Registered address & control inputs and On-card DLL 26h 22 DDR SDRAM device attributes: General +/-0.2V voltage tolerance C0h 335 23 DDR SDRAM cycle time at CL =2 10ns 7.5ns 7.5ns A0h 75h 75h 24 DDR SDRAM Access time from clock at CL =2 ±0.75 ±0.75 ±0.7 75h 75h 70h 25 DDR SDRAM cycle time at CL =1.5 — — — 00h 26 DDR SDRAM Access time from clock at CL =1.5 — — — 00h 27 Minimum row precharge time (=tRP) 20ns 20ns 18ns 50h 50h 28 Minimum row activate to row active delay (=tRRD) 15ns 15ns 12ns 3Ch 3Ch 30h 29 Minimum RAS to CAS delay (=tRCD) 20ns 20ns 18ns 50h 50h 48h 30 Minimum active to precharge time (=tRAS) 45ns 45ns 42ns 2Dh 2Dh 2Ah 31 Module ROW density 32 Command and address signal input setup time 0.9ns 0.9ns 0.8ns A0h A0h 80h 33 Command and address signal input hold time 0.9ns 0.9ns 0.8ns A0h A0h 80h 34 Data signal input setup time 0.5ns 0.5ns 0.45ns 50h 50h 45h Data signal input hold time 0.5ns 0.5ns 0.45ns 50h 50h 45h 35 36-40 512MB Superset information (may be used in future) 48h 80h — 00h 41 DDR SDRAM Minimum Active to Active/Auto Refresh Time (tRC) 65ns 65ns 60ns 41h 41h 3Ch 42 DDR SDRAM Minimim Auto-Refresh to Active/Auto-Refresh Commmand Period (tRFC) 75ns 75ns 72ns 4Bh 4Bh 48h 43 DDR SDRAM Maximum Device Cycle Time (tCK max) 13ns 13ns 12ns 34h 34h 30h 44 DDR SDRAM DQS-DQ Skew for DQS and associated DQ signals (tDQSQmax) 0.50ns 0.50ns 0.45ns 50h 50h 45h 45 DDR SDRAM Read Data Hold Skew Factor (tQHS) 0.75ns 0.75ns 0.50ns 75h 75h 50h 46 Reserved 00 00 00 00h 00h 00h 47 DIMM Height 48-61 62 63 64 - 127 August 2005 Rev. 0 Superset information (may be used in future) SPD data revision code Standard/Low profile 01h — 00h Initial release 10h Checksum for Bytes 0 ~ 62 — Manufacturer INFO — 8 69h 39h 6Fh 00h White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3EG264M72ESFR-D4 ADVANCED ORDERING INFORMATION FOR D4 Part Number Speed CAS Latency tRCD tRP Height* WV3EG264M72ESFR335D4-x 166MHz/333Mb/s 2.5 3 3 31.75mm (1.25") WV3EG264M72ESFR262D4-x 133MHz/266Mb/s 2 2 2 31.75mm (1.25") WV3EG264M72ESFR265D4-x 133MHz/266Mb/s 2.5 3 3 31.75mm (1.25") NOTES: • Consult Factory for availability of RoHS compliant products. (“G” = RoHS Compliant) • Vendor specific part numbers are used to provide memory component source control. The place holder for this is shown as a lower case "-x" in the part numbers above and is to be replaced with respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) • Consult factory for availability of industrial temperature (-40°C to 85°C) option PACKAGE DIMENSIONS FOR D4 67.60 (2.661) 3.80 (0.150) MAX. Full R 2x 63.60 (2.504) 4.00 ±0.10 (0.158 ±0.039) 31.75 (1.25) 20 (0.787) 6.0 0.236 1 39 41 199 11.40 (0.449) 2.15 (0.085) 2.45 (0.098) 4.20 (0.165) 47.40 (1.866) 4.00 (0.158) MIN. 2- 1.80 (0.071) 2.40 (0.094) 1.8 (0.071) 1.00 ±0.1 (0.04 ±0.0039) 1.0 ± 0.1 (0.04 ± 0.0039) 0.60 (0.024) 0.45 ±0.03 (0.018 ±0.001) 0.25 (0.01) 2.55 Min (0.102 Min) 4.00 ±0.10 (0.158 ±0.039) * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) Tolerances: 0.15 (0.006) unless otherwise specified August 2005 Rev. 0 9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3EG264M72ESFR-D4 ADVANCED PART NUMBERING GUIDE WV 3 E G 264M 72 E S F R xxx D4 -x G WEDC MEMORY DDR 2 GOLD DEPTH (Dual Rank) BUS WIDTH x8 2.5V FBGA REGISTERED SPEED (MHz) PACKAGE 200 PIN SO-DIMM COMPONENT VENDOR NAME (M = Micron) (S = Samsung) G = RoHS COMPLIANT August 2005 Rev. 0 10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3EG264M72ESFR-D4 ADVANCED Document Title 1GB – 2x64Mx72 DDR SDRAM REGISTERED, w/PLL Revision History Rev # History Release Date Status Rev 0 Created August 2005 Advanced August 2005 Rev. 0 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com