AGILENT HCPL316J

2.0 Amp Gate Drive Optocoupler
with Integrated (VCE) Desaturation
Detection and Fault Status
Feedback
Technical Data
HCPL-316J
Features
• “Soft” IGBT Turn-off
• Integrated Fail-Safe IGBT
Protection
– Desat (VCE ) Detection
– Under Voltage Lock-Out
Protection (UVLO) with
Hysterisis
• User Configurable:
Inverting, Non-inverting,
Auto-Reset, Auto-Shutdown
• Drive IGBTs up to
IC = 150 A, VCE = 1200 V
• Optically Isolated, FAULT
Status Feedback
• SO-16 Package
• CMOS/TTL Compatible
• 500 ns Max. Switching
Speeds
• Wide Operating VCC Range:
15 to 30 Volts
• -40°C to +100 °C Operating
Temperature Range
• 15 kV/µs Min. Common Mode
Rejection (CMR) at
VCM = 1500 V
• Regulatory Approvals: UL,
CSA, IEC/EN/DIN EN 607475-2 (891 Vpeak Working
Voltage)
Fault Protected IGBT Gate Drive
+HV
ISOLATION
BOUNDARY
ISOLATION
BOUNDARY
ISOLATION
BOUNDARY
HCPL - 316J
HCPL - 316J
HCPL - 316J
3-PHASE
INPUT
M
HCPL - 316J
HCPL - 316J
ISOLATION
BOUNDARY
HCPL - 316J
ISOLATION
BOUNDARY
ISOLATION
BOUNDARY
HCPL - 316J
ISOLATION
BOUNDARY
–HV
FAULT
MICRO-CONTROLLER
Agilent’s 2.0 Amp Gate Drive Optocoupler with Integrated Desaturation (VCE) Detection and Fault Status
Feedback makes IGBT VCE fault protection compact, affordable, and easy-to-implement while
satisfying worldwide safety and regulatory requirements.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to
prevent damage and/or degradation which may be induced by ESD.
2
Typical Fault Protected
IGBT Gate Drive Circuit
The HCPL-316J is an easy-to-use,
intelligent gate driver which
makes IGBT VCE fault protection
compact, affordable, and easy-toimplement. Features such as user
configurable inputs, integrated
VCE detection, under voltage
lockout (UVLO), “soft” IGBT
turn-off and isolated fault feedback provide maximum design
flexibility and circuit protection.
HCPL-316J
1
VIN+
VE
16
2
VIN-
VLED2+
15
3
VCC1
DESAT
14
*
CBLANK
100 Ω
+
–
µC
RF
4
GND1
5
VCC2
13
RESET
VC
12
6
FAULT
VOUT
11
7
VLED1+
VEE
10
8
VLED1-
VEE
9
DDESAT
+
+
–
*
VF
–
+
RG
VCE
–
– *
+
+
RPULL-DOWN
VCE
–
* THESE COMPONENTS ARE ONLY REQUIRED WHEN NEGATIVE GATE DRIVE IS IMPLEMENTED.
Figure 1. Typical Desaturation Protected Gate Drive Circuit, Non-Inverting.
Description of Operation
during Fault Condition
1. DESAT terminal monitors the
IGBT VCE voltage through
DDESAT.
2. When the voltage on the
DESAT terminal exceeds
7 volts, the IGBT gate voltage
(VOUT) is slowly lowered.
3. FAULT output goes low,
notifying the microcontroller
of the fault condition.
4. Microcontroller takes
appropriate action.
Output Control
The outputs (VOUT and FAULT)
of the HCPL-316J are controlled
by the combination of VIN, UVLO
and a detected IGBT Desat
condition. As indicated in the
below table, the HCPL-316J can
be configured as inverting or
non-inverting using the VIN+ or
VIN- inputs respectively. When an
inverting configuration is desired,
VIN+ must be held high and VINtoggled. When a non-inverting
configuration is desired, V INmust be held low and VIN+
toggled. Once UVLO is not active
(VCC2 - V E > VUVLO ), VOUT is
allowed to go high, and the
VIN+
VIN-
UVLO
(VCC2 - VE)
X
X
Low
X
High
X
X
X
High
Low
Active
X
X
X
Not Active
DESAT (pin 14) detection feature
of the HCPL-316J will be the
primary source of IGBT protection.
UVLO is needed to ensure DESAT
is functional. Once VUVLO+ > 11.6
V, DESAT will remain functional
until VUVLO- < 12.4 V. Thus, the
DESAT detection and UVLO
features of the HCPL-316J work in
conjunction to ensure constant
IGBT protection.
Desat Condition
Detected on
Pin 14
X
Yes
X
X
No
Pin 6
(FAULT)
Output
X
Low
X
X
High
VOUT
Low
Low
Low
Low
High
3
Product Overview
Description
The HCPL-316J is a highly
integrated power control device
that incorporates all the
necessary components for a
complete, isolated IGBT gate
drive circuit with fault protection
and feedback into one SO-16
package. TTL input logic levels
allow direct interface with a
microcontroller, and an optically
isolated power output stage
drives IGBTs with power ratings
of up to 150 A and 1200 V. A
high speed internal optical link
minimizes the propagation delays
between the microcontroller and
the IGBT while allowing the two
systems to operate at very large
common mode voltage
differences that are common in
industrial motor drives and other
power switching applications. An
VLED1+
output IC provides local
protection for the IGBT to
prevent damage during
overcurrents, and a second
optical link provides a fully
isolated fault status feedback
signal for the microcontroller. A
built in “watchdog” circuit
monitors the power stage supply
voltage to prevent IGBT caused
by insufficient gate drive
voltages. This integrated IGBT
gate driver is designed to
increase the performance and
reliability of a motor drive
without the cost, size, and
complexity of a discrete design.
designed on a bipolar process,
while the output Detector IC is
designed manufactured on a high
voltage BiCMOS/Power DMOS
process. The forward optical
signal path, as indicated by
LED1, transmits the gate control
signal. The return optical signal
path, as indicated by LED2,
transmits the fault status
feedback signal. Both optical
channels are completely
controlled by the input and
output ICs respectively, making
the internal isolation boundary
transparent to the
microcontroller.
Two light emitting diodes and two
integrated circuits housed in the
same SO-16 package provide the
input control circuitry, the output
power stage, and two optical
channels. The input Buffer IC is
Under normal operation, the
input gate control signal directly
controls the IGBT gate through
the isolated output detector IC.
LED2 remains off and a fault
latch in the input buffer IC is
disabled. When an IGBT fault is
detected, the output detector IC
immediately begins a “soft”
shutdown sequence, reducing the
IGBT current to zero in a
controlled manner to avoid
potential IGBT damage from
inductive overvoltages.
Simultaneously, this fault status is
transmitted back to the input
buffer IC via LED2, where the
fault latch disables the gate
control input and the active low
fault output alerts the
microcontroller.
VLED1-
7
8
13
INPUT IC
VIN+
VIN-
12
1
LED1
2
D
R
I
V
E
R
UVLO
11
14
VCC1
VOUT
DESAT
3
DESAT
9,10
SHIELD
LED2
RESET
FAULT
VCC2
VC
16
5
FAULT
6
SHIELD
OUTPUT IC
4
GND1
15
VLED2+
VEE
VE
During power-up, the Under
Voltage Lockout (UVLO) feature
prevents the application of
insufficient gate voltage to the
IGBT, by forcing the
HCPL-316J’s output low. Once
the output is in the high state, the
DESAT (VCE ) detection feature of
the HCPL-316J provides IGBT
protection. Thus, UVLO and
DESAT work in conjunction to
provide constant IGBT
protection.
4
Package Pin Out
1
VIN+
VE
16
2
VIN-
VLED2+
15
3
VCC1
DESAT
14
4
GND1
VCC2
13
5
RESET
VC
12
6
FAULT
VOUT
11
7
VLED1+
VEE
10
8
VLED1-
VEE
9
Pin Descriptions
Symbol
Description
VIN+
Non-inverting gate drive voltage output
(VOUT) control input.
VINInverting gate drive voltage output
(VOUT) control input.
VCC1
Positive input supply voltage. (4.5 V to 5.5 V)
GND1
RESET
Input Ground.
FAULT reset input. A logic low input for at
least 0.1 µs, asynchronously resets FAULT
output high and enables V IN. Synchronous
control of RESET relative to VIN is required.
RESET is not affected by UVLO. Asserting
RESET while VOUT is high does not affect
V OUT.
FAULT
Fault output. FAULT changes from a high
impedance state to a logic low output within
5 µs of the voltage on the DESAT pin
exceeding an internal reference voltage of
7 V. FAULT output remains low until RESET
is brought low. FAULT output is an open
collector which allows the FAULT outputs
from all HCPL-316Js in a circuit
to be connected together in a “wired OR”
forming a single fault bus for interfacing
directly to the micro-controller.
LED 1 anode. This pin must be left unconnected for guaranteed data sheet performance. (For optical coupling testing only)
LED 1 cathode. This pin must be connected
to ground.
VLED1+
VLED1-
Symbol
Description
VE
Common (IGBT emitter) output supply
voltage.
VLED2+ LED 2 anode. This pin must be left unconnected for guaranteed data sheet
performance. (For optical coupling testing
only)
DESAT Desaturation voltage input. When the voltage
on DESAT exceeds an internal reference
voltage of 7 V while the IGBT is on, FAULT
output is changed from a high impedance
state to a logic low state within 5 µs. See
Note 25.
VCC2
Positive output supply voltage.
VC
Collector of output pull-up triple-darlington
transistor. It is connected to VCC2 directly or
through a resistor to limit output turn-on
current.
VOUT
VEE
Gate drive voltage output.
Output supply voltage.
5
Ordering Information
Specify Part Number followed by Option Number (if desired).
Example: HCPL-316J#XXXX
No Option = 16-Lead, Surface Mt. package, 45 per tube.
500 = Tape and Reel Packaging Option, 850 per reel.
XXXE = Lead Free Option.
Remarks: The notation “#” is used for existing products, while (new) products launched since 15th July 2001 and lead free option will use “–”
Option data sheets available. Contact Agilent sales representative, authorized distributor, or visit our WEB site
at http://www.agilent.com/view/optocouplers.
Package Outline Drawings
16-Lead Surface Mount
Dimensions in
inches
(millimeters)
0.018
(0.457)
LAND PATTERN RECOMMENDATION
16 15 14 13 12 11 10 9
TYPE NUMBER
DATE CODE
A 316J
YYWW
Notes:
Initial and continued
variation in the color of the
HCPL-316J’s white mold
compound is normal and
does note affect device
performance or reliability.
Floating Lead Protrusion
is 0.25 mm (10 mils) max.
0.050
(1.270)
0.458 (11.63)
0.295 ± 0.010
(7.493 ± 0.254)
0.085 (2.16)
1
2
3
4
5
6
7
8
0.406 ± 0.10
(10.312 ± 0.254)
0.025 (0.64)
0.345 ± 0.010
(8.986 ± 0.254)
9°
0.018
(0.457)
0.138 ± 0.005
(3.505 ± 0.127)
0–8°
0.025 MIN.
0.408 ± 0.010
(10.160 ± 0.254)
ALL LEADS
TO BE
COPLANAR
± 0.002
0.008 ± 0.003
(0.203 ± 0.076)
STANDOFF
Package Characteristics
All specifications and figures are at the nominal (typical) operating conditions of VCC1 = 5 V, V CC2 - VEE =
30 V, VE - VEE = 0 V, and TA = +25°C.
Parameter
Symbol Min. Typ. Max. Units
Input-Output Momentary
VISO
3750
Vrms
Withstand Voltage
Resistance (Input - Output)
RI-O
>109
Ω
Capacitance (Input - Output)
CI-O
1.3
pF
Output IC-to-Pins 9 &10
θO9-10
30
°C/W
Thermal Resistance
Input IC-to-Pin 4 Thermal Resistance
θI4
60
Test Conditions
Note
RH < 50%, t = 1 min., 1, 2,
TA = 25°C
3
VI-O = 500 Vdc
3
f = 1 MHz
TA = 100°C
6
Solder Reflow Thermal Profile
300
TEMPERATURE (°C)
PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.
REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC.
PEAK
TEMP.
245°C
PEAK
TEMP.
240°C
PEAK
TEMP.
230°C
200
2.5°C ± 0.5°C/SEC.
SOLDERING
TIME
200°C
30
SEC.
160°C
150°C
140°C
30
SEC.
3°C + 1°C/–0.5°C
100
PREHEATING TIME
150°C, 90 + 30 SEC.
50 SEC.
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
0
50
0
100
150
200
TIME (SECONDS)
Recommended Pb-Free IR Profile
tp
Tp
TEMPERATURE
TL
Tsmax
TIME WITHIN 5 °C of ACTUAL
PEAK TEMPERATURE
20-40 SEC.
260 +0/-5 °C
217 °C
RAMP-UP
3 °C/SEC. MAX.
150 - 200 °C
RAMP-DOWN
6 °C/SEC. MAX.
Tsmin
ts
PREHEAT
60 to 180 SEC.
tL
60 to 150 SEC.
25
t 25 °C to PEAK
TIME
NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
Tsmax = 200 °C, Tsmin = 150 °C
250
7
Regulatory Information
The HCPL-316J has been approved by the following
organizations:
IEC/EN/DIN EN 60747-5-2
Approved under:
IEC 60747-5-2:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01.
UL
Recognized under UL 1577, component recognition
program, File E55361.
CSA
Approved under CSA Component Acceptance Notice #5,
File CA 88324.
IEC/EN/DIN EN 60747-5-2 Insulation Characteristics*
Description
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 150 Vrms
for rated mains voltage ≤ 300 Vrms
for rated mains voltage ≤ 600 Vrms
Climatic Classification
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b**
VIORM x 1.875 = VPR, 100% Production Test with t m = 1 sec,
Partial Discharge < 5 pC
Input to Output Test Voltage, Method a**
VIORM x 1.5 = VPR, Type and Sample Test, tm = 60 sec,
Partial Discharge < 5 pC
Highest Allowable Overvoltage**
(Transient Overvoltage tini = 10 sec)
Safety-limiting values - maximum values allowed in the event of
a failure, also see Figure 2.
Case Temperature
Input Power
Output Power
Insulation Resistance at TS, VIO = 500 V
Symbol
Characteristic
Unit
VIORM
I - IV
I - III
I - II
55/100/21
2
891
VPEAK
VPR
1670
VPEAK
VPR
1336
VPEAK
VIOTM
6000
VPEAK
TS
P S, INPUT
PS, OUTPUT
RS
175
400
1200
>109
°C
mW
mW
Ω
* Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in
application. Surface mount classification is class A in accordance with CECCOO802.
** Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations
section IEC/EN/DIN EN 60747-5-2, for a detailed description of Method a and Method b partial discharge test profiles.
1400
PS, OUTPUT
PS, INPUT
PS – POWER – mW
1200
1000
800
600
400
200
0
0
25
50
75 100 125 150 175 200
TS – CASE TEMPERATURE – °C
Figure 2. Dependence of Safety Limiting Values on Temperature.
8
Insulation and Safety Related Specifications
Parameter
Symbol Value Units
Conditions
Minimum External Air Gap L(101)
8.3
mm Measured from input terminals to output
(Clearance)
terminals, shortest distance through air.
Minimum External
L(102)
8.3
mm Measured from input terminals to output
Tracking (Creepage)
terminals, shortest distance path along body.
Minimum Internal Plastic
0.5
mm Through insulation distance conductor to
Gap (Internal Clearance)
conductor, usually the straight line distance
thickness between the emitter and detector.
Tracking Resistance
CTI
>175 Volts DIN IEC 112/VDE 0303 Part 1
(Comparative Tracking
Index)
Isolation Group
IIIa
Material Group (DIN VDE 0110, 1/89, Table 1)
Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Storage Temperature
Ts
-55
125
Operating Temperature
TA
-40
100
Output IC Junction Temperature
TJ
125
Peak Output Current
|Io(peak)|
2.5
Fault Output Current
IFAULT
8.0
Positive Input Supply Voltage
VCC1
-0.5
5.5
Input Pin Voltages
VIN+, VIN- and VRESET
-0.5
VCC1
Total Output Supply Voltage
(VCC2 - VEE)
-0.5
35
Negative Output Supply Voltage
(VE - VEE)
-0.5
15
Positive Output Supply Voltage
(VCC2 - VE)
-0.5
35 - (VE - VEE)
Gate Drive Output Voltage
Vo(peak)
-0.5
VCC2
Collector Voltage
VC
VEE + 5 V
VCC2
DESAT Voltage
VDESAT
VE
VE + 10
Output IC Power Dissipation
PO
600
Input IC Power Dissipation
PI
150
Solder Reflow Temperature Profile
See Package Outline Drawings section
Units
°C
A
mA
Volts
Note
4
5
6
mW
4
Recommended Operating Conditions
Parameter
Operating Temperature
Input Supply Voltage
Total Output Supply Voltage
Negative Output Supply Voltage
Positive Output Supply Voltage
Collector Voltage
Symbol
TA
VCC1
(VCC2 - VEE)
(VE - VEE)
(VCC2 - VE)
VC
Min.
-40
4.5
15
0
15
VEE + 6
Max.
+100
5.5
30
15
30 - (VE - VEE)
VCC2
Units
°C
Volts
Note
28
9
6
9
Electrical Specifications (DC)
Unless otherwise noted, all typical values at TA = 25°C, VCC1 = 5 V, and VCC2 - VEE = 30 V, VE - VEE = 0 V;
all Minimum/Maximum specifications are at Recommended Operating Conditions.
Parameter
Logic Low Input
Voltages
Symbol
VIN+L, VIN-L,
VRESETL
Min.
Logic High Input
Voltages
VIN+H, VIN-H,
VRESETH
2.0
Logic Low Input
Currents
IIN+L, IIN-L,
IRESETL
-0.5
-0.4
FAULT Logic Low
Output Current
IFAULTL
5.0
12
FAULT Logic High
Output Current
IFAULTH
-40
High Level Output
Current
IOH
-0.5
-2.0
-1.5
Low Level Output
Current
IOL
0.5
2.0
2.3
Low Level Output
Current during Fault
Condition
IOLF
90
160
230
mA
High Level Output
Voltage
VOH
VC - 3.5
VC -2.9
VC - 2.5
VC - 2.0
V
Low Level Output
Voltage
VOL
0.17
VC - 1.5
VC - 1.2
VC
0.5
High Level Input
Supply Current
ICC1H
17
22
mA
Low Level Input
Supply Current
ICCIL
6
11
VIN+ = VIN- = 0 V,
VCC1 = 5.5 V
Output Supply
Current
ICC2
2.5
5
VOUT open
Low Level Collector
Current
ICL
0.3
1.0
IOUT = 0
High Level Collector
Current
ICH
0.3
1.3
IEL
-0.7
3.0
0
IOUT = 0
IOUT = -650 µA
VE Low Level Supply
Current
1.8
-0.4
VE High Level Supply
Current
IEH
-0.5
-0.14
0
Blanking Capacitor
Charging Current
ICHG
-0.13
-0.25
-0.33
-0.18
-0.25
-0.33
Blanking Capacitor
Discharge Current
IDSCHG
10
50
UVLO Threshold
VUVLO+
11.6
12.3
13.5
11.1
12.4
VOUT < 5 V
7.5
VCC2 -VE >VUVLO -
VUVLO-
Typ.
UVLO Hysteresis
(VUVLO+ VUVLO-)
0.4
1.2
DESAT Threshold
V DESAT
6.5
7.0
Max.
0.8
Units
V
mA
Test Conditions
Fig. Note
VIN = 0.4 V
VFAULT = 0.4 V
30
µA
VFAULT = VCC1
31
A
VOUT = VCC2 - 4 V
VOUT = VCC2 - 15 V
V
3, 8,
7
5
VOUT = VEE + 2.5 V
VOUT = VEE + 15 V
32
4, 9,
33
7
5
VOUT - VEE = 14 V
5, 34
8
IOUT = -100 mA
IOUT = -650 µA
IOUT = 0
IOUT = 100 mA
6, 8, 9, 10,
35
11
VIN+ = VCC1 = 5.5 V,
VIN- = 0 V
7, 9,
36
26
10,
37,
38
11,12,
39,40
11
15,
59
27
15, 58
15, 57
14,
61
27
14,
40
25
VDESAT = 0 - 6 V
VDESAT = 0 - 6 V,
TA = 25°C - 100°C
VDESAT = 7 V
13,
41
11,
12
VOUT > 5 V
43
42
9, 11,
13
9, 11,
14
16,
44
11
10
Switching Specifications (AC)
Unless otherwise noted, all typical values at TA = 25°C, VCC1 = 5 V, and VCC2 - VEE = 30 V, VE - VEE = 0 V;
all Minimum/Maximum specifications are at Recommended Operating Conditions.
Parameter
VIN to High Level Output
Propagation Delay Time
Symbol
tPLH
Min.
0.10
Typ.
0.30
Max.
0.50
VIN to Low Level Output
Propagation Delay Time
tPHL
0.10
0.32
0.50
PWD
-0.30
0.02
(tPHL - tPLH)
PDD
-0.35
Pulse Width Distortion
Propagation Delay Difference
Between Any Two Parts
10% to 90% Rise Time
Units
µs
Test Conditions
Fig.
Note
Rg = 10 Ω
17,18,19, 15
Cg = 10 nF,
20,21,22,
f = 10 kHz,
Duty Cycle = 50%
45,54,
55
0.30
16,17
0.35
17, 18
tr
0.1
90% to 10% Fall Time
DESAT Sense to 90% VOUT
Delay
tf
tDESAT(90%)
0.1
0.3
0.5
Rg = 10 Ω,
Cg = 10 nF
23,56
DESAT Sense to 10% VOUT
Delay
tDESAT(10%)
2.0
3.0
VCC2 - VEE = 30 V
24,28,
46,56
DESAT Sense to Low Level
FAULT Signal Delay
tDESAT(FAULT)
1.8
5
DESAT Sense to DESAT Low
Propagation Delay
tDESAT(LOW)
0.25
RESET to High Level FAULT
Signal Delay
tRESET(FAULT)
3
RESET Signal Pulse Width
PWRESET
0.1
UVLO to VOUT High Delay
t UVLO ON
7
45
20
VCC2 = 1.0 ms
4.0
19
25, 47,
56
20
56
21
26, 27,
56
22
49
13
ramp
UVLO to VOUT Low Delay
tUVLO OFF
6.0
Output High Level Common
Mode Transient Immunity
|CMH|
15
30
Output Low Level Common
Mode Transient Immunity
|CML |
15
30
14
kV/µs
TA = 25°C ,
VCM = 1500 V,
VCC2 = 30 V
TA = 25°C,
VCM = 1500 V,
VCC2 = 30 V
50,51,
52,53
23
24
11
Notes:
1. In accordance with UL1577, each
optocoupler is proof tested by
applying an insulation test voltage
≥ 4500 Vrms for 1 second (leakage
detection current limit, II-O ≤ 5 µA).
This test is performed before the
100% production test for partial
discharge (method b) shown in IEC/
EN/DIN EN 60747-5-2 Insulation
Characteristic Table, if applicable.
2. The Input-Output Momentary Withstand Voltage is a dielectric voltage
rating that should not be interpreted
as an input-output continuous voltage
rating. For the continuous voltage
rating refer to your equipment level
safety specification or IEC/EN/DIN
EN 60747-5-2 Insulation
Characteristics Table.
3. Device considered a two terminal
device: pins 1 - 8 shorted together
and pins 9 - 16 shorted together.
4. In order to achieve the absolute
maximum power dissipation
specified, pins 4, 9, and 10 require
ground plane connections and may
require airflow. See the Thermal
Model section in the application notes
at the end of this data sheet for
details on how to estimate junction
temperature and power dissipation. In
most cases the absolute maximum
output IC junction temperature is the
limiting factor. The actual power
dissipation achievable will depend on
the application environment (PCB
Layout, air flow, part placement,
etc.). See the Recommended PCB
Layout section in the application
notes for layout considerations.
Output IC power dissipation is
derated linearly at 10 mW/°C above
90°C. Input IC power dissipation does
not require derating.
5. Maximum pulse width = 10 µs,
maximum duty cycle = 0.2%. This
value is intended to allow for component tolerances for designs with IO
peak minimum = 2.0 A. See
Applications section for additional
details on IOH peak. Derate linearly
from 3.0 A at +25°C to 2.5 A at
+100°C. This compensates for
increased I OPEAK due to changes in
VOL over temperature.
6. This supply is optional. Required only
when negative gate drive is
implemented.
7. Maximum pulse width = 50 µs,
maximum duty cycle = 0.5%.
8. See the Slow IGBT Gate Discharge
During Fault Condition section in the
applications notes at the end of this
data sheet for further details.
9. 15 V is the recommended minimum
operating positive supply voltage
(V CC2 - VE ) to ensure adequate
margin in excess of the maximum
V UVLO+ threshold of 13.5 V. For High
Level Output Voltage testing, V OH is
measured with a dc load current.
When driving capacitive loads, V OH
will approach VCC as IOH approaches
zero units.
10. Maximum pulse width = 1.0 ms,
maximum duty cycle = 20%.
11. Once V OUT of the HCPL-316J is
allowed to go high (V CC2 - V E >
V UVLO), the DESAT detection feature
of the HCPL-316J will be the primary
source of IGBT protection. UVLO is
needed to ensure DESAT is
functional. Once VUVLO+ > 11.6 V,
DESAT will remain functional until
V UVLO- < 12.4 V. Thus, the DESAT
detection and UVLO features of the
HCPL-316J work in conjunction to
ensure constant IGBT protection.
12. See the Blanking Time Control
section in the applications notes at
the end of this data sheet for further
details.
13. This is the “increasing” (i.e. turn-on
or “positive going” direction) of
VCC2 - VE.
14. This is the “decreasing” (i.e. turn-off
or “negative going” direction) of
VCC2 - VE.
15. This load condition approximates the
gate load of a 1200 V/75A IGBT.
16. Pulse Width Distortion (PWD) is
defined as |tPHL - tPLH| for any given
unit.
17. As measured from VIN+, VIN- to VOUT .
18. The difference between t PHL and tPLH
between any two HCPL-316J parts
under the same test conditions.
19. Supply Voltage Dependent.
20. This is the amount of time from when
the DESAT threshold is exceeded,
until the FAULT output goes low.
21. This is the amount of time the DESAT
threshold must be exceeded before
VOUT begins to go low, and the
FAULT output to go low.
22. This is the amount of time from when
RESET is asserted low, until FAULT
output goes high. The minimum
specification of 3 µs is the guaranteed
minimum FAULT signal pulse width
when the HCPL-316J is configured
for Auto-Reset. See the Auto-Reset
section in the applications notes at
the end of this data sheet for further
details.
23. Common mode transient immunity in
the high state is the maximum
tolerable dVCM/dt of the common
mode pulse, VCM, to assure that the
output will remain in the high state
(i.e., VO > 15 V or FAULT > 2 V). A
100 pF and a 3K Ω pull-up resistor is
needed in fault detection mode.
24. Common mode transient immunity in
the low state is the maximum
tolerable dVCM/dt of the common
mode pulse, VCM, to assure that the
output will remain in a low state (i.e.,
VO < 1.0 V or FAULT < 0.8 V).
25. Does not include LED2 current
during fault or blanking capacitor
discharge current.
26. To clamp the output voltage at
VCC - 3 VBE , a pull-down resistor
between the output and VEE is
recommended to sink a static current
of 650 µA while the output is high.
See the Output Pull-Down Resistor
section in the application notes at the
end of this data sheet if an output
pull-down resistor is not used.
27. The recommended output pull-down
resistor between VOUT and VEE does
not contribute any output current
when VOUT = VEE.
28. In most applications VCC1 will be
powered up first (before VCC2 ) and
powered down last (after VCC2 ). This
is desirable for maintaining control of
the IGBT gate. In applications where
VCC2 is powered up first, it is
important to ensure that Vin+ remains
low until VCC1 reaches the proper
operating voltage (minimum 4.5 V) to
avoid any momentary instability at
the output during VCC1 ramp-up or
ramp-down.
12
7
IOL – OUTPUT LOW CURRENT
1.8
1.6
1.4
1.2
1.0
-40 -20
0
20
40
60
80
6
5
VOUT = VEE + 15 V
VOUT = VEE + 2.5 V
4
3
2
1
0
-40 -20
100
Figure 3. IOH vs. Temperature.
60
40
80
100
-1
-2
-3
20
40
60
80
0.20
IOUT = 100 mA
0.15
0.10
0.05
0
-40 -20
100
Figure 6. V OH vs. Temperature.
0
20
40
60
80
100
ICC1 – SUPPLY CURRENT – mA
4
3
2
1
0.5
1.0
1.5
2.0
IOL – OUTPUT LOW CURRENT – A
Figure 9: VOL vs. I OL.
50
25
2.5
0
5
10
15
20
25
30
15
ICC1H
ICC1L
10
5
0
-40 -20
0
20
40
60
80
TA – TEMPERATURE – °C
Figure 10. ICC1 vs. Temperature.
+100°C
+25°C
-40°C
28.8
28.6
28.4
28.2
28.0
27.8
27.6
27.4
0
0.2
0.4
0.8
0.6
1.0
Figure 8. VOH vs. IOH .
20
+100°C
+25°C
-40°C
-40°C
25°C
100°C
75
IOH – OUTPUT HIGH CURRENT – A
Figure 7. V OL vs. Temperature.
6
0
0.1
100
TA – TEMPERATURE – °C
TA – TEMPERATURE – °C
5
125
29.0
VOH – OUTPUT HIGH VOLTAGE – V
IOUT = -650 µA
IOUT = -100 mA
0
150
Figure 5. IOLF vs. VOUT.
0.25
0
-4
-40 -20
175
VOUT – OUTPUT VOLTAGE – V
Figure 4. IOL vs. Temperature.
VOL – OUTPUT LOW VOLTAGE – V
(VOH -VCC) – HIGH OUTPUT VOLTAGE DROP – V
20
200
TA – TEMPERATURE – °C
TA – TEMPERATURE – °C
VOL – OUTPUT LOW VOLTAGE – V
0
100
ICC2 – OUTPUT SUPPLY CURRENT – mA
IOH – OUTPUT HIGH CURRENT – A
2.0
IOLF – LOW LEVEL OUTPUT CURRENT
DURING FAULT CONDITION – mA
Performance Plots
2.6
2.5
2.4
ICC2H
ICC2L
2.3
2.2
-40 -20
0
20
40
60
80
TA – TEMPERATURE – °C
Figure 11: ICC2 vs. Temperature.
100
-0.15
2.55
2.50
2.45
ICC2H
ICC2L
2.40
2.35
15
20
25
0.50
IE -VE SUPPLY CURRENT – mA
2.60
ICHG – BLANKING CAPACITOR
CHARGING CURRENT – mA
-0.20
-0.25
-0.30
-40 -20
30
80
2
-40°C
+25°C
+100°C
1
0
0.5
1.0
1.5
2.0
0.35
6.5
6.0
-40 -20
0
20
40
60
80
PROPAGATION DELAY – µs
0.35
0.30
0.25
25
VCC – SUPPLY VOLTAGE – V
Figure 18. Propagation Delay vs.
Supply Voltage.
30
0.40
60
80
100
0.4
0.3
0
20
40
60
80
100
TA – TEMPERATURE – °C
Figure 17. Propagation Delay vs.
Temperature.
0.50
VCC1 = 5.5 V
VCC1 = 5.0 V
VCC1 = 4.5 V
0.35
0.30
0.25
-50
40
tPHL
tPLH
0.2
-40 -20
100
0.45
tPHL
tPLH
20
0.5
Figure 16. DESAT Threshold vs.
Temperature.
0.40
0
Figure 14. IE vs. Temperature.
TA – TEMPERATURE – °C
Figure 15. I C vs. I OUT.
20
0.40
TA – TEMPERATURE – °C
7.0
IOUT (mA)
0.20
15
0.45
0.30
-40 -20
100
TP – PROPAGATION DELAY – µs
VDESAT – DESAT THRESHOLD – V
IC (mA)
60
7.5
3
TP – PROPAGATION DELAY – µs
40
Figure 13. ICHG vs. Temperature.
4
0
20
IEH
IEL
TA – TEMPERATURE – °C
VCC2 – OUTPUT SUPPLY VOLTAGE – V
Figure 12. ICC2 vs. VCC2.
0
PROPAGATION DELAY – µs
ICC2 – OUTPUT SUPPLY CURRENT – mA
13
0
50
TEMPERATURE – °C
Figure 19. V IN to High Propagation
Delay vs. Temperature.
100
0.45
VCC1 = 5.5 V
VCC1 = 5.0 V
VCC1 = 4.5 V
0.40
0.35
0.30
0.25
-50
0
50
TEMPERATURE – °C
Figure 20. V IN to Low Propagation
Delay vs. Temperature.
100
14
0.40
0.45
0.40
tPLH
tPHL
tPLH
tPHL
0.25
DELAY – µs
0.30
0.30
0
20
60
40
80
0.20
100
0
10
20
30
40
0.25
-50
50
LOAD RESISTANCE – Ω
LOAD CAPACITANCE – nF
Figure 21. Propagation Delay vs. Load
Capacitance.
2.4
DELAY – µs
2.5
2.0
100
50
Figure 23. DESAT Sense to 90% Vout
Delay vs. Temperature.
0.008
2.6
VCC2 = 15 V
VCC2 = 30 V
0
TEMPERATURE – °C
Figure 22. Propagation Delay vs. Load
Resistance.
3.0
DELAY – µs
0.35
0.30
0.25
VEE = 0 V
VEE = -5 V
VEE = -10 V
VEE = -15 V
VCC2 = 15 V
VCC2 = 30 V
0.006
DELAY – ms
0.20
0.40
0.35
DELAY – µs
DELAY – µs
0.35
2.2
2.0
1.5
0.004
0.002
1.8
1.0
-50
0
50
1.6
-50
100
TEMPERATURE – °C
0
12
VCC1 = 5.5 V
VCC1 = 5.0 V
VCC1 = 4.5 V
VCC2 = 15 V
VCC2 = 30 V
10
DELAY – µs
0.0025
0.0020
8
6
0.0015
20
30
40
LOAD RESISTANCE – Ω
Figure 27. DESAT Sense to 10% Vout
Delay vs. Load Resistance.
50
4
-50
0
50
100
0
0
10
20
30
40
50
LOAD CAPACITANCE – nF
Figure 25. DESAT Sense to Low Level
Fault Signal Delay vs. Temperature.
0.0030
DELAY – µs
100
TEMPERATURE – °C
Figure 24. DESAT Sense to 10% Vout
Delay vs. Temperature.
0.0010
10
50
150
TEMPERATURE – °C
Figure 28. RESET to High Level Fault
Signal Delay vs. Temperature.
Figure 26. DESAT Sense to 10% Vout
Delay vs. Load Capacitance.
15
Test Circuit Diagrams
VLED2+
VIN+
VE
VIN-
VLED2+
VCC1
DESAT
VCC1
DESAT
GND1
VCC2
GND1
VCC2
RESET
VC
FAULT
VOUT
IFAULT
0.1 µF
5V
VEE
VLED1-
VEE
VLED1-
VEE
Figure 31. IFAULTH Test Circuit.
VE
VIN-
VLED2+
VCC1
DESAT
GND1
VCC2
VC
VOUT
VLED1+
VEE
VLED1-
VEE
0.1 µF
30 V
0.1 µF
15 V
PULSED
+
–
+
–
30 V
IOUT
VIN+
VIN+
VE
VIN-
VLED2+
VCC1
DESAT
GND1
VCC2
0.1 µF
0.1 µF
Figure 32. IOH Pulsed Test Circuit.
RESET
VC
FAULT
VOUT
VLED1+
VEE
VLED1-
VEE
VE
0.1 µF
VIN-
VLED2+
VCC1
DESAT
GND1
VCC2
RESET
VC
FAULT
VOUT
VLED1+
VEE
VLED1-
VEE
5V
30 V
0.1 µF
+
–
IOUT
30 V
+
–
14 V
Figure 34. IOLF Test Circuit.
30 V
0.1 µF
0.1 µF
+
–
IOUT
30 V
15 V
PULSED
+
–
Figure 33. I OL Pulsed Test Circuit.
+
–
+
–
VOUT
VLED1+
FAULT
5V
FAULT
VEE
RESET
0.1
µF
VC
IFAULT
+
–
+
–
RESET
VLED1+
VIN+
5V
+
–
5V
Figure 30. IFAULTL Test Circuit.
0.1
µF
0.1
µF
10 mA
0.1
µF
+
–
0.1
µF
VIN+
VE
VIN-
VLED2+
VCC1
DESAT
GND1
VCC2
RESET
VC
FAULT
VOUT
VLED1+
VEE
VLED1-
VEE
Figure 35. V OH Pulsed Test Circuit.
0.1 µF
+
–
–
+
VE
VIN-
+
–
0.4 V
+
–
VIN+
+
–
4.5 V
0.1
µF
30 V
0.1 µF
+
–
VOUT
30 V
2A
PULSED
0.1
µF
16
VIN-
VLED2+
VCC1
DESAT
GND1
VCC2
RESET
VOUT
VLED1+
VEE
VLED1-
VEE
5.5 V
30 V
30 V
VOUT
0.1
µF
VIN+
VE
VIN-
VLED2+
VCC1
DESAT
0.1
µF
5V
+
–
ICC1
+
–
VCC2
VIN-
VLED2+
VCC1
DESAT
GND1
VCC2
RESET
VC
FAULT
VOUT
VLED1+
VEE
VLED1-
VEE
VIN+
VE
VIN-
VLED2+
VCC1
DESAT
0.1
µF
30 V
VCC2
GND1
RESET
VC
RESET
VC
FAULT
VOUT
FAULT
VOUT
VLED1+
VEE
VLED1+
VEE
VLED1-
VEE
VLED1-
VEE
Figure 38. ICC1L Test Circuit.
VIN-
VE
ICC2
GND1
VIN+
VIN+
Figure 37. I CC1H Test Circuit.
VE
VLED2+
VCC1
DESAT
GND1
VCC2
0.1 µF
0.1
µF
5V
30 V
ICC2
RESET
VC
FAULT
VOUT
VLED1+
VLED1-
0.1 µF
+
–
VIN+
VE
VIN-
VLED2+
VCC1
DESAT
GND1
VCC2
VC
FAULT
VOUT
VEE
VLED1+
VEE
VEE
VLED1-
VEE
+
–
Figure 40. ICC2L Test Circuit.
+
–
0.1 µF
ICHG
RESET
0.1 µF
0.1 µF
30 V
Figure 39. I CC2H Test Circuit.
+
–
5.5 V
ICC1
+
–
Figure 36. VOL Test Circuit.
0.1
µF
+
–
0.1 µF
100
mA
VC
FAULT
0.1
µF
30 V
Figure 41. ICHG Pulsed Test Circuit.
0.1
µF
+
–
+
–
0.1 µF
+
–
5V
VE
+
–
VIN+
0.1
µF
30 V
0.1 µF
+
–
0.1 µF
30 V
17
VE
VCC1
DESAT
GND1
VCC2
RESET
IDSCHG
0.1
µF
+
–
5V
30 V
0.1 µF
+
–
GND1
VCC2
VEE
VLED1-
VEE
VLED2+
VCC1
DESAT
GND1
VCC2
RESET
VC
FAULT
VOUT
SWEEP
0.1
µF
0.1
µF
15 V
+
–
VIN-
VIN
+
–
VE
0.1 µF
5V
+
–
15 V
0.1 µF
3k
VIN+
VE
VIN-
VLED2+
VCC1
DESAT
GND1
VCC2
RESET
VC
FAULT
VOUT
VLED1+
VEE
VLED1+
VEE
VLED1-
VEE
VLED1-
VEE
Figure 44. DESAT Threshold Test Circuit.
0.1 µF
VE
VIN-
VLED2+
VCC1
DESAT
GND1
VCC2
RESET
VC
FAULT
VOUT
VLED1+
VEE
VLED1-
VEE
Figure 46. tDESAT(10%) Test Circuit.
0.1 µF
30 V
0.1 µF
0.1
µF
VOUT
+
–
30 V
10 Ω
10
nF
Figure 45. tPLH, t PHL, t r, tf Test Circuit.
VIN
0.1
µF
0.1
µF
+
–
VIN+
VOUT
Figure 43. UVLO Threshold Test Circuit.
+
–
VIN+
SWEEP
+
–
VC
VEE
30 V
0.1 µF
Figure 42. IDSCHG Test Circuit.
3k
DESAT
VLED1+
VLED1-
5V
VCC1
VEE
VLED1+
+
–
VLED2+
VOUT
VOUT
0.1
µF
VIN-
FAULT
FAULT
0.1
µF
VE
RESET
VC
10 mA
VIN+
+
–
30 V
VOUT
10 Ω
10
nF
0.1
µF
5V
0.1
µF
+
–
3k
VFAULT
30 V
VIN+
VE
VIN-
VLED2+
VCC1
DESAT
GND1
VCC2
RESET
VC
FAULT
VOUT
VLED1+
VEE
VLED1-
VEE
Figure 47. tDESAT(FAULT) Test Circuit.
VIN
0.1
µF
+
–
VLED2+
0.1
µF
+
–
VIN-
+
–
7V
+
–
VIN+
30 V
0.1
µF
0.1
µF
10 Ω
10
nF
+
–
30 V
18
+
–
5V
VIN+
VE
VIN-
VLED2+
VCC1
3k
VC
FAULT
VOUT
VLED1+
VEE
VLED1-
VEE
+
–
5V
0.1
µF
VCC2
RESET
VFAULT
0.1
µF
30 V
DESAT
GND1
VIN HIGH
TO LOW
0.1
STROBE µF
8V
+
–
0.1
µF
0.1
µF
+
–
30 V
10 Ω
3k
10
nF
Figure 48. tRESET(FAULT) Test Circuit.
0.1
µF
1
VIN+
VE
16
2
VIN-
VLED2+
15
3
VCC1
DESAT
14
4
GND1
VCC2
13
5
RESET
VC
12
0.1
µF
25 V
0.1 µF
SCOPE
100 pF
7
100 pF
8
VOUT
FAULT
VEE
VLED1+
VLED1
VLED2+
VCC1
DESAT
GND1
VCC2
RESET
VC
FAULT
VOUT
VLED1+
VEE
VLED1-
VEE
VEE
11
10 Ω
10
VIN+
VE
16
2
VIN-
VLED2+
15
3
VCC1
DESAT
14
4
GND1
VCC2
13
5
RESET
VC
12
6
FAULT
VOUT
11
7
VLED1+
VEE
10
8
VLED1
VEE
9
VIN+
VE
16
2
VIN-
VLED2+
15
3
VCC1
DESAT
14
9
9V
0.1 µF
10 Ω
10 nF
Figure 51. CMR Test Circuit, LED2 on.
5V
25 V
0.1
µF
0.1 µF
GND1
25 V
VCm
1
4
10
nF
750 Ω
10 nF
Figure 50. CMR Test Circuit, LED2 off.
0.1
µF
10 Ω
1
VCm
5V
RAMP
0.1
µF
VOUT
+
–
6
VIN-
3 kΩ
3 kΩ
SCOPE
VE
Figure 49. UVLO Delay Test Circuit.
5V
5V
VIN+
VCC2
13
3 kΩ
1
VIN+
VE
16
2
VIN-
VLED2+
15
3
VCC1
DESAT
14
4
GND1
VCC2
13
5
RESET
VC
12
6
FAULT
VOUT
11
7
VLED1+
VEE
10
8
VLED1
VEE
9
0.1 µF
3 kΩ
5
RESET
VC
12
6
FAULT
VOUT
11
25 V
SCOPE
100
pF
7
VLED1+
VEE
10
8
VLED1
VEE
9
VCm
Figure 52. CMR Test Circuit, LED1 off.
10 Ω
10 nF
100 pF
VCm
Figure 53. CMR Test Circuit, LED1 on.
SCOPE
10 Ω
10 nF
19
VINVIN-
2.5 V
0V
VIN+
VIN+
2.5 V
2.5 V
5.0 V
2.5 V
tr
tf
tr
tf
90%
90%
50%
50%
10%
VOUT
tPLH
10%
VOUT
tPHL
tPLH
Figure 54. VOUT Propagation Delay Waveforms,
Noninverting Configuration.
tPHL
Figure 55. V OUT Propagation Delay Waveforms, Inverting
Configuration.
tDESAT (FAULT)
tDESAT (10%)
tDESAT (LOW)
7V
VDESAT
50%
tDESAT (90%)
VOUT
90%
10%
FAULT
50% (2.5 V)
tRESET (FAULT)
RESET
Figure 56. Desat, VOUT , Fault, Reset Delay Waveforms.
50%
20
VIN-
VLED2+
VCC1
DESAT
GND1
VCC2
RESET
VC
FAULT
VOUT
VLED1+
VLED1-
5V
0.1 µF
IC
VIN-
VLED2+
VCC1
DESAT
GND1
VCC2
FAULT
VOUT
VLED1+
VLED1-
+
–
DESAT
GND1
VCC2
VEE
VLED1+
VEE
VEE
VLED1-
VEE
650 µA
5V
+
–
30 V
0.1 µF
IC
0.1
µF
VIN+
VE
VIN-
VLED2+
VCC1
DESAT
GND1
VCC2
RESET
VC
FAULT
VOUT
VEE
VLED1+
VEE
VEE
VLED1-
VEE
0.1 µF
+
–
30 V
Figure 60. IEH Test Circuit.
VIN+
VE
VIN-
VLED2+
VCC1
DESAT
GND1
VCC2
RESET
VC
FAULT
VOUT
VLED1+
VEE
VLED1-
VEE
Figure 61. I EL Test Circuit.
30 V
0.1 µF
IC
+
–
0.1 µF
30 V
Figure 58. ICH Test Circuit.
IE
0.1
µF
+
–
5V
VCC1
VOUT
Figure 59. I CL Test Circuit.
0.1
µF
VLED2+
FAULT
30 V
+
–
VC
VIN-
VC
0.1 µF
RESET
VE
RESET
+
–
Figure 57. ICH Test Circuit.
VE
VIN+
0.1 µF
30 V
0.1 µF
VIN+
+
–
0.1
µF
30 V
0.1 µF
0.1 µF
+
–
30 V
IE
0.1
µF
+
–
+
–
0.1 µF
+
–
5V
VE
+
–
VIN+
0.1
µF
30 V
0.1 µF
0.1 µF
+
–
30 V
21
Applications Information
Typical Application/
Operation
Introduction to Fault
Detection and Protection
The power stage of a typical three
phase inverter is susceptible to
several types of failures, most of
which are potentially destructive
to the power IGBTs. These failure
modes can be grouped into four
basic categories: phase and/or
rail supply short circuits due to
user misconnect or bad wiring,
control signal failures due to
noise or computational errors,
overload conditions induced by
the load, and component failures
in the gate drive circuitry. Under
any of these fault conditions, the
current through the IGBTs can
increase rapidly, causing
excessive power dissipation and
heating. The IGBTs become
damaged when the current load
approaches the saturation current
of the device, and the collector to
emitter voltage rises above the
saturation voltage level. The
drastically increased power
dissipation very quickly overheats
the power device and destroys it.
To prevent damage to the drive,
fault protection must be
implemented to reduce or
turn-off the overcurrents during a
fault condition.
A circuit providing fast local fault
detection and shutdown is an
ideal solution, but the number of
required components, board
space consumed, cost, and
complexity have until now limited
its use to high performance
drives. The features which this
circuit must have are high speed,
low cost, low resolution, low
power dissipation, and small size.
The HCPL-316J satisfies these
criteria by combining a high
speed, high output current driver,
high voltage optical isolation
between the input and output,
local IGBT desaturation detection
and shut down, and an optically
isolated fault status feedback
signal into a single 16-pin surface
mount package.
The fault detection method,
which is adopted in the
HCPL-316J, is to monitor the
saturation (collector) voltage of
the IGBT and to trigger a local
fault shutdown sequence if the
collector voltage exceeds a
predetermined threshold. A small
gate discharge device slowly
reduces the high short circuit
IGBT current to prevent
damaging voltage spikes. Before
the dissipated energy can reach
destructive levels, the IGBT is
shut off. During the off state of
the IGBT, the fault detect
circuitry is simply disabled to
prevent false ‘fault’ signals.
The alternative protection
scheme of measuring IGBT
current to prevent desaturation is
effective if the short circuit
capability of the power device is
known, but this method will fail if
the gate drive voltage decreases
enough to only partially turn on
the IGBT. By directly measuring
the collector voltage, the
HCPL-316J limits the power
dissipation in the IGBT even with
insufficient gate drive voltage.
Another more subtle advantage of
the desaturation detection
method is that power dissipation
in the IGBT is monitored, while
the current sense method relies
on a preset current threshold to
predict the safe limit of
operation. Therefore, an overlyconservative overcurrent
threshold is not needed to protect
the IGBT.
Recommended Application
Circuit
The HCPL-316J has both
inverting and non-inverting gate
control inputs, an active low reset
input, and an open collector fault
output suitable for wired ‘OR’
applications. The recommended
application circuit shown in
Figure 62 illustrates a typical
gate drive implementation using
the HCPL-316J.
The four supply bypass
capacitors (0.1 µF) provide the
large transient currents necessary
during a switching transition.
Because of the transient nature of
the charging currents, a low
current (5 mA) power supply
suffices. The desat diode and 100
pF capacitor are the necessary
external components for the fault
detection circuitry. The gate
resistor (10 Ω) serves to limit
gate charge current and indirectly
control the IGBT collector
voltage rise and fall times. The
open collector fault output has a
passive 3.3 kΩ pull-up resistor
and a 330 pF filtering capacitor.
A 47 kΩ pulldown resistor on
VOUT provides a more predictable
high level output voltage (VOH).
In this application, the IGBT gate
driver will shut down when a fault
is detected and will not resume
switching until the
microcontroller applies a reset
signal.
22
HCPL-316J
µC
5V +
–
3.3
kΩ
1
VIN+
VE
16
2
VIN-
VLED2+
15
3
VCC1
DESAT
14
0.1
µF
0.1
µF
0.1
µF
100 pF
100 Ω
DDESAT
+
–
VF
330 pF
4
GND1
5
6
VCC2
13
RESET
VC
12
FAULT
VOUT
11
7
VLED1+
VEE
10
8
VLED1-
VEE
9
+
–
VCC2 = 18 V
Q1
VCE
Rg
47
kΩ
+
–
0.1
µF
3-PHASE
OUTPUT
–
+
Q2
VEE = -5 V
+
VCE
–
Figure 62. Recommended Application Circuit.
Description of Operation/
Timing
Figure 63 below illustrates input
and output waveforms under the
conditions of normal operation, a
desat fault condition, and normal
reset behavior.
Normal Operation
During normal operation, VOUT of
the HCPL-316J is controlled by
either VIN+ or VIN-, with the IGBT
collector-to-emitter voltage being
monitored through DDESAT. The
NORMAL
OPERATION
VINNON-INVERTING
CONFIGURED
INPUTS
INVERTING
CONFIGURED
INPUTS
FAULT output is high and the
RESET input should be held high.
See Figure 63.
the purpose of notifying the
micro-controller of the fault
condition. See Figure 63.
Fault Condition
When the voltage on the DESAT
pin exceeds 7 V while the IGBT is
on, VOUT is slowly brought low in
order to “softly” turn-off the IGBT
and prevent large di/dt induced
voltages. Also activated is an
internal feedback channel which
brings the FAULT output low for
Reset
The FAULT output remains low
until RESET is brought low. See
Figure 63. While asserting the
RESET pin (LOW), the input pins
must be asserted for an output
low state (VIN+ is LOW or VIN- is
HIGH). This may be
accomplished either by software
control (i.e. of the
microcontroller) or hardware
control (see Figures 73 and 74).
FAULT
CONDITION
0V
5V
VIN+
VIN-
5V
VIN+
5V
7V
VDESAT
VOUT
FAULT
RESET
Figure 63. Timing Diagram.
RESET
23
Slow IGBT Gate
Discharge During Fault
Condition
When a desaturation fault is
detected, a weak pull-down
device in the HCPL-316J output
drive stage will turn on to ‘softly’
turn off the IGBT. This device
slowly discharges the IGBT gate
to prevent fast changes in drain
current that could cause
damaging voltage spikes due to
lead and wire inductance. During
the slow turn off, the large output
pull-down device remains off until
the output voltage falls below VEE
+ 2 Volts, at which time the large
pull down device clamps the
IGBT gate to VEE.
DESAT Fault Detection
Blanking Time
The DESAT fault detection
circuitry must remain disabled for
a short time period following the
turn-on of the IGBT to allow the
collector voltage to fall below the
DESAT theshold. This time
period, called the DESAT
blanking time, is controlled by
the internal DESAT charge
current, the DESAT voltage
threshold, and the external
DESAT capacitor. The nominal
blanking time is calculated in
terms of external capacitance
(C BLANK), FAULT threshold
voltage (VDESAT), and DESAT
charge current (ICHG) as
tBLANK = CBLANK x V DESAT / ICHG.
The nominal blanking time with
the recommended 100 pF
capacitor is 100 pF * 7 V / 250 µA
= 2.8 µsec. The capacitance
value can be scaled slightly to
adjust the blanking time, though
a value smaller than 100 pF is not
recommended. This nominal
blanking time also represents the
longest time it will take for the
HCPL-316J to respond to a
DESAT fault condition. If the
IGBT is turned on while the
collector and emitter are shorted
to the supply rails (switching into
a short), the soft shut-down
sequence will begin after
approximately 3 µsec. If the IGBT
collector and emitter are shorted
to the supply rails after the IGBT
is already on, the response time
will be much quicker due to the
parasitic parallel capacitance of
the DESAT diode. The
recommended 100 pF capacitor
should provide adequate blanking
as well as fault response times for
most applications.
Under Voltage Lockout
The HCPL-316J Under Voltage
Lockout (UVLO) feature is
designed to prevent the
application of insufficient gate
voltage to the IGBT by forcing
the HCPL-316J output low during
power-up. IGBTs typically require
gate voltages of 15 V to achieve
their rated V CE(ON) voltage. At
gate voltages below 13 V
typically, their on-voltage
increases dramatically, especially
at higher currents. At very low
gate voltages (below 10 V), the
IGBT may operate in the linear
region and quickly overheat. The
UVLO function causes the output
to be clamped whenever
insufficient operating supply
(VCC2 ) is applied. Once VCC2
exceeds VUVLO+ (the positivegoing UVLO threshold), the
UVLO clamp is released to allow
the device output to turn on in
response to input signals. As
VCC2 is increased from 0 V (at
some level below VUVLO+), first
the DESAT protection circuitry
becomes active. As VCC2 is
further increased (above
VUVLO+), the UVLO clamp is
released. Before the time the
UVLO clamp is released, the
DESAT protection is already
active. Therefore, the UVLO and
DESAT FAULT DETECTION
features work together to provide
seamless protection regardless of
supply voltage (VCC2).
24
Behavioral Circuit
Schematic
The functional behavior of the
HCPL-316J is represented by the
logic diagram in Figure 64 which
fully describes the interaction and
sequence of internal and external
signals in the HCPL-316J.
Input IC
In the normal switching mode, no
output fault has been detected,
and the low state of the fault
latch allows the input signals to
control the signal LED. The fault
output is in the open-collector
state, and the state of the Reset
pin does not affect the control of
the IGBT gate. When a fault is
detected, the FAULT output and
are never on at the same time. If
an undervoltage condition is
detected, the output will be
actively pulled low by the 50x
DMOS device, regardless of the
LED state. If an IGBT
desaturation fault is detected
while the signal LED is on, the
Fault signal will latch in the high
state. The triple darlington AND
the 50x DMOS device are
disabled, and a smaller 1x DMOS
pull-down device is activated to
slowly discharge the IGBT gate.
When the output drops below two
volts, the 50x DMOS device again
turns on, clamping the IGBT gate
firmly to Vee. The Fault signal
remains latched in the high state
until the signal LED turns off.
signal input are both latched. The
fault output changes to an active
low state, and the signal LED is
forced off (output LOW). The
latched condition will persist until
the Reset pin is pulled low.
Output IC
Three internal signals control the
state of the driver output: the
state of the signal LED, as well as
the UVLO and Fault signals. If no
fault on the IGBT collector is
detected, and the supply voltage
is above the UVLO threshold, the
LED signal will control the driver
output state. The driver stage
logic includes an interlock to
ensure that the pull-up and pulldown devices in the output stage
250 µA
DESAT (14)
+
VIN+ (1)
VIN– (2)
–
LED
VCC1 (3)
GND (4)
VE (16)
UVLO
DELAY
7V
VCC2 (13)
–
+
12 V
FAULT
VC (12)
FAULT (6)
Q
VOUT (11)
R S
RESET (5)
50 x
FAULT
VEE (9,10)
1x
Figure 64. Behavioral Circuit Schematic.
25
HCPL-316J
HCPL-316J
1
VIN+
2
VIN-
3
VCC1
4
GND1
5
RESET
6
FAULT
7
VLED1+
8
VLED1-
HCPL-316J
VE
16
VE
16
VLED2+
15
VLED2+
15
100 pF
µC
DESAT
14
DESAT
14
VCC2
13
VCC2
13
VC
12
VC
12
VOUT
11
VOUT
11
VEE
10
VEE
10
VEE
9
VEE
9
Rg
RPULL-DOWN
100 Ω
DDESAT
Rg
3.3
kΩ
330 pF
+
–
Figure 65. Output Pull-Down Resistor.
Figure 66. DESAT Pin Protection.
Figure 67. FAULT Pin CMR Protection.
Other Recommended
Components
DESAT Pin Protection
The freewheeling of flyback
diodes connected across the
IGBTs can have large
instantaneous forward voltage
transients which greatly exceed
the nominal forward voltage of
the diode. This may result in a
large negative voltage spike on
the DESAT pin which will draw
substantial current out of the IC if
protection is not used. To limit
this current to levels that will not
damage the IC, a 100 ohm
resistor should be inserted in
series with the DESAT diode. The
added resistance will not alter the
DESAT threshold or the DESAT
blanking time.
value of 15 kV/µs. The added
capacitance does not increase the
fault output delay when a
desaturation condition is
detected.
The application circuit in Figure
62 includes an output pull-down
resistor, a DESAT pin protection
resistor, a FAULT pin capacitor
(330 pF), and a FAULT pin pullup resistor.
Output Pull-Down Resistor
During the output high transition,
the output voltage rapidly rises to
within 3 diode drops of VCC2 . If
the output current then drops to
zero due to a capacitive load, the
output voltage will slowly rise
from roughly VCC2-3(VBE) to VCC2
within a period of several
microseconds. To limit the output
voltage to VCC2 -3(VBE ), a pulldown resistor between the output
and VEE is recommended to sink
a static current of several 650 µA
while the output is high. Pulldown resistor values are
dependent on the amount of
positive supply and can be
adjusted according to the
formula, Rpull-down =
[VCC2 -3 * (VBE )] / 650 µA.
Capacitor on FAULT Pin for
High CMR
Rapid common mode transients
can affect the fault pin voltage
while the fault output is in the
high state. A 330 pF capacitor
(Fig. 66) should be connected
between the fault pin and ground
to achieve adequate CMOS noise
margins at the specified CMR
Pull-up Resistor on FAULT Pin
The FAULT pin is an opencollector output and therefore
requires a pull-up resistor to
provide a high-level signal.
Driving with Standard CMOS/
TTL for High CMR
Capacitive coupling from the
isolated high voltage circuitry to
the input referred circuitry is the
primary CMR limitation. This
coupling must be accounted for
to achieve high CMR performance. The input pins VIN+ and
VIN- must have active drive
signals to prevent unwanted
switching of the output under
extreme common mode transient
conditions. Input drive circuits
that use pull-up or pull-down
resistors, such as open collector
configurations, should be
avoided. Standard CMOS or TTL
drive circuits are recommended.
26
User-Configuration of the
HCPL-316J Input Side
The VIN+, VIN-, FAULT and
RESET input pins make a wide
variety of gate control and fault
configurations possible,
depending on the motor drive
requirements. The HCPL-316J
has both inverting and noninverting gate control inputs, an
open collector fault output
suitable for wired ‘OR’
applications and an active low
reset input.
configuration is desired, VIN– is
held low by connecting it to
GND1 and VIN+ is toggled. As
shown in Figure 69, when an
inverting configuration is desired,
VIN+ is held high by connecting it
to VCC1 and VIN– is toggled.
Driving Input pf HCPL-316J in
Non-Inverting/Inverting Mode
The Gate Drive Voltage Output of
the HCPL-316J can be
configured as inverting or
non-inverting using the VIN– and
VIN+ inputs. As shown in Figure
68, when a non-inverting
HCPL-316J
µC
HCPL-316J
1
VIN+
1
VIN+
2
VIN-
2
VIN-
3
VCC1
3
VCC1
+
–
µC
+
–
4
GND1
4
GND1
5
RESET
5
RESET
6
FAULT
6
FAULT
7
VLED1+
7
VLED1+
8
VLED1-
8
VLED1-
Figure 68. Typical Input Configuration, Non-Inverting.
Figure 69. Typical Input Configuration, Inverting.
27
Local Shutdown, Local Reset
As shown in Figure 70, the fault
output of each HCPL-316J gate
driver is polled separately, and
the individual reset lines are
asserted low independently to
reset the motor controller after a
fault condition.
Global-Shutdown, Global
Reset
As shown in Figure 71, when
configured for inverting
operation, the HCPL-316J can be
configured to shutdown
automatically in the event of a
fault condition by tying the
FAULT output to VIN+. For high
reliability drives, the open
collector FAULT outputs of each
HCPL-316J can be wire ‘OR’ed
together on a common fault bus,
forming a single fault bus for
interfacing directly to the microcontroller. When any of the six
gate drivers detects a fault, the
fault output signal will disable all
six HCPL-316J gate drivers
simultaneously and thereby
provide protection against further
catastrophic failures.
Auto-Reset
As shown in Figure 72, when the
inverting V IN- input is connected
to ground (non-inverting
configuration), the HCPL-316J
can be configured to reset
automatically by connecting
RESET to V IN+. In this case, the
gate control signal is applied to
the non-inverting input as well as
the reset input to reset the fault
latch every switching cycle.
During normal operation of the
IGBT, asserting the reset input
low has no effect. Following a
fault condition, the gate driver
remains in the latched fault state
until the gate control signal
changes to the ‘gate low’ state
and resets the fault latch. If the
HCPL-316J
1
VIN+
2
VIN-
3
VCC1
4
GND1
5
RESET
6
FAULT
7
VLED1+
8
VLED1-
+
–
µC
Figure 70. Local Shutdown, Local
Reset Configuration.
gate control signal is a
continuous PWM signal, the fault
latch will always be reset by the
next time the input signal goes
high. This configuration protects
the IGBT on a cycle-by-cycle
basis and automatically resets
before the next ‘on’ cycle. The
fault outputs can be wire ‘OR’ed
together to alert the
microcontroller, but this signal
would not be used for control
purposes in this (Auto-Reset)
configuration. When the
HCPL- 316J is configured for
Auto-Reset, the guaranteed
minimum FAULT signal pulse
width is 3 µs.
HCPL-316J
1
VIN+
2
VIN-
3
VCC1
4
GND1
5
RESET
6
FAULT
7
VLED1+
8
VLED1-
+
–
µC
CONNECT
TO OTHER
RESETS
CONNECT
TO OTHER
FAULTS
Figure 71. Global-Shutdown, Global
Reset Configuration.
HCPL-316J
µC
1
VIN+
2
VIN-
3
VCC1
4
GND1
5
RESET
6
FAULT
7
VLED1+
8
VLED1-
+
–
Figure 72. Auto-Reset Configuration.
Resetting Following a Fault
Condition
To resume normal switching
operation following a fault
condition (FAULT output low),
the RESET pin must first be
asserted low in order to release
the internal fault latch and reset
the FAULT output (high). Prior to
asserting the RESET pin low, the
input (VIN) switching signals must
be configured for an output (VOL)
low state. This can be handled
directly by the microcontroller or
by hardwiring to synchronize the
RESET signal with the
appropriate input signal. Figure
73a shows how to connect the
RESET to the VIN+ signal for safe
automatic reset in the noninverting input configuration.
Figure 73b shows how to
configure the VIN+/RESET signals
so that a RESET signal from the
microcontroller causes the input
to be in the “output-off” state.
Similarly, Figures 73c and 73d
show automatic RESET and
microcontroller RESET safe
configurations for the inverting
input configuration.
28
HCPL-316J
1
VIN+
2
VIN-
HCPL-316J
VIN+
VCC
1
VIN+
2
VIN-
3
VCC1
4
GND1
5
RESET
6
FAULT
VCC
3
VCC1
µC
µC
VIN+/
RESET
FAULT
4
GND1
5
RESET
RESET
FAULT
6
FAULT
7
VLED1+
7
VLED1+
8
VLED1-
8
VLED1-
Figure 73a. Safe Hardware Reset for Non-Inverting
Input Configuration (Automatically Resets for Every
VIN+ Input).
Figure 73b. Safe Hardware Reset for Non-Inverting Input
Configuration.
HCPL-316J
VCC
1
VIN+
2
VIN-
HCPL-316J
VCC
VIN-
VIN-
VCC
1
VIN+
2
VIN-
3
VCC1
4
GND1
5
RESET
6
FAULT
VCC
3
VCC1
µC
µC
4
GND1
RESET
RESET
FAULT
5
RESET
6
FAULT
7
VLED1+
7
VLED1+
8
VLED1-
8
VLED1-
FAULT
Figure 73c. Safe Hardware Reset for Inverting Input
Configuration.
User-Configuration of the
HCPL-316J Output Side
RG and Optional Resistor RC:
The value of the gate resistor RG
(along with VCC2 and VEE )
determines the maximum amount
of gate-charging/discharging
current (ION,PEAK and IOFF,PEAK)
and thus should be carefully
chosen to match the size of the
IGBT being driven. Often it is
desirable to have the peak gate
charge current be somewhat less
Figure 73d. Safe Hardware Reset for Inverting Input
Configuration (Automatically Resets for Every VINInput).
than the peak discharge current
(ION,PEAK < IOFF,PEAK). For this
condition, an optional resistor
(RC) can be used along with RG
to independently determine
ION,PEAK and IOFF,PEAK without
using a steering diode. As an
example, refer to Figure 74.
Assuming that RG is already
determined and that the design
IOH,PEAK = 0.5 A, the value of RC
can be estimated in the following
way:
RC + R G = [VCC2 – VOH – (VEE)]
IOH,PEAK
= [4 V – (-5 V)]
0.5 A
= 18 Ω
➯ RC = 8 Ω
See “Power and Layout
Considerations” section for more
information on calculating value
of RG.
29
Higher Output Current Using
an External Current Buffer:
To increase the IGBT gate drive
current, a non-inverting current
buffer (such as the npn/pnp
buffer shown in Figure 75) may
be used. Inverting types are not
compatible with the desaturation
fault protection circuitry and
should be avoided. To preserve
the slow IGBT turn-off feature
during a fault condition, a 10 nF
capacitor should be connected
from the buffer input to VEE and
a 10 Ω resistor inserted between
the output and the common npn/
pnp base. The MJD44H11 /
MJD45H11 pair is appropriate
for currents up to 8A maximum.
The D44VH10 / D45VH10 pair is
appropriate for currents up to 15
A maximum.
HCPL-316J
VE
16
VLED2+
15
DESAT
14
VCC2
13
VC
12
VOUT
11
VEE
10
VEE
9
100 pF
RC 8 Ω
10 Ω
10 nF
15 V
-5 V
Figure 74. Use of RC to Further Limit
I ON,PEAK.
DESAT Diode and DESAT
Threshold
The DESAT diode’s function is to
conduct forward current,
HCPL-316J
VE
16
VLED2+
15
DESAT
14
VCC2
13
VC
12
VOUT
11
VEE
10
100 pF
MJD44H11 or
D44VH10
4.5 Ω
10 Ω
VEE
2.5 Ω
10 nF
MJD45H11 or
D45VH10
9
15 V
-5 V
Figure 75. Current Buffer for Increased Drive Current.
Part Number
MUR1100E
MURS160T3
UF4007
BYM26E
BYV26E
BYV99
Manufacturer
Motorola
Motorola
General Semi.
Philips
Philips
Philips
Power/Layout
Considerations
Operating Within the
Maximum Allowable Power
Ratings (Adjusting Value of
RG ):
trr (ns)
75
75
75
75
75
75
Max. Reverse Voltage
Rating, VRRM (Volts)
1000
600
1000
1000
1000
600
When choosing the value of R G,
it is important to confirm that the
power dissipation of the
HCPL-316J is within the
maximum allowable power
rating.
allowing sensing of the IGBT’s
saturated collector-to-emitter
voltage, VCESAT, (when the IGBT
is “on”) and to block high
voltages (when the IGBT is “off”).
During the short period of time
when the IGBT is switching, there
is commonly a very high dVCE/dt
voltage ramp rate across the
IGBT’s collector-to-emitter. This
results in ICHARGE (= CD-DESAT x
dVCE /dt) charging current which
will charge the blanking
capacitor, CBLANK. In order to
minimize this charging current
and avoid false DESAT triggering,
it is best to use fast response
diodes. Listed in the below table
are fast-recovery diodes that are
suitable for use as a DESAT diode
(DDESAT). In the recommended
application circuit shown in
Figure 62, the voltage on pin 14
(DESAT) is VDESAT = VF + VCE,
(where VF is the forward ON
voltage of DDESAT and VCE is the
IGBT collector-to-emitter
voltage). The value of VCE which
triggers DESAT to signal a
FAULT condition, is nominally 7V
– VF. If desired, this DESAT
threshold voltage can be
decreased by using multiple
DESAT diodes in series. If n is
the number of DESAT diodes
then the nominal threshold value
becomes VCE,FAULT(TH) = 7 V – n
x VF. In the case of using two
diodes instead of one, diodes with
half of the total required
maximum reverse-voltage rating
may be chosen.
Package Type
59-04 (axial leaded)
Case 403A (surface mount)
DO-204AL (axial leaded)
SOD64 (axial leaded)
SOD57 (axial leaded)
SOD87 (surface mount)
The steps for doing this are:
1. Calculate the minimum desired
RG;
2. Calculate total power
dissipation in the part
referring to Figure 77.
30
As an example, the total input
and output power dissipation can
be calculated given the following
conditions:
• ION, MAX ~ 2.0 A
• VCC2 = 18 V
• VEE = -5 V
• fCARRIER = 15 kHz
Step 1: Calculate RG minimum
from I OL peak specification:
To find the peak charging lOL
assume that the gate is initially
charged the steady-state value of
VEE. Therefore apply the
following relationship:
RG =
[[email protected] µA – (VOL+VEE)]
I OL,PEAK
= [V CC2 – 1 – (VOL + VEE )]
IOL,PEAK
18 V – 1 V – (1.5 V + (-5 V))
2.0 A
= 10.25 Ω
≈ 10.5 Ω (for a 1% resistor)
The HCPL-316J total power
dissipation (PT) is equal to the
sum of the input-side power (P I)
and output-side power (PO):
PI = ICC1 * VCC1
PO = P O(BIAS) + PO,SWTICH
PO(SWITCH) = transient power
dissipation in the HCPL-316J
due to charging and discharging
power device gate.
Step 2: Calculate total power
dissipation in the HCPL-316J:
1
IOFF (MAX.)
0
ION (MAX.)
-1
-2
-3
0 20 40 60 80 100 120 140 160 180 200
Rg (Ω)
Figure 76. Typical Peak ION and IOFF
Currents vs. Rg (for HCPL-316J
Output Driving an IGBT Rated at
600 V/100 A.
SWITCHING ENERGY vs. GATE RESISTANCE
(VCC2 / VEE2 = 25 V / 5 V
9
8
ESWITCH = Average Energy
dissipated in HCPL-316J due to
switching of the power device
over one switching cycle
(µJ/cycle).
f SWITCH = average carrier signal
frequency.
7
6
5
For RG = 10.5, the value read
from Figure 77 is E SWITCH =
6.05 µJ. Assume a worst-case
average ICC1 = 16.5 mA (which is
given by the average of I CC1H and
ICC1L ). Similarly the average
ICC2 = 5.5 mA.
P I = 16.5 mA * 5.5 V = 90.8 mW
P O = P O(BIAS) + PO,SWITCH
= 5.5 mA * (18 V – (–5 V)) +
6.051 µJ * 15 kHz
= 217.3 mW
Step 3: Compare the
calculated power dissipation
with the absolute maximum
values for the HCPL-316J:
For the example,
Ess (Qg = 650 nC)
4
3
2
1
0
= 126.5 mW + 90.8 mW
(Note from Figure 76 that the
real value of I OL may vary from
the value calculated from the
simple model shown.)
2
= ICC2 * (VCC2 –VEE ) +
E SWITCH * fSWITCH
where,
PO(BIAS) = steady-state power
dissipation in the HCPL-316J
due to biasing the device.
MAX. ION, IOFF vs. GATE RESISTANCE
(VCC2 / VEE2 = 25 V / 5 V
3
ION, IOFF (A)
P T = P I + PO
4
Ess (µJ)
(Average switching energy
supplied to HCPL-316J per
cycle vs. R G plot);
3. Compare the input and output
power dissipation calculated in
step #2 to the maximum
recommended dissipation for
the HCPL-316J. (If the
maximum recommended level
has been exceeded, it may be
necessary to raise the value of
RG to lower the switching
power and repeat step #2.)
0
50
100
150
200
Rg (Ω)
Figure 77. Switching Energy Plot for
Calculating Average Pswitch (for
HCPL-316J Output Driving an IGBT
Rated at 600 V/100 A).
PI = 90.8 mW < 150 mW
(abs. max.) ➱ OK
PO = 217.3 mW < 400 mW
(abs. max.) ➱ OK
Therefore, the power dissipation
absolute maximum rating has not
been exceeded for the example.
Please refer to the following
Thermal Model section for an
explanation on how to calculate
the maximum junction
temperature of the HCPL-316J
for a given PC board layout
configuration.
31
Thermal Model
The HCPL-316J is designed to
dissipate the majority of the heat
through pins 4 for the input IC
and pins 9 and 10 for the output
IC. (There are two VEE pins on
the output side, pins 9 and 10,
for this purpose.) Heat flow
through other pins or through the
package directly into ambient are
considered negligible and not
modeled here.
In order to achieve the power
dissipation specified in the
absolute maximum specification,
it is imperative that pins 4, 9, and
10 have ground planes connected
to them. As long as the maximum
power specification is not
exceeded, the only other limitation to the amount of power one
can dissipate is the absolute
maximum junction temperature
specification of 125°C. The
junction temperatures can be
calculated with the following
equations:
Since θ4A and θ9,10A are
dependent on PCB layout and
airflow, their exact number may
not be available. Therefore, a
more accurate method of calculating the junction temperature is
with the following equations:
T ji = Piθi4 + TP4
T jo = Poθo9,10 + TP9,10
These equations, however,
require that the pin 4 and pins
9,10 temperatures be measured
with a thermal couple on the pin
at the HCPL-316J package edge.
From the earlier power
dissipation calculation
example:
P i = 90.8 mW, Po = 314 mW, TA
= 100°C, and assuming the
thermal model shown in Figure
77 below.
T ji = (90.8 mW)(60°C/W
+ 50°C/W) + 100°C = 110°C
T ji = Pi(θi4 + θ4A) + TA
T jo = Po (θo9,10 + θ9,10A) + TA
T jo = (240 mW)(30°C/W
+ 50°C/W) + 100°C = 119°C
where P i = power into input IC
and Po = power into output IC.
both of which are within the
absolute maximum specification
of 125°C.
Tji
Tjo
θi4 = 60°C/W
θO9,10 = 30°C/W
TP4
TP9,10
θ4A = 50°C/W*
θ9,10A = 50°C/W*
If we, however, assume a worst
case PCB layout and no air flow
where the estimated θ4A and
θ9,10A are 100°C/W. Then the
junction temperatures become
Tji = (90.8 mW)(60°C/W
+ 100°C/W) + 100°C = 115°C
Tjo = (240 mW)(30°C/W
+ 100°C/W) + 100°C = 131°C
The output IC junction
temperature exceeds the absolute
maximum specification of 125°C.
In this case, PCB layout and
airflow will need to be designed
so that the junction temperature
of the output IC does not exceed
125°C.
If the calculated junction
temperatures for the thermal
model in Figure 78 is higher than
125°C, the pin temperature for
pins 9 and 10 should be
measured (at the package edge)
under worst case operating
environment for a more accurate
estimate of the junction
temperatures.
Tji = junction temperature of input side IC
Tjo = junction temperature of output side IC
TP4 = pin 4 temperature at package edge
TP9,10 = pin 9 and 10 temperature at package edge
θI4 = input side IC to pin 4 thermal resistance
θI9,10 = output side IC to pin 9 and 10 thermal resistance
θ4A = pin 4 to ambient thermal resistance
θ9,10A = pin 9 and 10 to ambient thermal resistance
TA
*The θ4A and θ9,10A values shown here are for PCB layouts shown in Figure 78 with
reasonable air flow. This value may increase or decrease by a factor of 2 depending
on PCB layout and/or airflow.
Figure 78. HCPL-316J Thermal Model.
Printed Circuit Board
Layout Considerations
Adequate spacing should always
be maintained between the high
voltage isolated circuitry and any
input referenced circuitry. Care
must be taken to provide the
same minimum spacing between
two adjacent high-side isolated
regions of the printed circuit
board. Insufficient spacing will
reduce the effective isolation and
increase parasitic coupling that
will degrade CMR performance.
The placement and routing of
supply bypass capacitors requires
special attention. During switching transients, the majority of the
gate charge is supplied by the
Figure 79. Recommended Layout(s).
bypass capacitors. Maintaining
short bypass capacitor trace
lengths will ensure low supply
ripple and clean switching
waveforms.
Ground Plane connections are
necessary for pin 4 (GND1) and
pins 9 and 10 (VEE ) in order to
achieve maximum power
dissipation as the HCPL-316J is
designed to dissipate the majority
of heat generated through these
pins. Actual power dissipation
will depend on the application
environment (PCB layout, air
flow, part placement, etc.) See
the Thermal Model section for
details on how to estimate
junction temperature.
The layout examples below have
good supply bypassing and
thermal properties, exhibit small
PCB footprints, and have easily
connected signal and supply
lines. The four examples cover
single sided and double sided
component placement, as well as
minimal and improved
performance circuits.
System Considerations
Propagation Delay Difference
(PDD)
The HCPL-316J includes a
Propagation Delay Difference
(PDD) specification intended to
help designers minimize “dead
time” in their power inverter
designs. Dead time is the time
period during which both the
high and low side power
transistors (Q1 and Q2 in
Figure 62) are off. Any overlap in
Q1 and Q2 conduction will result
in large currents flowing through
the power devices between the
high and low voltage motor rails,
a potentially catastrophic condition that must be prevented.
transistor Q1 has just turned off
when transistor Q2 turns on, as
shown in Figure 80. The amount
of delay necessary to achieve this
condition is equal to the maximum value of the propagation
delay difference specification,
PDDMAX, which is specified to be
400 ns over the operating
temperature range of -40°C to
100°C.
Delaying the HCPL-316J turn-on
signals by the maximum
propagation delay difference
ensures that the minimum dead
time is zero, but it does not tell a
designer what the maximum dead
time will be. The maximum dead
To minimize dead time in a given
design, the turn-on of the
HCPL-316J driving Q2 should be
delayed (relative to the turn-off of
the HCPL-316J driving Q1) so
that under worst-case conditions,
time is equivalent to the
difference between the maximum
and minimum propagation delay
difference specifications as
shown in Figure 81. The
maximum dead time for the
HCPL-316J is 800 ns (= 400 ns (-400 ns)) over an operating
temperature range of -40°C to
100°C.
Note that the propagation delays
used to calculate PDD and dead
time are taken at equal temperatures and test conditions since
the optocouplers under consideration are typically mounted in
close proximity to each other and
are switching identical IGBTs.
VIN+1
VOUT1
Q1 ON
Q1 OFF
Q2 ON
VOUT2
Q2 OFF
VIN+1
VIN+2
VOUT1
tPHLMIN
Q1 ON
Q1 OFF
Q2 ON
VOUT2
VIN+2
Q2 OFF
tPHLMAX
tPLHMIN
tPLHMAX
(tPHL-tPLH)MAX = PDD*MAX
tPHLMAX
tPLHMIN
PDD* MAX = (tPHL- tPLH)
MAX
= tPHLMAX - tPLHMIN
MAXIMUM DEAD TIME
(DUE TO OPTOCOUPLER)
= (tPHLMAX - tPHLMIN) + (tPLHMAX - tPLHMIN)
= (tPHLMAX - tPLHMIN) – (tPHLMIN - tPLHMAX)
= PDD*MAX – PDD*MIN
*PDD = PROPAGATION DELAY
NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS
ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION
DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
Figure 80. Minimum LED Skew for Zero Dead Time.
Figure 81. Waveforms for Dead Time Calculation.
For product information and a complete list of
Agilent contacts and distributors, please go to
our web site.
www.agilent.com/semiconductors
E-mail: [email protected]
Data subject to change.
Copyright © 2005 Agilent Technologies, Inc.
Obsoletes 5989-0784EN
March 1, 2005
5989-2143EN
WWW.ALLDATASHEET.COM
Copyright © Each Manufacturing Company.
All Datasheets cannot be modified without permission.
This datasheet has been download from :
www.AllDataSheet.com
100% Free DataSheet Search Site.
Free Download.
No Register.
Fast Search System.
www.AllDataSheet.com