Voltage Regulators
AN8049FHN
1.8-volt 3-channel step-up, step-down, and polarity inverting
DC-DC converter control IC
Unit: mm
■ Overview
A
(1.10)
7
R0.3
0.10 S
Seating plane
19
20
12
2.0±0.2
8
3.0±0.1
24
1
, ,,
, ,,
13
12
4.0±0.1
4.2±0.2
13
20
8
B
24
7
0.80max.
19
3.0±0.2
4.0±0.1
(1.10)
3-
C
0.
5
5.2±0.2
5.0±0.1
0.2±0.1
The AN8049FHN is a three-channel PWM DC-DC
converter control IC that features low-voltage operation.
This IC can form a power supply that provides two stepup outputs and one step-down or polarity inverted output
with a minimal number of external components. Minimal
operating supply voltage of this IC is as low as 1.8 V, so
that it can operate from 2 dry-batteries.
And also, it is housed in an ultrathin, 4-directionallead SMD-package whose thickness is 0.8 mm maximum
and pin-pitch is 0.5 mm therefore it is most suitable for
making a power supply small and thin.
1
0.50
0.2±0.1
0.10
M
S A B
S
■ Features
QFN024-P-0405
• Wide operating supply voltage range: 1.8 V to 14 V
• High-precision reference voltage circuit
— VREF pin voltage: ±1%
— Error amplifier: ±1.5%
• Ultrathin surface mounting package for miniaturized and thinner power supplies
Package: QFN-24
0.5-mm lead pitch
5.4 mm × 4.4 mm × t 0.8 mm
• Supports control over a wide output frequency range: 20 kHz to 1 MHz
• On/off (sequence control) pins provided for each channel for easy sequence control setup
• The negative supply error amplifier supports 0-volt input.
Common-mode input voltage range: − 0.1 V to VCC −1.4 V
This allows the number of external components to be reduced by two resistors.
• Fixed duty factor: 86%
However, the duty can be adjusted to anywhere from 0% to 100% with an external resistor.
• Timer latch short-circuit protection circuit (charge current: 1.1 µA typical)
• Low input voltage malfunction prevention circuit (U.V.L.O.)
(operation start voltage: 1.67 V typical)
• Standby function (active-high control input, standby mode current: 1 µA maximum)
■ Applications
• Electronic equipment that requires a power supply system
1
AN8049FHN
Voltage Regulators
50 kΩ
6
1.26 V
11
VREF
50 kΩ
1.26 V
FB2
CTL2
4
20
1.1 mA
2
Description
8
PWM2
50 kΩ
■ Pin Descriptions
Pin No.
OUT1
30 kΩ
20 kΩ
20 kΩ
1.26 V
VCC
Pin No.
Description
1
DT2
13
OUT3
2
DT1
14
VCC
3
CTL3
15
OSC
4
CTL2
16
IN+3
5
CTL1
17
IN−3
6
Off
18
FB3
7
VREF
19
IN−2
8
RB2
20
FB2
9
RB1
21
IN−1
10
OUT1
22
FB1
11
OUT2
23
S.C.P.
12
GND
24
DT3
30 kΩ
Error
amplifier 3
1.1 mA
1
3
13
PWM3
DT2
24
10
RB1
PWM1
0.9 V
VREF
Off
OSC
15
DT1
2
VREF
50 kΩ
R Q
S
Latch
1.26 V
S.C.P. comp.
18
19
0.7 V
V
0.3 V On/off CC
control
9
U.V.L.O.
1.1 mA
23
IN−2
Triangular wave generator
VCC
50 kΩ50 kΩ
CTL3
7
1.26 V
Error
16 amplifier 2
IN+3
17
IN−3
DT3
Reference voltage
supply VREF 1.26 V
(Allowance: ±1%)
20 kΩ
1.26 V
FB3
14
1.1 mA
5
Error
amplifier 1
S.C.P.
VCC
CTL1
FB1
22
21
IN-1
■ Block Diagram
12
OUT3
RB2
OUT2
GND
Voltage Regulators
AN8049FHN
■ Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Supply voltage
VCC
14.2
V
Off pin allowable application voltage
VOFF
14.2
V
Error amplifier input allowable
VIN
VCC
V
ISO(OUT)
−50
mA
ISI(OUT)
+50
mA
PD
111
mW
Operating temperature
Topr
−30 to +85
°C
Storage temperature
Tstg
−55 to +150
°C
application voltage
*2
OUT1 and OUT2 pin output
source current
OUT3 pin output current
Power dissipation
*1
Note) *1: Ta = 85°C. For the independent IC without a heat sink.
*2: When VCC is less than 6 V, VIN−1 and VIN+2 must be VCC.
■ Recommended Operating Range
Parameter
Symbol
Range
Unit
VOFF
0 to 14
V
OUT1 and OUT2 pin output source current
ISO(OUT)
−40 (min.)
mA
OUT3 pin output current
ISI(OUT)
40 (max.)
mA
Timing resistance
RT
3 to 33
kW
Timing capacitance
CT
100 to 1 000
pF
Oscillator frequency
fOUT
20 to 1 000
kHz
Short-circuit protection time-constant setting capacitance
CSCP
1 000 (min.)
pF
RB
750 to 15 000
Ω
Off pin application voltage
Output current setting resistance
3
AN8049FHN
Voltage Regulators
■ Electrical Characteristics at VCC = 2.4 V, CREF = 0.1 µF, Ta = 25°C
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
1.247
1.26
1.273
V
Reference voltage block
Reference voltage
VREF
IREF = − 0.1 mA
Line regulation with input fluctuation
Line
VCC = 1.8 V to 14 V
2
20
mV
Load regulation
Load
IREF = −0.1 mA to −1 mA
−20
−3
mV
Ta = −30°C to +85°C
1
%
IOC
−10
mA
VUON
1.59
1.67
1.75
V
VTH1
1.241
1.26
1.279
V
IB1
0.1
0.2
µA
High-level output voltage 1
VEH1
1.0
1.2
1.4
V
Low-level output voltage 1
VEL1
0.2
Output source current 1
ISO(FB)1
−38
−31
−24
µA
Output sink current 1
ISI(FB)1
0.5
mA
VTH temperature characteristics 1
VTHdT1
1.5
%
AV1
80
dB
VTH2
1.241
1.26
1.279
V
IB2
0.1
0.2
µA
High-level output voltage 2
VEH2
1.0
1.2
1.4
V
Low-level output voltage 2
VEL2
0.2
Output source current 2
ISO(FB)2
−38
−31
−24
µA
Output sink current 2
ISI(FB)2
0.5
mA
VTH temperature characteristics 2
VTHdT2
1.5
%
AV2
80
dB
Input offset voltage
VIO
−6
6
mV
Common-mode input voltage range
VICR
− 0.1
VCC
−1.4
V
IB3
− 0.6
− 0.3
µA
High-level output voltag 3
VEH3
1.0
1.2
1.4
V
Low-level output voltage 3
VEL3
0.2
Output source current 3
ISO(FB)3
−38
−31
−24
µA
Output sink current 3
ISI(FB)3
0.5
mA
AV3
80
dB
VREF temperature characteristics
VREF pin short-circuit current
VRFEdT
U.V.L.O. block
Circuit operation start voltage
Error amplifier 1 block
Input threshold voltage 1
Input bias current 1
Open-loop gain 1
Ta = −30°C to +85°C
Error amplifier 2 block
Input threshold voltage 2
Input bias current 2
Open-loop gain 2
Ta = −30°C to +85°C
Error amplifier 3 block
Input bias current 3
Open-loop gain 3
4
Voltage Regulators
AN8049FHN
■ Electrical Characteristics (continued) at VCC = 2.4 V, CREF = 0.1 µF, Ta = 25°C
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Oscillator block
Oscillator frequency
fOUT
RT = 7.5 kΩ, CT = 680 pF
170
190
210
kHz
Frequency supply voltage
characteristics
fDV
RT = 7.5 kΩ, CT = 680 pF
1
%
Frequency temperature
characteristics
fDT
RT = 7.5 kΩ, CT = 680 pF
3
%
Output duty factor 1
Du1
RT = 7.5 kΩ, CT = 680 pF
80
86
92
%
High-level output voltage 1
VOH1
IO = −10 mA, RB = 1 kΩ
VCC −1
V
Low-level output voltage 1
VOL1
IO = 10 mA, RB = 1 kΩ
0.2
V
Output source current 1
ISO(OUT)1 VO = 0.7 V, RB = 1 kΩ
−32
−27
−22
mA
Output sink current 1
ISI(OUT)1
VO = 0.7 V, RB = 1 kΩ
40
mA
Pull-down resistor 1
RO1
20
30
40
kΩ
Output 1 block
Output 2 block
Output duty factor 2
Du2
RT = 7.5 kΩ, CT = 680 pF
80
86
92
%
High-level output voltage 2
VOH2
IO = −10 mA, RB = 1 kΩ
VCC −1
V
Low-level output voltage 2
VOL2
IO = 10 mA, RB = 1 kΩ
0.2
V
Output source current 2
ISO(OUT)2 VO = 0.7 V, RB = 1 kΩ
−32
−27
−22
mA
Output sink current 2
ISI(OUT)2
VO = 0.7 V, RB = 1 kΩ
40
mA
Pull-down resistor 2
RO2
20
30
40
kΩ
80
86
92
%
0.2
V
Output 3 block
Output duty factor 3
Output saturation voltage
Du3
RT = 7.5 kΩ, CT = 680 pF
VO(SAT)
Short-circuit protection circuit block
Input standby voltage
VSTBY
0.1
V
Input threshold voltage
VTHPC
0.8
0.9
1.0
V
Input latch voltage
VIN
0.1
V
Charge current
ICHG
−1.3
−1.0
−0.7
µA
Comparator threshold voltage
VTHL
1.26
V
VON(TH)
0.7
1.0
1.3
V
35
µA
1.07
1.26
1.47
V
−1.3
−1.0
−0.7
µA
4.2
5.5
mA
1
µA
VSCP = 0 V
On/off control block
Input threshold voltage
Off pin current
IOFF
VOFF = 5 V
CTL block
Input threshold voltage
Charge current
VTHCTL
ICTL
VCTL = 0 V
Whole device
Average consumption current
ICC(OFF)
Standby mode current
ICC(SB)
RB = 9.1 kΩ, duty = 50%
5
AN8049FHN
Voltage Regulators
■ Terminal Equivalent Circuit
Pin No.
Equivalent circuit
1
7 20 15
50 kΩ
1
50 kΩ
PWM2
2
7 22 15
50 kΩ
2
50 kΩ
PWM1
3
VCC
1.1 µA
20 kΩ
3
6
High
channel 3 operation
1.26 V is turned off.
Description
I/O
DT2:
Sets the channel 2 soft start time.
Set the time by connecting a capacitor
between this pin and ground.
Note that although the channel 2
maximum on duty is set internally to
86%, the maximum on duty can be set
to a value of 86% or less by inserting
a resistor between this pin and ground,
and can be set to a value of 86% or
more by inserting a resistor between
this pin and the VREF pin.
I
DT1:
Sets the channel 1 soft start time.
Set the time by connecting a capacitor
between this pin and ground.
Note that although the channel 1
maximum on duty is set internally to
86%, the maximum on duty can be set
to a value of 86% or less by inserting
a resistor between this pin and ground,
and can be set to a value of 86% or
more by inserting a resistor between
this pin and the VREF pin.
CTL3:
Controls the on/off state of channel 3.
A delay can be provided in the power
supply turn-on start time by connecting
a capacitor between this pin and ground.
tDLY3 = 1.26 (V) × CCTL3 (µF)/1.1 (µA) (s)
This pin can also be used to control the
on/off state with an external signal.
In that case, the allowable input voltage
range is from 0 V to VCC. Note that
during U.V.L.O. and timer latch
operation, this pin is connected to
ground through a 20 kΩ resistor.
I
Voltage Regulators
AN8049FHN
■ Terminal Equivalent Circuit (continued)
Pin No.
Equivalent circuit
4
VCC
1.1 µA
20 kΩ
High
channel 2 operation
1.26 V is turned off.
4
5
VCC
1.1 µA
20 kΩ
High
channel 1 operation
1.26 V is turned off.
5
6
6
100 kΩ
Start and stop of
internal circuits.
7
VCC
7
Description
I/O
CTL2:
Controls the on/off state of channel 2.
A delay can be provided in the power
supply turn-on start time by connecting
a capacitor between this pin and ground.
tDLY2 = 1.26 (V) × CCTL2 (µF)/1.1 (µA) (s)
This pin can also be used to control the
on/off state with an external signal.
In that case, the allowable input voltage
range is from 0 V to VCC. Note that
during U.V.L.O. and timer latch
operation, this pin is connected to
ground through a 20 kΩ resistor.
I
CTL1:
Controls the on/off state of channel 1.
A delay can be provided in the power
supply turn-on start time by connecting
a capacitor between this pin and ground.
tDLY1 = 1.26 (V) × CCTL1 (µF)/1.1 (µA) (s)
This pin can also be used to control the
on/off state with an external signal.
In that case, the allowable input voltage
range is from 0 V to VCC. Note that
during U.V.L.O. and timer latch
operation, this pin is connected to
ground through a 20 kΩ resistor.
I
Off:
Controls the on/off state.
When the input is high: normal
operation
(VOFF > 1.2 V)
When the input is low: standby mode
VOFF < 0.6 V)
In standby mode, the total current
consumption is held to under 1 µA.
I
VREF:
Outputs the internal reference voltage.
The reference voltage is 1.26 V
(allowance: ±1%) when VCC is 2.4 V
and IREF is −0.1 mA. Insert a capacitor
of at least 0.1 µF between VREF and
ground for phase compensation.
O
7
AN8049FHN
Voltage Regulators
■ Terminal Equivalent Circuit (continued)
Pin No.
8
Equivalent circuit
Description
VCC
I/O
RB2:
Connection for a resistor that sets the
channel 2 output source current.
Use a resistor in the range 750 Ω to
1.5 kΩ.
I
RB1:
Connection for a resistor that sets the
channel 1 output source current.
Use a resistor in the range 750 Ω to
1.5 kΩ.
I
OUT1:
O
11
200 Ω
30 kΩ
8
9
VCC
10
200 Ω
30 kΩ
9
10
VCC
9
Push-pull output.
The absolute maximum rating for the
ISO(OUT)1
10
output source current is −50 mA.
Connecting the external resistor to RB1
terminal allows this circuit to provide
30 kΩ
an output source current with excellent
line regulation and minimal sample-tosample variations.
11
OUT2:
VCC
8
ISO(OUT)2
11
O
Push-pull output.
The absolute maximum rating for the
output source current is −50 mA.
Connecting the external resistor to RB2
terminal allows this circuit to provide
30 kΩ
an output source current with excellent
line regulation and minimal sample-tosample variations.
12
GND:
Ground.
12
8
Voltage Regulators
AN8049FHN
■ Terminal Equivalent Circuit (continued)
Pin No.
Equivalent circuit
13
Description
OUT3:
VCC
O
Open-collector output.
The absolute maximum rating for the
output current is +50 mA.
13
14
14
15
VCC
Latch
S
Q
0.2 V R
15
VCC
16
I/O
VCC:
Power supply terminal.
Provide the operating supply voltage
in the range 1.8 V to 14 V.
OSC:
Connection for the capacitor and
resistor that determine the oscillator
frequency. Use a capacitor in the range
100 pF to 1 000 pF and a resistor in
the range 3 kΩ to 33 kΩ. Use an
oscillator frequency in the range
20 kHz to 1 MHz.
O
IN+3:
I
Noninverting input to the error
amplifier 3.
17
17
1.5 kΩ
16
1.5 kΩ
18
7
I
FB3:
O
Output from the error amplifier 3.
31 µA
OSC
16
17
IN−3:
Inverting input to the error amplifier 3.
This circuit can provide a source
PWM3
current of −31 µA or a sink current of
0.5 mA (minimum).
0.5 mA
min.
18
19
IN−2:
Inverting input to the error amplifier 2.
14
19
I
1.5 kΩ
1.26 V
9
AN8049FHN
Voltage Regulators
■ Terminal Equivalent Circuit (continued)
Pin No.
Equivalent circuit
Description
VCC
20
FB2:
31 µA
OSC
19
I/O
O
Output from the error amplifier 2.
PWM2
This circuit can provide a source
current of −31 µA or a sink current of
0.5 mA (minimum).
0.5 mA
min.
1.26 V
20
21
14
21
IN−1:
Inverting input to the error amplifier 1.
I
FB1:
O
1.5 kΩ
1.26 V
22
VCC
31 µA
OSC
21
Output from the error amplifier 1.
PWM1
This circuit can provide a source
current of −31 µA or a sink current of
0.5 mA (minimum).
0.5 mA
min.
1.26 V
22
23
S.C.P.:
VCC
O
Connection for the capacitor that sets
the timer latch short-circuit protection
1.1 µA
1.5 kΩ
Latch
S
Q
1.26 V R
Output
shutoff
23
24
with a value of 1 000 pF or higher.
The charge current ICHG is 1.1 µA
typical.
DT3:
7 18 15
50 kΩ
24
PWM3
50 kΩ
10
circuit time constant. Use a capacitor
Sets the channel 3 soft start time.
Set the time by connecting a capacitor
between this pin and ground. Note that
although the channel 3 maximum on duty
is set internally to 86%, the maximum
on duty can be set to a value of 86% or
less by inserting a resistor between this
pin and ground, and can be set to a value
of 86% or more by inserting a resistor
between this pin and the VREF pin.
I
Voltage Regulators
AN8049FHN
■ Usage Notes
[1] Allowable power dissipation
Since the power dissipation (P) in this IC increases proportionally with the supply voltage, applications must be
careful to operate so that the loss does not exceed the allowable power dissipation, PD, for the package.
Reference formula:
P = (VCC−VBEQ1) × ISO(OUT)1 × Du1
← Power dissipation in the channel 1 output stage
+(VCC−VBEQ2) × ISO(OUT)2 × Du2
← Power dissipation in the channel 2 output stage
+VO(SAT)3 × IOUT3 × Du3
← Power dissipation in the channel 3 output stage
+VCC × ICC
← Power dissipation between VCC and ground
<PD
VBEQ1
: The voltage between the base and emitter of the npn transistor Q1
ISO(OUT)1 : The OUT1 pin output source current
(When RRB1 is 1 kΩ, ISO(OUT)1 will be 38 mA, maximum.)
Du1
: The output 1 duty factor
VBEQ2
: The voltage between the base and emitter of the npn transistor Q2
ISO(OUT)2 : The OUT2 pin output source current
(When RRB2 is 1 kΩ, ISO(OUT)2 will be 38 mA, maximum.)
Du2
: The output 2 duty factor
VO(SAT)3 : The OUT3 pin saturation voltage (0.5 V maximum when OUT1 is 40 mA.)
IOUT3
: The OUT3 pin current (This will be {VCC − VBEQ3 − VO(SAT)3}/RO3.)
Du3
: The output 3 duty factor
ICC
: The VCC pin current
[2] Allowable VCC ripple
VCC ripple due to the switching transistor being turned on and off can cause this IC's U.V.L.O. circuit, which is
biased by VCC, to operate incorrectly, and can cause the S.C.P. capacitor charging operation to fail to start when the
output is shorted.
The figure shows the allowable range for VCC ripple. Applications should reduce VCC ripple to be within this range,
either by inserting a ripple filter in the VCC line or by inserting a capacitor between the IC GND and VCC pins and
locating that capacitor as close to the IC as possible.
Note that the allowable range shown here is the result of testing the IC alone and that the allowable range may
differ depending on the actual structure of the power supply circuit. Also note that this allowable range is a design
target, and is not guaranteed by testing of all samples.
Allowable VCC ripple
Ripple frequency (Hz)
10 M
Allowable range
when VCC is 3 V.
1M
100 k
Allowable range
when VCC is 10 V.
10 k
0
1
2
3
4
5
6
7
8
VCC ripple voltage VCC(AC) (V[p-p])
11
AN8049FHN
Voltage Regulators
■ Application Notes
[1] QFN024-P-0405 package power dissipation
PD T a
1.200
When mounted on a 4-layer printed
circuit board (50×50×t0.8 mm3)
Rth(j−a) = 93.0°C/W
1.075
Power dissipation PD (W)
1.000
When mounted on a standard
printed circuit board
(glass epoxy: 50×50×t0.8 mm3)
Rth(j−a) = 151.5°C/W
0.800
0.660
0.600
0.400
0.279
0.200
Independent IC
without a heat sink
Rth(j−a) = 357.4°C/W
0.000
0
25
50
75 85
100
Ambient temperature Ta (°C)
12
125
Voltage Regulators
AN8049FHN
■ Application Notes (continued)
[2] Main characteristics
fOSC Maximum output duty
(RT = 3 kΩ)
Timing capacitance Oscillator frequency
95
1M
Du1 , Du2 , Du3 (%)
fOUT (Hz)
90
RT = 3 kΩ
100k
RT = 7.5 kΩ
Du3
Du1 , Du2
85
80
RT = 33 kΩ
10k
10p
1n
75
10k
10n
100k
1M
fOSC (Hz)
CT (F)
fOSC Maximum output duty
fOSC Maximum output duty
(RT = 7.5 kΩ)
(RT = 33 kΩ)
95
95
90
90
85
Du1 , Du2 , Du3 (%)
Du1 , Du2 , Du3 (%)
Du2
Du3
Du1 , Du2
80
Du3
Du1
85
80
75
10k
100k
75
10k
1M
100k
fOSC (Hz)
RB ISO(OUT)
RB ISI(OUT)
0
100
−10
90
80
−20
70
ISI(OUT) (mA)
ISO(OUT) (mA)
VCC = 1.8 V
−30
2.4 V
−40
−50
1M
fOSC (Hz)
8V
VCC = 14 V
60
50
40
30
−60
20
−70
−80
100
14 V
8V
10
1k
10k
RB (Ω)
100k
0
100
1.8 V, 2.4 V
1k
10k
100k
RB (Ω)
13
AN8049FHN
Voltage Regulators
■ Application Notes (continued)
[3] Timing charts
VCC pin voltage
waveform
1.67 V
Output short
1.26 V
S.C.P. pin
voltage
waveform
CTL pin
voltage
1.26 V
waveform
FB
OSC
DT
0.9 V
OUT1/2 pin voltage waveform
Totem pole circuit
output (Step-up output)
OUT3 pin voltage waveform
Open-collector output
(Inverting or step-down output)
14
Voltage Regulators
AN8049FHN
■ Application Notes (continued)
[4] Function descriptions
1. Reference voltage block
This circuit is composed of a band gap circuit, and outputs a 1.26 V (typical) reference voltage that is
temperature compensated to a precision of ±1%. This reference voltage is stabilized when the supply voltage is 1.8
V or higher. This reference voltage is used by error amplifiers 1 and 2.
2. Triangular wave generator
This circuit generates a triangular wave like a
VOSCH
sawtooth with a peak of 0.7 V and a trough of 0.2 V
0.7 V
using a capacitor CT (for the time constant) and resistor
RT connected to the OSC pin (pin 15). The oscillator
frequency can be set to an arbitrary value by selecting
appropriate values for the external capacitor and resisVOSCL
tor, CT and RT. This IC can use an oscillator frequency
0.2 V
t
t
2
1
in the range 20 kHz to 1 MHz. The triangular wave
signal is provided to the noninverting input of the PWM
Discharge
Rapid charge
comparator in each channel internally to the IC. Use
T
the formulas below for rough calculation of the oscillator frequency.
Figure 1. Triangular oscillator waveform
1
≈ 0.8 ×
(Hz)
VOSCL
CT × RT
CT × RT × ln
VOSCH
Note, however, that the above formulas do not take the rapid charge time, overshoot, and undershoot into
account. See the experimentally determined graph of the oscillator frequency vs. timing capacitance value provided in the main characteristics section.
fOSC ≈ −
1
3. Error amplifier 1
This circuit is an npn-transistor input error amplifier
that detects and amplifies the DC-DC converter output
voltage, and inputs that signal to a PWM comparator.
The 1.26 V internal reference voltage is applied to the
noninverting input. Arbitrary gain and phase compensation can be set up by inserting a resistor and capacitor
in series between the FB1 pin (pin 22) and the IN±1 pin
(pin 21). The output voltage VOUT1 can be set using the
circuit shown in the figure.
FB1
22
VOUT1
R1
Error
amplifier 1
21
IN−1
R2
VOUT1 = 1.26 ×
1.26 V To the PWM
comparator input
R1 + R2
R2
Figure 2. Connection method of error amplifier 1
(Step-up output)
15
AN8049FHN
Voltage Regulators
■ Application Notes (continued)
[4] Function descriptions (continued)
4. Error amplifier 2
This circuit is an npn-transistor input error
amplifier that detects and amplifies the DC-DC
converter output voltage, and inputs that signal to
a PWM comparator. The 1.26 V internal reference
voltage is applied to the noninverting input. Arbitrary gain and phase compensation can be set up
by inserting a resistor and capacitor in series between the FB2 pin (pin 20) and the IN−2 pin (pin
19). The output voltage VOUT2 can be set using the
circuit shown in the figure.
FB2
20
VOUT2
R1
Error
amplifier 2
19
IN−2
1.26 V To the PWN
comparator input
R2
VOUT2 = 1.26 ×
R1 + R2
R2
Figure 3. Connection method of error amplifier 2 (Step-up output)
5. Error amplifier 3
This circuit is a pnp-transistor input error amplifier that detects and amplifies the DC-DC converter output
voltage and inputs that signal to a PWM comparator. Arbitrary gain and phase compensation can be set up by
inserting a resistor and capacitor in series between the FB3 pin (pin 18) and the IN−3 pin (pin 17). The output voltage
VOUT3 can be set using the circuit shown in the figure.
Step-down output
Inverting output
FB3
FB3
18
VREF VOUT3
R1
VREF
R3
IN+3
R2
R4
18
IN−3
R1
Error
amplifier 3
16
17
IN+3
To the PWM
comparator input
R R
R2
VOUT3 =
× 3+ 4 × VREF
R4
R1+R2
Error
amplifier 3
16
17
R2
To the PWM
comparator input
IN−3
VOUT3
VOUT3 = −VREF ×
R2
R1
Figure 4. Connection method of error amplifier 3
6. Timer latch short-circuit protection circuit
This circuit protects the external main switching elements, flywheel diodes, choke coils, and other components
against degradation or destruction if an excessive load or a short circuit of the power supply output continues for
longer than a certain fixed period.
The timer latch short-circuit protection circuit detects the output of the error amplifiers. If the DC-DC converter
output voltage drops and an FB pin (pins 18, 20, or 22) voltage exceeds 0.9 V, the S.C.P. comparator outputs a low
level and the timer circuit starts. This starts charging the external protection circuit delay time capacitor.
If the error amplifier output does not return to the normal voltage range before that capacitor reaches 1.26 V,
the latch circuit latches, the output drive transistors are turned off, and the dead-time is set to 100%.
16
Voltage Regulators
AN8049FHN
■ Application Notes (continued)
[4] Function descriptions (continued)
7. Low input voltage malfunction prevention circuit (U.V.L.O.)
This circuit protects the system against degradation or destruction due to incorrect control operation when the
power supply voltage falls during power on or power off.
The low input voltage malfunction prevention circuit detects the internal reference voltage that changes with
the supply voltage level. While the supply voltage is rising, this circuit cuts off the output drive transistor until the
reference voltage reaches 1.67 V. It also sets the dead-time to 100% and at the same time holds the S.C.P. pin (pin
23) and the DT pins (pins 1, 2, and 24) at 0 V, and the OSC pin (pin 15) at about 1.2 V.
8. PWM comparators
The PWM comparators control the on-period of the output pulse according to their input voltage.
The output transistors are turned on during periods when the OSC pin (pin 15) triangular wave is lower than
both of the corresponding FB pin (pins 18, 20, or 22) and the corresponding DT pin (pins 1, 2, or 24).
The PWM 2 circuit turns the output transistor on during periods when OSC pin (pin 15) triangular wave is at
a higher level than both of the FB2 pin (pin 20) and the DT2 pin (pin 1).
The maximum duty is set to 86% internally, but it can be set to a value lower than 86% by inserting a resistor
between the corresponding DT pin and ground, and can be set to a value higher than 86% by inserting a resistor
between the corresponding DT pin and the VREF pin.
The IC's soft start function operates to gradually increase the width of the output pulse on-period during startup
if a capacitor is inserted between the DT pin and ground.
9. Output 1 and output 2 blocks
These output circuits have a totem pole structure. A constant-current source output with good line regulation
can be set up freely by connecting current setting resistors to the RB pins.
These circuits can provide a constant-current source output of up to 50 mA.
10. Output 3 block
This output circuit has an open collector structure.
An output current of up to 50 mA can be provided, and the output pin has a breakdown voltage of 15 V.
11. CTL block
The CTL block output circuit also has a totem pole structure. A constant-current source output with good line
regulation can be set up freely by connecting current setting resistors to the RB2 pin.
The CTL block can provide a constant-current source output of up to 50 mA.
17
AN8049FHN
Voltage Regulators
■ Application Notes (continued)
[5] Time constant setup for the timer latch short-circuit protection circuit
Figure 6 shows the structure of the timer latch short-circuit protection circuit. The short-circuit protection
comparator continuously compares a 0.9 V reference voltage with the FB1, FB2, and FB3 error amplifier outputs.
When the DC-DC converter output load conditions are stable, the short-circuit protection comparator holds its
average value since there are no fluctuations in the error amplifier outputs. At this time, the output transistor Q1 will
be in the conducting state, and the S.C.P. pin will be held at 0 V.
If the output load conditions change rapidly and a high-level signal (0.9 V or higher) is input to the short-circuit
protection comparator from the error amplifier output, the short-circuit protection comparator will output a low level
and the output transistor Q1 will shut off. Then, the capacitor CSCP connected to the S.C.P. pin will start to charge.
When the external capacitor CSCP is charged to about 1.26 V by the constant current of about 1.1 mA, the latch circuit
will latch and the dead-time will be set to 100% with the output held fixed at the low level. Once the latch circuit has
latched, the S.C.P. pin capacitor will be discharged to about 0 V, but the latch circuit will not reset unless either power
is turned off or the power supply is restarted using on/off control.
1.26 V = ICHG ×
tPE
CSCP
∴tPE (s) = 1.15 × CSCP (µF)
VSCP (V)
At power supply startup, the output appears to be
in the shorted state, and the IC starts to charge the
S.C.P. pin capacitor. Therefore, users must select an
external capacitor that allows the DC-DC converter
output voltage to rise before the latch circuit in the
later stage latches. In particular, care is required if the
soft start function is used, since that function makes
the startup time longer.
1.26
Short-circuit detection time tPE
0
t (s)
Figure 5. S.C.P. pin charging waveform
On/off control
VREF
VCC
U.V.L.O.
FB1
FB2
20
18
Latch
R
Q
S
High level detection comparator
1.26 V
S.C.P. comp. Q1
0.9 V
23
FB3
1.1 µA
22
S.C.P.
Figure 6. Short-circuit protection circuit
18
Output shutoff
Voltage Regulators
AN8049FHN
■ Application Notes (continued)
[6] Parallel synchronous operation of multiple ICs
Multiple instances of this IC can be operated in parallel. If the OSC pins (pin 15) and Off pins (pin 6) are connected
to each other as shown in figure 7, the ICs will operate at the same frequency.
It is also possible to operate a one-channel control IC (e.g. the AN8016SH or AN8016NSH) and a two-channel
control IC (e.g. the AN8017SA or AN8018SA) in this parallel synchronous mode. In this case, short the OSC and Off
pins together.
Note that it is not possible to control the on/off states of each IC operating in this mode independently. It is only
possible to turn all the ICs on or off at the same time remotely.
15
OSC
15 OSC
OSC pins
connected
together
AN8049FHN
AN8049FHN
VREF 7
Off 6
H
VREF 7
S.C.P. 2
Off 6
S.C.P. 2
L
Off pins
connected
together
Figure 7. Slave operation circuit example
19
AN8049FHN
Voltage Regulators
■ Application Notes (continued)
[7] Sequential operation
Delays can be provided in the startup times by inserting capacitors (CCTL) between the CTL pins and ground.
Delay time: tDLY = 1.26 (V) × CCTL (µF)/1.1 (µA) (s)
Note that the individual channels can also be turned on or off independently by external signals. These external
signals may have voltages in the range 0 V to VCC.
CTL1
AN8049FHN
CCTL3
CTL1 5
CTL2 4
CTL3 3
1.26 V
U.V.L.O. cleared
CCTL1
CCTL2
OUT1
CCTL1 < CCTL2 < CCTL3
OUT2
OUT3
Figure 8. Sequential operation
20
CTL2
CTL3
Voltage Regulators
AN8049FHN
■ Application Notes (continued)
[8] Differences between this IC and the AN8049SH
The pin arrangements differ. The AN8049SH is an alternative package version of this IC.
OUT3
13
14
15
VCC
OSC
IN+3
16
IN−3
17
24
8
OUT2
OUT1
RB1
RB2
VREF
Off
CTL1
DT1
DT2
GND
7
9
6
23
5
10
4
22
1
DT3
11
CTL2
S.C.P.
21
CTL3
FB1
12
3
IN−1
20
2
FB2
18
19
FB3
IN−2
AN8049FHN
OUT2
13
OUT1
12
GND
14
RB1
11
OUT3
RB2
15
10
VCC
VREF
16
9
OSC
Off
17
8
IN+3
CTL1
18
7
IN−3
CTL2
19
6
FB3
CTL3
20
5
IN−2
DT1
21
4
FB2
22
DT2
3
IN−1
23
2
DT3
24
S.C.P.
1
FB1
AN8049SH
21
AN8049FHN
Voltage Regulators
■ Application Notes (continued)
[9] Error amplifier frequency characteristics
1. Error amplifiers 1 and 2
(Test circuit)
40
1 kΩ
30
IN−1
100 kΩ
Amp.1
VOUT
FB1
VREF
1.26 V
2.3 V
20
Gain (dB)
10 µF
VIN
4 mV[P-P]
100 kΩ
10
0
-10
-20
180
Phase (°)
135
90
45
0
−45
1k
10k
100k
1M
10M
100M
10M
100M
Frequency (Hz)
2. Error amplifier 3
(Test circuit)
1V
VIN
4 mV[p-p]
30
1 kΩ
IN−3
Amp.3
1 kW
IN+3
1 kΩ
FB3
VOUT
20
Gain (dB)
10 µF
40
10
0
100 kΩ
−10
10 µF
−20
0
Phase (°)
−45
−90
−135
−180
−225
1k
10k
100k
1M
Frequency (Hz)
22
Voltage Regulators
AN8049FHN
VIN
■ Application Circuit Example
−
VO3
13 OUT3
14 VCC
15 OSC
16 IN+3
17 IN−3
18 FB3
19 IN−2
Q3
VREF
FB2 20
12 GND
IN−1 21
11 OUT2
FB1 22
10 OUT1
+
VO1
Q2
Q1
RB1
RB2
VREF 7
Off 6
CTL1 5
CTL2 4
8
CTL3 3
DT3 24
DT1 2
9
DT2 1
S.C.P. 23
+
VO1
23