TC9256, 57APG/AFG TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC9256APG, TC9256AFG, TC9257APG, TC9257AFG PLL for DTS TC9256APG The TC9256APG, TC9256AFG, TC9257APG and TC9257AFG are phase-locked loop (PLL) LSIs for digital tuning systems (DTS) with built-in two-modulus prescalers. All functions are controlled through three serial bus lines. These LSIs are used to configure high-performance digital tuning systems. Features TC9257APG • Suitable for use in digital tuning systems in high-fi tuners and car stereos. • Built-in prescalers operate at an input frequency ranging from 30 to 150 MHz during FMIN input (with two-modulus prescaler) and at 0.5 to 40 MHz during AMIN input (with two-modulus prescaler or direct dividing) • 16-bit programmable counter, dual parallel output phase comparator, crystal oscillator and reference counter • 3.6 MHz, 4.5 MHz, 7.2 MHz or 10.8 MHz crystal oscillators can be used. • 15 possible reference frequencies (when using 4.5 MHz crystal):ref. = 0.5 k, 1 k, 2.5 k, 3 k, 3.125 k, 3.90625 k, 5 k, 6.25 k, 7.8125 k, 9 k, 10 k, 12.5 k, 25 k, 50 k and 100 kHz. • Built-in 20-bit general-purpose counter for such uses as measuring intermediate frequencies (IFIN1 and IFIN2) and low-frequency pilot signal cycles (SCIN). (No cycle measurement function is available on the TC9256APG and TC9256AFG.) • High-precision (±0.55 to ±7.15 µs) PLL phase error detection • Numerous general-purpose I/O pins for such uses as peripheral circuit control • Four N-channel open-drain output ports (OFF withstanding voltage: 12 V) for such uses as control signal output. (TC9256APG and TC9256AFG have only three ports.) • Standby mode function (turns off FM, AM and IF amps) to save current consumption • All functions controlled through three serial bus lines • CMOS structure with operating power supply range of VDD = 5.0 ± 0.5 V. • 16-pin DIP (TC9256APG), 20-pin DIP (TC9257APG), 16-pin SOP (TC9256AFG), 20-pin SOP (TC9257AFG) packages 1 TC9256AFG TC9257AFG Weight P-DIP16-300-2.54A: 1.0 g (typ.) P-DIP20-300-2.54A: 1.24 g (typ.) P-SOP16-300-1.27A: 0.16 g (typ.) P-SOP20-300-1.27A: 0.48 g (typ.) 2006-07-14 TC9256, 57APG/AFG Pin Assignment (Top view) TC9256APG, TC9256AFG TC9257APG, TC9257AFG Block Diagram Note: There are no pins marked z in the TC9256APG or TC9256AFG. Pin names and numbers in parentheses apply to the TC9256APG and TC9256AFG. Other pins are common to the TC9256APG, TC9256AFG, TC9257APG and TC9257AFG. 2 2006-07-14 TC9256, 57APG/AFG Pin Function Pin No. 1 Symbol Pin Name Circuit Diagram XT Crystal oscillator pins 2 XT 3 PERIOD CLOCK Clock signal input 5 DATA Serial data input/output 6 OT-1 OT-2 General-purpose output ports 8 OT-3 9 (⎯) OT-4 10 (⎯) I/O-5/CLK 11 (⎯) I/O-6 13 (10) AMIN FMIN 16 (13) I/O-9 (-6) /IFIN2 17 (14) I/O-8 (-5) /IFIN1 Serial I/O ports. These pins transfer data to and from the controller to set divisors and dividing modes, and to control the general-purpose counter and general-purpose I/O ports. N-channel open drain port pins, for such uses as control signal output. These pins are set to the OFF state when power is turned on. (On the TC9256APG and TC9256AFG, OT-4 can be used as a CMOS output pin by being switched with DO2.) The CMOS structure allows free use of these ports for input or output. Ports are General-purpose I/O set for input when the power is turned on. ports On the TC9257APG and TC9257AFG, I/O-5 can be switched for use as a system clock output pin. Programmable counter input 14 (11) Connects a 3.6 MHz, 4.5 MHz, 7.2 MHz or 10.8 MHz crystal oscillator to supply reference frequency and internal clock. Period signal input 4 7 Function These pins input FM and AM band local oscillator signals.. These pins feature built-in amps. Connecting a capacitor permits low-amplitude operation. General-purpose I/O port input/output pins. Can be switched for use as input pins to measure general-purpose counter General-purpose I/O frequencies. The frequency measurement function has such uses as ports measuring intermediate frequencies (IF). /General-purpose counter frequency These pins feature built-in amps. measurement input Connecting a capacitor permits low-amplitude operation. Note: These pins are set for input when power is turned on. 3 2006-07-14 TC9256, 57APG/AFG Pin No. Symbol 18 (⎯) I/O-7/SCIN 19 (15) DO1 20 (16) DO2 (DO2/OT-4) 15 (12) GND 12 (9) VDD Pin Name Function General-purpose I/O ports /General-purpose counter cycle measurement input General-purpose I/O port input/output pin. Can be switched for use as signal input pin to measure low-frequency signal cycles. (Not available on the TC9256APG and TC9256AFG.) Note: This pin is set for input when power is turned on. Phase comparator output (General-purpose output ports) These pins are for phase comparator tristate output. DO1 and DO2 are output in parallel. (On the TC9256APG and TC9256AFG, DO2 can be switched for use as a general-purpose output port.) Power supply pins Applies 5.0 V ± 10%. Circuit Diagram ⎯ Note 1: Pin numbers 1 to 8 are common to the TC9256APG, TC9256AFG, TC9257APG and TC9257AFG. Note 2: Pin names and numbers in parentheses apply to the TC9256APG and TC9256AFG. 4 2006-07-14 TC9256, 57APG/AFG Functions and Operation Serial I/O Ports As the block diagram shows, the functions of the TC9256APG, TC9256AFG, TC9257APG and TC9257AFG are controlled by setting data in the 48 bits contained in each of the two sets of 24-bit registers. Each bit of data in these registers is transferred through the serial ports between the controller and the DATA, CLOCK and PERIOD pins. Each serial transfer consists of a total of 32 bits, with 8 address bits and 24 data bits. Since all functions are controlled in units of registers, the explanation here focuses on the 8-bit addresses and functions of each register. These registers consist of 24 bits and are selected by an 8-bit address. A list of the address assignments for each register is given below under Register Assignments. Register Input Register 1 Address D0H 24-Bit Composition No. of Bits PLL divisor setting Reference frequency setting PLL input and mode setting Crystal oscillator selection Total Input Register 2 D2H 16 4 2 2 24 4 General-purpose counter control (Including lock-detection bit control) I/O port and general-purpose counter switching bits I/O-5/CLK pin switching bit (DO2/OT-4 pin switching bit for TC9256APG and TC9256AFG) DO pin control TEST bit I/O port control (Also used as general-purpose counter input-selection bits) Output data 3 1 1 1 5 9 24 Total Output Register 1 Output Register 2 D1H D3H General-purpose counter numeric data Not used Total 22 2 24 Total 5 5 4 5 5 24 Lock detection data I/O port control data Output data Input data (undefined during output port selection) Not used On the falling edge of the PERIOD signal, the input data is latched in register 1 or register 2 and the function is performed. On the ninth falling edge of the CLOCK signal, the output data is latched in parallel in the output registers. The data are subsequently output serially from the data pin. 5 2006-07-14 TC9256, 57APG/AFG Register Assignments When power is turned on, the input registers are set as shown below. *1: This setting is not available on the TC9256APG and TC9256AFG. *2: The data is “0” on the TC9256APG and TC9256AFG. *3: Bit names in parentheses “( )” apply to the TC9256APG and TC9256AFG. *4: Data is undefined. *5: Set data to “0” for the TEST bit. 6 2006-07-14 TC9256, 57APG/AFG Serial Transfer Format The serial transfer format consists of 8 address bits and 24 data bits (Figure 1). Addresses D0H to D3H are used. Figure 1 • Serial data transfer Serial data are transferred in sync with the clock signal. In the idle state, the PERIOD, CLOCK and DATA pin lines are all set to “H” level. When the period signal is at “L” level, serial data transfer starts at the falling edge of the clock signal. Data transfer ends when the period signal is set to “L” level while the clock signal is at “H” level. Once serial data transfer has begun, however, no more than 8 falls of the clock signal can occur during the time the period signal is at “L” level. Since the receiving side receives the serial data as valid data at the rising edge of the clock signal, it is effective for the sending side to produce output in sync with the falling edge of the clock signal. To receive serial data from the output registers (D1H, D3H), set the serial data output to high impedance after the 8-bit address is output but before the next falling edge of the clock signal. Data reception subsequently continues until the period signal becomes “L” level; data transfer ends just before the rising edge of the period signal. Therefore, the data pin must have an open-drain or tristate interface. Note 1: When power is turned on, some internal circuits have undefined states. To set the internal circuit state, execute a dummy data transfer before performing regular data transfer. Note 2: Times t1 to t8 have the following values: t1 > = 1.0 µs t2 > = 1.0 µs t3 > = 0.3 µs t4 > = 0.3 µs t5 > = 0.3 µs t6 > = 1.0 µs t7 > = 1.0 µs t8 > = 0.3 µs Note 3: Asterisks represent numbers taken from addresses, as in D*H. 7 2006-07-14 TC9256, 57APG/AFG Crystal Oscillator Pins (XT, XT ) As Figure 2 shows, the clock required for internal operation is produced by connecting a crystal oscillator between capacitors. Use the crystal oscillator selection bit to select an oscillating frequency of 3.6 MHz, 4.5 MHz, 7.2 MHz or 10.8 MHz to match that of the crystal oscillator being used. C = 30 pF typ. Figure 2 Note: 3.6 MHz (OSC1 = “0” and OSC2 = “0”) is set when power is turned on. The crystal is not oscillating at this time because the system is in standby mode. 8 2006-07-14 TC9256, 57APG/AFG Reference Counter (Reference Frequency Divider) The reference counter section consists of a crystal oscillator and a counter. A crystal oscillator frequency of 3.6 MHz, 4.5 MHz, 7.2 MHz or 10.8 MHz can be selected. A maximum of 15 reference frequencies can be generated. 1. Setting Reference Frequency The reference frequency is set using bits R0 to R3. Note 1: Reference frequencies marked with an asterisk “*” can only be generated with a 4.5 MHz crystal oscillator. Note 2: (*1) Standby mode Standby mode occurs when bits R0, R1, R2 and R3 are all set to “1”. In standby mode, the programmable counter stops, and FM, AM and IFIN (when IFIN is selected) are set to “amp off” state (pins at “L” level). This saves current consumption when the radio is turned off. The DO pins become high impedance during standby mode. During standby mode, the I/O ports (I/O-5 to I/O-9) and output ports (OT1 to OT4) can be controlled and the crystal oscillator can be turned on and off. Note 3: The system is set to standby mode when power is turned on. At this time, the crystal oscillator is not oscillating and the I/O ports are set to input mode. 9 2006-07-14 TC9256, 57APG/AFG Programmable Counter The programmable counter section consists of a 1/2 prescaler, a two-modulus prescaler and a 4 bit + 12 bit programmable binary counter. 1. Setting of Programmable Counter 16 bits of divisor data and 2 bits indicating the dividing mode are set in the programmable counter. (1) Setting dividing mode The FM and MODE bits are used to select the input pin and the dividing mode (pulse-swallow mode or direct dividing mode). There are fourtypes of mode, as shown in the table below. Select one based on the frequency band being used. (2) Setting divisor The divisor for the programmable counter is set as binary data in bits P0 to P15. z Pulse-swallow mode (16 bits) Divisor setting range (pulse-swallow mode): n = 210H to FFFFH (528 to 65535) Note: z In the 1/2 + pulse-swallow mode, the actual divisor is twice the programmed value. Direct dividing mode (12 bits) Divisor setting range (direct dividing mode): n = 10H to FFFH (16 to 4095) With the direct dividing mode, data P0 to P3 are don’t-care and bit P4 is the LSB. 10 2006-07-14 TC9256, 57APG/AFG 2. Prescaler and Programmable Counter Circuit Configuration (1) Pulse-swallow mode circuit configuration Figure 3 This circuit consists of a two-modulus prescaler, a 4-bit swallow counter and a 12-bit programmable counter. During FMIN (FMH mode), a 1/2 prescaler is added to the preceding step. (2) Circuit configuration for the direct dividing method Figure 4 In the direct dividing mode, the prescaler section is bypassed and the 12-bit programmable counter is used. Note: Both FMIN and AMIN have built-in amps. Connecting a capacitor permits low-amplitude operation. 11 2006-07-14 TC9256, 57APG/AFG General-Purpose Counter The general-purpose counter is a 20-bit counter. It has such uses as counting AM/FM band intermediate frequencies (IF) and detecting auto-stop signals during auto-search tuning. It also features a cycle measurement function for such uses as measuring low-frequency pilot signal cycles. The TC9256APG and TC9256AFG do not have the cycle measurement function (SCIN mode). General-purpose counter pins can also be used as I/O ports. 1. General-Purpose Counter Control Bits (1) Bits G0 and G1 ......................... Used for selecting the general-purpose counter gate time. (2) Bits SC, IF1 and IF2................. I/O port and general-purpose counter switching bits. The functions of the following pins are switched by data. Note 1: Pin names in parentheses “( )” apply to the TC9256APG and TC9256AFG. Note 2: Bits marked with “(*1)” cannot be set on the TC9256APG and TC9256AFG. 12 2006-07-14 TC9256, 57APG/AFG (3) Bits M7, M8 and M9 ................. M7 (*1) sets the state for pin I/O-7/SCIN; M8 (M5) sets the state for pin I/O-8/IFIN1; M9 (M6), for pin I/O-9/IFIN2. These operations are valid when bits SC, IF1 and IF2 are all set to 1. Note1: Bits marked with an asterisk “(*)” are don’t-care. Note2: Bit names in parentheses “( Note3: Bits marked with (*1) cannot be set on the TC9256APG and TC9256AFG. )” apply to the TC9256APG and TC9256AFG. (4) Bits f0 to f19.............................. The general-purpose counter results can be read in binary from bits f0 to f19 of the output register (D1H). (5) OVER and BUSY bits............... Detect the operating state of the general-purpose counter. Note: (6) When using the general-purpose counter, confirm that the BUSY bit is “0” (counting is ended) and the OVER bit is “0” (general-purpose counter data is normal) before referring to the contents of the general-purpose counter result bits (f0 to f19). START bit ................................. When the data is set to “1”, the general-purpose counter is reset; then counting start. 13 2006-07-14 TC9256, 57APG/AFG 2. General-Purpose Counter Circuit Configuration The general-purpose counter section consists of input amps, a gate time control circuit and a 20-bit binary counter. Figure 5 3. General-Purpose Counter Measurement Timing Frequency Measurement Timing Chart Cycle Measurement Timing Chart 0 < T1 < = 0.25 (µs), 0 < T2 < = 1 (ms) Figure 6 Note1: IFIN1 and IFIN2 input have built-in amps. Note2: SCIN is configured for CMOS input; therefore input signals should be logic level. Connecting a capacitor permits low-amplitude operation. 14 2006-07-14 TC9256, 57APG/AFG General-Purpose I/O Ports These LSIs feature general-purpose output and I/O ports that are controlled through the serial ports. Input/Output Form Output ports I/O ports TC9256APG, TC9256AFG TC9257APG, TC9257AFG Input/Output Configuration Dedicated: 3 ports Maximum: 4 ports (1 port for CMOS output) Dedicated: 4 ports N-channel open-drain output Maximum: 2 ports Dedicated: 1 port Maximum: 5 ports CMOS input/output 1. General-Purpose Output Ports (OT-1to OT-4) Pins OT-1to OT-4 are general-purpose dedicated output ports used for control signal output. They are configured for N-channel open-drain output and have an off withstanding voltage of 12 V. The data set in bits O1to O4 of the input register (D2H) are output in parallel from their corresponding dedicated output port pins OT-1to OT-4. The TC9256APG and TC9256AFG do not have the dedicated output port OT-4, but setting the input register (D2H) CLK (O4C) bit to “1” converts pin DO2 into an output port OT-4 (configured for CMOS output). The data set in bits O1to O4 of the input register (D2H) can also be read from the DATA pins as output register (D3H) serial data O1to O4. (1) TC9257APG and TC9257AFG (2) TC9256APG and TC9256AFG Note 1: Bit names in parentheses “( )” apply to the TC9256APG and TC9256AFG. Note 2: (*1) indicates the output state when the DO2/OT-4 pin is switched for use as an OT-4 output pin (configured for CMOS output). 15 2006-07-14 TC9256, 57APG/AFG (3) Output register ......................... The data set in bits O1 to O4 of the input register can be read as serial data O1 to O4 from the output register (D3H). 2. General-Purpose I/O Ports (I/O-5 to I/O-9) Pins I/O-5 to I/O-9 are general-purpose I/O ports used for control signal input and output. They are configured for CMOS input and output. These I/O ports are set for input or output using bits C5, C6 and M7 to M9 of the input register (D2H). Setting bits C5, C6 and M7 to M9 to “0” sets these ports for input. Data input in parallel from I/O-5to I/O-9 are latched in the internal register at the ninth falling edge of the serial clock signal. The data can then be read as serial data I5 to I9 from the DATA pins. Setting bits C5, C6 and M7 to M9 to “1” sets these ports for output. Data set in bits O5 to O9 of the input register (D2H) is output in parallel from their corresponding general-purpose I/O port pins I/O-5 to I/O-9. These operations are valid when bits SC, IF1, IF2 and CLK are all set to “0”. (1) TC9257APG and TC9257AFG • Setting data for output ports Note1: On TC9257APG and TC9257AFG, pins I/O-7to I/O-9 also serve as general-purpose counter input pins. Therefore, bits SC, IF1 and IF2 of the input register (D2H) must be set to “0” when pins I/O-7to I/O-9 are used for I/O ports. Since pin I/O-5 also serves as the CLK pin, the CLK bit of the input register (D2H) must be set to “0” when pin I/O-5 is used as an I/O port. Note2: Bit names in parentheses “( Note3: Bits marked with (*1) cannot be set on the TC9256APG and TC9256AFG. )” apply to the TC9256APG and TC9256AFG. 16 2006-07-14 TC9256, 57APG/AFG (2) TC9256APG and TC9256AFG • (3) Setting data for output ports Output register ......................... Data set in bits C5, C6 and M7to M9 of the input register (D2H) can be read as serial data C5, C6 and M7to M9 from the output register (D3H). Data input in parallel from pins I/O-5 to I/O-9 can be read as serial data I5 to I9 from the output register (D3H). 17 2006-07-14 TC9256, 57APG/AFG Note1: Bit names in parentheses “( )” apply to the TC9256APG and TC9256AFG. Note2: Bits marked with (*1) cannot be set on the TC9256APG and TC9256AFG. Data is “0” for bits marked with (*2) on the TC9256APG and TC9256AFG. Note3: When pins I/O-5 to I/O-9 are used for output, the data in I5~I9 of the output register (D3H) is undefined. Note4: When power is turned on, input register (D2H) I/O port control bits C5, C6 and M7 to M9 and output data bits O5 to O9 are set to “0”. (General-purpose I/O ports are set as input ports. Pins used both as general-purpose I/O ports and general-purpose counter input are set for I/O port input. The output state of general-purpose output ports is set to high impedance (N-channel open drain output = off). Note5: On TC9256APG and TC9256AFG, pins I/O-5 and I/O-6 also serve as general-purpose counter input pins. Therefore, bits IF1 and IF2 of input register 2 must be set to “0” when these pins are used as I/O ports. A typical example of data setting for general-purpose counter and I/O port use is shown below. • TC9257APG and TC9257AFG As shown above, the pins can be switched as required to enable use as an I/O port or general-purpose counter. 18 2006-07-14 TC9256, 57APG/AFG Phase Comparator The phase comparator outputs the phase error after comparing the phase difference of the reference frequency signal supplied by the reference counter and the divided output from the programmable counter. The frequencies and phase differences of these two signals are then equalized by passing them through low-pass filters. These signals then control the VCOs. The filter constants can be customized for FM and AM bands since the signals are output in parallel from the phase comparator then pass through the two tristate buffer pins, DO1 and DO2. Figure 7 Figure 8 DO Output Timing Chart Figure 9 Typical Active Low-Pass Filter Circuit The figures above show the DO output timing chart and a typical active low-pass filter circuit featuring a Darlington connection between the FET and transistor. The filter circuit shown above is just one example. Actual circuits should be designed based on the band composition and the properties desired from the system. Note: On the TC9256APG and TC9256AFG, pin DO2 can be switched for use as pin OT-4. 19 2006-07-14 TC9256, 57APG/AFG Lock Detection Bits The lock detection bits detect locked states in the PLL system. These systems have an unlock detection bit (unlock bit), which is used to detect, using the reference frequency cycle, the phase difference between the reference frequency and the divided output of the programmable counter. These systems also have phase error detection bits (bits PE1to PE3), which are capable of more precise detection (±0.55 µs to ±7.15 µs). 1. Unlock Detection Bit (UNLOCK) This bit detects, using the reference frequency cycle, the phase difference between the reference frequency and the divided output of the programmable counter. When there is no lock, that is, when the reference frequency and the divided output of the programmable counter are not the same, unlock F/F is set. Unlock F/F is reset every time the input register (D2H) unlock reset bit (RESET) is set to “1”. After unlock F/F has been reset in this way, locked state can be detected by checking the unlock detection bit (UNLOCK) of the output register (D3H). After unlock F/F has been reset, the unlock detection bit must be checked after a time interval exceeding the reference frequency cycle. This is because the reference frequency cycle inputs the lock detection strobe to unlock F/F. If the time interval is short, the correct locked state cannot be detected. Therefore, the output register (D3H) has a lock enable bit (ENABLE). This bit is reset every time the input register (D2H) reset bit is set to “1”, and set to “1” through the lock detection timing. That is, the locked state is correctly detected when the lock enable bit (ENABLE) is “1”. Figure 10 20 2006-07-14 TC9256, 57APG/AFG Note: The asterisk “(*)” indicates an error state of over 180° phase difference relative to the reference frequency. 2. Phase Error Detection Bits (PE1to PE3) The unlock bit detects, using the reference frequency cycle, the phase difference between the reference frequency and the divided output of the programmable counter. The phase error detection bits (bits PE1to PE3) are capable of precise phase error detection of ±0.55 to ±7.15 µs using the reference frequency cycle. (If the UNLOCK bit is set to “1” and the phase difference relative to the reference frequency is over 180°, bits PE1 to PE3 cannot correctly detect the phase error. Therefore, bits PE1to PE3 are normally used when the UNLOCK bit is set to “0”.) Bits PE1to PE3 detects phase error normally when the phase difference is −180°to 180° relative to the reference frequency cycle. The phase error data can be read from the output register (D3H) as serial data PE1 to PE3. 21 2006-07-14 TC9256, 57APG/AFG The following is a typical lock detection operation. It shows the operation flow from locked state to frequency change with a phase error greater than ±4.95 µs and less than ±6.05 µs. Figure 11 22 2006-07-14 TC9256, 57APG/AFG Other Control Bits 1. CLK (O4C) and C5 (XT) Bits ................... Control bits that switch the function for the I/O-5/CLK pin on the TC9257APG and TC9257AFG, and the OT-4/DO2 pin on the TC9256APG and TC9256AFG. (1) On the TC9257APG and TC9257AFG, the CLK bit controls switching of the I/O-5 pin and CLK pin. • When bits R0 to R3 of the input register (D0H) are all set to “1” (standby mode) • When one of bits R0 to R3 of the input register (D0H) is set to “0” (not standby mode) Note1: The system clock output marked with an asterisk “(*)” refers to output of the crystal oscillator frequencies listed below. Crystal Oscillator (MHz) System Clock (kHz) Duty (%) 10.8 7.2 600 50 3.6 4.5 Note2: Bit names in parentheses “( 750 )” apply to the TC9256APG and TC9256AFG. 23 2006-07-14 TC9256, 57APG/AFG (2) On the TC9256APG and TC9256AFG, the O4C bit controls switching of the DO2 pin and OT-4 pin. • When bits R0 to R3 of the input register (D0H) are all set to “1” (standby mode) • When one of bits R0 to R3 of the input register (D0H) is set to “0” (not standby mode) 2. DOHZ Bit ................................................. Controls the DO2 pin output state. 3. TEST Bit .................................................. Data should normally be set to “0”. Note: Bit names in parentheses “( )” apply to the TC9256APG and TC9256AFG. 24 2006-07-14 TC9256, 57APG/AFG Absolute Maximum Ratings (Ta = 25°C) Characteristic Symbol Rating Unit Supply voltage VDD −0.3~6.0 V Input voltage VIN −0.3~VDD + 0.3 V VOFF 13 V Power dissipation PD 300 (200) mW Operating temperature Topr −40~85 °C Storage temperature Tstg −65~150 °C N-ch open-drain OFF withstanding voltage ( ): Flat package Electrical Characteristics (unless otherwise specified, Ta = −40 to 85°C, VDD = 4.5 to5.5 V) Symbol Test Circuit VDD1 ⎯ IDD1 ⎯ Symbol Test Circuit Crystal oscillation frequency supply voltage VDD2 ⎯ Operating power supply current IDD2 ⎯ Operating power supply current IDD3 ⎯ Symbol Test Circuit Crystal oscillation frequency fXT ⎯ FMIN (FMH, FML) fFM FMIN (FML) AMIN (HF) Characteristic Min Typ Max Unit 4.5 5.0 5.5 V VDD = 5.0 V, XT = 10.8 MHz, FMIN = 150 MHz ⎯ 7 15 mA Test Condition Min Typ Max Unit 4.0 5.0 5.5 V VDD = 5.0 V, XT = 10.8 MHz, PLL OFF ⎯ 0.8 1.5 mA VDD = 5.0 V, XT stop, PLL OFF ⎯ 120 240 µA Min Typ Max Unit Connect crystal resonator to XT- XT pin 3.6 ~ 10.8 MHz ⎯ FMH, FML mode, VIN = 0.2 Vp-p 30 ~ 130 MHz fFML ⎯ FML mode, VIN = 0.3 Vp-p 30 ~ 150 MHz fHF ⎯ HF mode, VIN = 0.2 Vp-p 1 ~ 40 MHz AMIN (LF) fLF ⎯ LF mode, VIN = 0.2 Vp-p 0.5 ~ 20 MHz IFIN1, IFIN2 fIF ⎯ VIN = 0.2 Vp-p 0.1 ~ 15 MHz ⎯ VIH = 0.7 VDD, VIL = 0.3 VDD, Square wave input ⎯ ~ 100 kHz Operating power supply voltage Operating power supply current Test Condition PLL operation (normaloperation) Standby mode Characteristic PLL OFF (operating crystal oscillation) Operating frequency range Characteristic SCIN fSC Test Condition 25 2006-07-14 TC9256, 57APG/AFG Operating input amplitude range Symbol Test Circuit FMIN (FMH, FML) VFM ⎯ FMIN (FML) VFML AMIN (HF) Characteristic Test Condition Min Typ Max Unit FMH, FML mode, fIN = 30 to 130 MHz 0.2 ~ VDD − 0.5 Vp-p ⎯ FML mode, fIN = 30 to 150 MHz 0.3 ~ VDD − 0.5 Vp-p VHF ⎯ HF mode, fIN = 1 to 40 MHz 0.2 ~ VDD − 0.5 Vp-p AMIN (LF) VLF ⎯ LF mode, fIN = 0.5 to 20 MHz 0.2 ~ VDD − 0.5 Vp-p IFIN1, IFIN2 VIF ⎯ fIN = 0.1 to 15 MHz 0.2 ~ VDD − 0.5 Vp-p Symbol Test Circuit Min Typ Max Unit IOL1 ⎯ VOL = 1.0 V 5.0 10.0 ⎯ mA IOFF ⎯ VOFF = 12 V ⎯ ⎯ 2.0 µA Symbol Test Circuit Test Condition Min Typ Max Unit ⎯ 0.7 VDD ~ VDD ⎯ 0 ~ 0.3 VDD VIH = 5 V ⎯ ⎯ 2.0 VIL = 0 V ⎯ ⎯ −2.0 VOH = 4.0 V (except SCIN) −2.0 −4.0 ⎯ VOL = 1.0 V (except SCIN) 2.0 4.0 ⎯ Test Condition Min Typ Max ⎯ 0.8 VDD ~ VDD 0 ~ 0.2 VDD VIH = 5 V ⎯ ⎯ 2.0 VIL = 0 V ⎯ ⎯ −2.0 VOH = 4.0 V (DATA) −1.0 −3.0 ⎯ VOL = 1.0 V (DATA) 1.0 3.0 ⎯ OT1 to OT4 N-ch open drain Characteristic Output current “L” level OFF-leak current Test Condition I/O-5 to I/O-9, SCIN Characteristic “H” level VIH1 ⎯ Input voltage Input current “L” level VIL1 “H” level IIH “L” level IIL “H” level IOH4 “L” level IOL4 Output current ⎯ ⎯ V µA mA PERIOD, CLOCK, DATA Characteristic “H” level Symbol VIH2 ⎯ Input voltage “L” level VIL2 “H” level IIH “L” level IIL “H” level IOH5 “L” level IOL5 Input current Output current Test Circuit ⎯ ⎯ ⎯ 26 Unit V µA mA 2006-07-14 TC9256, 57APG/AFG DO1, DO2 Characteristic Input current Symbol “H” level IOH3 “L” level IOL3 Tristate lead current Test Circuit ⎯ ITL ⎯ Symbol Test Circuit Test Condition Min Typ Max Unit VOH = 4.0 V −2.0 −4.0 ⎯ VOL = 1.0 V 2.0 4.0 ⎯ VTLH = 5 V, VTLL = 0 V ⎯ ⎯ ±1.0 µA Min Typ Max Unit VOH = 4.0 V −0.1 −0.3 ⎯ VOL = 1.0 V 0.1 0.3 ⎯ Min Typ Max mA XT Characteristic Output current “H” level IOH2 “L” level IOL2 ⎯ Test Condition mA Input feedback resistance Characteristic Input feedback resistance Symbol Rf1 Rf2 Test Circuit ⎯ Test Condition FMIN, AMIN, IFIN (Ta = 25°C) 350 700 1400 XT- XT (Ta = 25°C) 500 1000 4000 27 Unit kΩ 2006-07-14 TC9256, 57APG/AFG 28 2006-07-14 TC9256, 57APG/AFG Application Circuit (Sample circuit containing TC9257APG and TC9257AFG) 29 2006-07-14 TC9256, 57APG/AFG Package Dimensions Weight: 1.0 g (typ.) (Note): Palladium plate 30 2006-07-14 TC9256, 57APG/AFG Package Dimensions Weight: 1.24 g (typ.) (Note): Palladium plate 31 2006-07-14 TC9256, 57APG/AFG Package Dimensions P-SOP16-300-1.27A Unit : mm Weight: 0.16 g (typ.) (Note): Palladium plate 32 2006-07-14 TC9256, 57APG/AFG Package Dimensions P-SOP20-300-1.27A Unit : mm Weight: 0.48 g (typ.) (Note): Palladium plate 33 2006-07-14 TC9256, 57APG/AFG RESTRICTIONS ON PRODUCT USE 060116EBA • The information contained herein is subject to change without notice. 021023_D • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. 021023_A • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. 021023_B • The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C • The products described in this document are subject to the foreign exchange and foreign trade laws. 021023_E About solderability, following conditions were confirmed • Solderability (1) Use of Sn-37Pb solder Bath · solder bath temperature = 230°C · dipping time = 5 seconds · the number of times = once · use of R-type flux (2) Use of Sn-3.0Ag-0.5Cu solder Bath · solder bath temperature = 245°C · dipping time = 5 seconds · the number of times = once · use of R-type flux 34 2006-07-14