TEMIC TSC87C52

TSC87C52
CMOS 0 to 33 MHz Programmable 8–bit Microcontroller
Description
TEMIC’s TSC87C52 is high performance CMOS
EPROM version of the 80C52 CMOS single chip 8 bit
microcontroller.
The fully static design of the TSC87C52 allows to
reduce system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.
The TSC87C52 retains all the features of the 80C52 with
some enhancement: 8 K bytes of internal code memory
(EPROM); 256 bytes of internal data memory (RAM);
32 I/O lines; three 16 bit timers one with count–down
and clock–out capability; a 6-source, 2-level interrupt
structure; a full duplex serial port with framing error
detection; a power off flag; and an on-chip oscillator.
The TSC87C52 has 2 software-selectable modes of
reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the RAM, the timers, the serial port and the interrupt
system continue to function. In the power down mode
the RAM is saved and all other functions are inoperative.
The TSC87C52 is manufactured using non volatile
SCMOS process which allows it to run up to:
33 MHz with VCC = 5 V ± 10%.
16 MHz with 2.7 V < VCC < 5.5 V.
8 Kbytes of EPROM
Fully static design
0.8µ SCMOS non volatile process
Features
Improved Quick Pulse programming algorithm
Secret ROM by encryption
256 bytes of RAM
ONCE Mode
64 Kbytes program memory space
Enhanced Hooks system for emulation purpose
64 Kbytes data memory space
Available temperature ranges:
32 programmable I/O lines
Three 16 bit timer/counters including enhanced
timer 2
Programmable serial port with framing error
detection
Power control modes
Two–level interrupt priority
commercial
industrial
Available packages:
PDIP40 (OTP)
PLCC44 (OTP)
PQFP44 (OTP)
CQPJ44 (UV erasable)
CERDIP40 (UV erasable)
MATRA MHS
Rev. C – 10 Sept 1997
1
Preliminary
TSC87C52
Block Diagram
EPROM
Figure 1 TSC87C52 Block diagram
MATRA MHS
Rev. C – 10 Sept 1997
2
Preliminary
TSC87C52
P0.2
P1.4
5
36
P0.3
39
P0.4/AD4
P0.5
P1.6
8
38
P0.5/AD5
P1.7
9
37
P0.6/AD6
RST
10
36
P0.7/AD7
P3.0/RxD
11
35
EA/VPP
Reserved
12
34
Reserved
P3.1/TxD
13
33
ALE/PROG
P3.2/INT0
P3.3/INT1
14
32
PSEN
15
31
P2.7/A15
P3.4/T0
P3.5/T1
16
30
P2.6/A14
17
29
P2.5/A13
P1.7
8
33
P0.6
RST
9
32
P0.7
10
31
EA/VPP
P3.1/TxD
11
30
ALE/PROG
P3.2/INT0
12
29
PSEN
P3.3/INT1
13
28
P2.7
P3.4/T0
14
27
P2.6
20
21
P2.0
P2.3/A11
P2.4/A12
P2.1
VSS
P2.2/A10
22
P2.1/A9
19
P2.0/A8
P2.2
XTAL1
VSS
Reserved
P2.3
23
XTAL1
24
18
XTAL2
17
XTAL2
P1.4
P3.7/RD
18 19 20 21 22 23 24 25 26 27 28
P3.7/RD
P2.4
P3.6/WR
P2.5
25
PLCC/CQPJ
P0.3/AD3
26
16
P0.2/AD2
15
P0.1/AD1
P3.5/T1
P3.6/WR
P0.0/AD0
DIP
VCC
P3.0/RxD
VSS1
34
P1.5
P1.0/T2
7
P0.4
P1.1/T2EX
35
P1.2
P1.6
6
6 5 4 3 2 1 44 43 42 41 40
7
P1.3
P1.5
P0.3/AD3
37
P0.2/AD2
4
P0.1/AD1
P0.1
P1.3
P0.0/AD0
38
VCC
3
VSS1
P0.0
P1.2
P1.0/T2
VCC
39
P1.1/T2EX
40
2
P1.2
1
P1.4
P1.0/T2
P1.1/T2EX
P1.3
Pin Configuration
44 43 42 41 40 39 38 37 36 35 34
P1.5
1
33
P0.4/AD4
P1.6
2
32
P0.5/AD5
P1.7
3
31
P0.6/AD6
RST
4
30
P0.7/AD7
P3.0/RxD
5
29
EA/VPP
Reserved
6
28
Reserved
P3.1/TxD
7
27
ALE/PROG
P3.2/INT0
P3.3/INT1
8
26
PSEN
9
25
P2.7/A15
10
24
P2.6/A14
11
23
P2.5/A13
P3.4/T0
P3.5/T1
Flat Pack
P2.3/A11
P2.4/A12
P2.2/A10
P2.1/A9
P2.0/A8
VSS
Reserved
XTAL1
XTAL2
P3.7/RD
P3.6/WR
12 13 14 15 16 17 18 19 20 21 22
Figure 2 TSC87C52 pin configuration
Do not connect Reserved pins.
MATRA MHS
Rev. C – 10 Sept 1997
3
Preliminary
TSC87C52
Pin Description
VSS
Circuit ground potential.
VSS1
Secondary ground (not on DIP). Provided to reduce ground bounce and improve power supply by–passing.
Note: This pin is not a substitute for the VSS pin. Connection is not necessary for proper operation.
VCC
Supply voltage during normal, Idle, and Power Down operation.
Port 0
Port 0 is an 8 bit open drain bi-directional I/O port. Port 0 pins that have 1’s written to them float, and in that state can
be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and data bus during accesses to external Program and Data Memory.
In this application it uses strong internal pullups when emitting 1’s.
Port 0 can sink eight LS TTL inputs.
Port 0 is used as data bus during EPROM programming and program verification.
Port 1
Port 1 is an 8 bit bi-directional I/O port with internal pullups. Port 1 pins that have 1’s written to them are pulled high
by the internal pullups, and in that state can be used as inputs. As inputs, Port 1 pins that are externally being pulled
low will source current (IIL, in the DC parameters section) because of the internal pullups.
Port 1 can sink/ source three LS TTL inputs. It can drive CMOS inputs without external pullups.
Port1 also serves the functions of the following special features of the TSC87C52 as listed below:
Port Pin
P1.0
P1.1
Alternate Function
T2 (External Count input to Timer/Counter 2), Clock–Out
T2EX (Timer/Counter 2 Capture/Reload Trigger and direction Control)
Port 1 receives the low–order address byte during EPROM programming and program verification.
Port 2
Port 2 is an 8 bit bi-directional I/O port with internal pullups. Port 2 pins that have 1’s written to them are pulled high
by the internal pullups, and in that state can be used as inputs. As inputs, Port 2 pins that are externally being pulled
low will source current (IIL, in the DC parameters section) because of the internal pullups.
Port 2 emits the high-order address byte during fetches from external Program Memory and during accesses to external
Data Memory that use 16 bit addresses (MOVX @DPTR). In this application, it uses strong internal pullups when
emitting 1’s. During accesses to external Data Memory that use 8 bit addresses (MOVX @Ri), Port 2 emits the contents
of the P2 Special Function Register.
Port 2 can sink/source three LS TTL inputs. It can drive CMOS inputs without external pullups.
Some Port 2 pins receive the high–order address bits and control signals during EPROM programming and program
verification.
Port 3
Port 3 is an 8 bit bi-directional I/O port with internal pullups. Port 3 pins that have 1’s written to them are pulled high
by the internal pullups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally being pulled
low will source current (IIL, in the DC parameters section) because of the pullups.
MATRA MHS
Rev. C – 10 Sept 1997
4
Preliminary
TSC87C52
Port 3 also serves the functions of various special features of the TEMIC’s C51 Family, as listed below:
Port Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Alternate Function
RxD (serial input port)
TxD (serial output port)
INT0 (external interrupt 0)
INT1 (external interrupt 1)
T0 (Timer 0 external input)
T1 (Timer 1 external input)
WR (external Data Memory write strobe)
RD (external Data Memory read strobe)
Port 3 can sink/source three LS TTL inputs. It can drive CMOS inputs without external pullups.
Some Port 3 pins receive control signals during EPROM programming and program verification.
RST
A high level on this pin for two machine cycles while the oscillator is running resets the device. An internal pull-down
resistor permits Power-On reset using only a capacitor connected to VCC. The port pins will be driven to their reset
condition when a minimum VIH1 voltage is applied whether the oscillator is started or not (asynchronous reset).
ALE/PROG
Address Latch Enable output for latching the low byte of the address during accesses to external memory. ALE is
activated as though for this purpose at a constant rate of 1/6 the oscillator frequency except during an external data
memory access at which time one ALE pulse is skipped.
ALE can sink/source 8 LS TTL inputs. It can drive CMOS inputs without external pullup.
If desired, to reduce EMI, ALE operation can be disabled by setting bit 0 of SFR location 8Eh (MSCON). With this
bit set, the pin is weakly pulled high. However, ALE remains active during MOVX, MOVC instructions and external
fetches. Setting the ALE disable bit has no effect if the microcontroller is in external execution mode (EA=0).
Throughout the remainder of this datasheet, ALE will refer to the signal coming out of the ALE/PROG pin, and the
pin will be referred to as the ALE/PROG pin.
PSEN
Program Store Enable output is the read strobe to external Program Memory. PSEN is activated twice each machine
cycle during fetches from external Program Memory. (However, when executing out of external Program Memory, two
activations of PSEN are skipped during each access to external Data Memory). PSEN is not activated during fetches
from internal Program Memory. PSEN can sink/source 8 LS TTL inputs. It can drive CMOS inputs without an external
pullup.
EA/VPP
External Access enable. EA must be strapped to VSS in order to enable the device to fetch code from external Program
Memory locations 0000h to FFFFh. Note however, that if any of the Security bits are programmed, EA will be internally
latched on reset.
EA should be strapped to VCC for internal program execution.
This pin also receives the programming supply voltage (VPP) during EPROM programming.
XTAL1
Input to the inverting amplifier that forms the oscillator. Receives the external oscillator signal when an external
oscillator is used.
XTAL2
Output from the inverting amplifier that forms the oscillator. This pin should be floated when an external oscillator
is used.
MATRA MHS
Rev. C – 10 Sept 1997
5
Preliminary
TSC87C52
New and Enhanced Features
In comparison to the original 80C52, the TSC87C52 implements some new and enhanced features. The new features
are the Power Off Flag, the ONCE mode and the ALE disabling. The enhanced features are located in the UART and
the Timer 2.
Power Off Flag
The Power Off Flag allows the user to distinguish between a ‘cold start’ reset and a ‘warm start’ reset.
A cold start reset is one that is coincident with VCC being turned on to the device after it was turned off. A warm start
reset occurs while VCC is still applied to the device and could be generated for example by an exit from Power Down.
The Power Off Flag (POF) is located in PCON at bit location 4 (see Table 1). POF is set by hardware when VCC rises
from 0 to its nominal voltage. The POF can be set or cleared by software allowing the user to determine the type of
reset.
Table 1 PCON – Power Control Register (87h)
7
6
5
4
3
2
1
0
SMOD1
SMOD0
–
POF
GF1
GF0
PD
IDL
Symbol
Description
SMOD1
Serial Port Mode bit 1, new name of SMOD bit
Set to select double baud rate in mode 1,2 or 3.
SMOD0
Serial Port Mode bit 0
Set to to select FE bit in SCON.
Clear to select SM0 bit in SCON.
–
Reserved
Do not write 1 in this bit.
POF
Power Off Flag
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software.
Clear by software to recognize next reset type.
GF1
General purpose Flag
Set by software for general purpose usage.
Clear by software for general purpose usage.
GF0
General purpose Flag
Set by software for general purpose usage.
Clear by software for general purpose usage.
PD
Power Down mode bit
Set to enter power down mode.
Clear by hardware when reset occurs.
IDL
Idle mode bit
Set to enter idle mode.
Clear by hardware when interrupt or reset occur.
The reset value of PCON is 00XX 0000b.
ONCE Mode
The ONCE mode facilitates testing and debugging of systems using TSC87C52 without the TSC87C52 having to be
removed from the circuit. The ONCE mode is invoked by driving certain pins of the TSC87C52, the following sequence
must be exercised.
Pull ALE low while the device is in reset (RST high) and PSEN is high.
Hold ALE low as RST is deactivated.
MATRA MHS
Rev. C – 10 Sept 1997
6
Preliminary
TSC87C52
While the TSC87C52 is in ONCE mode, an emulator or test CPU can be used to drive the circuit. Table 2 shows the
status of the port pins during ONCE mode.
Normal operation is restored when normal reset is applied.
Table 2 External pin status during ONCE mode
ALE
PSEN
Port 0
Port 1
Port 2
Port 3
XTAL1/2
Weak pull–up
Weak pull–up
Float
Weak pull–up
Weak pull–up
Weak pull–up
Active
ALE Disabling
The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data
memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to reduce EMI, ALE
signal should be disabled by setting AO bit.
The AO bit is located in MSCON at bit location 0 (see Table 3). As soon as AO is set, ALE is no longer output but
remains active during MOVX and MOVC instructions and external fetches. During ALE disabling, ALE pin is weakly
pulled high.
Table 3 MSCON – Miscellaneous Control Register (8Eh)
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
AO
Symbol
–
AO
Description
Reserved
Do not write 1 in these bits.
ALE Output bit
Set to disable ALE operation during internal fetches.
Clear to restore ALE operation during internal fetches.
The reset value of MSCON is XXXX XXX0b.
UART
The UART in the TSC87C52 operates identically to the UART in the 80C51 but includes the following enhancement.
For a complete understanding of the TSC87C52 UART please refer to the description in the 80C51 Hardware
Description Guide.
Framing Error Detection
Framing error detection allows the serial port to check for missing stop bits in the communication in mode 1, 2 or 3.
A missing stop bit can be caused for example by noise on the serial lines or transmission by two CPUs simultaneously.
If a stop bit is missing a Framing Error bit (FE) is set. The FE bit can be checked in software after each reception to
detect communication errors. Once set, the FE bit must be cleared in software. A valid stop bit will not clear FE.
The FE bit is located in SCON at bit location 7. It shares the same bit location as SM0 (see Table 4). The new control
bit SMOD0 in PCON (see Table 1) determines whether the SM0 or FE bit is accessed (see Figure 3), so whether the
framing error detection is enabled or not. If SMOD0 is set then SCON.7 functions as FE, if SMOD0 is cleared then
SCON.7 functions as SM0. Once set, the FE bit must be cleared by software. A valid stop bit will not clear FE. When
UART is in mode 1 (8–bit mode), RI flag is set during stop bit whether or not framing error is enabled (see Figure 4).
MATRA MHS
Rev. C – 10 Sept 1997
7
Preliminary
TSC87C52
When in mode 2 and 3 (9–bit mode), RI flag is set during stop bit if framing error is enabled or during ninth bit if not
(see Figure 5).
SM0/FE SM1
SM2
REN
TB8
RB8
TI
RI
Set FE bit if stop bit is 0 (framing error)
SM0 to UART mode control
SMOD1 SMOD0
–
POF
GF1
GF0
PD
IDL
To UART framing error control
Figure 3 Framing error block diagram
RXD
D0
D1
D2
Start
bit
D3
D4
D5
D6
D7
Data byte
Stop
bit
RI
SMOD0=X
FE
SMOD0=1
Figure 4 Enhanced UART timing diagram in mode 1
RXD
D0
D1
D2
Start
bit
D3
D4
D5
D6
D7
Data byte
D8
Ninth
bit
Stop
bit
RI
SMOD0=0
RI
SMOD0=1
FE
SMOD0=1
Figure 5 Enhanced UART timing diagram in mode 2 and 3
Table 4 SCON – Serial Control Register (98h)
7
6
5
4
3
2
1
0
SM0/FE
SM1
SM2
REN
TB8
RB8
TI
RI
Symbol
FE
Description
Framing Error bit (SMOD0 bit set)
Set by hardware when an invalid stop bit is detected.
Clear to reset the error state, not cleared by a valid stop bit.
SM0
Serial Mode bit 0 (SMOD0 bit cleared)
Used with SM1 to select serial mode.
SM1
Serial Mode bit 1
Used with SM0 to select serial mode.
SM2
Multiprocessor Communication Enable bit
Set to enable multiprocessor communication feature in mode 2 and 3.
Clear to disable multiprocessor communication feature.
MATRA MHS
Rev. C – 10 Sept 1997
8
Preliminary
TSC87C52
Symbol
Description
REN
Serial Reception Enable bit
Set to enable serial reception.
Clear to disable serial reception.
TB8
Ninth bit to transmit in mode 2 and 3
Set to transmit a logic 1 in the 9th bit.
Clear to transmit a logic 0 in the 9th bit.
RB8
Ninth bit received in mode 2 and 3
Set by hardware if 9th bit received is logic 1.
Clear by hardware if 9th bit received is logic 0.
TI
Transmit Interrupt Flag
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other
modes.
Clear to acknowledge interrupt.
RI
Receive Interrupt Flag
Set by hardware at the end of the 8th bit time in mode 0, see Figure 4 and Figure 5 in the other modes.
Clear to acknowledge interrupt.
The reset value of SCON is 0000 0000b.
Timer 2
The Timer 2 in the TSC87C52 operates identically to the Timer 2 in the 80C52 but includes the following
enhancements. For a complete understanding of the TSC87C52 Timer 2 please refer to the description in the 80C51
Hardware Description Guide.
Auto–reload (up or down counter)
Enhanced Timer 2 can now be programmed to count up or down when configured in its 16–bit auto–reload mode. This
feature is controlled by the DCEN (Down Counter Enable) bit. DCEN is located in T2MOD at bit location 0 (see
Table 5). Setting the DCEN bit enables Timer 2 to count up or down as shown in Figure 6. In this mode the T2EX pin
controls the direction of count.
A logic 1 at T2EX makes Timer 2 count up. The timer will overflow at FFFFh and set the TF2 bit. This overflow also
causes the 16–bit value in RCAP2H and RCAP2L to be reloaded into the timer registers, TH2 and TL2, respectively.
A logic 0 at T2EX makes Timer 2 count down. Now the timer underflows when TH2 and TL2 equal the values stored
in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes FFFFh to be reloaded into the timer registers.
The EXF2 bit toggles whenever Timer 2 overflows or underflows. In this operating mode, EXF2 does not flag an
interrupt.
(DOWN COUNTING RELOAD VALUE)
FFh
(8–bit)
FFh
(8–bit)
TOGGLE
EXF2
OSC
÷ 12
TL2
(8–bit)
TH2
(8–bit)
TF2
TIMER 2
INTERRUPT
T2
C/T2
TR2
COUNT DIRECTION
1= UP
0= DOWN
RCAP2L RCAP2H
(8–bit)
(8–bit)
(UP COUNTING RELOAD VALUE)
T2EX
Figure 6 Timer 2 Auto–Reload Mode Up/Down Counter
MATRA MHS
Rev. C – 10 Sept 1997
9
Preliminary
TSC87C52
Programmable Clock Output
A 50% duty cycle clock can be programmed to come out on P1.0. This pin, besides being a regular I/O pin, has two
alternate functions. It can be programmed to input external clock for Timer/Counter 2 or to output a 50% duty cycle
clock from frequency fosc/218 to frequency fosc/4 (61 Hz to 4 MHz at a 16 MHz operating frequency).
The clock–out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers
RCAP2H and RCAP2L as shown in this equation:
Clock–Out frequency=
Oscillator frequency
4 ⋅ (65536 – RCAP2H,RCAP2L)
To configure the Timer/Counter 2 as a clock generator, bit C/T2 in T2CON (bit location 1) must be cleared and bit T2OE
must be set. Bit TR2 in T2CON starts and stops the timer (see Figure 7). T2OE is located in T2MOD at bit location
1 (see Table 5).
In the clock–out mode, Timer 2 roll–overs will not generate an interrupt. This is similar to when Timer 2 is used as
a baud–rate generator. It is possible to use Timer 2 as a baud–rate generator and as clock generator simultaneously.
Note however, that the baud–rate and clock–out frequencies can not be determined independently from one another
since they both use RCAP2H and RCAP2L.
÷2
OSC
TL2
(8–bit)
TH2
(8–bit)
OVERFLOW
TR2
C/T2
RCAP2L RCAP2H
(8–bit)
(8–bit)
T2
÷2
EXEN2
T2OE
T2EX
EXF2
TIMER 2
INTERRUPT
Figure 7 Timer 2 Clock–Out Mode
Table 5 T2MOD – Timer 2 Control Register (C9h)
7
6
5
4
3
2
1
0
–
–
–
–
–
–
T2OE
DCEN
Symbol
–
Description
Reserved
Do not write 1 in these bits.
T2OE
Timer 2 Output Enable bit
Set to program P1.0/T2 as clock output.
Clear to program P1.0/T2 as clock input or I/O port.
DCEN
Decrement Enable bit
Set to enable Timer 2 as up/down counter.
Clear to disable Timer 2 as up/down counter.
The reset value of T2MOD is XXXX XX00b.
MATRA MHS
Rev. C – 10 Sept 1997
10
Preliminary
TSC87C52
EPROM
EPROM Structure
The TSC87C52 EPROM is divided in two different arrays:
the code array:
8 Kbytes.
the encryption array:
64 bytes.
In addition a third non programmable array is implemented:
the signature array:
4 bytes.
EPROM Lock System
The program Lock system, when programmed, protects the on–chip program against software piracy.
Encryption Array
Within the EPROM array are 64 bytes of encryption array that are initially unprogrammed (all 1’s). Every time a byte
is addressed during program verify, 6 address lines are used to select a byte of the encryption array. This byte is then
exclusive–NOR’ed (XNOR) with the code byte, creating an encryption verify byte. The algorithm, with the encryption
array in the unprogrammed state, will return the code in its original, unmodified form.
When using the encryption array, one important factor needs to be considered. If a byte has the value FFh, verifying
the byte will produce the encryption byte value. If a large block (>64 bytes) of code left unprogrammed, a verification
routine will display the content of the encryption array. For this reason all the unused code bytes should be programmed
with random values. This will ensure program protection.
EPROM Programming
Set–up modes
In order to program and verify the EPROM or to read the signature bytes, the TSC87C52 is placed in specific set–up
modes (see Figure 8).
Control and program signals must be held at the levels indicated in Table 6.
Definition of terms
Address Lines:
P1.0–P1.7, P2.0–P2.4 respectively for A0–A12
Data Lines:
P0.0–P0.7 for D0–D7
Control Signals:
RST, PSEN, P2.6, P2.7, P3.3, P3.6, P3.7.
Program Signals: ALE/PROG, EA/VPP.
Table 6 EPROM Set–up Modes
Mode
RST
PSEN
Program Code data
1
0
Verify Code data
1
0
Program Encryption Array
Address 0–3Fh
1
0
Read Signature Bytes
1
0
ALE/
PROG
1
1
EA/VPP
P2.6
P2.7
P3.3
P3.6
P3.7
12.75V
0
1
1
1
1
1
0
0
1
1
12.75V
0
1
0
1
1
0
0
0
0
MATRA MHS
Rev. C – 10 Sept 1997
1
11
Preliminary
TSC87C52
+5V
PROGRAM
SIGNALS*
CONTROL
SIGNALS*
4 to 6 MHz
EA/VPP
VCC
ALE/PROG
RST
PSEN
P2.6
P2.7
P3.3
P3.6
P3.7
P0.0–P0.7
D0–D7
P1.0–P1.7
A0–A7
P2.0–P2.4
A8–A12
XTAL1
VSS
GND
* See Table 6 for proper value on these inputs
Figure 8 Set–up modes configuration
Programming algorithm
The Improved Quick Pulse algorithm is based on the Quick Pulse algorithm and decreases the number of pulses applied
during byte programming from 25 to 5.
To program the TSC87C52 the following sequence must be exercised:
Step 1: Input the valid address on the address lines.
Step 2: Input the appropriate data on the data lines.
Step 3: Activate the combination of control signals.
Step 4: Raise EA/VPP from VCC to VPP (typical 12.75V).
Step 5: Pulse ALE/PROG 5 times.
Repeat step 1 through 5 changing the address and data for the entire array or until the end of the object file is reached
(see Figure 9).
Verify algorithm
Code array verify must be done after each byte or block of bytes is programmed. In either case, a complete verify of
the programmed array will ensure reliable programming of the TSC87C52.
To verify the TSC87C52 code the following sequence must be exercised :
Step 1: Activate the combination of program signals.
Step 2: Input the valid address on the address lines.
Step 3: Input the appropriate data on the data lines.
Step 4: Activate the combination of control signals.
Repeat step 2 through 4 changing the address and data for the entire array (see Figure 9).
The encryption array cannot be directly verified. Verification of the encryption array is done by observing that the code
array is well encrypted.
MATRA MHS
Rev. C – 10 Sept 1997
12
Preliminary
TSC87C52
Programming Cycle
Read/Verify Cycle
A0–A12
Data In
D0–D7
Data Out
100us
ALE/PROG
EA/VPP
1
2 3
10us
4
5
12.75V
5V
0V
Control
signals
Figure 9 Programming and verification signal’s waveform
Signature bytes
The TSC87C52 has four signature bytes in location 30h, 31h, 60h and 61h. To read these bytes follow the procedure
for EPROM verify but activate the control lines provided in Table 6 for Read Signature Bytes. Table 7 shows the
content of the signature byte for the TSC87C52.
Table 7 Signature bytes content
Location
Contents
Comment
30h
58h
Customer selection byte: TEMIC
31h
58h
Family selection byte: C51
60h
ADh
TSC87C52
61h
XXh
Product revision number
EPROM Erasure (Windowed Packages Only)
Erasing the EPROM erases the code array and also the encryption array returning the parts to full functionality.
Erasure leaves all the EPROM cells in a 1’s state.
Erasure Characteristics
The recommended erasure procedure is exposure to ultraviolet light (at 2537 Å) to an integrated dose at least 15
W–sec/cm2. Exposing the EPROM to an ultraviolet lamp of 12,000 µW/cm2 rating for 30 minutes, at a distance of
about 25 mm, should be sufficient.
Erasure of the EPROM begins to occur when the chip is exposed to light with wavelength shorter than approximately
4,000 Å. Since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources over
an extended time (about 1 week in sunlight, or 3 years in room–level fluorescent lighting) could cause inadvertent
erasure. If an application subjects the device to this type of exposure, it is suggested that an opaque label be placed
over the window.
MATRA MHS
Rev. C – 10 Sept 1997
13
Preliminary
TSC87C52
Electrical Characteristics
Absolute Maximum Ratings(1)
Notice:
Ambiant Temperature Under Bias:
C = commercial . . . . . . . . . . . . . . . . . . . . 0C to 70C
I = industrial . . . . . . . . . . . . . . . . . . . . . –40C to 85C
Storage Temperature . . . . . . . . . . . –65C to + 150C
Voltage on VCC to VSS . . . . . . . . . . . . –0.5 V to + 7 V
Voltage on VPP to VSS . . . . . . . . . . . –0.5 V to + 13 V
Voltage on Any Pin to VSS . . . –0.5 V to VCC + 0.5 V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 1 W(2)
1.Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
2. This value is based on the maximum allowable die temperature and
the thermal resistance of the package.
MATRA MHS
Rev. C – 10 Sept 1997
14
Preliminary
TSC87C52
DC Parameters for Standard Voltage, commercial and industrial
temperature range
TA = 0°C to +70°C; VSS = 0V; VCC = 5V ± 10%; F = 0 to 33 MHz.
TA = –40°C to +85°C; VSS = 0V; VCC = 5V ± 10%; F = 0 to 33 MHz.
Symbol
Parameter
Min
VIL
Input Low Voltage
VIH
Input High Voltage except XTAL1, RST
VIH1
Input High Voltage, XTAL1, RST
VOL
VOL1
VOH
Output Low Voltage, ports 1, 2, 3
Typ
Max
Unit
–0.5
0.2 VCC – 0.1
V
0.2 VCC + 0.9
VCC + 0.5
V
0.7 VCC
VCC + 0.5
V
0.3
V
IOL = 100µA(4)
0.45
V
IOL = 1.6mA(4)
1.0
V
IOL = 3.5mA(4)
0.3
V
IOL = 200µA(4)
0.45
V
IOL = 3.2mA(4)
1.0
V
IOL = 7.0mA(4)
VCC – 0.3
V
IOH = –10µA
VCC – 0.7
V
IOH = –30µA
VCC – 1.5
V
IOH = –60µA
(6)
Output Low Voltage, port 0, ALE, PSEN (6)
Output High Voltage, ports 1, 2, 3
Test Conditions
VCC = 5V ± 10%
VOH1
Output High Voltage, port 0, ALE, PSEN
VCC – 0.3
V
IOH = –200µA
VCC – 0.7
V
IOH = –3.2mA
VCC – 1.5
V
IOH = –7.0mA
VCC = 5V ± 10%
RRST
RST Pulldown Resistor
50
90
(5)
200
kΩ
IIL
Logical 0 Input Current ports 1, 2 and 3
–50
µA
Vin = 0.45V
ILI
Input Leakage Current
±10
µA
0.45 < Vin < VCC
ITL
Logical 1 to 0 Transition Current, ports 1, 2, 3
–650
µA
Vin = 2.0V
CIO
Capacitance of I/O Buffer
10
pF
fc = 1MHz, TA = 25°C
IPD
Power Down Current
50
µA
VCC = 2.0V to 5.5V(3)
ICC
Power Supply Current (7)
1.8
1
mA
mA
VCC = 5.5V(1)
10
4
mA
mA
VCC = 5.5V(2)
Freq = 1 MHz
Icc op
Icc idle
Freq = 6 MHz
Icc op
Icc idle
Freq ≥ 12 MHz
Icc op = 1.25 Frecq (MHz) + 5 mA
10 (5)
(5)
[email protected]
[email protected]
Icc idle = 0.36 Freq (MHz) + 2.7 mA
mA
[email protected]
[email protected]
MATRA MHS
Rev. C – 10 Sept 1997
mA
15
Preliminary
TSC87C52
DC Parameters for Low Voltage, commercial and industrial temperature range
TA = 0°C to +70°C; VSS = 0V; VCC = 2.7V to 5V ± 10%; F = 0 to 16 MHz.
TA = –40°C to +85°C; VSS = 0V; VCC = 2.7V to 5V ± 10%; F = 0 to 16 MHz.
Symbol
Parameter
Min
VIL
Input Low Voltage
VIH
Input High Voltage except XTAL1, RST
VIH1
Input High Voltage, XTAL1, RST
Typ
Max
Unit
–0.5
0.2 VCC – 0.1
V
0.2 VCC + 0.9
VCC + 0.5
V
0.7 VCC
VCC + 0.5
V
0.45
V
IOL = 0.8mA(4)
0.45
V
IOL = 1.6mA(4)
(6)
Test Conditions
VOL
Output Low Voltage, ports 1, 2, 3
VOL1
Output Low Voltage, port 0, ALE, PSEN (6)
VOH
Output High Voltage, ports 1, 2, 3
0.9 VCC
V
IOH = –10µA
VOH1
Output High Voltage, port 0, ALE, PSEN
0.9 VCC
V
IOH = –40µA
IIL
Logical 0 Input Current ports 1, 2 and 3
–50
µA
Vin = 0.45V
ILI
Input Leakage Current
±10
µA
0.45 < Vin < VCC
ITL
Logical 1 to 0 Transition Current, ports 1, 2, 3
–650
µA
Vin = 2.0V
200
kΩ
RRST
CIO
RST Pulldown Resistor
50
90 (5)
Capacitance of I/O Buffer
IPD
Power Down Current
ICC
Power Supply Current (7)
Active Mode 16MHz
Idle Mode
16MHz
10
pF
fc = 1MHz, TA = 25°C
(5)
TBD
µA
VCC = 2.0V to 5.5V(3)
TBD (5)
TBD (5)
TBD
TBD
mA
mA
VCC = 3.3V(1)
VCC = 3.3V(2)
TBD
Notes for DC Electrical Characteristics
1. Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 13), VIL = VSS + 0.5V,
VIH = VCC – 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used (see NO TAG).
2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5ns, VIL = VSS + 0.5V, VIH = VCC–0.5V; XTAL2
N.C; Port 0 = VCC; EA = RST = VSS (see Figure 11).
3. Power Down ICC is measured with all output pins disconnected; EA = VSS, PORT 0 = VCC; XTAL2 NC.; RST = VSS (see NO TAG).
4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports 1 and 3. The noise is due
to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operation. In the worst
cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed 0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not necessary.
5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and 5V.
6. Under steady state (non–transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin:
10 mA
Maximum IOL per 8–bit port:
Port 0:
26 mA
Ports 1, 2 and 3:
15 mA
Maximum total IOL for all output pins:
71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.
7. For other values, please contact your sales office.
MATRA MHS
Rev. C – 10 Sept 1997
16
Preliminary
TSC87C52
VCC
VCC
ICC
VCC
ICC
VCC
VCC
P0
P0
VCC
RST
(NC)
CLOCK
SIGNAL
VCC
EA
RST
XTAL2
EA
XTAL2
(NC)
XTAL1
XTAL1
VSS
VSS
All other pins are disconnected.
Figure 10 ICC Test Condition, Active Mode
All other pins are disconnected.
Figure 12 ICC Test Condition, Power Down Mode
VCC
ICC
VCC
VCC
VCC–0.5V
0.7VCC
0.2VCC–0.1
P0
0.45V
RST
TCHCL
EA
TCLCH
TCLCH = TCHCL = 5ns.
(NC)
CLOCK
SIGNAL
XTAL2
XTAL1
VSS
All other pins are disconnected.
Figure 11 ICC Test Condition, Idle Mode
Figure 13 Clock Signal Waveform for ICC Tests in
Active and Idle Modes
MATRA MHS
Rev. C – 10 Sept 1997
17
Preliminary
TSC87C52
AC Parameters
Explanation of the AC Symbols
Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters,
depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list
of all the characters and what they stand for.
Example:
TAVLL = Time for Address Valid to ALE Low.
TLLPL = Time for ALE Low to PSEN Low.
TA = 0 to +70C; VSS = 0V VCC = 5V±10%; 0 to 12MHz
TA = –40°C to +85°C; VSS = 0V; VCC = 5V ± 10%; F = 0 to 12MHz.
(Load Capacitance for PORT 0, ALE and PSEN = 100pf; Load Capacitance for all other outputs = 80 pF.)
External Program Memory Characteristics
0 to 12MHz
Symbol
Parameter
Min
Units
Max
TLHLL
ALE pulse width
2TCLCL – 40
ns
TAVLL
Address Valid to ALE
TCLCL – 40
ns
TLLAX
Address Hold After ALE
TCLCL – 30
ns
TLLIV
ALE to Valid Instruction In
TLLPL
ALE to PSEN
TCLCL – 30
ns
TPLPH
PSEN Pulse Width
3TCLCL – 45
ns
TPLIV
PSEN to Valid Instruction In
TPXIX
Input Instruction Hold After PSEN
TPXIZ
Input Instruction FloatAfter PSEN
TPXAV
PSEN to Address Valid
TAVIV
Address to Valid Instruction In
TPXAV
PSEN Low to Address Float
4TCLCL – 100
3TCLCL – 105
0
ns
ns
ns
TCLCL – 25
TCLCL – 8
ns
ns
5TCLCL – 105
ns
10
ns
External Program Memory Read Cycle
12 TCLCL
TLHLL
TLLIV
ALE
TLLPL
TPLPH
PSEN
TLLAX
TPLIV
TPLAZ
TAVLL
PORT 0
INSTR IN
A0–A7
TPXAV
TPXIZ
TPXIX
INSTR IN
A0–A7
INSTR IN
TAVIV
PORT 2
ADDRESS
OR SFR–P2
ADDRESS A8–A15
ADDRESS A8–A15
MATRA MHS
Rev. C – 10 Sept 1997
18
Preliminary
TSC87C52
External Data Memory Characteristics
0 to 12MHz
Symbol
Parameter
Min
Units
Max
TRLRH
RD Pulse Width
6TCLCL–100
ns
TWLWH
WR Pulse Width
6TCLCL–100
ns
TRLDV
RD to Valid Data In
TRHDX
Data Hold After RD
TRHDZ
Data Float After RD
2TCLCL–60
ns
TLLDV
ALE to Valid Data In
8TCLCL–150
ns
TAVDV
Address to Valid Data In
9TCLCL–165
ns
TLLWL
ALE to WR or RD
3TCLCL–50
3TCLCL+50
ns
TAVWL
Address to WR or RD
4TCLCL–130
ns
TQVWX
Data Valid to WR Transition
TCLCL–50
ns
TQVWH
Data set–up to WR High
7TCLCL–150
ns
TWHQX
Data Hold After WR
TCLCL–50
ns
TRLAZ
RD Low to Address Float
TWHLH
RD or WR High to ALE high
5TCLCL–165
ns
0
ns
TCLCL–40
0
ns
TCLCL+40
ns
External Data Memory Write Cycle
TWHLH
ALE
PSEN
TLLWL
TWLWH
WR
TQVWX
TLLAX
PORT 0
TQVWH
A0–A7
TWHQX
DATA OUT
TAVWL
PORT 2
ADDRESS
OR SFR–P2
ADDRESS A8–A15 OR SFR P2
MATRA MHS
Rev. C – 10 Sept 1997
19
Preliminary
TSC87C52
External Data Memory Read Cycle
TWHLH
TLLDV
ALE
PSEN
TLLWL
TRLRH
RD
TRHDZ
TAVDV
TLLAX
PORT 0
TRHDX
A0–A7
DATA IN
TRLAZ
TAVWL
PORT 2
ADDRESS
OR SFR–P2
ADDRESS A8–A15 OR SFR P2
Serial Port Timing – Shift Register Mode
0 to 12MHz
Symbol
Parameter
TXLXL
Serial port clock cycle time
TQVHX
Min
Units
Max
12TCLCL
ns
Output data set–up to clock rising edge
10TCLCL–133
ns
TXHQX
Output data hold after clock rising edge
2TCLCL–117
ns
TXHDX
Input data hold after clock rising edge
0
ns
TXHDV
Clock rising edge to input data valid
10TCLCL–133
ns
Shift Register Timing Waveforms
INSTRUCTION
0
1
2
3
4
5
6
7
8
ALE
TXLXL
CLOCK
TXHQX
TQVXH
OUTPUT DATA
0
WRITE to SBUF
TXHDV
INPUT DATA
1
VALID
2
3
4
5
6
7
TXHDX
VALID
VALID
SET TI
VALID
VALID
VALID
VALID
VALID
SET RI
CLEAR RI
MATRA MHS
Rev. C – 10 Sept 1997
20
Preliminary
TSC87C52
EPROM Programming and Verification Characteristics
TA = 21°C to 27°C; VSS = 0V; VCC = 5V ± 10%.
Symbol
Parameter
VPP
Programming Supply Voltage
IPP
Programming Supply Current
1/TCLCL
Oscillator Frquency
Min
Max
Units
12.5
13
V
75
mA
6
MHz
4
TAVGL
Address Setup to PROG Low
48 TCLCL
TGHAX
Adress Hold after PROG
48 TCLCL
TDVGL
Data Setup to PROG Low
48 TCLCL
TGHDX
Data Hold after PROG
48 TCLCL
TEHSH
(Enable) High to VPP
48 TCLCL
TSHGL
VPP Setup to PROG Low
10
µs
TGHSL
VPP Hold after PROG
10
µs
TGLGH
PROG Width
90
TAVQV
Address to Valid Data
48 TCLCL
TELQV
ENABLE Low to Data Valid
48 TCLCL
TEHQZ
Data Float after ENABLE
0
TGHGL
PROG High to PROG Low
10
µs
110
48 TCLCL
µs
EPROM Programming and Verification Waveforms
PROGRAMMING
VERIFICATION
ADDRESS
ADDRESS
P1.0–P1.7
P2.0–P2.4
TAVQV
P0
DATA OUT
DATA IN
TDVGL
TAVGL
TGHDX
TGHAX
5
Pulses
ALE/PROG
TSHGL
TGLGH
EA/VCC
VPP
VCC
TEHSH
CONTROL
SIGNALS
(ENABLE)
TGHGL
TGHSL
VCC
TELQV
MATRA MHS
Rev. C – 10 Sept 1997
TEHQZ
21
Preliminary
TSC87C52
External Clock Drive Characteristics (XTAL1)
Symbol
Parameter
Min
Max
Units
TCLCL
Oscillator Period
30
ns
TCHCX
High Time
5
ns
TCLCX
Low Time
5
ns
TCLCH
Rise Time
5
ns
TCHCL
Fall Time
5
ns
External Clock Drive Waveforms
VCC–0.5V
0.45V
0.7VCC
0.2VCC–0.1
TCHCX
TCLCX
TCHCL
TCLCH
TCLCL
AC Testing Input/Output Waveforms
VCC –0.5 V
0.2 VCC + 0.9
INPUT/OUTPUT
0.2 VCC – 0.1
0.45 V
AC inputs during testing are driven at VCC – 0.5 for a logic “1” and 0.45V for a logic “0”. Timing measurement are
made at VIH min for a logic “1” and VIL max for a logic “0”.
Float Waveforms
FLOAT
VOH – 0.1 V
VOL + 0.1 V
VLOAD
VLOAD + 0.1 V
VLOAD – 0.1 V
For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to
float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH ≥ ± 20mA.
MATRA MHS
Rev. C – 10 Sept 1997
22
Preliminary
TSC87C52
Clock Waveforms
INTERNAL
CLOCK
STATE4
STATE5
STATE6
STATE1
STATE2
STATE3
STATE4
STATE5
P1
P1
P1
P1
P1
P1
P1
P1
P2
P2
P2
P2
P2
P2
P2
P2
XTAL2
ALE
THESE SIGNALS ARE NOT ACTIVATED DURING THE
EXECUTION OF A MOVX INSTRUCTION
EXTERNAL PROGRAM MEMORY FETCH
PSEN
P0
DATA
SAMPLED
PCL OUT
DATA
SAMPLED
FLOAT
P2 (EXT)
PCL OUT
DATA
SAMPLED
FLOAT
PCL OUT
FLOAT
INDICATES ADDRESS TRANSITIONS
READ CYCLE
RD
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
P0
DPL OR Rt OUT
DATA
SAMPLED
FLOAT
P2
INDICATES DPH OR P2 SFR TO PCH TRANSITION
WRITE CYCLE
WR
P0
PCL OUT (EVEN IF PROGRAM
MEMORY IS INTERNAL)
DPL OR Rt OUT
DATA OUT
P2
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
INDICATES DPH OR P2 SFR TO PCH TRANSITION
PORT OPERATION
MOV PORT SRC
OLD DATA
NEW DATA
P0 PINS SAMPLED
P0 PINS SAMPLED
MOV DEST P0
MOV DEST PORT (P1. P2. P3)
(INCLUDES INTO. INT1. TO T1)
SERIAL PORT SHIFT CLOCK
P1, P2, P3 PINS SAMPLED
RXD SAMPLED
P1, P2, P3 PINS SAMPLED
RXD SAMPLED
TXD (MODE 0)
This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins,
however, ranges from 25 to 125ns. This propagation delay is dependent on variables such as temperature and pin
loading. Propagation also varies from output to output and component. Typically though (TA=25C fully loaded) RD
and WR propagation delays are approximately 50ns. The other signals are typically 85ns. Propagation delays are
incorporated in the AC specifications.
MATRA MHS
Rev. C – 10 Sept 1997
23
Preliminary
TSC87C52
Ordering Information
TSC
87C52
–20
C
B
R
OTP Packaging
A: PDIL 40
B: PLCC 44
C: PQFP 44 (F1)
D: PQFP 44 (F2)
E: VQFP 44 (1.4mm)
F: TQFP 44 (1mm)
G: CDIL 40 (.6)
H: LCC 44
I: CQPJ 44
–12: 12 MHz version
–16: 16 MHz version
–20: 20 MHz version
–25: 25 MHz version
–33: 33 MHz version
–L16: Low Power
(VCC: 2.7–5.5V,
Freq.: 0–16 MHz)
Part Number
87C52: Programmable ROM
EPROM–UV Erasable
J: Window CDIL 40
K: Window CQPJ 44
TEMIC Semiconductor
Microcontroller Product Line
Temperature Range
C: Commercial 0° to 70°C
I: Industrial –40° to 85°C
Conditioning
R: Tape & Reel
D: Dry Pack
B: Tape & Reel and
Dry Pack
MATRA MHS
Rev. C – 10 Sept 1997
24
Preliminary