TOSHIBA TC9328AF_04

TC9328AF
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC9328AF
Portable Audio DTS Controller (DTS-21)
The TC9328AF is a single-chip DTS microcontroller for
portable audio incorporating 230 MHz prescaller, PLL, and LCD
driver. In addition to a 20-bit IF counter, 6-bit A/D converter,
serial interface, and buzzer function, the device supports an
interrupt function, 8-bit timer/counter, and 8-bit pulse counter.
The LCD driver features built-in 1/4 duty, 1/2 bias and a 3 V
voltage doubler boosting circuit, implementing stable LCD.
The power supply voltage ranges from 0.9 to 1.8 V. Because of
its low-current consumption (CPU: 80 µA (max)), the device is
suitable for use in digital tuning systems in portable equipment
such as headphone stereos.
Weight: 0.45 g (typ.)
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
CMOS DTS microcontroller LSI with built-in 230 MHz prescaller, PLL, and LCD driver
Operating voltage: VDD = 0.9 to 1.8 V (typ.: 1.5 V)
Current dissipation:
When CPU in operation: IDD = 40 µA (typ.)
When PLL in operation: IDD = 6 mA (typ.) (VHF mode)
Operating temperature range: Ta = −10 to 60°C
Program memory (ROM): 16-bit × 8192 steps
Data memory (RAM): 4-bit × 512 words
Instruction execution time: 40 µs
Crystal oscillator frequency: 75 kHz
Stack level: 8
General-purpose IF counter: 20-bit (CMOS input supported)
A/D converter: 6-bit × 4 channel
LCD driver: 1/4 duty, 1/2 bias, 88 segments (max)
I/O port: CMOS I/O ports: 12
N-channel open drain I/O ports: 24 (max)
Output-only port: 1
Input-only ports: 5 (max)
Timer/counter: 8-bit (as timer clock: INTR1/INTR2, instruction cycle: 1 kHz selectable)
Pulse counter: 8-bit up/down counter (input via INTR2 pin)
Buzzer: Built-in four mode: 0.625 to 3 kHz (8 types), Continuous, Single-Shot,
10 Hz Intermittent, or 10 Hz Intermittent 1 Hz Interval
Package: QFP-80 (0.5 mm pitch, 1.4 mm thick)
1
2004-09-13
TC9328AF
TEST
HOLD
INTR1
INTR2 (PCTRin)
IFin1 (IN1)
IFin2 (IN2)
GND
FMin
AMin
VDD
DO2 (OT/N)
DO1 (P)
Vreg
P3-0
P3-1
P3-2
P3-3
P5-0 (ADin1)
P5-1 (ADin2)
P5-2 (ADin3)
Pin Assignment
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P5-3 (ADin4)
61
40
MUTE
P6-0
62
39
P4-3 (SCK)
P6-1
63
38
P4-2 (SO)
A/D converter (4-channel)
PLL
Interrupt input
SIO
P6-2
64
37
P4-1 (SI)
P6-3
65
36
P4-0 (BUZR) (Buzzer output)
P7-0
66
P7-1
67
P7-2
68
P7-3
69
RESET
70
XOUT
71
XIN
N-channel open drain I/O (16)
I/O ports (CMOS:12)
SVFP80
(0.5 mm pitch)
TOP-VIEW
35
P2-3 (PSC) (Prescaller PSC output)
34
P2-2
33
P2-1
32
P2-0
31
VDD
30
P1-3
72
29
P1-2
GND
73
28
P1-1
VDB
74
27
P1-0
C1
75
26
P9-3 (S22)
C2
76
25
P9-2 (S21)
VEE
77
24
P9-1 (S20)
C3
78
23
P9-0 (S19)
C4
79
22
P8-3 (S18)
VLCD
80
21
P8-2 (S17)
Oscillation circuit
Doubler circuit
N-channel open drain I/O (8)
2
COM4 (OT4)
S1 (OT5)
S2 (OT6)
S3 (OT7)
S4 (OT8)
S5 (OT9)
P8-1 (S16)
COM3 (OT3)
P8-0 (S15)
COM2 (OT2)
10 11 12 13 14 15 16 17 18 19 20
S14 (OT18)
9
S13 (OT17)
8
S12 (OT16)
7
S11 (OT15)
6
S10 (OT14)
5
S9 (OT13)
4
S8 (OT12)
3
S7 (OT11)
2
S6 (OT10)
1
COM1 (OT1)
LCD driver (1/4 duty, 1/2 bias: 88 segments max)
2004-09-13
TC9328AF
Block Diagram
Peripheral
CPU
P1-3
XOUT
X’tal
OSC
XIN
Port1
P1-0
Gregulator
PSC
R/W Buffer
P2-3 (PSC)
Vreg (1.5 V)
Vreg
Port2
P2-0
DO1 (P)
ALU
Phase
Comparator
DO2 (OT/N)
P3-3
Port3
P3-0
RAM
(4 × 512 words)
VLCD
FMin
PLL
AMin
P6-3
Port6
IFin1 (IN1)
P6-0
Data Reg
(16 bit)
IF
Counter
IFin2 (IN2)
P7-3
Port7
Up/Down
Counter
P7-0
MUTE
Timer
ROM
INTR1
Interrupt/
Counter
INTR2 (PCTRin)
Instruction
Decoder
(16 × 8192 Steps)
MUTE
P9-3 (S22)
Port9
P9-0 (S19)
P8-3 (S18)
Port8
P8-0 (S15)
Serial
Interface
LCD
Driver
P4-3 (SCK)
P4-2 (SO)
VLCD
Port4
P4-1 (SI)
HOLD
Program
Counter
P4-0 (BUZR)
TEST
Reset
BUZR
VDD
Stack regulator
(8 Level)
VDB
RESET
VDD
GND
VDB
AD
Converter
Doubler
C1
C2
VEE
(1.5 V)
P5-3 (ADin4)
P5-2 (ADin3)
Port5
VEE
C3
P5-1 (ADin2)
VLCD
LCD Driver/Output Port
P5-0 (ADin1)
Doubler
C4
3
S14 (OT18)
S13 (OT17)
S12 (OT16)
S11 (OT15)
S10 (OT14)
S2 (OT6)
S1 (OT5)
COM4
VLCD
(OT4)
COM3 (OT3)
COM2 (OT2)
COM1 (OT1)
VLCD
2004-09-13
TC9328AF
Description of Pin Function
Pin No.
Symbol
1
COM1/OT1
2
COM2/OT2
Pin Name
COM3/OT3
4
COM4/OT4
Remarks
Output common signals to LCD panels.
Through a matrix with pins S1 to S22, a
maximum 88 segments can be
displayed.
LCD common
output/Output port
3
Function and Operation
VLCD
Three levels, VLCD, VEE, and GND, are
output at 62.5 Hz every 2 ms.
VEE
VEE is output after system reset and
CLOCK STOP are released, and a
common signal is output after the DISP
OFF bit is set to “0”.
These pins can be programmed as
output ports (Note 1).
Segment signal output pins for LCD
panel. Together with COM1 to COM4, a
matrix is formed that can display a
maximum of 88 segments.
S1/OT5~
5~18
S14/OT18
LCD segment
output/Output port
VLCD
All pins from S1 to S14 can be
programmed as output ports (Note),
and all pins from S15 to S22 as I/O
ports, in units of pins.
When the pins function as output ports,
VLCD pin potential and GND potential
are output to them. When the pins
function as I/O ports, drain output is
N-ch open. Because power is supplied
from VLCD for the I/O ports, up to VLCD
voltage (3 V) can be applied.
P8-0/S15~
19~26
P9-3/S22
LCD segment
output/ I/O port
VLCD
These data ports (OT1 to OT18) are
incremented by 1 by instruction every
time data are accessed. Therefore, they
can be used for external memory
address signals, facilitating data
access.
Note: After system reset, the output
port pins are set to LCD output,
the I/O port pins to I/O port input.
VDD
Input
instruction
VDD
The input and output of these 4-bit I/O
ports can be programmed in 1-bit units.
27~30
P1-0~P1-3
I/O port 1
These pins can be programmed to be
pulled up or down. Thus, they can be
used as key input pins.
By altering the input of I/O ports set to
input, the CLOCK STOP mode or the
WAIT mode can be released, and the
MUTE bit of the MUTE pin can be set to
“1”.
VDD
RIN1
VDD
Note 1: When the LCD pin is set as an output port, the “H” level output is the doubled voltage VLCD. Therefore,
disconnect the voltage doubler boosting capacitor but connect the VLCD pin to the VDD pin.
4
2004-09-13
TC9328AF
Pin No.
Symbol
32~34
P2-0~P2-2
35
P2-3/PSC
Pin Name
I/O port 2
I/O port 2
/Prescaller
/PSC output
Function and Operation
Remarks
VLCD
The input and output of these 4-bit I/O
ports can be programmed in 1-bit units.
The P2-3 pin is also used as a PLL
prescaller PSC signal output pin. A PLL
can be configured using an external
prescaller. In such a case, set the pin to
I/O port output.
VDD
Input
instruction
4-bit I/O ports, allowing input and output
to be programmed in 1 bit units.
54~57
58~61
62~69
P3-0~P3-3
P5-0/ADin1~
P5-3/ADin4
P6-0~P7-3
I/O port 3
Pins P5-0 to P5-3 can also be used for
analog input to the built-in 6-bit,
4-channel AD converter.
The conversion time of the built-in AD
converter using the successive
I/O port 5
comparison method is 280 µs. The
/AD analog voltage necessary pin can be programmed to
input
AD analog input in 1-bit units. Up to the
doubled voltage VDB (VDD × 2) can be
input as the AD input voltage.
I/O port 6, 7
The I/O ports are N-ch open drain
output. Up to the VDB voltage can be
applied to the AD input pins, and up to
3.6 V can be applied to the I/O port
pins. I/O port 3 can obtain N-ch
high-output current (2 mA typ.) even at
low voltage.
To AD converter
VDD
Input
instruction
The AD converter and all associated
controls are performed via sortware.
5
2004-09-13
TC9328AF
Pin No.
Symbol
Pin Name
Function and Operation
Remarks
4-bit I/O ports, allowing input and output
to be programmed in 1-bit units.
The P4-0 pin is also used for buzzer
output. P4-1 to P4-3 are also used as
serial interface circuit (SIO) input /
output pins.
P4-0/BUZR
P4-1/SI
36~39
I/O port 4
/Buzzer output
/Serial data input
P4-2/SO
/Serial data output
P4-3/SCK
/Serial clock I/O
VDD
The buzzer output can select 8 kinds of
0.625 to 3 kHz frequencies with 4
modes: continuous output, single-shot
output, 10 Hz intermittent output, and
10 Hz intermittent 1 Hz interval output.
SIO functions for 4-bit or 8-bit serial
data inputs from the SI pin and outputs
from the SO pin at the SCK pin clock
edge.
Input
instruction
(P4-0)
The clock for serial operation (SCK) is
capable of internal (SCK = 37.5 kHz)/
external options and rise/fall shift
options. The SO pin is also capable of
switching to serial inputs (SI),
facilitating the control of various LSI’s
and communication between
controllers.
VDD
When SIO interrupts are enabled, an
interrupt is generated after SIO
execution and the program jumps to
address 4.
This is useful for high-speed serial
communications.
All SIO inputs use built-in Schmitt
circuits.
Input instruction + SIOon
(P4-1~P4-3)
P3-3 pins also functions as the output
for a built-in buzzer.
SIO, buzzer, and all associated controls
can be programmed.
1-bit output port, normally used for
muting control signal output.
40
MUTE
Muting output port
VDD
This pin can set the internal MUTE bit
to “1” according to a change in the input
of I/O port 1 and HOLD . MUTE bit
output logic can be changed.
Input pin used for controlling TEST
mode.
41
TEST
Test mode control
input
VDD
“H” (high) level indicates TEST mode,
while “L” (low) indicates normal
operation.
The pin is normally used at low level or
in NC (no connection) state.
(A pull-down resistor is builtin).
6
RIN2
2004-09-13
TC9328AF
Pin No.
Symbol
Pin Name
Function and Operation
Remarks
Input pin for request/release hold mode.
Normally, this pin is used to input radio
mode selection signals or battery
detection signals.
Hold mode includes CLOCK STOP
mode (stops crystal oscillation) and
WAIT mode (halts CPU). Setting is
implemented with the CKSTP
instruction or the WAIT instruction.
42
HOLD
Hold mode control
input
To request Clock Stop mode, either
L-level detection on the HOLD pin or
forced execution can be programmed.
The mode is released by H-level
detection on the HOLD pin or input
change, respectively. Executing the
CKSTP instruction stops the clock
generator and the CPU, entering
memory backup state. In memory
backup state, current dissipation
becomes low (1 µA or less) and the
display output/CMOS output ports
automatically become L level and N-ch
open drain output Off.
VDD
Regardless of this input state, Wait
mode is executed in order to lower
power dissipation. Either crystal
oscillator only in operation or CPU
suspension can be programmed. For
crystal oscillator only in operation, all
displays are at L level and other pins
are in hold state. For CPU suspension,
the CPU stops and all others retain
their states. Wait mode is released by
changing HOLD input.
External interrupt input pins.
When interrupts are enabled and a 13.3
to 26.7 ms pulse or longer is input to
the pin, interrupt INTR1/2 is generated
and the program jumps to address 1/2.
Input logic or rising/falling edge can be
selected for each input interrupt.
INTR1
43
INTR2
44
/PCTRin
External interrupt
input
/Pulse counter
input
The internal 8-bit timer clock input can
be selected as input to the pins. When
the count value reaches the specified
value, an interrupt is generated
(address 3).
The pin is also used for input of an 8-bit
pulse counter. Input rising/falling or
upcount/downcount can be selected for
the counter.
These inputs use built-in Schmitt
circuits. The pins can also be used as
input ports for input of remote control
signals or a tape count.
7
2004-09-13
TC9328AF
Pin No.
Symbol
Pin Name
Function and Operation
Remarks
IF signal input pin for the IF counter to
count the IF signals of the FM and AM
bands and to detect the automatic stop
position.
The input frequency is between 0.3 to
12 MHz. A built-in input amp. and C
coupling allow operation at low-level
input.
45
IFin1/IN1
46
IFin2/IN2
IF signal input
/Input port
The IF counter is a 20-bit counter with
optional gate times of 1, 4, 16 and 64
ms. 20 bits of data can be readily
stored in memory. In Manual mode,
gate On/Off can be performed using
instruction.
RfIN2
VDD
The input pin can be programmed for
use as an input port (IN port).
Note: When a pin is set to IF input, the
input is at high impedance in PLL
Off mode or if the pins are not
used for input.
Pins to which power is applied.
0.01 µF
VDD
VDD
4.7 µF
31, 50
Normally, VDD = 0.9~1.8 V is applied.
For the PLL, power for the prescaller in
the programmable counter block and IF
input amp can be individually
programmed. By switching to different
modes depending on the power supply
voltage and the frequency used, current
dissipation can be lowered.
Connect a stabilizing capacitor between
the VDD pin and GND (4.7 µF, 0.01 µF
typ.).
Power-supply pins
47, 73
GND
In backup state (at execution of the
CKSTP instruction), current dissipation
drops (1 µA or less) and the power
supply voltage can be reduced to 0.75
V.
If more than 0.9 V is applied when the
pin voltage is 0, the device system is
reset and the program starts from
address “0”. (Power on reset)
GND
Note: To operate the power on reset,
the power supply should start up
in 10~100 ms.
Note: The power-on reset function can
be enabled/disabled using the AI
switch.
8
2004-09-13
TC9328AF
Pin No.
Symbol
Pin Name
Function and Operation
Remarks
Programmable counter input pin for
FM/AM band.
48
FMin
For FM input, mode can be switched
between 1/2 + Pulse Swallow VHF and
FM mode. For AM input, mode can be
FM local oscillation switched between Pulse Swallow (HF)
and Direct Dividing (LF) mode.
signal input
RfIN1
VDD
Normally, local oscillation output
(Voltage-Controlled Oscillator: VCO
output) of 50 to 230 MHz is input in
VHF mode; 30 to 130 MHz in FM mode;
1 to 30 MHz in HF mode; 0.5 to 8 MHz
in LF mode.
A PLL can be configured using an
external prescaller. In such a case, set
the pin to LF, and connect the
prescaller divider output to the AMin
input pin and the PSC input to the P2-3
(PSC) output pin.
49
AMin
RfIN2
VDD
AM local oscillation
signal input
With an input amp incorporated,
capacitive-coupling, small-amplitude
operation.
Note: The input is at high impedance in
PLL Off mode or if the pins are
not used for input.
PLL phase comparator output pins.
Tristate output. When the program
counter divider output is higher than the
reference frequency, H level is output;
when lower, L level; and when they
match, high impedance. For the phase
comparator power supply, a 1.5 V
constant voltage supply (Vreg pin) is
used. Even if the power supply voltage
drops, a stable PLL can be configured.
Because DO1 and DO2 are output in
parallel, a filter constant can be
optimally designed for each FM/AM
band.
52
DO1/P
Phase comparator
output/output port
/P output
51
DO2/OT/N
Phase comparator
output/output port
/N output
Vreg
The DO2 pin can be programmed to
high impedance or as an output port
(OT). Therefore, using the DO1 and
DO2 pins, lockup time can be improved
or the pins can be effectively used as
output ports.
Also, the phase comparator charge
pump control signal (P/N) can be output
from the DO1/2 pin by program so a
PLL using an external charge pump can
be configured. In such a case, when the
program counter divider output is higher
than the reference frequency, P/N is
output at H/L level; when lower, L/H
level; and when they match, L/L level.
When set to this mode, H level output
becomes VDD level.
Note: For tristate output, the H level
output uses a constant voltage
supply. When H level output
current is required, Toshiba
recommend using an external
power supply.
9
2004-09-13
TC9328AF
Pin No.
Symbol
Pin Name
Function and Operation
Remarks
Phase comparator constant voltage
supply.
53
Vreg
Phase comparator
constant voltage
supply
When the phase comparator output is
tristate output, a constant voltage
supply of 1.5 V (typ.) is output to the
pin. For this output, connect a
stabilizing capacitor (0.47 µF typ.). At
constant voltage operation, the H level
phase comparator output uses a
constant voltage. Thus, when H level
output current is required, Toshiba
recommend using an external power
supply. In such a case, externally apply
1.8~3.6 V to the pin.
Vreg
When the phase comparator output is
output using the charge pump control
signal (P/N), the pin becomes the VDD
level. Then, the phase comparator
output operates using the power supply
voltage.
Input pin for system reset signals.
RESET takes place while at low level;
at high level, the program starts from
address “0”.
70
RESET
Reset input
VDD
Normally, if more than 0.9 V is supplied
to VDD when the voltage is 0, the
system is reset (power on reset).
Accordingly, this pin should be set to
high level during operation.
Note: When the power-on reset function
is enabled/disabled using the AI
switch, reset by pin.
ROUT
71
Crystal oscillator pins.
XOUT
XOUT
A reference 75 kHz crystal oscillator is
connected to the XIN and XOUT pins.
Crystal oscillator
pin
72
XIN
The oscillator stops oscillating during
CKSTP instruction execution.
RfXT
VDD
XIN
The VXT pin is the power supply for the
crystal oscillator. A stabilizing capacitor
(0.47 µF typ.) is connected.
10
2004-09-13
TC9328AF
Pin No.
74
Symbol
C1
76
C2
77
VEE
78
C3
79
C4
VLCD
Function and Operation
Remarks
Voltage doubler boosting output pins.
VDB
75
80
Pin Name
The VDB pin doubles the VDD pin
voltage using the voltage doubler
boosting capacitor between C1 and C2.
The doubled voltage is used for the AD
converter and constant voltage circuit
(Vreg, VEE) power supply.
Voltage doubler
boosting output
pins
The VEE pin supplies a constant
voltage of 1.5 V from the VDB voltage.
The voltage is doubled (to 3 V) using
the voltage doubler boosting capacitor
between C3 and C4. The doubled
voltage is then supplied to the VLCD
pin. The VEE potential and the VLCD
potential are used to drive the LCD.
VLCD
Connect a stabilizing capacitor between
the VDB pin and GND (0.1 µF, 10 µF
typ.), and between the VLCD pin and
GND (0.1 µF typ.). Connect a voltage
doubler boosting capacitor (0.1 µF typ.)
between C1 and C2, and between C3
and C4. (Note 1)
Note 1: When the LCD pin is set as an output port, the “H” level output is the doubled voltage VLCD. Therefore,
disconnect the voltage doubler boosting capacitor but connect the VLCD pin to the VDD pin.
11
2004-09-13
TC9328AF
Description of Operations
○
CPU
The CPU consists of a program counter, a stack register, ALU, a program memory, a data memory,
G-register, a data register, DAL address register, carry F/F, a judgment circuit, and an interruption circuit.
1. Program Counter (PC)
The program counter consists of a 14-bit binary up-counter and addresses the program memory (ROM).
The counter is cleared when the system is reset and the programs start from the 0 address.
Under normal conditions, the counter is increased in increments of one whenever an instruction is
executed, but the address specified in the instruction operand is loaded when a JUMP instruction or CALL
instruction is executed.
Also, when an instruction that is equipped with the skip function (AIS, SLTI, TMT, RNS instructions,
etc.) is executed and result of this includes a skip condition, the program counter is increased in increments
of two and the subsequent instruction is skipped. Furthermore, if interruption is received, the vector
address corresponding to each interruption is loaded.
Note: Program memory (ROM) It is 0000H-0FFFH address.
For this reason, an access setup to the address beyond this is forbidden.
Contents of Program Counter (PC)
Instruction
PC13 PC12 PC11 PC10
Power on reset
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
Operand of instruction (ADDR1)
JUMP ADDR1
JUMP ADDR2
PC9
0
0
0
0
Operand of instruction (ADDR2)
0
Operand of
instruction (ADDR3)
0
RESET by reset pin
Contents of general
register (r)
DAL (DA)
DAL address register (DA)
(DAL bit = 1)
RN, RNS, RNI
Contents of stack register
At the time of an
interruption reception
Power on reset
Vector address of each interruption
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET by reset pin
Priority
Interruption Factor
Vector Address
1
INTR1 pin
0001H
2
INTR2 pin
0002H
3
Serial inter face
0003H
4
Timer counter
0004H
2. Stack Register
A register consisting of 8 × 14 bits which stores the contents of the program counter +1 (the return
address) when a sub-routine call instruction is executed, or an interrupt is processed. The contents of the
stack register are loaded into the program counter when the return instruction (RN, RNS, RNI instruction)
is executed.
There are eight stack levels available and nesting occurs up to eight levels.
12
2004-09-13
TC9328AF
3. ALU
ALU is equipped with binary 4-bit parallel add/subtract functions, logical operation, comparison and
multiple bit judgment functions. This CPU is not equipped with an accumulator, and all operations are
handled directly within the data memory.
4. Program Memory (ROM)
The program memory consists of 16 bits × 16384 steps and is used for storing programs. The usable
address range consists of 16384 steps between address 0000H and 1FFFH.
The program memory divids 16384 into 8 separate steps and consists of page 0 to 7. The JUMP
instruction can be freely used throughout all 16384 steps though the Call instruction can use the address
from 0000H to 0fffH from page 0 to 3.
In case of setting DAL bit, arranged on I/O map, “0” (DAL ADDR3, (r) command), the program memory
address 0000H to 03FFH, page 0, are used as data area and setting DAL bit “1” (DAL (DA) command), the
program memory address 0000H to 0FFFH (page 0 to 3) are used as data area. The 16-bit content of this
can be loaded into the data register by executing the DAL instruction.
Note: Set the address for data area of program memory outside of the program loop.
ROM
16 bits
Page 1
0C00H
Page 3
1000H
Page 4
1400H
Page 5
1800H
Page 6
DAL instruction specification area (*2)
Page 2
JUMP instruction specification area
0800H
0001H
0002H
0003H
0004H
JUMP address at initialization
Interruption
vector address
0400H
0000H
CALL instruction specification area
Page 0
(1 k step)
(*1)
0000H
The vector address at an interruption
INTR1
INTR2
Serial interface
8-bit timer
1C00H
Page 7
1FFFH
*1:
DAL bit = DAL access area at setting “0”
*2:
DAL bit = DAL access area at setting “1”
Note: DAL bit is arranged on I/O map.
13
2004-09-13
TC9328AF
5. Data Memory (RAM)
The data memory consists of 4 bits × 512 words and used for storing data. These 512 words are expressed
in row address (6 bits) and column addresses (4 bits). 348 words (row address = address 04H to 1FH) within
the data memory are addressed indirectly by the G-register. Therefore, it is necessary to specify the row
address with the G-register before the data in this area is processed.
The address 00H to 0FH within the data memory are known as general registers, and these can be used
simply by specifying the relevant column address (4 bits). These sixteen general registers can be used for
operations and transfers with the data memory, and may also be used as normal data memories.
Note: The column address (4 bits) that specifies the general register is the register number of the general
register.
Note: All row address (addresses 00H to 1FH) can be specified indirectly with the G-register.
Note: The data memory has 512 words and the highest bit of 6 in the G-register row address must be used “0”
(00H - 1FH address).
Note: By using LD and ST instruction, it can be addressed directly in 256 words (row address = 00H to 0FH) in
the data memory.
COLMUN ADDRESS: DC
ROW ADDRESS: DR
0
(*)
1 2
3
4
5
6 7
8 9 A B C D E F
General register
(One from the addresses
00H to 0fH)
0
1
2
3
4
5
6
7
Indirect specification of
row addresses (04H to
2FH) with the G-register
8
9
A
B
C
D
E
LD and ST instruction can specify
row address from 00H to 0FH
directly.
F
10
11
12
*: The indirect
specification of row
address = 00H to 1FH
is also possible.
1D
1E
1F
14
2004-09-13
TC9328AF
6. G-Register (G-REG)
The G-register is a 6-bit register used for addressing the row addresses (DR = 04H to 2FH addresses) of
the data memory’s 448 words.
The contents of this register are validated when the MVGD instruction or MVGS instruction are
executed, and not affected through the execution of any other instructions. This register is used as one of
the ports, and the contents are set when the OUT1 instruction from among the I/O instructions is executed.
The 6-bit contents can be directly set by execution of STIG instruction.
(→ Refer to the section in Register Ports.)
7. Data Register (DATA REG)
The data register consists of 1 × 16 bits and loads 16 bits of optional address data in the program
memory at the DAL instruction executed. This register is used as one of the ports, and the contents are
loaded into the data memory in units of 4 bits when IN1 instruction among the I/O instruction is executed.
(→ Refer to the section in Register Ports.)
This register can be written from the data memory, and is used for the evacuation and the return
processing of the data at the interruption.
8. DAL Address Register (DA)
The data register consists of 1 × 14 bits.
If DAL instruction is executed when the DAL bit is set to “1”, 16 bits of the data of the free addresses in
the program memory specified by this DAL address register are loaded. By the setting (DATA) → DA bit to
“1”, the contents of data register (DATA REG) can be transmitted to DAL address register (DA).
This register and a control bit are treated as a port, and are accessed by IN3/OUT3 instruction of an
input-and-output instruction. (→ Refer to the register port item)
9. Carry F/F (Ca Flag)
This is set when either Carry or Borrow are issued in the result of calculation instruction execution and
is reset if neither of these are issued.
The contents of carry F/F can only be amended through the execution of addition and, subtraction or,
CLT and, CLTC instructions, and not affected by the execution of any other instruction.
The carry F/F can be accessed by IN1/OUT1 instruction of an input-and-output instruction. For this
reason, the evacuation and the return at the time of interruption are performed by the input-and-output
instruction between data memories. (Refer to the register port item)
10. Judgment Circuit (J)
This circuit judges the skip conditions when an instruction with the skip function is executed. The
program counter is increased by two when the skip conditions are satisfied, and the subsequent instruction
is skipped.
There are 15 instructions equipped with a wide variety of skip functions. (→ Refer to the items marked
with a “*” symbol in the Table Instruction Functions and Operational Instructions)
11. Interruption Circuit
An interruption circuit branches into each vector address by the demand from peripheral hardware, and
processes each interruption. (→ Refer to the interruption functional item)
15
2004-09-13
TC9328AF
12. Instruction Set Table
A total of 57 instruction sets is available, and all of these are single-word instructions.
These instructions are expressed with 6-bit instruction codes.
Upper 2 bits
Lower 4 bits
00
01
10
11
0
1
2
3
0000
0
AI
M, I
TMTR
r, M
SLTI
M, I
0001
1
AIC
M, I
TMFR
r, M
SGEI
M, I
0010
2
SI
M, I
SEQ
r, M
SEQI
M, I
0011
3
SIB
M, I
SNE
r, M
SNEI
M, I
0100
4
ORIM
M, I
TMTN
M, N
0101
5
ANIM
M, I
TMT
M, N
0110
6
XORIM
M, I
TMFN
M, N
0111
7
MVIM
M, I
TMF
M, N
1000
8
AD
r, M
IN1
M, C
1001
9
AC
r, M
IN2
M, C
IN3
M, C
LD
ST
1010
r, M*
JUMP ADDR1
M*, r
A
SU
r, M
1011
B
SB
r, M
OUT1
M, C
1100
C
ORR
r, M
CLT
r, M
OUT2
M, C
1101
D
ANDR
r, M
CLTC
r, M
OUT3
M, C
1110
E
XORR
r, M
MVGD
r, M
DAL
ADDR3, r
SHRC
M
RORC
M
STIG
I*
CAL ADDR2
1111
F
MVSR
M1, M2
MVGS
M, r
SKP, SKPN
RN, RNS
WAIT
P
CKSTP
XCH
M
DI, EI, RNI
NOOP
16
2004-09-13
TC9328AF
13. Table of Instruction Functions and Operational Instructions
(Description of the symbols used in the table)
M
; Data memory address.
Normally one of the addresses among the addresses 000H to 03FH in the data
memory.
M*
; Data memory address (256 words)
One of the addresses among the addresses 000H to 0FFH in the data memory.
(Effective only when ST and LD instruction are executed.)
r
; General register
One of the addresses among the addresses 000H to 00FH in the data memory.
PC
; Program Counter (14 bits)
STACK
; Stack register (14 bits)
G
; G-register (6 bits)
DATA
; Data register (16 bits)
I
; Immediate data (4 bits)
I*
; Immediate data (6 bits, effective only when STIG instruction is executed.)
N
; Bit position (4 bits)
⎯
; ALL “0”
C
; Port code No. (4 bits)
CN
; Port code No. (4 bits)
RN
; General register No. (4 bits)
ADDR1
; Program memory address (14 bits)
ADDR2
; Program memory address in the pages from 0 to 3 (12 bits)
ADDR3
; The upper 6 bits of the program memory address in the page 0.
DA
; DAL address register
(14bits, effective only when DAL instruction, DAL bit = 1, is executed.)
Ca
; Carry
CY
; Carry flag
P
; Wait condition
b
; Borrow
IN1~IN3
; The ports used during the execution of instructions from IN1 to IN3
OUT1~OUT3 ; The ports used during the execution of instructions from OUT1 to OUT3
()
; Contents of the register or data memory
[]C
; Contents of the port indicated by the code No. C (4 bits)
[]
; Contents of the data memory indicated by the contents of the register or data memory
[]P
; Contents of the program memory (16 bits)
IC
; Instruction code (6 bits)
*
; Commands equipped with the skip function
DC
; Data memory column address (4 bits)
DR
; Data memory row address (2 bits)
DR*
; Data memory row address
(4 bits, effective only when ST and LD instruction is executed)
(M) b0~(M) b3 ; Bit data of the contents of a data memory (1 bit)
17
2004-09-13
TC9328AF
Comparison Instructions
Subtraction Instructions
Addition Instructions
Instruc
-tion
Group
Mnemonic
Skip
Function
Machine Language (16 bits)
Function Description
Operation Description
IC
(6 bits)
A
(2 bits)
B
(4 bits)
C
(4 bits)
000000
DR
DC
I
AI
M, I
Add immediate data
to memory
AIC
M, I
Add immediate data
M ← (M) + I + ca
to memory with carry
000001
DR
DC
I
AD
r, M
Add memory to
general register
r ← (r) + (M)
001000
DR
DC
RN
AC
r, M
Add memory to
general register with
carry
r ← (r) + (M) + ca
001001
DR
DC
RN
SI
M, I
Subtract immediate
data from memory
M ← (M) − I
000010
DR
DC
I
SIB
M, I
Subtract immediate
data from memory
with borrow
M ← (M) − I − b
000011
DR
DC
I
SU
r, M
Subtract memory
from general register
r ← (r) − (M)
001010
DR
DC
RN
SB
r, M
Subtract memory
from general register
with borrow
r ← (r) − (M) − b
001011
DR
DC
RN
SLTI
M, I
*
Skip if memory is
less than immediate
data
Skip if (M) < I
110000
DR
DC
I
SGEI
M, I
*
Skip if memory is
greater than or equal Skip if (M) >
=I
to immediate data
110001
DR
DC
I
SEQI
M, I
*
Skip if memory is
equal to immediate
data
Skip if (M) = I
110010
DR
DC
I
SNEI
M, I
*
Skip if memory is not
equal to immediate
Skip if (M) ≠ I
data
110011
DR
DC
I
SEQ
r, M
*
Skip if general
register is equal to
memory
Skip if (r) = (M)
010010
DR
DC
RN
SNE
r, M
*
Skip if general
register is not equal
to memory
Skip if (r) ≠ (M)
010011
DR
DC
RN
CLT
r, M
Set carry flag if
general register is
(CY) ← 1 if (r) < (M) or
less than memory, or (CY) ← 0 if (r) >
= (M)
reset if not
011100
DR
DC
RN
r, M
Set carry flag if
general register is
less than memory
with carry or reset if
not
011101
DR
DC
RN
CLTC
M ← (M) + I
(CY) ← 1 if (r) < (M) + (ca)
or
(CY) ← 0 if (r) >
= (M) + (Ca)
18
2004-09-13
TC9328AF
Logical Instructions
I/O Instructions
Transfer Instructions
Instruc
-tion
Group
Mnemonic
Skip
Function
Machine Language (16 bits)
Function Description
Operation Description
IC
(6 bits)
A
(2 bits)
B
(4 bits)
C
(4 bits)
LD
r, M*
Load memory to
general register
r ← (M*)
0101
DR*
(4 bits)
DC
RN
ST
M*, r
Store memory to
general register
M* ← (r)
0110
DR*
(4 bits)
DC
RN
MVSR M1, M2
Move memory to
(DR, DC1) ← (DR, DC2)
memory in same row
001111
DR
DC1
DC2
MVIM
Move immediate data
M←I
to memory
000111
DR
DC
I
MVGD r, M
Move memory to
destination memory
[(G), (r)] ← (M)
referring to G-register
and general register
011110
DR
DC
RN
MVGS M, r
Move source
memory referring to
G-register and
(M) ← [(G), (r)]
general register to
memory
(Note)
011111
DR
DC
RN
STIG
I*
Move immediate data
G ← I*
to G-register
111111
IN1
M, C
Input IN1 port data to
M ← [IN1] C
memory
111000
DR
DC
CN
OUT1
M, C
Output contents of
memory to OUT1
port
111011
DR
DC
CN
IN2
M, C
Input IN2 port data to
M ← [IN2] C
memory
111001
DR
DC
CN
OUT2
M, C
Output contents of
memory to OUT2
port
111100
DR
DC
CN
IN3
M, C
Input IN3 port data to
M ← [IN3] C
memory
111010
DR
DC
CN
OUT3
M, C
Output contents of
memory to OUT3
port
[OUT3] C ← (M)
111101
DR
DC
CN
ORR
r, M
Logical OR of
general register and
memory
r ← (r) ∨ (M)
001100
DR
DC
RN
ANDR
r, M
Logical AND of
general register and
memory
r ← (r) ∧ (M)
001101
DR
DC
RN
ORIM
M, I
Logical OR of
memory and
immediate data
M ← (M) ∨ I
000100
DR
DC
I
ANIM
M, I
Logical AND of
memory and
immediate data
M ← (M) ∧ I
000101
DR
DC
I
XORIM M, I
Logical exclusive OR
of memory and
M ← (M) ∀ I
immediate data
000110
DR
DC
I
XORR
Logical exclusive OR
of general register
r ← (r) ∀ (M)
and memory
001110
DR
DC
RN
M, I
r, M
[OUT1] C ← (M)
[OUT2] C ← (M)
I*
0010
Note: The execution period for the MVGS instruction is two machine cycles.
19
2004-09-13
TC9328AF
Bit Judgment Instruction
Instruc
-tion
Group
Mnemonic
Subroutine
Instructions
JUMP Instructions
Function Description
Operation Description
IC
(6 bits)
A
(2 bits)
B
(4 bits)
C
(4 bits)
TMTR
r, M
*
Test general register
bits by memory bits,
then skip if all bits
specified are true
Skip if r [N (M)] = all “1”
010000
DR
DC
RN
TMFR
r, M
*
Test general register
bits by memory bits,
then skip if all bits
specified are false
Skip if r [N (M)] = all “0”
010001
DR
DC
RN
TMT
M, N
*
Test memory bits,
then skip if all bits
specified are true
Skip if M (N) = all “1”
110101
DR
DC
N
TMF
M, N
*
Test memory bits,
then skip if all bits
specified are false
Skip if M (N) = all “0”
110111
DR
DC
N
TMTN
M, N
*
Test memory bits,
then not skip if all bits Skip if M (N) = not all “1”
specified are true
110100
DR
DC
N
TMFN
M, N
*
Test memory bits,
then not skip if all bits Skip if M (N) = not all “0”
specified are false
110110
DR
DC
N
SKP
*
Skip if carry flag is
true
Skip if (CY) = 1
111111
00
⎯
0011
SKPN
*
Skip if carry flag is
false
Skip if (CY) = 0
111111
01
⎯
0011
Call subroutine
STACK ← (PC) + 1 and
PC ← ADDR2
1011
RN
Return to main
routine
PC ← (STACK)
111111
10
⎯
0011
RNS
Return to main
routine and skip
unconditionally
PC ← (STACK) and skip
111111
11
⎯
0011
Jump to address
specified
PC ← ADDR1
10
ADDR1 (14 bits)
CAL
JUMP
ADDR2
ADDR1
ADDR2 (12 bits)
Reset IMF
(Note) IMF ← 0
111111
00
⎯
0111
EI
Set IMF
(Note) IMF ← 1
111111
01
⎯
0111
RNI
Return to main
PC ← (STACK)
routine and set IMF
(Note) IMF ← 1
111111
11
⎯
0111
DI
Interruption
Instruction
Machine Language (16 bits)
Skip
Function
Note: IMF bits is an interruption master permission flag and is arranged on I/O map.
(→ Refer to the interruption function)
20
2004-09-13
TC9328AF
Instruc
-tion
Group
Mnemonic
Other Instructions
SHRC
M
Skip
Function
Function
Description
Shift memory bits to
right direction with
carry
RORC M
Rotate memory bits
to right direction with
carry
XCH
Exchange memory
bits mutually
DAL
M
ADDR3, r
WAIT
P
Operation
Description
A
(2 bits)
B
(4 bits)
C
(4 bits)
0 → (M) b3 → (M) b2 →
(M) b1 → (M) b0→ (CY)
111111
DR
DC
0000
(M) b3 → (M) b2 →
(M) b1→ (M) b0 →
(CY)
111111
DR
DC
0001
111111
DR
DC
0110
(M) b3 ⇔ (M) b0,
(M) b2 ⇔ (M) b1
IF DAL bit = 0 then
load program in page
0 to DATA register
(Note)
IF DAL bit = 1 then
DATA ← [ADDR3 + (r)] p
load program
in page 0
memory referring to
DAL address register
to DATA register
(Note)
At P = “0” H, the
condition is CPU
waiting
(Soft wait mode)
At P = “1” H, expect
for clock generator,
all function is waiting
(Hard wait mode)
CKSTP
Clock generator stop
NOOP
No operation
Machine Language (16 bits)
IC
(6 bits)
111110
ADDR3 (6 bits)
RN
Wait at condition P
111111
P
⎯
0100
Stop clock generator to
MODE condition
111111
⎯
⎯
0101
111111
⎯
⎯
1111
⎯
Note: The lower four bits among the ten-bit address of the program memory specified with the DAL instruction (DAL
ADDR3 and r) are addressed indirectly with the contents of the general register.
Note: The execution period for the DAL instruction is two machine cycles
Note: DAL bit and DAL address register (DA) are arranged on I/O map.
(→ Refer to the register port item)
Note: When “1” is set to DAL bit and DAL instruction is executed, all the operand part becomes invalid and reference
address is used for DAL address register (DA). In this case, assign 0, 0 as dummy data for the operand.
21
2004-09-13
TC9328AF
I/O Map (IN1 (M, C), IN2 (M, C), IN3 (M, C), OUT1 (M, C), OUT2 (M, C), OUT3 (M, C))
φL1
φL2
φL3
φK1
φK2
OUT1
OUT2
OUT3
IN1
IN2
I/O
Code
Y1
Y2
Y4
Y8
Y1
Y2
Power control
0
HF
Y4
Y8
Y1
Y2
I/O port 1 pull-down
Y4
Y8
Y1
I/O port 1
Y2
Y4
Y8
PW1
IN3
Y2
IF monitor
Y4
Y8
Y1
Y2
A/D data
Y4
Y8
-2
-3
-2
-3
-2
-3
-2
-3
-2
-3
-2
-3
-2
-3
-2
-3
I/O port 1
0
FM
PW0
Y1
φK3
PD0
K1
Programmable counter 1
PD2
PD3
-0
-1
A/D control
-2
-3
BUSY
MANUAL
I/O port 2
OVER
AD0
AD1
IF data 1
AD2
AD3
-0
-1
A/D data
I/O port 2
1
P0
P1
P2
P3
AD SEL0
Programmable counter 2
AD SEL1
STA
*
-0
-1
Serial interface control 1
-2
-3
F0
F1
I/O port 3
F2
F3
AD4
AD5
BUSY
0
-0
-1
IF data 2
I/O port 3
2
P4
P5
P6
P7
SCK - INV
edge
Programmable counter 3
SCK - I/O
SIO-ON
-0
-1
Serial interface control 2
-2
-3
F4
F5
I/O port 4
F6
F7
-0
IF data 3
-1
Serial interface monitor
I/O port 4
3
0
P8
P9
P10
P11
SO - I/ O
STA
Programmable counter 4
8/ 4 bit
*
-0
-1
Serial interface output data 1
-2
-3
F8
F9
I/O port 5
F10
F11
BUSY
IF data 4
COUNT
SIO F/F
-0
-1
Serial interface input data 1
I/O port 5
4
P12
P13
P14
5
R0
P15
SO0
SO1
Programmable
counter
Reference select
R1
R2
P16
IF counter control 1
SO4
SO5
Timer reset
6
IF1/ 2
PW
IF1/IN1
IF2/IN2
2 Hz F/F
IF counter control 2
MANUAL
G0
G1
POL1
(INTR1)
MUTE control
8
I/O-1
9
RESET
POL
HOLD
EF1
(INTR1)
DO2 control
PN
M0
-0
Clock
SO6
SO7
-0
#4
M1
ILR1
(INTR1)
ILR2
(INTR2)
-0
EF3
(SIO)
ILR3
(SIO)
ID0
POL
ID4
Buzzer output control 2
ID1
F13
F14
F15
*
-2
-3
F16
F17
ILR4
(Timer)
ID2
SI1
-1
-0
-2
-1
SI2
SI3
-0
-1
Serial interface input data 2
F18
F19
SI4
SI5
SI6
I/O port 6
SI7
-0
-1
Timer
-3
2 Hz F/F
-2
INTR1
INTR2
0
Interrupt
master flag
10 Hz
I/O port 7
100 Hz
0
MUTE control
-0
-1
I/O port 8
0
0
0
IMF
-3
I/O port 9
EF4
(Timer)
SI0
IF data 5
HOLD
IE
-0
-1
Interrupt permission flag
I/O port 9
MUTE
-0
-1
-2
HOLD PLL
off control
IF counter
Split
Prescaller
IN
Timer counter Interrupt detection data1
BEN
F12
I/O port 7
DAL
BF2
-3
I/O port 8
A
BF1
-1
Test
port 2
CKSTP
mode
POL2
(INTR2)
EF2
(INTR2)
-2
I/O port 6
Interrupt latch reset
Buzzer output control 1
BF0
-1
Interrupt permission flag
MUTE
UNLOCK
Detection
SO3
Interrupt control
7
STA/ STP
SO2
Serial interface output data 2
ID3
Timer counter Interrupt detection data2
(DATA)
→ DA
OT Count
Up
-3
I/O
POL
Unlock detection
HOLD
EF1
Input port
EF2
EF3
EF4
-0
-1
-2
-3
DAL
0
0
0
DA0
DA1
Interrupt latch
PSC ENA
F/F
ENA
IN1
IN2
IL1
IL2
IL3
IL4
Timer counter data 1
port 1
Pull-up
CT0
DAL address
CT1
CT2
CT3
Timer counter data 2
DAL address
B
BM0
BM1
BUZR ON
ID5
ID6
ID7
DA0
Timer counter control
C
CA Flag
*
*
DA1
DA2
DA3
CT4
G register 1
CT7
GT
CR
d0
Data select
d1
d2
DA2
DA3
Data register 1
CA flag
CK1
CT6
Data register 1
*
CK0
CT5
0
0
0
d3
d0
Data register 2
G register 1
Data select
d1
d2
d3
Data register 2
D
G0
G1
G2
G3
G register 2
SEL1
SEL2
SEL4
SEL8
d4
Segment data 1/ General-purpose output data
d5
d6
d7
G0
Data register 3
G1
G2
G3
S1
S2
S3
S4
d4
G register 2
d5
d6
d7
Data register 3
E
G4
G5
*
*
COM1/OT
Test port 1
COM2/OT
COM3/OT
COM4/OT
d8
Segment data2/ Segment IO control
d9
d10
d11
G4
G5
0
0
d8
Data register 4
d9
d10
d11
Data register 4
F
#0
#1
#2
#3
COM1
COM2
COM3
COM4
d12
d13
d14
d15
d12
d13
d14
d15
Refer to the next page
22
2004-09-13
TC9328AF
φKL2D
I/O
Data Select
S1
S2
S4
S8
φL2D
Y1
φL2E
φL2E
φL3B
OUT2
OUT2
OUT3
Y2
Y4
Y8
Y1
Y2
S1/OT1~OT4
0
COM1
/OT1
COM2
/OT2
COM3
/OT3
COM1
/OT5
COM2
/OT6
COM3
/OT7
COM4
/OT4
COM1
COM2
COM1
/OT9
COM2
/OT10
COM3
/OT11
COM4
/OT8
COM1
COM1
/OT13
COM2
/OT14
COM3
/OT15
COM1
COM1
/OT17
COM2
/OT18
COM3
COM1
COM4
COM4
COM1
COM3
COM2
DA8
COM4
DA12
COM4
COM1
COM3
COM2
DA1
DA2
DA5
DA6
DA9
DA10
DA13
*
COM4
DOWN
POL
*
DA3
DA0
DA7
DA4
COM4
CTR
RESET
OVER
RESET
*
Y8
DA1
DA2
DA3
DA5
DA6
DA7
DAL address 3
DA11
DA8
DA9
DA10
DA11
DAL address 4
*
DA12
DA13
0
0
Pulse counter data
*
PC0
Pulse counter control
COM3
Y4
DAL address 2
PC1
PC2
PC3
Pulse counter data
*
PC4
Segment/IO select
S7
Y2
DAL address 1
Pulse counter control
S22
COM3
Y1
DAL address 4
5
COM2
DA4
S21
COM4
Y8
DAL address 3
COM3
COM2
S6
COM1
DA0
S20
COM4
/OT16
IN3
Y4
DAL address 2
COM3
COM2
S5/OT17~OT18
4
COM4
S19
COM4
/OT12
Y2
DAL address 1
COM3
COM2
S4/OT13~OT16
3
Y1
S18
S3/OT9~OT12
2
Y8
S17
S2/OT5~OT8
1
Y4
φK3B
PC5
PC6
PC7
Pulse counter data
6
COM1
COM2
COM3
COM4
S15
S8
S16
S17
S18
OVER
0
0
0
Segment/IO select
7
COM1
COM2
COM3
COM4
S19
S20
S9
S21
S22
I/O control 1
8
COM1
COM2
COM3
COM4
-0
-1
S10
-2
-3
I/O control 2
9
COM1
COM2
COM3
COM4
-0
-1
S11
-2
-3
I/O control 4
A
COM1
COM2
COM3
COM4
COM3
COM4
COM3
COM4
COM3
COM4
COM3
COM4
COM3
COM4
-0
-1
-2
-3
S12
B
COM1
COM2
S13
C
COM1
COM2
S14
D
COM1
COM2
S15
E
COM1
COM2
S16
LCD control
F
*
COM1
COM2
DISP OFF
LCD OFF
23
OTB-UP
2004-09-13
TC9328AF
○
I/O map
All of the ports within the device are expressed with a matrix of six I/O instructions (OUT 1 to 3
instructions and IN 1 to 3 instructions) and a 4-bit code number.
The allocation of these ports is shown on the following page in the form of an I/O map. The ports used in
the execution of the various I/O instructions on the horizontal axis of the I/O map are allocated to the port
code numbers indicated on the vertical axis. The G-register, data register, DAL address register and DAL
bits are also used as ports.
The OUT1 to 3 instructions are specified as output ports and the IN 1 to 3 instructions are specified as
input ports.
Note: The ports indicated by the angled lines on the I/O map do not actually exist within the device.
The contents of other ports and data memories are not affected when data is output to a non-existent
output port with the execution of the output instruction. The data loaded from data memories is unfixed
when a non-existent input port has been specified with the execution of an input instruction.
Note: The output ports marked with an asterisk (*) on the I/O map are not used. Data output to these ports
assume the don’t care’s status.
Note: The Y1 contents of the ports expressed in 4 bits correspond to the data memory data’s low order bit and
the Y8 contents correspond to the high order bits.
The ports specified with the six I/O instructions and code No. C are coded in the following manner:
φ [K/L]
m n
(o)
Contents of the selection port (indirectly specified data, 0-F [HEX])
I/O instruction’s operand CN (0~F [HEX])
The six I/O instructions are coded with the digits 1 to 3
I/O Instruction
OUT1
OUT2
OUT3
IN1
IN2
IN3
m
1
2
3
1
2
3
Indicates the input/output port
K: Input port (IN1~IN3 instruction)
L: Output port (OUT1~OUT3 instruction)
(Example) The setting for the G-register is allocated to code “D” and “E” in the OUT1 instruction.
The encoded expression at this time becomes “φL1D”and “φL1E”.
○
Crystal Oscillation Circuit
75 kHz crystal oscillator is connected to the device’s crystal oscillator pin (XIN, XOUT) as indicated below.
Usually, the oscillation signal is supplied to the clock generator, the reference frequency divider and other
elements, and generates the various CPU timing signals and reference frequency.
(XOUT)
(XIN)
(GND)
71
72
73
70
R
CO
X’tal
CI
X’tal = 75 kHz
Note: It is necessary to use a crystal oscillator with a low CI value and favorable start-up characteristics.
Please adjust and determine external resistance and the constant of a capacitor as the actually used
crystal oscillator.
24
2004-09-13
TC9328AF
○
System Reset
The device’s system will be reset when the RESET pin is subject to the “L” level or when a voltage of 0
V → 0.9 V or more is supplied to the VDD pin (power-on reset). The program will start from 0 address
immediately after about 100 ms stand-by time. The RESET pin should be fixed at the “H” level as the
power-on reset function is used under normal condition.
Note: A power-on reset function can be forbidden with Al switch. Please specify power-on reset prohibition and
use in ES order request sheet. In case of forbidden the power-on reset function, reset with a RESET
pin.
Note: The LCD common signal and the segment output will be fixed at the “L” level during system reset and the
subsequent stand-by period.
Note: Among the internal port shown in the above I/O map, the port which is not initialized after the system
reset should be initialized by the program. The inside port on the I/O map, the port or bit with
mark on
I/O map is set to “0” after system reset and the port or bit with
mark is set to “1”. The port or bit with no
mark is unfixed.
φL2F
I/O
φL1
I/O
OUT2
φL2D
Y1
Y2
OUT1
Y4
Code
Y8
Y1
I/O control -1
Y2
Y4
Y8
Programmable
counter
Reference select
8
5
-0
-1
-2
-3
R0
After system reset, this
port is set to “0”.
After system reset, this
port is set to “1”.
(Note)
R1
R2
P16
After system reset, this bit
is unfixed.
(Note)
VDD pin
GND
RESET pin
GND
A crystal oscillator stops during
the reset from a reset pin.
XOUT pin
Internal reset
signal
Stand-by
(about 100 ms)
Reset
CPU operation
Stand-by
CPU
(about 100 ms) operation
Stand-by
(about 100 ms)
CPU
operation
<Timing of operation>
Note: When power supply voltage may become below 0.9 V, set up the clock stop mode or operate the reset
function. The CPU operations are reset when a power supply voltage is re-apply from 0.3 to 0.6 V.
(Power-on reset)
25
2004-09-13
TC9328AF
○
Back-up Mode
By executing CKSTP instruction or WAIT instruction, three kinds of back-up mode can be activated.
1. Clock Stop Mode
The clock stop mode is a function that suspends system operations and maintains the internal status
immediately prior to suspension at a low level of current consumption (under 1 µA). Crystal oscillations
suspend simultaneously and CMOS output ports and output pins for LCD display are automatically fixed
at the “L” level and N-channel open drain pins are fixed off status (high impedances) automatically. The
supply voltage can be reduced to 0.75 V with the clock stop mode.
Suspension is activated at the CKSTP instruction execution address when the CKSTP instruction is
executed. The next address is executed after approximately 100 ms of stand-by time when the clock stop
mode is cancelled.
(1)
Clock stop mode setting
There are two types of mode setting for the clock stop mode. The required setting is selected with
the CKSTP MODE bit. This bit is accessed with the OUT2 instruction for which [CN = 6H] has been
specified in the operand.
Y1
φL26
Y2
Y4
Y8
CKSTP
mode
0: MODE-0
1: MODE-1
①
MODE-0
By setting this mode, the clock stop mode is assumed if the CKSTP instruction is executed
when the HOLD pin is in the “L” level. The same operations as the NOOP instruction will be
assumed if the CKSTP instruction is executed when the HOLD pin is in the “H” level.
②
MODE-1
By setting this mode, the clock stop mode is assumed when the CKSTP instruction is executed
regardless of the HOLD pin level.
Note: PLL will assume the off status during CKSTP instruction execution.
Note: Before the execution of the clock stop instruction, be sure to access HOLD input pin and I/O port 1 input
port and reset the 2 Hz F/F. If the clock stop mode is executed without executing the instruction, it may
not be the mode.
(2)
Canceling the clock stop mode
①
MODE-0
The clock stop mode is cancelled when specified in this mode by changing the “H” level of the
HOLD pin or the input status of I/O port (P1-0~3) specified in the input port.
②
MODE-1
The clock stop mode is cancelled when specified in this mode by changing the HOLD pin or
the input status of I/O port (P1-0~3) specified in the input port.
26
2004-09-13
TC9328AF
(3)
Clock stop mode timing
①
MODE-0
HOLD pin
High impedance
XOUT pin
CPU operation
Stand-by
(about 100 ms)
Clock stop
CPU operation
CKSTP
instruction
NOOP operation
CKSTP instruction execution
NOOP operation
(The clock stop mode is assumed when the CKSTP is executed during the “L” level of the HOLD input.)
②
MODE-1
HOLD pin
High impedance
XOUT pin
CPU operation
Stand-by
(about 100 ms)
Clock stop
CPU operation
Clock stop
CKSTP
instruction
CKSTP instruction execution
CKSTP instruction execution
(The clock stop mode is assumed whenever the CKSTP instruction is executed.)
1 MΩ
HOLD
VDD 50
POWER
4700 µF
1 kΩ
POWER
1 kΩ
470 µF
VDD 50
1 MΩ
VDD 31
0.1 µF
VDD 31
42
0.1 µF
42
0.1 µF
HOLD
Example of a back-up circuit (example of a MODE-0 circuit)
0.1 µF
(4)
Example of a battery back-up
circuit
Example of a capacitor back-up
circuit
27
2004-09-13
TC9328AF
2. Wait Mode
The wait mode suspends system operations, maintains the internal status immediately prior to
suspension and reduces current consumption. There are two types of wait mode available; the SOFT WAIT
mode and the HARD WAIT mode. It is suspended at the address of the WAIT instruction execution when
the WAIT mode is activated. The next address is executed immediately after the wait mode is cancelled
without entering a stand-by status.
(1)
SOFT WAIT mode
Only the CPU operations within the device are suspended when the WAIT instruction in which [P =
0H] has been specified in the operand is executed. The crystal resonator and other elements will
continue to operate normally at this time. The SOFT WAIT mode is efficient in reducing current
consumption during clock operations used in programs that include clock functions.
Note: Current consumption will differ in accordance with execution time of CPU operation.
(2)
HARD WAIT mode
The operations of all elements, with the exception of the crystal resonator, can be suspended by the
execution of the WAIT instruction in which [P = 1H] has been specified in the operand. This enables
even greater levels of current consumption reduction than the SOFT WAIT mode. It suspends the
CPU operation.
Note: The output port is maintained during the HARD WAIT mode. All LCD display output pin are fixed “L”
level and voltage doubler circuit (VDB), constant voltage circuit for LCD (VEE) and voltage doubler
circuit for LCD (VLCD) are operated.
(3)
Wait mode setting
The wait status is assumed whenever the WAIT instruction is executed.
Note: The PLL OFF status will be assumed during the wait mode.
(4)
3.
Wait mode cancellation conditions
The wait mode is cancelled when the following conditions are fulfilled:
① When the input status of the HOLD pin changes.
② When the input status of the I/O port specified in the input port (P1-0~3) changes.
③ When the 2 Hz Timer F/F is set to “1” (only with the SOFT WAIT mode)
HOLD Input Port
Y1
φK17
Y2
Y4
Y8
Y1
φL39
HOLD
Y2
Y4
Y8
HOLD
PLL
OFF
control
0: Input “L” level
1: Input “H” level
0: Do not control PLL OFF with a HOLD pin
1: PLL OFF mode with “L” level of HOLD pin
The HOLD pin can be used as an input port. This bit loads data input with IN1 instruction for which
[CN = 7H] has been specified in the operand into the data memory. It is necessary to access this port prior
to the execution of the Back-up instruction when the clock stop mode or WAIT mode has been set. It is
necessary to note that there are cases when the clock stop mode will not be activated if the Back-up
instruction is executed without this port being accessed.
While HOLD PLL off control bit is set to “1”, if HOLD pin input “L” level, it will become PLL off-mode.
For this reason, a setup in PLL off-mode can be made quickly at the time of battery exchange.
The bit is accessed with the OUT3 instruction for which [CN = 9H] has been specified in the operand. All of
the reference port is “1”, it also becomes PLL off mode. (→ Refer to the reference frequency divider item)
28
2004-09-13
TC9328AF
○
Interrupt Function
The peripheral hardware which can use Interrupt function has INTR1 pin, INTR2 pin, Timer counter,
and Serial interface.
The peripheral hardware fulfill conditions, Interrupt demand signal from peripheral hardware is all
input, and Interrupt demand is transmitted. When it is received, it branches out vector address determined
by each Interrupt factor. Each Interrupt processing routine is started. The pretreatment for returning to
the same state as the time of Interrupt, before and after usually carrying out Interrupt processing, and
post-processing are required of Interrupt routine. It is necessary to perform shunting and a return for the
register data memory used by ALU to the data memory for interchange. When ending Interrupt processing,
a program is returned by the return command for Interrupt.
1. Interrupt Control Circuit
Interrupt control circuit consists of an Interrupt enable flag, an Interrupt latch, and an Interrupt priority
circuit block. This control performs setup and control by OUT2/IN2 instructions.
(1)
Interrupt enable flag
Interrupt enable flag has an individual permission flag corresponding to a master permission flag
and each Interrupt factor. An individual enable flag sets up prohibition/permission of Interrupt
corresponding to each Interrupt factor. A master enable flag is a flag for which performs
prohibition/permission of all Interrupts. If these enable register is set to “1”, it becomes permission
and is set to “0”, it becomes prohibition. An individual enable flag is accessed with OUT2/IN2
instructions for which [CN = 8H] has been specified to the operand. A master enable flag can perform
permission/prohibition by execution of an EI/DI instruction. A master enable flag is a flag which
performs prohibition/permission of all Interrupts. If these enable register is set to “1”, it becomes
enable and is set to “0”, it becomes prohibition.
In case of forbidding Interrupt in a program, it executes DI instruction, and in case of enabling, it
executes EI instruction. At this time, Interrupt is enabled during the EI instruction execution in a
program, and the DI instruction execution.
If master enable flag is received the Interrupt request, it is reset by “0” and all Interrupts will be in
a prohibition state. By executing of Interrupt return instruction, it is set to “1”. A master enable flag
is read into data memory by IN2 instruction for which [CN = 7H] has been specified.
φLK28
Y1
Y2
Y4
Y8
EF1
EF2
EF3
EF4
An individual enable flag
EF1 • • • INTR1 pin
EF2 • • • INTR2 pin
EF3 • • • Serial interface
EF4 • • • 8-bit timer counter
φK27
Y1
Y2
Y4
Y8
IMF
0
0
0
Master enable flag
“0” • • • Prohibition
“1” • • • Enable
It’s reset to “0” when it is able to receive interrupt or DI instruction execution.
It’s set to “1” by Interrupt return instruction or EI instruction execution.
29
2004-09-13
TC9328AF
(2)
φL29
Interrupt latch
If Interrupt request generates, interrupt latch is set to “1”.
If Interrupt is enabled, Interrupt reception will be required of CPU and it will branch Interrupt
routine. If Interrupt is received at this time, Interrupt latch is reset by data “0” automatically.
Interrupt latch data can read by the program and judge individual existence or nothing of interrupt
generating. By interrupt request, interrupt latch is reset from “1” from setting “0”, it is able to cancel
interrupt request or initialization.
Y1
Y2
Y4
Y8
ILR1
ILR2
ILR3
ILR4
Interrupt latch reset
φK29
If it’s set to “1”, interrupt latch is reset to “0”.
Y1
Y2
Y4
Y8
ILR1
ILR2
ILR3
ILR4
Interrupt latch data
0: No interrupt existence
1: Interrupt existence
If the interrupt request, it’s set to “1”, receiving
interrupt, It’s reset to “0”.
ILR1 • • • INTR1 pin
ILR2 • • • INTR2 pin
ILR3 • • • Serial interface
ILR4 • • • 8-bit timer counter
(3)
Interrupt priority circuit block
Interrupt priority circuit is a circuit of determined the ranking of the interrupt generating when
interrupt occurs simultaneously or interrupt permit after two or more interrupts had occurred. Vector
address to interrupt routine is also generated by this block.
Priority
Interrupt Factor
Vector Address
1
INTR1 pin
0001H
2
INTR2 pin
0002H
3
Serial interface
0003H
4
Timer counter
0004H
30
2004-09-13
TC9328AF
2. Interrupt Reception Processing
Interrupt request is maintained until it receives interrupt or reset to “0” to interrupt latch by system
reset operation or by the program. Interrupt reception operation is as shown below.
① Each peripheral hardware is output each interrupt signal and set to “1” to interrupt latch if
interrupt conditions are fulfilled.
② Interrupt latch of Interrupt factor received resets to “0” if interrupt enable flag and the master
enable flag corresponding to each Interrupt factor set to “1”
③ Interrupt master enable flag resets to “0” and interrupt is forbidden.
④ The contents of a stack pointer are -1.
⑤ The contents of program counter (PC) evacuates stack register. At this time, the contents of a
program counter become the following address, which permitted the next address or next interrupt
at the time of interrupt being received.
⑥ The contents of vector address corresponding to received interrupt transfers to program counter.
⑦ Executes the contents of vector address.
These executions ①~⑥ are executed during 1 instruction cycle. The instruction cycle is called “Interrupt
cycle”.
Note: Stack pointer is the pointer which specifies the 8-level stack register. Reference of the contents of a stack
pointer cannot be performed.
In case of Interrupt enable period
Instruction
EI
Instruc
-tion
Set “1” to
individual
enable
flag
Interrupt
cycle
IMF
(Master enable flag)
Interrupt signal
Interrupt signal
IL
(Interrupt latch)
EF
(Individual enable flag)
Interrupt enable period
One instruction cycle
Interrupt processing
routine
Interrupt reception
In case of interrupt reservation period
Instruction
Set “1” to
individual
enable
flag
EI
instruction
Interrupt
cycle
IMF
(Master enable flag)
Interrupt signal
Interrupt signal
IL
(Interrupt latch)
EF
(Individual enable flag)
Interrupt reservation period
31
Interrupt processing
routine
Interrupt reception
2004-09-13
TC9328AF
3. Return Processing from Interrupt Processing Routine
In order to make it return to processing before receiving Interrupt from Interrupt processing routine,
RNI instruction which is an exclusive command is used.
Execution of RNI instruction follows the processing automatically one by one.
① The contents of address stack, which is specified with a stack pointer, are returned to a program
counter.
② Set “1” to interrupt master enable and changes into an enable state.
③ The contents of a stack pointer are done +1.
RNI instruction of the above-mentioned processing is processed in 1 instruction cycle.
4. Interrupt Processing Routine
Interruption is received regardless of the program currently performed when an interruption request will
be done if it is the program area where interruption is enabled. Therefore, after doing interrupt processing,
when making it return to the program of a basis, it is necessary to return to the state where it is performed
by interrupt processing. For this reason, it is necessary to perform shunting and return operation within an
interruption processing routine about a register, a data memory, etc. which may be operated within an
interruption processing routine at least.
(1)
Shunting processing
In execution of shunting processing, a carry flag surely needs to be shunted. If interruption is
received during execution of arithmetic operation, the contents will change about carry flag (CY) etc.
and the program after a return will mistake judgment. For this reason, the contents of a carry flag
are shunted in a data memory at once by IN1 instruction in the data of the carry flag in I/O map.
The contents of the data memory used by the interruption processing routine and the contents of a
general register are also made to shunt if needed. Furthermore, when MVGD, MVGS or DAL
instruction is used in interrupt routine, it’s necessary to shunt the contents of G-register or DAL
address register.
(2)
Return processing
Return processing should just do opposite to the above-mentioned shunting processing.
If interrupt is received, interrupt master enable flag is reset by “0”, before receiving interrupt, an
interrupt master enable flag must have been “1”.
For this reason, RNI instruction is executed and a master enable flag is returned.
5. Multiplex Interrupt
Multiplex Interrupt is the method of processing another interrupt during interrupt processing.
As shown in the figure, another interrupt factor C or D is processed during interrupt processing to a
certain interrupt factor A and B. The depth of interrupt at this time is called interrupt level.
Main
routine
Interrupt
level 1
Interrupt
level 2
MAIN
B
D
A
B
Interrupt
level 3
Interrupt
level 4
C
D
C
The example of multiplex interrupt
32
2004-09-13
TC9328AF
Note the following points when using multiplex interrupt.
① The priority of interrupt factor
② Restriction of the address stack level used at the time of interrupt request issue
③ Shunting processing of a carry flag, a data memory, etc.
(1)
Priority of interrupt factor
The priority of multiplex interrupt is A < B < C < D in the figure. In this priority, interrupt of C
must be processed prior to interrupt of A or B even if it is under processing and even if interrupt of C
is under processing, interrupt of D must be given priority.
For example, there are interruption factors A and B, it assumed that the factor of A requests every
10 ms and the interrupt processing time is 4 ms and the factor of B requests every 2 ms and the
interrupt processing time is 1 ms. When there is no priority of A and B, if an interrupt requests of A
enters during interrupt processing of B interrupt, processing of A is done and it will stop doing
interrupt processing of B. In such a case, it is necessary to program that give the priority of A < B and
forbid interrupt of A during interrupt processing of B, and even if interrupt of B is received under
processing of interrupt of A.
When all individual enable flags is setup “1” (enable state), it becomes the priority by the hardware
explained according to the item of an interrupt priority circuit block, the priority of hardware is
changeable by operating an individual enable flag by the program.
Usually, in interrupt processing routine, received interrupt and low priority interrupt is forbidden
and high priority interrupt of Interrupt is enabled.
(2)
Restriction of address stack level
As the item of Interrupt reception processing explained, when interrupt request was done, the
return address is shunted automatically to address stack. As the register item explained, an address
stack is used also for execution of a sub routine call instruction on eight levels. For this reason, if
interrupt level and a sub routine call level exceed eight levels, it returns and the contents of an
address stack which was recorded from the first will be destroyed, it is necessary to use it so that this
may not be exceeded.
(3)
Shunting processing
When using multiplex interrupt, it is necessary to secure the shunting area of shunting processing
separately to each Interrupt factor.
33
2004-09-13
TC9328AF
○
External Interrupt and Timer Counter Function
External interrupt has two types of INTR1 pin and INTR2 pin. Interrupt request is done by the rising or
falling edge of a signal added to these pins.
Timer counter is 8-bits binary counter and has the function of timer and external clock timer. The input
of external clock timer function is used as external interrupt pin (INTR1, INTR2).
1. External Interrupt Function
External interrupt has two types of INTR1 pin and INTR2 pin and the edge of these inputs is detected
and Interrupt request is done. Input has noise cancel circuit, the frequency of 75 kHz is used for a noise
removal clock and the pulse of under this frequency is removed as a noise. IE bit is enable bit which
permits 8-bit timer counter operation or interrupt and external interrupt request. The rising or falling edge
used as input edge can choose for every pin. Usually, this bit is set “1”.
These controls are accessed with OUT2 instruction for which [CN = 7H] has been specified in the operand.
If Interrupt of INTR1 pin is received, the program will branch to 0001H address and a program will branch
to 0002H address at the time of INTR2 pin.
These pins are used as input port and the input status can read into data memory by execution of the
IN2 instruction for which [CN = 7H] has been specified in the operand.
Y1
φL27
Y2
POL1 POL2
Y4
Y8
IE
*
INTR1 INTR2
Edge select
8-bit Timer and control external interrupt
operation enable
0: Prohibition
1: Enable
Usually, the bit is set to “1”.
Reduce less than 13.3 µs pulse
More than 40 µs regards as a signal
certainly.)。
1: Rising edge
0: Falling edge
Note: The edge of the external clock of timer counter is also controlled. The Timer counter input is
not used the function of noise cancel function. For this reason, even if external Interrupt
does not occur, it is 40 (since the clock pulse of under s is inputted into counter, cautions
are required.).
Select edge of timer counter
Y1
φK27
Y2
Y4
Y8
INTR1
INTR2
0
The each input state
1: Count by rising edge
0: Count by falling edge
0: Input “L” level
1: Input “H” level
Note: Interrupt request may be transmitted if edge is changed by POL bits. For this reason, when changing
edge, it changes after forbidding Interrupt, and Interrupt latch is reset, and it returns to usual operation.
34
2004-09-13
TC9328AF
2. Timer Counter Function
Timer counter are consists of 8-bit binary counter, counter coincidence register, digital comparator and
controlled the control circuit.
If timer counter is coincided with the contents of counter coincidence register, timer counter is outputted
a coincidence signal pulse and interrupt request is done by inputting timer clock to 8-bit binary counter
timer clock. Reset of Timer counter is possible with a coincidence pulse and a program, and it can perform
enable and prohibition of reset by the coincidence pulse. As a clock of timer, it can be selected INTR1/2
input and an instruction cycle and 1 kHz.
(1)
φL2A
Timer counter register configuration
The register of timer counter consists of counter data, coincidence register and control register.
Y1
Y2
Y4
Y8
ID0
ID1
ID2
ID3
φL2B
Y1
Y2
Y4
Y8
ID4
ID5
ID6
ID7
Timer counter coincidence data
φK2A
Y1
Y2
Y4
Y8
ID0
ID1
ID2
ID3
φK2B
Y1
Y2
Y4
Y8
ID4
ID5
ID6
ID7
Timer counter data
φL2C
Y1
Y2
Y4
Y8
CK0
CK1
GT
CR
Select timer clock
A coincidence pulse will be output in accordance with
timer counter.
Timer counter data is read into data memory as a
binary data.
Timer counter reset • • • “Whenever sets “1”, counter is reset.
Enable counter reset by coincidence pulse.
CK0
CK1
0
0
INTR1 pin input
0
1
INTR2 pin input
1
0
Instruction cycle clock (40 µs)
1
1
1 kHz
0: Enable
1: Prohibition
Timer clock
Select clock edge by POL bit
0: Count by raising edge
1: Count by falling edge
Note: It’s necessary to set “1” to IE bit when it uses timer counter.
35
2004-09-13
TC9328AF
(2)
Timer mode
Timer mode is detected fixed time. Interrupt request is done and reset to counter whenever it
detects fixed time. At this time, control bit is set to 1 kHz or an instruction as timer clock, “0” to GT
bit and “0” (it does not reset) to CR bit.
Timer coincidence data is
Timer time = IDn (coincidence data) × Timer clock cycle
It sets up the data which corresponding to time.
In addition, although an external pin can be used for Timer clock, a clock frequency should use the
frequency below 25 kHz. If GT bit is setup “1”, it can also be integrated of an external clock.
It is used by inputting more than 40 µs cycle at the time of an external clock input.
Timer clock
Timer data
IDn
00H
01H
02H
03H
ID (n − 1)
IDn
00H
01H
02H
03H
Coincidence pulse
Coincidence pulse
Request for interrupt and
reset timer counter.
36
2004-09-13
TC9328AF
○
Internal Interrupt and Interrupt Function
Interrupt has two types of timer counter and serial interface.
1. Interrupt of Timer Counter
If timer counter value is the same as coincidence register value, interrupt of timer counter is transmitted
interruption. Refer to the item of timer counter function for details.
2. Interrupt of Serial Interface
Interrupt of serial interface is transmitted interruption at the time of finishing operation of serial
interface. Refer to the item of serial interface function for details.
3. Interruption Block Configuration
Serial interface interrupt
75 kHz
ILR1
INTR1 43
ILR1
ILR1
Noise canceller
POL1
INTR2 44
S
INTR2
INTR1
R
S
IL1
Noise canceller
1 kHz
Instruction cycle clock
CK0
CK1
ILR1
EF1
POL2
R
S
IL2
R
IL3
EF2
S
R
IL4
EF3
EF4
Decoder
Priority determination • Vector address generate circuit
La
Interrupt
receiving
signal
Selector
CT0~CT7
CR
EI instruction
S
Vector
address
IMF
R
8-bit binary counter R
DI instruction
Coincidence pulse
RNI instruction
Coincidence register (ID0~ID7)
GT
37
2004-09-13
TC9328AF
○
Programmable Counter
The programmable counter consists of two modulus prescaller, a 4-bit + 13-bit programmable counter and
a port to control these elements.
The programmable counter controls the ON/OFF functions for the contents of the reference port and
HOLD input status. By using external prescaller (TD6134AF/TD7101/04F) or 1 chip tuner IC that is
built-in for 1/16 prescaller (TA2142FN), it’s possible to reduce the emission from the tuner portion and
consumption current.
1. Programmable Counter Control Port
This port is controlling for division frequency, division method and operating current and gain of
prescaller.
φL10
Y1
Y2
Y4
Y8
HF
PW0
PW1
FM
Power control
Division method setting
φL11
φL12
φL13
φL14
Y1
Y2
Y4
Y8
Y1
Y2
Y4
Y8
Y1
Y2
Y4
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10 P11
LSB
Y8
Y1
φL15
Y2
Y4
Y8
P12 P13 P14 P15
A setup of the number of division of programmable counter
Y1
Y2
Y4
Y8
P16
MSB
The division method and power control of prescaller are accessed with the OUT1 instruction for which
[CN = 0H] has been specified in the operand.
The division frequency setting is accessed with the OUT1 instruction for which [CN = 1~5H] has been
specified and setting is by writing in the P16 bit (φL15). All data between P0 to P16 are updated when P16
is set. It is therefore necessary to access P16 even when updating only certain items of data and to perform
setting as the final process.
Y1
φL39
Y2
Y4
Y8
Prescaller
PSC
ENA
IN
PSC output permission setup
0: PSC output prohibition
1: PSC output permission
Prescaller IF counter input setup
0: Regular PLL composition
1: Prescaller division output is inputted to IF counter.
PSC output permission setup is used at the time of connection of external prescaller.
In the setup to prescaller IF input, if the bit is set to “1”, a programmable counter stops and prescaller
1/15 and 16 are fixed to 16 division. Usually, consisting of PLL, the bit is set to “0”.
(→ Refer IF counter item)
38
2004-09-13
TC9328AF
2. Division Method Setting
The pulse swallow method or direct method are selected with the HF and FM bit.
The power control bits (PW0/1) are controlled the gain of amplifier and prescaller (1/2 + 1/15•16).
Although the power bit in each mode has five methods, set up it as shown in the table.
By using 1 chip tuner IC that is built-in for 1/16 prescaller (TA2142FN), set up to the LF mode and set
the division value after 1/16 division frequency.
Mode
HF
PW0
PW1
FM
Division Method
Example of
Receiving Band
Operation
Frequency Range
LF
0
1
0
0
Direct division method
MW/LW
0.5~8 MHz
HF1
1
1
0
0
Pulse swallow method
(1/15•16)
HF2
1
0
1
0
FM
1
1
0
1
VHF
1
0
1
1
3~30 MHz
SW
Input Pin
Division
Number
(Note)
AMin
n
FMin
2•n
1~10 MHz
FM
Pulse swallow method
30~130 MHz
TV
(1/2 + 1/15•16)
50~230 MHz
(1 ch~12 ch)
Note: “n” represents the number of divisions programmed.
Note: It may not operate normally with abnormal current dissipation or unlocked PLL etc.
3. Frequency Division Number Setting
The frequency division number for the programmable counter is set in bits P0 to P16 in binary.
• Pulse swallow method (17 bits)
MSB
LSB
P16 P15 P14 P13 P12 P11 P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
16
2
The range of frequency division number setting (n = 210H~1FFFFH (528~131071))
P0
2
0
• Direct division method (13 bits)
MSB
LSB
P16 P15 P14 P13 P12 P11 P10
P9
P8
P7
P6
12
P5
P4
P3
P2
P1
P0
0
2
2
The range of frequency division number setting (n = 10H~1FFFH (16~8191))
39
Don’t care
2004-09-13
TC9328AF
4. PSC Output Permission Setting
In case of using the external pre-sccaler (TD6134AF/TD7101/04F), PSC output permission bit is setup to
“1”. At this time, a swallow counter will be operating and prescaller will be in a stop state, and PSC output
is outputted P2-3 pin. A division method is set as LF mode, and AM VCO input and an external prescaller
output are changed and inputted into AMin input pin. P2-3 pin is used by setting it as an output port.
TC9328AF
TD6134AF
PSC 35
AMin 49
7 PSC
0.01 µF
5 OUT
0.001 µF
0.001 µF
AM VCO
2 FMin
3 VHFin
FM/TV VCO
The example of an external prescaller connection circuit
5. Programmable Counter Circuit Configuration
• Pulse swallow method circuit configuration
This circuit consists of amplifier, 1/2 prescaller, two 1/15•16 modulus prescallers, the 4-bit swallow
counter and a 13-bit binary programmable counter. A 1/2 frequency divider is added to the front stage of
the prescaller in the VHF/FM mode.
P0~P3
PW0/1
FMin
0.01 µF
48
AMin
0.01 µF
4-bit
swallow counter
1/16
Amplifier
1/2
1/15•16
1/15
Pre-set
13-bit
programmable counter
49
To the phase
comparator
P4~P16
40
2004-09-13
TC9328AF
• Direct division method circuit configuration
The prescaller is not required if this is selected, and instead, the13-bit programmable counter is used.
Pre-set
PW0/1
Amplifier
AMin 49
13-bit
programmable counter
To the phase comparator
P4~P16
Note: FMin and AMin contain the amplifier, and small-size width operation can be performed by connecting
them to a capacitor. In the division method, when non-selected input pins are in PLL off mode, the input
becomes high impedance. Therefore FMin and AMin can be used as wired-OR configuration as shown
below.
Note: If it becomes PLL off-mode, all programmable counter parts will be stopped. The contents of each control
port are held at this time.
FM/TV VCO
AM VCO
0.001 µF
0.001 µF
AM/FM/TV
VCO
48 FMin
49 AMin
0.001 µF
48 FMin
49 AMin
The example of connection circuit using VSO for
each FM and AM band
The example of connection circuit using VSO with
FM and AM bands
41
2004-09-13
TC9328AF
○
Reference Frequency Divider
The reference frequency divider divides the oscillation frequency of the external 75-kHz crystal and
generates the following seven types of PLL reference frequency signals; 1 kHz, 3 kHz, 3.125 kHz, 5 kHz,
6.25 kHz, 12.5 kHz and 25 kHz. These signals are selected with reference port data.
The selected signal is supplied as a reference frequency for the phase comparator as described below. Also,
the PLL is switched on and off with the contents of the reference port.
1. Reference Port
The reference port is an internal port for selecting the seven reference frequency signals. This port is
accessed with the OUT1 instruction for which [CN = 5H] has been specified in the operand (φL15).
Operations for the programmable counter, the If counter, reference counter and the phase comparator are
suspended and the PLL assumes the off mode when the contents of the reference port are all “1”. As the
frequency division setting data for the programmable counter is updated when the reference port is set, it
is necessary to set the frequency division number of the programmable counter prior to setting the
reference port.
φL15
Y1
Y2
Y4
R0
R1
R2
Y8
Reference frequency selection code
42
R2
R1
R0
0
0
0
0
1 kHz
0
0
1
1
3 kHz
0
1
0
2
3.125 kHz
0
1
1
3
5 kHz
1
0
0
4
6.25 kHz
1
0
1
5
12.5 kHz
1
1
0
6
25 kHz
1
1
1
7
PLL off mode
Reference Frequency
2004-09-13
TC9328AF
○
Phase Comparator and Lock Detection Port
The phase comparator compares the difference in phasing between the reference frequency signal
supplied from the reference frequency divider and frequency division output of the programmable counter
and outputs the result. Then it controls the VCO (Voltage control oscillator) via a low pass filter in order to
ensure that the two frequency signals and the phase difference match.
Two tristate buffer DO1 and DO2 are outputted in parallel from the phase comparator, the filter constant
can be designed for each VHF and AM bands. A charge pump output uses constant voltage Vreg potential
(1.5 V) so that a stabilized phase comparison machine can be used when VDD potential is 0.9 V.
Also DO2 pin can be used with DO2 control port as general-purpose output port and charge pump signal
(P, N) can be outputted from DO1 and DO2 pins. Therefore it is possible to use an external charge pump.
1. DO1 control Port and the Unlock Detection Port
Y1
φL19
UNLOCK
RESET
Y2
Y4
Y8
DO2 control
PN
M0
PN
M1
M0
0
0
0
DO output
0
0
1
“L” level
0
1
0
“H” level
0
1
1
“HZ”
1
*
*
N output
M1
DO2 output setting
PN output setting
DO2 Output Status DO1 Output Status
DO output
P output
Unlock F/F and unlock enable are reset whenever the data is set to “1”.
Y1
φK19
Y2
Y4
Y8
UNLOCK
F/F
ENA
Unlock enable
0: PLL unlock detection stand-by
1: PLL unlock detection enabled
Unlock detection bit
0: PLL lock status
1: PLL unlock status
M0 and M1 bit of DO2 control ports perform a general-purpose output port setup of DO2 output, and a
setup of high impedance. PN bit performs control setup of an external charge pump for DO1/2 pins as P/N
output.
Unlock F/F detects the phase difference of a programmable counter division output and reference
frequency to the timing from which about 180 degrees of phases shifted. When a phase does not suit at this
time (that is unlock status), unlock F/F is set. The unlock F/F status is reset whenever the UNLOCK
RESET bit is set to “1”.
It is necessary to access to UNLOCK F/F after establishing more time than is required for the reference
frequency cycle after the unlock F/F has been reset in order to detect the phase difference with the
reference frequency cycle. It is for this purpose that the enable bit has been made available, but the unlock
F/F must not be accessed before it has been confirmed that the unlock enable has been set at “1”.
Note: When P/N output and DO output are set up in PLL off-mode state, these outputs are high impedance.
This state is held when PLL off-mode or clock stop mode is set up at outputting “L” or “H” level of DO2
pin.
Note: When PN output is setup, “H” level of DO1/2 pin is output as VDD level and Vreg potential (1.5 V) is
output as “H” level for other settings.
43
2004-09-13
TC9328AF
2. Phase Comparator and Unlock Port timing
Reference frequency
Programmable
counter output
High impedance
“H” level (Vreg)
DO output
“L” level (GND)
Phase difference
Lock detection
strobe
Unlock reset
execution
Unlock F/F
When PN = “1” is set up
Unlock enable
P output
(DO1 pin)
“H” level (VDD)
N output
(DO2 pin)
“H” level (VDD)
“L” level (GND)
“L” level (GND)
3. Phase Comparator and the Unlock Port Circuit Configuration
Vreg
Reference
frequency
32 DO1/P
Decoder
Phase comparator
Programmable
counter output
PN bit
Vreg
UNLOCK
ENABLE
UNLOCK
F/F
UNLOCK
RESET
Decoder
31 DO2/OT/N
M1, M0, PN bit
VDB
(VDD × 2 doubler
power supply)
PNvoltage
bit
Constant
circuit
33 Vreg
PN bit
Note: When PLL is off mode and PN bit is set to “1”, Vreg pin becomes VDD level.
44
2004-09-13
TC9328AF
C1 R2
DO1/P 32
FM/VHF
VCO
R1
DO1/P 32
R1
C2 R4
R3
AM
VCO
Vreg 33
R2
VCO
LPF
0.47 µF (typ.)
LPF
DO2/OT/N 31
Vreg 33
When filter constant is set up for
each band
0.47 µF (typ.)
DO2/OT/N 31
C1 R3
When LPF is used in common
(Set DO2 as high impedance and switch
the filter constant)
DC-DC
converter
DO1/P 32
10 kΩ
DO2/OT/N 31
0.01 µF
1 µF
4.7 kΩ
4.7 kΩ
32 DO1/P
0.1 µF
To the VCO
variable
capacitor
To the VCO
variable
capacitor
Vreg 33
0.47 µF (typ.)
100 kΩ
DC-DC
converter
Example of external charge pump
circuit (when PN = “1” is set up)
Example of an active low pass filter
circuit (for reference)
Note: The filter circuits illustrated in the above diagrams are for reference purposes only. It is necessary to
examine the system band configuration and characteristic and design actual circuits in accordance with
requirements.
45
2004-09-13
TC9328AF
○
IF Counter
The IF counter is 20-bit general-purpose IF counter that calculates FM and AM intermediate frequencies
(IF) during auto-tuning and can be used for detecting auto-stop signals, etc. VCO of an analog tuner is
measured and detection of received frequency and detection of CR oscillation frequency can be performed.
1. IF Counter Control Port and Data Port
φL16
Y1
Y2
Y4
Y8
IF1/ 2
PW
IF1/IN1
IF2/IN2
0: Set input port
1: Set IF input port
Selection of IF input
/Input port
Set IF amplifier gain → set up “0”
0: Set IFin2 input
1: Set IFin1 input
Selection IF input
Note: At the time of an input port setup, the pin becomes CMOS input type and be able to detect frequency by
IF counter.
φL17
Y1
Y2
Y4
Y8
STA/ STP
MANUAL
G0
G1
Selection of the gate time for frequency
measurements (measurement time)
G1
G0
Gate Time
0
0
1 ms
0
1
4 ms
1
0
16 ms
1
1
64 ms
Selection of frequency measurements automatic/manual mode switching bit
0: Automatic mode (measurement is performed with the
above-mentioned gate time)
1: Manual mode (Starts/stops measurements with
the STA/ STP bits)
IF counter start/stop control bit
0: Counter stop
1: Counter start
Y1
φL39
Y2
Y4
IF
counter
Split
Prescaller
IN
Y8
FMin/AMin prescaller input setup at IF counter
0: Set IFin pin input
1: Set FMin/AMin pin input
IF counter division operation setup
0: IF counter 20-bit operation
1: Inputs into 8 bits of IF counter higher ranks from INTR2 pin.
Note: When a prescaller input is set as IF counter input, at the time of a setup of a pulse-swallow system,
pre-scsler; 1/15•16 are fixed to 16 division, and this frequency is inputted into IF counter.
Note: When a division operation setup of the IF counter is carried out, the counter of 8 bits of higher ranks is
inputted from INTR2 pin. However, only 8 bits of this higher rank cannot perform a gate setup by the auto
mode. Reset of this counter is reset by setting up “1” to STA/ STP bit.
46
2004-09-13
TC9328AF
φK10
Y1
Y2
Y4
Y8
BUSY
MANUAL
OVER
0
20
0: IF counter calculation value <
=2 −1
20
1: IF counter calculation value >
= 2 (overflow status)
Overflow detection
0: IF counter automatic mode
1: IF counter manual mode
Operation mode
0: IF counter calculation ended
1: IF counter calculation in progress
Operation monitor
φK11
φK12
φK13
φK14
Y1
Y2
Y4
Y8
Y1
Y2
Y4
Y8
Y1
Y2
Y4
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10 F11
Y8
Y1
φK15
Y2
Y4
Y8
F12 F13 F14 F15
20
Y1
Y2
Y4
Y8
F16 F17 F18 F19
219
LSB
IF counter data
MSB
Note: When it is set as IF input, in PLL off-mode, IF input amplifier is turned off in PLL-off mode. In using IF
counter in PLL off-mode, it sets it as an input port (CMOS input).
Note: The input amplifier un-chosen by IF1/2 bit. If input amplifier turns off, this input will serve as high
impedance.
(1)
IF counter automatic mode
A setup in the auto mode of IF counter is set “0” to MANUAL bit and gate time is set up according
to the frequency band to measure. If the STA/ STP is set “1”, operation of IF counter will be started
and the set-up clock in gate time will be inputted, and this number of input pulses is counted and it
ends. An end of the calculation of IF counter can be judged by referring to BUSY bit. When more 220
pulses are inputted for a total numerical value, OVER bit is set to “1”. BUSY bit and OVER bit are
judged “0” and the frequency inputted can be measured by taking in IF data of F0-F19.
(2)
IF counter manual mode
By internal time base (10 Hz etc.), it is used when gate time is controlled and it measures frequency.
The manual mode is set “1” to MANUAL bit. At this time, a gate time setup serves as don't care. In
STA/ STP bit is set to “1”, it starts calculation. In STA/ STP bit is set to “0”, it will end and
calculation will take in data by the binary.
(3)
An input setup and division setup of IF counter
Usually, intermediate frequency (IF) Measurement is inputted into IFin1 or IFin2 pin input, and
measures this frequency. These pins contain input amplifier and small-size width operation is
possible. In addition, the following setup is possible to the input to IF counter, and use it for it
according to specification.
IF1/ 2
IF1/IN1
IF2/IN2
IF
counter
Split
Prescaller
IN
1
0
*
0
0
IFin1 input (Amplifier operation)
1
1
*
0
0
IN1 (IFin1) input (CMOS input)
0
*
0
0
0
IFin2 input (Amplifier operation)
0
*
1
0
0
IN2 (IFin2) input (CMOS input)
IF Input Setup
VHF mode
FMin input (32-divided frequency)
(Note)
HF1/2 mode
AMin input (16-divided frequency)
(Note)
LF mode
AMin input (inputted frequency)
(Note)
FM mode
*
*
*
*
*
*
0
1
1
*
Only 8 bits of higher ranks are inputted from INTR2 pin.
Note: Refer to the programmable counter item for the input frequency range at the time of prescaller input setup.
47
2004-09-13
TC9328AF
2. IF Counter Circuit Configuration
The IF counter consists of the input amplifier, the gate time control circuit and the 12 + 8 bits binary
counter.
The clock of FMin/AMin prescaller and can be inputted as an IF counter.
PW0/1
FMin
0.001 µF
amplifier
1/2
48
To programmable counter
1/15•16
AMin
0.001 µF
PSC
49
Prescaller
IN
PW
IF1/IN1
IFin1
0.001 µF
45
Prescaller IN
IF counter
Split
F0~F11
F12~F19
OVER
8-bit binary counter
OVER
IF2/IN2
IFin2
0.001 µF
12-bit binary counter
46
Gate
IF1/ 2
IN2 IN1
1 kHz
Gate time
control circuit
Manual
G0
G1
STA/ STP
INTR2
44
Note: All the binary counters of IF counter operate in a standup.
Note: At inputting IF counter, dividing frequency of prescaller 1/15, 16 is fixed to 1/16. 1/32 for FMin input, and
1/16 or the direct input for AMin are enabled.
IF counter input
“1”
Data set to STA/ STP bit
BUSY bit
1 kHz
Gate
Binary counter input
The example of IF counter auto mode operation timing
48
2004-09-13
TC9328AF
○
LCD Driver
The LCD driver uses the 1/4 duty and 1/2 bias drive method (62.5-Hz frame frequency).
The common output outputs the VLCD, VLCD/2 (VEE) and the GND electrical potential, and the segment
output outputs the VLCD and GND electrical potential.
A combination of four common outputs and 22 segment outputs enables a maximum of 88 segments to be
illuminated. The S15 to S22 pin for LCD driver are also used as the I/O port, after system reset is set as an
I/O Port, and can perform a change of an I/O Port and a segment output per 1 bit. All LCD output pins
(COM1-S14) can be changed to an output port. The LCD driver is built-in a constant voltage circuit (VEE =
1.5 V) for display purposes and a voltage doubler circuit (VLCD = 3.0 V), The constant voltage circuit for
display (VEE) is used as for twice doubler voltage (VDB) is used. For this reason, LCD display stabilized
even if power supply voltage was set to 0.9 V is possible.
1. LCD Driver Port
φL2D
Y1
Y2
Y4
Y8
SEL1
SEL2
SEL4
SEL8
Data select
Segment-1 data
Y1
φL2E
Y2
Y4
Segment-2 data
Y8
Y1 COM2
Y2 COM3
Y4 COM4
Y8
COM1
Y1
Y2
Y4
Y8
0
S1
1
Y1
φL2F
S2
2
Y2
1
S3
Y8
S18
2
Segment data
0: Illuminated
1: Extinguished
S19
COM1 COM2 COM3 COM4
F
Y4
Y1 COM2
Y2 COM3
Y4 COM4
Y8
COM1
Y1
Y2
Y4
Y8
0
S17
COM1 COM2 COM3 COM4
S16
5
Change for segment and I/O port
6
0: I/O port
1: Segment output
7
Y1
Y2S22
Y4
Y8
S15
S16
S17
S18
Y1Segment
Y2 /IO select
Y4
Y8
S19
S22
S20
S21
Segment /IO select
LCD display off control bit
0: All LCD display illuminated
1: All LCD display extinguished
F
DISP
OFF
LCD
OFF
OTB
-UP
*
LCD off control bit
0: LCD output setting
1: Output port setting
Buffer capacity bit of output port (OT)
0: Low output buffer
1: High output buffer
Note: It is available only when output port is set. When
LCD is output, low buffer output is available.
Note: When “1” is set at DISP OFF bit, common output becomes VEE level and all displays are turned off.
Different from the situation in which all segment data is set to “0” at display status, the contrast slightly
becomes bad. If extinguished status by DISP OFF bit is not favorable, set “0” to DISP OFF bit and all
segment data, or set “1” to LCD bit and output “L” level at output port.
Note: Segment data controls lighting/putting out lights of the segment corresponding to a common output and a
segment output.
Note: At the time of clock stop mode and about 100 ms after system reset, all the common output and segment
output are fixed at “L” level.
49
2004-09-13
TC9328AF
The LCD driver control port consists of the segment data selection port and the segment data port. These
ports are accessed with OUT2 instruction for which [CN = DH~FH] has been specified in the operand. The
segment data for LCD driver is set with the segment data ports (φL2E, φL2F). The LCD display will be
extinguished when the segment data port is set at “0”, and will be illuminated when set at “1”. Also, the
segment-2 data (φL2FF) specified with FH in the segment selection port becomes the DISP OFF bit and
LCD OFF bit without setting the segment data.
It is possible to extinguish all LCD display with DISP OFF bit without setting the segment data. In this
bit, if “1” is set, a common output and non selection wave form (fixed at VEE level) and LCD display all
puts out the light. In that time, segment data is held and if DISP OFF bit is set “0”, former display is stilled
display on LCD. In addition, rewriting of segment data is possible during DISP OFF. Moreover, after reset
and CKSTP instruction execution, DISP off-bit is set to “1”.
LCD OFF-bit can set all LCD output pins as an output port. In LCD display, this bit is set “0”.
(→ Refer to output port item)
S15 to S22 pin is used as I/O Port. This control is done at segment I/O port select port (φL2F6, φL2F7).
If the port is set “1”, it will become segment output port and set “0”, It will become an I/O Port.
(→ Refer to output port item)
These data is divided and undirected setting by data selects port (φL2D). Set the data of a specification port
of a segment data port in advance and access data port corresponding to it. A data select port is +1
increment whenever accessing data port (φL2E, φL2F). For this reason, after setting up a data selection
port, it can set up continuously.
Note: The data select port is +1 increment automatically by accessing φL2E, φL2F, φL3B, φK3B on I/O map.
DISP OFF
COM1/OT1
COM2/OT2
COM3/OT3
COM4/OT4
S1/OT5
S2/OT6
S3/OT7
S14/OT18
P8-0/S15
P8-1/S16
P9-2/S21
P9-3/S22
2. LCD Driver Circuit Configuration
1
2
3
4
5
6
7
18
19
20
25
26
Segment driver
Common output
circuit
500 Hz
Segment data
I/O-8•9 Port
VLCD OFF
77
78
79
0.1 µF
75 kHz/2
VLCD
C4
C3
VEE
VDB
74
Voltage doubler
circuit (VEE × 2)
80
0.1 µF
0.1 µF
Constant voltage
circuit
(VEE = 1.5 V)
0.47 µF
72
10 µF
76
0.1 µF
To A/D converter
Constant voltage
circuit (Vreg)
C1
VDD
Power supply voltage
Double voltage circuit
(VDD × 2)
C2
75 kHz/2
Note: In case of setting I/O port, this output port is Nch open drain.
Note: In case of setting segment output as output port in setup “1” to VLCD OFF bit, “H” level of all output
becomes VLCD potential output. When “H” output is made into VDD remove the capacitor between C3/C4,
and connect VLCD and VDD.
Note: During the clock stop mode and reset, the potential of VLCD/VEE/VDB becomes as VDD level.
50
2004-09-13
TC9328AF
The example of segment data
COM1
Segment data -1 (φL2E)
Y1
COM2
0
(S1)
COM3
S1
Y2
Y4
Y8
COM1 COM2 COM3 COM4
1
0
1
0
Y1
Y2
Y4
Y8
COM4
1
S2
(S2)
COM1 COM2 COM3 COM4
1
1
0
1
Segment data selection (φL2D)
DISP OFF
16 ms (62.5 Hz)
2 ms
VLCD
COM1
VEE
GND
VLCD
COM2
VEE
GND
VLCD
COM3
VEE
GND
VLCD
COM4
VEE
GND
VLCD
S1
GND
VLCD
S2
GND
VLCD
COM1-S1
(ON waveform)
GND
−VLCD
VLCD
COM2-S1
(OFF waveform)
GND
−VLCD
The potential of LCD driver waveform outputs the potential of VLCD and GND, and the middle potential
level.
51
2004-09-13
TC9328AF
○
Serial Interface
The serial interface is the serial I/O port which transmits and receives 4 bits or 8 bits data synchronizing
with the internal or external serial clock. SI, SO and SCK pins perform the transmission and reception
with LSI for extension and a microcomputer, etc. When a serial interface operation is finished, interruption
is occurred.
1. The Serial Interface’s Control Port and Data Port
Y1
φL22
edge
Y2
Y4
Y8
SCK-INV SCK - I/ O SIO-ON
Selection of the I/O port-4 and serial interface
0: I/O port-4 selection (P4-1~P4-3)
1: Serial interface function selection
SCK clock external/internal selection
0: External clock output
1: Internal clock output
Inversion of the SCK Clock signal
0: SCK clock output from “H” level
1: SCK clock output from “L” level
Edge selection of serial data shift operation
0: Shift at the SCK rising edge
1: Shift at the SCK falling edge
φL23
Y1
Y2
Y4
Y8
STA
SO - I/ O
8/4 bit
*
Selection of the data length of serial data
0: 4-bit data
1: 8-bit data
Selection of input and output of SO pin
0: SO output
1: SI input
Serial operation start and internal port reset
0: don’t care
1: Reset COUNT, SIO F/F and the serial output data in
the shift register. Serial operation is started when the
internal SCK clock is selected.
52
2004-09-13
TC9328AF
φL24
Y1
Y2
Y4
Y8
SO0
SO1
SO2
SO3
φL25
Y1
Y2
Y4
Y8
SO4
SO5
SO6
SO7
Serial output data: The data set in these ports is output in the serial format
φK24
Y1
Y2
Y4
Y8
SI0
SI1
SI2
SI3
φK25
Y1
Y2
Y4
Y8
SI4
SI5
SI6
SI7
Serial input data: It is possible to load data input in the serial format into data memory
Note: At serial data input, the contents of shift register are accessed as they are.
Y1
φK23
Y2
BUSY COUNT
Y4
Y8
SIO
F/F
0
SIO start flag
0: SIO operations performed
1: SIO operations not performed
SCK clock count detection
0: Clock count normal (SCK clock count is in multiple of four)
1: Clock count abnormal (SCK clock count is not in multiple of four)
SIO operation monitor
0: SIO operations ended
1: SIO operation in progress
Serial interface control and data are accessed with the OUT2 an IN2 instruction for which [CN = 2H~5H]
has been specified in the operand.
The serial interface pin is used together with the I/O-4 P4-1, P4-2, P4-3 pins, and each of the I/O port-4
pins are switched across to the SI, SO and SCK pins by setting “1” in the SIO ON bit.
Note: All the inputs of a serial interface build in the Schmidt circuit.
Note: Since SI (P4-1) pin can be used as an I/O Port even when a serial interface is chosen, it can be used for
the strike robe signal of SIO etc.
In case of using this pin as a serial input, change into an input state for I/O control bit of P4-1.
53
2004-09-13
TC9328AF
(1)
edge, SCK-INV, SCK-I/O bit
The edge bit setups the edge of a shift and the SCK-INV bit sets up the input-and-output waveform
of a shift clock. If the edge bit is set “0”, (SCK) shift operation is done at rising edge and set “1”, (SCK)
Shift operation is done at falling edge. SCK-INV bit sets the bit of serial clock output from “H” or L”.
In case of setting “0”, it starts shift operation from “H” output, and setting “1”, it starts shift operation
from “L” output. These bits perform serial operation as shown in the following table by setup. Set up
by the serial format to control.
SCK-I/O bit setups the input-output of serial clock. Usually, when this product is used as a master,
set “1” to SCK-I/O bit and then it used as serial clock output and in the case of a slave, set to “0” and
then it used as serial input.
SCK-INV = 0
SCK INV = 1
STA bit set as “1”
STA bit set as “1”
1
edge = 0
SCK pin
SO pin
2
SO0
SO1
SI0
SI pin
3
4
SO2
SI1
SO3
SI3
SI2
BUSY
SCK pin
edge = 1
2
SI pin
BUSY
SI0
SO0
SO1
SO2
SO3
SI pin
SI0
SI1
SI2
SI3
Interrupt
SCK pin
4
SO1
SI1
4
STA bit set as “1”
3
SO0
SO pin
3
BUSY
Interrupt
1
2
SO pin
STA bit set as “1”
SCK pin
1
SO2
SI2
SO3
SO pin
SI pin
SI3
BUSY
Interrupt
54
1
2
SO0
3
SO1
SI0
4
SO2
SI1
SO3
SI2
SI3
Interrupt
2004-09-13
TC9328AF
(2)
8/4 bit
The 8/4 bit selects the length of the serial data. The length of the serial data is set at 4 bits when
this bit is “0”, and at 8 bits when this bit is “1”. If SIO is started when a serial clock is set as an
internal clock, a clock (4 bits or 8 bits) will be continuously outputted by the state of this bit.
STA bit set as “1”
SCK pin
1
2
SO pin
3
SO0
SI pin
4
SO1
SI0
5
SO2
SI1
6
SO3
SI2
SI3
7
SO4
SI4
8
SO5
SI5
SO6
SI6
BUSY
SO7
SI7
Interrupt
The example of serial operation at the time of setting it as 8 bits
(3)
SO - I/ O bit
The bit sets the serial I/O for the SO pin.
The SO pin outputs serial data when the bit is set at “0”, and the SO pin is used for serial data
input when this bit is set at “1”. This control is used as the serial bus system which outputs and
inputs serial data with one pin.
Changing edge
SCK pin
SO pin
1
2
SO0
Set STA bit to “1”
Set SO-I/O bit to “0”
3
SO1
4
SO2
1
SO3
(Note)
SI0
2
SI1
3
SI2
4
SI3
Set STA bit to “1”
Set SO-I/O bit to “1”
Example for Serial input-output operation
Note: Usually insert pull-up or pull-down in SO pin to prevent floating.
(4)
Serial interface operation monitor
The operational status of the serial interface is determined by referring to the BUSY, COUNT, SIO
F/F bits.
As the BUSY bit becomes “1” during SIO operations, control data switching and serial data access
are performed when the BUSY bit is “0”. It interrupts in falling of BUSY bit and a demand is
transmitted.
COUNT bit determines if the data sending/receiving has been performed per 4 bits. When shift
operation performs with the four multiple, “0” is outputted. When it performs without the four
multiple, “1” is outputted.
“1” is set in the SIO F/F bit when the SCK pin starts shift operations.
Both COUNT bit and SIO F/F bits are reset to “0” when “1” is set in the STA bit. These two bits are
mainly used when the SCK pin sets external clocks (slave mode). An external clock is inputted and it
can be judged to be the information that serial data was transmitted and received whether operation
was performed normally.
Usually, since interruption is transmitted, interruption processing performs a serial interface end.
55
2004-09-13
TC9328AF
(5)
STA bit
STA bit is a bit of starting serial interface operation. Serial operation is started whenever STA bit
sets “1”. If STA bit setups “1”, serial output data will be transferred to a shift register, and COUNT bit
and SIO F/F bit will be reset. When SCK clock is made an internal setup, a serial clock is outputted,
and when an external setup of the SCK clock is carried out, it will be in the state waiting for a serial
clock input.
56
2004-09-13
TC9328AF
2. Configuration of the Serial Interface
STA
SCK - I/ O
Interrupt requirement
SCK-INV
COUNT
Control circuit
BUSY
39 SCK (P4-3)
SIO F/F
SO - I/ O
edge
38 SO (P4-2)
8/ 4 bit
4-bit shift register
4-bit shift register
SO0 SO1 SO2 SO3
SO4 SO5 SO6 SO7
-3
Serial output data
SI0~SI3
37 SI (P4-1)
SI4~SI7
-2
-1
-0
I/O port-4
I/O control data
Serial input data
-3
-2
-1
-0
I/O port-4 data
The serial interface consists of a control circuit, a shift register, and an I/O Port.
Note: SI pin can be used as I/O Port -4 (P4-1).
Note: As for data and serial input data, the contents of a shift register are taken in by the data memory.
For this reason, the contents of the data set to serial output data and serial input data are not in
agreement.
Note: All serial input pins are the Schmitt input type.
57
2004-09-13
TC9328AF
3. Serial Interface Timing
The clock frequency outputted from SCK pin when SCK clock is set as an internal clock is 37.5 kHz (Duty.
= 50%). When SCK clock is considered as an external input, the clock of a maximum of 200 kHz can be
inputted.
At external clock: Tcyc = 5 µs min, Th = 2.5 µs min, TPLH/TPLL = 2 µs max
At internal clock: Tcyc = 26.6 µs typ., Th = 13.3 µs typ., TPLH/TPLL = 2 µs max
Tcyc
Th
SCK pin
At internal
clock
26.6 µs
TPLH/TPLL
SO0
SO pin
SI pin
a
Y8
Serial input
Data port (φK24)
Y4
Y2
Y1
STA bit
SO1
×
×
×
×
SO2
b
SO3
c
a
d
SO3
a
b
c
SO2
SO3
a
b
d
c
SO1
SO2
SO3
a
b
SO0
SO1
SO2
SO3
a
×: Unfixed
Set “1”
Set “1”
Interrupt
BUSY bit
COUNT bit
SIO F/F bit
58
2004-09-13
TC9328AF
○
A/D Converter
The A/D converter is used for measuring the strength of electric fields and the voltage of batteries with
4-channel 6-bit resolution.
1. A/D Converter Control Port and Data Port
φL21
Y1
Y2
Y4
Y8
AD
SEL0
AD
SEL1
*
STA
A/D converter start bit
A/D conversion is performed whenever this bit is set at “1”.
A/D input selection
φK20
Y1
Y2
Y4
Y8
AD0
AD1
AD2
AD3
SEL0
SEL1
AD INPUT
0
0
ADin1
0
1
ADin2
1
0
ADin3
1
1
ADin4
φK21
Y1
Y2
Y4
Y8
AD4
AD5
BUSY
0
A/D converter operation monitor
LSB
A/D Conversion data
MSB
0: A/D conversion ended
1: A/D conversion in progress
A/D converter is the serial comparison systems of 6-bit decomposition ability.
The standard voltage of A/D conversion is an internal power supply (VDD). The voltage which divided
this power supply into 64 and A/D input voltage is compared, and data is outputted to A/D conversion data
port. A/D conversion input follows multiplex method for the 4-external input pins (ADin1~ADin4 pin), and
selected by AD SEL0/1 bit.
The A/D converter performs A/D conversion whenever the STA bit is set at “1”, and this is ended after
seven machine cycles (280 µs). A/D conversion completion is determined by referring the BUSY bit, and the
A/D conversion data is loaded into the data memory after conversion has finished.
The result of A/D conversion is required for by the following calculation.
V DD ×
n − 0.5
n + 0.5
(63 >
(62 >
=n>
= 1) <
= A/D Input voltage <
= V DD ×
=n>
= 0)
64
64
(n is A/D conversion data value. [decimal])
These control are accessed with the OUT2/IN2 instruction for which [CN = 0H, 1H] has been specified in
the operand.
59
2004-09-13
TC9328AF
2. A/D Converter Circuit Configuration
39 ADin1 (P5-0)
Sample
hold
38 ADin2 (P5-1)
VDD
SEL0/1
37 ADin3 (P5-2)
BUSY
R
Control
circuit
STA BUSY
36 ADin4 (P5-3)
R
Decoder
AD0
~
AD5
A/D conversion data latch
A/D conversion data
Comparator
R
R
VDB
(VDD × 2 doubler
power supply)
3R/2
The A/D converter consists of a 6-bit D/A converter, a comparator, an A/D conversion latch and control
circuit. Only when BUSY bit is “1”, 6 bit D/A converter and a comparator part is in order to operate, there
is no current consumption of A/D converter when it is not operating. A/D converter part is driving using by
doubler voltage VDB (two times to VDD).
Note: To the output data of I/O Port -5 (Nch open drain) corresponding to A/D input pin to use set up “1” and
use it by changing into an input state.
60
2004-09-13
TC9328AF
○
Buzzer Output
The buzzer output can be used to output tones and alarm tones to confirm key operations and the tuning
scan mode. Buzzer type can be selected from a combination of four output modes and eight different
frequencies.
1. Buzzer Control Port
φL1A
Y1
Y2
Y4
Y8
BF0
BF1
BF2
BEN
Buzzer frequency selection port
BF2
BF1
BF0
Buzzer Frequency
Duty
0
0
0
0.625 kHz
1/2
0
0
1
0.75 kHz
1/2
0
1
0
1 kHz
2/3
0
1
1
1.25 kHz
1/2
1
0
0
1.5 kHz
1/2
1
0
1
2.08 kHz
2/3
1
1
0
2.5 kHz
1/2
1
1
1
3 kHz
2/3
Buzzer output enable bit
0: Buzzer output fixed (at POL = “0”, “L” level, at POL = “1”, “H” level)
1: Buzzer output enabled
φL1B
Y1
Y2
Y4
Y8
BM0
BM1
BUZR
ON
POL
Buzzer output logic setup
Buzzer output mode setup
0: Positive logic output. Buzzer frequency is outputted in positive logic from “L” level
1: Negative logic output. Buzzer output is outputted in negative logic from “H” level
P4-0 of I/O port-4 and buzzer output selection
0: I/O port-4 (P4-0) selection
1: Buzzer output selection
BM1
BM0
0
0
Continual output
(mode A)
0
1
Staggered output
(mode B)
1
0
10-Hz intermittent output
(mode C)
1
1
10-Hz intermittent output with 1Hz intervals
(mode D)
Buzzer Output Mode
The buzzer output is also used P4-0 I/O Port. In order to set it as a buzzer output, BUZR ON bit is set to
“1” and it changes to a buzzer output by setting it as an output by the P4-0 I/O control port. After logic
setting up of buzzer frequency, mode setup and a logic setup, buzzer enable bit is set to “1”, it outputs
buzzer. At the time of condition setup, buzzer enable bit is setup “0”.
In Continuation output mode (mode A), if buzzer enable bit is set “1”, buzzer frequency will be outputted
continuously, and if “0” is set, a buzzer output will stop. In staggered output mode, whenever buzzer enable
bit is set to “1”, buzzer is outputted for 50 ms and stopped. In this mode, when “1” is reset to the buzzer
enable bit during buzzer output (50 ms), 50 ms is extended and the buzzer of 100 ms can be outputted. If it
is reset during the extra 50 ms, 150 ms is extended and the buzzer output time can be easily set up. If 10
Hz intermittence output mode (mode C) sets “1” to the buzzer enable bit, 50-ms buzzer output and 50-ms
buzzer pause are performed continuously. And a set of “0” stops a buzzer output.
61
2004-09-13
TC9328AF
10-Hz intermittent output with 1 Hz intervals mode (mode D), if buzzer enable bit is set “1”, 50-ms
buzzer output and 50-ms buzzer pause will carry out 500-ms output, after that 500-ms pause output of
50-ms buzzer output and the 50-ms buzzer pause is carried out again, and this operation is repeated. A set
of “0” stops a buzzer output. At mode B, C, and D, a buzzer is in an output state, even if it sets “0” to buzzer
enable bit and it makes it stop, the buzzer of 50 ms is outputted and stops. In addition, a buzzer output
state can be judged according to the contents of a timer port. The timer port 10-Hz bit is “0”, buzzer is an
output state and it is in a pause state at the time of “1”.
The control of buzzer is accessed by the OUT 1 instruction for which [CN = AH, BH] has been specified in
the operand.
2. Buzzer Circuit Configuration
10 Hz
Multiplexer
0.625 kHz~3 kHz
1 Hz
Buzzer output circuit
BF0~BF2
36 BUZR (P4-0)
BM0~BM2
BEN
3. Buzzer Output Timing
Buzzer frequency
“1”
“0”
“1”
Data set to BEN bit
10 Hz
Buzzer output (mode A)
Buzzer output (mode B)
During a buzzer output, If “1” is set to BEN bit again, 50 ms extension will be
carried out.
50 ms
Buzzer output (mode C)
Period of buzzer frequency
output
50 ms
Period of non-output
The output state in mode C
Buzzer output (mode D)
500 ms
Period of non-output
500 ms
Period of output
Note: When making a buzzer output, it sets up an output state about P4-0 (set “1” to I/O control port)
62
2004-09-13
TC9328AF
○
Pulse Counter
The pulse counter is 8-bit up/down counter and the number of clocks can be detected with CMOS input
from INTR2 pin. It can be used for counting and detecting tape run.
1. Pulse Counter Control Port, Data Port
φL2D
Y1
Y2
Y4
Y8
SEL1
SEL2
SEL4
SEL8
Data select
DAL Address data
φL3B
DAL Address data
Y1
Y2
Y4
Y8
Y1
DA0
Y2
DA1
Y4
DA2
Y8
DA3
Y1 Address
Y2 data
Y4 1
DAL
0
Y8
Y1 Address
Y2 data
Y4 2
DAL
1
2
φK3B
4
Y4
Y8
Y2
DA1
Y4
DA2
Y8
DA3
Y1 Address
Y2 data
Y4 1
DAL
2
CTR OVER
RESET RESET
5
DAL Address data 4
PC0
*
Pulse counter control
Control
*
4
PC1
PC4
*
5
Pulse counter control
PC2
PC3
Pulse counter data
PC5
PC6
PC7
Data
Pulse counter data
OVER
6
•
Y8
DAL Address data 3
3
*
Y8
Y1 Address
Y2 data
Y4 2
DAL
1
DAL Address data 4
DOWN POL
Y2
Y1
DA0
0
Y8
DAL Address data 3
3
Y1
0
0
0
Pulse counter control
DOWN bit............................. Set up 8-bit up/down counter
0: Up count action
1: Down count action
•
POL bit................................. Set up input pin (INTR2 pin) counter input edge
0: Cont for input fallig edge
1: Count for input rising edge
•
•
CTR RESET bit .................... Whenever it sets “1”, a 8-bit rise down counter is reset.
OVER RESET bit ................. Whenever it sets “1”, OVER F/F is reset.
PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7
0
2
LSB
2
MSB
Pulse counter data
OVER
7
OVER F/F bit ................. Detected of overflow
8
0: Counter calculation value <
=2 −1
8
1: Counter calculation value >
2
=
(Overflow status)
63
2004-09-13
TC9328AF
The pulse counter measures pulse number of INTR2 pin.
POL bit set up the clock edge of input pin. If “0” is set, it will count in the falling of an input and it will
set to “1”, it will count in the rising of an input. Usually, this bit is used fixed.
DOWN bit sets up a up/down of 8-bit counter. If it sets to “0” and it will set to rise count operation and
“1”, down count operation will be done. A change of a up/down can be performed freely. However, if a clock
pulse is inputted during change command execution, since it is canceled, be careful of this count.
When 28 or more pulses are inputted, OVER F/F bit is set to “1”. When performing count operation of
8-bits or more, this OVER F/F are detected, and on a data memory, only the number of times of overflow is
added and subtracted, and can correspond. After detection by this bit, and OVER RESET bit is set “1” and
OVER F/F is reset.CTR RESET bit resets only 8-bit counter. The counter is reset whenever it sets “1”.
Counter data loaded data in a data memory by the binary.
The control of pulse counter and data loading is accessed with the OUT3/IN3 instructions for which [CN
= BH] have been specified in the operand and arranges in DAL address register port. This port is set up by
data select port (φL2D), which specified the division. The data of a specification port is set beforehand and
the data port corresponding to it can be accessed. The data select port is +1 increments whenever it
accesses DAL address port (φL3B, φK3B). For this reason, after setting up a data selection port, it can set
up continuously.
Note: If POL bit is changed, a clock pulse may enter. Reset data by the reset bit after changing.
Note: If data select port is +1 increments when it accesses φL2E, φL2F, φL3B, φK3B on the I/O map.
2. Pulse Counter Circuit Configuration
OVER RESET
To interrupt circuit
CTR RESET
DOWN
F/F
44 PCTRin (INTR2)
8-bit up/down counter
POL
OVER F/F
PC0~PC7
Note: Pulse input is the Schmitt input type.
Note: It can be used as pulse counter and interrupt function (INTR2 pin input) together.
3. Example for Pulse Counter Timing
OVER
RESET execution
CTR/OVER RESET
execution
Data set to pulse counter
control bit
DOWN bit
set to “1”
Pulse width 1 µs (min)
DOWN bit
PCTRin input
Counter data
01H
02H
03H
FFH
00H
01H
02H
N
N+1 N−1 N−2
OVER F/F
64
2004-09-13
TC9328AF
○
Input and Output Port (I/O Port)
There are 36 I/O ports available between I/O port-1~-9 which are used to input and output control signals.
Of these 36 I/O ports, 12 I/O ports are CMOS type and 24 I/O ports are Nch open drain type. The
combination function and the functional feature of each I/O port are as follows.
I/O Port
Combination and Additional Function
It’s possible to set pull-up/pull-down.
I/O port-1
But, mixture of a pull-up pull down is impossible.
⎯
P2-0~-2
I/O port-2
Structure
P2-3
CMOS
Pre-scaller PSC output
Nch high output buffer
I/O port-3
Output withstand voltage 3.6 V (max)
P4-0
Nch open
drain
Buzzer output
I/O port-4
CMOS
P4-1~3
Serial interface input/output port
6-bit A/D converter analog input
I/O port-5
The potential to VDB (VDD × 2) can be inputted.
I/O port-6
Output withstand voltage 3.6 V (max)
I/O port-7
Nch open
drain
I/O port-8
The potential to VLCD (3 V) can be inputted.
I/O port-9
1. I/O Port Control, I/O Port Data
φL2D
Y1
Y2
Y4
Y8
SEL1
SEL2
SEL4
SEL8
Data select
Segment-2 data
φL2F
Y1
Y2
Y4
Y8
S15
S16
S17
S18
6
Y1Segment
Y2 /IO select
Y4
Y8
Segment and I/O port changing
S19
7
8
S20
Y8
-0
-3
-1
-0
Y1
-0
A
S22
Y1Segment
Y2 /IO select
Y4
Y1
9
S21
-2
I/OY2
control-1
Y4
-1
-2
I/OY2
control-2
Y4
-1
-2
0: I/O port
1: Segment output
Y8
-3
Y8
-3
I/O control data (Input/output setting)
0: I/O port input
1: I/O port output
I/O control-4
Note: I/O-1, I/O-2, - - - - - is correspond to the pin name of P1-0~-3, P2-0~-3, - - - - - .
65
2004-09-13
TC9328AF
Y1
φLK30
φLK31
φLK32
φLK33
φLK34
Y2
Y4
Y8
-0
-1
-2
-3
Y1
Y2
Y4
I/O port-1
Y8
-0
-1
-2
-3
Y1
Y2
Y4
I/O port-2
Y8
-0
-1
-2
-3
Y1
Y2
Y4
I/O port-3
Y8
-0
-1
-2
-3
Y1
Y2
Y4
I/O port-4
Y8
-0
-1
-3
-2
-0
-1
-2
-3
Y1
Y2
Y4
I/O port-6
Y8
φLK36
-0
-1
-3
φLK37
-0
-1
-2
-3
Y1
Y2
Y4
I/O port-8
Y8
-0
-1
-3
-2
-2
I/O port-9
Y4
Y8
PD0
PD1
PD2
PD3
Control pull-down or pull-up of I/O port-1
0: Pull-up or pull-down off
1: Pull-up or pull-down on
Note: PD0~PD3 is correspond to P1-0~P1-3
:
Y1
Y2
φL3A
I/O port-7
φLK38
Y2
I/O port-1 pull-down
I/O port data
I/O port-5
φLK35
φL20
Y1
Y4
Y8
Port 1
Pull up
Control bit of pull-up/pull-down of I/O port-1
0: Set up pull-down
1: Set up pull-up
CMOS I/O port
0: I/O pin “L” level
1: I/O pin “H” level
Nch open drain
I/O port
0: I/O pin “L” level
1: I/O pin “H” level
output pin is high impedance
The I/O port for the I/O ports is set with the contents of the I/O control data port. “0” is set in the I/O
control data port bit which corresponds to the relevant port when setting the input port, and “1” is set when
setting the output port.
I/O control data port is arranged segment-2 data port and set up by data select port (φL2D), which
specified the division. The data of a specification port to set beforehand is set and the data port
corresponding to it can be accessed. The data select port is +1 increments whenever it accesses DAL
address port (φL2F). For this reason, after setting up a data selection port, it can set up continuously.
The output status of the I/O port is controlled by executing the OUT3 instruction for which corresponds
to each I/O port during output port setting. The contents of the data currently output can also be loaded
into the data memory by executing the IN3 instruction. In addition, the data read by the IN3 command is
not surely in agreement with the data outputted by the OUT3 instruction and, in order to read the state of
a pin.
The data input in the I/O port is loaded into the data memory by executing the IN3 instruction for which
corresponds to each I/O port during input port setting. The contents of the output latch will have no effect
on the input data at this point.
Nch open drain I/O ports have not I/O control data. When it makes an input, it is set “1” in I/O data port,
the status becomes high impedance and read the input status into data memory by IN3 instruction. When
output state becomes "L" level, it set “0” in I/O data port by OUT3 command.
The execution of the WAIT instruction and CKSTP instruction is cancelled and CPU operations are
re-started when the status of the I/O port input specified in the input port changes with I/O port-1. Also,
the MUTE port and MUTE bit are forcibly set to “1” during changes in the input status when the MUTE
port’s I/O bit is set at “1”. By control port of I/O port-1 pull-down, it sets up pull-down or pull-up status. It
can set up a pull-down or pull-up for every pin and if the port is set up “1”, it will become a pull-up or a
pull-down. The pull-up/pull-down control bit of I/O Port -1 perform a change of a pull-up and a pull down.
If the bit is set up“0”, the status becomes pull-down and set up “1”, it becomes pull-up.
66
2004-09-13
TC9328AF
Set up the pull-up and pull-down is used for key matrix configuration. I/O Port-1 with a pull down or a
pull-up is considered for a usual I/O Port output as an input as an output of a key matrix, and a key matrix
is configured. It is able to configure the key matrix of a low noise by the following methods. In setting
pull-down to I/O port-1, the output side of a key matrix is usually high impedance (input state), output and
scan to “H” level on key loaded line, detected key input or non by loading input status of I/O port-1. In the
case of a pull-up, “L” level is outputted and it detected on a key loading line. During executing of CKSTP
instruction and WAIT instruction, the existence of this key input can also be judged and restarted. When
restarting at the time of CKSTP command execution, I/O Port-1 is used by changing into a pull-up state.
For the clock stop mode, since the outputs of an I/O Port are outputted all “L” level, I/O Port-1 stands by in
the state of a pull-up, and if a key is inputted, I/O Port-1 input will change and restart. In this case, since
the standby time of about 100 ms occurs as time lag after being canceled of a clock stop. Since release of
WAIT instruction holds the output state, restarting is possible by the method of both a pull-up and a pull
down, and since there is no time lag from release, detection and operation of a key are quickly possible.
Using these backup modes together can reduce consumption current.
Since the input of I/O Port-1 is an inverter input, the usage that serves as middle potential cannot be
done to this input. But, only at the time of execution of the input instruction, since an input will be in an
ON state, even if middle potential is inputted, as for other I/O Port inputs, unusual consumption current
does not occur. For this reason, use of the pull-up in potential lower than VDD potential, the three value
output of an output level, etc. is possible.
I/O Port -2, -4 pins are the I/O Ports of CMOS structure, P2-3 pin is the prescaller PSC output, P4-0 pin
is the buzzer output and P4-1-3 pins are the serial interface serve a double purpose, respectively. I/O port-3,
-5~-9 are Nch open drain I/O port.
I/O Port -3 uses VLCD (3 V) for the gate potential of Nch output buffer. For this reason, the output
current by which power supply voltage was stabilized also in the time of low voltage can be obtained. This
port can perform the input and output to 3.6 V.
I/O port-5 is used as 6-bit A/D converter input. This port is able to inputted VDB potential (the potential
to VDD × 2).
I/O Port -8, -9 are also used as LCD driver. VLCD (3 V) is used for the gate potential of an Nch open
output buffer. For this reason, the output current by which power supply voltage was stabilized also in the
time of low voltage can be obtained. These pins can perform the input and output to VLCD (3 V). These pins
are set as the input of an I/O Port after reset.
Note: The data select port is +1 increments automatically when it accesses φL2E, φL2F, φL3B, φK3B on the
I/Omap.
VDD
P1-3
30
P1-2 29
The following is an example of key input matrix circuit
configuration. Without key input, it pulled-up and key is
pushed, it inputted “L” level from sauce side(I/O port-9).
It is necessary to take into consideration the shift time to
the pull-up of a key input from “L”. They are all about a key
sauce side at the time of WAIT instruction execution and
“L” WAIT instruction can be lifted, whenever a key input
will be pushed, if it stands by on the level.
P1-1 28
P1-3
P1-0 27
P1-2
P9-3
26
P1-1
P9-2 25
P1-0
P9-1 24
Pull-up
Pull-up
Pushing of P9-3 and P1-1 keys
Pull-up
High impedance
P9-3
P9-0 23
P9-2
P9-1
Example for key input matrix circuit
configuration
P9-0
I/O port-1
Loaded into data
67
2004-09-13
TC9328AF
○
Register Port
The G-register and data register outlined in the explanation on the CPU are also used as a single
internal port.
1. G-register (φKL1D, φKL1E)
This register addresses the data memory’s row addresses (DR = 04H~3FH) during execution of the
MVGD instruction and MVGS instruction. This register is accessed with the OUT1/IN1 instruction for
which [CN = DH~EH] has been specified in the operand. Moreover, if STGI instruction is used, data can be
set to this register by one instruction.
Note: The contents of this register are only valid when the MVGD instruction and MVGS instruction are
executed and are ineffective when any other instruction is executed. Moreover, it does not have the
influence on this register by MVGD instruction and MVGS instruction.
Note: All of the data memory row addresses can be specified indirectly by setting data 00H to 3FH in the
G-register. (DR = 00H~3FH)
Note: For a reason with a RAM capacity of 512 words, this product will become unfixed if 20H-3FH is specified
to be G-register.
Note: Writing and read-out are possible for this register. Please evacuate and return in a data memory if
needed at the time of interruption.
φKL1D
φKL1E
Y1
Y2
Y4
Y8
Y1
Y2
Y4
Y8
G0
G1
G2
G3
G4
G5
*
*
Data memory row address specification
I0
I1
Transmit
I2
I3
I4
G4
G3
G2
G1
G0
DR
0
0
0
1
0
0
04H
0
0
0
1
0
1
05H
0
0
0
1
1
0
06H
0
1
1
1
1
1
1FH
1
0
0
0
0
0
20H
1
1
1
1
1
0
3EH
1
1
1
1
1
1
3FH
I5
I*
68
Can’t specified in this area
STGI instruction
G5
2004-09-13
TC9328AF
2. Data Register (φKL3C~φKL3F), DAL Address Register (φKL3B0~φKL3B3) and Control
Bit
φL2D
Y1
SEL1
φL/K3A
φL/K3B
Y2
SEL2
Y4
SEL4
Y8
Y1
Y2
Y4
Y8
φL/K3B
Y1 DALY2
Y4
address1
SEL8
Y4
Y8
DAL
(data)
→ DA/0
/0
/0
DA4Y1 DAL
DA5Y2
アドレス
DA6Y41DA7Y8
1
Data select
Y2
Y8
アドレス
DA0Y1 DAL
DA1Y2
DA2Y41DA3Y8
0
Y1
2
DA8
DAL
DA9 アドレス
DA10 1DA11
3 DA12 DA13
*/0
0: DAL ADD3, (r) instruction select
1: DAL DA instruction select
*/0
DAL address register
DA13 DA12
DA11 DA10
DA9
MSB
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
LSB
DAL instruction indirect specification
φKL3F
φKL3E
φKL3D
Whenever it sets “1”, the contents of a data register
are transmitted to DAL address register.
1:
φKL3C
Y1
Y2
Y4
Y8
Y1
Y2
Y4
Y8
Y1
Y2
Y4
Y8
Y1
Y2
Y4
Y8
d15
d14
d13
d12
d11
d10
d9
d8
d7
d6
d5
d4
d3
d2
d1
d0
MSB
LSB
Data register 16-bit data
It transmits 16 bits of program memories by DAL instruction
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Program memory 16-bit data
69
2004-09-13
TC9328AF
The data register is 16-bit register for which load the program memory data when the DAL instruction is
executed. The contents of this register are loaded into the data memory in 4-bit units with the execution of
the OUT1/IN1 instructions for which [CN = CH~FH] has been specified in the operand. This register can be
used for loading LCD segment decoding operations, radio band edge data and the data related to binary to
BCD conversion.
The DAL address register (DA) is 14-bit register for which specified the program memory indirectly when
the DAL instruction is executed. There are two kinds of operation methods of DAL instruction. The
control is selected by DAL bit. When DAL bit is set “0”, ADDR3 (6 bits) of the operand and contents of
general register (r) becomes the reference address of program memory and when DAL bit is set “1”, 14 bit
of DAL address register becomes reference address. At the time of setting DAL bit is “0” and execution of
DAL instruction, only program memory area (0000H~03FF) becomes reference area and DAL bit is set “1”
and execution of DAL instruction, all program memory area (0000H~3FFFH) becomes reference area.
If (DATA) → DA bit is set to “1”, it can transfer from the contents of data register to 14-bit DAL address
register by executing of single instruction.
The contents of DAL address register are accessed the data in 4-bit units with the execution of the
OUT3/IN3 instruction for which [CN = BH] have been specified in the operand. DAL address register port
is setup by data select port (φL2D) for which divides and indirect specified. The data of a specification port
to set beforehand is set and the data port corresponding to it is accessed. Data select port is +1 incremented
whenever is accessed this port (φL3B, φK3B). For this reason, after setting up a data selection port, it can
access continuously.
DAL bit and (DATA) → DA bit are accessed with the execution of OUT3/IN3 instruction for which [CN =
AH] has been specified in the operand.
Note: DAL address register becomes effective only execution of DAL instruction when setting “1” and becomes
unrelated at the time of other instruction execution. It does not have the influence on this register by DAL
instruction.
Note: For this product have 8 K step of ROM Capacity, If 2000H - 3FFFH is specified to be DAL address
register and DAL instruction is executed, the contents of a data register will become unfixed.
Note: It’s possible to write in and read out for data registeter and DAL address register. Please evacuate and
return in a data memory if needed at the time of interruption.
Note: There is no action when (DATA) → DA bit is set “0”. When it accesses to φK3A, it only read out only the
DAL bit. (The other bit is “0”.)
3. Carry F/F (Ca flag, φKL1C)
This is set when Carry or Borrow is issued in the result of calculation instruction execution and is reset if
neither of these is issued. The carry F/F is accessed with OUT1/IN1 instructions for which [CN = CH] have
been specified. For this reason, evacuation and a return of the carry F/F at the time of interruption can be
performed easily. Carry F/F is written in a data memory by IN1 instruction at the time of evacuation, it is
evacuated, and the data evacuated by OUT1 instruction is transmitted to carry F/F from a data memory
after the time of a return.
φL/K1C
Y1
Y2
Y4
Y8
CA
flag
*/0
*/0
*/0
Carry F/F
70
2004-09-13
TC9328AF
○
Timer Port
The timer is equipped with 100-Hz, 10-Hz and 2-Hz F/F bits and used for counting clock operations and
tuning scan mode, etc.
1. Timer Port
φL26
Y1
Y2
2 Hz
F/F
Timer
Y4
Y8
The 10 Hz, 100 Hz and under 1 kHz bits are reset
whenever “1” is set.
Reset port
The 2 Hz F/F is reset whenever “1” is set.
Y1
φK26
Y2
2 Hz
F/F
Y4
Y8
10 Hz 100 Hz
Timer
The timer ports are accessed with the OUT2/IN2 instructions for which [CN = 6H] has been specified in
the operand
2. Timer Port Timing
The 2-Hz timer F/F is set with the 2-Hz (500 ms) signal and is reset by setting “1” in the reset port’s 2-Hz
F/F. This bit is usually used as a clock counter.
The 2-Hz timer F/F can only by reset with the reset port’s 2 Hz F/F, and incorrect counts will be output
and correct timers not acquired if not reset within a 500 ms cycle.
2-Hz F/F output
2-Hz F/F reset execution
t < 500 ms
2-Hz clock
500 ms
t
The 10-Hz and 100-Hz timers are outputted to 10-Hz and 100-Hz bits with a duty 50% of 100-ms and
10-ms cycles respectively. Counters at 1 kHz or below will be reset whenever the reset port’s timer bit is set
at “1”.
100 Hz
5 ms
10 ms
10 Hz
50 ms
100 ms
71
2004-09-13
TC9328AF
○
Output Port (Used as LCD Driver Pin)
There are 18-output ports of CMOS type. These output port are used as LCD driver and changed output
port by VLCD OFF bit. If VLCD OFF bit is set to “1”, this port becomes output port. The outputted data to
output port is used as segment data port-1 (φL2E). This data is accessed with OUT2 instruction for which
[CN = EH] is specified and is setup by data select port (φL2D) for which divides and indirect specified like
segment data. The data of a specification port to set a segment data port is set beforehand, and the data
port corresponding to it is accessed. The data select port is +1 incremented whenever it accesses segment
data port-1 (φL2E). For this reason, after setting up a data selection port, it can set up continuously.
Output data is +1 increment with OT count UP bit by executing one instruction. For this reason, it can
use as an address signal output when using an external memory etc. Output buffer capability can be
changed at the time of an output setup. If OTB-UP bit is set “0”, it becomes low output buffer (same
performance of LCD output driver) and set “1”, it becomes high output buffer. Usually, at the time of an
output port setup, this bit is set to “1”.
The power supply of this output port is used VLCD dobuler potential, when using it as an output port,
remove for the capacitor of VLCD doubler potential (between C3-C4) and connect VLCD pin with VDD pin.
Note: Data select port is +1 increment automatically whenever it accesses φL2E, φL2F, φL3B, φK3B on I/O
map.
Note: If set “0” to OT count UP bit, it does not perform count-up.
Note: Refer to LCD driver item.
φL2D
Y1
SEL1
φL2E
Y2
SEL2
Y4
SEL4
Y8
Y1
SEL8
Y4
Y8
Y8
If VLCD off-bit is set to “1”, segment
output data will turn into output port data.
アドレス
OT1Y1 DAL
OT2Y2
OT3Y41OT4Y8
0
OT5Y1 DAL
OT6Y2
アドレス
OT7Y41OT8Y8
1
Data select
Y2
φL/K3B
Y1 Output
Y2 port data
Y4
2
DALY2
アドレス
OT9Y1 OT10
OT11Y41OT12Y8
DAL アドレス
OT15 1OT16
3 OT13 OT14
4 OT17 OT18
φL3A
Y1
Y2
Y4
Y8
OT
count
up
*
*
Whenever this bit is set to “1”, all the OT1 - OT18 is
count up (+1).
OT1 bit is lower bit; OT18 bit is upper bit and are
counted up from OT1 bit.
φL2FF
Y1
Y2
Y4
Y8
Control bit for output port (OT) buffer performance
OTB
-UP
0: Low-output buffer
1: High-output buffer
72
At setting up output port, set “1”.
2004-09-13
TC9328AF
○
MUTE Output
This is a 1-bit CMOS output port for muting control purposes.
1. MUTE Port
φL/K18
Y1
Y2
Y4
Y8
MUTE
I/O
POL
HOLD
Control by change of HOLD input state changing
0: Even if HOLD input status changes, MUTE output does not change.
1: By changing HOLD input status, MUTE bit is set to “1”.
MUTE output polarity control
0: Positive logic: MUTE bit output without modification
1: Negative logic: MUTE bit inversed and output
Control selection by changes in the I/O port-1input status
0: Even if I/O port -1 status changes, MUTE output doesn’t change.
1: By changing I/O port -1 status, MUTE bit is set to “1”.
MUTE output setting
0: MUTE output set at “L” level during positive logic and “H” level during negative logic.
1: MUTE output set at “H” level during positive logic and “L” level during negative logic.
This port is accessed with the OUT1/IN1 instruction for which [CN = 8H] has been specified in the
operand. MUTE output is used for muting control. Setting the MUTE bit to “1” suppresses the generation
of noise when the linear circuit is switched, for example when the equipment is powered down, or when the
I/O Port 1 input or HOLD input is used to switch band. This control is set up according to the contents of
I/O bit and HOLD bit. POL bit sets up the logic of MUTE output.
Please set up according to specification.
2. Circuit Configuration of MUTE Output
MUTE bit
30 MUTE
S
POL bit
HOLD bit
I/O bit
The signal of input change of I/O Port -1
The signal of HOLD input pin changing
Reset signal
73
2004-09-13
TC9328AF
○
Test Port
This internal port is to test device function. It is accessed with OUT1 instruction specifying [CN = FH]
and OUT2 instruction specifying [CN = 6H] in the operand.
φL1F
Y1
Y2
Y4
Y8
#0
#1
#2
#3
Y1
φL26
Test port
○
Y2
Y4
Y8
#4
Test port
Application to an Emulator Tip
If TEST pin is supplied “H” level (Test mode), the device operates as an emulator chip. Three kinds of
test modes are prepared and can constitute a soft development tool by using three devices.
Radio operation can be checked by the connection between this soft development tool and IC for tuners,
performing soft development.
Please refer to TC9328FA software development tool specifications of a development tool.
74
2004-09-13
TC9328AF
Maximum Ratings (Ta = 25°C)
Characteristics
Symbol
Rating
Unit
Supply voltage
VDD
−0.3~4.0
V
Voltage doubler boosting voltage
VDB
−0.3~4.0
V
Output voltage 1
(N-channel open drain)
VO1 (*)
−0.3~4.0
V
Output voltage 2
(N-channel open drain)
VO2 (*)
−0.3~VDB + 0.3
V
Output voltage 3
(N-channel open drain)
VO3 (*)
−0.3~VLCD + 0.3
V
Input voltage
VIN
−0.3~VDD + 0.3
V
Power dissipation
PD
100
mW
Operating temperature
Topr
−10~60
°C
Storage temperature
Tstg
−65~150
°C
*: VO1: P3-0~P3-3, P6-0~P6-3, P7-0~P7-3 pin
VO2: P5-0~P5-3 pin
VO3: P8-0~P8-3, P9-0~P9-3 pin
Electrical Characteristics (unless otherwise noted, Ta = 25°C, VDD = 1.8 V)
Characteristics
Symbol
Test
Circuit
VDD1
⎯
Under CPU operation
VDD2
⎯
Under PLL operation
VHD
Min
Typ.
Max
(*)
0.9
~
1.8
(*)
0.9
~
1.8
⎯
Crystal oscillation stopped
(CKSTP instruction executed)
(*)
0.75
~
1.8
V
IDD1
⎯
PLL operation (VHF mode)
at input FMin = 230 MHz
⎯
6
10
mA
IDD2
⎯
Under CPU operation only
(PLL off, display turned on)
⎯
40
80
IDD3
⎯
Hard wait mode
(crystal oscillator operating
only)
⎯
20
40
IDD4
⎯
Soft wait mode
(CPU stopped, PLL off)
⎯
30
⎯
Memory retention current
IHD
⎯
Crystal oscillation stopped
(CKSTP instruction executed)
⎯
0.1
1.0
µA
Crystal oscillation frequency
fXT
⎯
⎯
75
⎯
kHz
Crystal oscillation start-up time
tst
⎯
⎯
⎯
1.0
s
Range of operating supply voltage
Range of memory retention voltage
Operating current
Test Condition
(*)
Crystal oscillation fXT = 75 kHz
Unit
V
µA
For conditions marked by an asterisk (*), guaranteed when VDD = 0.9~1.8 V, Ta = −10~60°C
75
2004-09-13
TC9328AF
Voltage Doubler Boosting Circuit
Symbol
Test
Circuit
Doubled voltage
VDB
⎯
GND reference (VDB)
Doubled voltage output current
IDB
⎯
Doubled voltage reference voltage
VEE
Constant voltage for phase
comparator
Characteristics
Test Condition
Min
Typ.
Max
Unit
⎯
VDD
×2
⎯
V
VOH = VDB − 0.1 V (VDB)
−50
−200
⎯
µA
⎯
GND reference (VEE)
1.35
1.50
1.65
V
Vreg
⎯
GND reference (Vreg)
1.35
1.50
1.65
V
Constant voltage temperature
characteristic
Dv
⎯
GND reference (VDD, Vreg)
―
−5
⎯
mV/°C
Power supply output current for phase
comparator
Ireg
⎯
VOH = Vreg − 0.1 V (Vreg)
(Note 1)
−50
−200
⎯
µA
Doubled voltage
VLCD
⎯
GND reference (VLCD)
2.7
3.0
3.3
V
Doubled voltage output current
ILCD
⎯
VOH = VLCD − 0.1 V (VLCD)
(Note 1)
−50
−200
⎯
µA
Note 1: The “H” level output current of the pin using the Vreg/VLCD power supply must not exceed the power supply
(doubled voltage: VDB) output current.
Programmable Counter/IF Counter Operating Frequency Range
Symbol
Test
Circuit
FMin (VHF mode)
f VHF
⎯
VIN = 0.1 Vp-p
FMin (FM mode)
f FM
⎯
Characteristics
Test Condition
Min
Typ.
Max
Unit
(*)
50
~
230
MHz
VIN = 0.1 Vp-p
(*)
30
~
130
MHz
f HF1
⎯
VIN = 0.1 Vp-p
(*)
3.0
~
30
f HF2
⎯
VIN = 0.1 Vp-p
(*)
1.0
~
10
AMin (LF mode)
f LF
⎯
VIN = 0.1 Vp-p
(*)
0.5
~
8
MHz
IFin1, IFin2
f IF
⎯
VIN = 0.1 Vp-p
(*)
0.3
~
12
MHz
⎯
(PSC) CL = 15 pF,
VDD = 1.1~1.8 V
(*)
―
―
400
ns
Min
Typ.
Max
Unit
AMin (HF mode)
PSC transfer delay time
tpd
MHz
*: Guaranteed when VDD = 0.9~1.8 V, Ta = −10~60°C
Programmable Counter/IF Counter Input Amplitude Range
Symbol
Test
Circuit
FMin (VHF mode)
V VHF
―
Same as for f VHF
(*)
0.1
~
0.6
Vp-p
FMin (FM mode)
V FM
―
Same as for f FM
(*)
0.1
~
0.6
Vp-p
AMin (HF mode)
V HF
―
Same as for f HF1~2
(*)
0.1
~
0.6
Vp-p
AMin (LF mode)
V LF
―
Same as for f LF
(*)
0.1
~
0.6
Vp-p
IFin1, IFin2
V IF
―
Same as for f IF
(*)
0.1
~
0.6
Vp-p
Characteristics
Test Condition
*: Guaranteed when VDD = 0.9~1.8 V, Ta = −10~60°C
76
2004-09-13
TC9328AF
LCD Common Output/Segment Output (COM1~COM4, S1~S22)
Characteristics
Symbol
Test
Circuit
IOH1
⎯
IOH2
Min
Typ.
Max
VLCD = 3 V,
VOH = VLCD − 0.3 V
(COM1~COM4)
−0.10
−0.20
⎯
⎯
VLCD = 3 V,
VOH = VLCD − 0.3 V (S1~S22)
−0.05
−0.10
⎯
IOL1
⎯
VLCD = 3 V, VOL = 0.3 V
(COM1~COM4)
0.10
0.30
⎯
IOL2
⎯
VLCD = 3 V, VOL = 0.3 V
(S1~S22)
0.05
0.15
⎯
VBS
⎯
No load (COM1~COM4)
1.35
1.5
1.65
V
Min
Typ.
Max
Unit
“H” level
Output current
“L” level
Output voltage 1/2 level
Test Condition
Unit
mA
Output Port, I/O Port (OT1~OT18, P8-0~P8-3, P9-0~P9-3)
Symbol
Test
Circuit
“H” level
IOH3
⎯
VLCD = 3 V,
VOH = VLCD − 0.3 V
(Note 1, except I/O port)
−1.5
−3.0
⎯
“L” level
IOL3
⎯
VLCD = 3 V, VOL = 0.3 V
1.5
3.0
⎯
ILI
⎯
VIH = VLCD, VIL = 0 V
(P8-0~P8-3, P9-0~P9-3)
⎯
⎯
±1.0
“H” level
VIH
⎯
(P8-0~P8-3, P9-0~P9-3)
VDD
× 0.8
~
VDD
“L” level
VIL
⎯
(P8-0~P8-3, P9-0~P9-3)
0
~
VDD
× 0.2
Characteristics
Output current
Input leak current
Test Condition
Input voltage
mA
µA
V
Note 1: The “H” level output current is the current when the pin power supply is fixed.
Make sure that pins using Vreg/VLCD power supply do not exceed the power supply (doubled voltage: VDB)
output current.
77
2004-09-13
TC9328AF
I/O Port (P1-0~P7-3)
Characteristics
Symbol
Test
Circuit
IOH4
⎯
IOH5
Min
Typ.
Max
VDD = 1.5 V,
VOH = VDD − 0.2 V
(I/O port P2, P4)
−0.4
−0.8
⎯
⎯
VDD = 0.9 V,
VOH = VDD − 0.2 V
(I/O port P2, P4)
−0.04
−0.2
⎯
IOL4
⎯
VDD = 1.5 V, VOL = 0.2 V
(except I/O port P3)
0.5
1.0
⎯
IOL5
⎯
VDD = 0.9 V, VOL = 0.2 V
(except I/O port P3)
0.1
0.3
⎯
IOL6
⎯
VDD = 0.9~1.8 V, VOL = 0.2 V
(I/O port P3)
1.0
2.0
⎯
⎯
VIH = VDD, VIL = 0 V
(I/O port P1, P2, P4)
⎯
⎯
±1.0
⎯
VIH = 3.6 V, VIL = 0 V
(I/O port P3, P6, P7)
⎯
⎯
±1.0
⎯
VIH = VDB, VIL = 0 V
(I/O port P5)
⎯
⎯
±1.0
“H” level
Output current
“L” level
Input leak current
ILI
Test Condition
Unit
mA
µA
“H” level
VIH
⎯
⎯
VDD
× 0.8
~
VDD
“L” level
VIL
⎯
⎯
0
~
VDD
× 0.2
Input pull-down resistor
RIN1
⎯
When P1-0~P1-3 are set to
pull-down or pull-up
30
60
120
kΩ
SCK clock external input frequency
fSIO
⎯
When I/O port P4-3 are set to
serial clock input
⎯
⎯
200
kHz
Input voltage
V
For conditions marked by an asterisk (*), guaranteed when VDD = 1.8~3.6 V, Ta = −10~60°C
Note 1: The “H” level output current is the current when the pin power supply is fixed.
Make sure that pins using Vreg/VLCD power supply do not exceed the power supply (doubled voltage: VDB)
output current.
MUTE Output
Characteristics
Symbol
Test
Circuit
IOH4
⎯
IOH5
Min
Typ.
Max
VDD = 1.5 V,
VOH = VDD − 0.2 V
−0.4
−0.8
⎯
⎯
VDD = 0.9 V,
VOH = VDD − 0.2 V
−0.04
−0.2
⎯
IOL4
⎯
VDD = 1.5 V, VOL = 0.2 V
0.5
1.0
⎯
IOL5
⎯
VDD = 0.9 V, VOL = 0.2 V
0.1
0.3
⎯
Min
Typ.
Max
Unit
µA
“H” level
Output current
“L” level
Test Condition
Unit
mA
HOLD , INTR1/2, IN1/2 Input Port, RESET Input
Characteristics
Input leak current
Symbol
Test
Circuit
ILI
⎯
Test Condition
VIH = VDD, VIL = 0 V
⎯
⎯
±1.0
~
VDD
~
VDD
× 0.2
“H” level
VIH3
⎯
⎯
VDD
× 0.8
“L” level
VIL3
⎯
⎯
0
Input voltage
78
V
2004-09-13
TC9328AF
AD Converter (ADin1~ADin4)
Characteristics
Analog input voltage range
Resolution
Conversion total error
Symbol
Test
Circuit
VAD
⎯
VRES
⎯
⎯
⎯
Test Condition
Min
Typ.
Max
Unit
0
~
VDB
V
⎯
⎯
6
⎯
bit
⎯
⎯
±0.5
±1.0
LSB
⎯
⎯
±1.0
µA
Min
Typ.
Max
Unit
−0.4
−0.8
⎯
ADin1~ADin4
VDD = VDB, VIH = VDB,
VIL = 0 V
(ADin1~ADin4)
ILI
⎯
Symbol
Test
Circuit
“H” level
IOH4
⎯
Vreg = 1.5 V,
VOH = Vreg − 0.2 V
“L” level
IOL4
⎯
Vreg = 1.5 V, VOL = 0.2 V
0.5
1.0
⎯
ITL
⎯
VDD = 1.5 V, VTLH = 1.5 V,
VTLL = 0 V
⎯
⎯
±100
nA
Symbol
Test
Circuit
Min
Typ.
Max
Unit
RIN2
⎯
(TEST)
5
10
30
kΩ
XIN amp. feedback resistance
RfXT
⎯
(XIN-XOUT)
⎯
20
⎯
MΩ
XOUT output resistance
ROUT
⎯
(XOUT)
⎯
4
⎯
kΩ
RfIN1
⎯
(FMin)
100
200
400
RfIN2
⎯
(AMin, IFin1, IFin2)
300
600
1200
Analog input leak
DO1, DO2 Output
Characteristics
Output current
Output off leak current
Test Condition
(Note 1)
mA
Others
Characteristics
Input pull-down resistance
Input amp. feedback resistance
Test Condition
kΩ
For conditions marked by an asterisk (*), guaranteed when VDD = 1.8~3.6 V, Ta = −10~60°C
Note 1: The “H” level output current is the current when the pin power supply is fixed.
Make sure that pins using Vreg/VLCD power supply do not exceed the power supply (doubled voltage: VDB)
output current.
79
2004-09-13
TC9328AF
Typical TC9328AF product
IDD (Ta = 25°C) in different modes at PLL operation
Typical TC9328AF product
IDD (Ta = 25°C) in different modes at CPU operation
10
50
At CPU operation
(IDD2)
9
8
IDD (mA)
IDD (mA)
40
VHF mode
(fin = 230 MHz)
7
6
FM mode
(fin = 130 MHz)
5
4
HF1 mode
(fin = 30 MHz)
3
20
In Hard Wait mode
(IDD3)
HF2 mode (fin = 10 MHz)
2
10
1
0
0.5
In Soft Wait mode
(Note) (IDD4)
30
LF mode (fin = 8 MHz)
1
1.5
2
0
0.5
2.5
VDD (V)
1
1.5
2
2.5
VDD (V)
Note: The IDD (operating current) in Soft Wait mode is the current dissipation value.
The actual current dissipation value differs depending on the CPU execution state.
80
2004-09-13
TC9328AF
Typical TC9328AF product input sensitivity VHF mode
(VDD = 1.5 V, Ta = 25°C)
Typical TC9328AF product input sensitivity VHF mode
VDD − fmax/fmin (Vin = 35 mVrms, Ta = 25°C)
1000
240
200
160
120
Specification
50~230 MHz
@35 mVrms
80
40
0
0.1
VHF mode specification:
50~230 MHz
(MHz)
100
fmax/fmin
Input amplitude
(mVrms)
280
1
10
100
10
1
0.1
0.5
1000
1
1.5
2
2.5
fin (MHz)
VDD (V)
Typical TC9328AF product input sensitivity FM mode
(VDD = 1.5 V, Ta = 25°C)
Typical TC9328AF product input sensitivity FM mode
VDD − fmax/fmin (Vin = 35 mVrms, Ta = 25°C)
1000
240
(MHz)
100
200
160
fmax/fmin
Input amplitude
(mVrms)
280
120
Specification
30~130 MHz
@35 mVrms
80
FM mode specification:
30~130 MHz
10
1
40
0
0.1
1
10
100
0.1
0.5
1000
1
1.5
2
2.5
fin (MHz)
VDD (V)
Typical TC9328AF product input sensitivity HF1 mode
(VDD = 1.5 V, Ta = 25°C)
Typical TC9328AF product input sensitivity HF1 mode
VDD − fmax/fmin (Vin = 35 mVrms, Ta = 25°C)
1000
240
(MHz)
100
200
160
fmax/fmin
Input amplitude
(mVrms)
280
120
Specification
3~130 MHz
@35 mVrms
80
40
0
0.1
1
10
HF1 mode specification:
3~30 MHz
10
1
100
0.1
0.5
1000
fin (MHz)
1
1.5
2
2.5
VDD (V)
81
2004-09-13
TC9328AF
Typical TC9328AF product input sensitivity HF2 mode
(VDD = 1.5 V, Ta = 25°C)
Typical TC9328AF product input sensitivity HF2 mode
VDD − fmax/fmin (Vin = 35 mVrms, Ta = 25°C)
1000
100
(MHz)
240
200
160
fmax/fmin
Input amplitude
(mVrms)
280
120
Specification
1~10 MHz
@35 mVrms
80
40
0
0.1
1
10
10
HF2 mode specification:
1~10 MHz
1
0.1
100
0.01
0.5
1000
1
1.5
2
2.5
fin (MHz)
VDD (V)
Typical TC9328AF product input sensitivity LF mode
(VDD = 1.5 V, Ta = 25°C)
Typical TC9328AF product input sensitivity LF mode
VDD − fmax/fmin (Vin = 35 mVrms, Ta = 25°C)
1000
100
(MHz)
240
200
160
fmax/fmin
Input amplitude
(mVrms)
280
120
80
40
0
0.1
Specification
0.5~8 MHz
@35 mVrms
1
10
LF mode specification:
1~10 MHz
1
0.1
10
100
0.01
0.5
1000
fin (MHz)
1
1.5
2
2.5
VDD (V)
Typical TC9328AF product input sensitivity IFin mode
(VDD = 1.5 V, Ta = 25°C)
Input amplitude
(mVrms)
280
240
200
160
120
80
40
0
0.1
Specification
0.3~12 MHz
@35 mVrms
1
10
100
1000
fin (MHz)
82
2004-09-13
TC9328AF
Package Dimensions
Weight: 0.45 g (typ.)
83
2004-09-13
TC9328AF
RESTRICTIONS ON PRODUCT USE
030619EBA
• The information contained herein is subject to change without notice.
• The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of
TOSHIBA or others.
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk.
• The products described in this document are subject to the foreign exchange and foreign trade laws.
• TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced
and sold, under any law and regulations.
84
2004-09-13