DATA SHEET MOS INTEGRATED CIRCUIT µPD75312(A), 75316(A) 4-BIT SINGLE-CHIP MICROCOMPUTER DESCRIPTION The µPD75316(A) is one of the 75X Series 4-bit single-chip microcomputer having a built-in LCD controller/ driver, and has a data processing capability comparable to that of an 8-bit microcomputer. In addition to high-speed operation with 0.95 µ s minimum instruction execution time for the CPU, the µ PD75316(A) can also process data in 1-, 4-, and 8-bit units. Therefore, as a 4-bit single-chip microcomputer chip having a built-in LCD panel controller/driver, its data processing capability is the highest in its class in the world. Detailed functions are described in the following user's manual. Be sure to read it for designing. µ PD75308 User's Manual: IEM-5016 FEATURES • Higher reliability than µPD75316 • Internal memory • Program memory (ROM) : 16256 × 8 bits (µ PD75316(A)) : 12160 × 8 bits (µ PD75312(A)) • Data memory : 512 × 4 bits • Capable of high-speed operation and variable instruction execution time to power save • 0.95 µs, 1.91 µs, 15.3 µs (operating at 4.19 MHz) • 122 µs (operating at 32.768 kHz) • 75X architecture comparable to that for an 8-bit microcomputer is employed • Built-in programmable LCD controller/driver • Clock operation at reduced power dissipation: 5 µA TYP. (operating at 3 V) • Enhanced timer function (3 channels) • Interrupt functions especially enhanced for applications, such as remote control receiver • Pull-up resistors can be provided for 31 I/O lines • Built-in NEC standard serial bus interface (SBI) • Upgraded model of µPD7514 (µPD7500 Series) • PROM version (µ PD75P316, µPD75P316A) available APPLICATIONS Suitable for controlling automotive and transportation equipment. The µPD75316(A) is treated as the representative model throughout this document, unless there are differences between µ PD75312(A) and µPD75316(A) functions. The information in this document is subject to change without notice. Document No. IC-2825A (O. D. No. IC-8270A) Date Published December 1993 P Printed in Japan The mark ★ shows major revised points. NEC Corporation 1991 µPD75312(A), 75316(A) ORDERING INFORMATION Part Number Package Quality Grade µ PD75312GF(A)-xxx-3B9 80-pin plastic QFP (14×20 mm) Special µ PD75316GF(A)-xxx-3B9 80-pin plastic QFP (14×20 mm) Special Remarks: xxx is ROM code number. Please refer to “Quality Grade on NEC Semiconductor Devices” (Document Number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. DIFFERENCE BETWEEN µPD75316(A) and µPD75316 Product µPD75316(A) µPD75316 Special Standard Not offered Offered Item Quality Grade Directly Driving LED Absolute Maximum Ratings Differ in high-level output currrent and low-level output current DC Characteristics Differ in low-level output voltage Electrical Characteristics 2 µPD75312(A), 75316(A) FUNCTIONAL OUTLINE (1/2) Item Function Number of Basic Instructions 41 Instruction Cycle • 0.95 µs, 1.91 µs, 15.3 µs (Main system clock: operating at 4.19 MHz) • 122 µs (Subsystem clock: operating at 32.768 kHz) Internal Memory ROM RAM 16256 × 8-bit (µPD75316(A)), 12160 × 8-bit (µPD75312(A)) 512 × 4 bits General-Purpose Registers • 4-bit manipulation: 8 (B, C, D, E, H, L, X, A) • 8-bit manipulation: 4 (BC, DE, HL, XA) Accumulator • Bit accumulator (CY) • 4-bit accumulator (A) • 8-bit accumulator (XA) Instruction Set • • • • I/O Line 40 Abundant bit manipulation instructions Efficient 4-bit data manipulation instructions 8-bit data transfer instructions GETI instruction executing 2-/3-byte instruction with a single byte 8 16 CMOS input pins Pull-up by software is possible. : 23 CMOS input/output pins 8 CMOS output pins Also serve as segment pins 8 N-ch open-drain input/output Withstand voltage: 10 V Pull-up by mask option is possible. :8 LCD Controller/ Driver • Segment number selection: 24/28/32 segments (4/8 pins can also be used as bit ports.) • Display mode selection: Static, 1/2 duty, 1/3 duty (1/2 bias), 1/3 duty (1/3 bias), 1/4 duty • Dividing resistor for LCD driving can be built-in by mask option. Supply Voltage Range VDD = 2.7 to 6.0 V Timer 3 chs • 8-bit timer/event counter • Clock source: 4 steps • Event count is possible • 8-bit basic interval timer • Reference time generation: 1.95 ms, 7.82 ms, 31.3 ms, 250 ms (operating at 4.19 MHz) • Can be used as watchdog timer • Watch timer • Generates 0.5-second time intervals • Count clock source: Main system clock or subsystem clock (selectable) • Watch fast forward mode (generates 3.9-ms time intervals) • Buzzer output (2 kHz) 3 µPD75312(A), 75316(A) FUNCTIONAL OUTLINE (2/2) Item 8-bit Serial Interface Function • Three modes: • 3-line serial I/O mode • 2-line serial I/O mode • SBI mode • LSB/MSB first selectable Bit Sequential Buffer Special bit manipulation memory: 16 bits • Ideal for remote controller Clock Output Function Timer/event counter output (PTO0): Output of square wave at specified frequency Clock output (PCL): Φ, 524, 262, 65.5 kHz (operating at 4.19 MHz) Buzzer output (BUZ): 2 kHz (operating at 4.19 MHz or 32.768 kHz) 4 Vector Interrupt • External: 3 • Internal: 3 Test Input • External: 1 • Internal: 1 System Clock Oscillator Circuit • Ceramic/crystal oscillator circuit for main system clock oscillation: 4.194304 MHz • Crystal oscillator circuit for subsystem clock oscillation: 32.768 kHz Standby STOP/HALT mode Package 80-pin plastic QFP (14 × 20 mm) µPD75312(A), 75316(A) CONTENTS 1. PIN CONFIGURATION (Top View) ................................................................................................ 7 2. BLOCK DIAGRAM ........................................................................................................................... 8 3. PIN FUNCTIONS .............................................................................................................................. 9 3.1 PORT PINS ............................................................................................................................................. 9 3.2 NON PORT PINS ................................................................................................................................... 11 3.3 PIN INPUT/OUTPUT CIRCUITS ........................................................................................................... 13 3.4 RECOMMENDED PROCESSING OF UNUSED PINS .......................................................................... 15 3.5 NOTES ON USING THE P00/INT4, AND RESET PINS ...................................................................... 16 4. MEMORY CONFIGURATION .......................................................................................................... 16 5. PERIPHERAL HARDWARE FUNCTIONS ........................................................................................ 20 5.1 PORTS .................................................................................................................................................... 20 5.2 CLOCK GENERATOR CIRCUIT ............................................................................................................ 21 5.3 CLOCK OUTPUT CIRCUIT .................................................................................................................... 22 5.4 BASIC INTERVAL TIMER ..................................................................................................................... 23 5.5 WATCH TIMER ...................................................................................................................................... 24 5.6 TIMER/EVENT COUNTER ..................................................................................................................... 25 5.7 SERIAL INTERFACE .............................................................................................................................. 27 5.8 LCD CONTROLLER/DRIVER .................................................................................................................. 29 5.9 BIT SEQUENTIAL BUFFER ................................................................................................................... 31 6. INTERRUPT FUNCTIONS ................................................................................................................ 31 7. STANDBY FUNCTIONS .................................................................................................................. 33 8. RESET FUNCTION ........................................................................................................................... 34 9. INSTRUCTION SET ......................................................................................................................... 36 10. SELECTION OF MASK OPTION ..................................................................................................... 42 11. ELECTRICAL SPECIFICATIONS ...................................................................................................... 43 12. PACKAGE DRAWINGS ................................................................................................................... 55 5 µPD75312(A), 75316(A) 6 13. RECOMMENDED SOLDERING CONDITIONS ............................................................................... 57 APPENDIX A. COMPARISION OF FEATURES AMONG THIS SERIES PRODUCTS ..................... 58 APPENDIX B. DEVELOPMENT TOOLS .............................................................................................. 59 APPENDIX C. 60 RELATED DOCUMENTS .............................................................................................. µPD75312(A), 75316(A) S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 RESET P73/KR7 P72/KR6 P71/KR5 1. PIN CONFIGURATION (Top View) P70/KR4 P63/KR3 P62/KR2 P61/KR1 P60/KR0 X2 X1 NC XT2 XT1 VDD P33 P32 P31/SYNC P30/LCDCL P23/BUZ P22/PCL P21 P20/PTO0 P13/TI0 P12/INT2 P11/INT1 P10/INT0 P03/SI/SB1 BIAS V LC0 V LC1 V LC2 P40 P41 P42 P43 V SS P50 P51 P52 P53 P00/INT4 P01/SCK P02/SO/SB0 µ PD75312GF(A) – ×××–3B9 80 79 78 77 76 75 74 73 72 7170 69 68 67 66 65 1 64 2 63 3 62 4 61 5 60 6 59 7 58 8 57 9 56 10 55 11 54 12 53 13 52 14 51 15 50 16 49 17 48 18 47 19 46 20 45 21 44 22 43 23 42 24 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 µ PD75316GF(A) – ×××–3B9 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24/BP0 S25/BP1 S26/BP2 S27/BP3 S28/BP4 S29/BP5 S30/BP6 S31/BP7 COM0 COM1 COM2 COM3 P00-P03 : Port 0 S0-S31 : Segment Output 0-31 P10-P13 : Port 1 COM0-COM3 : Common Output 0-3 P20-P23 : Port 2 VLC0-VLC2 : LCD Power Supply 0-2 P30-P33 : Port 3 BIAS : LCD Power Supply Bias Control P40-P43 : Port 4 LCDCL : LCD Clock P50-P53 : Port 5 SYNC : LCD Synchronization P60-P63 : Port 6 TI0 : Timer Input 0 P70-P73 : Port 7 PTO0 : Programmable Timer Output 0 BP0-BP7 : Bit Port BUZ : Buzzer Clock KR0-KR7 : Key Return PCL : Programmable Clock SCK : Serial Clock INT0, INT1, INT4 : External Vectored Interrupt 0, 1, 4 SI : Serial Input INT2 : External Test Input 2 SO : Serial Output X1, X2 : Main System Clock Oscillation 1, 2 SB0, SB1 : Serial Bus 0,1 XT1, XT2 : Subsystem Clock Oscillation 1, 2 RESET NC : No Connection : Reset Input 7 8 INTBT PROGRAM COUNTER (14) SP (8) PTO0/P20 ALU BANK INTT0 WATCH TIMER BUZ/P23 GENERAL REG. INTW SI/SB1/P03 f LCD CLOCKED SERIAL INTERFACE SO/SB0/P02 SCK/P01 4 P00-P03 PORT 1 4 P10-P13 PORT 2 4 P20-P23 PORT 3 4 P30-P33 PORT 4 4 P40-P43 PORT 5 4 P50-P53 PORT 6 4 P60-P63 PORT 7 4 P70-P73 CY TIMER/EVENT COUNTER #0 TI0/P13 PORT 0 PROGRAM MEMORY (ROM) 16256 × 8 BITS µ : PD75316(A) 12160 × 8 BITS : µPD75312(A) DECODE AND CONTROL DATA MEMORY (RAM) 512 × 4 BITS INTCSI 24 S0-S23 8 S24/BP0 -S31/BP7 4 COM0-COM3 2. BLOCK DIAGRAM BASIC INTERVAL TIMER INT0/P10 INT1/P11 INT4/P00 KR0/P60 –KR7/P73 8 LCD CONTROLLER /DRIVER f X /2 N BIT SEQ. BUFFER (16) CLOCK OUTPUT CONTROL PCL/P22 CLOCK DIVIDER SYSTEM CLOCK GENERATOR SUB MAIN XT1 XT2 X1 X2 3 STAND BY CONTROL CPU CLOCK V DD V SS RESET V LC0 -V LC2 f LCD BIAS LCDCL/P30 SYNC/P31 µPD75312(A), 75316(A) INTERRUPT CONTROL INT2/P12 µPD75312(A), 75316(A) 3. PIN FUNCTIONS 3.1 PORT PINS (1/2) Pin Name Input/Output Also Served As P00 Input INT4 P01 Input/ Output SCK P02 Input/ Output SO/SB0 P03 Input/ Output SI/SB1 P10 P11 Input INT1 INT2 P13 TI0 P20 PTO0 P22 Input/ Output — PCL P23 BUZ P30 LCDCL P31 P32 Input/ Output P33 P40-43 SYNC — — Input/ Output 8-Bit I/O 4-bit input port (PORT0) Pull-up resistors can be specified in 3-bit units for the P01 to P03 pins by software. Input/ Output Input/ Output Circuit TYPE * F -A × Input F -B M -C With noise elimination function 4-bit input port (PORT1) Internal pull-up resistors can be specified in 4-bit units by software. × Input B -C 4-bit input/output port (PORT2) Internal pull-up resistors can be specified in 4-bit units by software. × Input E-B Programmable 4-bit input/output port (PORT3) This port can be specified for input/ output in bit units. Internal pull-up resistors can be specified in 4-bit units by software. × Input E-B — N-ch open-drain 4-bit input/output port (PORT4) Internal pull-up resistors can be specified in bit units. (mask option) Withstand voltage is 10 V in the opendrain mode. — N-ch open-drain 4-bit input/output port (PORT5) Internal pull-up resistors can be specified in bit units. (mask option) Withstand voltage is 10 V in the opendrain mode. ● P50-53 When Reset B INT0 P12 P21 Function High level (with internal pull-up resistor) or high impedance High level (with internal pull-up resistor) or high impedance M M *: Circles indicate Schmitt trigger inputs. 9 µPD75312(A), 75316(A) 3.1 PORT PINS (2/2) Pin Name Input/Output Also Served As P60 P61 P62 KR0 KR1 Input/ Output KR2 P63 KR3 P70 KR4 P71 P72 KR5 Input/ Output KR6 P73 KR7 BP0 S24 Function Programmable 4-bit input/output port (PORT6) This port can be specified for input/ output in bit units. Internal pull-up resistors can be specified in 4-bit units by software. 8-Bit I/O When Reset Input/ Output Circuit TYPE*1 Input F -A Input F -A *2 G-C ● 4-bit input/output port (PORT7) Internal pull-up resistors can be specified in 4-bit units by software. S25 BP1 Output BP2 S26 BP3 S27 BP4 S28 BP5 1-bit output port (BIT PORT) Shared with a segment output pin. × S29 Output BP6 S30 BP7 S31 *1: Circles indicate Schmitt trigger inputs. 2: For BP0-7, V LC1 indicated below are selected as the input source. However, the output level is changed depending on BP0-7 and the VLC1 external circuits. Example: Since BP0-7 are connected to each other within the µPD75316(A) as shown in the diagram below, the output level of BP0-7 depends on the sizes of R1, R2 and R 3. µ PD75316(A) V DD R2 BP0 V LC1 ON BP1 R1 ON R3 10 3 µPD75312(A), 75316(A) 3.2 NON PORT PINS Also Served Pin Name Input/Output As Functon When Reset Input/ Output Circuit TYPE*1 Input P13 Timer/event counter external event pulse Input Input B -C PTO0 Input/ Output P20 Timer/event counter output Input E-B PCL Input/ Output P22 Clock output Input E-B BUZ Input/ Output P23 Fixed frequency output (for buzzer or for trimming the system clock) Input E-B SCK Input/ Output P01 Serial clock input/output Input F -A SO/SB0 Input/ Output P02 Serial data output Serial bus input/output Input F -B SI/SB1 Input/ Output P03 Serial data input Serial bus input/output Input M -C Input P00 Edge detection vector interrupt input (both rising and falling edge detection are effective) Input B Input B -C TI0 INT4 P10 INT0 INT1 INT2 Input Clock synchronous P11 Edge detection vector interrupt input (detection edge can be selected) P12 Edge detection testable Asynchronous input (rising edge detection) Input B -C Input Asynchronous KR0-KR3 Input/ Output P60-P63 Parallel falling edge detection testable input Input F -A KR4-KR7 Input/ Output P70-P73 Parallel falling edge detection testable input Input F -A S0-S23 Output — Segment signal output *2 G-A S24-S31 Output BP0-7 Segment signal output *2 G-C COM0COM3 Output — Common signal output *2 G-B VLC0-VLC2 — — LCD drive power Internal dividing resistor (mask option) — — BIAS Output — Disconnect output for external expanded driver *3 — LCDCL*4 Input/ Output P30 Externally expanded driver clock output Input E-B SYNC*4 Input/ Output P31 Externally expanded driver sync clock output Input E-B To connect the crystal/ceramic oscillator to the main system clock generator. When inputting the external clock, input the external clock to pin X1, and the reverse phase of the external clock to pin X2. — — To connect the crystal oscillator to the subsystem clock generator. When the external clock is used, pin XT1 inputs the external clock. In this case, pin XT2 must be left open. — — X1, X2 Input — XT1 Input — XT2 — — Pin XT1 can be used as a 1-bit input (test) pin. (to be cont'd) 11 µPD75312(A), 75316(A) (cont'd) Pin Name Input/Output Also Served As Function When Reset Input/ Output Circuit TYPE*1 RESET Input — System reset input — B NC *5 — — No connection — — VDD — — Positive power supply — — VSS — — GND — — *1: Circles indicate Schmitt trigger inputs. 2: For these display output, VLCX indicated below are selected as the input source. S0 to S31: VLC1, COM0 to COM2: VLC2, COM3: VLC0 However, display output level varies depending on the particular display output and VLCX external circuit. 3: Internal dividing resistor provided Internal dividing resistor not provided : Low level : High impedance 4: These pins are provided for future system expansion. At present, these pins are used only as pins P30 and P31. 5: When sharing the printed circuit board with the µ PD75P316 and 75P316A, the NC pin must be connected to VDD . 12 µPD75312(A), 75316(A) 3.3 PIN INPUT/OUTPUT CIRCUITS The following shows a simplified input/output circuit diagram for each pin of the µPD75316(A). TYPE D (for TYPE E– B, F– A) TYPE A (for TYPE E–B) VDD VDD data P–ch P–ch OUT IN N–ch Input buffer of CMOS standard output disable N–ch Push–pull output that can be set in a output high–impedance state (both P–ch and N–ch are off) TYPE E–B TYPE B VDD P.U.R. P.U.R. enable P–ch IN data IN/OUT Type D output disable Type A Schmitt trigger input with hysteresis characteristics TYPE B–C P.U.R. : Pull–Up Resistor TYPE F–A VDD P.U.R. VDD P.U.R. enable P.U.R. P–ch P.U.R. enable P–ch data IN/OUT Type D IN output disable Type B P.U.R. : Pull–Up Resistor P.U.R. : Pull–Up Resistor 13 µPD75312(A), 75316(A) TYPE F–B TYPE G– C VDD V DD P.U.R. P-ch P.U.R. enable output disable (P) P–ch V LC0 VDD V LC1 P-ch IN/OUT data output disable P-ch SEG data/Bit Port data N-ch OUT N-ch output disable (N) V LC2 N-ch P.U.R. : Pull–Up Resistor TYPE M TYPE G–A VDD P.U.R. enable (Mask option) V LC0 IN/OUT P-ch data V LC1 P-ch SEG data OUT N-ch output disable N-ch V LC2 Middle voltage input buffer (withstand voltage: +10 V) N-ch P.U.R. : Pull–Up Resistor TYPE M–C TYPE G–B VDD V LC0 P.U.R. P-ch P.U.R. enable V LC1 P–ch P-ch N-ch IN/OUT OUT COM data N-ch P-ch data output disable V LC2 N-ch P.U.R. : Pull–Up Resistor 14 N-ch µPD75312(A), 75316(A) 3.4 RECOMMENDED PROCESSING OF UNUSED PINS Table 3-1 Unused Pins Processing Pin P00/INT4 Recommended Connections Connect to VSS P01/SCK P02/SO/SB0 Connect to VSS or VDD P03/SI/SB1 P10/INT0-P12/INT2 P13/TI0 Connect to VSS P20/PTO0 P21 P22/PCL P23/BUZ P30/LCDCL P31/SYNC P32 Input : Connect to VSS or V DD Output: Open P33 P40-P43 P50-P53 P60/KR0-P63/KR3 P70/KR4-P73/KR7 S0-S23 S24/BP0-S31/BP7 Open COM0-COM3 VLC0-VLC2 Connect to VSS BIAS Connect to VSS only when all of the VLC0-VLC2 pins are unused, otherwise, open. XT1 Connect to VSS or VDD XT2 Open 15 µPD75312(A), 75316(A) 3.5 NOTES ON USING THE P00/INT4, AND RESET PINS In addition to the functions described in Sections 3.1 and 3.2, an exclusive function for setting the test mode, in which the internal fuctions of the µPD75316(A) are tested, is provided to the P00/INT4 and RESET pins. If a voltage exceeding VDD is applied to either of these pins, the µPD75316(A) is put into test mode. Therefore, even when the µPD75316(A) is in normal operation, if noise exceeding the VDD is input into any of these pins, the µPD75316(A) will enter the test mode, and this will cause problems for normal operation. As an example, if the wiring to the P00/INT4 pin or the RESET pin is long, stray noise may be picked up and the above montioned problem may occur. Therefore, all wiring to these pins must be made short enough to not pick up stray noise. If noise cannot be avoided, suppress the noise using a capacitor or diode as shown in the figure below. • Connect a diode having a low VF across P00/INT4 and RESET, and VDD . • Connect a capacitor across P00/INT4 and RESET, and V DD. VDD VDD Low VF diode VDD VDD P00/INT4, RESET P00/INT4, RESET 4. MEMORY CONFIGURATION • Program memory (ROM) ...16256 × 8 bits (0000H-3F7FH): µ PD75316(A) ...12160 × 8 bits (0000H-2F7FH): µ PD75312(A) • 0000H, 0001H : Vector table to which address from which program is started is written after reset • 0002H-000BH: Vector table to which address from which program is started is written after interrupt • 0020H-007FH : Table area referenced by GETI instruction • Data memory • Data area .... 512 × 4 bits (000H–1FFH) • Peripheral hardware area .... 128 × 4 bits (F80H–FFFH) 16 µPD75312(A), 75316(A) (a) µPD75316(A) Address 7 0000H MBE 6 0 0 5 Internal reset start address (upper 6 bits) Internal reset start address (lower 8 bits) 0002H MBE 0 INTBT/INT4 start address (upper 6 bits) INTBT/INT4 start address (lower 8 bits) 0004H MBE 0 INT0 start address (upper 6 bits) INT0 start address (lower 8 bits) 0006H MBE 0 INT1 start address (upper 6 bits) INT1 start address (lower 8 bits) 0008H MBE 0 CALL ! addr instruction subroutine entry address CALLF ! faddr instruction entry address BR ! addr instruction branch address INTCSI start address (upper 6 bits) INTCSI start address (lower 8 bits) 000AH MBE 0 INTT0 start address (upper 6 bits) INTT0 start address (lower 8 bits) BRCB ! caddr instruction branch address BR $addr instruction relational branch address (-15 to -1, +2 to +16) 0020H GETI instruction reference table 007FH 0080H Branch destination address and subroutine entry address for GETI instruction 07FFH 0800H 0FFFH 1000H BRCB ! caddr instruction branch address 1FFFH 2000H BRCB ! caddr instruction branch address 2FFFH 3000H BRCB ! caddr instruction branch address 3F7FH Fig. 4-1 Program Memory Map (1/2) 17 µPD75312(A), 75316(A) (b) µPD75312(A) Address 7 0000H MBE 6 0 0 5 Internal reset start address (upper 6 bits) Internal reset start address (lower 8 bits) 0002H MBE 0 INTBT/INT4 start address (upper 6 bits) INTBT/INT4 start address (lower 8 bits) 0004H MBE 0 INT0 start address (upper 6 bits) INT0 start address (lower 8 bits) 0006H MBE 0 INT1 start address (upper 6 bits) INT1 start address (lower 8 bits) 0008H MBE 0 CALL ! addr instruction subroutine entry address CALLF ! faddr instruction entry address BR ! addr instruction branch address INTCSI start address (upper 6 bits) INTCSI start address (lower 8 bits) 000AH MBE 0 INTT0 start address (upper 6 bits) INTT0 start address (lower 8 bits) BRCB ! caddr instruction branch address BR $addr instruction relational branch address (-15 to -1, +2 to +16) 0020H GETI instruction reference table 007FH 0080H Branch destination address and subroutine entry address for GETI instruction 07FFH 0800H 0FFFH 1000H BRCB ! caddr instruction branch address 1FFFH 2000H BRCB ! caddr instruction branch address 2F7FH Fig. 4-1 Program Memory Map (2/2) 18 µPD75312(A), 75316(A) Data memory General-purpose register area Stack area 000H Memory bank (8 × 4) 007H 008H 0 256× 4 (248 × 4) Data area Static RAM (512 × 4) 0FFH 100H 256× 4 (224 × 4) 1 1DFH 1E0H (32 × 4) Display data memory area 1FFH Unmapped F80H Peripheral hardware area 128× 4 15 FFFH Fig. 4-2 Data Memory Map 19 µPD75312(A), 75316(A) 5. PERIPHERAL HARDWARE FUNCTIONS 5.1 PORTS I/O ports are classified into the following 4 kinds: • CMOS input (PORT0, 1) : • CMOS input/output (PORT2, 3, 6, 7) : 16 • N-ch open-drain (PORT4, 5) : 8 • CMOS output (BP0-BP7) : 8 Total : 40 Port Name Function 8 Operation and Feature PORT0 4-bit input PORT1 Can be always read or tested regardless of operation mode of multiplexed pin. Can be set in input or output mode in 4-bit units. Ports 6 and 7 are used in pairs to input/output data in 8-bit units. PORT2 PORT7 Remarks Multiplexed with INT4, SCK, SO/SB0, and SI/SB1 Multiplexed with INT0INT2 and TI0 Multiplexed with PTO0, PCL, and BUZ Multiplexed with KR4-KR7 4-bit Input/Output PORT3 Can be set in input or output mode in 1-bit units. Multiplexed with KR0-KR3 PORT6 20 Multiplexed with LCDCL and SYNC PORT4 PORT5 4-bit Input/Output (N-ch open-drain, 10 V) Can be set in input or output mode in 4-bit units. Ports 4 and 5 are used in pairs to input/output data in 8-bit units. Can be connected to a pull-up resistor in 1-bit units by using mask option. BP0-BP7 1-bit output Output data in 1-bit units. Can be used as LCD drive segment output pins S24-S31 through software. Low drive capability For driving CMOS load µPD75312(A), 75316(A) 5.2 CLOCK GENERATOR CIRCUIT The operation of the clock generator circuit is determined by the processor clock control regiser (PPC) and system clock control register (SCC). This circuit can generate two types of clocks: main system clock and subsystem clock. In addition, it can also change the instruction execution time. • 0.95 µs/1.91 µ s/15.3 µs (main system clock: 4.19 MHz) • 122 µ s (subsystem clock: 32.768 kHz) · Basic interval timer (BT) · Timer/event counter · Serial interface · Watch timer · LCD controller/driver · INT0 noise rejecter circuit · Clock output circuit XT1 V DD XT2 Subsystem clock oscillator f XT LCD controller /driver Watch timer X1 WM.3 SCC SCC3 1/8 to 1/4096 Frequency divider 1/2 1/16 Oscillator disable signal Selector X2 Main system f X clock oscillator Selector V DD Frequency divider 1/4 Internal bus SCC0 PCC PCC0 Φ · CPU · INT0 noise rejecter circuit · Clock output circuit PCC1 4 HALT F/F PCC2 S HALT* STOP* PCC3 PCC2, PCC3 clear signal R STOP F/F Q S Q Wait release signal from BT RESET signal R Standby release signal from interrupt control circuit Remarks 1: fX = Main system clock frequency 2: fXT = Subsystem clock frequency 3: PCC: Processor clock control register 4: SCC: System clock control register 5: *: instruction execution. ★ 6: One clock cysle (tCY) of Φ is one machine cycle of an instruction. For tCY, refer to AC characteristics in 11. ELECTRICAL SPECIFICATIONS. Fig. 5-1 Clock Generator Block Diagram 21 µPD75312(A), 75316(A) 5.3 CLOCK OUTPUT CIRCUIT The clock output circuit outputs clock pulse from the P22/PCL pin. This clock pulse is used for the remote control output, peripheral LSIs, etc. • Clock output (PCL) : Φ, 524, 262, 65.5 kHz (operating at 4.19 MHz) • Buzzer output (BUZ) : 2 kHz (operating at 4.19 MHz or 32.768 kHz) Fig. 5-2 shows the clock output circuit configuration. From the clock generator Φ Output buffer fX/23 Selector fX/24 PCL/P22 fX/26 PORT2.2 CLOM3 0 CLOM1 CLOM0 CLOM P22 output latch Bit 2 of PMGB Port 2 input/ output mode specification bit 4 Internal bus Fig. 5-2 Clock Output Circuit Configuration Remarks: A measures to prevent outputting narrow width pulse when selecting clock output enable/ disable is taken. 22 µPD75312(A), 75316(A) 5.4 BASIC INTERVAL TIMER The basic interval timer has these functions: • Interval timer operation which generates a reference time interrupt • Watchdog timer application which detects a program runaway • Selects the wait time for releasing the standby mode and counts the wait time • Reads out the count value From the clock generator Clear Clear fX/25 fX/27 Set signal Basic interval timer (8-bit frequency divider circuit) MPX fX/29 BT fX/212 3 BTM3 SET1* BT interrupt request flag BTM2 BTM1 Vector interrupt request IRQBT signal Wait release signal for standby release BTM0 BTM 4 8 Internal bus Remarks : *: Instruction execution Fig. 5-3 Basic Interval Timer Configuration 23 µPD75312(A), 75316(A) 5.5 WATCH TIMER The µPD75316(A) has a built-in 1-ch watch timer. The watch timer is configured as shown in Fig. 5-4. • Sets the test flag (IRQW) with 0.5 sec interval. The standby mode can be released by IRQW. • 0.5 second interval can be generated either from the main system clock or subsystem clock. • Time interval can be advanced to 128 times faster (3.91 ms) by setting the fast mode. This is convenient for program debugging, test, etc. • Fixed frequency (2.048 kHz) can be output to the P23/BUZ pin. This can be used for beep and system clock frequency trimming. • The frequency divider circuit can be cleared so that zero second watch start is possible. fW (512 Hz: 1.95 ms) 26 f LCD fW (256 Hz: 3.91 ms) 27 fX From the 128 (32.768 kHz) clock generator f XT (32.768 kHz) Selector fW (32.768 kHz) Frequency divider f W (2.048 16 kHz) fW 2 14 INTW (IRQW set signal) Selector (2 Hz 0.5 sec) Clear Output buffer P23/BUZ WM WM7 PORT2.3 0 0 0 WM3 WM2 WM1 WM0 8 P23 output latch Bit test instruction Internal bus ( ) is for f X = 4.194304 MHz, fXT = 32.768 kHz. Fig. 5-4 Watch Timer Block Diagram 24 Bit 2 of PMGB Port 2 input/output mode µPD75312(A), 75316(A) 5.6 TIMER/EVENT COUNTER The µPD75316(A) has a built-in 1-ch timer/event counter. The timer/even counter has these functions: • Programmable interval timer operation • Outputs square-wave signal of an arbitrary frequency to the PTO0 pin. • Event counter operation • Divides the TI0 pin input in N and outputs to the PTO0 pin (frequency divider operation). • Supplies serial shift clock to the serial interface circuit. • Count condition read out function 25 26 Internal bus 8 — SET1*1 TM06 TM05 TM04 TM03 TM02 TM0 — 8 8 TMOD0 TOE0 TO enable flag Modulo register (8) — Coincidence Comparator (8) Input buffer Bit 2 of PGMB Port 2 input/ output mode To serial interface 8 PORT1.3 PORT2.0 P20 output latch 8 TOUT F/F Reset P20/PTO0 Output buffer T0 P13/TI0 From the clock generator*2 Count register (8) MPX CP Clear ( INTT0 IRQT0 set signal ) Timer operation start signal *1: SET1: Instruction execution 2: For details, refer to Fig. 5-1. Fig. 5-5 Timer/Event Counter Block Diagram µPD75312(A), 75316(A) RESET IRQT0 clear signal µPD75312(A), 75316(A) 5.7 SERIAL INTERFACE The µ PD75316(A) is equipped with an 8-bit clocked serial interface that operates in the following three modes: • Three-line serial I/O mode • Two-line serial I/O mode • SBI mode (serial bus interface mode) 27 28 Internal bus 8/4 CSIM 8 Bit test 8 8 Slave address register (SVA) (8) SBIC Coincidence signal Address comparator (8) RELT CMDT SET CLR (8) D SO latch Q ACKT ACKE BSYE Selector P03/SI/SB1 Shift register (SIO) Bit test Bit manipulation Selector P02/SO/SB0 Busy/ acknowledge output circuit Bus release/ command/ acknowledge detector circuit P01/SCK Serial clock counter Serial clock control circuit INTCSI control circuit ( Serial clock selector INTCSI IRQCSI set signal fX/23 fX/24 fX/26 TOUT F/F (from timer/ event counter) External SCK Fig. 5-6 Serial Interface Block Diagram ) µPD75312(A), 75316(A) P01 output latch RELD CMDD ACKD µPD75312(A), 75316(A) 5.8 LCD CONTROLLER/DRIVER The µPD75316(A) is provided with a display controller that generates segment and common signals and a segment driver and a common driver that can directly drive an LCD panel. Figure 5-7 shows the LCD controller/driver configuration. These LCD controller and drivers have the following functions: • Generate segment and common signals by automatically reading the display data memory by means of DMA • Five display modes selectable ➀ Static ➁ 1/2 duty (1/2 bias) ➂ 1/3 duty (1/2 bias) 4 1/3 duty (1/3 bias) ➄ 1/4 duty (1/3 bias) • Four types of frame frequencies selectable in each display mode • Up to 32 segment signals (S0-S31) and four common signals (COM0-COM3) can be output. • Four segment signal output pins (S24-S27, S28-S31) can be used as an output port (BP0-BP3, BP4-BP7). • Dividing resistor for LCD driving power source can be provided (by mask option). • All bias modes and LCD drive voltages can be used. • Current flowing to dividing resistor can be cut when display is off. • Display data memory not used for display can be used as ordinary data memory. • Can also operate on subsystem clock. 29 30 Internal bus 4 Display 1FFH 1FEH data memory 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 1F9H 1F8H 8 4 4 8 Display mode register Display control register Port 3 output latch 1 0 Port mode register group A 1 0 1ECH Timing controller f LCD Multiplexer Selector S31/BP7 S30/BP6 S24/BP0 Common driver S23 S0 LCD driving voltage control COM3 COM2 COM1 COM0 V LC2 Fig. 5-7 LCD Controller/Driver Block Diagram V LC1 V LC0 P31/ SYNC P30/ LCDCL µPD75312(A), 75316(A) Segment driver µPD75312(A), 75316(A) 5.9 BIT SEQUENTIAL BUFFER .... 16 BITS The bit sequential buffer is a data memory specifically provided for bit manipulation. With this buffer, addresses and bit specifications can be sequentially up-dated in bit manipulation operation. Therefore, this buffer is very useful for processing long data in bit units. FC3H Address bit 3 Symbol L register 2 FC2H 1 0 3 BSB3 L=F 2 FC1H 1 0 3 BSB2 L=C L=B 2 FC0H 1 0 3 BSB1 L=8 L=7 2 1 0 BSB0 L=4 L=3 L=0 DECS L INCS L Remarks: For the pmem.@L addressing, the specification bit is shifted according to the L register. Fig. 5-8 Bit Sequential Buffer Format 6. INTERRUPT FUNCTIONS The µ PD75316(A) has 6 different interrupt sources and multiple interrupt by software control is also possible. The µ PD75316(A) is also provided with two types of test sources, of which INT2 has two types of edge detection testable inputs. The interrupt control circuit of the µPD75316(A) has these functions: • Hardware controlled vector interrupt function which can control whether or not to accept an interrupt by using the interrupt flag (IExxx) and interrupt master enable flag (IME). • The interrupt start address can be arbitrarily set. • Interrupt request flag (IRQxxx) test function (an interrupt generation can be confirmed by means of software). • Standby mode release (Interrupts to be released can be selected by the interrupt enable flag). 31 32 Internal bus 2 1 3 IM2 IM1 IM0 Interrupt enable flag (IE ××× ) INT BT INT0 /P10 INT1 /P11 Both edge detection circuit Edge Noise detection elimination circuit circuit Edge detection circuit IRQ1 INTT0 IRQT0 INTW IRQW Falling edge detection circuit Priority control circuit Vector table address generator IRQ2 Standby release signal IM2 Fig. 6-1 Interrupt Control Block Diagram µPD75312(A), 75316(A) KR0/P60 KR7/P73 IRQ0 IRQCSI Rising edge detection circuit VRQn IRQ4 INTCSI INT2 /P12 IST0 Decoder IRQBT Selector INT4 /P00 IME µPD75312(A), 75316(A) 7. STANDBY FUNCTIONS The µPD75316(A) has two different standby modes (STOP mode and HALT mode) to reduce the power consumption while waiting for program execution. Table 7-1 Each Status in Standby Mode STOP Mode HALT Mode Setting Instruction STOP instrtuction HALT instruction System Clock for Setting Can be set only when operating on the main system clock Can be set either with the main system clock or the subsystem clock Operation Status Clock Generator Only the main system clock stops its operation. Only the CPU clock Φ stops its operation. (oscillation continues) Basic Interval Timer No operation Operation (Sets IRQBT at reference time interval) * Serial Interface Can operate only when the external SCK input is selected for the serial clock Can operate * Timer/Event Counter Can operate only when the TI0 pin input is selected for the count clock Can operate * Watch Timer Can operate when fXT is selected for the count clock Can operate LCD Controller Can operate only when fXT is selected for LCDCL Can operate External Interrupt INT1, INT2, and INT4 can operate. Only INT0 cannot operate. CPU No operation Release Signal An interrupt request signal from a hardware whose operation is enabled by the interrupt enable flag or the RESET signal input An interrupt request signal from a hardware whose operation is enabled by the interrupt enable flag or the RESET signal input *: Operation is possible only when the main system clock is operating. 33 µPD75312(A), 75316(A) 8. RESET FUNCTION When the RESET signal is input, the µPD75316(A) is reset and each hardware is initialized as indicated in Table 8-1. Fig. 8-1 shows the reset operation timing. Wait (31.3ms/4.19MHz) RESET input Operation mode or standby mode HALT mode Operation mode Internal reset operation Fig. 8-1 Reset Operation by RESET Input Table 8-1 Status of Each Hardware after Reset (1/2) Hardware Program Counter (PC) PSW Carry Flag (CY) RESET Input in Standby Mode RESET Input during Operation The contents of the lower 6 bits of address 0000H of the program memory are set to PC13-8, and the contents of address 0001H are set to PC7-0. The contents of the lower 6 bits of address 0000H of the program memory are set to PC13-8, and the contents of address 0001H are set to PC7-0. Retained Undefined Skip Flag (SK0-2) 0 0 Interrupt Status Flag (IST0) 0 0 Bank Enable Flag (MBE) The contents of bit 7 of address 0000H of the program memory are set to MBE. The contents of bit 7 of address 0000H of the program memory are set to MBE. Stack Pointer (SP) Undefined Undefined Data Memory (RAM) Retained * Undefined Retained Undefined General-Purpose Register (X, A, H, L, D, E, B, C) Bank Selection Register (MBS) Basic Interval Counter (BT) Timer Mode Register (BTM) Timer/Event Counter Counter (T0) Module Register (TMOD0) Mode Register (TM0) TOE0, TOUT F/F Watch Timer Mode Register (WM) 0 0 Undefined Undefined 0 0 0 0 FFH FFH 0 0 0, 0 0, 0 0 0 *: Data of address 0F8H to 0FDH of the data memory becomes undefined when a RESET signal is input. 34 µPD75312(A), 75316(A) Table 8-1 Status of Each Hardware after Reset (2/2) Hardware Serial Interface Clock Generator, Clock Output Circuit LCD Controller Interrupt Function Digital Port Shift Register (SIO) RESET Input in Standby Mode RESET Input during Operation Retained Undefined Operation Mode Register (CSIM) 0 0 SBI Control Register (SBIC) 0 0 Slave Address Register (SVA) Retained Undefined Processor Clock Control Register (PCC) 0 0 System Clock Control Register (SCC) 0 0 Clock Output Mode Register (CLOM) 0 0 Display Mode Register (LCMD) 0 0 Display Control Register (LCDC) 0 0 Reset (0) Reset (0) Interrupt Enable Flag (IExxx) 0 0 Interrupt Master Enable Flag (IME) 0 0 INT0, INT1, INT2 Mode Registers (IM0, 1, 2) 0, 0, 0 0, 0, 0 Output Buffer Off Off Output Latch Interrupt Request Flag (IRQxxx) Clear (0) Clear (0) Input/Output Mode Register (PMGA, B) 0 0 Pull-Up Resistor Specification Register (POGA) 0 0 Retained Specified Bit Sequential Buffer (BSB0-3) 35 µPD75312(A), 75316(A) 9. INSTRUCTION SET (1) Operand representation and description Describe one or more operands in the operand field of each instruction according to the operand representation and description methods of the instruction (for details, refer to RA75X Assembler Package User's Manual - Language (EEU-730)). With some instructions, only one operand should be selected from several operands. The uppercase characters, +, and – are keywords and must be described as is. Describe an appropriate numeric value or label as immediate data. The symbols in the register and flag symbols can be described as labels in the places of mem, fmem, pmem, and bit (for details, refer to µPD75308 User's Manual (IEM-5016)). However, fmem and pmem restricts the label that can be described. Representation Description reg reg1 X, A, B, C, D, E, H, L X, B, C, D, E, H, L rp rp1 rp2 XA, BC, DE, HL BC, DE, HL BC, DE rpa rpa1 HL, DE, DL DE, DL n4 n8 4-bit immediate data or label 8-bit immediate data or label mem * bit 8-bit immediate data or label 2-bit immediate data or label fmem pmem FB0H to FBFH,FF0H to FFFH immediate data or label FC0H to FFFH immediate data or label addr µPD75312(A) 0000H-2F7FH immediate data or label µPD75316(A) 0000H-3F7FH immediate data or label caddr 12-bit immediate data or label faddr 11-bit immediate data or label taddr 20H to 7FH immediate data (where bit0 = 0) or label PORTn IExxx MBn PORT0 to PORT7 IEBT, IECSI, IET0, IE0, IE1, IE2, IE4, IEW MB0, MB1, MB15 *: Only even addresses can be described as mem for 8-bit data processing. 36 µPD75312(A), 75316(A) (2) Legend of operation field A : A register; 4-bit accumulator B : B register; 4-bit accumulator C : C register; 4-bit accumulator D : D register; 4-bit accumulator E : E register; 4-bit accumulator H : H register; 4-bit accumulator L : L register; 4-bit accumulator X : X register; 4-bit accumulator XA : Register pair (XA); 8-bit accumulator BC : Register pair (BC); 8-bit accumulator DE : Register pair (DE); 8-bit accumulator HL : Register pair (HL); 8-bit accumulator PC : Program counter SP : Stack pointer CY : Carry flag; or bit accumulator PSW : Program status word MBE : Memory bank enable flag PORTn : Port n (n = 0 to 7) IME : Interrupt mask enable flag IExxx : Interrupt enable flag MBS : Memory bank selector register PCC . : Processor clock control register : Delimiter of address and bit (xx) : Contents addressed by xx xxH : Hexadecimal data 37 µPD75312(A), 75316(A) (3) Symbols in addressing area field *1 MB = MBE . MBS (MBS = 0, 1, 15) *2 MB = 0 *3 MBE = 0 : MB = 0 (00H-7FH) MB = 15 (80H-FFH) MBE = 1 : MB = MBS (MBS = 0, 1, 15) *4 MB = 15, fmem = FB0H-FBFH, FF0H-FFFH *5 MB = 15, pmem = FC0H-FFFH *6 µPD75312(A) addr = 0000H-2F7FH µPD75316(A) addr = 0000H-3F7FH *7 addr = (Current PC) – 15 to (Current PC) – 1 (Current PC) + 2 to (Current PC) + 16 *8 µPD75312(A) caddr = 0000H-0FFFH (PC 13 = 0, PC 12 = 0) or 1000H-1FFFH (PC 13 = 0, PC 12 = 1) or 2000H-2F7FH (PC 13 = 1, PC12 = 0) µPD75316(A) caddr = 0000H-0FFFH 1000H-1FFFH 2000H-2FFFH 3000H-3F7FH *9 faddr = 0000H-07FFH *10 taddr = 0020H-007FH Remarks 1: (PC 13 (PC 13 (PC 13 (PC 13 Data memory addressing = = = = 0, 0, 1, 1, PC 12 PC 12 PC 12 PC12 = = = = Program memory addressing 0) or 1) or 0) or 1) MB indicates memory bank that can be accessed. 2: In *2, MB = 0 regardless of MBE and MBS. 3: In *4 and *5, MB = 15 regardless of MBE and MBS. 4: *6 to *10 indicate areas that can be addressed. (4) Machine cycle field In this field, S indicates the number of machine cycles required when an instruction having a skip function skips. The value of S varies as follows: • When no instruction is skipped .................................................................................. S = 0 • When 1-byte or 2-byte instruction is skipped ........................................................... S = 1 • When 3-byte instruction (BR ! addr or CALL ! addr) is skipped ............................ S = 2 Note : The GETI instruction is skipped in one machine cycle. One machine cycle equals to one cycle of the CPU clock Φ, (=tCY), and can be changed in three steps depending on the setting of the processor clock control register (PCC). 38 µPD75312(A), 75316(A) Instructions Mnemonics Transfer MOV XCH Table Re- MOVT ference Arith- ADDS metic Operand Machine Bytes Cycles 1 1 A ← n4 reg1, #n4 2 2 reg1 ← n4 XA, #n8 2 2 XA ← n8 String effect A HL, #n8 2 2 HL ← n8 String effect B rp2, #n8 2 2 rp2 ← n8 A, @HL 1 1 A ← (HL) A, @rpa1 1 1 A ← (rpa1) *2 XA, @HL 2 2 XA ← (HL) *1 @HL, A 1 1 (HL) ← A *1 @HL, XA 2 2 (HL) ← XA *1 A, mem 2 2 A ← (mem) *3 XA, mem 2 2 XA ← (mem) *3 mem, A 2 2 (mem) ← A *3 *3 mem, XA 2 2 (mem) ← XA A, reg 2 2 A ← reg XA, rp 2 2 XA ← rp reg1, A 2 2 reg1 ← A rp1, XA 2 2 rp1 ← XA 1 1 A ↔ (HL) 1 1 A ↔ (rpa1) *2 XA, @HL 2 2 XA ↔ (HL) *1 A, mem 2 2 A ↔ (mem) *3 XA, mem 2 2 XA ↔ (mem) *3 A, reg1 1 1 A ↔ reg1 XA, rp 2 2 XA ↔ rp XA, @PCDE 1 3 XA ← (PC13-8+DE)ROM *1 XA ← (PC13-8+XA)ROM XA, @PCXA 1 3 A, #n4 1 1+S A ← A+n4 A, @HL 1 1+S A ← A+(HL) carry *1 A, CY ← A+(HL)+CY *1 A ← A-(HL) *1 1 A, CY ← A-(HL)-CY *1 A, @HL 1 1 SUBS A, @HL 1 1+S SUBC A, @HL 1 Accumu- RORC lator Manipu- NOT lation *1 A, @HL ADDC XOR String effect A A, @rpa1 tion OR Skip Conditions A, #n4 Opera- AND Operation Addressing Area A, #n4 2 2 A ← A ∧ n4 A, @HL 1 1 A ← A ∧ (HL) A, #n4 2 2 A ← A ∨ n4 A, @HL 1 1 A ← A ∨ (HL) A, #n4 2 2 A ← A ∨ n4 A, @HL 1 1 A ← A ∨ (HL) A 1 1 CY ← A0, A3 ← CY, An-1 ← An A 2 2 A←A carry borrow *1 *1 *1 39 µPD75312(A), 75316(A) Instructions Mnemonics Incre- INCS ment/ Decrement DECS Compare SKE Operand Operation Addressing Area Skip Conditions reg 1 1+S reg ← reg+1 @HL 2 2+S (HL) ← (HL)+1 *1 (HL) = 0 mem 2 2+S (mem) ← (mem)+1 *3 (mem) = 0 reg 1 1+S reg ← reg-1 reg = FH reg, #n4 2 2+S Skip if reg = n4 reg = n4 @HL, #n4 2 2+S Skip if (HL) = n4 A, @HL 1 1+S Skip if A = (HL) A, reg 2 2+S Skip if A = reg reg = 0 *1 (HL) = n4 *1 A = (HL) A = reg Carry SET1 CY 1 1 CY ← 1 flag CLR1 CY 1 1 CY ← 0 Manipu- SKT CY 1 1+S lation CY 1 1 CY ← CY mem.bit 2 2 (mem.bit) ← 1 *3 Bit fmem.bit 2 2 (fmem.bit) ← 1 *4 Manipu- pmem.@L 2 2 (pmem7-2 + L 3-2.bit(L1-0)) ← 1 *5 lation @H+mem.bit 2 2 (H + mem 3-0.bit) ← 1 *1 mem.bit 2 2 (mem.bit) ← 0 *3 fmem.bit 2 2 (fmem.bit) ← 0 *4 pmem.@L 2 2 (pmem 7-2 + L 3-2.bit(L1-0)) ← 0 *5 @H+mem.bit 2 2 (H+mem3-0.bit) ← 0 *1 mem.bit 2 2+S Skip if (mem.bit) = 1 *3 fmem.bit 2 2+S Skip if (fmem.bit) = 1 *4 (fmem.bit) = 1 pmem.@L 2 2+S Skip if (pmem 7-2+L 3-2.bit (L1-0 )) = 1 *5 (pmem.@L) = 1 @H+mem.bit 2 2+S Skip if (H + mem 3-0.bit) = 1 *1 (@H+mem.bit) = 1 mem.bit 2 2+S Skip if (mem.bit) = 0 *3 (mem.bit) = 0 fmem.bit 2 2+S Skip if (fmem.bit) = 0 *4 (fmem.bit) = 0 (pmem.@L) = 0 NOT1 Memory/ SET1 CLR1 SKT SKF AND1 OR1 XOR1 Skip if CY = 1 CY = 1 (mem.bit) = 1 pmem.@L 2 2+S Skip if (pmem7-2 +L3-2.bit (L1-0)) = 0 *5 @H+mem.bit 2 2+S Skip if (H + mem 3-0.bit) = 0 *1 (@H+mem.bit) = 0 2 2+S Skip if (fmem.bit) = 1 and clear *4 (fmem.bit) = 1 pmem.@L 2 2+S Skip if (pmem 7-2+L 3-2.bit (L 1-0)) = 1 and clear *5 (pmem.@L) = 1 @H+mem.bit 2 2+S Skip if (H+mem 3-0.bit) = 1 and clear *1 (@H+mem.bit) = 1 SKTCLR fmem.bit 40 Machine Bytes Cycles CY,fmem.bit 2 2 CY ← CY ∧ (fmem.bit) *4 CY,pmem.@L 2 2 CY ← CY ∧ (pmem 7-2+L 3-2.bit(L1-0)) *5 CY,@H+mem.bit 2 2 CY ← CY ∧ (H+mem3-0.bit) *1 CY,fmem.bit 2 2 CY ← CY ∨ (fmem.bit) *4 CY,pmem.@L 2 2 CY ← CY ∨ (pmem 7-2+L3-2.bit (L1-0)) *5 CY,@H+mem.bit 2 2 CY ← CY ∨ (H+mem3-0.bit) *1 CY,fmem.bit 2 2 CY ← CY ∨ (fmem.bit) *4 CY,pmem.@L 2 2 CY ← CY ∨ (pmem 7-2+L 3-2.bit (L 1-0)) *5 CY,@H+mem.bit 2 2 CY ← CY ∨ (H+mem3-0.bit) *1 µPD75312(A), 75316(A) Instructions Mnemonics Branch BR Operand Machine Bytes Cycles — — PC13-0 ← addr (The most suitable instruction is selectable from among BR !addr, BRCB !caddr, and BR $addr depending on the assembler.) *6 !addr 3 3 PC13-0 ← addr *6 $addr 1 2 PC13-0 ← addr *7 !caddr 2 2 PC13-0 ← PC13,12 + caddr11-0 *8 !addr 3 3 (SP-4)(SP-1)(SP-2) ← PC11-0 (SP-3) ← MBE, 0, PC13 , PC12 PC13-0 ← addr, SP ← SP-4 *6 !faddr 2 2 (SP-4)(SP-1)(SP-2) ← PC11-0 (SP-3) ← MBE, 0, PC13 , PC12 PC13-0 ← 00, faddr, SP ← SP-4 *9 RET 1 3 MBE, PC13 , PC12 ← (SP+1) 3, 1, 0 PC11-0 ← (SP)(SP+3)(SP+2) SP ← SP+4 RETS 1 3+S MBE, PC13 , PC12 ← (SP+1) 3, 1, 0 PC11-0 ← (SP)(SP+3)(SP+2) SP ← SP+4, then skip unconditionally RETI 1 3 PC13, PC 12 ← (SP+1)1, 0 PC11-0 ← (SP)(SP+3)(SP+2) PSW ← (SP+4)(SP+5), SP ← SP+6 1 1 (SP-1)(SP-2) ← rp, SP ← SP-2 Subrou- CALL tine/ Stack Inter- Operation addr BRCB Control Addressing Area CALLF PUSH rp BS 2 2 (SP-1) ← MBS, (SP-2) ← 0, SP ← SP-2 POP rp 1 1 rp ← (SP+1)(SP), SP ← SP+2 BS 2 2 MBS ← (SP+1), SP ← SP+2 2 2 IME ← 1 IExxx 2 2 IExxx ← 1 2 2 IME ← 0 EI rupt Control DI I/O IN OUT IExxx 2 2 IExxx ← 0 A,PORTn 2 2 A ← PORTn (n = 0-7) XA,PORTn 2 2 XA ← PORTn+1,PORTn (n = 4, 6) PORTn,A 2 2 PORTn ← A (n = 2-7) PORTn,XA 2 2 PORTn+1,PORTn ← XA (n = 4, 6) CPU HALT 2 2 Set HALT Mode (PCC.2 ← 1) Control STOP 2 2 Set STOP Mode (PCC.3 ← 1) NOP 1 1 No Operation Special SEL MBn 2 2 GETI taddr 1 3 MBS ← n (n = 0, 1, 15) . Where TBR instruction, PC13-0 ← (taddr)5-0 +(taddr+1) ......................................................... . Where TCALL instruction, (SP-4)(SP-1)(SP-2) ← PC11-0 (SP-3) ← MBE, 0, PC13, PC 12 PC13-0 ← (taddr)5-0 +(taddr+1) SP ← SP-4 ......................................................... . Except for TBR and TCALL instructions, Instruction execution of (taddr)(taddr+1) Skip Conditions Undefined *10 ............................. ............................. Depends on referenced instruction Note: When executing the IN/OUT instruction, MBE = 0, or MBE = 1, and MBS = 15. Remarks: The TBR and TCALL instructions are the assembler pseudo-instructions for the table definition of GETI instruction. 41 µPD75312(A), 75316(A) 10. SELECTION OF MASK OPTION The following mask operations are available and can be specified for each pin. Pin 42 Mask Option P40-P43, P50-P53 • With pull-up resistor (Specification in bit units) • Without pull-up resistor (Specification in bit units) VLC0-VLC2, BIAS • With dividing resistor for LCD drive power source (Specification in 4-bit units) • Without dividing resistor for LCD drive power source (Specification in 4-bit units) µPD75312(A), 75316(A) 11. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (Ta = 25°C) Parameter Supply Voltage Input Voltage Symbol Conditions Ratings VDD VI1 Other than ports 4, 5 VI2 Ports 4, 5 w/pull-up resistor -0.3 to +7.0 V -0.3 to V DD+0.3 V -0.3 to V DD+0.3 Open drain Output Voltage VO High-Level Output IOH 1 pin Current All pins Low-Level Output IOL* 1 pin Current Other than ports 0, 2, 3, 5 Total of ports 4, 6, 7 Unit -0.3 to +11 V V -0.3 to V DD+0.3 V Peak -10 mA rms -5 mA Peak -30 mA rms -5 mA Peak 10 mA rms 5 mA Peak 100 mA rms 60 mA Peak 100 mA rms 50 mA Operating Temperature Topt -40 to +85 °C Storage Temperature Tstg -65 to +150 °C *: rms = Peak value x √Duty CAPACITANCE (Ta = 25°C, VDD = 0 V) Parameter Symbol Input Capacitance C IN Output Capacitance C OUT Input/Output Capacitance C IO Conditions f = 1 MHz Pins other than thosemeasured are at 0 V MIN. TYP. MAX. Unit 15 pF 15 pF 15 pF 43 µPD75312(A), 75316(A) MAIN SYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS (Ta = -40 to +85°C, V DD = 2.7 to 6.0 V) Oscillator Recommended Constants Ceramic *3 Item Conditions Oscillation frequency(fX)*1 X1 X2 C1 C2 MIN. TYP. 1.0 MAX. 5.0 Oscillation stabiliza- After VDD came to tion time*2 MIN. of oscillation voltage range *3 4 Unit MHz ms VDD Crystal *3 Oscillation frequency (fX)*1 X1 X2 C1 1.0 4.19 Oscillation stabiliza- VDD = 4.5 to 6.0 V tion time*2 5.0 *3 MHz 10 ms 30 ms C2 VDD External Clock X1 input frequency (f X)*1 X1 X2 µ PD74HCU04 X1 input high-, low-level widths (t XH, t XL) 3 1.0 5.0 * 100 500 MHz ns *1: The oscillation frequency and X1 input frequency are indicated only to express the characteristics of the oscillator circuit. For instruction execution time, refer to AC Characteristics. 2: Time required for oscillation to stabilize after V DD reaches the minimum value of the oscillation voltage range or the STOP mode has been released. 3: When the oscillation frequency is 4.19 MHz < fx ≤ 5.0 MHz, do not select PCC = 0011 as the ★ instruction execution time: otherwise, one machine cycle is set to less than 0.95 µs, falling short of the rated minimum value of 0.95 µs. SUBSYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS (Ta = -40 to +85°C, V DD = 2.7 to 6.0 V) Oscillator Recommended Constants Crystal XT1 Conditions Oscillation frequency (fXT) XT2 R C3 Item MIN. TYP. MAX. 32 32.768 35 kHz 1.0 2 s 10 s Oscillation stabiliza- VDD = 4.5 to 6.0 V tion time* C4 Unit VDD External Clock XT1 XT2 Open *: 32 100 kHz XT1 input high-, low-level widths (tXTH, t XTL ) 5 15 µs Time required for oscillation to stabilize after VDD reaches the minimum value of the oscillation voltage range. 44 XT1 input frequency (f XT)* µPD75312(A), 75316(A) Note: When using the oscillation circuit of the main system clock and subsystem clock, wire the portion enclosed in dotted line in the figures as follows to avoid adverse influences on the wiring capacity: • Keep the wiring length as short as possible. • Do not cross the wiring over the other signal lines. Do not route the wiring in the vicinity of lines through which a high alternating current flows. • Always keep the ground point of the capacitor of the oscillator circuit at the same potential as VDD. Do not connect the power source pattern through which a high current flows. • Do not extract signals from the oscillation circuit. The amplification factor of the subsystem clock oscillation circuit is designed to be low to reduce the current dissipation and therefore, the subsystem clock oscillation circuit is influenced by noise more easily than the main system clock oscillation circuit. When using the subsystem clock, therefore, exercise utmost care in wiring the circuit. 45 µPD75312(A), 75316(A) DC CHARACTERISTICS (Ta = -40 to +85°C, V DD = 2.7 to 6.0 V) Parameter High-Level Input Voltage Low-level Input Voltage High-Level Output Voltage Low-Level Output Voltage High-Level Input Leakage Current Low-Level Input Leakage Current High-Level Output Leakage Current Low-Level Output Leakage Current Symbol Conditions MIN. TYP. MAX. Unit VIH1 Ports 2, 3 0.7V DD VDD V VIH2 Ports 0, 1, 6, 7, RESET 0.8VDD VDD V VIH3 Ports 4, 5 w/pull-up resistor 0.7VDD VDD V Open-drain 0.7V DD 10 V VDD-0.5 VDD V VIH4 X1, X2, XT1 VIL1 Ports 2, 3, 4, 5 0 0.3VDD V VIL2 Ports 0, 1, 6, 7, RESET 0 0.2VDD V VIL3 X1, X2, XT1 0 0.4 V VOH1 Ports 0, 2, 3, 6, 7 and BIAS VOH2 BP0-7 (with two I OH outputs) VOL1 Ports 0, 2, 3, 4, 5, 6, 7, and 8 Ports 3, 4, and 5 VDD = 4.5 to 6.0 V IOL = -15 mA VDD = 4.5 to 6.0 V IOH = -1 mA VDD-1.0 V IOH = -100 µA VDD-0.5 V VDD = 4.5 to 6.0 V IOH = -100 µA VDD-2.0 V IOH = -30 µA VDD-1.0 V 0.2 1.0 V VDD = 4.5 to 6.0 V IOL = 1.6 mA 0.4 V IOL = 400 µA 0.5 V 0.2V DD V V SB0, 1 Open-drain Pull-up resistor ≥ 1 kΩ VOL2 BP0-7 (with two IOL outputs) VDD = 4.5 to 6.0 V IOL = 100 µA 1.0 IOL = 50 µA 1.0 V ILIH1 VIN = VDD Other than below 3 µA X1, X2, XT1 20 µA ILIH3 VIN = 10 V Ports 4, 5 (open-drain) 20 µA ILIL1 VIN = 0 V Other than below -3 µA X1, X2, XT1 -20 µA ILIH2 ILIL2 ILOH1 VOUT = VDD Other than below 3 µA ILOH2 VOUT = 10 V Ports 4, 5 (open-drain) 20 µA ILOL VOUT = 0 V -3 µA 80 kΩ Internal Pull-Up Resistor RL1 RL2 Ports 0, 1, 2, 3, 6, 7 VDD = 5.0 V±10% (except P00) VIN = 0V VDD = 3.0 V±10% Ports 4, 5 VOUT = VDD -2.0 V LCD Drive Voltage VLCD LCD Step-down Resistor RLCD LCD Output Voltage Deviation (Common) *1 VODC IO = ±5 µA LCD Output Voltage Deviation (Segment) VODS IO = ±1 µA VDD = 5.0 V±10% VDD = 3.0 V±10% 15 300 kΩ 70 kΩ 10 60 kΩ 2.5 VDD V 15 60 VLCD0 = V LCD VLCD1 = V LCD×2/3 VLCD2 = V LCD×1/3 2.7 V ≤ VLCD ≤ VDD 40 30 40 150 kΩ 0 100 ±0.2 V 0 ±0.2 V (to be cont'd) 46 µPD75312(A), 75316(A) (cont'd) Parameter Symbol Supply Current * 2 IDD1 IDD2 IDD3 IDD4 IDD5 Conditions 4.19 MHz*3 crystal oscillator C1 = C2 = 22pF kHz*6 32 crystal oscillato XT1 = 0 V STOP mode TYP. MAX. Unit VDD = 5 V±10%* 4 2.5 8 mA V±10%* 5 VDD = 3 MIN. HALT mode 0.35 1.2 mA VDD = 5 V±10% 500 1500 µA VDD = 3 V±10% 150 450 µA VDD = 3 V±10% 30 90 µA HALT mode 5 15 µA VDD = 3 V±10% VDD = 5 V±10% 0.5 20 µA VDD = 3 V±10% 0.1 10 µA 0.1 5 µA Ta = 25°C *1: "Voltage deviation" means the difference between the ideal segment or common output value (VLCDn: n = 0, 1, 2) and output voltage. 2: Currents for the built-in pull-up resistor and the LCD step-down resistor are not included. 3: Including when the subsystem clock is operated. 4: When operand in the high-speed mode with the processor clock control register (PCC) set to 0011. 5: When operated in the low-speed mode with the PCC set to 0000. 6: When operated with the subsystem clock by setting the system clock control register (SCC) to 1001 to stop the main system clock operation. 47 µPD75312(A), 75316(A) AC CHARACTERISTICS (Ta = -40 to +85°C, V DD = 2.7 to 6.0 V) Parameter Symbol Conditions w/main system clock MIN. VDD = 4.5 to 6.0 V TYP. MAX. Unit 0.95 64 µs 3.8 64 µs 125 µs CPU Clock Cycle Time (Minimum Instruction Execution Time = 1 Machine Cycle)*1 tCY TI0 Input Frequency fTI VDD = 4.5 to 6.0 V 0 1 MHz 0 275 kHz TI0 Input High-, LowLevel Widths tTIH, tTIL VDD = 4.5 to 6.0 V 0.48 µs 1.8 µs Interrupt Input High-, Low-Level Widths tINTH, tINTL INT0 *2 µs INT1, 2, 4 10 µs 10 µs RESET Low-Level Width tRSL 10 µs w/sub-system clock 114 KR0-7 122 *1: The CPU clock ( Φ) cycle time is tCY vs VDD determined by the oscillation frequency of the connected oscillator, system clock (with main system clock) 70 control register (SCC), and processor 64 30 clock control register (PCC). The figure on the right is cycle time tCY 6 vs. supply voltage V DD characteristics 5 at the main system clock. 2: 2tCY or 128/fX depending on the setting Cycle time tCY [µs] of the interrupt mode register (IM0). Operation guaranteed range 4 3 2 1 0.5 0 1 2 3 4 Supply voltage VDD [V] 48 5 6 µPD75312(A), 75316(A) SERIAL TRANSFER OPERATION Two-Line and Three-Line Serial I/O Modes (SCK: internal clock output) Parameter SCK Cycle Time SCK High-, Low-Level Widths Symbol tKCY1 tKL1 Conditions MIN. VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V tKH1 ns ns tKCY1/2-50 ns tKCY1/2-150 ns 150 ns 400 RL = 1 kΩ, CL = 100 pF* Unit 1600 SI Hold Time (vs. SCK ↑ ) tKSI1 tKSO1 MAX. 3800 SI Set-Up Time (vs. SCK ↑) tSIK1 SCK ↓→ SO Output Delay Time TYP. ns VDD = 4.5 to 6.0 V 250 ns 1000 ns MAX. Unit TWO-LINE AND THREE-LINE SERIAL I/O MODES (SCK: external clock input) Parameter SCK Cycle Time SCK High-, Low-Level Widths Symbol tKCY2 tKL2 Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V tKH2 SI Set-Up Time (vs. SCK ↑) tSIK2 SI Hold Time (vs. SCK ↑) tKSI2 SCK ↓→ SO Output Delay Time tKSO2 MIN. TYP. 800 ns 3200 ns 400 ns 1600 ns 100 ns 400 RL = 1 kΩ, CL = 100 pF* VDD = 4.5 to 6.0 V ns 300 ns 1000 ns *: RL and CL are load resistance and load capacitance of the SO output line. 49 µPD75312(A), 75316(A) SBI MODE (SCK: internal clock output (master)) Parameter SCK Cycle Time Symbol tKCY3 Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V MIN. TYP. MAX. Unit 1600 ns 3800 ns tKCY3/2-50 ns tKCY3/2-150 ns 150 ns tKCY3/2 ns SCK High-, Low-Level Widths tKL3 tKH3 SB0, 1 Set-Up Time (vs. SCK ↑ ) tSIK3 SB0, 1 Hold Time (vs. SCK ↑ ) tKSI3 SCK ↓→ SB0, 1 Output Delay Time tKSO3 SCK ↑→ SB0, 1 ↓ tKSB tKCY3 ns SB0,1 ↓→ SCK tSBK tKCY3 ns SB0, 1 Low-Level Width tSBL tKCY3 ns SB0, 1 High-Level Width tSBH tKCY3 ns RL = 1 kΩ, CL = 100 pF* VDD = 4.5 to 6.0 V 0 250 0 1000 ns ns SBI MODE (SCK: external clock input (slave)) Parameter SCK Cycle Time Symbol tKCY4 Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V MIN. TYP. MAX. ns 3200 ns SCK High-, Low-Level Widths tKL4 tKH4 SB0, 1 Set-Up Time (vs. SCK ↑ ) tSIK4 SB0, 1 Hold Time (vs. SCK ↑ ) tKSI4 SCK ↓→ SB0, 1 Output Delay Time tKSO4 SCK ↑→ SB0, 1 ↓ tKSB tKCY4 ns SB0,1 ↓→ SCK ↓ tSBK tKCY4 ns SB0, 1 Low-Level Width tSBL tKCY4 ns SB0, 1 High-Level Width tSBH tKCY4 ns RL = 1 kΩ, CL = 100 pF* VDD = 4.5 to 6.0 V 400 ns 1600 ns 100 ns tKCY4/2 ns 0 300 ns 0 1000 ns *: RL and C L are load resistance and load capacitance of the SB0 and SB1 output lines. 50 Unit 800 µPD75312(A), 75316(A) AC TIMING TEST POINT (excluding X1 and XT1 inputs) 0.8 VDD 0.8 VDD Test points 0.2 VDD 0.2 VDD CLOCK TIMING 1/fX tXL tXH X1 input VDD –0.5V 0.4 V 1/fXT tXTL tXTH XT1 input VDD –0.5V 0.4 V TI0 TIMING 1/fTI tTIL tTIH TI0 51 µPD75312(A), 75316(A) SERIAL TRANSFER TIMING THREE-LINE SERIAL I/O MODE: tKCY1 tKL1 tKH1 SCK tSIK1 SI tKSI1 Input data tKSO1 Output data SO TWO-LINE SERIAL I/O MODE: tKCY2 tKH2 tKL2 SCK tKSO2 SB0,1 52 tSIK2 tKSI2 µPD75312(A), 75316(A) SERIAL TRANSFER TIMING BUS RELEASE SIGNAL TRANSFER: t KCY3,4 tKL3,4 tKH3,4 SCK tKSB tSBL tSBH tSIK3,4 tSBK tKSI3,4 SB0,1 tKSO3,4 COMMAND SIGNAL TRANSFER: tKCY3,4 tKL3,4 tKH3,4 SCK tKSB tSIK3,4 tSBK tKSI3,4 SB0,1 tKSO3,4 INTERRUPT INPUT TIMING: tINTL tINTH INT0, 1, 2, 4 KR0-7 RESET INPUT TIMING: tRSL RESET 53 µPD75312(A), 75316(A) LOW-VOLTAGE DATA RETENTION CHARACTERISTICS OF DATA MEMORY IN STOP MODE (Ta = –40 to +85°C) Parameter Symbol Data Retention Supply Voltage VDDDR Data Retention Supply Current*1 IDDDR Release Signal Set Time tSREL Oscillation Stabilization tWAIT Conditions MIN. TYP. MAX. Unit 6.0 V 10 µA 2.0 VDDDR = 2.0 V 0.1 µs 0 Released by RESET Wait Time*2 Released by interrupt 217 /fX ms *3 ms *1: Does not include current flowing through internal pull-up resistor 2: The oscillation stabilization wait time is the time during which the CPU is stopped to prevent unstable operation when oscillation is started. 3: Depends on the setting of the basic interval timer mode register (BTM) as follows: BTM3 BTM2 BTM1 BTM0 – 0 0 0 220/fX (approx. 250 ms) – 0 1 1 217/fX (approx. 31.3 ms) – 1 0 1 215/fX (approx. 7.82 ms) – 1 1 1 213/fX (approx. 1.95 ms) DATA RETENTION TIMING WAIT time ( ): fX = 4.19 MHz (releasing STOP mode by RESET) Internal reset operation HALT mode STOP mode Operation mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT DATA RETENTION TIMING (standby release signal: releasing STOP mode by interrupt) HALT mode STOP mode Operation mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT 54 µPD75312(A), 75316(A) PACKAGE DRAWINGS 80 PIN PLASTIC QFP (14×20) A B 41 40 64 65 F Q 5°±5° S D C detail of lead end 25 24 80 1 G H I M J K M P 12. N L P80GF-80-3B9-2 NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 23.6 ± 0.4 0.929 ± 0.016 B 20.0 ± 0.2 0.795 +0.009 –0.008 C 14.0 ± 0.2 0.551+0.009 –0.008 D 17.6 ± 0.4 0.693 ± 0.016 F 1.0 0.039 G 0.8 0.031 H 0.35 ± 0.10 0.014 +0.004 –0.005 I 0.15 0.006 J 0.8 (T.P.) 0.031 (T.P.) K 1.8 ± 0.2 0.071 –0.009 L 0.8 ± 0.2 0.031+0.009 –0.008 M 0.15+0.10 –0.05 0.006+0.004 –0.003 N 0.15 0.006 P 2.7 Q 0.1 ± 0.1 S 3.0 MAX. +0.008 0.106 0.004 ± 0.004 0.119 MAX. 55 µPD75312(A), 75316(A) 13. RECOMMENDED SOLDERING CONDITIONS It is recommended that µ PD75316(A) be soldered under the following conditions. For details on the recommended soldering conditions, refer to Information Document "Semiconductor Devices Mounting Manual" (IEI-616). The soldering methods and conditions are not listed here, consult NEC. Table 13-1 Soldering Conditions µPD75312GF(A) - xxx - 3B9: 80-pin plastic QFP (14×20 mm) µPD75316GF(A) - xxx - 3B9: 80-pin plastic QFP (14×20 mm) Soldering Method Soldering Conditions Symbol for Recommended Condition Infrared Reflow Package peak temperature: 230°C, time: 30 seconds max. (210°C min.), number of times: 1 IR30-00-1 VPS Package peak temperature: 215°C, time: 40 seconds max. (200°C min.), number of times: 1 VP15-00-1 Wave Soldering Soldering bath temperature: 260°C max., time: 10 seconds max., number of times: 1, pre-heating temperature: 120°C max. (package surface temperature) WS60-00-1 Pin Partial Heating Pin temperature: 300°C max., time: 3 seconds max. (per side) — Caution: Do not use two or more soldering methods in combination (except the pin partial heating method). Notice A model that can be soldered under the more stringent conditions (infrared reflow peak temperature: 235°C, number of times: 2, and an extended number of days) is also available. For details, consult NEC. 57 µPD75312(A), 75316(A) APPENDIX A. COMPARISION OF FEATURES AMONG THIS SERIES PRODUCTS Product Item µ PD75304(A) µPD75306(A) µPD75308(A) µPD75312(A) µPD75316(A) ROM Configuration ROM (bits) 512 × 4 (bank 0, 1 : 256 × 4) 3-byte Branch Instruction None Program Counter Mask Option Commonly provided 12 bits 13 bits Directly Driving LED Operating Supply Voltage Range DC Characteristics 14 bits 14 bits Not offered None Offered Not offered Offered 2.7 to 6.0 V 5 V ± 5% 5 V ± 5% 2.7 to 6.0 V Differ in high-level output current and low-level output current Differ in low-level output voltage Quality Grade Special • 80-pin plastic QFP (14 × 20 mm) Package *1: For the µPD75P316, only the one-time PROM is provided. 2: 1024 × 4 (Banks 0, 1, 2, 3, 15 : 256 × 4) 58 4 13 bits • Pull-up resistor for Ports 4, 5 • Dividing resistor for LCD driving supply voltage VPP, PROM Programming Pin Connections Absolute Maximum Ratings *2 Provided Others Electrical Characteristics µPD75P316A 0000H-177FH 0000H-1F7FH 0000H-2F7FH 0000H-3F7FH 0000H-1F7FH 0000H-3F7FH 0000H-3F7FH 6016 × 8 8064 × 8 12160 × 8 16256 × 8 8064 × 8 16256 × 8 16256 × 8 RAM (bits) Instruction Set µPD75P316 EPROM/One-time PROM*1 Mask ROM 000H-FFFH 4096 × 8 µPD75P308 Standard • 80-pin plastic QFP (14 × 20 mm) • 80-pin ceramic LCC w/ window • 80-pin plastic QFP (14 × 20 mm) • 80-pin plastic QFP (14 × 20 mm) • 80-pin ceramic LCC w/ window µPD75312(A), 75316(A) ★ APPENDIX B. DEVELOPMENT TOOLS The following development support tools are readily available to support development of systems using µPD75312(A) and 75316(A): Hardware IE-75000-R *1 IE-75001-R In-circuit emulator for 75X series IE-75000-R-EM *2 Emulation board for IE-75000-R and IE-75001-R EP-75308GF-R Emulation prove for µPD75312GF(A) and 75316GF(A), provided with 80-pin conversion socket EV-9200G-80. EV-9200G-80 Software PG-1500 PROM programmer PA-75P308GF PROM programmer adapter solely used for µPD75P316GF and 75P316AGF. It is connected to PG-1500. IE Control Program Host machine PC-9800 series (MS-DOSTM Ver.3.30 to Ver.5.00A*3 ) PG-1500 Controller IBM PC/AT TM (PC DOSTM Ver.3.1) RA75X Relocatable Assembler *1: Maintenance product 2: Not provided with IE-75001-R. 3: Ver.5.00/5.00A has a task swap function, but this function cannot be used with this function. Remarks: For development tools from other companies, refer to 75X Series Selection Guide (IF-151). 59 µPD75312(A), 75316(A) APPENDIX C. RELATED DOCUMENTS 60 µPD75312(A), 75316(A) GENERAL NOTES ON CMOS DEVICES ➀ STATIC ELECTRICITY (ALL MOS DEVICES) Exercise care so that MOS devices are not adversely influenced by static electricity while being handled. The insulation of the gates of the MOS device may be destroyed by a strong static charge. Therefore, when transporting or storing the MOS device, use a conductive tray, magazine case, or conductive buffer materials, or the metal case NEC uses for packaging and shipment, and use grounding when assembling the MOS device system. Do not leave the MOS device on a plastic plate and do not touch the pins of the device. Handle boards on which MOS devices are mounted similarly . ➁ PROCESSING OF UNUSED PINS (CMOS DEVICES ONLY) Fix the input level of CMOS devices. Unlike bipolar or NMOS devices, if a CMOS device is operated with nothing connected to its input pin, intermediate level input may be generated due to noise, and an inrush current may flow through the device, causing the device to malfunction. Therefore, fix the input level of the device by using a pull-down or pull-up resistor. If there is a possibility that an unused pin serves as an output pin (whose timing is not specified), each pin should be connected to VDD or GND through a resistor. Refer to “Processing of Unused Pins” in the documents of each devices. ➂ STATUS BEFORE INITIALIZATION (ALL MOS DEVICES) The initial status of MOS devices is undefined upon power application. Since the characteristics of an MOS device are determined by the quantity of injection at the molecular level, the initial status of the device is not controlled during the production process. The output status of pins, I/O setting, and register contents upon power application are not guaranteed. However, the items defined for reset operation and mode setting are subject to guarantee after the respective operations have been executed. When using a device with a reset function, be sure to reset the device after power application. 61 µPD75312(A), 75316(A) [MEMO] No p art of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties b y or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for uses in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for the applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime system, etc. M4 92.6 MS-DOS is a trademark of Microsoft Corporation. PC DOS and PC/AT are trademarks of IBM Corporation. 62