EPSON S1D13700

S1D13700 Embedded Memory Graphics LCD Controller
Hardware Functional Specification
Document Number: X42A-A-001-00
Status: Revision 1.0
Issue Date: 2004/01/06
Copyright © 2002, 2004 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners
Page 2
Epson Research and Development
Vancouver Design Center
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S1D13700
X42A-A-001-00
Hardware Functional Specification
Issue Date: 2004/01/06
Revision 1.0
Epson Research and Development
Vancouver Design Center
Page 3
Table of Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2 Overview Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2
Features . . . . . . . . .
2.1 Internal Memory . .
2.2 Host CPU Interface .
2.3 Display Support . . .
2.4 Display Modes . . .
2.5 Character Generation
2.6 Power . . . . . .
2.7 Clock Source . . . .
2.8 Package . . . . . .
3
System Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5
Pins . . . . . . . . . . . . . . . . .
5.1 Pinout Diagram . . . . . . . .
5.2 Pin Descriptions . . . . . . .
5.2.1 Host Interface . . . . . . . .
5.2.2 LCD Interface . . . . . . . .
5.2.3 Clock Input . . . . . . . . .
5.2.4 Power And Ground . . . . .
5.3 Summary of Configuration Options
5.4 Host Bus Interface Pin Mapping .
6
D.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7
A.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.1 Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3 CPU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.1 Generic Bus Direct/Indirect Interface with WAIT# Timing . . . . . . . . . . . . .
7.3.2 Generic Bus Direct/Indirect Interface without WAIT# Timing . . . . . . . . . . . .
7.3.3 MC68K Family Bus Direct/Indirect Interface with DTACK# Timing . . . . . . . .
7.3.4 MC68K Family Bus Direct/Indirect Interface without DTACK# Timing . . . . . .
7.3.5 M6800 Family Bus Indirect Interface Timing . . . . . . . . . . . . . . . . . . . .
7.4 Power Save Mode/Display Enable Timing . . . . . . . . . . . . . . . . . . .
7.5 Display Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Hardware Functional Specification
Issue Date: 2004/01/06
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S1D13700
X42A-A-001-00
Revision 1.0
Page 4
Epson Research and Development
Vancouver Design Center
8
Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
9
Clocks . . . . . . . . . . .
9.1 Clock Diagram . . . .
9.2 Clock Descriptions . .
9.2.1 System Clock . .
9.2.2 FPSHIFT Clock .
9.3 Oscillator Circuit . . .
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10 Registers . . . . . . . . . . . . . . . .
10.1 Register Set . . . . . . . . . . .
10.2 Register Restrictions . . . . . . .
10.3 Register Descriptions . . . . . . .
10.3.1 System Control Registers . . . .
10.3.2 Display Control Registers . . . .
10.3.3 Drawing Control Registers . . .
10.3.4 Gray Scale Register . . . . . . .
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11 Indirect Addressing . . .
11.1 System Control . . .
11.1.1 SYSTEM SET . .
11.1.2 POWER SAVE .
11.1.3 DISP ON/OFF . .
11.1.4 SCROLL . . . . .
11.1.5 CSRFORM . . .
11.1.6 CSRDIR . . . . .
11.1.7 OVLAY . . . . .
11.1.8 CGRAM ADR . .
11.1.9 HDOT SCR . . .
11.1.10 CSRW . . . . . .
11.1.11 CSRR . . . . . .
11.1.12 GRAYSCALE . .
11.1.13 Memory Control .
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12 Display Control Functions . . . . . . .
12.1 Character Configuration . . . . . .
12.2 Screen Configuration . . . . . . .
12.2.1 Screen Configuration . . . . . .
12.2.2 Display Address Scanning . . . .
12.2.3 Display Scan Timing . . . . . .
12.3 Cursor Control . . . . . . . . . .
12.3.1 Cursor Write Register Function .
12.3.2 Cursor Movement . . . . . . . .
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S1D13700
X42A-A-001-00
Hardware Functional Specification
Issue Date: 2004/01/06
Revision 1.0
Epson Research and Development
Vancouver Design Center
Page 5
12.3.3 Cursor Display Layers . . . . . . . .
12.4 Memory to Display Relationship . . . .
12.5 Scrolling . . . . . . . . . . . . .
12.5.1 On-Page Scrolling . . . . . . . . . .
12.5.2 Inter-Page Scrolling . . . . . . . . .
12.5.3 Horizontal Wraparound Scrolling . .
12.5.4 Bi-directional Scrolling . . . . . . .
12.5.5 Scroll Units . . . . . . . . . . . . .
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13 Character Generator . . . . . . . . . . . .
13.1 CG Characteristics . . . . . . . . .
13.1.1 Internal Character Generator . . . .
13.1.2 Character Generator RAM . . . . .
13.2 Setting the Character Generator Address .
13.2.1 CGRAM Addressing Example . . .
13.3 Character Codes . . . . . . . . . .
14 Microprocessor Interface . . . . .
14.1 System Bus Interface . . . . .
14.1.1 Generic . . . . . . . . . . .
14.1.2 M6800 Family . . . . . . . .
14.1.3 MC68K Family . . . . . . .
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15 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
15.1 Register Initialization/Initialization Parameters . . . . . . . . . . . . . . . . . 103
15.1.1 SYSTEM SET Command and Parameters . . . . . . . . . . . . . . . . . . . . . . 103
15.1.2 Initialization Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
15.1.3 Display Mode Setting Example 1: Combining Text and Graphics . . . . . . . . . . 110
15.1.4 Display Mode Setting Example 2: Combining Graphics and Graphics . . . . . . . . 112
15.1.5 Display Mode Setting Example 3: Combining Three Graphics Layers . . . . . . . . 114
15.2 System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
15.3 Smooth Horizontal Scrolling . . . . . . . . . . . . . . . . . . . . . . . . 116
15.4 Layered Display Attributes . . . . . . . . . . . . . . . . . . . . . . . . . 118
15.4.1 Inverse Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
15.4.2 Half-Tone Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
15.4.3 Flash Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
15.5 16 ¥ 16-Dot Graphic Display . . . . . . . . . . . . . . . . . . . . . . . . 121
15.5.1 Command Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
15.5.2 Kanji Character Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
16 Internal Character Generator Font
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17 Power Save Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
18 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Hardware Functional Specification
Issue Date: 2004/01/06
S1D13700
X42A-A-001-00
Revision 1.0
Page 6
Epson Research and Development
Vancouver Design Center
19 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
20 Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
S1D13700
X42A-A-001-00
Hardware Functional Specification
Issue Date: 2004/01/06
Revision 1.0
Epson Research and Development
Vancouver Design Center
Page 7
List of Tables
Table 5-1: Cell Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5-2 Host Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . .
Table 5-3 LCD Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . .
Table 5-4 Clock Input Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . .
Table 5-5 Power And Ground Pin Descriptions . . . . . . . . . . . . . . . . . . .
Table 5-6: Summary of Configuration Options . . . . . . . . . . . . . . . . . . . .
Table 5-7: Host Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . .
Table 6-3 Electrical Characteristics for VDD = 3.3V typical . . . . . . . . . . . . .
Table 6-4 Electrical Characteristics for VDD = 5.0V typical . . . . . . . . . . . . .
Table 6-5 Cell Type Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-1 Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-2 Generic Bus Direct/Indirect Interface with WAIT# Timing . . . . . . . .
Table 7-3 Generic Bus Direct/Indirect Interface without WAIT# Timing . . . . . .
Table 7-4 MC68K Family Bus Direct/Indirect Interface with DTACK# Timing . .
Table 7-5 MC68K Family Bus Direct/Indirect Interface without DTACK# Timing .
Table 7-6 M6800 Family Bus Indirect Interface Timing . . . . . . . . . . . . . . .
Table 7-7 Power Save Mode/Display Enable Timing. . . . . . . . . . . . . . . . .
Table 7-8: Single Monochrome 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . .
Table 9-1 Crystal Oscillator Circuit Parameters . . . . . . . . . . . . . . . . . . .
Table 10-1: S1D13700 Register Set. . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 10-2 LCD Parameter Summary . . . . . . . . . . . . . . . . . . . . . . . . .
Table 10-3 Screen Block 3 Attribute Selection. . . . . . . . . . . . . . . . . . . . .
Table 10-4 Screen Block 2/4 Attribute Selection . . . . . . . . . . . . . . . . . . .
Table 10-5 Screen Block Attribute Selection. . . . . . . . . . . . . . . . . . . . . .
Table 10-6 Cursor Flash Rate Selection . . . . . . . . . . . . . . . . . . . . . . . .
Table 10-7 Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 10-8 Cursor Shift Direction . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 10-9 Composition Method Selection . . . . . . . . . . . . . . . . . . . . . .
Table 10-10 Bit-Per-Pixel Selection . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-1 Indirect Addressing Command Set . . . . . . . . . . . . . . . . . . . . .
Table 11-2 Generic Indirect Addressing Command/Write/Read. . . . . . . . . . . .
Table 11-3 M6800 Indirect Addressing Command/Write/Read . . . . . . . . . . . .
Table 11-4 M68K Indirect Addressing Command/Write/Read . . . . . . . . . . . .
Table 11-5 SYSTEM SET Command and Parameters . . . . . . . . . . . . . . . . .
Table 11-6 POWER SAVE Command . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Functional Specification
Issue Date: 2004/01/06
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S1D13700
X42A-A-001-00
Revision 1.0
Page 8
Epson Research and Development
Vancouver Design Center
Table 11-7 DISP ON Command and Parameters . . . . . . . . . . . . . . . . .
Table 11-8 DISP OFF Command and Parameters . . . . . . . . . . . . . . . .
Table 11-9 SCROLL Command and Parameters . . . . . . . . . . . . . . . . .
Table 11-10CSRFORM Command and Parameters. . . . . . . . . . . . . . . .
Table 11-11CSRDIR Command. . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-12OVLAY Command and Parameters . . . . . . . . . . . . . . . . .
Table 11-13CGRAM ADR Command and Parameters . . . . . . . . . . . . . .
Table 11-14HDOT SCR Command and Parameters . . . . . . . . . . . . . . .
Table 11-15CSRW Command and Parameters . . . . . . . . . . . . . . . . . .
Table 11-16CSRR Command and Parameters . . . . . . . . . . . . . . . . . .
Table 11-17Gray Scale Command and Parameters . . . . . . . . . . . . . . . .
Table 12-1 Scrolling Unit Summary . . . . . . . . . . . . . . . . . . . . . . .
Table 13-1 Character Fonts Where Number of Lines ≤ 8 (REG[00h] bit 2 = 0) .
Table 13-2 Character Fonts Where Number of Lines ≤ 16 (REG[00h] bit 2 = 1)
Table 13-3 Character Data Example . . . . . . . . . . . . . . . . . . . . . . .
Table 14-1 Generic Interface Signals . . . . . . . . . . . . . . . . . . . . . . .
Table 14-2 M6800 Family Interface Signals . . . . . . . . . . . . . . . . . . .
Table 14-3 M6800 Family Interface Signals . . . . . . . . . . . . . . . . . . .
Table 15-1 Panel Calculations . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 15-2 Indirect Addressing Initialization Procedure . . . . . . . . . . . . .
Table 17-1 State of LCD Pins During Power Save Mode . . . . . . . . . . . .
S1D13700
X42A-A-001-00
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Hardware Functional Specification
Issue Date: 2004/01/06
Revision 1.0
Epson Research and Development
Vancouver Design Center
Page 9
List of Figures
Figure 3-1 Indirect Generic to S1D13700 Interface Example . . . . . . . . . . . . . . . . . . .
Figure 3-2 Direct Generic to S1D13700 Interface Example . . . . . . . . . . . . . . . . . . . .
Figure 3-3 Indirect MC68K to S1D13700 Interface Example . . . . . . . . . . . . . . . . . . .
Figure 3-4 Direct MC68K to S1D13700 Interface Example . . . . . . . . . . . . . . . . . . . .
Figure 3-5 Indirect M6800 to S1D13700 Interface Example . . . . . . . . . . . . . . . . . . .
Figure 4-1 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 5-1 Pinout Diagram (TQFP13 - 64 pin). . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7-1 Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7-2 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7-3 Generic Bus Direct/Indirect Interface with WAIT# Timing . . . . . . . . . . . . . .
Figure 7-4 Generic Bus Direct/Indirect Interface without WAIT# Timing . . . . . . . . . . . .
Figure 7-5 MC68K Family Bus Direct/Indirect Interface with DTACK# Timing. . . . . . . . .
Figure 7-6 MC68K Family Bus Direct/Indirect Interface without DTACK# Timing . . . . . . .
Figure 7-7 M6800 Family Bus Indirect Interface Timing . . . . . . . . . . . . . . . . . . . . .
Figure 7-8: Monochrome 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 8-1 S1D13700 Memory Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 9-1: Clock Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 9-2 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-1 Screen Origin Compensation and HDOT SCR Adjustment . . . . . . . . . . . . . .
Figure 10-2 Single Drive Panel Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-3 Dual Drive Panel Display. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-4 Horizontal and Vertical Character Size Example . . . . . . . . . . . . . . . . . . .
Figure 10-5 Horizontal Address Range and Character Bytes Per Row Relationship . . . . . . . .
Figure 10-6 Dual Panel Display Height . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-7 Cursor Size and Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-8 Cursor Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-9 Combined Layer Display Examples . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-10 Horizontal Scrolling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-1 Example of Character Display from Generator Bitmap (when [FX] ≤ 8) . . . . . . .
Figure 12-2 Character Width Greater than One Byte Wide ([FX] = 9) . . . . . . . . . . . . . . .
Figure 12-3 Virtual and Physical Screen Relationship . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-4 Display Addressing in Text Mode Example . . . . . . . . . . . . . . . . . . . . . .
Figure 12-5 Display Addressing in Graphics Mode Example . . . . . . . . . . . . . . . . . . . .
Figure 12-6 Dual Panel Display Address Indexing in Text Mode. . . . . . . . . . . . . . . . . .
Figure 12-7 Relationship Between Total Character Bytes Per Row and Character Bytes Per Row
Figure 12-8 Cursor Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-9 Cursor Display Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Functional Specification
Issue Date: 2004/01/06
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S1D13700
X42A-A-001-00
Revision 1.0
Page 10
Epson Research and Development
Vancouver Design Center
Figure 12-10 Cursor Movement . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-11 Screen Layers and Memory Relationship. . . . . . . . . . .
Figure 12-12 Virtual Display (Display Window to Memory Relationship).
Figure 12-13 Memory Map and Magnified Characters . . . . . . . . . . .
Figure 12-14 On-Page Scrolling. . . . . . . . . . . . . . . . . . . . . . .
Figure 12-15 Inter-Page Scrolling . . . . . . . . . . . . . . . . . . . . . .
Figure 12-16 Horizontal Wraparound Scrolling. . . . . . . . . . . . . . .
Figure 12-17 Bi-Directional Scrolling. . . . . . . . . . . . . . . . . . . .
Figure 13-1 Row Select Address . . . . . . . . . . . . . . . . . . . . . .
Figure 13-2 On-Chip Character Codes. . . . . . . . . . . . . . . . . . .
Figure 15-1 Initialization Procedure . . . . . . . . . . . . . . . . . . . .
Figure 15-2 Character Over Graphics Layers . . . . . . . . . . . . . . .
Figure 15-3 Two-Layer Graphics . . . . . . . . . . . . . . . . . . . . .
Figure 15-4 Three-Layer Graphics . . . . . . . . . . . . . . . . . . . . .
Figure 15-5 HDOT SCR Example . . . . . . . . . . . . . . . . . . . . .
Figure 15-6 Layer Synthesis . . . . . . . . . . . . . . . . . . . . . . . .
Figure 15-7 Half-Tone Character And Graphics. . . . . . . . . . . . . .
Figure 15-8 Flash Attribute for a Large Area . . . . . . . . . . . . . . .
Figure 15-9 Graphics Address Indexing . . . . . . . . . . . . . . . . . .
Figure 15-10 Graphics Bit Map . . . . . . . . . . . . . . . . . . . . . . .
Figure 15-11 16 ¥ 16-Dot Display Flowchart . . . . . . . . . . . . . . . .
Figure 16-1 On-Chip Character Set . . . . . . . . . . . . . . . . . . . .
Figure 18-1 Mechanical Drawing TQFP13 - 64 pin . . . . . . . . . . . .
S1D13700
X42A-A-001-00
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Hardware Functional Specification
Issue Date: 2004/01/06
Revision 1.0
Epson Research and Development
Vancouver Design Center
Page 11
1 Introduction
1.1 Scope
This is the Hardware Functional Specification for the S1D13700 Embedded Memory
Graphics LCD Controller. Included in this document are timing diagrams, AC and DC
characteristics, register descriptions, and power management descriptions. This document
is intended for two audiences: Video Subsystem Designers and Software Developers.
This document is updated as appropriate. Please check the Epson Research and Development Website at www.erd.epson.com for the latest revision of this document before
beginning any development.
We appreciate your comments on our documentation. Please contact us via email at
[email protected]
1.2 Overview Description
The S1D13700 Embedded Memory Graphics LCD Controller can display both text and
graphics on an LCD panel. The S1D13700 allows layered text and graphics, scrolling of the
display in any direction, and partitioning of the display into multiple screens. It includes
32K bytes of embedded SRAM display memory which is used to store text, character
codes, and bit-mapped graphics. The S1D13700 handles display controller functions
including: transferring data from the controlling microprocessor to the buffer memory,
reading memory data, converting data to display pixels, and generating timing signals for
the LCD panel.
The S1D13700 is designed with an internal character generator which supports 160, 5x7
pixel characters in internal mask ROM (CGROM) and 64, 8x8 pixel characters in character
generator RAM (CGRAM). When the CGROM is not used, up to 256, 8x16 pixel
characters are supported in CGRAM.
Hardware Functional Specification
Issue Date: 2004/01/06
S1D13700
X42A-A-001-00
Revision 1.0
Page 12
Epson Research and Development
Vancouver Design Center
2 Features
2.1 Internal Memory
• Embedded 32K bytes of SRAM display memory
2.2 Host CPU Interface
• Direct Address Bus support for:
• Generic Bus (Z80 family) microprocessor interface
• MC68K family microprocessor interface
• Indirect Address Bus support for:
• Generic Bus (Z80 family) microprocessor interface
• MC68K family microprocessor interface
• M6800 family microprocessor interface
• 8-bit CPU data bus interface
2.3 Display Support
• 4-bit monochrome LCD interface
• Maximum resolutions supported:
640x240 at 1 bpp
320x240 at 2 bpp
240x160 at 4 bpp
• 1/2-duty to 1/256-duty LCD drive
2.4 Display Modes
• 1/2/4 bit-per-pixel color depth support
• Text, graphics and combined text/graphics display modes
• Three overlapping screens in graphics mode
• Programmable cursor control
• Smooth horizontal scrolling of all or part of the display in monochrome mode
• Smooth vertical scrolling of all or part of the display in all modes
S1D13700
X42A-A-001-00
Hardware Functional Specification
Issue Date: 2004/01/06
Revision 1.0
Epson Research and Development
Vancouver Design Center
Page 13
2.5 Character Generation
• 160, 5x7 pixel characters in embedded mask-programmed character generator ROM
(CGROM)
• Up to 64, 8x8 pixel characters in character generator RAM (CGRAM)
• Up to 256, 8x16 pixel characters in embedded character generator RAM (when
CGROM is not used)
2.6 Power
• Software initiated power save mode
• Low power consumption
• CORE VDD 3.0 to 3.6 volts
• IO VDD 3.0 to 5.5 volts
2.7 Clock Source
• Two terminal crystal or Single Oscillator input
Input Clock (maximum 60 MHz)
FPSHIFT Clock (maximum 15 MHz)
2.8 Package
• TQFP13 - 64-pin Pb-used package
• TQFP13 - 64-pin Pb-free package (lead free)
Hardware Functional Specification
Issue Date: 2004/01/06
S1D13700
X42A-A-001-00
Revision 1.0
Page 14
Epson Research and Development
Vancouver Design Center
3 System Diagrams
Generic Bus (Indirect)
S1D13700
CNF4
AS#
CS#
Axx
Decoder
CS#
A[15:1]
A0
A0 (command or parameter)
D[15:8]
D[7:0]
D[7:0]
RD0#
RD1#
RD#
WR0#
WR#
CNF3
WR1#
WAIT#
WAIT#
RESET#
CNF2
RESET#
/RESET
Figure 3-1 Indirect Generic to S1D13700 Interface Example
S1D13700
Generic Bus (Direct)
CNF4
AS#
CS#
CS#
A[15:0]
A[15:0]
D[15:8]
D[7:0]
D[7:0]
RD0#
RD1#
RD#
WR0#
WR#
WR1#
CNF3
WAIT#
WAIT#
RESET#
CNF2
RESET#
/RESET
Figure 3-2 Direct Generic to S1D13700 Interface Example
S1D13700
X42A-A-001-00
Hardware Functional Specification
Issue Date: 2004/01/06
Revision 1.0
Epson Research and Development
Vancouver Design Center
Page 15
MC68K (Indirect)
S1D13700
CNF4
AS#
FC[2:0]
A[23:1]
AS#
Decoder
CS#
A[15:1]
A0
A0 (command or parameter)
D[15:8]
D[7:0]
D[7:0]
UDS#
LDS#
RD#
R/W#
WR#
DTACK#
WAIT#
RESET#
RESET#
CNF3
CNF2
/RESET
Figure 3-3 Indirect MC68K to S1D13700 Interface Example
S1D13700
MC68K (Direct)
CNF4
AS#
FC[2:0]
A[23:16]
AS#
Decoder
CS#
A[15:0]
A[15:0]
D[15:8]
D[7:0]
D[7:0]
UDS#
LDS#
RD#
R/W#
WR#
DTACK#
WAIT#
RESET#
RESET#
CNF3
CNF2
/RESET
Figure 3-4 Direct MC68K to S1D13700 Interface Example
Hardware Functional Specification
Issue Date: 2004/01/06
S1D13700
X42A-A-001-00
Revision 1.0
Page 16
Epson Research and Development
Vancouver Design Center
S1D13700
M6800 (Indirect)
CNF4
AS#
VMA#
Decoder
A[16:1]
CS#
A[15:1]
A0
A0 (command or parameter)
D[15:8]
D[7:0]
D[7:0]
E
RD#
R/W#
WR#
CNF3
WAIT#
RESET#
CNF2
RESET#
/RESET
Figure 3-5 Indirect M6800 to S1D13700 Interface Example
S1D13700
X42A-A-001-00
Hardware Functional Specification
Issue Date: 2004/01/06
Revision 1.0
Epson Research and Development
Vancouver Design Center
Page 17
4 Functional Block Diagram
FPDAT[3:0]
FPSHIFT
XECL
YSCL
FPLINE
FPFRAME
MOD
YDIS
LCD
Character
Generator
ROM
LCD Controller
Video
RAM
Arbitrate
Display
Address
Generator
Cursor
Address
Controller
Layered
Controller
Layered
DotClock
Generator
GrayScale
FRM Controller
Dot Counter
Internal Clock
CLKI
CNF[4:0]
RESET#
Oscillator
A0 to A15
D0 to D7
CS#
RD#
WR#
AS#
WAIT#
Microprocessor Interface
XCD1
Character
Generator RAM
XCG1
VideoRAM
Host Microprocessor
Figure 4-1 Functional Block Diagram
Hardware Functional Specification
Issue Date: 2004/01/06
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X42A-A-001-00
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5 Pins
48
D3
VSS
XCD1
XCG1
RESET#
SCANEN
TSTEN
CLKI
RD#
COREVDD
WR#
D7
CS#
D6
D5
D4
HIOVDD
5.1 Pinout Diagram
33
49
32
NIOVDD
D2
YDIS
D1
FPFRAME
D0
YSCL
VSS
VSS
WAIT#
MOD
HIOVDD
FPLINE
CNF0
COREVDD
S1D13700
CNF1
XECL
CNF2
FPSHIFT
CNF3
NIOVDD
CNF4
FPDAT0
Index
AS#
FPDAT1
A15
FPDAT2
A14
FPDAT3
64
17
A1
A2
A3
COREVDD
A4
A5
A6
A7
A8
HIOVDD
A9
A10
A11
16
A12
VSS
1
VSS
A0
A13
Figure 5-1 Pinout Diagram (TQFP13 - 64 pin)
S1D13700
X42A-A-001-00
Hardware Functional Specification
Issue Date: 2004/01/06
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5.2 Pin Descriptions
Key:
Pin Types
I
O
IO
P
=
=
=
=
Input
Output
Bi-Directional (Input/Output)
Power pin
RESET# States
Z
L
H
0
1
=
=
=
=
=
High Impedance (Hi-Z)
Low level output
High level output
Pull-down control on input
Pull-up control on input
Table 5-1: Cell Descriptions
Item
Description
SI
CMOS level Schmitt input
CI
CMOS input
CID1
CMOS input with internal pull-down resistor (typical value of [email protected])
CB2
CMOS IO buffer ([email protected], [email protected])
OB2T
Output buffer ([email protected]) with Test
LIN
TTL transparent input
LOT
TTL transparent output
T1
Test mode control input with pull-down resistor (typical value of 50 [email protected])
HTB2T
Tri-state output buffer ([email protected])
5.2.1 Host Interface
Many of the host interface pins have different functions depending on the selection of the
host bus interface (see configuration of CNF[4:2] pins in Table 5-6: “Summary of Configuration Options,” on page 24). For a summary of host interface pins, see Table 5-7: “Host
Interface Pin Mapping,” on page 25.
Table 5-2 Host Interface Pin Descriptions
Pin Name
A[15:1]
Type
Pin #
I
62-64,
2-6,
8-11,
13-15
Cell
Power
RESET#
State
Description
System Address pins 15-1.
CI
HIOVDD
Z
• For Direct addressing mode, these pins are used for the
system address bits 15-1.
• For Indirect addressing mode, these pins must be connected
to ground (VSS).
Hardware Functional Specification
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Table 5-2 Host Interface Pin Descriptions
Pin Name
Type
Pin #
Cell
Power
RESET#
State
Description
System Address pin 0.
• For Direct addressing mode, this pin is used for system
address bit 0.
• For Indirect addressing mode, this pin in conjunction with RD#
and WR# determines the type of data present on the data bus.
A0
I
16
CI
HIOVDD
Z
D[7:0]
IO
44-47,
49-52
CB2
HIOVDD
0 or Z
CNF[1:0]
CNF[3:2]
CNF4
I
I
I
57, 56
59, 58
60
SI
SI
SI
HIOVDD
HIOVDD
HIOVDD
System data bus pins 7-0.
These tristate input/output data pins must be connected to the
microprocessor data bus.
Z
These input pins are used for configuration of the FPSHIFT clock
cycle time and must be connected to either HIOVDD or VSS. For
further information, see Section 5.3, “Summary of Configuration
Options” on page 24.
Z
These input pins select the host bus interface (microprocessor
interface) and must be connected to either HIOVDD or VSS. The
S1D13700 supports Generic processors (such as the 8085 and
Z80®), the MC68K family of processors (such as the 68000) and
the M6800 family of processors (such as the 6800). For further
information, see Section 5.3, “Summary of Configuration Options”
on page 24.
Z
This input pin selects the microprocessor addressing mode and
must be connected to either HIOVDD or VSS. The S1D13700
supports both Direct and Indirect addressing modes. For further
information, see Section 5.3, “Summary of Configuration Options”
on page 24.
This input pin has multiple functions.
RD#
I
41
SI
HIOVDD
Z
• When the Generic host bus interface is selected, this pin is the
active-LOW read strobe (RD#). The S1D13700 data output
buffers are enabled when this signal is low.
• When the M6800 host bus interface is selected, this pin is the
active-high enable clock (E). Data is read from or written to the
S1D13700 when this clock goes high.
• When the MC68K host bus interface is selected, this pin is the
active-low lower data strobe (LDS#). Data is read from or
written to the S1D13700 when this signal goes low.
This input pin has multiple functions.
WR#
CS#
I
I
42
43
SI
SI
HIOVDD
HIOVDD
Z
Z
• When the Generic host bus interface is selected, this signal is
the active-low write strobe (WR#). The bus data is latched on
the rising edge of this signal.
• When the M6800 host bus interface is selected, this signal is
the read/write control signal (R/W#). Data is read from the
S1D13700 if this signal is high, and written to the S1D13700 if
it is low.
• When the MC68K host bus interface is selected, this signal is
the read/write control signal (RD/WR#). Data is read from the
S1D13700 if this signal is high, and written to the S1D13700 if
it is low.
Chip select.
This active-low input enables the S1D13700. It is usually
connected to the output of an address decoder device that maps
the S1D13700 into the memory space of the controlling
microprocessor.
S1D13700
X42A-A-001-00
Hardware Functional Specification
Issue Date: 2004/01/06
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Table 5-2 Host Interface Pin Descriptions
Pin Name
Type
Pin #
Cell
Power
RESET#
State
Description
This output pin has multiple functions.
WAIT#
O
54
HTB2T
HIOVDD
Z
• When the Generic host bus interface is selected, this pin is
WAIT#. During a data transfer, WAIT# is driven active-low to
force the system to insert wait states. It is driven inactive to
indicate the completion of a data transfer. WAIT# is released
to a high impedance state after the data transfer is complete.
For indirect addressing mode, the WAIT# pin should be left
unconnected and floating.
• When the MC68K host bus interface is selected, this pin is
DTACK#. During a data transfer, DTACK# is driven active-high
to force the system to insert wait states. It is driven inactive to
indicate the completion of a data transfer. DTACK# is released
to a high impedance state after the data transfer is complete.
For indirect addressing mode, DTACK# should be left
unconnected and floating.
• When the M6800 host bus interface is selected, this pin must
be left unconnected and floating.
This input pin has multiple functions.
AS#
RESET#
I
I
61
36
CI
SI
HIOVDD
HIOVDD
Z
Z
• When the Generic host bus interface is selected, this pin must
be connected to VDD (pulled high).
• When the MC68K host bus interface is selected, this pin is the
address strobe (AS#).
• When the M6800 host bus interface is selected, this pin must
be connected to VDD (pulled high).
This active-low input performs a hardware reset of the S1D13700
which sets all internal registers to their default states and forces all
signals to their inactive states.
Note: Do not trigger a RESET# when the supply voltage is lowered.
SCANEN
I
37
CID1
HIOVDD
0
Reserved
This pin must be connected to ground (VSS).
TSTEN
I
38
T1
HIOVDD
0
Reserved
This pin must be connected to ground (VSS).
Hardware Functional Specification
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5.2.2 LCD Interface
In order to provide effective low-power drive for LCD matrixes, the S1D13700 can directly
control both the X and Y-drivers using an enable chain.
Table 5-3 LCD Interface Pin Descriptions
Pin Name
Type
Pin #
Cell
Power
RESET#
State
Description
FPDAT[3:0]
(XD[3:0])
O
18-21
OB2T
NIOVDD
X
These output pins are the 4-bit X-driver (column drive) data
outputs and must be connected to the inputs of the X-driver chips.
FPSHIFT
(XSCL)
O
23
OB2T
NIOVDD
X
The falling edge of FPSHIFT latches the data on FPDAT[3:0] into
the input shift registers of the X-drivers. To conserve power, this
clock is stopped between FPLINE and the start of the following
display line.
XECL
O
24
OB2T
NIOVDD
X
The falling edge of XECL triggers the enable chain cascade for the
X-drivers. Every 16th clock pulse is output to the next X-driver.
FPLINE
(LP)
O
26
OB2T
NIOVDD
X
FPLINE latches the signal in the X-driver shift registers into the
output data latches. FPLINE is a falling edge triggered signal, and
pulses once every display line. FPLINE must be connected to the
Y-driver shift clock on LCD modules.
MOD
(WF)
O
27
OB2T
NIOVDD
X
This output pin is the LCD panel backplane bias signal. The MOD
period is selected using the SYSTEM SET command.
YSCL
O
29
OB2T
NIOVDD
X
The falling edge of YSCL latches the data on FPFRAME into the
input shift registers of the Y-drivers. YSCL is not used with driver
ICs which use FPLINE as the Y-driver shift clock.
X
This output pin is the data pulse output for the Y drivers. It is active
during the last line of each frame, and is shifted through the Y
drivers one by one (by YSCL), to scan the display’s common
connections.
L
This output pin is the power-down output signal. YDIS is high while
the display drive outputs are active. YDIS goes low one or two
frames after the power save command is written to the S1D13700.
All Y-driver outputs are forced to an intermediate level (deselecting the display segments) to blank the display. In order to
implement power-down operation in the LCD unit, the LCD power
drive supplies must also be disabled when the display is disabled
by YDIS.
FPFRAME
(YD)
YDIS
O
O
30
31
OB2T
OB2T
NIOVDD
NIOVDD
S1D13700
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5.2.3 Clock Input
Table 5-4 Clock Input Pin Descriptions
Pin Name
XCG1
Type
I
Pin #
35
Cell
LIN
Power
COREVDD
RESET#
State
Description
Z
This input pin is the crystal connection for use with the internal
oscillator. This pin must be pulled down when using an external
clock source (CLKI). For further information on the use of the
internal oscillator, see Section 9.3, “Oscillator Circuit” on page 46.
XCD1
O
34
LOT
COREVDD
—
This output pin is the crystal connection for use with the internal
oscillator. This pin must be left unconnected when using an
external clock source (CLKI). For further information on the use of
the internal oscillator, see Section 9.3, “Oscillator Circuit” on page
46.
CLKI
I
39
CI
HIOVDD
Z
This is the external clock input. This pin must be pulled down when
using a crystal with the internal oscillator. For further information on
clocks, see Section 9, “Clocks” on page 45.
5.2.4 Power And Ground
Table 5-5 Power And Ground Pin Descriptions
Pin Name
Type
Pin #
Cell
Power
RESET#
State
HIOVDD
P
55, 48,
7
P
—
—
IO power supply for the Host (MPU) interface, 3.3/5.0 volts.
NIOVDD
P
32, 22
P
—
—
IO power supply for the LCD interface, 3.3/5.0 volts.
COREVDD
P
40, 25,
12
P
—
—
Core power supply, 3.3 volts.
VSS
P
53, 33,
28, 17,
1
P
—
—
Ground for HIOVDD, NIOVDD, and COREVDD
Description
Hardware Functional Specification
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5.3 Summary of Configuration Options
These pins are used for configuration of the chip and must be connected directly to
HIOVDD or VSS.
Note
The state of CNF[4:0] can be set at any time before or during operation of the
S1D13700.
Table 5-6: Summary of Configuration Options
Configuration
Input
CNF4
Configuration State
1 (connected to HIOVDD)
Indirect Addressing Mode:
1-bit address bus
8-bit data bus
9 pins are used
0 (connected to VSS)
DIrect Addressing Mode:
16-bit address bus
8-bit data bus
24 pins are used
CNF[3:2]
Select the host bus interface as follows:
CNF3 CNF2
Host Bus
0
0
Generic Bus
0
1
Reserved
1
0
M6800 Family Bus Interface
1
1
MC68K Family Bus Interface
CNF[1:0]
Select the FPSHIFT cycle time (FPSHIFT:Clock Input) as follows:
CNF1 CNF0
FPSHIFT Cycle Time
0
0
4:1
0
1
8:1
1
0
16:1
1
1
Reserved
S1D13700
X42A-A-001-00
Hardware Functional Specification
Issue Date: 2004/01/06
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5.4 Host Bus Interface Pin Mapping
Table 5-7: Host Interface Pin Mapping
Pin Name
Generic
Direct
Generic
Indirect
MC68K
Direct
MC68K
Indirect
AB[15:1]
A[15:1]
Connected to
VSS
A[15:1]
Connected to
VSS
M6800 Direct
M6800
Indirect
Connected to
VSS
AB0
A0
A0
A0
A0
A0
DB[7:0]
D[7:0]
D[7:0]
D[7:0]
D[7:0]
D[7:0]
CS#
CS#
CS#
External
Decode
External
Decode
External
Decode
AS#
AS#
Connected to
VSS
AS#
Connected to Connected to
HIOVDD
HIOVDD
RD#
RD#
RD#
LDS#
LDS#
WR#
WR#
WR#
RD/WR#
RD/WR#
WAIT#
RESET#
WAIT# or Unconnected
RESET#
RESET#
DTACK# or Unconnected
RESET#
RESET#
Not
supported
E
R/W#
Unconnected
RESET#
CNF4
Connected to Connected to Connected to Connected to
VSS
HIOVDD
VSS
HIOVDD
Connected to
HIOVDD
CNF3
Connected to Connected to Connected to Connected to
VSS
VSS
HIOVDD
HIOVDD
Connected to
HIOVDD
CNF2
Connected to Connected to Connected to Connected to
VSS
VSS
HIOVDD
HIOVDD
Connected to
VSS
CNF[1:0]
See Note
See Note
See Note
See Note
See Note
Note
CNF[1:0] are used to configure the FPSHIFT cycle time and must be set according to
the requirements of the specific implementation.
Hardware Functional Specification
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6 D.C. Characteristics
Table 6-1 Absolute Maximum Ratings
Symbol
Parameter
Rating
Units
CORE VDD
Supply Voltage
VSS - 0.3 to 4.0
V
IO VDD
Supply Voltage
VSS - 0.3 to 7.0
V
VIN
Input Voltage
VSS - 0.3 to IO VDD + 0.5
V
VOUT
Output Voltage
VSS - 0.3 to IO VDD + 0.5
V
TSTG
Storage Temperature
-65 to 150
°C
TSOL
Solder Temperature/Time
260 for 10 sec. max at lead
°C
Table 6-2 Recommended Operating Conditions
Symbol
Parameter
Condition
Core VDD
Supply Voltage
VSS = 0 V
HIO VDD
Host Bus IO Supply Voltage
VSS = 0 V
VSS = 0 V
Min
Typ
Max
Units
3.0
3.3
3.6
V
3.0
3.3
3.6
V
4.5
5.0
5.5
V
3.0
3.3
3.6
V
4.5
5.0
5.5
V
HIO VDD
V
NIO VDD
Panel IO Supply Voltage
HIO VIN
Host Input Voltage
VSS
NIO VIN
Non-Host Input Voltage
VSS
TOPR
Operating Temperature
-40
NIO VDD
25
V
°C
85
Table 6-3 Electrical Characteristics for VDD = 3.3V typical
Symbol
ILZ
IOZ
Parameter
Core Quiescent Current
IO Quiescent Current
Input Leakage Current
Output Leakage Current
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
VIH1
VIL1
VT+
VTVH1
RPD
High Level Input Voltage
Low Level Input Voltage
High Level Input Voltage
Low Level Input Voltage
Hysteresis Voltage
Pull Down Resistance
IQH
Condition
Power save mode enabled
Power save mode enabled
VDD = min.
IOH =
-6mA
VDD = min.
IOL =
6mA
LVTTL Level, VDD = max
LVTTL Level, VDD = min.
LVTTL Schmitt
LVTTL Schmitt
LVTTL Schmitt
VI = VDD
S1D13700
X42A-A-001-00
Min
Typ


-1
-1




Max
35
30
1
1
Units
µA
µA
µA
µA
VDD-0.4


V


0.4
V
2.0






0.8
2.4
1.8
50
120
V
V
V
V
V
kΩ

1.1
0.6
0.1
20

Hardware Functional Specification
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Table 6-4 Electrical Characteristics for VDD = 5.0V typical
Symbol
ILZ
IOZ
Parameter
Core Quiescent Current
IO Quiescent Current
Input Leakage Current
Output Leakage Current
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
VIH
VIL
VT+
VTVH
RPD
High Level Input Voltage
Low Level Input Voltage
High Level Input Voltage
Low Level Input Voltage
Hysteresis Voltage
Pull Down Resistance
IQH
Condition
Power save mode enabled
Power save mode enabled
VDD = min.
-8mA
IOH =
VDD = min.
8mA
IOL =
CMOS Level, VDD = max
CMOS Level, VDD = min.
CMOS Schmitt
CMOS Schmitt
CMOS Schmitt
VI = VDD
Min
Typ


-1
-1




Max
35
30
1
1
Units
µA
µA
µA
µA
VDD-0.4


V


0.4
V
3.5






1.0
4.0
3.1
60
144
V
V
V
V
V
kΩ

2.0
0.8
0.3
30

The following electrical characteristics from Table 6-3 “Electrical Characteristics for VDD
= 3.3V typical,” on page 26 and Table 6-4 “Electrical Characteristics for VDD = 5.0V
typical,” on page 27 apply to the following cell types.
Table 6-5 Cell Type Reference
Electrical Characteristic
Cell Type
VOH / VOL
OB2T
CB2
HTB2T
VIH / VIL
CI
CID1
CB2
VT+ / VT-
SI
VH
SI
RPD
CID1
Hardware Functional Specification
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7 A.C. Characteristics
Conditions:
Core VDD = 3.3V ± 10%
IO VDD = 3.3V ± 10% or 5.0V ± 10%
TOPR = -40° C to 85° C
Trise and Tfall for all inputs must be < 5 nsec (10% ~ 90%)
CL = 30pF (Bus/MPU Interface)
CL = 30pF (LCD Panel Interface)
Note
CL includes a maximum pin capacitance of 5pF.
7.1 Clock Timing
7.1.1 Input Clock
t
Clock Input Waveform
t
PWH
PWL
90%
V
IH
VIL
10%
t
tr
f
TCLKI
Figure 7-1 Clock Input Requirements
Table 7-1 Clock Input Requirements
Symbol
3.0V
Parameter
Max
Min
Max

60

60
MHz
1/fOSC



1/fOSC



ns
2
ns
2
ns
Input Clock Frequency (CLKI)
TCLKI
Input Clock period (CLKI)
tPWH
Input Clock Pulse Width High (CLKI)
0.4TCLKI
tPWL
Input Clock Pulse Width Low (CLKI)
0.4TCLKI
Input Clock Fall Time (10% - 90%)
tr
Input Clock Rise Time (10% - 90%)
Units
Min
fCLKI
tf
5.0V


2
2
0.4TCLKI
0.4TCLKI


ns
ns
Note
Maximum internal requirements for clocks derived from CLKI must be considered
when determining the frequency of CLKI. For further details on internal clocks, see Section 9, “Clocks” on page 45.
S1D13700
X42A-A-001-00
Hardware Functional Specification
Issue Date: 2004/01/06
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7.2 Reset Timing
VDD
1ms
RESET#
0.7 VDD
0.3 VDD
Figure 7-2 Reset Timing
The S1D13700 requires a reset pulse of at least 1 ms after power-on in order to re-initialize
its internal state. For maximum reliability, it is not recommended to apply a DC voltage to
the LCD panel while the S1D13700 is reset. Turn off the LCD power supplies for at least
one frame period after the start of the reset pulse.
During the reset period the S1D13700 cannot receive commands. Commands to initialize
the internal registers should be issued soon after a reset. During reset, the LCD drive signals
FPDAT, FPLINE and FR are halted.
A delay of 3 ms (maximum) is required following the rising edges of both RESET# and
VDD to allow for system stabilization.
Hardware Functional Specification
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7.3 CPU Interface Timing
7.3.1 Generic Bus Direct/Indirect Interface with WAIT# Timing
t1
t6
t2
t7
CS#
AB[15:0]
t13
t14
t15
WR#, RD#
t3
t8
t16
WAIT#
t9
t4
DB[7:0] (write)
Valid
t11
t5
DB[7:0] (read)
t10
Valid
t12
Figure 7-3 Generic Bus Direct/Indirect Interface with WAIT# Timing
S1D13700
X42A-A-001-00
Hardware Functional Specification
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Table 7-2 Generic Bus Direct/Indirect Interface with WAIT# Timing
Symbol
3.3 Volt
Parameter
5.0 Volt
Units
Min
Max
Min
Max
5
5
ns
t1
CS# setup time
t2
AB[15:0] setup time
5


5


t3
WR#, RD# falling edge to WAIT# driven low
2
15
2
15
ns
t4
DB[7:0] setup time to WR# rising edge (write cycle)
Note 2
Note 2
RD# falling edge to DB[7:0] driven (read cycle)
3
t6
CS# hold time
7
t7
AB[15:0] hold time
7
7




ns
t5




t8
RD#, WR# rising edge to WAIT# high impedance
2
10
2
10
ns
t9
DB[7:0] hold time from WR# rising edge (write cycle)
5

5

ns
t10
DB[7:0] hold time from RD# rising edge (read cycle)
t11
WAIT# rising edge to valid Data if WAIT# is used
t12
RD# falling edge to valid Data if WAIT# is not used
t13
RD#, WR# cycle time
t14
RD#, WR# pulse active time
t15
RD#, WR# pulse inactive time
t16
WAIT# pulse active time
3
7
ns
ns
ns
ns
3
14
3
14
ns


Note 3


Note 3
ns
Note 4
ns
Note 5
Note 5
Ts
Note 6



ns
Note 6




Note 7

Note 7
ns
5
Note 4
5
ns
1. Ts
= System clock period
2. t4min = 2Ts + 5
3. t11max = 1Ts + 5 (for 3.3V)
= 1Ts + 7 (for 5.0V)
4. t12max = 4Ts + 18 (for 3.3V)
= 4Ts + 20 (for 5.0V)
5. t13min = 6Ts (for a read cycle followed by a read or write cycle)
= 7Ts + 2 (for a write cycle followed by a write cycle)
= 10Ts + 2 (for a write cycle followed by a read cycle)
6. t15min = 1Ts (for a read cycle followed by a read or write cycle)
= 2Ts + 2 (for a write cycle followed by a write cycle)
= 5Ts + 2 (for a write cycle followed by a read cycle)
7. t16max = 4Ts + 2
Hardware Functional Specification
Issue Date: 2004/01/06
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7.3.2 Generic Bus Direct/Indirect Interface without WAIT# Timing
t1
t5
t2
t6
CS#
AB[15:0]
t10
t11
t12
WR#, RD#
t7
t3
DB[7:0] (write)
Valid
t8
t4
DB[7:0] (read)
Valid
t9
Figure 7-4 Generic Bus Direct/Indirect Interface without WAIT# Timing
S1D13700
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Table 7-3 Generic Bus Direct/Indirect Interface without WAIT# Timing
Symbol
3.3 Volt
Parameter
5.0 Volt
Units
Min
Max
Min
Max
5
5
ns
5







t2
AB[15:0] setup time
t3
DB[7:0] setup time to WR# rising edge (write cycle)
t4
RD# falling edge to DB[7:0] driven (read cycle)
3
t5
CS# hold time
7
t6
AB[15:0] hold time
7
t7
DB[7:0] hold time from WR# rising edge (write cycle)
5







t8
DB[7:0] hold time from RD# rising edge (read cycle)
3
14
3
14
ns
t9
RD# falling edge to valid Data (read cycle)

Note 3

Note 3
ns
Note 4



Note 4



Ts
t1
CS# setup time
t10
RD#, WR# cycle time
t11
RD#, WR# pulse active time
t12
RD#, WR# pulse inactive time
5
Note 2
5
Note 5
5
Note 2
3
7
7
5
Note 5
ns
ns
ns
ns
ns
ns
ns
ns
1. Ts
= System clock period
2. t3min = 2Ts + 5
3. t9max = 4Ts + 18 (for 3.3V)
= 4Ts + 20 (for 5.0V)
4. t10min = 6Ts (for a read cycle followed by a read or write cycle)
= 7Ts + 2 (for a write cycle followed by a write cycle)
= 10Ts + 2 (for a write cycle followed by a read cycle)
5. t12min = 1Ts (for a read cycle followed by a read or write cycle)
= 2Ts + 2 (for a write cycle followed by a write cycle)
= 5Ts + 2 (for a write cycle followed by a read cycle)
Hardware Functional Specification
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7.3.3 MC68K Family Bus Direct/Indirect Interface with DTACK# Timing
t1
t6
t2
t7
t17
t18
CS#
AB[15:0], WR# (RW#, MR#)
AS#
t13
t14
t15
RD# (UDS#, LDS#)
t19
t3
t8
t16
t20
WAIT# (DTACK#)
t4
t9
DB[7:0] (write)
t11
t5
DB[7:0] (read)
t10
t12
Figure 7-5 MC68K Family Bus Direct/Indirect Interface with DTACK# Timing
S1D13700
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Table 7-4 MC68K Family Bus Direct/Indirect Interface with DTACK# Timing
Symbol
3.3 Volt
Parameter
5.0 Volt
Units
Min
Max
Min
Max
5
ns
t1
CS# setup time
5
t2
AB[15:0] setup time
5


5


t3
AS# falling edge to WAIT# driven
2
15
2
15
ns
t4
DB[7:0] setup time to RD# rising edge (write cycle)
Note 2
Note 2
RD# falling edge to DB[7:0] driven (read cycle)
3
t6
CS# hold time
7
t7
AB[15:0] hold time
7
7




ns
t5




t8
RD# rising edge to WAIT# high impedance if Direct interface and in
Power Save Mode
2
10
2
10
ns
3
7
ns
ns
ns
ns
t9
DB[7:0] hold time from RD# rising edge (write cycle)
5

5

ns
t10
DB[7:0] hold time from RD# rising edge (read cycle)
2
55
2
55
ns
t11
WAIT# falling edge to valid Data if WAIT# is used
Note 3
ns
RD# falling edge to valid Data if WAIT# is not used


Note 3
t12


Note 4
ns
Note 5
Note 5
Note 6



Ts
Note 6




Note 7

Note 7
ns
t13
RD# cycle time
t14
RD# pulse active time
t15
RD# pulse inactive time
t16
WAIT# pulse inactive time from WAIT# driven
5
Note 4
5
ns
ns
t17
AS# setup time
0
0
0


ns
AS# hold time


0
t18
t19
AS# rising edge to WAIT# high de-asserted if not Direct interface
and not in Power Save Mode

10

10
ns
t20
WAIT# pulse inactive time
0
Note 8
0
Note 8
ns
ns
1. Ts
= System clock period
2. t4min = 2Ts + 5
3. t11max = 1Ts + 5 (for 3.3V)
= 1Ts + 7 (for 5.0V)
4. t12max = 4Ts + 18 (for 3.3V)
= 4Ts + 20 (for 5.0V)
5. t13min = 6Ts (for a read cycle followed by a read or write cycle)
= 7Ts + 2 (for a write cycle followed by a write cycle)
= 10Ts + 2 (for a write cycle followed by a read cycle)
6. t15min = 1Ts (for a read cycle followed by a read or write cycle)
= 2Ts + 2 (for a write cycle followed by a write cycle)
= 5Ts + 2 (for a write cycle followed by a read cycle)
7. t16max = 4Ts + 2
8. t20max = 1Ts - 15
Hardware Functional Specification
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7.3.4 MC68K Family Bus Direct/Indirect Interface without DTACK# Timing
t1
t5
t2
t6
t13
t14
CS#
AB[15:0], WR# (RW#, MR#)
AS#
t10
t11
t12
RD# (UDS#, LDS#)
t3
t7
DB[7:0] (write)
t8
t4
DB[7:0] (read)
t9
Figure 7-6 MC68K Family Bus Direct/Indirect Interface without DTACK# Timing
S1D13700
X42A-A-001-00
Hardware Functional Specification
Issue Date: 2004/01/06
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Table 7-5 MC68K Family Bus Direct/Indirect Interface without DTACK# Timing
Symbol
3.3 Volt
Parameter
5.0 Volt
Units
Min
Max
Min
Max
5
5
ns
5







t2
AB[15:0] setup time
t3
DB[7:0] setup time to RD# rising edge (write cycle)
t4
RD# falling edge to DB[7:0] driven (read cycle)
3
t5
CS# hold time
7
t6
AB[15:0] hold time
7
t7
DB[7:0] hold time from RD# rising edge (write cycle)
5







t8
DB[7:0] hold time from RD# rising edge (read cycle)
2
55
2
55
ns
t9
RD# falling edge to valid Data

Note 3

Note 3
ns
Note 4





Note 4





t1
CS# setup time
5
Note 2
t10
RD# cycle time
t11
RD# pulse active time
t12
RD# pulse inactive time
t13
AS# setup time
0
t14
AS# hold time
0
5
Note 5
5
Note 2
3
7
7
5
Note 5
0
0
ns
ns
ns
ns
ns
ns
ns
Ts
ns
ns
ns
1. Ts
= System clock period
2. t3min = 2Ts + 5
3. t9max = 4Ts + 18 (for 3.3V)
= 4Ts + 20 (for 5.0V)
4. t13min = 6Ts (for a read cycle followed by a read or write cycle)
= 7Ts + 2 (for a write cycle followed by a write cycle)
= 10Ts + 2 (for a write cycle followed by a read cycle)
6. t15min = 1Ts (for a read cycle followed by a read or write cycle)
= 2Ts + 2 (for a write cycle followed by a write cycle)
= 5Ts + 2 (for a write cycle followed by a read cycle)
Hardware Functional Specification
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7.3.5 M6800 Family Bus Indirect Interface Timing
t1
t5
t2
t6
t13
t14
CS#
AB[15:0], WR# (RW#, MR#)
AS#
t10
t11
t12
RD# (UDS#, LDS#)
t3
t7
DB[7:0] (write)
t8
t4
DB[7:0] (read)
t9
Figure 7-7 M6800 Family Bus Indirect Interface Timing
Note
CLK input to the M6800 interface must be driven synchronous to the host microprocessor.
S1D13700
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Table 7-6 M6800 Family Bus Indirect Interface Timing
Symbol
3.3 Volt
Parameter
5.0 Volt
Units
Min
Max
Min
Max
5
5
ns
5







t2
AB[15:0] setup time
t3
DB[7:0] setup time to RD# falling edge (write cycle)
t4
RD# rising edge to DB[7:0] driven (read cycle)
3
t5
CS# hold time
7
t6
AB[15:0] hold time
7
t7
DB[7:0] hold time from RD# falling edge (write cycle)
5







t8
DB[7:0] hold time from RD# falling edge (read cycle)
2
55
2
55
ns
t9
RD# rising edge to valid Data

Note 3

Note 3
ns
Note 4





Note 4





t1
CS# setup time
5
Note 2
t10
RD# cycle time
t11
RD# pulse active time
t12
RD# pulse inactive time
t13
AS# setup time
0
t14
AS# hold time
0
5
Note 5
5
Note 2
3
7
7
5
Note 5
0
0
ns
ns
ns
ns
ns
ns
ns
Ts
ns
ns
ns
1. Ts
= System clock period
2. t3min = 2Ts + 5
3. t9max = 4Ts + 18 (for 3.3V)
= 4Ts + 20 (for 5.0V)
4. t13min = 6Ts (for a read cycle followed by a read or write cycle)
= 7Ts + 2 (for a write cycle followed by a write cycle)
= 10Ts + 2 (for a write cycle followed by a read cycle)
6. t15min = 1Ts (for a read cycle followed by a read or write cycle)
= 2Ts + 2 (for a write cycle followed by a write cycle)
= 5Ts + 2 (for a write cycle followed by a read cycle)
Hardware Functional Specification
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7.4 Power Save Mode/Display Enable Timing
WR#
t2
t1
YDIS
Display On
Display Off or Power Save Mode Enabled
Display On
Table 7-7 Power Save Mode/Display Enable Timing
Symbol
3.0 Volt
Parameter
5.0 Volt
Min.
Max.
Min.
Max.
Units
t1a
YDIS falling edge delay for Power Save Mode
Enable in Indirect Mode (see Note 2)

2

2
Frames
t1b
YDIS falling edge delay for Display Off in Indirect
Mode (58h)

1Ts + 10

1Ts + 10
ns
t1c
YDIS falling edge delay for Display Off in Direct
Mode (see Note 3)

2Ts + 10

2Ts + 10
ns
t2
YDIS rising edge delay for Display On (see Note 3)

2Ts + 10

2Ts + 10
ns
1. Ts
= System Clock Period
2. Power Save Mode is controlled by the Power Save Mode Enable bit, REG[08h] bit 0.
3. Display On/Off is controlled by the Display Enable bit, REG[09h] bit 0.
S1D13700
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Hardware Functional Specification
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7.5 Display Interface
The timing parameters required to drive a flat panel display are shown below.
VDP (1 Frame)
FPFRAME (YD)
FPLINE (LP)
MOD (WF)
FPDAT[3:0]
Invalid
LINE1
LINE2
LINE3
LINE4
LINE239 LINE240
Invalid
LINE1
LINE2
YSCL
MOD
1 Line
YSCL
FPLINE (LP)
HNDP
HDP
HNDP
FPSHIFT (XSCL)
FPDAT3
Invalid
1-1
1-5
1-317
Invalid
FPDAT2
FPDAT1
Invalid
1-2
1-6
1-318
Invalid
Invalid
1-3
1-7
1-319
Invalid
FPDAT0
Invalid
1-4
1-8
1-320
Invalid
XECL
Figure 7-8: Monochrome 4-Bit Panel Timing
Hardware Functional Specification
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t3
t2
t1
FPSHIFT (XSCL)
t4
t5
FPDAT3
FPDAT2
FPDAT1
FPDAT0
t6
t7
FPLINE (LP)
t8
t10
t9
XECL
t11
t12
MOD (WF(B))
t13
t14
FPFRAME (YD)
t15
YSCL
t16
S1D13700
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Hardware Functional Specification
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Table 7-8: Single Monochrome 4-Bit Panel A.C. Timing
Symbol
3.3 Volts
Min
Max
Parameter
t1
FPSHIFT cycle time
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
FPSHIFT pulse width
Latch data setup time from FPSHIFT falling edge
FPDAT[3:0] setup to FPSHIFT falling edge
FPDAT[3:0] hold from FPSHIFT falling edge
FPLINE rising edge delay from FPSHIFT rising edge
Latch pulse width
XECL falling edge setup time to FPSHIFT falling edge
XECL falling edge setup time from FPLINE rising edge
XECL falling edge hold time to FPLINE falling edge
XECL pulse width
Permitted MOD delay time
FPLINE falling edge from FPFRAME rising edge
FPLINE falling edge to FPFRAME falling edge
FPFRAME falling edge hold time from YSCL falling edge
YSCL pulse width
1. Ts
2. Tc
5.0 Volts
Min
Max
1

1

0.5Tc - 5
0.5Tc - 5
0.5Tc - 5
0.5Tc - 5
0
Tc - 5
0.25Tc -5
0.75Tc - 5
Tc - 8
0.75Tc - 5




0.5Tc - 4
0.5Tc - 4
0.5Tc - 4
0.5Tc - 4
0
Tc - 4
0.25Tc - 4
0.75Tc - 4
Tc - 8
0.75Tc - 4




2Tc - 10
2Tc
3Tc - 10
Tc - 5




2Tc - 10
2Tc
3Tc - 10
Tc - 4





4





4

4





4
Units
Tc
(Note 2)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
= System clock period
= FPSHIFT cycle time
= 4Ts when CNF[1:0] = 00
= 8Ts when CNF[1:0] = 01
= 16Ts when CNF[1:0] = 10
Hardware Functional Specification
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8 Memory Mapping
The S1D13700 includes 32K bytes of embedded SRAM. The memory is used for the
display data, the registers and the CGROM.
(MSB)
D7
D0
0000h
DISPLAY
RAM Area
7FFFh
8000h
Register Area
802Fh
8030h
Not Used
FFFFh
Figure 8-1 S1D13700 Memory Mapping
S1D13700
X42A-A-001-00
Hardware Functional Specification
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Page 45
9 Clocks
9.1 Clock Diagram
The following figure shows the clock tree of the S1D13700.
System Clock
FPSHIFT Clock
CLKI
DIV
Internal
OSC
Power Save Mode
(REG[08h] bit 0)
FPSHIFT Cycle Time
(CNF[1:0] see Note)
Figure 9-1: Clock Diagram
Note
The FPSHIFT Cycle Time is configured using the CNF[1:0] pins. For further information, see Section 5.3, “Summary of Configuration Options” on page 24.
9.2 Clock Descriptions
9.2.1 System Clock
The maximum frequency of the system clock is 60MHz. The system clock source can be
either an external clock source (i.e. oscillator) or the internal crystal. If an external clock
source is used, the crystal input (XCG1) must be pulled down and the crystal output
(XCD1) must be left unconnected. If the internal crystal is used, the CLKI pin must be
pulled down.
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9.2.2 FPSHIFT Clock
The FPSHIFT clock is derived from the internal system clock as shown in Figure 9-1:
“Clock Diagram,” on page 45. The maximum frequency possible for FPSHIFT clock is
15MHz.
9.3 Oscillator Circuit
The S1D13700 design incorporates an oscillator circuit. A stable oscillator can be
constructed by connecting an AT-cut crystal, two capacitors, and two resistors to XCG1
and XCD1, as shown in the figure below. If the oscillator frequency is increased, Cd and
Cg should be decreased proportionally.
Note
The circuit board lines to XCG1 and XCD1 must be as short as possible to prevent wiring capacitance from changing the oscillator frequency or increasing the power consumption.
S1D13700
XCD1
XCG1
Rf
Rd
Xtal
Cg
Cd
Figure 9-2 Crystal Oscillator
Table 9-1 Crystal Oscillator Circuit Parameters
Symbol
Min
Typ
Max
Units
fOSC
40
100




MHz
Rd




Cg
2
10
18
pF
Cd
3
10
20
pF
TOSC
Rf
1/fOSC
1
S1D13700
X42A-A-001-00
ns
MΩ
kΩ
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10 Registers
10.1 Register Set
The S1D13700 registers are listed in the following table.
Table 10-1: S1D13700 Register Set
Register
Pg
Register
Pg
LCD Register Descriptions (Offset = 8000h)
System Control Registers
REG[00h] Memory Configuration Register
48
REG[01h] Horizontal Character Size Register
52
REG[02h] Vertical Character Size Register
53
REG[03h] Character Bytes Per Row Register
53
REG[04h] Total Character Bytes Per Row Register
53
REG[05h] Frame Height Register
54
REG[06h] Horizontal Address Range Register 0
54
REG[07h] Horizontal Address Range Register 1
54
REG[08h] Power Save Mode Register
55
Display Control Registers
REG[09h] Display Enable Register
56
REG[0Ah] Display Attribute Register
56
REG[0Bh] Screen Block 1 Start Address Register 0
58
REG[0Ch] Screen Block 1 Start Address Register 1
58
REG[0Dh] Screen Block 1 Size Register
58
REG[0Eh] Screen Block 2 Start Address Register 0
58
REG[0Fh] Screen Block 2 Start Address Register 1
58
REG[10h] Screen Block 2 Size Register
59
REG[11h] Screen Block 3 Start Address Register 0
59
REG[12h] Screen Block 3 Start Address Register 1
59
REG[13h] Screen Block 4 Start Address Register 0
59
REG[14h] Screen Block 4 Start Address Register 1
59
REG[15h] Cursor Width Register
63
REG[16h] Cursor Height Register
63
REG[17h] Cursor Shift Direction Register
64
REG[18h] Overlay Register
65
REG[19h] Character Generator RAM Start Address Register 0
67
REG[1Ah] Character Generator RAM Start Address Register 1
67
REG[1Bh] Horizontal Pixel Scroll Register
68
Drawing Control Registers
REG[1Ch] Cursor Write Register 0
69
REG[1Dh] Cursor Write Register 1
69
REG[1Eh] Cursor Read Register 0
70
REG[1Fh] Cursor Read Register 1
70
GrayScale Register
REG[20h] Bit-Per-Pixel Select Register
71
Hardware Functional Specification
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10.2 Register Restrictions
All reserved bits must be set to 0 unless otherwise specified. Writing a value to a reserved
bit may produce undefined results. Bits marked as n/a have no hardware effect.
10.3 Register Descriptions
10.3.1 System Control Registers
The following registers initialize the S1D13700, set the window sizes, and select the LCD
interface format. Incorrect configuration of these registers may cause other commands to
operated incorrectly. For an example initialization of the S1D13700, see Section 15.1.2,
“Initialization Example” on page 105.
SYSTEM SET
The SYSTEM SET command is used to initialize the S1D13700 and the display when
indirect addressing is used. The values from REG[00h] through REG[07h] are passed as
parameters when the SYSTEM SET command is issued. For further information on the
SYSTEM SET command, see Section 11.1.1, “SYSTEM SET” on page 73.
REG[00h] Memory Configuration Register
Address = 8000h
n/a
7
6
Read/Write
Screen Origin
Compensation
Reserved
Panel Drive
Select
Character Height
Reserved
Character
Generator Select
5
4
3
2
1
0
Note
When REG[00h] is written to, the S1D13700 automatically performs the following
functions.
1. Resets the internal timing generator
2. Disables the display
3. When indirect addressing mode is selected, completes and exits power save mode
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Screen Origin Compensation (IV)
This bit controls Screen Origin Compensation which is used for inverse display and is
usually set to 1. A common method of displaying inverted characters is to Exclusive-OR
the text layer with the graphics back-ground layer. However when this is done, the
inverted characters at the top or left of the screen become difficult to read. This is because
the character origin is at the top-left of its bitmap and there are no background pixels
either above or to the left of these characters.
This bit causes the S1D13700 to offset the text screen against the graphics back layer by
one vertical pixel. To shift the text screen horizontally, the horizontal pixel scroll function
(REG[1Bh] or the HDOT SCR command for indirect addressing) can be used to shift the
text screen 1 to 7 pixels to the right. If both of these functions are enabled, all characters
have the appropriate surrounding back-ground pixels to ensure easy reading of the inverted
characters.
When this bit = 0, screen origin compensation is done.
When this bit = 1, screen origin compensation is not done.
The following figure shows an example of screen origin compensation and the HDOT SCR
command in use.
Display start point
REG[00h] bit 5 = 0
Back layer
1 dot
HDOT SCR
(REG[1Bh])
Character
Dots 1 to 7
Figure 10-1 Screen Origin Compensation and HDOT SCR Adjustment
bit 4
Reserved
The default value for this bit is 1.
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Panel Drive Select (W/S)
This bit specifies the LCD panel drive method.
When this bit = 0, a single panel drive is selected.
When this bit = 1, a dual panel drive is selected.
The following diagrams show examples of the possible drive methods.
XECL
X driver
X driver
FPFRAME
Y driver
LCD
Figure 10-2 Single Drive Panel Display
XECL
X driver
X driver
FPFRAME
Upper Panel
Y driver
Lower Panel
X driver
X driver
Figure 10-3 Dual Drive Panel Display
The following table summarizes the parameters that must be configured for correct
operation of an LCD panel.
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Table 10-2 LCD Parameter Summary
Parameter
Single Panel (REG[00h] bit 3 = 0)
Dual Panel (REG[00h] bit 3 = 1)
REG[00h] bit 5 = 1 (IV)
REG[00h] bit 5 = 0 (IV)
REG[00h] bit 5 = 1 (IV)
REG[00h] bit 5 = 0 (IV)
C/R
REG[03h] bits 7-0
REG[03h] bits 7-0
REG[03h] bits 7-0
REG[03h] bits 7-0
TC/R
REG[04h] bits 7-0
REG[04h] bits 7-0
REG[04h] bits 7-0
REG[04h] bits 7-0
L/F
REG[05h] bits 7-0
REG[05h] bits 7-0
REG[05h] bits 7-0
REG[05h] bits 7-0
SL1
00h to REG[05h] bits 7-0
00h to REG[05h] bits 7-0
[REG[05h] bits 7-0 + 1] ÷ 2 - 1 [REG[05h] bits 7-0 + 1] ÷ 2 - 1
(See Note)
SL2
00h to REG[05h] bits 7-0
00h to REG[05h] bits 7-0
[REG[05h] bits 7-0 + 1] ÷ 2 - 1 [REG[05h] bits 7-0 + 1] ÷ 2 - 1
(See Note)
SAD1
First screen block (Start Address = REG[0Bh], REG[0Ch])
SAD2
Second screen block (Start Address = REG[0Eh], REG[0Fh])
SAD3
Third screen block (Start Address = REG[11h], REG[12h])
SAD4
Invalid
Fourth screen block (Start Address = REG[13h], REG[14h])
Cursor
movement
range
Continuous movement over whole screen
Above-and-below configuration: continuous movement over
whole screen
Note
Screen Origin Compensation shifts the character font down by one pixel row. If the bottom pixel row of the font is at the bottom of the Screen Block, that row disappears when
REG[00h] bit 5 = 0. To compensate for the bad visual effect, SL can be increased by
one.
bit 2
Character Height (M2)
This bit selects the height of the character bitmaps. It is possible to display characters
greater than 16 pixels high by creating a bitmap for each portion of each character and
using graphics mode to reposition them.
When this bit = 0, the character height is 8 pixels.
When this bit = 1, the character height is 16 pixels.
bit 1
Reserved
The default value for this bit is 0.
bit 0
Character Generator Select (M0)
This bit determines whether characters are generated by the internal character generator
ROM (CGROM) or character generator RAM (CGRAM). The CGROM contains 160,
5x7 pixel characters which are fixed at fabrication. The CGRAM can contain up to 256
user-defined characters which are mapped at the CG Start Address (REG[1Ah] REG[19h]). However, when the CGROM is used, the CGRAM can only contain up to 64,
8x8 pixel characters.
When this bit = 0, the internal CGROM is selected.
When this bit = 1, the internal CGRAM is selected.
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REG[01h] Horizontal Character Size Register
Address = 8001h
MOD
7
bit 7
Read/Write
n/a
6
Horizontal Character Size bits 3-0
5
4
3
2
1
0
MOD
This bit selects the AC frame drive waveform period. MOD is typically set to 1.
When this bit = 0, 16-line AC drive is selected.
When this bit = 1, two-frame AC drive is selected.
In two-frame AC drive, the MOD period is twice the frame period. In 16-line AC drive,
MOD inverts every 16 lines. Although 16-line AC drive gives a more readable display,
horizontal lines may appear when using high LCD drive voltages or at high viewing angles.
bits 3-0
Horizontal Character Size (FX) bits [3:0]
These bits define the horizontal size, or width, of each character, in pixels.
REG[01h] bits 3-0 = Horizontal Character Size in pixels - 1
The S1D13700 handles display data in 8-bit units, therefore characters larger than 8 pixels
wide must be formed from 8-pixel segments. The following diagram shows an example of
a character requiring two 8-pixel segments where the remainder of the second eight bits are
not displayed. This also applies to the second screen layer. In graphics mode, the normal
character field is also eight pixels. If a wider character field is used, any remainder in the
second eight bits is not displayed.
FX
FX
FY
8 bits
8 bits
FY
8 bits
8 bits
Address A Address B
Non-display area
Where:
FX = horizontal character size in pixels (REG[01h] bits 3-0)
FY = vertical character size in pixels (REG[02h] bits 3-0)
Figure 10-4 Horizontal and Vertical Character Size Example
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REG[02h] Vertical Character Size Register
Address = 8002h
Read/Write
n/a
7
6
bit 3-0
Vertical Character Size bits 3-0
5
4
3
2
1
0
Vertical Character Size (FY) bits [3:0]
These bits define the vertical size, or height, of each character, in pixels.
REG[02h] bits 3-0 = Vertical Character Size in pixels - 1
REG[03h] Character Bytes Per Row Register
Address = 8003h
Read/Write
Character Bytes Per Row bits 7-0
7
6
bits 7-0
5
4
3
2
1
0
Character Bytes Per Row (C/R) bits [7:0]
These bits determine the size of each character row (or display line), in bytes, to a maximum of 239. The value of these bits is defined in terms of C/R which is calculated in Section 15.1.1, “SYSTEM SET Command and Parameters” on page 103.
REG[03h] bits 7-0 = ([C/R] x bpp) - 1
REG[04h] Total Character Bytes Per Row Register
Address = 8004h
Read/Write
Total Character Bytes Per Row bits 7-0
7
bits 7-0
6
5
4
3
2
1
0
Total Character Bytes Per Row (TC/R) bits [7:0]
These bits set the length of one line, including horizontal blanking, in bytes, to a maximum of 255. The value of these bits is defined in terms of TC/R which is calculated in
Section 15.1.1, “SYSTEM SET Command and Parameters” on page 103. TC/R can be
adjusted to hold the frame period constant and minimize jitter for any given main oscillator frequency, fosc.
REG[04h] bits 7-0 = [TC/R] + 1
Note
TC/R must be programmed such that the following formulas are valid.
[TC/R] ≥ [C/R] + 2
0 ≤ [TC/R] ≤ 255
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REG[05h] Frame Height Register
Address = 8005h
Read/Write
Frame Height bits 7-0
7
6
bits 7-0
5
4
3
2
1
0
Frame Height (L/F) bits [7:0]
These bits determine the frame height, in lines. The maximum frame height is 256 lines.
REG[05h] bits 7-0 = frame height in lines - 1.
Note
If the Panel Drive Select bit is set for a dual drive panel (REG[00h] bit 3 = 1), the frame
height must be an even number of lines resulting in an odd number value for REG[05h]
bits 7-0.
REG[06h] Horizontal Address Range Register 0
Address = 8006h
Read/Write
Horizontal Address Range bits 7-0
7
6
5
4
3
2
1
REG[07h] Horizontal Address Range Register 1
Address = 8007h
0
Read/Write
Horizontal Address Range bits 15-8
7
bits 15-0
6
5
4
3
2
1
0
Horizontal Address Range (AP) bits [15:0]
These bits define the horizontal address range of the virtual screen. The maximum value
for this register is 7FFFh.
REG[07h] bits 7-0, REG[06h] bits 7-0 = Addresses per line
The following diagram demonstrates the relationship between the Horizontal Address
Range and the Character Bytes Per Row value.
Display area
C/R
Display memory limit
AP
Where:
C/R = character bytes per row (REG[03h] bits 7-0)
AP = horizontal address range (REG[06h] bits 7-0, REG[07h] bits 7-0)
Figure 10-5 Horizontal Address Range and Character Bytes Per Row Relationship
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POWER SAVE
The POWER SAVE command is used to enter standby mode on the S1D13700 when
indirect addressing is used. For further information on the POWER SAVE command, see
Section 11.1.2, “POWER SAVE” on page 73.
REG[08h] Power Save Mode Register
Address = 8008h
Read/Write
Power Save Mode
Enable
n/a
7
bit 0
6
5
4
3
2
1
0
Power Save Mode Enable
This bit controls the state of the software initiated power save mode. When power save
mode is disabled, the S1D13700 is operating normally. When power save mode is
enabled, the S1D13700 is in a power efficient state where all internal operations, including
the oscillator, are stopped. For more information on the condition of the S1D13700 during
Power Save Mode, see Section 17, “Power Save Mode” on page 126.
When this bit = 0, power save mode is disabled (see note).
When this bit = 1, power save mode is enabled (default).
Note
To fully disable power save mode when in Direct mode, a dummy write to any register
must be performed after setting REG[08h] bit 0 = 0. To fully disable power save mode
when in Indirect mode, at least two dummy writes to any register must be performed after setting REG[08h] bit 0 = 0.
Note
Enabling power save mode automatically clears the Display Enable bit (REG[09h] bit
0). After power save mode is disabled, the Display Enable bit must be set (REG[09h] bit
0 = 1) in order to turn on the display again.
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10.3.2 Display Control Registers
These registers enable/disable the display, and control the cursor and layered screens.
DISP ON/OFF
The DISP ON/OFF command is used to enable/disable the display and display attributes
when indirect addressing is used. The values from REG[0Ah] are passed as parameters
when the DISP ON/OFF command is issued. For further information on the DISP ON/OFF
command, see Section 11.1.3, “DISP ON/OFF” on page 74.
REG[09h] Display Enable Register
Address = 8009h
Read/Write
n/a
7
6
bit 0
5
Display Enable
4
3
2
1
0
Display Enable
This bit controls the LCD display, including the cursor and all layered screens. The display enable bit takes precedence over the individual attribute bits in the Display Attribute
register, REG[0Ah]. For information on LCD pin states when the display is off (REG[09h]
bit 0 = 0), see Table 17-1 “State of LCD Pins During Power Save Mode,” on page 126.
When this bit = 0, the display is off.
When this bit = 1, the display is on.
REG[0Ah] Display Attribute Register
Address = 800Ah
Read/Write
SAD3 Attribute bits 1-0
SAD2 Attribute bits 1-0
7
5
bits 7-6
6
SAD1 Attribute bits 1-0
4
3
Cursor Attribute bits 1-0
2
1
0
SAD3 Attribute (FP 5-4) bits [1:0]
These bits control the attributes of the third screen block (SAD3) as follows.
Table 10-3 Screen Block 3 Attribute Selection
Third Screen Block (SAD3)
REG[0Ah] bit 7
REG[0Ah] bit 6
Attributes
0
0
OFF (Blank)
0
1
1
0
1
1
No Flashing
ON
Flash at fFR/32 Hz
(approx. 2 Hz)
Flash at fFR/4 Hz
(approx. 16 Hz)
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bits 5-4
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SAD2 Attribute (FP 3-2) bits [1:0]
These bits control the attributes of the second screen block (SAD2). These bits also control the attributes of the fourth screen block (SAD4) when it is enabled by setting the Panel
Drive Select bit to dual panel mode (REG[00h] bit 3 = 1). In this mode, the attributes of
the second screen block (SAD2) and the fourth screen block (SAD4) share the same settings and cannot be set independently.
Table 10-4 Screen Block 2/4 Attribute Selection
Second Screen Block (SAD2, SAD4)
bits 3-2
REG[0Ah] bit 5
REG[0Ah] bit 4
Attributes
0
0
OFF (Blank)
0
1
1
0
1
1
No Flashing
Flash at fFR/32 Hz
(approx. 2 Hz)
ON
Flash at fFR/4 Hz
(approx. 16 Hz)
SAD1 Attribute (FP 1-0) bits [1:0]
These bits control the attributes of the first screen block (SAD1) as follows.
Table 10-5 Screen Block Attribute Selection
First Screen Block (SAD1)
bits 1-0
REG[0Ah] bit 3
REG[0Ah] bit 2
Attributes
0
0
OFF (Blank)
0
1
1
0
1
1
No Flashing
ON
Flash at fFR/32 Hz
(approx. 2 Hz)
Flash at fFR/4 Hz
(approx. 16 Hz)
Cursor Attribute (FC) bits [1:0]
These bits control the cursor and set the flash rate. The cursor flashes with a 70% duty
cycle (ON 70% of the time and OFF 30% of the time).
Table 10-6 Cursor Flash Rate Selection
Bit 1
Bit 0
Cursor Display
0
0
0
1
ON
No Flashing
1
0
ON
Flash at fFR/32 Hz
(approx. 2 Hz)
1
1
ON
Flash at fFR/64 Hz
(approx. 1 Hz)
OFF (Blank)
Note
When the cursor is disabled, a write to memory automatically enables the cursor and
places the cursor at the next memory location. A read from memory does not enable the
cursor, however, it still places the cursor at the next memory location.
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SCROLL
The SCROLL command is used to configure the display start addresses for the various
screen blocks when indirect addressing is used. The values from REG[0Bh] through
REG[14h] are passed as parameters when the SCROLL command is issued. For further
information on the SCROLL command, see Section 11.1.4, “SCROLL” on page 75.
REG[0Bh] Screen Block 1 Start Address Register 0
Address = 800Bh
Read/Write
Screen Block 1 Start Address bits 7-0 (LSB)
7
6
5
4
3
2
1
REG[0Ch] Screen Block 1 Start Address Register 1
Address = 800Ch
0
Read/Write
Screen Block 1 Start Address bits 15-8 (MSB)
7
6
bits 15-0
5
4
3
2
1
0
Screen Block 1 Start Address (SAD1) bits [15:0]
These bits determine the memory start address of screen block 1.
REG[0Dh] Screen Block 1 Size Register
Address = 800Dh
Read/Write
Screen Block 1 Size bits 7-0
7
6
bits 7-0
5
4
3
2
1
0
Screen Block 1 Size (SL1) bits [7:0]
These bits determine the size of screen block 1, in lines.
REG[0Dh] bits 7-0 = screen block 1 size in number of lines - 1
Note
The relationship between the screen block start address (SADx), screen block size
(SLx), and the display mode is described in Table 10-7 “Display Modes,” on page 60.
REG[0Eh] Screen Block 2 Start Address Register 0
Address = 800Eh
Read/Write
Screen Block 2 Start Address bits 7-0 (LSB)
7
6
5
4
3
2
1
REG[0Fh] Screen Block 2 Start Address Register 1
Address = 800Fh
0
Read/Write
Screen Block 2 Start Address bits 15-8 (MSB)
7
bits 15-0
6
5
4
3
2
1
0
Screen Block 2 Start Address (SAD2) bits [15:0]
These bits determine the memory start address of screen block 2.
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REG[10h] Screen Block 2 Size Register
Address = 8010h
Read/Write
Screen Block 2 Size bits 7-0
7
6
bits 7-0
5
4
3
2
1
0
Screen Block 2 Size (SL2) bits [7:0]
These bits determine the size of screen block 2, in lines.
REG[10h] bits 7-0 = screen block 2 size in number of lines - 1
Note
The relationship between the screen block start address (SADx), screen block size
(SLx), and the display mode is described in Table 10-7 “Display Modes,” on page 60.
REG[11h] Screen Block 3 Start Address Register 0
Address = 8011h
Read/Write
Screen Block 3 Start Address bits 7-0 (LSB)
7
6
5
4
3
2
1
REG[12h] Screen Block 3 Start Address Register 1
Address = 8012h
0
Read/Write
Screen Block 3 Start Address bits 15-8 (MSB)
7
6
bits 15-0
5
4
3
2
1
0
Screen Block 3 Start Address (SAD3) bits [15:0]
These bits determine the memory start address of screen block 3.
REG[13h] Screen Block 4 Start Address Register 0
Address = 8013h
Read/Write
Screen Block 4 Start Address bits 7-0 (LSB)
7
6
5
4
3
2
1
REG[14h] Screen Block 4 Start Address Register 1
Address = 8014h
0
Read/Write
Screen Block 4 Start Address bits 15-8 (MSB)
7
bits 15-0
6
5
4
3
2
1
0
Screen Block 4 Start Address (SAD4) bits [15:0]
These bits determine the memory start address of screen block 4.
The following table summaries the required settings for each possible display mode.
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Table 10-7 Display Modes
REG[00h] bit 3
(W/S)
Screen
First Layer
Second Layer
First Screen Block
SAD1
SAD2
Second Screen Block
SL1
SL2
SAD3 (see note 1)
Third Screen Block (partitioned screen) Set both SL1 and SL2 to L/F + 1 if not using
a partitioned screen.
Screen Configuration Example
SAD2
SAD1
SL2
0
SL1
Graphics display page 2
Character or
Graphics page 1
SAD3
Character or
Graphics page 3
Layer 1
Layer 2
First Screen Block
SAD1, SL1
SAD2, SL2
Second Screen Block
SAD3 (see note 2)
SAD4 (see note 2)
Set both SL1 and SL2 to ([L/F] ÷ 2 + 1)
Screen Configuration Example
SAD2
SAD1
1
SL1
SAD3
Graphics display page 2
Character or
Graphics display
page 1
Graphics display page 4
(SAD4)
Character or
Graphics display
page 3
Layer 1
Layer 2
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Table 10-7 Display Modes (Continued)
REG[00h] bit 3
(W/S)
Screen
First Layer
Second Layer
First Screen Block
SAD1, SL1
SAD2, SL2
—
SAD3 (see note 2)
Second Screen Block
Set SL1 > SL2
Screen Configuration Example
SAD2
SAD1
Graphics display page 2
0
SL1
Graphics display
page 1
Graphics display page 3
(SAD3)
Layer 1
REG[00h] bit 3
(W/S)
Layer 2
Screen
First Layer
Second Layer
Third Layer
Three-Layer Configuration
SAD1,
SL1 = L/F + 1
SAD2,
SL2 = L/F + 1
SAD3
Screen Configuration Example
SAD3
SAD2
SAD1
Graphics display page 3
SL2
SL1
0
Graphics display page 2
Graphics display
page 1
Layer 1
Layer 3
Layer 2
Note
1
2
3
The size of screen block 3, in lines, is automatically set to the size of the screen
block with the least number of lines (either SL1 or SL2).
The parameters corresponding to SL3 and SL4 are fixed by REG[05h] bits 7-0
(L/F) and do not have to be set.
If a dual panel is selected (REG[00h] bit 3 = 1), the differences between SL1 and
(L/F + 1) ÷ 2, and between SL2 and (L/F + 1) ÷ 2, are blanked.
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Upper Panel
SL1
L/F
Lower Panel
L/F÷2
Graphics
Where:
SL1 = screen block 1 size (REG[0Dh] bits 7-0)
L/F = (REG[05h] bits 7-0)
Figure 10-6 Dual Panel Display Height
CSRFORM
The CSRFORM command is used to configure the S1D13700 cursor when indirect
addressing is used. The values from REG[15h] through REG[16h] are passed as parameters
when the CSRFORM command is issued. For further information on the CSRFORM
command, see Section 11.1.5, “CSRFORM” on page 76.
The cursor registers are used to set the size, shape, and position of the cursor. Although the
cursor is normally only used for text displays, it may be used for graphics displays when
displaying special characters.
Character origin
0
0 1 2 3 4 5 6 •
•
•
1
2
3
4
CRX = 5 pixels
CRY = 9 lines
5
CM = underscore (0)
6
7
8
9
Where:
CRX = cursor width (REG[15h] bits 3-0)
CRY = cursor height (REG[16h] bits 3-0)
CM = cursor mode (REG[16h] bit 7)
Figure 10-7 Cursor Size and Position
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REG[15h] Cursor Width Register
Address = 8015h
Read/Write
n/a
7
6
bits 3-0
Cursor Width bits 3-0
5
4
3
2
1
0
Cursor Width (CRX) bits[3:0]
These bits specify the width (or horizontal size) of the cursor, in pixels from the character
origin (see Figure 10-7 “Cursor Size and Position,” on page 62).
REG[15h] bits 3-0 = cursor width in pixels - 1
Note
The cursor width must be less than or equal to the horizontal character size.
(REG[16h] bits 3-0 <= REG[01h] bits 3-0)
REG[16h] Cursor Height Register
Address = 8016h
Cursor Mode
7
Read/Write
n/a
6
5
Cursor Height bits 3-0
4
3
2
1
0
bit 7
Cursor Mode (CM)
This bit determines the cursor mode. When graphics mode is selected, this bit must be set
to 1.
When this bit = 0, an underscore cursor ( _ ) is selected.
When this bit = 1, a block cursor ( ■ ) is selected.
bits 3-0
Cursor Height (CRY) bits [3:0]
For an underscore cursor (REG[16h] bit 7 = 0), these bits set the location of the cursor, in
lines from the character origin (see Figure 10-7 “Cursor Size and Position,” on page 62).
For a block cursor (REG[16h] bit 7 = 1), these bits set the height (or vertical size) of the
cursor, in lines from the character origin (see Figure 10-7 “Cursor Size and Position,” on
page 62).
REG[16h] bits 3-0 = cursor height in lines - 1
Note
The vertical cursor size must be less than or equal to the vertical character size.
(REG[16h] bits 3-0 <= REG[02h] bits 3-0)
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CSRDIR
The CSRDIR command controls cursor movement when indirect addressing is used. The
values from REG[17h] are passed as part of the command when the CSRDIR command is
issued. For further information on the CSRDIR command, see Section 11.1.6, “CSRDIR”
on page 76.
REG[17h] Cursor Shift Direction Register
Address = 8017h
Read/Write
n/a
7
bits 1-0
6
5
Cursor Shift Direction bits 1-0
4
3
2
1
0
Cursor Shift Direction bits [1:0]
These bits set the direction of automatic cursor increment when the cursor is automatically
moved after a memory access (read or write). The cursor can move left/right by one character or up/down by the number of bytes specified by the horizontal address range (or
address pitch), REG[06h] - REG[07h]. When reading from and writing to display memory, this automatic cursor increment controls the display memory address increment on
each read or write.
10
–AP
01
–1
+1
00
+AP
11
AP = Horizontal Address Range
(REG[06h] bits 7-0, REG[07h] bits 7-0)
Figure 10-8 Cursor Direction
Table 10-8 Cursor Shift Direction
Direct Mode
Bit 1
Bit 0
Indirect Mode
Command
Shift Direction
0
0
4C
Right
0
1
4D
Left
1
0
4E
Up
1
1
4F
Down
Note
The cursor moves in address units even if horizontal character size is equal to 9
(REG[01h] bits 3-0 = 9), therefore the cursor address increment must be preset for
movement in character units. For further information, see Section 12.3, “Cursor Control” on page 86.
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OVLAY
The OVLAY command selects layered screen composition and screen text/graphics mode
when indirect addressing is used. The values from REG[18h] are passed as parameters
when the OVLAY command is issued. For further information on the OVLAY command,
see Section 11.1.7, “OVLAY” on page 77.
REG[18h] Overlay Register
Address = 8018h
Read/Write
n/a
7
6
5
3 Layer Overlay
Select
Screen Block 3
Display Mode
Screen Block 1
Display Mode
4
3
2
Layer Composition Method bits 1-0
1
0
bit 4
3 Layer Overlay Select (OV)
This bit determines how many layers are used when graphics mode is enabled. For mixed
text and graphics, this bit must be set to 0.
When this bit = 0, two layers are used.
When this bit = 1, three layers are used.
bit 3
Screen Block 3 Display Mode (DM1)
This bit determines the display mode for screen block 3.
When this bit = 0, screen block 3 is configured for text mode.
When this bit = 1, screen block 3 is configured for graphics mode.
Note
Screen blocks 2 and 4 can display graphics only.
bit 2
Screen Block 1 Display Mode (DM0)
This bit determines the display mode for screen block 1.
When this bit = 0, screen block 1 is configured for text mode.
When this bit = 1, screen block 1 is configured for graphics mode.
Note
Screen blocks 2 and 4 can display graphics only.
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bits 1-0
Layer Composition Method (MX) bits [1:0]
These bits select the layered screen composition method, which can be OR, AND, or
Exclusive-OR. Since the screen composition is organized in layers and not by screen
blocks, when using a layer divided into two screen blocks, different composition methods
cannot be specified for the individual screen blocks.
Table 10-9 Composition Method Selection
REG[18h] bit 1 REG[18h] bit 0
Function
Composition Method
Applications
0
0
L1 ∪ L2 ∪ L3
OR
0
1
(L1 ⊕ L2) ∪ L3
Exclusive-OR
Inverted characters, flashing regions, underlining
1
0
(L1 ∩ L2) ∪ L3
AND
Simple animation, three-dimensional appearance
1
1


Underlining, rules, mixed text and graphics
Reserved
Note
L1: First layer (text or graphics). If text is selected, layer L3 cannot be used.
L2: Second layer (graphics only)
L3: Third layer (graphics only)
Layer 1
Layer 2
Layer 3
Visible display
1
EPSON
EPSON OR
2
EPSON
EPSON Exclusive OR
3
EPSON
SON AND
Figure 10-9 Combined Layer Display Examples
Note
L1: Not flashing
L2: Flashing at 1 Hz
L3: Flashing at 2 Hz
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CGRAM ADR
The CGRAM ADR command sets the start address of the character generator RAM
(CGRAM) when indirect addressing is used. The values from REG[19h] through
REG[1Ah] are passed as parameters when the CGRAM ADR command is issued. For
further information on the CGRAM ADR command, see Section 11.1.8, “CGRAM ADR”
on page 77.
REG[19h] Character Generator RAM Start Address Register 0
Address = 8019h
Read/Write
CGRAM Start Address bits 7-0 (LSB)
7
6
5
4
3
2
1
REG[1Ah] Character Generator RAM Start Address Register 1
Address = 801Ah
0
Read/Write
CGRAM Start Address bits 15-8 (MSB)
7
bits 15-0
6
5
4
3
2
1
0
Character Generator RAM Start Address bits [15:0]
These bits determine the memory start address of the Character Generator RAM
(CGRAM). The exact memory location of the start of each character stored in CGRAM
can be calculated by multiplying the character code index by the character height and adding the total to the CGRAM start address.
For example, to determine the address of a 8x8 character at character code index 80h with
a CGRAM start address of 6000h, the following calculation can be used.
character start = (character code index x character height) + CGRAM start address
= (80h x 8) + 6000h
= 400h + 6000h
= 6400h
The character starts in RAM at address 6400h and takes 8 memory locations.
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HDOT SCR
The HDOT SCR command sets the horizontal scroll position when indirect addressing is
used. The values from REG[1Bh] are passed as parameters when the HDOT SCR command
is issued. For further information on the HDOT SCR command, see Section 11.1.9, “HDOT
SCR” on page 77.
Normal scrolling on text screens allows scrolling of entire characters only. The HDOT SCR
command provides horizontal pixel scrolling for text screens. HDOT SCR cannot be used
on individual layers.
Note
HDOT SCR must be set to zero for all display modes except 1 bpp (REG[20h] Bit-PerPixel Select Register bits 1-0 = 0).
REG[1Bh] Horizontal Pixel Scroll Register
Address = 801Bh
Read/Write
n/a
7
bits 2-0
6
Horizontal Pixel Scroll bits 2-0
5
4
3
2
1
0
Horizontal Pixel Scroll bits [2:0]
These bits specify the number of horizontal pixels to scroll the display. The character
bytes per row (C/R), REG[03h] bits 7-0, must be set to one more than the actual number of
horizontal characters before using horizontal pixel scroll. Smooth scrolling can be simulated by repeatedly changing the value of REG[1Bh] bits 2-0. See Section 12.5, “Scrolling” on page 92 for more information on scrolling the display.
M
A
Z
B
A
Z
X
B
A
Y
X
B
X
Display width
M=0
N=0
Y
Y
N
M/N is the number of bits (dots) that parameter 1 (P1)
is incremented/decremented by.
Figure 10-10 Horizontal Scrolling
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10.3.3 Drawing Control Registers
CSRW
The CSRW command sets the cursor address when indirect addressing is used. The values
from REG[1Ch] through REG[1Dh] are passed as parameters when the CSRW command
is issued. For further information on the CSRW command, see Section 11.1.10, “CSRW”
on page 78.
REG[1Ch] Cursor Write Register 0
Address = 801Ch
Write Only
Cursor Write bits 7-0 (LSB)
7
6
5
4
3
2
1
REG[1Dh] Cursor Write Register 1
Address = 801Dh
0
Write Only
Cursor Write bits 15-8 (MSB)
7
bits 15-0
6
5
4
3
2
1
0
Cursor Write (CSRW) bits [15:0]
These bits set the display memory address to the data at the cursor position as shown in
Figure 12-10 “Cursor Movement,” on page 88.
Note
The microprocessor cannot directly access the display memory in indirect addressing
mode.
For Indirect Addressing Mode:
The MREAD and MWRITE commands use the address in this register when in indirect
mode. The cursor address register can only be modified by the CSRW command, and by
the automatic increment after an MREAD or MWRITE command. It is not affected by
display scrolling.
If a new address is not set, display memory accesses are from the last set address or the
address after previous automatic increments.
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CSRR
The CSRR command reads the cursor address when indirect addressing is used. The values
from REG[1Eh] through REG[1Fh] are passed as parameters when the CSRR command is
issued. For further information on the CSRR command, see Section 11.1.11, “CSRR” on
page 78.
REG[1Eh] Cursor Read Register 0
Address = 801Eh
Read Only
Cursor Read bits 7-0 (LSB)
7
6
5
4
3
2
1
REG[1Fh] Cursor Read Register 1
Address = 801Fh
0
Read Only
Cursor Read bits 15-8 (MSB)
7
bits 15-0
6
5
4
3
2
1
0
Cursor Read (CSRR) bits [15:0]
These bits are only used in Indirect Addressing mode.
These bits indicate the memory address where the cursor is currently located. After issuing
the command, the data read address is read twice. Once for the low byte and then again for
the high byte of the register.
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10.3.4 Gray Scale Register
GRAYSCALE
The GRAYSCALE command selects the gray scale depth, in bits-per-pixel (bpp), when
indirect addressing is used. The values from REG[20h] are passed as parameters when the
GRAYSCALE command is issued. For further information on the GRAYSCALE
command, see Section 11.1.12, “GRAYSCALE” on page 78.
REG[20h] Bit-Per-Pixel Select Register
Address = 8020h
Read/Write
n/a
7
bits 1-0
6
Bit-Per-Pixel Select bits 1-0
5
4
3
2
1
0
Bit-Per-Pixel Select bits [1:0]
These bits select the bit-per-pixel mode as follows.
Table 10-10 Bit-Per-Pixel Selection
REG[20h] bits 1-0
Bits-Per-Pixel
00
1
01
2
10
4
11
Reserved
Note
The horizontal character size (REG[01h] bits 3-0) must be set to 7h and the Horizontal
Pixel Scroll bits (REG[1Bh] bits 2-0) must be set to 0.
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11 Indirect Addressing
Table 11-1 Indirect Addressing Command Set
Class
System
Control
Register
Address
Command
8000h - 8007h
8008h
8009h - 800A
Display
Control
Drawing
Control
Memory
Control
Register Description
Control Byte
No. of Bytes
Value
SYSTEM SET Initializes device and display
40h
8
POWER SAVE Enters standby mode
53h
0
Enables/disables display and display
DISP ON/OFF
attributes
58h
59h
1
44h
10
800Bh - 8014h
SCROLL
Sets screen block start addresses and sizes
8015h - 8016h
CSRFORM
8017h
CSRDIR
Sets direction of cursor movement
8018h
OVLAY
8019h - 801Ah
CGRAM ADR
Sets cursor type
5Dh
2
4Ch - 4Fh
0
Sets display overlay format
5Bh
1
Sets start address of character generator
RAM
5Ch
2
801Bh
HDOT SCR
Sets horizontal scroll position
5A
1
801Ch - 801Dh
CSRW
Sets cursor address
46h
2
801Eh - 801Fh
CSRR
Reads cursor address
47h
2
8020h
GRAYSCALE
Sets the Grayscale depth (bpp)
60h
1
MEMWRITE
Writes to memory
42h
MEMREAD
Reads from memory
43h
n/a
Table 11-2 Generic Indirect Addressing Command/Write/Read
A0
WR
RD
1
0
1
Command [C]
1
1
0
Parameter Read [P#]
0
0
1
Parameter Write [P#]
Table 11-3 M6800 Indirect Addressing Command/Write/Read
A0
R/W
E
1
0
1
Command write
1
1
1
Display data and cursor address read
0
0
1
Display data and parameter write
Table 11-4 M68K Indirect Addressing Command/Write/Read
A0
R/W LDS#
1
0
0
Command write
1
1
0
Display data and cursor address read
0
0
0
Display data and parameter write
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11.1 System Control
See Section 15.1.2, “Initialization Example” on page 105 for the initialization sequence.
11.1.1 SYSTEM SET
See Section , “SYSTEM SET” on page 48 for further information.
Table 11-5 SYSTEM SET Command and Parameters
MSB
LSB
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Indirect
0
1
0
0
0
0
0
0
C
0
0
IV1
0
W/S2
M23
0
M04
P1
MOD5
0
0
0
REG[01h] bits 3-0
P2
0
0
0
0
REG[02h] bits 3-0
P3
REG[03h] bits 7-0
P4
REG[04h] bits 7-0
P5
REG[05h] bits 7-0
P6
REG[06h] bits 7-0
P7
REG[07h] bits 7-0
P8
Note
1
2
3
4
5
IV is the Screen Origin Compensation bit, REG[00h] bit 5.
W/S is the Panel Drive Select bit, REG[00h] bit 3.
M2 is the Character Height bit, REG[00h] bit 2.
M0 is the Character Generator Select bit, REG[00h] bit 0.
MOD is defined by REG[01h] bit 7.
11.1.2 POWER SAVE
See Section , “POWER SAVE” on page 55 for further information.
Table 11-6 POWER SAVE Command
MSB
LSB
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Indirect
0
1
0
1
0
0
1
1
C
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11.1.3 DISP ON/OFF
The following parameters are used for the DISP ON command. For further details, see
Section , “DISP ON/OFF” on page 56.
Table 11-7 DISP ON Command and Parameters
MSB
LSB
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Indirect
0
1
0
1
1
0
0
1
C
REG[0Ah] bits 7-0
P1
The following parameters are used for the DISP OFF command. For further details, see
Section , “DISP ON/OFF” on page 56.
Table 11-8 DISP OFF Command and Parameters
MSB
LSB
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Indirect
0
1
0
1
1
0
0
0
C
REG[0Ah] bits 7-0
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11.1.4 SCROLL
See “SCROLL” on page 58 for further information.
Table 11-9 SCROLL Command and Parameters
MSB
LSB
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Indirect
0
1
0
0
0
1
0
0
C
A7
A6
A5
A4
A3
A2
A1
A0
REG[0Bh] bits 7-0
P1
A15
A14
A13
A12
A11
A10
A9
A8
REG[0Ch] bits 7-0
P2
L7
L6
L5
L4
L3
L2
L1
L0
REG[0Dh] bits 7-0
P3
A7
A6
A5
A4
A3
A2
A1
A0
REG[0Eh] bits 7-0
P4
A15
A14
A13
A12
A11
A10
A9
A8
REG[0Fh] bits 7-0
P5
L7
L6
L5
L4
L3
L2
L1
L0
REG[10h] bits 7-0
P6
A7
A6
A5
A4
A3
A2
A1
A0
REG[11h] bits 7-0
P7
A15
A14
A13
A12
A11
A10
A9
A8
REG[12h] bits 7-0
P8
A7
A6
A5
A4
A3
A2
A1
A0
REG[13h] bits 7-0
P9
A15
A14
A13
A12
A11
A10
A9
A8
REG[14h] bits 7-0
P10
Note
Set parameters P9 and P10 only if both dual panel (REG[00h] bit 3 = 1) and two-layer
configuration are selected. SAD4 is the fourth screen block display start address.
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11.1.5 CSRFORM
See “CSRFORM” on page 62 for further information.
Table 11-10 CSRFORM Command and Parameters
MSB
LSB
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Indirect
0
1
0
1
1
1
0
1
C
0
0
0
0
CM1
0
0
0
REG[15h] bits 3-0
X3
X2
X1
X0
REG[16h] bits 3-0
Y3
Y2
Y1
Y0
P1
P2
Note
1
CM is the Cursor Mode bit, REG[16h] bit 7.
11.1.6 CSRDIR
See “CSRDIR” on page 64 for further information.
Table 11-11 CSRDIR Command
MSB
bit 7
0
LSB
bit 6
1
bit 5
0
bit 4
0
bit 3
bit 2
1
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bit 1
bit 0
Indirect
REG[17h] bits 1-0
CD1
CD0
C
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11.1.7 OVLAY
See “OVLAY” on page 65 for further information.
Table 11-12 OVLAY Command and Parameters
MSB
LSB
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Indirect
0
1
0
1
1
0
1
1
C
0
0
0
OV1
MX13
MX03
P1
DM22 DM12
Note
1
2
3
OV is the 3 Layer Overlay Select bit, REG[18h] bit 4.
DM2 and DM1 are the Screen Block 3/1 Display Mode bits, REG[18h] bits 3-2.
MX1 and MX0 are the Layer Composition Method bits, REG[18h] bits 1-0.
11.1.8 CGRAM ADR
See “CGRAM ADR” on page 67 for further information.
Table 11-13 CGRAM ADR Command and Parameters
MSB
LSB
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Indirect
0
1
0
1
1
1
0
0
C
A7
A6
A5
A4
A3
A2
A1
A0
(SAGL)
P1
A15
A14
A13
A12
A11
A10
A9
A8
(SAGH)
P2
11.1.9 HDOT SCR
See “HDOT SCR” on page 68 for further information.
Table 11-14 HDOT SCR Command and Parameters
MSB
LSB
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Indirect
0
1
0
1
1
0
1
0
C
0
0
0
0
0
D2
D1
D0
P1
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11.1.10 CSRW
See “CSRW” on page 69 for further information.
Table 11-15 CSRW Command and Parameters
MSB
LSB
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Indirect
0
1
0
0
0
1
1
0
C
A7
A6
A5
A4
A3
A2
A1
A0
(CSRL)
P1
A15
A14
A13
A12
A11
A10
A9
A8
(CSRH)
P2
11.1.11 CSRR
See “CSRR” on page 70 for further information.
Table 11-16 CSRR Command and Parameters
MSB
LSB
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Indirect
0
1
0
0
0
1
1
1
C
A7
A6
A5
A4
A3
A2
A1
A0
(CSRL)
P1
A15
A14
A13
A12
A11
A10
A9
A8
(CSRH)
P2
11.1.12 GRAYSCALE
See Section , “GRAYSCALE” on page 71 for further information.
Table 11-17 Gray Scale Command and Parameters
MSB
LSB
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Indirect
0
1
1
0
01
0
0
0
C
0
0
0
0
0
0
BPP1 BPP0
P1
11.1.13 Memory Control
See “Drawing Control Registers” on page 69 for further information.
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12 Display Control Functions
12.1 Character Configuration
The origin of each character bitmap is the top left corner as shown in Figure 12-1. Adjacent
bits in each byte are horizontally adjacent in the corresponding character image.
Although the size of the bitmap is fixed by the character generator, the actual displayed size
of the character field can be varied in both dimensions.
Character starting point
FX
D7
Character
height
FY
Space
Character width
to
D0
R0
0
1
1
1
0
0
0
0
R1
1
0
0
0
1
0
0
0
R2
1
0
0
0
1
0
0
0
R3
1
0
0
0
1
0
0
0
R4
1
1
1
1
1
0
0
0
R5
1
0
0
0
1
0
0
0
R6
1
0
0
0
1
0
0
0
R7
0
0
0
0
0
0
0
0
R8
0
0
0
0
0
0
0
0
R9
0
0
0
0
0
0
0
0
R10
0
0
0
0
0
0
0
0
R11
0
0
0
0
0
0
0
0
R12
0
0
0
0
0
0
0
0
R13
0
0
0
0
0
0
0
0
R14
0
0
0
0
0
0
0
0
R15
0
0
0
0
0
0
0
0
Space
data
Space
data
Space
Where:
FX = horizontal character size is 16 pixels (REG[01h] bits 3-0)
FY = vertical character size is 16 pixels (REG[02h] bits 3-0)
Figure 12-1 Example of Character Display from Generator Bitmap (when [FX] ≤ 8)
If the area outside the character bitmap contains only zeros, the displayed character size can
be increased by increasing the horizontal character size (REG[01h] bits 3-0) and the vertical
character size (REG[01h] bits 3-0). The zeros ensure that the extra space between displayed
characters is blank.
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The displayed character width can be set to any value up to 16 even if each horizontal row
of the bitmap is two bytes wide.
Horizontal
non-display
area
FX
Character
Height
FY
16 dots
Space
Vertical
non-display
area
8 dots
8 dots
Character width
Space
Where:
FX = horizontal character size is 16 pixels (REG[01h] bits 3-0)
FY = vertical character size is 16 pixels (REG[02h] bits 3-0)
Figure 12-2 Character Width Greater than One Byte Wide ([FX] = 9)
Note
The S1D13700 does not automatically insert spaces between characters. If the displayed
character size is 8 pixels or less and the space between character origins is nine pixels or
more, the bitmap must use two bytes per row, even though the character image requires
only one.
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12.2 Screen Configuration
12.2.1 Screen Configuration
The S1D13700 can be configured for a single text screen, overlapping text screens, or
overlapping graphics screens. Graphics screens use eight times as much display memory as
a text screen in 1 bpp. Figure 12-3 shows the relationship between the virtual screens and
the physical screen.
REG[0
6h],
REG[0
3h]
REG[0
7h]
0000h
Character
memory area
0800h
07FFh
Display
Memory
Window
Graphics
memory area
47FFh
(0,YM)
(XW,YM)
(X,Y)
Y
(XM,YM)
(0,0)
X
(XM,0)
Figure 12-3 Virtual and Physical Screen Relationship
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12.2.2 Display Address Scanning
The S1D13700 scans the display memory in the same way as a raster scan CRT screen.
Each row is scanned from left to right until the address range equals C/R, REG[03h] bits 70. Rows are scanned from top to bottom. When in graphics mode, at the start of each line
the address counter is set to the address at the start of the previous line plus the horizontal
address range (or address pitch), REG[06h] - REG[07h].
In text mode, the address counter is set to the same start address, and the same character
data is read, for each row in the character bitmap. However, a new row of the character
generator output is used each time. Once all the rows in the character bitmap have been
displayed, the address counter is set to the start address plus the horizontal address range
(or address pitch) and the next line of text is displayed.
1
•
•
•
8
9
•
•
•
16
17
•
•
•
24
•
•
•
•
SAD
SAD + 1
SAD + 2
SAD + C/R
SAD + AP
SAD + AP
+1
SAD + AP
+2
SAD + AP
+ C/R
SAD + 2AP
C/R
Where:
SAD = start address of the screen block
AP = horizontal address range (REG[06h], REG[07h])
C/R = number of character bytes per row (REG[03h])
Note
Assumes REG[00h] bit 3 = 0, REG[01h] bits 3-0 = 8, REG[02h] bits 3-0 = 8
Figure 12-4 Display Addressing in Text Mode Example
Note
One byte of display memory corresponds to one character.
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1
SAD
SAD +1
SAD + 2
SAD + C/R
2
SAD + AP
SAD + AP
+1
SAD + AP
+2
SAD + AP
+ C/R
3
SAD + 2AP
Line 1
•
•
•
•
•
•
•
•
SAD
SAD +1
SAD + 2
AP
SAD + C/R
Line 2
SAD + AP
SAD + AP + 1
AP
SAD + AP + C/R
SAD + 2AP
Line 3
REG[03h] bits 7-0
Where:
SAD = start address of the screen block
AP = horizontal address range (REG[06h], REG[07h])
C/R = number of character bytes per row (REG[03h])
Note
Assumes REG[00h] bit 3 = 0, REG[01h] bits 3-0 = 8
Figure 12-5 Display Addressing in Graphics Mode Example
Note
In 1 bpp, one bit of display memory corresponds to one pixel. Therefore, 1 byte of display memory corresponds to 8 pixels. In 2 bpp, 1 byte corresponds to 4 pixels. In 4 bpp,
1 byte corresponds to 2 pixels.
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1a
•
•
•
8a
9a
•
•
•
16a
17a
•
•
•
24a
25a
•
•
•
(L/F)/2 =
1b
•
•
•
8b
9b
•
•
•
16b
17b
•
•
•
24b
25b
•
•
•
•
SAD1
SAD1 + 1
SAD1 + 2
SAD1 + C/R
SAD1 + AP
SAD1 + AP
+1
SAD1 + AP
+2
SAD1 + AP
+ C/R
SAD3 + 2
SAD3 + C/R
SAD3 + AP
+2
SAD3 + AP
+ C/R
SAD1 + 2AP
SAD3 + 1
SAD3 + AP
SAD3 + AP
+1
SAD3 + 2AP
(L/F)
C/R
Where:
SAD = start address of the screen block
AP = horizontal address range (REG[06h], REG[07h])
C/R = number of character bytes per row (REG[03h])
L/F = frame height in lines (REG[05h])
Note
Assumes REG[00h] bit 3 = 0, REG[01h] bits 3-0 = 8, REG[02h] bits 3-0 = 8
Figure 12-6 Dual Panel Display Address Indexing in Text Mode
Note
In dual panel drive, the S1D13700 reads line 1a and line 1b as one cycle. The upper and
lower panels are thus read alternately, one line at a time.
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12.2.3 Display Scan Timing
During display scanning, the S1D13700 pauses at the end of each line for TC/R - C/R
((REG[04h] bits 7-0) - (REG[03h] bits 7-0)) display memory read cycles, although the
LCD drive signals are still generated. TC/R may be set to any value within the constraints
imposed by C/R, Input Clock (CLK), fFR, and the size of the LCD panel. This pause may
be used to fine tune the frame frequency. Alternately, the microprocessor may use this
pause to access the display memory data.
Display period
Divider frequency
period
TC/R
C/R
Line 1
O
R
2
O
R
3
O
R
O
R
Frame
period
•
•
•
•
•
L/F
FPLINE
Where:
C/R = character bytes per row (REG[03h] bits 7-0)
TC/R = total character bytes per row (REG[04h] bits 7-0)
L/F = frame height in lines (REG[05h] bits 7-0)
Figure 12-7 Relationship Between Total Character Bytes Per Row and Character Bytes Per Row
Note
The divider adjustment interval (R) applies to both the upper and lower screens even if a
dual panel drive is selected, REG[00h] bit 3 = 1. In this case, FPLINE is active only at
the end of the lower screen’s display interval.
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12.3 Cursor Control
12.3.1 Cursor Write Register Function
The Cursor Write register (REG[1Ch] - REG[1Dh]) functions as both the displayed cursor
position address register and, in indirect addressing mode, the display memory access
address register. When accessing display memory outside the actual visible screen
memory, the Cursor Write register should be saved before accessing the memory and then
restored after the memory access is complete. This is done to prevent the cursor from
visibly disappearing outside the display area.
Cursor display
address register
REG[1Ch], REG[1Dh]
Address pointer
Figure 12-8 Cursor Addressing
Note
The cursor may disappear from the display if the cursor address remains outside the displayed screen memory for more than a few hundred milliseconds.
12.3.2 Cursor Movement
On each memory access, the Cursor Write register (REG[1Ch] - REG[1Dh]) is changed by
the amount specified by the CSRDIR command (see REG[17h] bits 1-0) which automatically moves the cursor to the desired location.
12.3.3 Cursor Display Layers
Although the S1D13700 can display up to three layers, the cursor is displayed in only one
of these layers. For a two layer configuration (REG[18h] bit 4 = 0), the cursor is displayed
in the first layer (L1). For a three layer configuration (REG[18h] bit 4 = 1), the cursor is
displayed in the third layer (L3).
The cursor is not displayed if the address is moved outside of the memory for its layer. If it
is necessary to display the cursor in a layer other than the present one, the layers may be
swapped, or the cursor layer can be moved within the display memory.
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Although the cursor is normally displayed for character data, the S1D13700 may also
display a dummy cursor for graphical characters. This is only possible if a graphics screen
is displayed, the text screen is turned off, and the microprocessor generates the cursor
control address.
D (REG[09h] bit 0) = 1
FC1 (REG[0Ah] bit 1) = 0
Cursor ON
FC0 (REG[0Ah] bit 0) = 1
FP1 (REG[0Ah] bit 3) = 0
FP0 (REG[0Ah] bit 2) = 0
FP3 (REG[0Ah] bit 5) = 0
FP2 (REG[0Ah] bit 4) = 1
Screen Block 1 Off
(text screen)
Screen Block 2 On
(graphics screen)
Figure 12-9 Cursor Display Layers
For example, if Chinese characters are displayed on a graphics screen, the cursor address is
set to the second screen block in order to write the “graphics” display data. However, the
cursor is not displayed. To display the cursor, the cursor address must be set to an address
within the blank text screen block.
Since the automatic cursor increment is in address units, not character units, the controlling
microprocessor must set the Cursor Write register (REG[1Ch] - REG[1Dh]) when moving
the cursor over the graphical characters.
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8 dots 8 dots
8 dots 8 dots
Block cursor
18 dots
Auto shift
Auto shift
Auto shift
Cursor address preset
Figure 12-10 Cursor Movement
If no text screen is displayed, only a bar cursor can be displayed at the cursor address.
If the first layer is a mixed text and graphics screen and the cursor shape is set to a block
cursor, the S1D13700 automatically decides which cursor shape to display. On the text
screen it displays a block cursor, and on the graphics screen, a bar cursor.
12.4 Memory to Display Relationship
The S1D13700 supports virtual screens that are larger than the physical size of the LCD
panel address range (C/R), REG[03h] bits 7-0. A layer of the S1D13700 can be considered
as a window into the larger virtual screen held in display memory. This window can be
divided into two blocks, with each block able to display a different portion of the virtual
screen.
For example, this allows one block to dynamically scroll through a data area while the other
block is used as a status message display area.
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For examples of the memory to display relationships, see Figure 12-11 “Screen Layers and
Memory Relationship,” on page 89 and Figure 12-12 “Virtual Display (Display Window to
Memory Relationship),” on page 90, and Figure 12-13 “Memory Map and Magnified
Characters,” on page 91.
AP
C/R
SAD1
REG[00h] bit 3 = 0
SAD3
Character page 1
SAD1
Character page 3
SAD3
Display page 1
REG[00h] bit 3 = 1
Display page 1
Display page 3
SAD2
Layer 1
SAD4
Graphics page 2
SAD2
Layer 1
Graphics page 2
SAD4
Display page 2
Display page 2
C/R
Display page 4
Layer 2
Layer 2
CGRAM
SAD1
C/R
Character page 1
SAD1
SAD3
SAD2
Display page 1
C/R
SAD3 Character page 3
Display page 3
Layer 1
C/R
SAD2
Display page 2
Graphics page 2
Layer 2
SAD3
C/R
Graphics page 3
SAD3
SAD2
Display page 3
SAD1
Display page 2
Display page 1
C/R
SAD2 Graphics page 2
C/R
SAD1
Layer 1
Graphics page 1
Layer 2
Layer 3
Where:
SADx = start address of screen block x
AP = horizontal address range (REG[06h], REG[07h])
C/R = number of character bytes per row (REG[03h])
Figure 12-11 Screen Layers and Memory Relationship
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AP
0000h
SAD1
FX
CRY
FY
CSRA
CRX
Display
window
L/F
Virtual display
memory limit
C/R
FFFFh
Where:
FX = horizontal character size is 16 pixels (REG[01h] bits 3-0)
FY = vertical character size is 16 pixels (REG[02h] bits 3-0)
CRX = cursor width is 16 pixels (REG[15h] bits 3-0)
CRY = cursor height is 16 pixels (REG[16h] bits 3-0)
C/R = character bytes per row is 240 bytes (REG[03h] bits 7-0)
L/F = frame height is 256 (REG[05h] bits 7-0)
AP = horizontal address range (or address pitch) is 64K bytes (REG[06h] bits 7-0, REG[07h] bits 7-0)
Figure 12-12 Virtual Display (Display Window to Memory Relationship)
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SAD1
D7
0000
SL1
Character
code
Page 91
to
D0
D7
to
D0
A (Code)
Page 1
0000
ABC
B
0300
0400
C
Page 2
0800
SAD2
SL2
XY
Display
X
Page 1
02FF
Y
2000
2800
Back
layer
0080
(MSB)
D7
Page 2
SAG
(LSB)(MSB)
D0 D7
(LSB)
D0
4440
4800
1FFF
CG RAM
4A00
D7
Not used
802F
8030
Internal ROM
70h
88h
88h
88h
F8h
88h
88h
00h
D0
01110000
10001000
10001000
10001000
11111000
10001000
10001000
00000000
#4800
1
2
3
4
5
6
#4807
Magnified image
Example of character A
Figure 12-13 Memory Map and Magnified Characters
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12.5 Scrolling
The microprocessor can control S1D13700 scrolling modes by writing the scroll address
registers for each screen block, REG[0Bh] - REG[14h]. This is referred to as address
scrolling and can be used for both text and graphic screen blocks, if the display memory
capacity is greater than one screen.
12.5.1 On-Page Scrolling
The normal method of scrolling within a page is to move the whole display up one line and
erase the bottom line. However, the S1D13700 does not automatically erase the bottom
line, so it must be erased with blanking data when changing the scroll address register.
Display memory
AP
Before scrolling
After scrolling
C/R
ABC
WXYZ
WXYZ
789
789
SAD1
ABC
WXYZ
789
WXYZ
789
SAD3
SAD1
Blank
Blank
Where:
SADx = start address of screen block x
AP = horizontal address range (REG[06h] bits 7-0, REG[07h] bits 7-0)
C/R = character bytes per row (REG[03h] bits 7-0)
Figure 12-14 On-Page Scrolling
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12.5.2 Inter-Page Scrolling
Scrolling between pages and page switching can be performed only if the display memory
capacity is greater than one screen. To scroll down one line/character, add the value of the
horizontal address range (or address pitch), REG[06h] - REG[07h], to the current SADx.
To scroll up, subtract the value of the horizontal address range from SADx.
Display memory
AP
C/R
Before scrolling
After scrolling
ABC
ABC
WXYZ
789
WXYZ
789
SAD1
SAD1
WXYZ
789
ABC
WXYZ
789
Where:
SADx = start address of screen block x
AP = horizontal address range (REG[06h] bits 7-0, REG[07h] bits 7-0)
C/R = character bytes per row (REG[03h] bits 7-0)
Figure 12-15 Inter-Page Scrolling
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12.5.3 Horizontal Wraparound Scrolling
For screen block in text mode, the display can be scrolled horizontally in one character
units, regardless of the display memory capacity.
Display memory
Display
Before scrolling
ABC
123
XYZ
SAD1
ABC
123
XYZ
AP
C/R
After scrolling
BC
23
XYZ1
SAD1
ABC
123
XYZ
Where:
SADx = start address of screen block x
AP = horizontal address range (REG[06h] bits 7-0, REG[07h] bits 7-0)
C/R = character bytes per row (REG[03h] bits 7-0)
Figure 12-16 Horizontal Wraparound Scrolling
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12.5.4 Bi-directional Scrolling
Bi-directional scrolling can be performed only if the display memory is larger than the
physical screen in both the horizontal (REG[06h], REG[07h] > REG[03h]) and vertical
directions. Scrolling is normally done in single-character units, however the HDOT SCR
command (see REG[1Bh] bits 2-0) allows horizontal scrolling in pixel units (for text blocks
only). Single pixel horizontal scrolling can be performed using both the SCROLL and
HDOT SCR commands. For more information, see Section 15.3, “Smooth Horizontal
Scrolling” on page 116.
Note
In 2 bpp and 4 bpp grayscale mode REG[1Bh] bits 2-0 (HDOT SCR) must be set to 0, so
horizontal scrolling can only be done in single character units (not pixel units).
Display memory
Before scrolling
BC
EFG
TUV
AP
12
A BC
EFG
TUV
C/R
After scrolling
FG
TUV
12 34
567
89
ABC
E FG
TUV
1234
56
1234
56 7
89
Where:
AP = horizontal address range (REG[06h] bits 7-0, REG[07h] bits 7-0)
C/R = character bytes per row (REG[03h] bits 7-0)
Figure 12-17 Bi-Directional Scrolling
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12.5.5 Scroll Units
The following table summarizes the units, or steps, that can be scrolled for each mode.
Table 12-1 Scrolling Unit Summary
Mode
Vertical
Horizontal
Text
Characters
Pixels or Characters
Graphics
Pixels
Pixels
Note
In a divided screen, each block cannot be independently scrolled horizontally in pixel
units.
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13 Character Generator
13.1 CG Characteristics
13.1.1 Internal Character Generator
The internal character generator is recommended for minimum system configurations
containing a S1D13700, display RAM, LCD panel, single-chip microprocessor and power
supply. Since the internal character generator uses a CMOS mask ROM, it is also recommended for low-power applications.
• 5 x 7 pixel font (See Section 16, “Internal Character Generator Font” on page 125)
• 160 JIS standard characters
• Can be mixed with character generator RAM (maximum of 64 CGRAM characters)
• Can be automatically spaced out up to 8 x 16 pixels
13.1.2 Character Generator RAM
The character generator RAM can be used for storing graphics characters. The character
generator RAM can be mapped to any display memory location by the microprocessor,
allowing effective usage of unused address space.
• Up to 8 x 8 pixel characters when REG[00h] bit 2 = 0 and 8 x 16 characters when
REG[00h] bit 2 = 1
• Can be mapped anywhere in display memory address space if used with the character
generator ROM (REG[00h] bit 0 = 0)
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13.2 Setting the Character Generator Address
The CGRAM addresses in the display memory address space are not mapped directly from
the address in the Character Generator RAM Start Address registers, REG[19h] REG[1Ah]. The data to be displayed is at a CGRAM address calculated from (REG[19h] REG[1Ah]) + character code + ROW select address. For the ROW select address, see
Figure 13-1 “Row Select Address,” on page 99.
The following tables show the address mapping for CGRAM addresses.
Table 13-1 Character Fonts Where Number of Lines ≤ 8 (REG[00h] bit 2 = 0)
SAG
A15 A14 A13 A12 A11 A10
Character Code
+ROW Select Address
CGRAM Address
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
D7
D6
0
0
0
0
0
0
0
VA15 VA14 VA13 VA12 VA11 VA10 VA9
0
0
0
0
0
0
R2
R1
R0
VA8
VA7
VA6
VA5
VA4
VA3
VA2
VA1
VA0
Table 13-2 Character Fonts Where Number of Lines ≤ 16 (REG[00h] bit 2 = 1)
SAG
Character Code
+ROW Select Address
CGRAM Address
A15 A14 A13 A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
D7
D6
D5
0
0
0
0
0
0
0
VA15 VA14 VA13 VA12 VA11 VA10 VA9
S1D13700
X42A-A-001-00
0
0
0
0
0
R3
R2
R1
R0
VA8
VA7
VA6
VA5
VA4
VA3
VA2
VA1
VA0
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Row
R3
R2
R1
R0
Row 0
0
0
0
0
Row 1
0
0
0
1
Row 2
0
0
1
0
Line 1
Line 2
Row 7
0
1
1
1
Row 8
1
0
0
0
Row 14
1
1
1
0
Row 15
1
1
1
1
Figure 13-1 Row Select Address
Note
Lines = 1: lines in the character bitmap ≤ 8.
Lines = 2: lines in the character bitmap ≥ 9.
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13.2.1 CGRAM Addressing Example
Example 1: Define a pattern for the “A” in Figure 12-1 on page 79. The CGRAM table
start address is 4800h. The character code for the defined pattern is 80h
(the first character code in the CGRAM area).
As the character codes in Figure 13-2 “On-Chip Character Codes,” on page 101 show,
codes 80h to 9Fh and E0h to FFh are allocated to the CGRAM and can be used as desired.
80h is the first code for the CGRAM. As characters cannot be used if only using graphics
mode, there is no need to set the CGRAM data.
Table 13-3 Character Data Example
CGRAM ADR
5Ch
P1
00h Reverse the CGRAM address calculation to calculate SAG
P2
40h
CSRDIR
CSRW
4Ch Set cursor shift direction to right
46h
P1
00h CGRAM start address is 4800h
P2
48h
MWRITE
42h
P
70h Write ROW 0 data
P2
88h Write ROW 1 data
P3
88h Write ROW 2 data
P4
88h Write ROW 3 data
P5
F8h Write ROW 4 data
P6
88h Write ROW 5 data
P7
88h Write ROW 6 data
P8
00h Write ROW 7 data
P9
00h Write ROW 8 data
↓
P16
↓
↓
00h Write ROW 15 data
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13.3 Character Codes
The following figure shows the character codes and the codes allocated to CGRAM. All
codes can be used by the CGRAM if not using the internal ROM, but the CGRAM address
must be set to 0.
Upper 4 bits
Lower 4 bits
0
1
2
0
3
4
5
6
7
0 @ P
'
p
1
!
1
A
Q
a
q
2
"
2
B
R
b
r
3
#
3
C
S
c
s
4
$
4
D
T
d
t
5
%
5
E
U
e
u
6
&
6
F
V
f
v
7
'
7
G W g
w
8
(
8
H
X
h
x
9
)
9
I
Y
i
y
A
*
:
J
Z
j
z
B
+
;
K
[
k
{
C
,
<
L
¥
l
|
D
.
=
M
]
m
}
E
-
>
N
^
n →
F
/
?
O
_
o ←
CGRAM1
8
9
A
B
C
D
E
F
CGRAM2
Figure 13-2 On-Chip Character Codes
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14 Microprocessor Interface
14.1 System Bus Interface
CNF[4:0], A[15:1], A0, D[7:0], RD#, WR#, AS and CS are used as control signals for the
microprocessor data bus. A0 is normally connected to the lowest bit of the system address
bus. CNF[4:2] change the operation of the RD# and WR# pins to enable interfacing to
either a Generic (Z80), M6800, or MC68K family bus, and should be pulled-up or pulleddown according to Table 5-6: “Summary of Configuration Options,” on page 24.
14.1.1 Generic
The following table shows the signal states for each function.
Table 14-1 Generic Interface Signals
A0
RD#
WR#
1
0
1
Display data and cursor address read
Function
0
1
0
Display data and parameter write
1
1
0
Command write
14.1.2 M6800 Family
The following table shows the signal states for each function.
Table 14-2 M6800 Family Interface Signals
A0
R/W#
E
Function
1
1
1
Display data and cursor address read
0
0
1
Display data and parameter write
1
0
1
Command write
14.1.3 MC68K Family
The following table shows the signal states for each function.
Table 14-3 M6800 Family Interface Signals
A0
RD/WR# LDS#
Function
1
1
0
Display data and cursor address read
0
0
0
Display data and parameter write
1
0
0
Command write
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15 Application Notes
15.1 Register Initialization/Initialization Parameters
Square brackets around a parameter name indicate the number represented by the
parameter, rather than the value written to the parameter register. For example, [FX] = FX
+ 1.
15.1.1 SYSTEM SET Command and Parameters
• FX
The horizontal character field size is determined from the horizontal display size in
pixels [VD] and the number of characters per line [VC].
[VD] / [VC] = [FX]
• C/R
C/R can be determined from VC and FX.
[C/R] = RND ([FX] / 8) [VC]
Where RND(x) denotes rounded up to the next highest integer. [C/R] is the number of
bytes per line, not the number of characters.
• TC/R
TC/R must satisfy the condition [TC/R] ≥ [C/R] + 2.
• fSYSCLK and fFR
Once TC/R has been set, the frame frequency, fFR, and lines per frame [L/F] will also
have been set. The oscillator frequency fSYSCLK is given by:
fSYSCLK = ([ClockDiv] x [bpp] x [TC/R'] x [FX] x [L/F] x Ffr) ÷ 4
where:
ClockDiv
bpp
Ffr
4, 8, or 16
1, 2, or 4
Frame Rate
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To determine the values for TC/R’, the following formulas must also be calculated.
A = (CR + 1) x (FX + 1) ÷ 4
B = (A ÷ 16)
C = 16 x B x 8 ÷ (FX + 1)
C = 16 x B x 16 ÷ (FX + 1)
D = (TC/R - CR) x 2
TC/R’ = (C + D) ÷ 2
round up to the nearest integer
(when [FX] ≤ 8)
(when [FX] > 8)
• If no standard crystal close to the calculated value of fOSC exists, a higher frequency
crystal can be used and the value of TC/R revised using the above equation.
• Symptoms of an incorrect TC/R setting are listed below. If any of these appears, check
the value of TC/R and modify it if necessary.
• Vertical scanning halts and a high-contrast horizontal line appears.
• All pixels are on or off.
• The FPLINE output signal is absent or corrupted.
• The display is unstable.
Table 15-1 Panel Calculations
Product Resolution
(X × Y
[FX]
[FY]
[C/R]
[TC/R]
fOSC (MHz)
See note 2
256 x 64
[FX] = 6 pixels:
[C/R] = 42 = 2Ah bytes:
8 or 16, depending
256 ÷ 6 = 42 remainder 4
C/R = 29h. When using HDOT
on the screen
= 4 blank pixels
SCR, [C/R] = 43 bytes
24h
1
512 x 64
[FX] = 6 pixels:
[C/R] = 85 = 55h bytes:
8 or 16, depending
512 ÷ 6 = 85 remainder 2
C/R = 54h. When using HDOT
on the screen
= 2 blank pixels
SCR, [C/R] = 86 bytes
62h
2.66
256 x 128
[FX] = 8 pixels:
[C/R] = 32 = 20h bytes:
8 or 16, depending
256 ÷ 8 = 32 remainder 0
C/R = 19h. When using HDOT
on the screen
= no blank pixels
SCR, [C/R] = 33 bytes
16h
1.84
512 x 128
[C/R] = 102 = 66h bytes:
[FX] = 10 pixels:
8 or 16, depending
C/R = 65h. When using HDOT
256 ÷ 10 = 51 remainder 2
on the screen
SCR, [C/R] = 103 bytes
= 2 blank pixels
78h
20
Note
1
The remaining pixels on the right-hand side of the display are automatically blanked
by the S1D13700. There is no need to zero the display memory corresponding to
these pixels.
2
Assumes a frame frequency of 70 Hz, 1 bpp, and a clock divide of 4.
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15.1.2 Initialization Example
The initialization example shown below is for a S1D13700 with an 8-bit microprocessor
interface bus and an Epson EG4810S-AR display unit (512 × 128 pixels).
Indirect Addressing
Start
Clear first
memory layer
Supply on
Clear second
memory layer
SYSTEM SET
CSRW
SCROLL
CSR FORM
HDOT SCR
DISP ON
OVLAY
Output display
data
DISP OFF
Figure 15-1 Initialization Procedure
Note
Set the cursor address to the start of each screen’s layer memory, and use MWRITE to
fill the memory with space characters, 20h (text screen only) or 00h (graphics screen
only). Determining which memory to clear is explained in Section 15.1.3, “Display
Mode Setting Example 1: Combining Text and Graphics” on page 110.
Table 15-2 Indirect Addressing Initialization Procedure
No.
Command
1
Power-up
2
Supply
3
SYSTEM SET
Operation
C = 40h
P1 = 38h
M0: Internal CGROM (REG[00h] bit 0)
M2: 8 lines per character (REG[00h] bit 2)
W/S: Two-panel drive (REG[00h] bit 3)
IV: Sets top-line compensation to none (REG[00h] bit 5)
P2 = 87h
FX: Horizontal character size = 8 pixels (REG[01h] bits 3-0)
MOD: Two-frame AC drive (REG[01h] bit 7)
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Table 15-2 Indirect Addressing Initialization Procedure (Continued)
No.
Command
Operation
P3 = 07h
FY: Vertical character size = 8 pixels (REG[02h] bits 3-0
P4 = 3Fh
C/R: 64 display addresses per line (REG[03h] bits 7-0)
P5 = 49h
TC/R: Total address range per line = 90 (REG[04h] bits 7-0)
fOSC = 6.5 MHz, fFR = 70 Hz
P6 = 7Fh
L/F: 128 display lines (REG[05h] bits 7-0
P7 = 80h
AP: Virtual screen horizontal size is 128 addresses (REG[06h] bits 7-0, REG[07h]
bits 7-0)
P8 = 00h
4
SCROLL
C = 44h
P1 = 00h
First screen block start address (REG[0Bh] bits 7-0, REG[0Ch] bits 7-0)
P2 = 00h
Set to 0000h
P3 = 40h
Display lines in first screen block = 64 (REG[0Dh] bits 7-0)
P4 = 00h
Second screen block start address (REG[0Eh] bits 7-0, REG[0Fh] bits 7-0)
P5 = 10h
Set to 1000h
P6 = 40h
Display lines in second screen block = 64 (REG[10h] bits 7-0)
P7 = 00h
Third screen block start address (REG[11h] bits 7-0, REG[12h] bits 7-0)
P8 = 04h
Set to 0400h
P9 = 00h
Fourth screen block start address (REG[13h] bits 7-0, REG[14h] bits 7-0)
P10 = 30h
Set to 3000h
Display memory
(SAD1) 0000h
(SAD3) 0400h
0800h
1st display memory page
2nd display memory page
(SAD2) 1000h
3rd display memory page
(SAD4) 3000h
4th display memory page
5000h
5
HDOT SCR
C = 5Ah
P1 = 00h
6
Set horizontal pixel shift to zero (REG[1Bh] bits 2-0)
OVLAY
C = 5Bh
P1 = 01h
MX 1, MX 0: Inverse video superposition (REG[18h] bits 1-0)
DM 1: First screen block is text mode (REG[18h] bit 2)
DM 2: Third screen block is text mode (REG[18h] bit 3)
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Table 15-2 Indirect Addressing Initialization Procedure (Continued)
No.
Command
7
DISP ON/OFF
Operation
C = 58h
D: Display OFF (REG[09h] bit 0)
P1 = 56h
FC1, FC0: Flash cursor at 2 Hz (REG[0Ah] bits 1-0)
FP1, FP0:
First screen block ON (REG[0Ah] bits 3-2)
FP3, FP2:
Second and fourth screen blocks ON (REG[0Ah] bits 5-4)
FP5, FP4:
Third screen block ON (REG[0Ah] bits 7-6)
8
Clear data in first layer Fill first screen layer memory with 20h (space character)
9
Clear data in second Fill second screen layer memory with 00h (blank data)
layer
Display
Character code in every position
1st layer
Blank code in every position
2nd layer
10
CSRW
C = 46h
P1 = 00h
Set cursor to start of first screen block (REG[1Ch] bits 7-0, REG[1Dh] bits 7-0)
P2 = 00h
11
CSR FORM
C = 5Dh
P1 = 04h
CRX: Horizontal cursor size = 5 pixels (REG[15h] bits 3-0)
P2 = 86h
CRY: Vertical cursor size = 7 pixels (REG[16h] bits 3-0)
CM: Block cursor (REG[16h] bit 7)
12
DISP ON/OFF
C = 59h
Display ON
Display
13
CSR DIR
C = 4Ch
14
Set cursor shift direction to right (REG[17h] bits 1-0)
MWRITE
C = 42h
P1 = 20h
‘’
P2 = 45h
‘E’
P3 = 50h
‘P’
P4 = 53h
‘S’
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Table 15-2 Indirect Addressing Initialization Procedure (Continued)
No.
Command
Operation
P5 = 4Fh
‘O’
P6 = 4Eh
‘N’
EPSON
15
CSRW
C = 46h
P1 = 00h
Set cursor to start of second screen block (REG[1Ch] bits 7-0, REG[1Dh] bits 7-0)
P2 = 10h
16
CSR DIR
C = 4Fh
17
Set cursor shift direction to down (REG[17h] bits 1-0)
MWRITE
C = 42h
P1 = FFh
Fill in a square to the left of the ‘E’
↓
P9 = FFh
EPSON
18
CSRW
C = 46h
P1 = 01h
Set cursor address to 1001h (REG[1Ch] bits 7-0, REG[1Dh] bits 7-0)
P2 = 10h
19
MWRITE
C = 42h
P1 = FFh
Fill in the second screen block in the second column of line 1
↓
P9 = FFh
20
CSRW
Repeat operations 18 and 19 to fill in the background under ‘EPSON’
(REG[1Ch] bits 7-0, REG[1Dh] bits 7-0)
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Table 15-2 Indirect Addressing Initialization Procedure (Continued)
No.
Command
Operation
Inverse display
EPSON
↓
29
MWRITE
30
CSRW
C = 46h
P1 = 00h
Set cursor to line three of the first screen block
(REG[1Ch] bits 7-0, REG[1Dh] bits 7-0)
P2 = 01h
31
CSR DIR
C = 4Ch
32
Set cursor shift direction to right (REG[17h] bits 1-0)
MWRITE
C = 42h
P1 = 44h
‘D’
P2 = 6Fh
‘o’
P3 = 74h
‘t’
P4 = 20h
‘’
P5 = 4Dh
‘M’
P6 = 61h
‘a’
P7 = 74h
‘t’
P8 = 72h
‘r’
P9 = 69h
‘i’
P10 = 78h
‘x’
P11 = 20h
‘’
P12 = 4Ch
‘L’
P13 = 43h
‘C’
P14 = 44h
‘D’
Inverse display
EPSON
Dot matrix LCD
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15.1.3 Display Mode Setting Example 1: Combining Text and Graphics
Conditions
• 320 × 200 pixels, single panel drive (1/200 duty cycle)
• First layer: text display
• Second layer: graphics display
• 8 × 8-pixel character font
• CGRAM not required
Display memory allocation
• First layer (text): 320 ÷ 8 = 40 characters per line, 200 ÷ 8 = 25 lines. Required memory
size = 40 × 25 = 1000 bytes.
• Second layer (graphics): 320 ÷ 8 = 40 characters per line, 200 ÷ 1 = 200 lines. Required
memory size = 40 × 200 = 8000 bytes.
03E8h
2nd graphics layer
(8000 bytes)
0000h
1st character layer
(1000 bytes)
2327h
03E7h
Figure 15-2 Character Over Graphics Layers
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Register Setup Procedure
SYSTEM SET
TC/R calculation
C = 40h
P1 = 30h
fOSC = 6 MHz (refer to Section 15.1.1, “SYSTEM SET
Command and Parameters” on page 103)
P2 = 87h
fFR = 70 Hz (refer to Section 15.1.1, “SYSTEM SET
Command and Parameters” on page 103)
P3 = 07h
P4 = 27h
P5 = 34h
[TC/R] = 52, so TC/R = 34h
P6 = C7h
P7 = 28h
P8 = 00h
SCROLL
C = 44h
P1 = 00h
P2 = 00h
P3 = C8h
P4 = E8h
P5 = 03h
P6 = C8h
P7 = Xh
P8 = Xh
P9 = Xh
P10 = Xh
CSRFORM
C = 5Dh
P1 = 04h
P2 = 86h
HDOT SCR
C = 5Ah
P1 = 00h
OVLAY
C = 5Bh
P1 = 00h
DISP ON/OFF
C = 59h
P1 = 16h
X = Don’t care
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15.1.4 Display Mode Setting Example 2: Combining Graphics and Graphics
Conditions
• 320 × 200 pixels, single-panel drive (1/200 duty cycle)
• First layer: graphics display
• Second layer: graphics display
Display memory allocation
• First layer (graphics): 320 ÷ 8 = 40 characters per line, 200 ÷ 1 = 200 lines. Required
memory size = 40 × 200 = 8000 bytes.
• Second layer (graphics): 320 ÷ 8 = 40 characters per line, 200 ÷ 1 = 200 lines. Required
memory size = 8000 bytes.
1F40h
2nd graphics layer
(8000 bytes)
0000h
1st graphics layer
(8000 bytes)
3E7Fh
1F3Fh
Figure 15-3 Two-Layer Graphics
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Register setup procedure
SYSTEM SET
TC/R calculation
C = 40h
P1 = 30h
fOSC = 6 MHz (refer to Section 15.1.1, “SYSTEM SET
Command and Parameters” on page 103)
P2 = 87h
fFR = 70 Hz (refer to Section 15.1.1, “SYSTEM SET
Command and Parameters” on page 103)
P3 = 07h
P4 = 27h
P5 = 34h
[TC/R] = 52, so TC/R = 34h
P6 = C7h
P7 = 28h
P8 = 00h
SCROLL
C = 44h
P1 = 00h
P2 = 00h
P3 = C8h
P4 = 40h
P5 = 1Fh
P6 = C8h
P7 = Xh
P8 = Xh
P9 = Xh
P10 = Xh
CSRFORM
C = 5Dh
P1 = 07h
P2 = 87h
HDOT SCR
C = 5Ah
P1 = 00h
OVLAY
C = 5Bh
P1 = 0Ch
DISP ON/OFF
C = 59h
P1 = 16h
X = Don’t care
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15.1.5 Display Mode Setting Example 3: Combining Three Graphics Layers
Conditions
• 320 × 200 pixels, single-panel drive (1/200 duty cycle)
• First layer: graphics display
• Second layer: graphics display
• Third layer: graphics display
Display memory allocation
• All layers (graphics): 320 ÷ 8 = 40 characters per line, 200 ÷ 1 = 200 lines. Required
memory size = 40 × 200 = 8000 bytes.
3E80h
3rd graphics layer
(8000 bytes)
1F40h
2nd graphics layer
(8000 bytes)
0000h
1st graphics layer
(8000 bytes)
5DBFh
3E7Fh
1F3Fh
Figure 15-4 Three-Layer Graphics
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Register setup procedure
SYSTEM SET
TC/R calculation
C = 40h
P1 = 30h
fOSC = 6 MHz (refer to Section 15.1.1, “SYSTEM SET
Command and Parameters” on page 103)
P2 = 87h
fFR = 70 Hz (refer to Section 15.1.1, “SYSTEM SET
Command and Parameters” on page 103)
P3 = 07h
P4 = 27h
P5 = 34h
[TC/R] = 52, so TC/R = 34h
P6 = C7h
P7 = 28h
P8 = 00h
SCROLL
C = 44h
P1 = 00h
P2 = 00h
P3 = C8h
P4 = 40h
P5 = 1Fh
P6 = C8h
P7 = 80h
P8 = 3Eh
P9 = Xh
P10 = Xh
CSR FORM
C = 5Dh
P1 = 07h
P2 = 87h
HDOT SCR
C = 5Ah
P1 = 00h
OVLAY
C = 5Bh
P1 = 1Ch
DISP ON/OFF
C = 59h
P1 = 16h
X = Don’t care
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15.2 System Overview
Section 3, “System Diagrams” on page 14 shows some typical S1D13700 implementations
where the microprocessor issues instructions to the S1D13700, and the S1D13700 drives
the LCD panel. Since the S1D13700 integrates all required LCD control circuits, minimal
external components are required to construct a complete medium- resolution liquid crystal
display solution.
15.3 Smooth Horizontal Scrolling
The S1D13700 supports smooth horizontal scrolling to the left as shown in Figure 15-5
“HDOT SCR Example,” on page 117. When scrolling left, the screen is effectively moving
to the right over the larger virtual screen.
Instead of changing the screen block start address (SADx) and shifting the display by eight
pixels, smooth scrolling is achieved by repeatedly changing the horizontal pixel scroll
parameter of the HDOT SCR command (REG[1Bh] bits 2-0). When the display has been
scrolled seven pixels, the horizontal pixel scroll parameter is reset to zero and screen block
start address is incremented by one. Repeating this operation at a suitable rate gives the
appearance of smooth scrolling.
Note
To scroll the display to the right, the procedure is reversed.
When the edge of the virtual screen is reached, the microprocessor must take appropriate
steps to avoid corrupting the display. For example, scrolling must be stopped or the display
must be modified.
Note
The HDOT SCR command cannot be used to scroll individual layers.
Note
When in 2 bpp or 4 bpp mode, smooth horizontal scrolling in pixel units is not supported.
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HDOT SCR
parameter
Page 117
SAD
SAD + 1
P1 = 00h
SAD + 2
Magnified
AP
P1 = 01h
SAD = SAD
P1 = 02h
Display
C/R
P1 = 03h
Virtual screen
P1 = 07h
P1 = 00h
SAD = SAD + 1
Not visible
Visible
Where:
AP = horizontal address range (REG[06h] bits 7-0, REG[07h] bits 7-0)
C/R = character bytes per row (REG[03h] bits 7-0)
Figure 15-5 HDOT SCR Example
Note
The response time of LCD panels changes considerably at low temperatures. Smooth
scrolling under these conditions may make the display difficult to read.
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15.4 Layered Display Attributes
S1D13700 incorporates a number of functions for enhancing displays using monochrome
LCD panels. It allows the display of inverse characters, half-intensity menu pads and
flashing of selected screen areas. These functions are controlled by REG[18h] Overlay
Register and REG[0Ah] Display Attribute Register.
MX0
Combined Layer
Display
Attribute
MX1
Reverse
0
1
IV
EPSON
IV
EPSON
Half-tone
0
0
ME
Yes, No
ME
Yes, No
0
0
0
1
BL
Error
BL
0
0
0
1
Local flashing
Ruled line
LINE
RL
1st Layer Display
RL
LINE
2nd Layer Display
Error
LINE
LINE
Figure 15-6 Layer Synthesis
These effects can be achieved in different ways, depending on the display configuration.
The following sections describe these functions.
Note
Not all functions can be used in one layer at the same time.
15.4.1 Inverse Display
For inverse display where the first layer is text and the second layer is graphics.
1. CSRW, CSRDIR, MWRITE
Write to the graphics screen at the area to be inverted.
2. OVLAY: MX0 = 1, MX1 = 0 (REG[18h] bits 1-0)
Set the layer compensation method of the two layers to Exclusive-OR.
3. DISP ON/OFF: FP0 = 1, FP1 = 0, FP2 = 1, FP3 = 0.
Turn on layers 1 and 2 with no flashing.
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15.4.2 Half-Tone Display
The FP parameter (display attributes) can be used to generate a half-intensity display by
flashing the display at 17Hz. Note that this mode may cause flicker problems with certain
LCD panels.
Menu Pad Display
Turn flashing off for the first layer, on at 17 Hz for the second layer, and combine the
screens using the OR function.
1. REG[18h] Overlay Register = 00h
2. REG[0Ah] Display Attribute Register = 34h
SAD1
Half-tone
SAD2
AB
AB
+
1st layer
2nd layer
Combined layer display
Figure 15-7 Half-Tone Character And Graphics
Graph Display
To display two overlaid graphs on the screen, configure the display in the same manner as
for menu pad display and put one graph on each screen layer. The difference in contrast
between the half and full intensity displays make it easy to distinguish between the two
graphs and create an attractive display.
1. REG[18h] Overlay Register = 00h
2. REG[0Ah] Display Attribute Register = 34h
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15.4.3 Flash Attribute
Small Area
To flash selected characters, the MPU can alternately write the characters as character
codes and blank characters at intervals of 0.5 to 1.0 seconds.
Large Area
Divide both layer 1 and layer 2 into two screen blocks each, layer 2 being divided into the
area to be flashed and the remainder of the screen. Flash the layer 2 screen block at 2 Hz
for the area to be flashed and combine the layers using the OR function.
ABC
ABC
XYZ
XYZ
Figure 15-8 Flash Attribute for a Large Area
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15.5 16 × 16-Dot Graphic Display
15.5.1 Command Usage
To display 16 × 16 pixel characters, use the following procedure.
1. Set the cursor address, REG[1Ch] - REG[1Dh]
2. Set the cursor shift direction, REG[17h] bits 1-0
3. Write to the display memory
15.5.2 Kanji Character Display
To write large characters, use the following procedure. For further information, see the
flowchart in Figure 15-9 “Graphics Address Indexing,” on page 122.
1. Reads the character data from the CGRAM
2. Set the display address
3. Writes to the display memory
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0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
A0 = 0
A0 = 1
O8 O7 O6 O5 O4 O3 O2 O1
(1)
(3)
(5)
(7)
(9)
(11)
(13)
(15)
(17)
(19)
(21)
(23)
(25)
(27)
(29)
(31)
O8 O7 O6 O5 O4 O3 O2 O1
(2)
(4)
(6)
(8)
(10)
(12)
(14)
(16)
(18)
(20)
(22)
(24)
(26)
(28)
(30)
(32)
1st column
2nd column
CGROM output
(n) shows the CG data
readout order
(Kanji pattern)
Scan address A1 to A4
(6)
(4)
(2)
(19)
(17)
(15)
(13)
(11)
(9)
(7)
(5)
(3)
(1)
Data held in the microprocessor memory
2nd column
memory area
(4)
(2)
1st column
memory area
(3)
(1)
Data written into the S1D13700 display memory
Figure 15-9 Graphics Address Indexing
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320 dots
Direction of cursor movement
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
(31)
(32)
240 dots
Figure 15-10 Graphics Bit Map
Using an external character generator RAM an 8 × 16 pixel font can be used, which allows
a 16 × 16 pixel character to be displayed in two segments. The CGRAM data format is
described in Figure 13 “Character Generator,” on page 97. This allows the display of up to
128, 16 × 16 pixel characters. If CGRAM is also used, 96 fixed characters and 32 bankswitchable characters are also be supported.
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For Direct Addressing Mode
Start
Enable cursor downwards movement
Set column 1 cursor address
Write data
Set column 2 cursor address
Write data
End
For Indirect Addressing Mode
Start
Enable cursor downwards movement
Set column 1 cursor address
Write data
Set column 2 cursor address
Write data
End
Figure 15-11 16 × 16-Dot Display Flowchart
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16 Internal Character Generator Font
0
1
2
3
4
Character code bits 0 to 3
5
6
7
8
9
A
B
C
D
E
F
2
3
Character code bits 4 to 7
4
5
6
7
A
B
C
D
1
Figure 16-1 On-Chip Character Set
Note
The shaded positions indicate characters that have the whole 6 × 8 bitmap blackened.
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17 Power Save Mode
The S1D13700 supports a power save mode that places it into a power efficient state. Power
save mode is controlled by the Power Save Mode Enable bit, REG[08h] bit 0. The
S1D13700 enters power save mode at least one blank frame after the enable bit is set.
When power save mode is enabled, blank data is sent to the X-drivers, and the Y-drivers
have their bias supplies turned off by the YDIS signal. Using the YDIS signal to disable the
Y-drivers guards against any spurious displays. The internal registers of the S1D13700
maintain their values during the power save state and the display memory control pins
maintain their logic levels to ensure that the display memory is not corrupted.
The S1D13700 is removed from power save mode by writing a 0 the Power Save Mode
Enable bit, REG[08h] bit 0. However, after disabling power save mode, one dummy write
to any register must be performed for direct addressing mode, and at least two dummy
writes must be performed for indirect addressing mode.
For indirect addressing mode, the POWER SAVE command has no parameter bytes. For
indirect addressing mode, the SYSTEM SET command exits power save mode.
1. The YDIS signal goes LOW between one and two frames after the power save command is received. Since YDIS forces all display driver outputs to go to the deselected
output voltage, YDIS can be used as a power down signal for the LCD unit. This can
be done by having YDIS turn off the relatively high power LCD drive supplies at the
same time as it blanks the display.
2. Since all internal clocks in the S1D13700 are halted while power save mode is enabled, a DC voltage is applied to the LCD panel if the LCD drive supplies remain on.
If reliability is a prime consideration, turn off the LCD drive supplies before issuing
the power save command.
3. The bus lines become high impedance when power save mode is enabled. If the bus is
required to be a known state, pull-up or pull-down resistors can be used.
Table 17-1 State of LCD Pins During Power Save Mode
LCD Pin
State During Display Off
State During Power Save Mode
YDIS
Low
Low
FPFRAME
Low
Low
YSCL
High
High
MOD
Low
Low
FPLINE
Low
Low
XECL
Low
Low
FPSHIFT
Low
Low
FPDAT[3:0]
Low
Low
WAIT#
Hi-Z
Hi-Z
DB[7:0]
Hi-Z
Hi-Z
XCD1
High
High
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18 Mechanical Data
All dimensions in mm
12±0.4
10.2±0.1
33
32
64
17
10.2±0.1
49
0.5
0.2±0.03
16
1.0±0.1
1
12±0.4
48
1.2max
0° to 10°
0.15±0.05
0.5±0.2
0.1
1.0
Figure 18-1 Mechanical Drawing TQFP13 - 64 pin
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19 References
The following documents contain additional information related to the S1D13700.
Document numbers are listed in parenthesis after the document name. All documents can
be found at the Epson Research and Development Website at www.erd.epson.com.
20 Technical Support
Japan
Seiko Epson Corporation
Electronic Devices Marketing Division
421-8, Hino, Hino-shi
Tokyo 191-8501, Japan
Tel: 042-587-5812
Fax: 042-587-5564
http://www.epson.co.jp/
Hong Kong
Epson Hong Kong Ltd.
20/F., Harbour Centre
25 Harbour Road
Wanchai, Hong Kong
Tel: 2585-4600
Fax: 2827-4346
http://www.epson.com.hk/
North America
Epson Electronics America, Inc.
150 River Oaks Parkway
San Jose, CA 95134, USA
Tel: (408) 922-0200
Fax: (408) 922-0238
http://www.eea.epson.com/
Taiwan
Epson Taiwan Technology
& Trading Ltd.
10F, No. 287
Nanking East Road
Sec. 3, Taipei, Taiwan
Tel: 02-2717-7360
Fax: 02-2712-9164
http://www.epson.com.tw/
Europe
Epson Europe Electronics GmbH
Riesstrasse 15
80992 Munich, Germany
Tel: 089-14005-0
Fax: 089-14005-110
http://www.epson-electronics.de/
Singapore
Epson Singapore Pte., Ltd.
No. 1
Temasek Avenue #36-00
Millenia Tower
Singapore, 039192
Tel: 337-7911
Fax: 334-2716
http://www.epson.com.sg/
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Hardware Functional Specification
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Change Record
X42A-A-001-01
Revision 1.0
• released as revision 1.0
X42A-A-001-00
Revision 0.07
• section 5.2, updated reset state to “Z” for CNF[4:0], A[15:0], RD#, WR#, CS#, AS#,
RESET#, XCG1, and CLKI
• table 5-7, updated host pin mapping for generic direct/indirect, AS# should be
connected to HIOVDD
• table 6-5, in DC Characteristics for VOH/VOL: cell type changed from “CS2” to “CB2”
• table 7-8, in LCD AC Timing, t6 min and max for both 3.3 and 5.0 volts changed to 0ns
for min and 4ns for max
• REG[16h] bit 7, fixed block style cursor example
• table 15-1, for 256x64 [TC/R] should be 24h and for 256x128 [TC/R] should be 16h
X42A-A-001-00
Revision 0.06
• section 1.2, clarified character generator options
• section 2.5, clarified character generator options
• section 2.7, changed input clock max to 60MHz and pixel clock max to 15MHz
• section 2.7, changed max pixel clock to max FPSHIFT clock
• section 2.8, added lead free package
• figures 3-1, 3-2, 3-5, corrected AS# signal to be pulled up to VDD
• figures 3-3 and 3-4, updated system diagrams for MC68K implementations to show
AS# ORed with CS#
• section 4, removed TESTEN from the diagram and XCG1/XCD1 no longer are shown
connecting to the Host
• section 5.2.1,
• changed A[15:1], A0, D[7:0] RESET# state to "0 or Z"
• changed CNF[4:0] RESET# state to "Z"
• changed WAIT# cell type to HTB2T
• changed RESET# reset state to "1"
• changed AS# to be pulled up to VDD for Generic and M6800 interfaces
• changed SCANEN pin description to be "...must be connected to ground..." instead
of "...must be left unconnected and floating..."
• section 5.2.3, changed XCG1 and XCD1 power to COREVDD
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• section 5.2.3, changed CLKI power to HIOVDD
• section 5.4, changed WAIT# pin mapping to WAIT#/DTACK# or unconnected for indirect interfaces
• table 6-2, changed NIOVin max to NIOVDD instead of HIOVDD
• table 6-3, changed Voh min to VDD-0.4 instead of HIOVDD-0.4
• table 6-4, removed Vih2/Vil2 and renamed Vih1/Vil1 to Vih/Vil, also renamed Vh1 to
Vh
• table 6-5, added new tables that references the cell types associated with each electrical
characteristic
• section 7, added note about pin capacitance
• section 7.2, changed RES to RESET#
• section 7.3, updated CPU Interface timing to Generic Direct/Indirect with/without
WAIT# and MC68K Direct/Indirect with/without WAIT#
• section 7.3.1, for t11/t12 changed "...WAIT# is/is not asserted..." to "...WAIT# is/is not
used..."
• section 7.3.3, for t11/t12 changed "...WAIT# is/is not asserted..." to "...WAIT# is/is not
used..."
• section 7.4, updated Power Save Mode/Display Enable Timng parameters and values
• section 7.5, updated LCD timing diagrams and added 2 new parameters
• section 8, removed the CGROM area from the memory map
• section 9.1, updated clock diagram, added CLKI/OSC logic
• section 9.2, added descriptions for system clock and FPSHIFT clock
• REG[00h] bit 4, changed bit to “reserved with a default of 1”
• REG[00h] bit 3, removed diagram for left and right dual panel display
• REG[00h] bit 3, updated note about adjusting SL to compensate for the shift in characters
• REG[00h] bit 0, updated Character Generator Select bit to mention that if the CGROM
is used, the CGRAM can only support up to 64 8x8 characters
• REG[02h], removed comment about setting to 00h when graphics mode is enabled
• REG[03h], updated bit description and added reference to C/R formulas
• REG[04h], updated bit description and added reference to TC/R formulas
• REG[0Ah] bits 1-0, changed frequency of option 10 to "...(approx 2Hz)..."
• REG[0Ah] bits 7-2, seperated the Display Attribute bits for each address block
• REG[17h], clarified the possible movement for the Cursor Shift Direction bits
• REG[18h] bit 4, changed bit name from "Overlay Select" to "3 Layer Overlay Select"
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Hardware Functional Specification
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• REG[18h] bits 3-2, split these bits into individual display mode bits for screen block 3
and 1
• REG[1Bh], changed wording of Horizontal Pixel Scroll bit description
• REG[1Ch]-[1Dh], updated the bit description for the CSRW bits
• REG[1Eh]-[1Fh], updated bit description
• section 11, changed number of bytes for DISP ON/OFF from 2 to 1
• section 11, changed Parameter Read from 101 to 110 and Parameter Write from 010 to
001
• section 11.1.1, moved fOSC formulas to section 15.1.1
• section 11.1.3, updated display on parameters and added display off parameters
• section 11.1.3, fixed display on/off parameters, display off is 01011000 and display on
is 01011001
• section 11.1.6, updated cursor direction parameters
• section 11.1.9, updated Hdot Scr parameters
• section 12.2.1, added “...in 1 bpp.”
• section 12.2.2, expanded note under figure 12-5 to describe all color depths
• figure 12-6, changed line notation between upper and lower panel to be clearer
• section 15.1.1, changed TC/R restriction to TC/R >= C/R + 2 instead of C/R + 4
• table 15-1, updated TC/R values in table and fosc values
• table 15-2, for P5 = 49h changed fOSC from 6.0MHz to 6.5MHz
• section 15.1.3, updated register setup procedure table
• section 15.1.4, updated register setup procedure table
• section 15.1.5, updated register setup procedure table
• figure 15-5 and 15-6, changed FPFRAMEIS to YDIS
• section 15.3, removed “system Interconnection” section as redundant
• section 15.4, removed the MX1=1, MX0=1 options from the diagram
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Revision 0.05
• section 5.2.1 and 5.2.2, confirmed RESET# states for all pins
• section 5.2, clarified pin descriptions and “standardized” them to normal 13xxx descriptions where possible
• section 5.3, removed all references regarding CNF pins being latched at the rising edge
of RESET#
• section 5.4, completed the host bus interface pin mapping table
• section 7.5, updated LCD timing table parameters t6,t7, and removed parameters t11
and t14
• REG[00h] bit 1, removed M1 bit and all references
• REG[01h], reworded the bit description for the FX bits
• REG[03h], added reference to section 11.1.2 and fOSC formula
• REG[08h], updated the power save mode enable bit and moved the extra information
about power save mode to section 19
• REG[09h], updated bit description for Display Enable bit and added cross reference to
LCD pin state table
• REG[0Ah] bits 5-0, clarified screen block attributes table
• REG[0Ah] bits 1-0, added note about writing and reading to/from memory while the
cursor is disabled
• REG[18h] bits 1-0, reserved the Priority-OR function
• section 11.1.2, added formulas for determining fOSC and Frame Rate
• section 17, added table listing the state of all LCD pins during Power Save mode as per
etr i42bl001
S1D13700
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Revision 0.04
• section 5.2, add RESET# State to all pins
• section 5.2.1 Host Interface - in table 5-1, description for pin A0, removed the 3 truth
tables for Generic, M6800 and MC68K
• section 6 D.C. Characteristics - change Topr “min = -40” and “max = 85”
• REG[00h] bit 0 - change second paragraph in description to read “... mapped at the CG
Start Address, REG[1Ah] and REG[19h]”
• REG[03h] - delete “The number of excess pixels must not exceed 64” from description
• REG[08h} bit 0 - add “Entering power save also clears the Display-On...” to bit description
• REG[08h} bit 0 - add “in Direct mode, performing one dummy...” to bit description
• REG[16h bits 3-0 - add “These bits must be set less than or equal to FY.” to bit description
• REG[17h] bits 1-0 - add indirect mode commands to table
• REG[19h], REG[1Ah] - delete note, rewrite description
• REG[1Ch], REG[1Dh] - mark registers as Write Only
• CSRR (REG[1E], REG[1Fh]) - delete text “These registers are used only in Indirect
Addressing mode”
• REG[1E], REG[1Fh] - mark registers as Read Only
• table 11-2 Indirect Addressing Command/Write/Read - change Parameter Read [P#] to
101b
• section 15.3.1 S1D13700 - in figures 15-5 and 15-6 correct the Crystal connections
•
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Revision 0.03
• section 5.3, revised summary of configuration options table
• section 6, updated 3.3V and 5.0V DC Characteristics
• section 7, changed Capacitance load to 30pF for Host and LCD
• section 7.1.1, changed input clock pwh and pwl to 0.4Tclki
• section 7.2, moved reset timing to this section
• section 7.3.1, updated Generic Bus Direct Timing diagram and table
• section 7.3.2, updated Generic Bus Indirect Timing diagram and table
• section 7.3.3, updated MC68K Bus Direct Timing diagram and table
• section 7.3.4, updated MC68K Bus Indirect Timing diagram and table
• section 7.4, updated power save enable/display enable timing
• section 7.5, updated display timings diagrams and table
• section 9, updated clock section with diagram and moved oscillator circuit to subsection
• section 15, updated Oscillator circuit diagram and added table
S1D13700
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Hardware Functional Specification
Issue Date: 2004/01/06
Revision 1.0