AMD AM29243EH

PRELIMINARY
Am29240EH, Am29245EH, and
Am29243EH
Enhanced High-Performance RISC Microcontrollers
5/2/97
DISTINCTIVE CHARACTERISTICS
Am29240EH Microcontroller
All three microcontrollers in the Am29240EH microcontroller series have the following characteristics:
The Am29240EH microcontroller has the following additional features:
Completely integrated system for embedded
applications
2-Kbyte, two-way set-associative data cache
Full 32-bit architecture
4-Kbyte, two-way set-associative instruction
cache
4-Gbyte virtual address space, 304-Mbyte
physical space implemented
Glueless system interfaces with on-chip wait
state control
36 VAX MIPS (million instructions per second)
sustained at 25 MHz
Four banks of ROM, each separately
programmable for 8-, 16-, or 32-bit interface
Four banks of DRAM
Single-cycle ROM burst-mode and DRAM
page-mode access
DRAM timing is software-programmable for 3/1
or 2/1 initial/burst access cycles
Single-cycle 32-bit multiplier for faster integer
math; two-cycle Multiply Accumulate (MAC)
function
16-entry on-chip Memory Management Unit
(MMU) with one Translation Look-Aside Buffer
4-channel double-buffered DMA controller with
queued reload
Two serial ports (UARTs)
Bidirectional bit serializer/deserializer
20- and 25-MHz operating frequencies
Am29243EH Microcontroller
The Am29243EH data microcontroller is similar to the
Am29240EH microcontroller, without the video interface. It includes the following features:
2-Kbyte, two-way set-associative data cache
6-port peripheral interface adapter
Single-cycle 32-bit multiplier for faster integer
math; two-cycle MAC
16-line programmable I/O port
32-entry on-chip MMU with dual TLBs
Bidirectional parallel port controller
4-channel, double-buffered DMA controller with
queued reload
Interrupt controller
Fully pipelined integer unit
Three-address instruction architecture
192 general purpose registers
Traceable Cache technology instruction and
data cache tracing
IEEE Std 1149.1-1990 (JTAG) compliant
Standard Test Access Port and
Boundary Scan Architecture
Binary compatibility with all 29K family
microprocessors and microcontrollers
Two serial ports (UARTs)
20- and 25-MHz operating frequencies
DRAM parity
Am29245EH Microcontroller
The low-cost Am29245EH microcontroller is similar to
the Am29240EH microcontroller, without the data cache
and 32-bit multiplier. It includes the following features:
16-entry on-chip MMU with one TLB
Two-channel DMA controller
CMOS technology/TTL compatible
One serial port (UART)
208-pin Plastic Quad Flat Pack (PQFP) package
Bidirectional bit serializer/deserializer
3.3-V power supply with 5-V-tolerant I/O
16-MHz operating frequency
This document contains information on a product under development at Advanced Micro Devices, Inc. The information is intended
to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.
Publication #: 20068 Rev. A Amendment: /0
Issue Date: May 1997
PRELIMINARY
Am29240EH MICROCONTROLLER BLOCK DIAGRAM
Parallel Port
Control/Status
Lines
4
6
Serial
Data
Printer/Scanner
Video
ROM
Chip Selects
6
STAT
MEMCLK
4
JTAG
Clock/
Control
Lines
11
8
4 DREQ
4 DACK
GREQ/GACK/TDMA
Parallel Port
Controller
Am29000 CPU
4-Channel DMA
Controller
16
Dual
Serial Ports
Programmable
I/O Port
I/O
4K ICache
Serializer/
Deserializer
2K DCache
Interrupt
Controller
ROM
Controller
4
6
24
4/4
32
Instruction/Data
Bus
Address
Bus
PIA
Chip Selects
RAS/CAS
Timer/Counter
MMU
6
Interrupts, Traps
32x32 Multiply DRAM Controller
PIA
Controller
ROM
Space
Memory
5
DRAM
Peripherals
Am29245EH MICROCONTROLLER BLOCK DIAGRAM
Parallel Port
Control/Status
Lines
4
4
Serial
Data
Printer/Scanner
Video
ROM
Chip Selects
4
ROM
Space
Memory
6
STAT
MEMCLK
Parallel Port
Controller
Single
Serial Port
4
JTAG
5
Clock/
Control
Lines
8
7
2 DREQ
2 DACK
GREQ/GACK/TDMA
16
Am29000 CPU
2-Channel DMA
Controller
Programmable
I/O Port
I/O
4K ICache
Serializer/
Deserializer
Interrupt
Controller
ROM
Controller
DRAM Controller
PIA
Controller
MMU
6
PIA
Chip Selects
24
Address
Bus
Timer/Counter
32
Instruction/Data
Bus
Peripherals
2
Am29240 EH Microcontroller Series
6
Interrupts, Traps
RAS/CAS
4/4
DRAM
PRELIMINARY
Am29243EH MICROCONTROLLER BLOCK DIAGRAM
Parallel Port
Control/Status
Lines
5
6
Serial
Data
ROM
Chip Selects
6
STAT
MEMCLK
JTAG
Clock/
5 Control
Lines
8
11
4 DREQ
4 DACK
GREQ/GACK/TDMA
Parallel Port
Controller
4-Channel DMA
Controller
16
Am29000 CPU
Dual
Serial Ports
Programmable
I/O Port
I/O
4K ICache
2K DCache
Interrupt
Controller
ROM
Controller
4
4
MMU
Timer/Counter
32
ROM
Space
Memory
6
PIA
Chip Selects
Interrupts, Traps
32x32 Multiply DRAM Controller
PIA
Controller
24
Address
Bus
32
Instruction/Data
Bus
6
36
DRAM Parity
RAS/CAS
4/4
DRAM
Peripherals
CUSTOMER SERVICE
AMD’s customer service network includes U.S. offices,
international offices, and a customer training center. Expert technical assistance is available from AMD’s worldwide staff of field application engineers and support staff.
For answers to technical questions, AMD provides a
toll-free number for direct access to our corporate applications hotline. Also available is the AMD World Wide
Web home page and FTP site, which provides the latest
29K family product information.
Documentation and Literature
A simple phone call gets you free 29K family information such as data sheets, user’s manuals, application
notes, the Fusion29K Partner Solutions Catalog, and
other literature. Internationally, contact your local AMD
sales office for complete 29K family literature.
Literature Ordering
Corporate Applications Hotline
(800) 222-9323, option 3
(512) 602-5651
(800) 222-9323, option 2
(800) 222-9323, option 5
44-(0) 1276-803-299
Engineering Support
RELATED DOCUMENTS
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The Am29240EH, Am29245EH, and Am29243EH
RISC Microcontrollers User’s Manual (order #17741)
describes the technical features, programming interface, on-chip peripherals, register set, and instruction
set for the Am29240EH microcontroller series.
Programming the 29K RISC Family (order #19243) includes comprehensive information about the 29K family
for the software developer.
Am29240 EH Microcontroller Series
3
PRELIMINARY
GENERAL DESCRIPTION
Am29245EH Microcontroller
The Am29240EH microcontroller series is an enhanced
bus-compatible extension of the Am29200 RISC microcontroller family, with two to four times the performance. The Am29240EH microcontroller series
includes the Am29240EH microcontroller, the low-cost
Am29245EH microcontroller, and the Am29243EH data
microcontroller. The on-chip caches, MMU, faster integer math, and extended DMA addressing capability of
the Am29240EH microcontroller series allow the embedded systems designer to provide increasing levels of
performance and software compatibility throughout a
range of products (see Table 1 on page 6).
The low-cost Am29245EH microcontroller is designed
for embedded applications in which cost and space
constraints, along with increased performance requirements, are primary considerations.
Based on a low-voltage CMOS-technology design,
these devices offer a complete set of system peripherals
and interfaces commonly used in embedded applications. Compared to CISC processors, the Am29240EH
microcontroller series offers better performance, more
efficient use of low-cost memories, lower system cost,
and complete design flexibility for the designer. Coupled
with hardware and software development tools from the
AMD Fusion29K partners, the Am29240EH microcontroller series provides the embedded product designer
with the cost and performance edge required by today’s
marketplace.
For a complete description of the technical features, onchip peripherals, programming interface, register set,
and instruction set, please refer to the Am29240EH,
Am29245EH, and Am29243EH RISC Microcontrollers
User’s Manual (order #17741).
Am29240EH Microcontroller
The Am29245EH microcontroller also provides an easy
upgrade path for Am29200, Am29202, and
Am29205 microcontroller-based products.
Am29243EH Microcontroller
With DRAM parity support and a full MMU, the
Am29243EH data microcontroller is recommended for
communications applications that require high-speed
data movement and fast protocol processing in a faulttolerant environment.
Both the Am29243EH and Am29240EH microcontrollers support fly-by DMA at 100 Mbytes/s for LANs and
switching applications, and a two-cycle Multiply Accumulate function for DSP applications. The low power requirements make either microcontroller a good choice
for field-deployed devices.
Development Support Products
The Fusion29K Program of Partnerships for Application
Solutions provides the user with a vast array of products
designed to meet critical time-to-market needs. Products/solutions available from the AMD Fusion29K partners include the following:
Optimizing compilers for common high-level
languages
Assembler and utility packages
For general-purpose embedded applications, such as
mass-storage controllers, communications, digital signal processing, networking, industrial control, penbased systems, and multimedia, the Am29240EH
microcontroller provides a high-performance solution
with a low total-system cost. The memory interface of
the Am29240EH microcontroller provides even faster
direct memory access than the Am29200 microcontroller. This performance improvement minimizes the effect
of memory latency, allowing designers to use low-cost
memory with simpler memory designs. On-chip instruction and data caches provide even better performance
for time-critical code.
Source- and assembly-level software debuggers
Other on-chip functions include: a ROM controller,
DRAM controller, peripheral interface adapter controller, DMA controller, programmable I/O port, parallel port
controller, serial ports, and an interrupt controller.
Networking and communication solutions
4
Target-resident development monitors
Simulators
Execution boards
Hardware development tools
Silicon products
Board-level products
Laser-printer solutions
Multiuser, kernel, and real-time operating systems
Graphics solutions
Manufacturing support
Custom software consulting, support, and training
Am29240 EH Microcontroller Series
PRELIMINARY
ORDERING INFORMATION
Standard Products
AMDr standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the elements below.
Am29240EH
–25
K
C
\W
PROCESSING
\W = Trimmed and Formed
TEMPERATURE RANGE
C = Commercial (TC = 0°C to +85°C)
PACKAGE TYPE
K = 208-Lead Plastic Quad Flat Pack (PQR 208)
SPEED OPTION
–25 = 25 MHz
–20 = 20 MHz
–16 = 16 MHz
DEVICE NUMBER/DESCRIPTION
Am29240EH Enhanced RISC Microcontroller
Am29245EH Enhanced RISC Microcontroller
Am29243EH Enhanced RISC Data Microcontroller
Valid Combinations
Valid Combinations
Am29240EH–20
Am29240EH–25
KC\W
Am29243EH–20
Am29243EH–25
KC\W
Am29245EH–16
KC\W
Valid Combinations lists configurations
planned to be supported in volume. Consult
the local AMD sales office to confirm
availability of specific valid combinations, to
check on newly released combinations, and
to obtain additional data on AMD standard
military grade products.
RELATED AMD PRODUCTS
29K Family Devices
Product
Description
Am29000R
32-bit RISC microprocessor
Am29005
Low-cost 32-bit RISC microprocessor with no MMU and no branch target cache
Am29030
32-bit RISC microprocessor with 8-Kbyte instruction cache
Am29035
32-bit RISC microprocessor with 4-Kbyte instruction cache
Am29040
32-bit RISC microprocessor with 8-Kbyte instruction cache and 4-Kbyte data cache
Am29050
32-bit RISC microprocessor with on-chip floating point
Am29200
32-bit RISC microcontroller
Am29202
Low-cost 32-bit RISC microcontroller with IEEE-1284-compliant parallel interface
Am29205
Low-cost 32-bit RISC microcontroller
Am29240 EH Microcontroller Series
5
PRELIMINARY
Table 1. Product Comparison—Am29200 Microcontroller Family
Am29205
Controller
Am29202
Controller
Am29200
Controller
Am29245EH
Controller
Am29240EH
Controller
Am29243EH
Controller
Instruction Cache
—
—
—
4 Kbytes
4 Kbytes
4 Kbytes
Data Cache
—
—
—
—
2 Kbytes
2 Kbytes
Cache Associativity
—
—
—
2-way
2-way
2-way
Software
Software
Software
Software
32 x 32-bit
32 x 32-bit
—
—
—
1 TLB
16 Entry
1 TLB
16 Entry
2 TLBs
32 Entry
32 bits
16 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
3
8, 16 bits
4 Mbytes
16 bits
Not Supported
4
8, 16, 32 bits
4 Mbytes
8, 16, 32 bits
Not Supported
4
8, 16, 32 bits
16 Mbytes
8, 16, 32 bits
Supported
4
8, 16, 32 bits
16 Mbytes
8, 16, 32 bits
Supported
4
8, 16, 32 bits
16 Mbytes
8, 16, 32 bits
Supported
4
8, 16, 32 bits
16 Mbytes
8, 16, 32 bits
Supported
4
16 bits only
—
8 Mbytes/bank
Not Supported
4
16, 32 bits
16 Mbytes/bank
8 Mbytes/bank
Not Supported
4
16, 32 bits
16 Mbytes/bank
8 Mbytes/bank
Supported
4
32 bits
16 Mbytes/bank
Not supported
Supported
4
32 bits
16 Mbytes/bank
Not supported
Supported
4
32 bits
16 Mbytes/bank
Not supported
Not Supported
3/2
No
3/2
No
3/2
No
2/1 or 3/1
No
2/1 or 3/1
No
2/1 or 3/1
Yes
8, 16 bits
2
1
No
No
No
8, 16, 32 bits
2
1
No
No
No
8, 16, 32 bits
2
2
Yes
No
Yes
8, 16, 32 bits
2
2
Yes
Yes
Yes
8, 16, 32 bits
4
4
Yes
Yes
Yes
8, 16, 32 bits
4
4
Yes
Yes
Yes
No
No
No
Yes
Yes
Yes
2
8, 16 bits
3
2
8, 16, 32 bits
3
6
8, 16, 32 bits
3
6
8, 16, 32 bits
1
6
8, 16, 32 bits
1
6
8, 16, 32 bits
1
8
12
16
16
16
16
8
8
8
8
8
8
1 Port
PIO signals
1 Port
PIO signals
1 Port
Supported
1 Port
Supported
2 Ports
1 Port Supported
2 Ports
1 Port Supported
2
2
4
4
4
4
0
0
3
3
3
3
Parallel Port Controller
32-Bit Transfer
IEEE-1284 Interface
Yes
No
No
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
No
Yes
Yes
No
Yes
Yes
No
JTAG Debug Support
No
Yes
Yes
Yes
Yes
Yes
Serializer/Deserializer
Yes
Yes
Yes
Yes
Yes
No
100 PQFP
132 PQFP
168 PQFP
208 PQFP
208 PQFP
208 PQFP
5V
5V
5V
5V
5V
5V
3.3 V
5V
3.3 V
5V
3.3 V
5V
12, 16 MHz
12, 16, 20 MHz
16, 20 MHz
16 MHz
20, 25 MHz
20, 25 MHz
FEATURE
Integer Multiplier
Memory Management
Unit (MMU)
Data Bus Width
Internal
External
ROM Interface
Banks
Width
ROM Size (Max/Bank)
Boot-Up ROM Width
Burst-Mode Access
DRAM Interface
Banks
Width
Size: 32-Bit Mode
Size: 16-Bit Mode
Video DRAM
Access Cycles
Initial/Burst
DRAM Parity
On-Chip DMA
Width (ext. peripherals)
Total Number of Channels
Externally Controlled
External Master Access
External Master Burst
External Terminate Signal
Low-Voltage Operation
Peripheral Interface
Adapter (PIA)
PIA Ports
Data Width
Min. Cycles Access
Programmable I/O Port
(PIO)
Signals
Signals programmable
for interrupt generation
Serial Ports
Ports
DSR/DTR
Interrupt Controller
External Interrupt Pins
External Trap and Warn
Pins
Pin Count and Package
Operating Voltage
VCC
I/O Tolerance
Processor Clock Rate
6
Am29240 EH Microcontroller Series
PRELIMINARY
KEY FEATURES AND BENEFITS
Complete Set of Common Peripherals
The Am29240EH microcontroller series extends the line
of RISC microcontrollers based on 29K family architecture, providing performance upgrades to the Am29205
and Am29200 microcontrollers. The RISC microcontroller product line allows users to benefit from the very high
performance of the 29K family architecture, while also
capitalizing on the very low system cost made possible
by integrating processor and peripherals.
The Am29240EH microcontroller series minimizes system cost by incorporating a complete set of system facilities commonly found in embedded applications,
eliminating the cost of additional components. The onchip functions include: a ROM controller, a DRAM controller, a peripheral interface adapter, a DMA controller,
a programmable I/O port, a parallel port, up to two serial
ports, and an interrupt controller. A video interface is
also included in the Am29240EH and Am29245EH microcontrollers for printer, scanner, and other imaging applications. These facilities allow many simple systems to
be built using only the Am29240EH microcontroller series, external ROM, and/or DRAM memory.
The Am29240EH microcontroller series expands the
price/performance range of systems that can be built
with the 29K family. The Am29240EH microcontroller
series is fully software compatible with the Am29000,
Am29005, Am29030, Am29035, Am29040, and
Am29050 microprocessors, as well as the Am29200
and Am29205 microcontrollers. It can be used in existing 29K family microcontroller applications without software modifications.
On-Chip Caches
The Am29240EH microcontroller series incorporates a
4-Kbyte, two-way instruction cache that supplies most
processor instructions without wait states at the processor frequency. For best performance, the instruction
cache supports critical-word-first reloading with fetchthrough, so that the processor receives the required
instruction and the pipeline restarts with minimum delay.
The instruction cache has a valid bit per word to minimize the reload overhead. All cache array elements are
visible to software for testing and preload.
The Am29240EH and Am29243EH microcontrollers incorporate a 2-Kbyte, two-way set-associative data
cache. The data cache appears in the execute stage of
the processor pipeline, so that loaded data is available
immediately to the next instruction. This provides the
maximum performance for loads without requiring load
scheduling. This minimizes the time the processor waits
on external data as well as minimizing the reload time.
The data cache uses a write-through policy with a twoentry write buffer. Byte, half-word, and word reads and
writes are supported. All cache array elements are visible to software for testing and preload.
Single-Cycle Multiplier
The Am29240EH and Am29243EH microcontrollers
incorporate a full combinatorial multiplier that accepts
two 32-bit input operands and produces a 32-bit result
in a single cycle. The multiplier can produce a 64-bit result in two cycles. The multiplier permits maximum performance without requiring instruction scheduling,
since the latency of the multiply is the same as the latency of other integer operations. High-performance
multiplication benefits imaging, signal processing, and
state modeling applications.
ROM Controller
The ROM controller supports four individual banks of
ROM or other static memory, each with its own timing
characteristics. Each ROM bank may be a different size
and may be either 8, 16, or 32 bits wide. The ROM banks
can appear as a contiguous memory area of up to 64
Mbytes in size. The ROM controller also supports byte,
half-word, and word writes to the ROM memory space
for devices such as flash EPROMs and SRAMs.
DRAM Controller
The DRAM controller supports four separate banks of
dynamic memory. Each bank may be a different size and
must be 32 bits wide. The DRAM banks can appear as a
contiguous memory area of up to 64 Mbytes in size. The
DRAM controller supports two- or three-cycle accesses
(programmable by software), with single-cycle pagemode and burst-mode accesses. Burst accesses are
supported at two initial, one burst, or three initial, one
burst.
Peripheral Interface Adapter
The Peripheral Interface Adapter (PIA) permits glueless
interfacing to as many as six external peripheral chips.
The PIA allows for additional system features implemented by external peripheral chips.
DMA Controller
The DMA controller provides up to four channels for
transferring data between the DRAM and internal or external peripherals.
Fly-by DMA transfers data directly between an external
peripheral and DRAM or ROM, permitting very high data
bandwidth. The peripheral must support the timing of
the memory (DRAM or ROM). The transfer occurs at the
rate of one 32-bit word per cycle, if DRAM page-mode
accesses or ROM burst-mode or single-cycle accesses
are enabled.
For page-mode DRAM, the TDMA signal is asserted on
the rising edge following the last access. For an initial
access, TDMA is asserted simultaneously with DACKx.
DMA wait states and peripheral wait states are ignored
Am29240 EH Microcontroller Series
7
PRELIMINARY
during fly-by transfers. A higher fly-by DMA transfer can
interrupt a lower fly-by transfer.
Refresh does not pre-empt a fly-by transfer. A DMA
transfer continues until either DREQx is deasserted, the
transfer is interrupted by a higher priority DMA, or the
Count Terminate Enable (CTE) bit is set. No refreshes
will occur until the fly-by transfer is completed, so fly-by
transfers must be less than one refresh interval in
length. The DREQx signal must be configured as levelsensitive in the DRAM Control Register.
Parity checking and generation cannot be performed
during a fly-by transfer. Note also that zero-wait-state
ROM cannot be used with fly-by DMA.
I/O Port
The I/O port permits direct access to 16 individually programmable external input/output signals. Eight of these
signals can be configured to cause interrupts.
Parallel Port
The parallel port implements a bidirectional IBM PCcompatible parallel interface to a host processor.
Serial Port
The serial port implements up to two full-duplex UARTs.
Serializer/Deserializer
The serializer/deserializer (video interface) on the
Am29240EH and Am29245EH microcontrollers permits
direct connection to a number of laser-marking engines,
video displays, or raster input devices such as scanners.
Interrupt Controller
The interrupt controller generates and reports the status
of interrupts caused by on-chip peripherals.
Wide Range of Price/Performance Points
To reduce design costs and time-to-market, the product
designer can use the Am29200 microcontroller family
and one basic system design as the foundation for an
entire product line. From this design, numerous implementations of the product at various levels of price and
performance may be derived with minimum time, effort,
and cost.
The Am29240EH RISC microcontroller series supports
this capability through various combinations of on-chip
caches, programmable memory widths, programmable
wait states, burst-mode and page-mode access support, bus compatibility, and 29K family software compatibility. A system can be upgraded using various memory
architectures without hardware and software redesign.
The ROM controller accommodates memories that are
either 8, 16, or 32 bits wide, and the DRAM controller accommodates dynamic memories that are 32 bits wide.
This unique feature provides a flexible interface to lowcost memory, as well as a convenient, flexible upgrade
8
path. For example, a system can start with a 16-bit ROM
memory design and can subsequently improve performance by migrating to a 32-bit ROM memory design.
One particular advantage is the ability to add memory in
half-megabyte increments. This provides significant
cost savings for applications that do not require larger
memory upgrades.
The Am29200, Am29202, Am29205, Am29240,
Am29245, and Am29243EH microcontrollers allow users to address an extremely wide range of cost performance points, with higher performance and lower cost
than existing designs based on CISC microprocessors.
Glueless System Interfaces
The Am29240EH microcontroller series also minimizes
system cost by providing a glueless attachment to external ROMs, DRAMs, and other peripheral components.
Processor outputs have edge-rate control that allows
them to drive a wide range of load capacitances with low
noise and ringing. This eliminates the cost of external
logic and buffering.
Bus and Software Compatibility
Compatibility within a processor family is critical for
achieving a rational, easy upgrade path. Processors in
the Am29240EH microcontroller series are all members
of a bus-compatible family of RISC microcontrollers. All
members of this family—the Am29205, Am29202,
Am29200, Am29240, Am29245, and Am29243EH microcontrollers—allow improvements in price, performance, and system capabilities without requiring that
users redesign their system hardware or software. Bus
compatibility ensures a convenient upgrade path for future systems.
The Am29240EH microcontroller series is available in a
208-pin plastic quad flat-pack (PQFP) package. The
Am29240EH microcontroller series is signal-compatible
with the Am29200 and the Am29205 microcontrollers.
Moreover, the Am29240EH microcontroller series is
binary compatible with existing RISC microcontrollers
and other members of the 29K family (the Am29000,
Am29005, Am29030, Am29035, Am29040, and
Am29050 microprocessors, as well as the Am29200,
Am29202, and Am29205 microcontrollers). The
Am29240EH microcontroller series provides a migration path to low-cost, high-performance, highly integrated systems from other 29K family members,
without requiring expensive rewrites of application
software.
Debugging and Testing
The Am29240EH microcontroller series provides debugging and testing features at both the software and
hardware levels.
Am29240 EH Microcontroller Series
PRELIMINARY
Software debugging is facilitated by the instruction
trace facility and instruction breakpoints. Instruction
tracing is accomplished by forcing the processor to trap
after each instruction has been executed. Instruction
breakpoints are implemented by the HALT instruction
or by a software trap.
The processor provides several additional features to
assist system debugging and testing:
The Test/Development Interface is composed of a
group of pins that indicate the state of the processor
and control the operation of the processor.
A Traceable Cache feature permits a hardwaredevelopment system to track accesses to the onchip caches, permitting a high level of visibility into
processor operation.
An IEEE Std 1149.1-1990 (JTAG) compliant Standard Test Access Port and Boundary-Scan Architecture. The Test Access Port provides a scan interface
for testing processor and system hardware in a production environment, and contains extensions that
allow a hardware-development system to control
and observe the processor without interposing hardware between the processor and system.
PERFORMANCE OVERVIEW
The Am29240EH microcontroller series offers a significant margin of performance over CISC microprocessors
in existing embedded designs, since the majority of processor features were defined for the maximum achievable performance at very low cost. This section
describes the features of the Am29240EH microcontroller series from the point of view of system performance.
Instruction Timing
The Am29240EH microcontroller series uses an arithmetic/logic unit, a field shift unit, and a prioritizer to
execute most instructions. Each of these is organized to
operate on 32-bit operands and provide a 32-bit result.
All operations are performed in a single cycle.
The performance degradation of load and store operations is minimized in the Am29240EH microcontroller
series by overlapping them with instruction execution,
by taking advantage of pipelining, by an on-chip data
cache, and by organizing the flow of external data into
the processor so that the impact of external accesses is
minimized.
Pipelining
Instruction operations are overlapped with instruction
fetch, instruction decode and operand fetch, instruction
execution, and result write-back to the Register File.
Pipeline forwarding logic detects pipeline dependencies
and routes data as required, avoiding delays that might
arise from these dependencies. Pipeline interlocks are
implemented by processor hardware. Except for a few
special cases, it is not necessary to rearrange programs
to avoid pipeline dependencies, although this is sometimes desirable for performance.
On-Chip Instruction and Data Caches
On-chip instruction and data caches satisfy most processor fetches without wait states. The caches are pipelined
for best performance. The reload policies minimize the
amount of time spent waiting for reload, while optimizing
the benefit of locality of reference.
Burst-Mode and Page-Mode Memories
The Am29240EH microcontroller series directly supports burst-mode memories. The burst-mode memory
supplies instructions at the maximum bandwidth, without the complexity of an external cache or the performance degradation due to cache misses.
The processor can also use the page-mode capability of
common DRAMs to improve the access time in cases
where page-mode accesses can be used.
Instruction Set Overview
All 29K family members employ a three-address instruction set architecture. The compiler or assembly-language programmer is given complete freedom to
allocate register usage. There are 192 general-purpose
registers, allowing the retention of intermediate calculations and avoiding needless data destruction. Instruction operands may be contained in any of the
general-purpose registers, and the results may be
stored into any of the general-purpose registers.
The Am29240EH microcontroller series instruction set
contains 117 instructions that are divided into nine
classes. These classes are integer arithmetic, compare,
logical, shift, data movement, constant, floating point,
branch, and miscellaneous. The floating-point instructions are not executed directly, but are emulated by trap
handlers.
All directly implemented instructions are capable of
executing in one processor cycle, with the exception of
interrupt returns, loads, and stores.
Data Formats
The Am29240EH microcontroller series defines a word
as 32 bits of data, a half-word as 16 bits, and a byte as 8
bits. The hardware provides direct support for wordinteger (signed and unsigned), word-logical, word-Boolean, half-word integer (signed and unsigned), and character data (signed and unsigned).
Word-Boolean data is based on the value contained in
the most significant bit of the word. The values TRUE
and FALSE are represented by the most significant bit
values 1 and 0, respectively.
Other data formats, such as character strings, are supported by instruction sequences. Floating-point formats
Am29240 EH Microcontroller Series
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(single and double precision) are defined for the processor; however, there is no direct hardware support for
these formats in the Am29240EH microcontroller series.
PIN DESCRIPTIONS
A23–A0
Address Bus (output, synchronous)
Protection
The Am29240EH microcontroller series offers two mutually exclusive modes of execution—the User and Supervisor modes—that restrict or permit accesses to certain
processor registers and external storage locations.
The Address Bus supplies the byte address for all accesses, except for DRAM accesses. For DRAM accesses, multiplexed row and column addresses are
provided on A14–A1. A2–A0 are also used to provide a
clock to an optional burst-mode EPROM.
The register file may be configured to restrict accesses
to Supervisor-mode programs on a bank-by-bank basis.
BOOTW
Memory Management Unit
This input configures the width of ROM Bank 0, so the
ROM can be accessed before the ROM configuration
has been set by the system initialization software. The
BOOTW signal is sampled during and after a processor
reset. If BOOTW is High before and after reset (tied
High), the boot ROM is 32 bits wide. If BOOTW is Low
before and after reset (tied Low), the boot ROM is 16 bits
wide. If BOOTW is Low before reset and High after reset
(tied to RESET), the boot ROM is 8 bits wide. This signal
has special hardening against metastable states, allowing it to be driven with a slow-rise-time signal and permitting it to be tied to RESET.
The Am29240EH microcontroller series provides a
memory-management unit (MMU) for translating virtual
addresses into physical addresses. The page size for
translation ranges from 1 Kbyte to 16 Mbytes in powers
of 4. The Am29245EH and Am29240EH microcontrollers each have a single, 16-entry TLB. The Am29243EH
microcontroller has dual 16-entry TLBs, each capable of
mapping pages of different size.
Interrupts and Traps
When the microcontroller takes an interrupt or trap, it
does not automatically save its current state information
in memory. This lightweight interrupt and trap facility
greatly improves the performance of temporary interruptions such as simple operating-system calls that require no saving of state information.
In cases where the processor state must be saved, the
saving and restoring of state information is under the control of software. The methods and data structures used to
handle interrupts—and the amount of state saved—may
be tailored to the needs of a particular system.
Interrupts and traps are dispatched through a 256-entry
vector table that directs the processor to a routine that
handles a given interrupt or trap. The vector table may
be relocated in memory by the modification of a processor register. There may be multiple vector tables in the
system, though only one is active at any given time.
The vector table is a table of pointers to the interrupt and
trap handlers, and requires only 1 Kbyte of memory. The
processor performs a vector fetch every time an interrupt or trap is taken. The vector fetch requires at least
three cycles, in addition to the number of cycles required
for the basic memory access.
Boot ROM Width (input, asynchronous)
BURST
Burst-Mode Access (output, synchronous)
This signal is asserted to perform sequential accesses
from a burst-mode device.
CAS3–CAS0
Column Address Strobes, Byte 3–0
(output, synchronous)
A High-to-Low transition on these signals causes the
DRAM selected by RAS3–RAS0 to latch the column address and complete the access. To support byte and
half-word writes, column address strobes are provided
for individual DRAM bytes. CAS3 is the column address
strobe for the DRAMs, in all banks, attached to
ID31–ID24. CAS2 is for the DRAMs attached to
ID23–ID16, and so on. These signals are also used in
other special DRAM cycles.
CNTL1–CNTL0
CPU Control
(input, asynchronous, internal pull-ups)
These inputs specify the processor mode: Load Test
Instruction, Step, Halt, or Normal.
DACKD–DACKA
DMA Acknowledge D through A
(output, synchronous)
These signals acknowledge an external transfer on a
DMA channel. DMA acknowledgments are not dedicated to a particular DMA channel—each channel specifies which acknowledge line, if any, it is using. Only one
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channel at a time can use either DACKD, DACKC,
DACKB, or DACKA, and the same channel uses the respective DREQD–DREQA signal for transfer requests.
DMA transfers can occur to and from internal peripherals independent of these acknowledgments. The
DACKD and DACKC signals are supported on the
Am29240EH and Am29243EH microcontrollers only.
DREQD–DREQA
DMA Request D through A
(input, asynchronous, pull-up resistors)
These inputs request an external transfer on a DMA
channel. DMA requests are not dedicated to a particular
channel—each channel specifies which request line, if
any, it is using. Only one channel at a time can use either
DREQD, DREQC, DREQB, or DREQA. This channel acknowledges a transfer using the respective DACKD–
DACKA signal. These requests are individually programmable to be either level- or edge-sensitive for either polarity of level or edge. DMA transfers can occur to and
from internal peripherals independent of these requests.
The DMA request/acknowledge pairs DREQA/ DACKA
and DREQB/ DACKB correspond to the Am29200 microcontroller signals DREQ0/DACK0 and DREQ1/DACK1,
respectively. The pin placement reflects this correspondence, and a processor reset dedicates these request/
acknowledge pairs to DMA channels 0 and 1,
respectively. This permits backward-compatible upgrade to an Am29200 microcontroller. The DREQD and
DREQC signals are supported on the Am29240EH and
Am29243EH microcontrollers only.
GREQ
External Memory Grant Request
(input, synchronous, pull-up resistor)
This signal is used by an external device to request an
access to the processor’s ROM or DRAM. To perform
this access, the external device supplies an address to
the ROM controller or DRAM controller.
To support a hardware-development system, GREQ
should be either tied High or held at a high-impedance
state during a processor reset.
ID31–ID0
Instruction/Data Bus (bidirectional, synchronous)
The Instruction/Data Bus (ID Bus) transfers instructions
to, and data to and from the processor.
IDP3–IDP0
Instruction/Data Parity
(bidirectional, synchronous)
If parity checking is enabled by the PCE bit of the
DRAM Control Register, IDP3–IDP0 are parity bits for
the ID Bus during DRAM accesses. IDP3 is the parity
bit for ID31–ID24, IDP2 is the parity bit for ID23–ID16,
and so on. If parity is enabled, the processor drives
IDP3–IDP0 with valid parity during DRAM writes, and
expects IDP3–IDP0 to be driven with valid parity during
DRAM reads. These signals are supported on the
Am29243EH microcontroller only.
INCLK
DSRA
Input Clock (input)
Data Set Ready, Port A (output, synchronous)
This is an oscillator input at twice the system operating
frequency.
This indicates to the host that the serial port is ready to
transmit or receive data on Serial Port A.
INTR3–INTR0
Interrupt Requests 3–0
(input, asynchronous, internal pull-up resistors)
DTRA
Data Terminal Ready, Port A
(input, asynchronous)
This indicates to the processor that the host is ready to
transmit or receive data on Serial Port A.
GACK
External Memory Grant Acknowledge
(output, synchronous)
This signal indicates to an external device that it has
been granted an access to the processor’s ROM or
DRAM, and that the device should provide an address.
The processor can be placed into a slave configuration
that allows tracing of a master processor. In this configuration, GACK is used to indicate that the processor pipeline was held during the previous processor cycle.
These inputs generate prioritized interrupt requests.
The interrupt caused by INTR0 has the highest priority,
and the interrupt caused by INTR3 has the lowest priority. The interrupt requests are masked in prioritized order by the Interrupt Mask field in the Current Processor
Status Register and are disabled by the DA and DI bits of
the Current Processor Status Register. These signals
have special hardening against metastable states, allowing them to be driven with slow-transition-time
signals.
LSYNC
Line Synchronization (input, asynchronous)
This signal indicates the start of a raster line. This signal
is supported on the Am29240EH and Am29245EH microcontrollers only.
Am29240 EH Microcontroller Series
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MEMCLK
PIO15–PIO0
Memory Clock (output)
Programmable Input/Output
(input/output, asynchronous)
MEMCLK is an output clock only. It operates at the system operating frequency, which is half of the INCLK frequency. Most processor inputs and outputs are
synchronous to MEMCLK. Note that MEMCLK as an input is not supported on the Am29240EH microcontroller
series.
MEMDRV
MEMCLK Drive Enable
(input, internal pull-up resistor)
The MEMDRV signal is reserved on the Am29240EH
microcontroller series. This pin should be either tied
High or left unconnected.
PACK
Parallel Port Acknowledge (output, synchronous)
This signal is used by the processor to acknowledge a
transfer from the host or to indicate to the host that data
has been placed on the port.
PAUTOFD
These signals are available for direct software control
and inspection. PIO15–PIO8 may be individually programmed to cause processor interrupts. These signals
have special hardening against metastable states, allowing them to be driven with slow-transition-time
signals.
The PIO signals are sampled during a processor reset.
After reset, the sampled value is held in the PIO Input
Register. This sampled value is supplied the first time
this register is read, unless the read is preceded by write
to the PIO Input Register or by a read or write of any other PIO register. This may be used to indicate system
configuration information to the processor during a
reset.
POE
Parallel Port Output Enable (output, synchronous)
This signal enables an external data buffer containing
data from the host to drive the ID Bus.
Parallel Port Autofeed (input, asynchronous)
PSTROBE
This signal is used by the host to indicate how line feeds
should be performed or is used to indicate that the host
is busy and cannot accept a data transfer.
Parallel Port Strobe (input, asynchronous)
PBUSY
This signal is used by the host to indicate that data is on
the Parallel Port or to acknowledge a transfer from the
processor.
Parallel Port Busy (output, synchronous)
PSYNC
This indicates to the host that the Parallel Port is busy
and cannot accept a data transfer.
Page Synchronization (input/output, asynchronous)
PIACS5–PIACS0
This signal indicates the beginning of a raster page. This
signal is supported on the Am29240EH and
Am29245EH microcontrollers only.
Peripheral Chip Selects, Regions 5–0
(output, synchronous)
PWE
These signals are used to select individual peripheral
devices. DMA channels may be programmed to use
dedicated chip selects during an external peripheral
access.
Parallel Port Write Enable (output, synchronous)
This signal writes a buffer with data on the ID Bus. Then,
the buffer drives data to the host.
R/W
PIAOE
Read/Write (output, synchronous)
Peripheral Output Enable (output, synchronous)
This signal enables the selected peripheral device to
drive the ID bus.
During an external ROM, DRAM, DMA, or PIA access,
this signal indicates the direction of transfer: High for a
read and Low for a write.
PIAWE
RAS3–RAS0
Peripheral Write Enable (output, synchronous)
Row Address Strobe, Banks 3–0
(output, synchronous)
This signal causes data on the ID bus to be written into
the selected peripheral.
12
A High-to-Low transition on one of these signals causes
a DRAM in the corresponding bank to latch the row address and begin an access. RAS3 starts an access in
DRAM Bank 3, and so on. These signals also are used in
other special DRAM cycles.
Am29240 EH Microcontroller Series
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RESET
TDI
Reset (input, asynchronous)
Test Data Input
(input, synchronous to TCK, pull-up resistor)
This input places the processor in the Reset mode. This
signal has special hardening against metastable states,
allowing it to be driven with a slow-rise-time signal.
ROMCS3–ROMCS0
ROM Chip Selects, Banks 3–0 (output, synchronous)
A Low level on one of these signals selects the memory
devices in the corresponding ROM bank. ROMCS3 selects devices in ROM Bank 3, etc. The timing and access
parameters of each bank are individually programmable.
ROMOE
ROM Output Enable (output, synchronous)
This signal enables the selected ROM Bank to drive the
ID bus. It is used to prevent bus contention when switching between different ROM banks or switching between
a ROM bank and another device or DRAM bank.
RSWE
ROM Space Write Enable (output, synchronous)
This signal is used to write an alterable memory in a
ROM bank (such as an SRAM or Flash EPROM).
This input supplies data to the test logic from an external
source. It is sampled on the rising edge of TCK. If it is not
driven, it appears High internally.
TDMA
Terminate DMA (input/output, synchronous)
This signal is either an input or an output as controlled by
the corresponding DMA Control Register. As an input,
this signal can be asserted during an external DMA
transfer (non-fly-by) to terminate the transfer after the
current access. The TDMA input is ignored during fly-by
transfers. As an output, this signal is asserted to indicate
the final transfer of a sequence.
TDO
Test Data Output
(three-state output, synchronous to TCK)
This output supplies data from the test logic to an external destination. It changes on the falling edge of TCK. It
is in the high-impedance state except when scanning is
in progress.
TMS
RXDA
Receive Data, Port A (input, asynchronous)
This input is used to receive serial data to Serial Port A.
Test Mode Select
(input, synchronous to TCK, pull-up resistor)
RXDB
This input is used to control the Test Access Port. If it is
not driven, it appears High internally.
Receive Data, Port B (input, asynchronous)
TR/OE
This input is used to receive data to Serial Port B. This
signal is supported on the Am29240EH and
Am29243EH microcontrollers only.
Video DRAM Transfer/Output Enable
(output, synchronous)
STAT2–STAT0
CPU Status (output, synchronous)
These outputs indicate information about the processor
or the current access for the purposes of hardware
debug.
This signal is used with video DRAMs to transfer data to
the video shift register. It is also used as an output enable in normal video DRAM read cycles. This signal is
supported on the Am29240EH and Am29245EH microcontrollers only.
TRAP1–TRAP0
Trap Requests 1–0
(input, asynchronous, internal pull-ups)
TCK
Test Clock Input
(input, asynchronous, pull-up resistor)
This input is used to operate the Test Access Port. The
state of the Test Access Port must be held if this clock is
held either High or Low. This clock is internally synchronized to MEMCLK for certain operations of the Test Access Port controller, so signals internally driven and
sampled by the Test Access Port are synchronous to
processor internal clocks.
These inputs generate prioritized trap requests. The
trap caused by TRAP0 has the highest priority. These
trap requests are disabled by the DA bit of the Current
Processor Status Register. These signals have special
hardening against metastable states, allowing them to
be driven with slow-transition-time signals.
Am29240 EH Microcontroller Series
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PRELIMINARY
This input is asserted to force all processor outputs into
the high-impedance state. This signal is tied High
through an internal pull-up resistor.
For external DMA accesses, the number of wait states
taken by the DRAM controller (this includes peripheral
read and write wait states during DMA transfers) is determined by the actual value in the DMAWAIT field of the
DMA Control Register or the number of wait states specified by the IOWAIT field in the PIA Control Register,
whichever is greater.
TRST
WARN
Test Reset Input
(input, asynchronous, pull-up resistor)
Warn (input, asynchronous, edge-sensitive,
internal pull-up)
This input asynchronously resets the Test Access Port.
If TRST is not driven, it appears High internally. TRST
must be tied to RESET, even if the Test Access Port is
not being used.
This output is used to transmit serial data from Serial
Port A.
A High-to-Low transition on this input causes a nonmaskable WARN trap to occur. This trap bypasses the
normal trap vector fetch sequence, and is useful in situations where the vector fetch may not work (e.g., when
data memory is faulty). This signal has special hardening against metastable states, allowing it to be driven
with a slow-transition-time signal. WARN must be held
active for at least four system clocks for the processor to
recognize it.
TXDB
WE
Transmit Data, Port B (output, asynchronous)
Write Enable (output, synchronous)
This output is used to transmit data from Serial Port B.
This signal is supported on the Am29240EH and
Am29243EH microcontrollers only.
This signal is used to write the selected DRAM bank.
“Early write” cycles are used so the DRAM data inputs
and outputs can be tied to the common ID Bus.
UCLK
PRODUCT ENHANCEMENTS
Programmable DRAM Timing
TRIST
Three-State Control
(input, asynchronous, pull-up resistor)
TXDA
Transmit Data, Port A (output, asynchronous)
UART Clock (input)
This is an oscillator input for generating the UART (Serial Port) clock. To generate the UART clock, the oscillator
frequency may be divided by any amount up to 65,536.
The UART clock operates at 16 times the Serial Port’s
baud rate. As an option, UCLK may be driven with
MEMCLK or INCLK. It can be driven with TTL levels.
VCLK
Video Clock (input, asynchronous)
This clock is used to synchronize the transfer of video
data. As an option, VCLK may be driven with MEMCLK
or INCLK. It can be driven with TTL levels. This signal is
supported on the Am29240EH and Am29245EH microcontrollers only.
VDAT
Through Bit 24 in the DRAM Control Register, the DRAM
controller now supports programmable DRAM timing,
for either two- or three-cycle simple accesses, with
single-cycle page-mode accesses. The new bit defined
below.
Bit 24: Programmable DRAM Timing (PDT)—A 1 in
this bit sets the DRAM timing to 2/1, for two-cycle simple
accesses and single-cycle page-mode accesses. A 0 in
this bit sets the DRAM timing to 3/1, for three-cycle simple accesses and single-cycle page-mode accesses.
FEATURES NO LONGER SUPPORTED
The following features are no longer supported on the
Am29240EH, Am29245EH, and Am29243EH microcontrollers:
Video Data (input/output, synchronous to VCLK)
33 MHz operating frequency
This is serial data to or from the video device. This signal
is supported on the Am29240EH and Am29245EH microcontrollers only.
Scalable Clocking technology (also known as
turbo mode or clock doubling)
WAIT
MEMDRV signal
Add Wait States
(input, synchronous, internal pull-up)
16-bit DRAM memory
MEMCLK as an input
External accesses are normally timed by the processor.
However, the WAIT signal may be asserted during a PIA,
ROM, or DMA access to extend the access indefinitely.
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CONNECTION DIAGRAM
208-Pin PQFP
Top Side View
Am29240EH Microcontroller Series
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Pin 1 is marked for orientation.
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PQFP PIN DESIGNATIONS (Pin Number)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Pin Name
Reserved
MEMCLK
MEMDRV
INCLK
VCC
GND
ID31
ID30
ID29
ID28
ID27
ID26
ID25
ID24
GND
VCC
ID23
ID22
ID21
ID20
ID19
ID18
ID17
ID16
GND
VCC
ID15
ID14
ID13
ID12
ID11
ID10
ID9
ID8
GND
VCC
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
GND
VCC
IDP3 1, 3
IDP2 1, 3
IDP1 1, 3
IDP0 1, 3
Pin No.
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
Pin Name
Reserved
VCC
GND
Reserved
TXDB 3
RXDB 3
DTRA
RXDA
UCLK
DSRA
TXDA
ROMCS3
ROMCS2
ROMCS1
ROMCS0
VCC
GND
BURST
RSWE
ROMOE
RAS3
RAS2
RAS1
RAS0
CAS3
CAS2
VCC
GND
CAS1
CAS0
TR/ OE
WE
GACK
PIACS5
PIACS4
PIACS3
PIACS2
VCC
GND
PIACS1
PIACS0
PIAWE
PIAOE
R/ W
DACKB
DACKA
DACKD 3
DACKC 3
VCC
GND
51
GND
103
Reserved
52
Reserved
104
Reserved
Notes:
1. Defined as no-connect on Am29240EH microcontroller.
16
Pin No.
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
Pin Name
Reserved
VCC
GND
Reserved
A23
A22
A21
A20
A19
A18
A17
A16
GND
VCC
A15
A14
A13
A12
A11
A10
A9
A8
GND
VCC
A7
A6
A5
A4
A3
A2
A1
A0
GND
VCC
BOOTW
WAIT
PAUTOFD
PSTROBE
PWE
POE
PACK
PBUSY
GND
VCC
PIO15
PIO14
PIO13
DREQD 3
DREQC 3
GND
Pin No.
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
Pin Name
Reserved
VCC
GND
PIO12
PIO11
PIO10
PIO9
PIO8
PIO7
PIO6
PIO5
PIO4
GND
VCC
PIO3
PIO2
PIO1
PIO0
TDO
STAT2
STAT1
STAT0
VDAT 2
PSYNC 2
GND
VCC
GREQ
DREQB
DREQA
TDMA
TRAP0
TRAP1
INTR0
INTR1
INTR2
INTR3
GND
VCC
WARN
VCLK 2
LSYNC 2
TMS
TRST
TCK
TDI
RESET
CNTL1
CNTL0
TRIST
VCC
155
VCC
207
GND
156
Reserved
208
Reserved
2. Defined as no-connect on Am29243EH microcontroller.
3. Defined as no-connect on Am29245EH microcontroller.
Am29240 EH Microcontroller Series
PRELIMINARY
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PQFP PIN DESIGNATIONS (Pin Name)
Pin Name
Pin No.
Pin Name
Pin No.
A0
136
GND
91
A1
135
GND
102
A2
134
GND
107
A3
133
GND
117
A4
132
GND
127
A5
131
GND
137
A6
130
GND
147
A7
129
GND
154
A8
126
GND
159
A9
125
GND
169
A10
124
GND
181
A11
123
GND
193
A12
122
GND
207
A13
121
Reserved
208
A14
120
GREQ
183
A15
119
ID0
44
A16
116
ID1
43
A17
115
ID2
42
A18
114
ID3
41
A19
113
ID4
40
A20
112
ID5
39
A21
111
ID6
38
A22
110
ID7
37
A23
109
ID8
34
BOOTW
139
ID9
33
BURST
70
ID10
32
CAS0
82
ID11
31
CAS1
81
ID12
30
CAS2
78
ID13
29
CAS3
77
ID14
28
CNTL0
204
ID15
27
CNTL1
203
ID16
24
DACKA
98
ID17
23
DACKB
97
ID18
22
DACKC 3
100
ID19
21
3
DACKD
99
ID20
20
DREQA
185
ID21
19
DREQB
184
ID22
18
DREQC 3
153
ID23
17
DREQD 3
152
ID24
14
DSRA
62
ID25
13
DTRA
59
ID26
12
GACK
85
ID27
11
GND
6
ID28
10
GND
15
ID29
9
GND
25
ID30
8
GND
35
ID31
7
1,
3
GND
45
IDP0
50
GND
51
IDP1 1, 3
49
GND
55
IDP2 1, 3
48
GND
69
IDP3 1, 3
47
GND
80
INCLK
4
Notes:
1. Defined as no-connect on Am29240EH microcontroller.
Pin Name
Pin No.
Pin Name
Pin No.
INTR0
189
RESET
202
INTR1
190
ROMCS0
67
INTR2
191
ROMCS1
66
INTR3
192
ROMCS2
65
2
LSYNC
197
ROMCS3
64
MEMCLK
2
ROMOE
72
MEMDRV
3
RSWE
71
PACK
145
RXDA
60
PAUTOFD
141
RXDB 3
58
PBUSY
146
STAT0
178
PIACS0
93
STAT1
177
PIACS1
92
STAT2
176
PIACS2
89
TCK
200
PIACS3
88
TDI
201
PIACS4
87
TDMA
186
PIACS5
86
TDO
175
PIAOE
95
TMS
198
PIAWE
94
TR/OE
83
PIO0
174
TRAP0
187
PIO1
173
TRAP1
188
PIO2
172
TRIST
205
PIO3
171
TRST
199
PIO4
168
TXDA
63
3
PIO5
167
TXDB
57
PIO6
166
UCLK
61
PIO7
165
Reserved
1
PIO8
164
VCC
5
PIO9
163
VCC
16
PIO10
162
VCC
26
PIO11
161
VCC
36
PIO12
160
VCC
46
PIO13
151
VCC
54
PIO14
150
VCC
68
PIO15
149
VCC
79
POE
144
VCC
90
PSTROBE
142
VCC
101
PSYNC 2
180
VCC
106
PWE
143
VCC
118
R/W
96
VCC
128
RAS0
76
VCC
138
RAS1
75
VCC
148
RAS2
74
VCC
155
RAS3
73
VCC
158
Reserved
52
VCC
170
Reserved
53
VCC
182
Reserved
56
VCC
194
Reserved
103
VCC
206
2
Reserved
104
VCLK
196
Reserved
105
VDAT 2
179
Reserved
108
WAIT
140
Reserved
156
WARN
195
Reserved
157
WE
84
2. Defined as no-connect on Am29243EH microcontroller.
3. Defined as no-connect on Am29245EH microcontroller.
Am29240 EH Microcontroller Series
17
PRELIMINARY
Am29240EH MICROCONTROLLER LOGIC SYMBOL
INCLK
MEMDRV
2
TRIST
CNTL1–CNTL0
3
A23–A0
24
R/ W
RESET
WARN
ROMCS3–ROMCS0
INTR3–INTR0
4
2
STAT2–STAT0
4
ROMOE
RSWE
BURST
TRAP1–TRAP0
WAIT
RAS3–RAS0
4
CAS3–CAS0
4
BOOTW
WE
TR/ OE
PIACS5–PIACS0
Am29240EH Microcontroller
4
PIAOE
PIAWE
DACKD–DACKA
DREQD–DREQA
GREQ
PBUSY
PACK
POE
PWE
UCLK
RXDB–RXDA
DTRA
TXDB–TXDA
DSRA
VCLK
LSYNC
TCK
TDI
TMS
TRST
TDO
MEMCLK VDAT PSYNC TDMA
18
4
GACK
PSTROBE
PAUTOFD
2
6
PIO15–PIO0
ID31–ID0
16
32
Am29240 EH Microcontroller Series
2
PRELIMINARY
Am29245EH MICROCONTROLLER LOGIC SYMBOL
INCLK
MEMDRV
2
TRIST
CNTL1–CNTL0
3
A23–A0
24
R/ W
RESET
WARN
ROMCS3–ROMCS0
INTR3–INTR0
4
2
STAT2–STAT0
4
ROMOE
RSWE
BURST
TRAP1–TRAP0
WAIT
RAS3–RAS0
4
CAS3–CAS0
4
BOOTW
WE
TR/ OE
PIACS5–PIACS0
PIAOE
PIAWE
Am29245EH Microcontroller
2
6
DACKB–DACKA
DREQB–DREQA
GREQ
2
GACK
PBUSY
PACK
POE
PWE
PSTROBE
PAUTOFD
UCLK
RXDA
DTRA
TXDA
DSRA
VCLK
LSYNC
TCK
TDI
TMS
TRST
TDO
MEMCLK VDAT PSYNC TDMA
PIO15–PIO0
ID31–ID0
16
32
Am29240 EH Microcontroller Series
19
PRELIMINARY
Am29243EH MICROCONTROLLER LOGIC SYMBOL
INCLK
MEMDRV
2
TRIST
CNTL1–CNTL0
STAT2–STAT0
3
A23–A0
24
R/ W
RESET
WARN
ROMCS3–ROMCS0
INTR3–INTR0
4
2
4
ROMOE
RSWE
BURST
TRAP1–TRAP0
WAIT
RAS3–RAS0
4
CAS3–CAS0
4
BOOTW
WE
TR/ OE
PIACS5–PIACS0
Am29243EH Microcontroller
4
PIAOE
PIAWE
DACKD–DACKA
DREQD–DREQA
GREQ
PBUSY
PACK
POE
PWE
UCLK
RXDB–RXDA
DTRA
TXDB–TXDA
DSRA
TCK
TDI
TMS
TRST
MEMCLK
TDO
TDMA
PIO15–PIO0
16
20
4
GACK
PSTROBE
PAUTOFD
2
6
ID31–ID0
32
Am29240 EH Microcontroller Series
IDP3–IDP0
4
2
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . . –65°C to +125°C
Voltage on any Pin
with Respect to GND . . . . . . . . . –0.5 V to VCC +2.4
Commercial (C) Devices
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
Case Temperature (TC) . . . . . . . . . . . . . . 0°C to +85°C
Supply Voltage (VCC) . . . . . . . . . . . . . . . +3 V to +3.6 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL Operating Ranges
Preliminary
Symbol
Parameter Description
VIL
Test Conditions
Min
Max
Unit
Input Low Voltage
–0.5
0.8
V
VIH
Input High Voltage
2.0
VCC +2.4
V
VILINCLK
INCLK Input Low Voltage
–0.5
0.8
V
VIHINCLK
INCLK Input High Voltage
2.4
5.5
V
VOL
Output Low Voltage for
All Outputs except MEMCLK
IOL = 3.2 mA
0.5
V
VOH
Output High Voltage for
All Outputs except MEMCLK
IOH = –400 µA
ILI
Input Leakage Current
0.45 V ≤ VIN ≤ VCC –0.45 V
Note 1
ILO
Output Leakage Current
0.45 V ≤ VOUT ≤ VCC –0.45 V
ICCOP
Operating Power-Supply Current with
respect to MEMCLK
VCC = 3.6 V, Outputs Floating;
Holding RESET active at 25 MHz
VOLC
MEMCLK Output Low Voltage
IOLC = 20 mA
VOHC
MEMCLK Output High Voltage
IOHC = –20 mA
2.4
V
IOSGND
MEMCLK GND Short Circuit Current
VCC = 3.3 V
100
mA
IOSVCC
MEMCLK VCC Short Circuit Current
VCC = 3.3 V
100
mA
2.4
V
±10 or
+10/–200
µA
±10
µA
8
mA/MHz
0.6
V
Notes:
1. The Low input leakage current for the inputs CNTL1–CNTL0, INTR3–INTR0, TRAP1–TRAP0, DREQD–DREQA, TCK, TDI,
RESET, TRST, TMS, GREQ, WARN, MEMDRV, WAIT, and TRIST is –200 µA. These pins have internal pull-up resistors.
CAPACITANCE
Preliminary
Symbol
Parameter Description
CIN
Test Conditions
Max
Unit
Input Capacitance
15
pF
CINCLK
INCLK Input Capacitance
15
pF
CMEMCLK
MEMCLK Capacitance
20
pF
COUT
Output Capacitance
20
pF
CI/O
I/O Pin Capacitance
20
pF
fC = 10 MHz
Min
Note: Limits guaranteed by characterization.
Am29240 EH Microcontroller Series
21
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL Operating Ranges
Preliminary
16 MHz
No.
Test Conditions 1
Parameter Description
20 MHz
25 MHz
Min
Max
Min
Max
Min
Max
Unit
50
25
50
20
50
ns
1
INCLK Period (=0.5T)
30
2
INCLK High Time
10
8
6
ns
3
INCLK Low Time
10
8
6
ns
4
INCLK Rise Time
0
5
0
5
0
5
ns
5
INCLK Fall Time
0
5
0
5
0
5
ns
6
MEMCLK Delay from INCLK
Note 1C, 3
1
7
1
7
1
7
ns
8
MEMCLK High Time
Note 1C
0.5T–3
0.5T–3
0.5T–3
ns
9
MEMCLK Low Time
Note 1C
0.5T–3
0.5T–3
0.5T–3
ns
10
MEMCLK Rise Time
Note 1C
1
4
1
4
1
4
ns
11
MEMCLK Fall Time
Note 1C
1
4
1
4
1
4
ns
12a
12b
Synchronous Output Valid Delay from MEMCLK Rising Edge
PIO15–PIO0, STAT2–STAT0,
PIACS5–PIACS0, and
RAS3–RAS0
Note 1A
1
13
1
12
1
11
ns
CAS3–CAS0 Rising Edge/
CAS3–CAS0 Falling Edge
Notes 1B, 4B
1
17/11
1
15/9
1
13/7
ns
All others
Note 1B
1
12
1
11
1
10
ns
Synchronous Output Valid Delay from MEMCLK Falling Edge
PIO15–PIO0, STAT2–STAT0,
PIACS5–PIACS0
Note 1A
1
12
1
11
1
10
ns
RAS3–RAS0
Note 1B
1
15
1
14
1
13
ns
CAS3–CAS0 Falling Edge
Notes 1B, 4B
1
11
1
9
1
7
ns
All others
Note 1B
1
11
1
10
1
9
ns
1
12
1
11
1
10
ns
13
Synchronous Output Disable
Delay from MEMCLK Rising
Edge
14
Synchronous Input Setup Time to MEMCLK Rising Edge
ID31–ID0 and IDP3–IDP0 for
DRAM access
Parity Enabled
Note 4A
18
16
15
ID31–ID0 for DRAM access
Parity Disabled
Note 4A
10
8
7
10
8
7
All others
15
Available CAS Access Time
(TCAS–TSetup)
Note 4B
16a
Synchronous Input Hold Time to
MEMCLK Rising Edge
Note 4A
0
0
0
16b
Synchronous Input Hold Time to
CAS Rising Edge
Note 4B
3
3
3
22
25
Am29240 EH Microcontroller Series
24
ns
ns
ns
19
ns
ns
ns
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL Operating Ranges (continued)
Preliminary
16 MHz
Test Conditions 1
No.
Parameter Description
17
Asynchronous Input Pulse Width
LSYNC and PSYNC
All others
Min
Max
20 MHz
Min
Max
25 MHz
Min
Max
Unit
Note 5
Note 5
Note 5
4T
4T
4T
ns
UCLK Period
Note 2
30
25
20
ns
VCLK Period
Note 2
25
20
15
ns
UCLK High Time
Note 2
10
8
6
ns
VCLK High Time
Note 2
8
6
4
ns
UCLK Low Time
Note 2
10
8
6
ns
VCLK Low Time
Note 2
8
6
4
ns
UCLK Rise time
Note 2
0
5
0
5
0
5
ns
VCLK Rise time
Note 2
0
3
0
3
0
3
ns
UCLK Fall Time
Note 2
0
5
0
5
0
5
ns
VCLK Fall Time
Note 2
0
3
0
3
0
3
ns
23
Synchronous Output Valid Delay
from VCLK Rise and Fall
Note 6
1
16
1
14
1
14
ns
24
Input Setup Time to VCLK Rise
and Fall
Notes 6, 7
10
9
9
ns
25
Input Hold Time to VCLK Rise
and Fall
Notes 6, 7
0
0
0
ns
26
RAS Low Time
50
50
50
ns
27
CAS Low Time
13
13
13
ns
18
19
20
21
22
Notes:
1. All outputs driving 80 pF, measured at VOL = 1.5 V and VOH = 1.5 V using the switching test circuit shown on page 33.
For higher capacitance loads:
A. Add 1 ns output delay per 15 pF loading above 80 pF, up to 150 pF total. The minimum delay from PIAOE to PIACSx is 0 ns if
the capacitance loading on PIACSx is equal to or higher than the capacitance loading on PIAOE.
B. Add 1 ns output delay per 25 pF loading above 80 pF, up to 300 pF total. For 2/1 DRAM timing, in order to meet the setup time
(tASR ) from A23–A0 to RAS3–RAS0 for DRAM, the capacitive loading of A23–A0 must not exceed the capacitance loading of
RAS3–RAS0 by more than 150 pF.
C. Add 1 ns of output delay for MEMCLK to drive an external load of 100 pF.
2. VCLK and UCLK can be driven with TTL inputs. UCLK must be tied High if it is unused.
3. Maximum INCLK-to-MEMCLK delay can be decreased by 0.5 ns for each 10 mA increase in IOL up to the maximum of 20 mA,
i.e., 6 ns maximum delay at IOL = 20 mA.
4. ID31–ID0 and IDP3–IDP0 are sampled on the rising edge of MEMCLK for all non-DRAM accesses, simple DRAM accesses,
and the first access of a DRAM page-mode access. ID31–ID0 and IDP3–IDP0 are sampled on the rising edge of CASx for all
DRAM page-mode accesses, except the first access of a DRAM page-mode access. (See Figures 1–12 on pages 25–32.)
A. Applies to ID31–ID0 and IDP3–IDP0 for simple DRAM accesses and the first access of a DRAM page-mode access.
B. Applies to ID31–ID0 and IDP3–IDP0 for DRAM page-mode accesses, except the first access of a DRAM page-mode access.
When ID31–ID0 and IDP3–IDP0 are sampled on CASx, there is no additional setup time required for ID31–ID0 and
IDP3–IDP0 when the parity is enabled.
5. LSYNC and PSYNC minimum width is two bit-times. A bit-time is one period of the internal video clock, which is determined by
the CLKDIV field in the Video Control Register and VCLK.
6. Active VCLK edge depends on the CLKI bit in the Video Control Register.
7. LSYNC and PSYNC can be treated as synchronous signals by meeting the setup and hold times, though the synchronization
delay still applies.
Am29240 EH Microcontroller Series
23
PRELIMINARY
SWITCHING WAVEFORMS
1
3
2
4
5
2.0 V
1.5 V
0.8 V
INCLK
6
8
9
10
11
VCC –0.6 V
1.5 V
0.8 V
MEMCLK
12a
SYNCHRONOUS
OUTPUTS
12b
13
1.5 V
14
SYNCHRONOUS
INPUTS
1.5 V
16a
1.5 V
15
CASx
Note: See Note 4 on page 23.
16b
17
ASYNCHRONOUS
INPUTS
1.5 V
1.5 V
18
19
21
UCLK, VCLK
20
22
2.0 V
1.5 V
0.8 V
23
VCLK-RELATIVE
OUTPUTS
25
24
VCLK-RELATIVE
INPUTS
1.5 V
1.5 V
Note:
During AC testing, all inputs are driven at VIL = 0.4 V, VIH = 2.4 V.
24
Am29240 EH Microcontroller Series
Note: Video Timing may be
relative to VCLK falling edge
if CLK = 1.
PRELIMINARY
SWITCHING WAVEFORMS (continued)
1.5 V
MEMCLK
A14–A1
Row Address
Column Address
R/W
RAS3–RAS0
CAS3–CAS0
WE
TR/OE
16a
14
ID31–ID0
IDP3–IDP0
1.5 V
1.5 V
Note: The RAS3–RAS0 signals are asserted and deasserted on the falling edge of MEMCLK.
Figure 1. Simple 3/1 DRAM Read Cycle
MEMCLK
A14–A1
Row Address
Column Address
R/W
RAS3–RAS0
CAS3–CAS0
WE
TR/OE
ID31–ID0
IDP3–IDP0
Data
Figure 2. Simple 3/1 DRAM Write Cycle
Am29240 EH Microcontroller Series
25
PRELIMINARY
SWITCHING WAVEFORMS (continued)
1.5 V
MEMCLK
A14–A1
Row Address
+2/4
+4/8
+6/12
1.5 V
1.5 V
1.5 V
Column Address
R/W
RAS3–RAS0
CAS3–CAS0
1.5 V
WE
TR/OE
15 + T/2
ID31–ID0
IDP3–IDP0
1.5
1.5VV
16b
15
16b
1.5 V
1.5 V
15
16b
16b
15
1.5 V
1.5 V
Note: The RAS3–RAS0 signals are asserted and deasserted on the falling edge of MEMCLK.
Figure 3. 3/1 DRAM Page-Mode Read
MEMCLK
A14–A1
Row Address
Column Address
+2/4
+4/8
+6/12
R/W
RAS3–RAS0
CAS3–CAS0
WE
TR/OE
ID31–ID0
IDP3–IDP0
Data
Data
Data
Figure 4. 3/1 DRAM Page-Mode Write
26
Am29240 EH Microcontroller Series
Data
PRELIMINARY
SWITCHING WAVEFORMS (continued)
MEMCLK
A14–A1
1.5 V
Row
Addr
Column Address
R/W
RAS3–RAS0
CAS3–CAS0
WE
TR/OE
14
ID31–ID0
IDP3–IDP0
1.5 V
16a
1.5 V
Figure 5. Simple 2/1 DRAM Read Cycle
MEMCLK
A14–A1
Row
Addr
Column Address
R/W
RAS3–RAS0
CAS3–CAS0
WE
TR/OE
ID31–ID0
IDP3–IDP0
Data
Figure 6. Simple 2/1 DRAM Write Cycle
Am29240 EH Microcontroller Series
27
PRELIMINARY
SWITCHING WAVEFORMS (continued)
MEMCLK
A14–A1
1.5 V
Row
Addr
Column Address
+2/4
+4/8
+6/12
R/W
RAS3–RAS0
CAS3–CAS0
1.5 V
1.5 V
1.5 V
1.5 V
WE
TR/OE
15 + T/2
1.5 V
ID31–ID0
IPD3–IDP0
16b
15
16b
15
1.5 V
1.5 V
16b
15
16b
1.5 V
1.5 V
Note: May be repeated up to 1-Kbyte address boundary.
Figure 7. 2/1 DRAM Page-Mode Read Cycle
MEMCLK
A14–A1
Row
Addr
Column Address
+2/4
+4/8
+6/12
Data
Data
Data
R/W
RAS3–RAS0
CAS3–CAS0
WE
TR/OE
ID31–ID0
IDP3–IDP0
Data
Note: May be repeated up to 1-Kbyte address boundary.
Figure 8. 2/1 DRAM Page-Mode Write Cycle
28
Am29240 EH Microcontroller Series
PRELIMINARY
SWITCHING WAVEFORMS (continued)
MEMCLK
DREQx
DACKx
A14–A1
Row Addr
Col
Addr
Col
Addr
Row Addr
Col
Addr
R/W
RASx
CASx
WE
TR/OE
ID31–ID0
Data
Data
Data
PIACSx
PIAOE
PIAWE
Note: May be repeated up to 1-Kbyte address
boundary.
Figure 9. Fly-By DMA Reads (Read Peripheral, Write DRAM)—3/1 DRAM Accesses
Am29240 EH Microcontroller Series
29
PRELIMINARY
SWITCHING WAVEFORMS (continued)
MEMCLK
DREQx
DACKx
A14–A1
Row Addr
Col
Addr
Col
Addr
Row Addr
Col
Addr
R/W
RASx
CASx
WE
TR/OE
ID31–ID0
Data
Data
Data
PIACSx
PIAOE
PIAWE
Note: May be repeated up to 1-Kbyte address
boundary.
Figure 10. Fly-By DMA Writes (Read DRAM, Write Peripheral)—3/1 DRAM Accesses
30
Am29240 EH Microcontroller Series
PRELIMINARY
SWITCHING WAVEFORMS (continued)
MEMCLK
DREQx
DACKx
A14–A1
Row
Addr
Col
Addr
Col
Addr
Row
Addr
Col
Addr
R/W
RASx
CASx
WE
TR/OE
ID31–ID0
Data
Data
Data
PIACSx
PIAOE
PIAWE
Note: May be repeated up to 1-Kbyte address boundary.
Figure 11. Fly-By DMA Reads (Read Peripheral, Write DRAM)—2/1 DRAM Accesses
Am29240 EH Microcontroller Series
31
PRELIMINARY
SWITCHING WAVEFORMS (continued)
MEMCLK
DREQx
DACKx
Row
Addr
A14–A1
Col
Addr
Col
Addr
Row
Addr
Col
Addr
R/W
RASx
CASx
WE
TR/OE
ID31–ID0
Data
Data
Data
PIACSx
PIAOE
PIAWE
Note: May be repeated up to 1-Kbyte address boundary.
Figure 12. Fly-By DMA Writes (Read DRAM, Write Peripheral)—2/1 DRAM Accesses
32
Am29240 EH Microcontroller Series
PRELIMINARY
SWITCHING TEST CIRCUIT
VL
IOL = 3.2 mA *
CL
V
Am29240EH Microcontroller
Pin Under Test
VREF = 1.5 V
IOH = 400 µA *
VH
Note:
*All outputs except MEMCLK. MEMCLK is tested with IOL = 20 mA and IOH = –20mA.
THERMAL CHARACTERISTICS
The Am29240EH microcontroller series is specified for
operation with case temperature ranges for a commercial
temperature device. Case temperature is measured at
the top center of the PQFP package as shown in Figure
13.
The various temperatures and thermal resistances can
be determined using the equations shown in Figure 14
along with information given in Table 2. (The variable P
is power in watts.)
θJA = θJC + θCA
θJA
P = ICCOP ⋅ freq ⋅ VCC
TJ = TC + P ⋅ θJC
θCA
TC
TJ = TA + P ⋅ θJA
θJC
ÉÉÉÉ
TC = TJ – P ⋅ θJC
TC = TA + P ⋅ θCA
TA = TJ – P ⋅ θJA
TA = TC – P ⋅ θCA
θJA = θJC + θCA
Figure 13. Thermal Resistance — °C/Watt
Figure 14. Thermal Characteristics Equations
Table 2. Thermal Characteristics (°C/Watt) Surface Mounted
Parameter
°C/Watt
θJA
Junction-to-Ambient
38
θJC
Junction-to-Case
8
θCA
Case-to-Ambient
30
Am29240 EH Microcontroller Series
33
PRELIMINARY
PHYSICAL DIMENSIONS
PQR 208, Trimmed and Formed
Plastic Quad Flat Pack
30.40
30.80
27.90
28.10
Pin 208
25.50
Ref.
Pin 156
Pin 1 I.D.
25.50
Ref.
–B–
–A–
27.90
28.10
30.40
30.80
Pin 52
–D–
Pin 104
Top View
See Detail X
0.50
Basic
S
3.95
Max.
3.20
3.60
0.25
Min.
–C–
S
Side View
Notes:
All measurements are in millimeters unless otherwise noted.
Not to scale. For reference only.
34
–A–
Am29240 EH Microcontroller Series
Seating
Plane
PRELIMINARY
PQR 208 (continued)
0.20 Min. Flat Shoulder
7° Typ.
0° Min.
0.30±0.05 R
Gage
Plane
3.95
Max
0.25
0.50
0.75
7° Typ.
0.13
0.20
0°–7°
0.18
0.30
Detail X
0.18
0.30
0.13
0.20
Section S–S
Notes:
All measurements are in millimeters unless otherwise noted.
Not to scale. For reference only.
Am29240 EH Microcontroller Series
35
PRELIMINARY
PHYSICAL DIMENSIONS (continued)
Solder Land Recommendations—208-Lead PQFP
31.60 Ref.
1.80 Typ.
28.00 Typ.
0.50 Typ.
25.50 Typ.
0.30 Typ.
29.80 Ref.
Notes:
All measurements are in millimeters unless otherwise noted.
Not to scale. For reference only.
Trademarks
Copyright  1997 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, Am29000, MiniMON29K, and Fusion29K are registered trademarks; 29K, AMD Facts-On-Demand, Am29005, Am29030,
Am29035, Am29040, Am29050, Am29200, Am29202, Am29205, Am29240, Am29243, Am29245, and Traceable Cache are trademarks of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
36
Am29240 EH Microcontroller Series