ONSEMI MC74VHC1GT125DF1

MC74VHC1GT125
Noninverting Buffer /
CMOS Logic Level Shifter
with LSTTL−Compatible Inputs
The MC74VHC1GT125 is a single gate noninverting buffer fabricated
with silicon gate CMOS technology. It achieves high speed operation
similar to equivalent Bipolar Schottky TTL while maintaining CMOS
low power dissipation.
The MC74VHC1GT125 requires the 3−state control input (OE) to be
set High to place the output into the high impedance state.
The device input is compatible with TTL−type input thresholds and the
output has a full 5 V CMOS level output swing. The input protection
circuitry on this device allows overvoltage tolerance on the input,
allowing the device to be used as a logic−level translator from 3.0 V
CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V
CMOS Logic while operating at the high−voltage power supply.
The MC74VHC1GT125 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHC1GT125 to be used to interface 5 V circuits to 3 V
circuits. The output structures also provide protection when VCC = 0 V.
These input and output structures help prevent device destruction caused
by supply voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
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MARKING
DIAGRAMS
SC−88A / SOT−353/SC−70
DF SUFFIX
CASE 419A
W1d
Pin 1
d = Date Code
TSOP−5/SOT−23/SC−59
DT SUFFIX
CASE 483
W1d
Pin 1
d = Date Code
High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V
Low Power Dissipation: ICC = 1 A (Max) at TA = 25°C
PIN ASSIGNMENT
TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V
CMOS−Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Pin and Function Compatible with Other Standard Logic Families
1
OE
2
IN A
3
GND
4
OUT Y
5
VCC
Chip Complexity: FETs = 62; Equivalent Gates = 16
FUNCTION TABLE
OE 1
5 VCC
IN A 2
GND 3
A Input
OE Input
Y Output
L
H
X
L
L
H
L
H
Z
4 OUT Y
Figure 1. Pinout (Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
OE
OUT Y
IN A
Figure 2. Logic Symbol
 Semiconductor Components Industries, LLC, 2003
December, 2003 − Rev. 8
1
Publication Order Number:
MC74VHC1GT125/D
MC74VHC1GT125
MAXIMUM RATINGS (Note 1)
Symbol
Value
Unit
VCC
DC Supply Voltage
Characteristics
−0.5 to +7.0
V
VIN
DC Input Voltage
−0.5 to +7.0
V
VOUT
DC Output Voltage
−0.5 to 7.0
−0.5 to VCC + 0.5
V
IIK
Input Diode Current
−20
mA
IOK
Output Diode Current
+20
mA
IOUT
DC Output Current, per Pin
+25
mA
ICC
DC Supply Current, VCC and GND
PD
Power Dissipation in Still Air
JA
Thermal Resistance
TL
VCC = 0
High or Low State
VOUT < GND; VOUT > VCC
+50
mA
SC−88A, TSOP−5
200
mW
SC−88A, TSOP−5
333
°C/W
Lead Temperature, 1 mm from Case for 10 s
260
°C
TJ
Junction Temperature Under Bias
+150
°C
Tstg
Storage Temperature
−65 to +150
°C
VESD
ESD Withstand Voltage
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
> 2000
> 200
N/A
V
ILatch−Up
Latch−Up Performance
Above VCC and Below GND at 125°C (Note 5)
±500
mA
1. Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those
indicated may adversely affect device reliability. Functional operation under absolute−maximum−rated conditions is not implied. Functional
operation should be restricted to the Recommended Operating Conditions.
2. Tested to EIA/JESD22−A114−A
3. Tested to EIA/JESD22−A115−A
4. Tested to JESD22−C101−A
5. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
Max
Unit
VCC
DC Supply Voltage
3.0
5.5
V
VIN
DC Input Voltage
0.0
5.5
V
VOUT
DC Output Voltage
0.0
VCC
V
TA
Operating Temperature Range
−55
+125
°C
tr , tf
Input Rise and Fall Time
0
20
ns/V
VCC = 5.0 V ± 0.5 V
47.9
100
178,700
20.4
110
79,600
9.4
120
37,000
4.2
130
17,800
2.0
140
8,900
1.0
TJ = 80 ° C
117.8
419,300
TJ = 90 ° C
1,032,200
90
TJ = 100 ° C
80
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
TJ = 110° C
Time, Years
TJ = 120° C
Time, Hours
TJ = 130 ° C
Junction
Temperature C
NORMALIZED FAILURE RATE
Device Junction Temperature versus
Time to 0.1% Bond Failures
1
1
10
100
TIME, YEARS
Figure 3. Failure Rate vs. Time
Junction Temperature
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2
1000
MC74VHC1GT125
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DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Conditions
Min
1.4
2.0
2.0
VIH
Minimum High−Level
Input Voltage
3.0
4.5
5.5
VIL
Maximum Low−Level
Input Voltage
3.0
4.5
5.5
VOH
Minimum High−Level
Output Voltage
g
VIN = VIH or VIL
VOL
Maximum Low−Level
Output Voltage
g
VIN = VIH or VIL
TA ≤ 85°C
TA = 25°C
VCC
(V)
Typ
Max
Min
3.0
4.5
2.9
4.4
VIN = VIH or VIL
IOH = − 4 mA
IOH = − 8 mA
3.0
4.5
2.58
3.94
VIN = VIH or VIL
IOL = 50 A
3.0
4.5
VIN = VIH or VIL
IOL = 4 mA
IOL = 8 mA
Max
1.4
2.0
2.0
0.53
0.8
0.8
VIN = VIH or VIL
IOH = − 50 A
−55 ≤ TA ≤ 125°C
3.0
4.5
0.0
0.0
Min
Max
1.4
2.0
2.0
V
0.53
0.8
0.8
0.53
0.8
0.8
2.9
4.4
2.9
4.4
2.48
3.80
2.34
3.66
Unit
V
V
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
V
IIN
Maximum Input
Leakage Current
VIN = 5.5 V or GND
0 to
5.5
± 0.10
± 1.0
± 1.0
A
ICC
Maximum Quiescent
Supply Current
VIN = VCC or GND
5.5
1.0
20
40
A
ICCT
Quiescent Supply
Current
Input: VIN = 3.4 V
Other Input: VCC or GND
5.5
1.35
1.50
1.65
mA
IOPD
Output Leakage
Current
VOUT = 5.5 V
0.0
0.5
5.0
10
A
IOZ
Maximum 3−State
Leakage Current
VIN = VIH or VIL
VOUT = VCC or GND
5.5
± 0.25
± 2.5
± 2.5
A
IOPD
Output Leakage
Current
VOUT = 5.5 V
0.0
0.5
5.0
10
A
AC ELECTRICAL CHARACTERISTICS Input tr = tf = 3.0 ns
TA ≤ 85°C
TA = 25°C
Symbol
tPLH,
tPHL
tPZL,
tPZH
tPLZ,
tPHZ
Typ
Max
Min
Max
VCC = 3.3 ± 0.3 V CL = 15pF
CL = 50pF
5.6
8.1
8.0
11.5
1.0
1.0
9.5
13.0
12.0
16.0
VCC = 5.0 ± 0.5 V CL = 15pF
CL = 50pF
3.8
5.3
5.5
7.5
1.0
1.0
6.5
8.5
8.5
10.5
Maximum Output
Enable TIme,OE to Y
(Fi
(Figures
4.
4 and
d 5.)
5)
VCC = 3.3 ± 0.3 V CL = 15pF
RL = RI = 500 CL = 50pF
5.4
7.9
8.0
11.5
1.0
1.0
9.5
13.0
11.5
15.0
VCC = 5.0 ± 0.5 V CL = 15pF
RL = RI = 500 CL = 50pF
3.6
5.1
5.1
7.1
1.0
1.0
6.0
8.0
7.5
9.5
Maximum Output
Disable Time,OE to Y
(Fi
4 and
d 5.)
5)
(Figures
4.
VCC = 3.3 ± 0.3 V CL = 15pF
RL = RI = 500 CL = 50pF
6.5
8.0
9.7
13.2
1.0
1.0
11.5
15.0
14.5
18.0
VCC = 5.0 ± 0.5 V CL = 15pF
RL = RI = 500 CL = 50pF
4.8
7.0
6.8
8.8
1.0
1.0
8.0
10.0
10.0
12.0
10
10
10
Parameter
Maximum Propagation
Delay,
y A to Y
(Fi
(Figures
3.
3 and
d 5.)
5)
Min
−55 ≤ TA ≤ 125°C
Test Conditions
Cin
Maximum Input Capacitance
4
Cout
Maximum Three−State
Output Capacitance (Output
in High Impedance State)
6
Min
Max
Unit
ns
ns
ns
pF
pF
Typical @ 25°C, VCC = 5.0 V
CPD
14
Power Dissipation Capacitance (Note 6)
pF
6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 4 (per buffer). CPD is used to determine the
no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
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3
MC74VHC1GT125
SWITCHING WAVEFORMS
VCC
50%
A
OE
tPHL
tPLH
VCC
50%
GND
tPZL
GND
tPZH
Y
VOL + 0.3V
tPHZ
VOH − 0.3V
50% VCC
Y
Figure 4. Switching Waveforms
HIGH
IMPEDANCE
Figure 5.
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
HIGH
IMPEDANCE
50% VCC
Y
50% VCC
tPLZ
DEVICE
UNDER
TEST
CL*
*Includes all probe and jig capacitance
1 k
OUTPUT
CL *
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
*Includes all probe and jig capacitance
Figure 6. Test Circuit
Figure 7. Test Circuit
INPUT
Figure 8. Input Equivalent Circuit
DEVICE ORDERING INFORMATION
Device Nomenclature
Device
Order Number
Circuit
Indicator
Temp
Range
Identifier
Technology
Device
Function
Package
Suffix
Tape &
Reel
Suffix
Package Type
(Name/SOT#/
Common Name)
Tape and
Reel Size†
MC74VHC1GT125DF1
MC
74
VHC1G
T125
DF
1
SC−88A / SOT−353
/ SC−70
178 mm (7”)
3000 Unit
MC74VHC1GT125DF2
MC
74
VHC1G
T125
DF
2
SC−88A / SOT−353
/ SC−70
178 mm (7”)
3000 Unit
MC74VHC1GT125DT1
MC
74
VHC1G
T125
DT
1
TSOPS / SOT−23
/ SC−59
178 mm (7”)
3000 Unit
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
MC74VHC1GT125
CAVITY
TAPE
TAPE TRAILER
(Connected to Reel Hub)
NO COMPONENTS
160 mm MIN
TOP TAPE
COMPONENTS
TAPE LEADER
NO COMPONENTS
400 mm MIN
DIRECTION OF FEED
Figure 9. Tape Ends for Finished Goods
TAPE DIMENSIONS mm
4.00
1.50 TYP
4.00
2.00
1.75
3.50 0.50
8.00 0.30
1
1.00 MIN
DIRECTION OF FEED
Figure 10. SC−70−5/SC−88A/SOT−353 DF1 Reel Configuration/Orientation
TAPE DIMENSIONS mm
4.00
1.50 TYP
4.00
2.00
1.75
3.50 0.50
8.00 0.30
1
1.00 MIN
DIRECTION OF FEED
Figure 11. SC−70/SC−88A/SOT−353 DF2 and SOT23−5/TSOP−5/SC59−5 DT1 Reel Configuration/Orientation
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5
MC74VHC1GT125
t MAX
1.5 mm MIN
(0.06 in)
A
13.0 mm 0.2 mm
(0.512 in 0.008 in)
50 mm MIN
(1.969 in)
20.2 mm MIN
(0.795 in)
FULL RADIUS
G
Figure 12. Reel Dimensions
REEL DIMENSIONS
Tape Size
T and R Suffix
A Max
G
t Max
8 mm
1, 2
178 mm
(7 in)
8.4 mm, + 1.5 mm, −0.0
(0.33 in + 0.059 in, −0.00)
14.4 mm
(0.56 in)
DIRECTION OF FEED
BARCODE LABEL
POCKET
Figure 13. Reel Winding Direction
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6
HOLE
MC74VHC1GT125
PACKAGE DIMENSIONS
SC70−5/SC−88A/SOT−353
DF SUFFIX
5−LEAD PACKAGE
CASE 419A−02
ISSUE G
A
G
5
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
4
DIM
A
B
C
D
G
H
J
K
N
S
−B−
S
1
2
3
D 5 PL
0.2 (0.008)
B
M
M
N
INCHES
MIN
MAX
0.071
0.087
0.045
0.053
0.031
0.043
0.004
0.012
0.026 BSC
−−−
0.004
0.004
0.010
0.004
0.012
0.008 REF
0.079
0.087
J
K
SOLDERING FOOTPRINT*
0.50
0.0197
0.65
0.025
0.65
0.025
0.40
0.0157
SCALE 20:1
1.9
0.0748
mm inches
Figure 14. SC−88A/SC70−5/SOT−353
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
MILLIMETERS
MIN
MAX
1.80
2.20
1.15
1.35
0.80
1.10
0.10
0.30
0.65 BSC
−−−
0.10
0.10
0.25
0.10
0.30
0.20 REF
2.00
2.20
MC74VHC1GT125
PACKAGE DIMENSIONS
SOT23−5/TSOP−5/SC59−5
DT SUFFIX
5−LEAD PACKAGE
CASE 483−01
ISSUE C
D
S
5
4
1
2
3
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. A AND B DIMENSIONS DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
L
MILLIMETERS
INCHES
DIM MIN
MAX
MIN
MAX
A
2.90
3.10 0.1142 0.1220
B
1.30
1.70 0.0512 0.0669
C
0.90
1.10 0.0354 0.0433
D
0.25
0.50 0.0098 0.0197
G
0.85
1.05 0.0335 0.0413
H 0.013 0.100 0.0005 0.0040
J
0.10
0.26 0.0040 0.0102
K
0.20
0.60 0.0079 0.0236
L
1.25
1.55 0.0493 0.0610
M
0_
10 _
0_
10 _
S
2.50
3.00 0.0985 0.1181
G
A
J
C
0.05 (0.002)
H
M
K
SOLDERING FOOTPRINT*
0.95
0.037
1.9
0.074
2.4
0.094
1.0
0.039
0.7
0.028
SCALE 10:1
mm inches
Figure 15. THIN SOT23−5/TSOP−5/SC59−5
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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MC74VHC1GT125/D