PROCESS CP214 Central Small Signal Transistor TM Semiconductor Corp. NPN - Silicon RF Transistor Chip PROCESS DETAILS Process EPITAXIAL PLANAR Die Size 16 x 16 MILS Die Thickness 7.5 MILS Base Bonding Pad Area 2.9 x 3.4 MILS Emitter Bonding Pad Area 2.9 x 3.4 MILS Top Side Metalization Al - 20,000Å Back Side Metalization Au - 16,000Å GEOMETRY GROSS DIE PER 4 INCH WAFER 44,460 PRINCIPAL DEVICE TYPES 2N5109 B E BACKSIDE COLLECTOR 145 Adams Avenue Hauppauge, NY 11788 USA Tel: (631) 435-1110 Fax: (631) 435-1824 www.centralsemi.com R1 R2 (1-August 2002) Central TM Semiconductor Corp. 145 Adams Avenue Hauppauge, NY 11788 USA Tel: (631) 435-1110 Fax: (631) 435-1824 www.centralsemi.com PROCESS CP214 Typical Electrical Characteristics R2 (1-August 2002)