FUJITSU SEMICONDUCTOR DATA SHEET DS05-20894-1E FLASH MEMORY CMOS 32 M (4 M × 8/2 M × 16) BIT MBM29LV320TE 80/90/10 MBM29LV320BE80/90/10 ■ DESCRIPTION The MBM29LV320TE/BE is 32 M-bit, 3.0 V-only Flash memory organized as 4 M bytes of 8 bits each or 2 M words of 16 bits each. The device is offered in a 48-pin TSOP (I) and 63-ball FBGA packages. This device is designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The device can also be reprogrammed in standard EPROM programmers. The standard device offers access times 80 ns, 90 ns and 100 ns, allowing operation of high-speed microprocessors without wait state. To eliminate bus contention the device has separate chip enable(CE), write enable(WE) and output enable (OE) controls. (Continued) ■ PRODUCT LINE UP Part No. MBM29LV320TE/BE 80 90 VCC = 3.3 V Power Supply Voltage (V) +0.3 V −0.3 V 100 V VCC = 3.0 V +0.6 −0.3 V Max Address Access Time (ns) 80 90 100 Max CE Access Time (ns) 80 90 100 Max OE Access Time (ns) 30 35 35 ■ PACKAGES 48-pin plastic TSOP (I) 48-pin plastic TSOP (I) 63-ball plastic FBGA Marking Side (FPT-48P-M19) Marking Side (FPT-48P-M20) (BGA-63P-M01) MBM29LV320TE/BE80/90/10 (Continued) The device is pin and command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices. The device is programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically time the erase pulse widths and verify proper cell margin. A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.) The device also features a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The device is erased when shipped from the factory. The device features single 3.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been completed, the device internally resets to the read mode. The device also has a hardware RESET pin. When this pin is driven low, execution of any Embedded Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the read mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during the Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the read mode and will have erroneous data stored in the address locations being programmed or erased. These locations need re-writing after the Reset. Resetting the device enables the system’s microprocessor to read the boot-up firmware from the Flash memory. Fujitsu’s Flash technology combines years of EPROM and E2PROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The device memory electrically erase the entire chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection. 2 MBM29LV320TE/BE80/90/10 ■ FEATURES • 0.23 µm Process Technology • Single 3.0 V read, program, and erase Minimized system level power requirements • Compatible with JEDEC-standard commands Use the same software commands as E2PROMs • Compatible with JEDEC-standard world-wide pinouts 48-pin TSOP (I) (Package suffix : TN − Normal Bend Type, TR − Reversed Bend Type) 63-ball FBGA (Package suffix : PBT) • Minimum 100,000 program/erase cycles • High performance 80 ns maximum access time • Sector erase architecture Eight 4 K word and sixty-three 32 K word sectors in word mode Eight 8 K byte and sixty-three 64 K byte sectors in byte mode Any combination of sectors can be concurrently erased. Also supports full chip erase. • Boot Code Sector Architecture T = Top sector B = Bottom sector • Hidden ROM (Hi-ROM) region 256 byte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence Factory serialized and protected to provide a secure electronic serial number (ESN) • WP/ACC input pin At VIL, allows protection of boot sectors, regardless of sector protection/unprotection status At VIH, allows removal of boot sector protection At VACC, increases program performance • Embedded EraseTM* Algorithms Automatically pre-programs and erases the chip or any sector • Embedded ProgramTM* Algorithms Automatically writes and verifies data at specified address • Data Polling and Toggle Bit feature for detection of program or erase cycle completion • Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion • Automatic sleep mode When addresses remain stable, automatically switch themselves to low power mode. • Low VCC write inhibit ≤ 2.5 V • Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device • Sector group protection Hardware method disables any combination of sector groups from program or erase operations • Sector Group Protection Set function by Extended sector group protection command • Fast Programming Function by Extended Command • Temporary sector group unprotection Temporary sector group unprotection via the RESET pin. • In accordance with CFI (Common Flash Memory Interface) *: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. 3 MBM29LV320TE/BE80/90/10 ■ PIN ASSIGNMENTS TSOP (I) A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE RESET N.C. WP/ACC RY/BY A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 (Marking Side) MBM29LV320TE/BE Normal Bend 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE VSS CE A0 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 A0 CE VSS OE DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 VCC DQ4 DQ12 DQ5 DQ13 DQ6 DQ14 DQ7 DQ15/A-1 VSS BYTE A16 (FPT-48P-M19) A1 A2 A3 A4 A5 A6 A7 A17 A18 RY/BY WP/ACC N.C. RESET WE A20 A19 A8 A9 A10 A11 A12 A13 A14 A15 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 (Marking Side) MBM29LV320TE/BE Reverse Bend (FPT-48P-M20) (Continued) 4 MBM29LV320TE/BE80/90/10 (Continued) FBGA (TOP VIEW) Marking Side A8 B8 L8 M8 N.C. N.C. N.C. N.C. A7 B7 C7 D7 E7 F7 G7 L7 M7 N.C. N.C. A13 A12 A14 A15 A16 N.C. N.C. C6 D6 E6 F6 G6 A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6 C5 D5 E5 F5 G5 A19 DQ5 DQ12 WE RESET N.C. C4 D4 RY/BY WP/ ACC H7 J7 K7 BYTE DQ15/ VSS A-1 H6 H5 H4 J6 K6 J5 K5 VCC DQ4 J4 K4 E4 F4 G4 A18 A20 DQ2 DQ10 DQ11 DQ3 C3 D3 E3 F3 G3 H3 J3 K3 A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1 A2 C2 D2 E2 F2 G2 H2 J2 K2 L2 M2 N.C. A3 A4 A2 A1 A0 CE OE VSS N.C. N.C. A1 B1 L1 M1 N.C. N.C. N.C. N.C. (BGA-63P-M01) 5 MBM29LV320TE/BE80/90/10 ■ PIN DESCRIPTION MBM29LV320 TE/BE Pin Configuration Table Pin A20 to A0, A-1 Address Inputs DQ15 to DQ0 Data Inputs/Outputs CE Chip Enable OE Output Enable WE Write Enable RY/BY Ready/Busy Output RESET Hardware Reset Pin/Temporary Sector Group Unprotection BYTE WP/ACC 6 Function Selects 8-bit or 16-bit mode Hardware Write Protection/Program Acceleration N.C. No Internal Connection VSS Device Ground VCC Device Power Supply MBM29LV320TE/BE80/90/10 ■ BLOCK DIAGRAM RY/BY Buffer DQ15 to DQ0 RY/BY VCC VSS WE BYTE Erase Voltage Generator Input/Output Buffers State Control RESET WP/ACC Command Register Program Voltage Generator Chip Enable Output Enable Logic CE STB Data Latch OE Y-Decoder STB Low VCC Detector Timer for Program/Erase Address X-Decoder Latch Y-Gating Cell Matrix A20 to A09 A-1 ■ LOGIC SYMBOL A-1 21 A20 to A0 16 or 8 DQ15 to DQ0 CE OE WE RY/BY RESET BYTE WP/ACC 7 MBM29LV320TE/BE80/90/10 ■ DEVICE BUS OPERATION MBM29LV320TE/BE User Bus Operations Table (BYTE = VIH) CE OE WE Operation Auto-Select Manufacturer Code *1 A0 A1 A6 A9 DQ15 to DQ0 RESET WP/ ACC L L H L L L VID Code H X Auto-Select Device Code * L L H H L L VID Code H X Extended Auto-Select Device Code *1 L L H H H L VID Code H X Read *3 L L H A0 A1 A6 A9 DOUT H X Standby H X X X X X X High-Z H X Output Disable L H H X X X X High-Z H X Write (Program/Erase) L H L A0 A1 A6 A9 DIN H X Enable Sector Group Protection *2, *4 L VID L H L VID X H X *6 Verify Sector Group Protection *2, *4 L L H L H L VID Code H X *6 Temporary Sector Group Unprotection *5 X X X X X X X X VID X *6 Reset (Hardware) /Standby X X X X X X X High-Z L X Boot Block Sector Write Protection X X X X X X X X X L 1 Legend : L = VIL, H = VIH, X = VIL or VIH, = Pulse input. See “■DC CHARACTERISTICS” for voltage levels. *1: Manufacturer and device codes may also be accessed via a command register write sequence. See “MBM29LV320TE/BE Command Definitions Table”. *2: See the section on “7. Sector Group Protection” in ■FUNCTIONAL DESCRIPTION. *3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *4: VCC = 3.3 V ± 10% *5: It is also used for the extended sector group protection. *6: Conditional exceptions are to be noticed as follows: For MBM29LV320TE (SA22, 23) , WP/ACC = VIH. For MBM29LV320BE (SA0, 1) , WP/ACC = VIH. 8 MBM29LV320TE/BE80/90/10 MBM29LV320TE/BE User Bus Operations Table (BYTE = VIL) CE OE WE Operation Auto-Select Manufacturer Code *1 DQ15 /A-1 A0 A1 A6 A9 DQ7 to DQ0 RESET WP/ ACC L L H L L L L VID Code H X Auto-Select Device Code * L L H L H L L VID Code H X Extended Auto-Select Device Code *1 L L H L H H L VID Code H X Read *3 L L H A-1 A0 A1 A6 A9 DOUT H X Standby H X X X X X X X High-Z H X Output Disable L H H X X X X X High-Z H X Write (Program/Erase) L H L A-1 A0 A1 A6 A9 DIN H X Enable Sector Group Protection *2, *4 L VID L L H L VID X H X *6 Verify Sector Group Protection *2, *4 L L H L L H L VID Code H X *6 Temporary Sector Group Unprotection *5 X X X X X X X X X VID X *6 Reset (Hardware) /Standby X X X X X X X X High-Z L X Boot Block Sector Write Protection X X X X X X X X X X L 1 Legend : L = VIL, H = VIH, X = VIL or VIH, = Pulse input. See “■DC CHARACTERISTICS” for voltage levels. *1: Manufacturer and device codes may also be accessed via a command register write sequence. See “MBM29LV320TE/BE Command Definitions Table”. *2: See the section on “7. Sector Group Protection” in ■FUNCTIONAL DESCRIPTION. *3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *4: VCC = 3.3 V ± 10% *5: It is also used for the extended sector group protection. *6: Conditional exceptions are to be noticed as follows: For MBM29LV320TE (SA22, 23) , WP/ACC = VIH. For MBM29LV320BE (SA0, 1) , WP/ACC = VIH. 9 MBM29LV320TE/BE80/90/10 MBM29LV320TE/BE Command Definitions Table Second Command Sequence First Bus Third Bus Bus Bus Write Write Cycle Write Cycle Write Cycle Cycles Req’d Fourth Bus Fifth Bus Sixth Bus Read/Write Write Cycle Write Cycle Cycle Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Read/ Reset Word Read/ Reset Word Autoselect Program Chip Erase Sector Erase Byte Byte Word Byte Word Byte Word Byte Word Byte 1 3 3 4 6 6 XXXh F0h 555h AAAh 555h AAAh 555h AAAh 555h AAAh 555h AAAh AAh AAh AAh AAh AAh 2AAh 555h 2AAh 555h 2AAh 555h 2AAh 555h 2AAh 555h 55h 55h 55h 55h 55h 555h AAAh 555h AAAh 555h AAAh 555h AAAh 555h AAAh F0h RA RD 90h A0h PA PD 80h 80h 555h AAAh 555h AAAh AAh AAh 2AAh 555h 2AAh 555h 55h 555h AAAh 10h 55h SA 30h Erase Suspend 1 XXXh B0h Erase Resume 1 XXXh 20h Set to Fast Mode Word Fast Program*1 Word Byte Byte 3 2 Reset from Word Fast Mode*1 Byte 2 Extended Sector Group Protection*2 4 Query*3 555h AAAh XXXh XXXh XXXh XXXh 30h AAh A0h 90h 2AAh 555h PA 55h PD XXXh *5 XXXh F0h 555h AAAh Word Byte Word Byte Hi-ROM Entry Word Hi-ROM Program*4 Word Hi-ROM Exit*4 Word Byte Byte Byte 1 3 4 4 XXXh 55h AAh 555h AAAh 555h AAAh 555h AAAh 60h SPA 60h SPA 40h SPA SD 98h 88h PD 00h AAh AAh AAh 2AAh 555h 2AAh 555h 2AAh 555h 55h 55h 55h 555h AAAh 555h AAAh 555h AAAh A0h 90h (HRA) PA XXXh (Continued) 10 MBM29LV320TE/BE80/90/10 (Continued) *1 : This command is valid during Fast Mode. *2 : This command is valid while RESET = VID. *3 : The valid addresses are A6 to A0. *4 : This command is valid during Hi-ROM mode. *5 : The data "00h" is also acceptable. Notes: • Address bits A20 to A11 = X = “H” or “L” for all address commands except or Program Address (PA) and Sector Address (SA) . • Bus operations are defined in “MBM29LV320TE/BE User Bus Operations Tables (BYTE = VIH and BYTE = VIL)” . • RA = Address of the memory location to be read PA = Address of the memory location to be programmed Addresses are latched on the falling edge of the write pulse. SA = Address of the sector to be erased. The combination of A20, A19, A18, A17, A16, A15, A14, A13, and A12 will uniquely select any sector. • RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the falling edge of write pulse. • SPA = Sector group address to be protected. Set sector group address (SGA) and (A6, A1, A0) = (0, 1, 0) . SD = Sector group protection verify data. Output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. • HRA = Address of the Hi-ROM area 29LV320TE (Top Boot Type) Word Mode : 1FFFE0h to 1FFFFFh Byte Mode : 3FFFC0h to 3FFFFFh 29LV320BE (Bottom Boot Type) Word Mode : 000000h to 000040h Byte Mode : 000000h to 000080h • The system should generate the following address patterns : Word Mode : 555h or 2AAh to addresses A10 to A0 Byte Mode : AAAh or 555h to addresses A10 to A0, and A-1 • Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. • The command combinations not described in “MBM29LV320TE/BE Command Definition Table” are illegal. 11 MBM29LV320TE/BE80/90/10 MBM29LV320TE/BE Sector Group Protection Verify Autoselect Codes Table Type A20 to A12 A6 A1 A0 A-1 *1 Code (HEX) SA VIL VIL VIL VIL 04h SA VIL VIL VIH VIL F6h X 22F6h SA VIL VIL VIH VIL F9h X 22F9h VIL 19h SA VIL VIH VIH X 0019h Sector Group Addresses VIL VIH VIL VIL 01h*2 Manufacture’s Code MBM29LV320TE Device Code MBM29LV320BE Extend Device Code Byte Word Byte Word Byte MBM29LV320TE/BE Word Sector Group Protection *1 : A-1 is for Byte mode. *2 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. Expanded Autoselect Code Table Type Manufacturer’s Code 04h A-1/0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 0 1 1 0 1 1 1 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 0 0 0 1 1 0 0 1 A-1 HZ HZ HZ HZ 0 0 0 1 0 F9h MBM29LV (B) 320BE (W) 22F9h A-1 HZ HZ HZ HZ 0 0 0 1 0 Extend (B) 19h MBM29LV Device 320TE/BE (W) 0019h Code A-1 HZ HZ HZ HZ 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Sector Group Protection (B) : Byte mode (W) : Word mode HZ: High-Z 01h A-1/0 HZ HZ HZ 0 F6h MBM29LV (B) 320TE (W) 22F6h Device Code 12 Code DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 0 1 0 HZ HZ HZ 0 1 0 HZ HZ HZ MBM29LV320TE/BE80/90/10 ■ FLEXIBLE SECTOR-ERASE ARCHITECTURE Sector Address Table (MBM29LV320TE) Sector Address Sector A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Sector Size (Kbytes/ Kwords) ×8) (× Address Range ×16) (× Address Range SA0 0 0 0 0 0 0 X X X X 64/32 000000h to 00FFFFh 000000h to 007FFFh SA1 0 0 0 0 0 1 X X X X 64/32 010000h to 01FFFFh 008000h to 00FFFFh SA2 0 0 0 0 1 0 X X X X 64/32 020000h to 02FFFFh 010000h to 017FFFh SA3 0 0 0 0 1 1 X X X X 64/32 030000h to 03FFFFh 018000h to 01FFFFh SA4 0 0 0 1 0 0 X X X X 64/32 040000h to 04FFFFh 020000h to 027FFFh SA5 0 0 0 1 0 1 X X X X 64/32 050000h to 05FFFFh 028000h to 02FFFFh SA6 0 0 0 1 1 0 X X X X 64/32 060000h to 06FFFFh 030000h to 037FFFh SA7 0 0 0 1 1 1 X X X X 64/32 070000h to 07FFFFh 038000h to 03FFFFh SA8 0 0 1 0 0 0 X X X X 64/32 080000h to 08FFFFh 040000h to 047FFFh SA9 0 0 1 0 0 1 X X X X 64/32 090000h to 09FFFFh 048000h to 04FFFFh SA10 0 0 1 0 1 0 X X X X 64/32 0A0000h to 0AFFFFh 050000h to 057FFFh SA11 0 0 1 0 1 1 X X X X 64/32 0B0000h to 0BFFFFh 058000h to 05FFFFh SA12 0 0 1 1 0 0 X X X X 64/32 0C0000h to 0CFFFFh 060000h to 067FFFh SA13 0 0 1 1 0 1 X X X X 64/32 0D0000h to 0DFFFFh 068000h to 06FFFFh SA14 0 0 1 1 1 0 X X X X 64/32 0E0000h to 0EFFFFh 070000h to 077FFFh SA15 0 0 1 1 1 1 X X X X 64/32 0F0000h to 0FFFFFh 078000h to 07FFFFh SA16 0 1 0 0 0 0 X X X X 64/32 100000h to 10FFFFh 080000h to 087FFFh SA17 0 1 0 0 0 1 X X X X 64/32 110000h to 11FFFFh 088000h to 08FFFFh SA18 0 1 0 0 1 0 X X X X 64/32 120000h to 12FFFFh 090000h to 097FFFh SA19 0 1 0 0 1 1 X X X X 64/32 130000h to 13FFFFh 098000h to 09FFFFh SA20 0 1 0 1 0 0 X X X X 64/32 140000h to 14FFFFh 0A0000h to 0A7FFFh SA21 0 1 0 1 0 1 X X X X 64/32 150000h to 15FFFFh 0A8000h to 0AFFFFh SA22 0 1 0 1 1 0 X X X X 64/32 160000h to 16FFFFh 0B0000h to 0B7FFFh SA23 0 1 0 1 1 1 X X X X 64/32 170000h to 17FFFFh 0B8000h to 0BFFFFh SA24 0 1 1 0 0 0 X X X X 64/32 180000h to 18FFFFh 0C0000h to 0C7FFFh SA25 0 1 1 0 0 1 X X X X 64/32 190000h to 19FFFFh 0C8000h to 0CFFFFh SA26 0 1 1 0 1 0 X X X X 64/32 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh SA27 0 1 1 0 1 1 X X X X 64/32 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh SA28 0 1 1 1 0 0 X X X X 64/32 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh SA29 0 1 1 1 0 1 X X X X 64/32 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh SA30 0 1 1 1 1 0 X X X X 64/32 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh SA31 0 1 1 1 1 1 X X X X 64/32 1F0000h to 1FFFFFh 0F8000h to 0FFFFFh (Continued) 13 MBM29LV320TE/BE80/90/10 Sector Address Sector A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Sector Size (Kbytes/ Kwords) ×8) (× Address Range ×16) (× Address Range SA32 1 0 0 0 0 0 X X X X 64/32 200000h to 20FFFFh 100000h to 107FFFh SA33 1 0 0 0 0 1 X X X X 64/32 210000h to 21FFFFh 108000h to 10FFFFh SA34 1 0 0 0 1 0 X X X X 64/32 220000h to 22FFFFh 110000h to 117FFFh SA35 1 0 0 0 1 1 X X X X 64/32 230000h to 23FFFFh 118000h to 11FFFFh SA36 1 0 0 1 0 0 X X X X 64/32 240000h to 24FFFFh 120000h to 127FFFh SA37 1 0 0 1 0 1 X X X X 64/32 250000h to 25FFFFh 128000h to 12FFFFh SA38 1 0 0 1 1 0 X X X X 64/32 260000h to 26FFFFh 130000h to 137FFFh SA39 1 0 0 1 1 1 X X X X 64/32 270000h to 27FFFFh 138000h to 13FFFFh SA40 1 0 1 0 0 0 X X X X 64/32 280000h to 28FFFFh 140000h to 147FFFh SA41 1 0 1 0 0 1 X X X X 64/32 290000h to 29FFFFh 148000h to 14FFFFh SA42 1 0 1 0 1 0 X X X X 64/32 2A0000h to 2AFFFFh 150000h to 157FFFh SA43 1 0 1 0 1 1 X X X X 64/32 2B0000h to 2BFFFFh 158000h to 15FFFFh SA44 1 0 1 1 0 0 X X X X 64/32 2C0000h to 2CFFFFh 160000h to 167FFFh SA45 1 0 1 1 0 1 X X X X 64/32 2D0000h to 2DFFFFh 168000h to 16FFFFh SA46 1 0 1 1 1 0 X X X X 64/32 2E0000h to 2EFFFFh 170000h to 177FFFh SA47 1 0 1 1 1 1 X X X X 64/32 2F0000h to 2FFFFFh 178000h to 17FFFFh SA48 1 1 0 0 0 0 X X X X 64/32 300000h to 30FFFFh 180000h to 187FFFh SA49 1 1 0 0 0 1 X X X X 64/32 310000h to 31FFFFh 188000h to 18FFFFh SA50 1 1 0 0 1 0 X X X X 64/32 320000h to 32FFFFh 190000h to 197FFFh SA51 1 1 0 0 1 1 X X X X 64/32 330000h to 33FFFFh 198000h to 19FFFFh SA52 1 1 0 1 0 0 X X X X 64/32 340000h to 34FFFFh 1A0000h to 1A7FFFh SA53 1 1 0 1 0 1 X X X X 64/32 350000h to 35FFFFh 1A8000h to 1AFFFFh SA54 1 1 0 1 1 0 X X X X 64/32 360000h to 36FFFFh 1B0000h to 1B7FFFh SA55 1 1 0 1 1 1 X X X X 64/32 370000h to 37FFFFh 1B8000h to 1BFFFFh SA56 1 1 1 0 0 0 X X X X 64/32 380000h to 38FFFFh 1C0000h to 1C7FFFh SA57 1 1 1 0 0 1 X X X X 64/32 390000h to 39FFFFh 1C8000h to 1CFFFFh SA58 1 1 1 0 1 0 X X X X 64/32 3A0000h to 3AFFFFh 1D0000h to 1D7FFFh SA59 1 1 1 0 1 1 X X X X 64/32 3B0000h to 3BFFFFh 1D8000h to 1DFFFFh SA60 1 1 1 1 0 0 X X X X 64/32 3C0000h to 3CFFFFh 1E0000h to 1E7FFFh SA61 1 1 1 1 0 1 X X X X 64/32 3D0000h to 3DFFFFh 1E8000h to 1EFFFFh SA62 1 1 1 1 1 0 X X X X 64/32 3E0000h to 3EFFFFh 1F0000h to 1F7FFFh SA63 1 1 1 1 1 1 0 0 0 X 8/4 3F0000h to 3F1FFFh 1F8000h to 1F8FFFh SA64 1 1 1 1 1 1 0 0 1 X 8/4 3F2000h to 3F3FFFh 1F9000h to 1F9FFFh (Continued) 14 MBM29LV320TE/BE80/90/10 (Continued) Sector Address Sector A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Sector Size (Kbytes/ Kwords) ×8) (× Address Range ×16) (× Address Range SA65 1 1 1 1 1 1 0 1 0 X 8/4 3F4000h to 3F5FFFh 1FA000h to 1FAFFFh SA66 1 1 1 1 1 1 0 1 1 X 8/4 3F6000h to 3F7FFFh 1FB000h to 1FBFFFh SA67 1 1 1 1 1 1 1 0 0 X 8/4 3F8000h to 3F9FFFh 1FC000h to 1FCFFFh SA68 1 1 1 1 1 1 1 0 1 X 8/4 3FA000h to 3FBFFFh 1FD000h to 1FDFFFh SA69 1 1 1 1 1 1 1 1 0 X 8/4 3FC000h to 3FDFFFh 1FE000h to 1FEFFFh SA70 1 1 1 1 1 1 1 1 1 X 8/4 3FE000h to 3FFFFFh 1FF000h to 1FFFFFh Note : The address range is A20 : A-1 if in byte mode (BYTE = VIL) . The address range is A20 : A0 if in word mode (BYTE = VIH) . 15 MBM29LV320TE/BE80/90/10 Sector Address Table (MBM29LV320BE) Sector Address Sector A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Sector Size (Kbytes/ Kwords) ×8) (× Address Range ×16) (× Address Range SA70 1 1 1 1 1 1 X X X X 64/32 3F0000h to 3FFFFFh 1F8000h to 1FFFFFh SA69 1 1 1 1 1 0 X X X X 64/32 3E0000h to 3EFFFFh 1F0000h to 1F7FFFh SA68 1 1 1 1 0 1 X X X X 64/32 3D0000h to 3DFFFFh 1E8000h to 1EFFFFh SA67 1 1 1 1 0 0 X X X X 64/32 3C0000h to 3CFFFFh 1E0000h to 1E7FFFh SA66 1 1 1 0 1 1 X X X X 64/32 3B0000h to 3BFFFFh 1D8000h to 1DFFFFh SA65 1 1 1 0 1 0 X X X X 64/32 3A0000h to 3AFFFFh 1D0000h to 1D7FFFh SA64 1 1 1 0 0 1 X X X X 64/32 390000h to 39FFFFh 1C8000h to 1CFFFFh SA63 1 1 1 0 0 0 X X X X 64/32 380000h to 38FFFFh 1C0000h to 1C7FFFh SA62 1 1 0 1 1 1 X X X X 64/32 370000h to 37FFFFh 1B8000h to 1BFFFFh SA61 1 1 0 1 1 0 X X X X 64/32 360000h to 36FFFFh 1B0000h to 1B7FFFh SA60 1 1 0 1 0 1 X X X X 64/32 350000h to 35FFFFh 1A8000h to 1AFFFFh SA59 1 1 0 1 0 0 X X X X 64/32 340000h to 34FFFFh 1A0000h to 1A7FFFh SA58 1 1 0 0 1 1 X X X X 64/32 330000h to 33FFFFh 198000h to 19FFFFh SA57 1 1 0 0 1 0 X X X X 64/32 320000h to 32FFFFh 190000h to 197FFFh SA56 1 1 0 0 0 1 X X X X 64/32 310000h to 31FFFFh 188000h to 18FFFFh SA55 1 1 0 0 0 0 X X X X 64/32 300000h to 30FFFFh 180000h to 187FFFh SA54 1 0 1 1 1 1 X X X X 64/32 2F0000h to 2FFFFFh 178000h to 17FFFFh SA53 1 0 1 1 1 0 X X X X 64/32 2E0000h to 2EFFFFh 170000h to 177FFFh SA52 1 0 1 1 0 1 X X X X 64/32 2D0000h to 2DFFFFh 168000h to 16FFFFh SA51 1 0 1 1 0 0 X X X X 64/32 2C0000h to 2CFFFFh 160000h to 167FFFh SA50 1 0 1 0 1 1 X X X X 64/32 2B0000h to 2BFFFFh 158000h to 15FFFFh SA49 1 0 1 0 1 0 X X X X 64/32 2A0000h to 2AFFFFh 150000h to 157FFFh SA48 1 0 1 0 0 1 X X X X 64/32 290000h to 29FFFFh 148000h to 14FFFFh SA47 1 0 1 0 0 0 X X X X 64/32 280000h to 28FFFFh 140000h to 147FFFh SA46 1 0 0 1 1 1 X X X X 64/32 270000h to 27FFFFh 138000h to 13FFFFh SA45 1 0 0 1 1 0 X X X X 64/32 260000h to 26FFFFh 130000h to 137FFFh SA44 1 0 0 1 0 1 X X X X 64/32 250000h to 25FFFFh 128000h to 12FFFFh SA43 1 0 0 1 0 0 X X X X 64/32 240000h to 24FFFFh 120000h to 127FFFh SA42 1 0 0 0 1 1 X X X X 64/32 230000h to 23FFFFh 118000h to 11FFFFh SA41 1 0 0 0 1 0 X X X X 64/32 220000h to 22FFFFh 110000h to 117FFFh SA40 1 0 0 0 0 1 X X X X 64/32 210000h to 21FFFFh 108000h to 10FFFFh SA39 1 0 0 0 0 0 X X X X 64/32 200000h to 20FFFFh 100000h to 107FFFh SA38 0 1 1 1 1 1 X X X X 64/32 1F0000h to 1FFFFFh 0F8000h to 0FFFFFh (Continued) 16 MBM29LV320TE/BE80/90/10 Sector Address Sector A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Sector Size (Kbytes/ Kwords) ×8) (× Address Range ×16) (× Address Range SA37 0 1 1 1 1 0 X X X X 64/32 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh SA36 0 1 1 1 0 1 X X X X 64/32 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh SA35 0 1 1 1 0 0 X X X X 64/32 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh SA34 0 1 1 0 1 1 X X X X 64/32 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh SA33 0 1 1 0 1 0 X X X X 64/32 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh SA32 0 1 1 0 0 1 X X X X 64/32 190000h to 19FFFFh 0C8000h to 0CFFFFh SA31 0 1 1 0 0 0 X X X X 64/32 180000h to 18FFFFh 0C0000h to 0C7FFFh SA30 0 1 0 1 1 1 X X X X 64/32 170000h to 17FFFFh 0B8000h to 0BFFFFh SA29 0 1 0 1 1 0 X X X X 64/32 160000h to 16FFFFh 0B0000h to 0B7FFFh SA28 0 1 0 1 0 1 X X X X 64/32 150000h to 15FFFFh 0A8000h to 0AFFFFh SA27 0 1 0 1 0 0 X X X X 64/32 140000h to 14FFFFh 0A0000h to 0A7FFFh SA26 0 1 0 0 1 1 X X X X 64/32 130000h to 13FFFFh 098000h to 09FFFFh SA25 0 1 0 0 1 0 X X X X 64/32 120000h to 12FFFFh 090000h to 097FFFh SA24 0 1 0 0 0 1 X X X X 64/32 110000h to 11FFFFh 088000h to 08FFFFh SA23 0 1 0 0 0 0 X X X X 64/32 100000h to 10FFFFh 080000h to 087FFFh SA22 0 0 1 1 1 1 X X X X 64/32 0F0000h to 0FFFFFh 078000h to 07FFFFh SA21 0 0 1 1 1 0 X X X X 64/32 0E0000h to 0EFFFFh 070000h to 077FFFh SA20 0 0 1 1 0 1 X X X X 64/32 0D0000h to 0DFFFFh 068000h to 06FFFFh SA19 0 0 1 1 0 0 X X X X 64/32 0C0000h to 0CFFFFh 060000h to 067FFFh SA18 0 0 1 0 1 1 X X X X 64/32 0B0000h to 0BFFFFh 058000h to 05FFFFh SA17 0 0 1 0 1 0 X X X X 64/32 0A0000h to 0AFFFFh 050000h to 057FFFh SA16 0 0 1 0 0 1 X X X X 64/32 090000h to 09FFFFh 048000h to 04FFFFh SA15 0 0 1 0 0 0 X X X X 64/32 080000h to 08FFFFh 040000h to 047FFFh SA14 0 0 0 1 1 1 X X X X 64/32 070000h to 07FFFFh 038000h to 03FFFFh SA13 0 0 0 1 1 0 X X X X 64/32 060000h to 06FFFFh 030000h to 037FFFh SA12 0 0 0 1 0 1 X X X X 64/32 050000h to 05FFFFh 028000h to 02FFFFh SA11 0 0 0 1 0 0 X X X X 64/32 040000h to 04FFFFh 020000h to 027FFFh SA10 0 0 0 0 1 1 X X X X 64/32 030000h to 03FFFFh 018000h to 01FFFFh SA9 0 0 0 0 1 0 X X X X 64/32 020000h to 02FFFFh 010000h to 017FFFh SA8 0 0 0 0 0 1 X X X X 64/32 010000h to 01FFFFh 008000h to 00FFFFh SA7 0 0 0 0 0 0 1 1 1 X 8/4 00E000h to 00FFFFh 007000h to 007FFFh SA6 0 0 0 0 0 0 1 1 0 X 8/4 00C000h to 00DFFFh 006000h to 006FFFh SA5 0 0 0 0 0 0 1 0 1 X 8/4 00A000h to 00BFFFh 005000h to 005FFFh (Continued) 17 MBM29LV320TE/BE80/90/10 (Continued) Sector Address Sector A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Sector Size (Kbytes/ Kwords) ×8) (× Address Range ×16) (× Address Range SA4 0 0 0 0 0 0 1 0 0 X 8/4 008000h to 009FFFh 004000h to 004FFFh SA3 0 0 0 0 0 0 0 1 1 X 8/4 006000h to 007FFFh 003000h to 003FFFh SA2 0 0 0 0 0 0 0 1 0 X 8/4 004000h to 005FFFh 002000h to 002FFFh SA1 0 0 0 0 0 0 0 0 1 X 8/4 002000h to 003FFFh 001000h to 001FFFh SA0 0 0 0 0 0 0 0 0 0 X 8/4 000000h to 001FFFh 000000h to 000FFFh Note : The address range is A20 : A-1 if in byte mode (BYTE = VIL) . The address range is A20 : A0 if in word mode (BYTE = VIH) . 18 MBM29LV320TE/BE80/90/10 Sector Group Address Table (MBM29LV320TE) (Top Boot Block) Sector Group A20 A19 A18 A17 A16 A15 A14 A13 A12 Sectors SGA0 0 0 0 0 X X X X X SA0 to SA3 SGA1 0 0 0 1 X X X X X SA4 to SA7 SGA2 0 0 1 0 X X X X X SA8 to SA11 SGA3 0 0 1 1 X X X X X SA12 to SA15 SGA4 0 1 0 0 X X X X X SA16 to SA19 SGA5 0 1 0 1 X X X X X SA20 to SA23 SGA6 0 1 1 0 X X X X X SA24 to SA27 SGA7 0 1 1 1 X X X X X SA28 to SA31 SGA8 1 0 0 0 X X X X X SA32 to SA35 SGA9 1 0 0 1 X X X X X SA36 to SA39 SGA10 1 0 1 0 X X X X X SA40 to SA43 SGA11 1 0 1 1 X X X X X SA44 to SA47 SGA12 1 1 0 0 X X X X X SA48 to SA51 SGA13 1 1 0 1 X X X X X SA52 to SA55 SGA14 1 1 1 0 X X X X X SA56 to SA59 0 0 0 1 X X X SA60 to SA62 1 0 SGA15 1 1 1 1 SGA16 1 1 1 1 1 1 0 0 0 SA63 SGA17 1 1 1 1 1 1 0 0 1 SA64 SGA18 1 1 1 1 1 1 0 1 0 SA65 SGA19 1 1 1 1 1 1 0 1 1 SA66 SGA20 1 1 1 1 1 1 1 0 0 SA67 SGA21 1 1 1 1 1 1 1 0 1 SA68 SGA22 1 1 1 1 1 1 1 1 0 SA69 SGA23 1 1 1 1 1 1 1 1 1 SA70 19 MBM29LV320TE/BE80/90/10 Sector Group Address Table (MBM29LV320BE) (Bottom Boot Block) Sector Group A20 A19 A18 A17 A16 A15 A14 A13 A12 Sectors SGA0 0 0 0 0 0 0 0 0 0 SA0 SGA1 0 0 0 0 0 0 0 0 1 SA1 SGA2 0 0 0 0 0 0 0 1 0 SA2 SGA3 0 0 0 0 0 0 0 1 1 SA3 SGA4 0 0 0 0 0 0 1 0 0 SA4 SGA5 0 0 0 0 0 0 1 0 1 SA5 SGA6 0 0 0 0 0 0 1 1 0 SA6 SGA7 0 0 0 0 0 0 1 1 1 SA7 0 1 1 0 X X X SA8 to SA10 1 1 SGA8 20 0 0 0 0 SGA9 0 0 0 1 X X X X X SA11 to SA14 SGA10 0 0 1 0 X X X X X SA15 to SA18 SGA11 0 0 1 1 X X X X X SA19 to SA22 SGA12 0 1 0 0 X X X X X SA23 to SA26 SGA13 0 1 0 1 X X X X X SA27 to SA30 SGA14 0 1 1 0 X X X X X SA31 to SA34 SGA15 0 1 1 1 X X X X X SA35 to SA38 SGA16 1 0 0 0 X X X X X SA39 to SA42 SGA17 1 0 0 1 X X X X X SA43 to SA46 SGA18 1 0 1 0 X X X X X SA47 to SA50 SGA19 1 0 1 1 X X X X X SA51 to SA54 SGA20 1 1 0 0 X X X X X SA55 to SA58 SGA21 1 1 0 1 X X X X X SA59 to SA62 SGA22 1 1 1 0 X X X X X SA63 to SA66 SGA23 1 1 1 1 X X X X X SA67 to SA70 MBM29LV320TE/BE80/90/10 Common Flash Memory Interface Code Table Description A6 to A0 DQ15 to DQ0 Query-unique ASCII string “QRY” 10h 11h 12h 0051h 0052h 0059h Primary OEM Command Set 02h : AMD/FJ standard type 13h 14h 0002h 0000h Address for Primary Extended Table 15h 16h 0040h 0000h Alternate OEM Command Set (00h = not applicable) 17h 18h 0000h 0000h Address for Alternate OEM Extended Table 19h 1Ah 0000h 0000h VCC Min (write/erase) DQ7 to DQ4 : 1 V/bit, DQ3 to DQ0 : 100 mV/bit 1Bh 0027h VCC Max (write/erase) DQ7 to DQ4 : 1 V/bit, DQ3 to DQ0 : 100 mV/bit 1Ch 0036h VPP Min voltage 1Dh 0000h 1Eh 0000h Typical timeout per single byte/word write 2 µs 1Fh 0004h Typical timeout for Min size buffer write 2N µs 20h 0000h Typical timeout per individual block erase 2N ms 21h 000Ah Typical timeout for full chip erase 2 ms 22h 0000h Max timeout for byte/word write 2N times typical 23h 0005h Max timeout for buffer write 2N times typical 24h 0000h Max timeout per individual block erase 2 times typical 25h 0004h Max timeout for full chip erase 2N times typical 26h 0000h Device Size = 2N byte 27h 0016h Flash Device Interface description 28h 29h 0002h 0000h Max number of byte in multi-byte write = 2N 2Ah 2Bh 0000h 0000h Number of Erase Block Regions within device 2Ch 0002h Erase Block Region 1 Information 2Dh 2Eh 2Fh 30h 0007h 0000h 0020h 0000h Erase Block Region 2 Information 31h 32h 33h 34h 003Eh 0000h 0000h 0001h VPP Max voltage N N N (Continued) 21 MBM29LV320TE/BE80/90/10 (Continued) Description 22 A6 to A0 DQ15 to DQ0 Query-unique ASCII string “PRI” 40h 41h 42h 0050h 0052h 0049h Major version number, ASCII 43h 0031h Minor version number, ASCII 44h 0031h Address Sensitive Unlock 00h = Required 01h = Not Required 45h 0000h Erase Suspend 00h = Not Supported 01h = To Read Only 02h = To Read & Write 46h 0002h Sector Group Protection 00h = Not Supported X = Number of sectors in per group 47h 0004h Sector Group Temporary Unprotection 00h = Not Supported 01h = Supported 48h 0001h Sector Group Protection Algorithm 49h 0004h Number of Sector for Bank 2 00h = Not Supported 4Ah 0000h Burst Mode Type 00h = Not Supported 4Bh 0000h Page Mode Type 00h = Not Supported 4Ch 0000h VACC (Acceleration) Supply Minimum 00h = Not Supported, DQ7 to DQ4 : 1 V/bit, DQ3 to DQ0 : 100 mV/bit 4Dh 00B5h VACC (Acceleration) Supply Maximum 00h = Not Supported, DQ7 to DQ4 : 1 V/bit, DQ3 to DQ0 : 100 mV/bit 4Eh 00C5h Boot Type 02h = MBM29LV320BE 03h = MBM29LV320TE 4Fh 00XXh MBM29LV320TE/BE80/90/10 ■ FUNCTIONAL DESCRIPTION 1. Read Mode The device has two control functions which must be satisfied in order to obtain data at the outputs. CE is the power control and should be used for a device selection. OE is the output control and should be used to gate data to the output pins if a device is selected. Address access time (tACC) is equal to delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the addresses have been stable for at least tACC-tOE time.) When reading out data without changing addresses after power-up, it is necessary to input hardware reset or to change CE pin from “H” or “L”. 2. Standby Mode There are two ways to implement the standby mode on the device, one using both the CE and RESET pins; the other via the RESET pin only. When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC ± 0.3 V. Under this condition the current consumed is less than 5 µA Max During Embedded Algorithm operation, VCC active current (ICC2) is required even CE = “H”. The device can be read with standard access time (tCE) from either of these standby modes. When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS ± 0.3 V (CE = “H” or “L”) . Under this condition the current consumed is less than 5 µA Max Once the RESET pin is taken high, the device requires tRH as wake up time for outputs to be valid for read access. In the standby mode the outputs are in the high impedance state, independently of the OE input. 3. Automatic Sleep Mode There is a function called automatic sleep mode to restrain power consumption during read-out of the device data. This mode can be useful in the application such as a handy terminal which requires low power consumption. To activate this mode, the device automatically switches themselves to low power mode when the device addresses remain stable during access time of 150 ns. It is not necessary to control CE, WE, and OE on the mode. Under the mode, the current consumed is typically 1 µA (CMOS Level) . During simultaneous operation, VCC active current (ICC2) is required. Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed, the mode is canceled automatically, and the device read the data for changed addresses. 4. Output Disable With the OE input at a logic high level (VIH) , output from the device is disabled. This will cause the output pins to be in a high impedance state. 5. Autoselect The autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device. To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two identifier bytes may then be sequenced from the device outputs by toggling address A0 from VIL to VIH. All addresses are DON’T CARES except A6, A1, and A0 (A-1) . (See “MBM29LV320TE/BE User Bus Operations Tables (BYTE = VIH and BYTE = VIL)” in ■DEVICE BUS OPERATIONS.) The manufacturer and device codes may also be read via the command register, for instances when the device is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in “MBM29LV320TE/BE Command Definitions Table” (■DEVICE BUS OPERATIONS) (See “2. Autoselect Command” in ■COMAND DIFINITIONS) . 23 MBM29LV320TE/BE80/90/10 Word 0 (A0 = VIL) represents the manufacturer’s code (Fujitsu = 04h) and word 1 (A0 = VIH) represents the device identifier code. Word 3 (A1 = A0 = VIH) represents the extended device code. These three bytes/words are given in “MBM29LV320TE/BE Sector Group Protection Verify Autoselect Codes Table”and “Expanded Autoselect Code Table“ (■DEVICE BUS OPERATIONS) . In order to read the proper device codes when executing the autoselect, A1 must be VIL. (See “MBM29LV320TE/BE Sector Group Protection Verify Autoselect Codes Table” and “Expanded Autoselect Code Table“ in ■DEVICE BUS OPERATIONS.) 6. Write The device erasure and programming are accomplished via the command register. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE, whichever happens first. Standard microprocessor write timings are used. See “Read Only Operation Characteristics” in ■AC CHARACTERISTICS for specific timing parameters. 7. Sector Group Protection The device features hardware sector group protection. This feature will disable both program and erase operations in any combination of twenty five sector groups of memory. (See “Sector Group Address Tables (MBM29LV320TE/BE)” in ■FLEXIBLE SECTOR-ERASE ARCHITECTURE). The sector group protection feature is enabled using programming equipment at the user’s site. The device is shipped with all sector groups unprotected. To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest VID = 11.5 V) , CE = VIL and A6 = A0 = VIL, A1 = VIH. The sector group addresses (A20, A19, A18, A17, A16, A15, A14, A13, and A12) should be set to the sector to be protected. “Sector Address Tables (MBM29LV320TE/BE)” in ■FLEXIBLE SECTOR-ERASE ARCHITECTURE define the sector address for each of the seventy one (71) individual sectors, and “Sector Group Address Tables (MBM29LV320TE/BE)” in ■FLEXIBLE SECTOR-ERASE ARCHITECTURE define the sector group address for each of the twenty five (25) individual group sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. Sector group addresses must be held constant during the WE pulse. See “14. Sector Group Protection Timing Diagram” in ■TIMING DIAGRAM and “5. Sector Group Protection Algorithm” in ■FLOW CHART for sector group protection waveforms and algorithm. To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9 with CE and OE at VIL and WE at VIH. Scanning the sector group addresses (A20, A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” code at device output DQ0 for a protected sector. Otherwise the device will produce “0” for unprotected sector. In this mode, the lower order addresses, except for A0, A1, and A6 are DON’T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes. A-1 requires to apply to VIL on byte mode. It is also possible to determine if a sector group is protected in the system by writing an Autoselect command. Performing a read operation at the address location XX02h, where the higher order addresses (A20, A19, A18, A17, A16, A15, A14, A13, and A12) are the desired sector group address will produce a logical “1” at DQ0 for a protected sector group. See “MBM29LV320TE/BE Sector Group Protection Verify Autoselect Codes Table” and “Expanded Autoselect Code Table” in ■DEVICE BUS OPERATIONS for Autoselect codes. 8. Temporary Sector Group Unprotection This feature allows temporary unprotection of previously protected sector groups of the device in order to change data. The Sector Group Unprotection mode is activated by setting the RESET pin to high voltage (VID) . During this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. Once the VID is taken away from the RESET pin, all the previously protected sector groups will be protected again. See “15. Temporary Sector Group Unprotection Timing Diagram” in ■TIMING DIAGRAM and “6. Temporary Sector Group Unprotection Algorithm” in ■FLOW CHART. 24 MBM29LV320TE/BE80/90/10 9. Extended Sector Group Protection In addition to normal sector group protection, the device has Extended Sector Group Protection as extended function. This function enables to protect sector group by forcing VID on RESET pin and write a command sequence. Unlike conventional procedure, it is not necessary to force VID and control timing for control pins. The only RESET pin requires VID for sector group protection in this mode. The extended sector group protection requires VID on RESET pin. With this condition, the operation is initiated by writing the set-up command (60h) into the command register. Then, the sector group addresses pins (A20, A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set to the sector group to be protected (recommend to set VIL for the other addresses pins) , and write extended sector group protection command (60h) . A sector group is typically protected in 250 µs. To verify programming of the protection circuitry, the sector group addresses pins (A20, A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set and write a command (40h) . Following the command write, a logical “1” at device output DQ0 will produce for protected sector in the read operation. If the output is logical “0”, please repeat to write extended sector group protection command (60h) again. To terminate the operation, it is necessary to set RESET pin to VIH. (See “16. Extended Sector Group Protection Timing Diagram” in ■TIMING DIAGRAM and “7. Extended Sector Group Protection Algorithm” in ■FLOW CHART.) 10. RESET Hardware Reset The device may be reset by driving the RESET pin to VIL. The RESET pin has a pulse requirement and has to be kept low (VIL) for at least “tRP” in order to properly reset the internal state machine. Any operation in the process of being executed will be terminated and the internal state machine will be reset to the read mode “tREADY” after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the device requires an additional “tRH” before it will allow read access. When the RESET pin is low, the device will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please note that the RY/BY output signal should be ignored during the RESET pulse. See “10. RESET, RY/BY Timing Diagram” in ■TIMING DIAGRAM for the timing diagram. See “8. Temporary Sector Group Unprotection” for additional functionality. 11. Boot Block Sector Protection The Write Protection function provides a hardware method of protecting certain boot sectors without using VID. This function is one of two provided by the WP/ACC pin. If the system asserts VIL on the WP/ACC pin, the device disables program and erase functions in the two “outermost” 8 K byte boot sectors independently of whether those sectors are protected or unprotected using the method described in “Sector Protection/Unprotection”. The two outermost 8 K byte boot sectors are the two sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-congfigured device. (MBM29LV320TE : SA69 and SA70, MBM29LV320BE : SA0 and SA1) If the system asserts VIH on the WP/ACC pin, the device reverts to whether the two outermost 8 K byte boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in “Sector protection/unprotection”. 12. Accelerated Program Operation The device offers accelerated program operation which enables the programming in high speed. If the system asserts VACC to the WP/ACC pin, the device automatically enters the acceleration mode and the time required for program operation will reduce to about 60%. This function is primarily intended to allow high speed program, so caution is needed as the sector group will temporarily be unprotected. The system would use a fast program command sequence when programming during acceleration mode. Set command to fast mode and reset command from fast mode are not necessary. When the device enters the acceleration mode, the device automatically set to fast mode. Therefore, the pressent sequence could be used for programming and detection of completion during acceleration mode. Removing VACC from the WP/ACC pin returns the device to normal operation. Do not remove VACC from WP/ ACC pin while programming. See “17. Accelerated Program Timing Diagram” in ■TIMING DIAGRAM. 25 MBM29LV320TE/BE80/90/10 ■ COMMAND DEFINITIONS The device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. “MBM29LV320TE/BE Command Definitions Table” in ■DEVICE BUS OPERATIONS defines the valid register command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only while the Sector Erase operation is in progress. Moreover both Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that commands are always written at DQ7 to DQ0 and DQ15 to DQ8 bits are ignored. 1. Read/Reset Command In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to Read/Reset mode, the Read/ Reset operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remain enabled for reads until the command register contents are altered. The device will automatically power-up in the Read/Reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. See “■AC CHARACTERISTICS” for the specific timing parameters. 2. Autoselect Command Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacture and device codes must be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto the address lines is not generally desired system design practice. The device contains an Autoselect command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the Autoselect command sequence into the command register. Following the command write, a read cycle from address (XX) 00h retrieves the manufacture code of 04h. A read cycle from address (XX) 01h for ×16 ( (XX) 02h for ×8) returns the device code. A read cycle from address (XX) 03h for ×16 ( (XX) 06h for ×8) returns the extended device code. (See “MBM29LV320TE/BE Sector Group Protection Verify Autoselect Codes Table” and “Expanded Autoselect Code Table” in ■DEVICE BUS OPERATIONS.) The sector state (protection or unprotection) will be informed by address (XX) 02h for ×16 ( (XX) 04h for ×8) . Scanning the sector group addresses (A20, A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” at device output DQ0 for a protected sector group. The programming verification should be performed by verify sector group protection on the protected sector. (See “MBM29LV320TE/BE User Bus Operations Tables (BYTE = VIH and BYTE = VIL)” in ■DEVICE BUS OPERATIONS.) To terminate the operation, it is necessary to write the Read/Reset command sequence into the register. To execute the Autoselect command during the operation, writing Read/Reset command sequence must precede the Autoselect command. 3. Byte/Word Programming The device is programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation. There are two “unlock” write cycles. These are followed by the program set-up command and data write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. The system can determine the status of the program operation by using DQ7 (Data Polling) , DQ6 (Toggle Bit) , or RY/BY. The Data Polling and Toggle Bit must be performed at the memory location which is being programmed. 26 MBM29LV320TE/BE80/90/10 The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this bit at which time the device return to the read mode and addresses are no longer latched. (See “Hardware Sequence Flags Table”.) Therefore, the device requires that a valid address to the device be supplied by the system at this particular instance of time. Hence, Data Polling must be performed at the memory location which is being programmed. Any commands written to the chip during this period will be ignored. If hardware reset occurs during the programming operation, it is impossible to guarantee the data are being written. Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from Read/Reset mode will show that the data is still “0”. Only erase operations can convert “0”s to “1”s. “1. Embedded ProgramTM Algorithm” in ■FLOW CHART illustrates the Embedded ProgramTM Algorithm using typical command strings and bus operations. 4. Chip Erase Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the “set-up” command. Two more “unlock” write cycles are then followed by the chip erase command. Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase Algorithm command sequence the device will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase (Preprogram function) . The system is not required to provide any controls or timings during these operations. The system can determine the status of the erase operation by using DQ7 (Data Polling) , DQ6 (Toggle Bit) , or RY/BY. The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command sequence and terminates when the data on DQ7 is “1” (See “12. Write Operation Status”.) at which time the device returns to read the mode. Chip Erase Time; Sector Erase Time × All sectors + Chip Program Time (Preprogramming) “2. Embedded EraseTM Algorithm” in ■FLOW CHART illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations. 5. Sector Erase Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the “set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector address (any address location within the desired sector) is latched on the falling edge of CE or WE whichever happens later, while the command (Data = 30h) is latched on the rising edge of CE or WE which happens first. After time-out of “tTOW” from the rising edge of the last sector erase command, the sector erase operation will begin. Multiple sectors may be erased concurrently by writing the six bus cycle operations on “MBM29LV320TE/BE Command Definitions Table” in ■DEVICE BUS OPERATIONS. This sequence is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must be less than “tTOW” otherwise that command will not be accepted and erasure will not start. It is recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of “tTOW” from the rising edge of last CE or WE whichever happens first will initiate the execution of the Sector Erase command(s). If another falling edge of CE or WE, whichever happens first occurs within the “tTOW” time-out window the timer is reset. (Monitor DQ3 to determine if the sector erase timer window is still open, see “16. DQ3”, Sector Erase Timer.) Any command other than Sector Erase or Erase Suspend during this time-out period will reset the device to the read mode, ignoring the previous command string. Resetting the device once execution has begun will corrupt the data in the sector. In that case, restart the erase on those sectors and allow them to complete. (See “12. Write Operation Status” for Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 70) . Sector erase does not require the user to program the device prior to erase. The device automatically program all memory locations in the sector (s) to be erased prior to electrical erase (Preprogram function) . When erasing 27 MBM29LV320TE/BE80/90/10 a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. The system can determine the status of the erase operation by using DQ7 (Data Polling) , DQ6 (Toggle Bit) , or RY/BY. The sector erase begins after the “tTOW” time out from the rising edge of CE or WE whichever happens first for the last sector erase command pulse and terminates when the data on DQ7 is “1” (See “12. Write Operation Status”.) at which time the device return to the read mode. Data polling and Toggle Bit must be performed at an address within any of the sectors being erased. Multiple Sector Erase Time; [Sector Erase Time + Sector Program Time (Preprogramming) ] × Number of Sector Erase “2. Embedded EraseTM Algorithm” in ■FLOW CHART illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations. 6. Erase Suspend/Resume The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if written during the Chip Erase operation or Embedded Program Algorithm. Writting the Erase Suspend command (B0h) during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase operation. Writing the Erase Resume command (30h) resumes the erase operation. The addresses are “DON’T CARES” when writing the Erase Suspend or Erase Resume command. When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum of “tSPD” to suspend the erase operation. When the device has entered the erase-suspended mode, the RY/BY output pin will be at Hi-Z and the DQ7 bit will be at logic “1”, and DQ6 will stop toggling. The user must use the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further writes of the Erase Suspend command are ignored. When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause DQ2 to toggle. (See “17. DQ2”.) After entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for Program. This program mode is known as the erase-suspend-program mode. Again, programming in this mode is the same as programming in the regular Program mode except that the data must be programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector while the device is in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erase-suspended Program operation is detected by the RY/BY output pin, Data polling of DQ7 or by the Toggle Bit I (DQ6) which is the same as the regular Program operation. Note that DQ7 must be read from the Program address while DQ6 can be read from any address. To resume the operation of Sector Erase, the Resume command (30h) should be written. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip has resumed erasing. 7. Extended Command (1) Fast Mode The device has Fast Mode function. This mode dispenses with the initial two unclock cycles required in the standard program command sequence by writing Fast Mode command into the command register. In this mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program command. (Do not write erase command in this mode.) The read operation is also executed after exiting this mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command register. (See “8. Embedded ProgramTM Algorithm for Fast Mode” in ■FLOW CHART .) The VCC active current is required even CE = VIH during Fast Mode. 28 MBM29LV320TE/BE80/90/10 (2) Fast Programming During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD) . (See “8. Embedded ProgramTM Algorithm for Fast Mode” in ■FLOW CHART.) (3) CFI (Common Flash Memory Interface) The CFI (Common Flash Memory Interface) specification outlines device and host system software interrogation handshake which allows specific vendor-specified software algorithms to be used for entire families of device. This allows device-independent, JEDEC ID-independent, and forward-and backward-compatible software support for the specified flash device families. See “Common Flash Memory Interface Code Table” in ■FLEXIBLE SECTOR-ERASE ARCHITECTURE for details. The operation is initiated by writing the query command (98h) into the command register. Following the command write, a read cycle from specific address retrives device information. Please note that output data of upper byte (DQ15 to DQ8) is “0” in word mode (16 bit) read. See “Common Flash Memory Interface Code Table” in ■FLEXIBLE SECTOR-ERASE ARCHITECTURE. To terminate operation, it is necessary to write the read/reset command sequence into the register. (See “Common Flash Memory Interface Code Table” in ■FLEXIBLE SECTORERASE ARCHITECTURE.) 8. Hidden ROM (Hi-ROM) Region The Hi-ROM feature provides a Flash memory region that the system may access through a new command sequence. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the device with the ESN protected against modification. Once the Hi-ROM region is protected, any further modification of that region is impossible. This ensures the security of the ESN once the product is shipped to the field. The Hi-ROM region is 256 bytes in length and is stored at the same address of the “outermost” 8 K byte boot sector. The MBM29LV320TE occupies the address of the byte mode 3FFFC0h to 3FFFFFh (word mode 1FFFE0h to 1FFFFFh) and the MBM29LV320BE type occupies the address of the byte mode 000000h to 000080h (word mode 000000h to 000040h) . After the system has written the Enter Hi-ROM command sequence, the system may read the Hi-ROM region by using the addresses normally occupied by the boot sector. That is, the device sends all commands that would normally be sent to the boot sector to the Hi-ROM region. This mode of operation continues until the system issues the Exit Hi-ROM command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the boot sector. 9. Hidden ROM (Hi-ROM) Entry Command The device has a Hidden ROM area with One Time Protect function. This area is to enter the security code and to unable the change of the code once set. Program/erase is possible in this area until it is protected. However, once it is protected, it is impossible to unprotect, so please use this with caution. Hidden ROM area is 256 byte and in the same address area of “outermost” 8 K byte boot block. Therefore, write the Hidden ROM entry command sequence to enter the Hidden ROM area. It is called as Hidden ROM mode when the Hidden ROM area appears. Sector other than the boot block area could be read during Hidden ROM mode. Read/program of the Hidden ROM area is possible during Hidden ROM mode. Write the Hidden ROM reset command sequence to exit the Hidden ROM mode. 10. Hidden ROM (Hi-ROM) Program Command To program the data to the Hidden ROM area, write the Hidden ROM program command sequence during Hidden ROM mode. This command is the same as the program command in usual except to write the command during Hidden ROM mode. Therefore the detection of completion method is the same as in the past, using the DQ7 data poling, DQ6 toggle bit and RY/BY pin. Need to pay attention to the address to be programmed. If the address other than the Hidden ROM area is selected to program, data of the address will be changed. Please note that the sector erase command is prohibited during Hidden ROM mode. If the sector erase command is appeared in this mode, data of the address will be erased. 29 MBM29LV320TE/BE80/90/10 11. Hidden ROM (Hi-ROM) Protect Command There are two methods to protect the Hidden ROM area. One is to write the sector group protect setup command (60h) , set the sector address in the Hidden ROM area and (A6, A1, A0) = (0,1,0) , and write the sector group protect command (60h) during the Hidden ROM mode. The same command sequence could be used because it is the same as the extension sector group protect in the past except that it is in the Hidden ROM mode and it does not apply high voltage to RESET pin. Please see “9. Extended Sector Group Protection” in ■FUNCTIONAL DESCRIPTION for details of extention sector group protect setting. The other is to apply high voltage (VID) to A9 and OE, set the sector address in the Hidden ROM area and (A6, A1, A0) = (0,1,0) , and apply the write pulse during the Hidden ROM mode. To verify the protect circuit, apply high voltage (VID) to A9, specify (A6, A1, A0) = (0,1,0) and the sector address in the Hidden ROM area, and read. When “1” appears on DQ0, the protect setting is completed. “0” will appear on DQ0 if it is not protected. Please apply write pulse agian. The same command sequence could be used for the above method because other than the Hidden ROM mode, it is the same as the sector group protect in the past. Please see “7. Sector Group Protection” in ■FUNCTIONAL DESCRIPTION for details of the sector group protect setting. Other sector group will be effected if the address other than those for Hidden ROM area is selected for the sector group address, so please be carefull. Once it is protected, protection can not be cancelled, so please pay the closest attention. 12. Write Operation Status Details in “Hardware Sequence Flags Table” are all the status flags that can be used to check the status of the device for current mode operation. During sector erase, the part provides the status flags automatically to the I/O ports. The information on DQ2 is address sensitive. This means that if an address from an erasing sector is consecutively read, then the DQ2 bit will toggle. However, DQ2 will not toggle if an address from a non-erasing sector is consecutively read. This allows users to determine which sectors are in erase. Once erase suspend is entered, address sensitivity still applies. If the address of a non-erasing sector (that is, one available for read) is provided, then stored data can be read from the device. If the address of an erasing sector (that is, one unavailable for read) is applied, the device will output its status bits. Hardware Sequence Flags Table DQ7 DQ6 DQ5 DQ3 DQ2 DQ7 Toggle 0 0 1 0 Toggle 0 1 Toggle * 1 1 0 0 Toggle Erase Suspend Read (Non-Erase Suspended Sector) Data Data Data Data Data Erase Suspend Program (Non-Erase Suspended Sector) DQ7 Toggle 0 0 1* DQ7 Toggle 1 0 1 0 Toggle 1 1 N/A DQ7 Toggle 1 0 N/A Status Embedded Program Algorithm Embedded Erase Algorithm In Progress Erase Suspend Read (Erase Suspended Sector) Erase Suspended Mode Embedded Program Algorithm Exceeded Time Limits Embedded Erase Algorithm Erase Suspended Mode Erase Suspend Program (Non-Erase Suspended Sector) *: Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle. Reading from non-erase suspend sector address will indicate logic “1” at the DQ2 bit. 30 MBM29LV320TE/BE80/90/10 13. DQ7 Data Polling The device features Data Polling as a method to indicate to the host that the Embedded Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the device will produce a complement of data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read device will produce true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read device will produce a “0” at the DQ7 output. Upon completion of the Embedded Erase Algorithm an attempt to read device will produce a “1” on DQ7. The flowchart for Data Polling (DQ7) is shown in “3. Data Polling Algorithm” ( ■FLOW CHART). For programming, the Data Polling is valid after the rising edge of the fourth write pulse in the four write pulse sequence. For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased, not a protected sectors. Otherwise, the status may be invalid. Once the Embedded Algorithm operation is close to being completed, the device data pins (DQ7) may change asynchronously while the output enable (OE) is asserted low. This means that the device is driving status information on DQ7 at one instant of time and then that byte’s valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operation and DQ7 has a valid data, the data outputs on DQ0 to DQ6 may be still invalid. The valid data on DQ0 to DQ7 will be read on the successive read attempts. The Data Polling feature is active only during the Embedded Programming Algorithm, Embedded Erase Algorithm, Erase Suspend mode or sector erase time-out. (See “Hardware Sequence Flags” Table.) See “6. Data Polling during Embedded Algorithm Operation Timing Diagram” in ■TIMING DIAGRAM for the Data Polling timing specifications and diagrams. 14. DQ6 Toggle Bit I The device also features the “Toggle Bit I” as a method to indicate to the host system that the Embedded Algorithms are in progress or completed. During Embedded Program or Erase Algorithm cycle, successive attempts to read (CE or OE toggling) data from the device will results in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequence. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six write pulse sequence. The Toggle Bit I is active during the sector time out. In program operation, if the sector being written is protected, the toggle bit will toggle for about 1 µs and then stop toggling with data unchanged. In erase operation, the device will erase all selected sectors except for ones that are protected. If all selected sectors are protected, chip will toggle the toggle bit for about 400 µs and then drop back into read mode, having data unchanged. Either CE or OE toggling will cause DQ6 to toggle. See “7. Toggle Bit I during Embedded Algorithm Operation Timing Diagram” in ■TIMING DIAGRAM for the Toggle Bit I timing specifications and diagrams. 15. DQ5 Exceeded Timing Limits DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count) . Under these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase cycle was not successfully completed. Data Polling is the only operating function of device under this condition. The CE circuit will partially power down device under these conditions (to approximately 2 mA) . The OE and 31 MBM29LV320TE/BE80/90/10 WE pins will control the output disable functions as described in “MBM29LV320TE/BE User Bus Operations Tables (BYTE = VIH and BYTE = VIL)” (■DEVICE BUS OPERATIONS). The DQ5 failure condition may also appear if a user tries to program a non blank location without erasing. In this case the device locks out and never complete the Embedded Algorithm operation. Hence, the system never read valid data on DQ7 bit and DQ6 never stop toggling. Once the device has exceeded timing limits, the DQ5 bit will indicate a “1.” Please note that this is not a device failure condition since device was incorrectly used. If this occurs, reset device with command sequence. 16. DQ3 Sector Erase Timer After completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will remain low until the time-out is completed. Data Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data Polling or Toggle Bit I indicates device has been written with a valid erase command, DQ3 may be used to determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low (“0”) , the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent Sector Erase command. If DQ3 were high on the second status check, the command may not have been accepted. See “Hardware Sequence Flags Table”. 17. DQ2 Toggle Bit II This toggle bit II, along with DQ6, can be used to determine whether the device is in the Embedded Erase Algorithm or in Erase Suspend. Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause DQ2 to toggle. When the device is in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic “1” at the DQ2 bit. DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized as follows : For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress. (DQ2 toggles while DQ6 does not.) See also “Toggle Bit Status Table” and “8. DQ2 vs DQ6” in ■TIMING DIAGRAM. Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase mode, DQ2 toggles if this bit is read from an erasing sector. 18. Reading Toggle Bits DQ6/DQ2 Whenever the system initially begins reading toggle bit status, it must read DQ7 to DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, this indicates that the device has completed the program or erase operation. The system can read array data on DQ7 to DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see “15. DQ5”) . If it is the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. 32 MBM29LV320TE/BE80/90/10 The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. (See “4. Toggle Bit Algorithm” in ■FLOW CHART.) Toggle Bit Status Table DQ7 DQ6 DQ2 DQ7 Toggle 1 Erase 0 Toggle Toggle* Erase-Suspend Read (Erase-Suspended Sector) 1 1 Toggle DQ7 Toggle 1* Mode Program Erase-Suspend Program * : Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle. Reading from non-erase suspend sector address will indicate logic “1” at the DQ2 bit. 19. RY/BY Ready/Busy The device provides a RY/BY open-drain output pin as a way to indicate to the host system that the Embedded Algorithms are either in progress or has been completed. If output is low, the device is busy with either a program or erase operation. If output is high, the device is ready to accept any read/write or erase operation. When the RY/BY pin is low, the device will not accept any additional program or erase commands. If the device is placed in an Erase Suspend mode, RY/BY output will be high. During programming, RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase operation, RY/BY pin is driven low after the rising edge of the sixth write pulse. RY/BY pin will indicate a busy condition during RESET pulse. See “9. RY/BY Timing Diagram during Program/Erase operations” and “10. RESET, RY/BY Timing Diagram” in ■TIMING DIAGRAM for a detailed timing diagram. RY/BY pin is pulled high in standby mode. Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to VCC. 20. Byte/Word Configuration BYTE pin selects byte (8-bit) mode or word (16-bit) mode for device. When this pin is driven high, the device operates in word (16-bit) mode. Data is read and programmed at DQ15 to DQ0. When this pin is driven low, the device operates in byte (8-bit) mode. Under this mode, DQ15/A-1 pin becomes the lowest address bit, and DQ14 to DQ8 bits are tri-stated. However, the command bus cycle is always an 8-bit operation and hence commands are written at DQ15 to DQ8 and the DQ7 to DQ0 bits are ignored. See “11. Word Mode Configuration Timing Diagram”, “12. Byte Mode Configuration Timing Diagram” and “13. BYTE Timing Diagram for Write Operations” in ■TIMING DIAGRAM the detail . 21. Data Protection The device is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up device automatically resets internal state machine in Read mode. Also, with its control register architecture, alteration of memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transitions or system noise. 33 MBM29LV320TE/BE80/90/10 22. Low VCC Write Inhibit To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less than VLKO (Min) . If VCC < VLKO, the command register is disabled and all internal program/erase circuits are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when VCC is above VLKO (Min) . If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector (s) cannot be used. 23. Write Pulse “Glitch” Protection Noise pulses of less than 3 ns (Typ) on OE, CE, or WE will not initiate a write cycle. 24. Logical Inhibit Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle CE and WE must be a logical zero while OE is a logical one. 25. Power-Up Write Inhibit Power-up of the device with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE. The internal state machine is automatically reset to the read mode on power-up. 34 MBM29LV320TE/BE80/90/10 ■ ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Min Max Tstg −55 +125 °C TA −40 +85 °C VIN, VOUT −0.5 VCC + 0.5 V Power Supply Voltage *1 VCC −0.5 +4.0 V A9, OE, and RESET *1, *3 VIN −0.5 +13.0 V 1, 4 VACC −0.5 +13.0 V Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All pins except A9, OE, and RESET *1, *2 WP/ACC * * *1 : Voltage is defined on the basis of VSS = GND = 0 V. *2 : Minimum DC voltage on input or l/O pins is −0.5 V. During voltage transitions, input or I/O pins may undershoot VSS to −2.0 V for periods of up to 20 ns. Maximum DC voltage on input or l/O pins is VCC + 0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC + 2.0 V for periods of up to 20 ns. * 3: Minimum DC input voltage on A9, OE and RESET pins is −0.5 V. During voltage transitions, A9, OE and RESET pins may undershoot VSS to −2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN − VCC) does not exceed +9.0 V.Maximum DC input voltage on A9, OE and RESET pins is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns. * 4: Minimum DC input voltage on WP/ACC pin is −0.5 V. During voltage transitions, WP/ACC pin may undershoot VSS to −2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +13.0 V which may overshoot to +12.0 V for periods of up to 20 ns when VCC is applied. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING RANGES Parameter Symbol Ambient Temperature TA Power Supply Voltage VCC Part No. Value Min Max MBM29LV320TE/BE 80/90/10 −40 +85 MBM29LV320TE/BE 80/90 +3.0 +3.6 MBM29LV320TE/BE 10 +2.7 +3.6 Unit °C V Operating ranges define those limits between which the functionality of the device is guaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 35 MBM29LV320TE/BE80/90/10 ■ MAXIMUM OVERSHOOT/UNDERSHOOT 20 ns 20 ns +0.6 V −0.5 V −2.0 V 20 ns Maximum Undershoot Waveform 20 ns VCC + 2.0 V VCC + 0.5 V +2.0 V 20 ns 20 ns Maximum Overshoot Waveform 1 20 ns +14.0 V +13.0 V VCC + 0.5 V 20 ns 20 ns Note : This waveform is applied for A9, OE, and RESET. Maximum Overshoot Waveform 2 36 MBM29LV320TE/BE80/90/10 ■ DC CHARACTERISTICS Parameter Symbol Conditions Min Max Unit Input Leakage Current ILI VIN = VSS to VCC, VCC = VCC Max −1.0 +1.0 µA Output Leakage Current ILO VOUT = VSS to VCC, VCC = VCC Max −1.0 +1.0 µA A9, OE, RESET Inputs Leakage Current ILIT VCC = VCC Max, A9, OE, RESET = 12.5 V 35 µA CE = VIL, OE = VIH, f = 5 MHz VCC Active Current *1 ICC1 CE = VIL, OE = VIH, f = 1 MHz Byte Word Byte Word 16 18 7 7 mA mA VCC Active Current *2 ICC2 CE = VIL, OE = VIH 40 mA VCC Current (Standby) ICC3 VCC = VCC Max, CE = VCC ± 0.3 V, RESET = VCC ± 0.3 V 5 µA VCC Current (Standby, Reset) ICC4 VCC = VCC Max,WE/ACC = VCC ± 0.3 V, RESET = VSS ± 0.3 V 5 µA VCC Current (Automatic Sleep Mode) *3 ICC5 VCC = VCC Max, CE = VSS ± 0.3 V, RESET = VCC ± 0.3 V VIN = VCC ± 0.3 V or VSS ± 0.3 V 5 µA WP/ACC Accelerated Program Current IACC VCC = VCC Max, WP/ACC = VACC Max 20 mA Input Low Level VIL − 0.5 + 0.6 V Input High Level VIH 2.0 VCC + 0.3 V VACC 11.5 12.5 V Voltage for Autoselect and Sector Group Protection (A9, OE, RESET) *4 VID 11.5 12.5 V Output Low Voltage Level VOL IOL = 4.0 mA, VCC = VCC Min 0.45 V VOH1 IOH = −2.0 mA, VCC = VCC Min 2.4 V VOH2 IOH = −100 µA VCC − 0.4 V 2.3 2.5 V Voltage for WP/ACC Sector Protection/Unprotection and Program Acceleration Output High Voltage Level Low VCC Lock-Out Voltage VLKO * 1: The ICC current listed includes both the DC operating current and the frequency dependent component. * 2: ICC active while Embedded Algorithm (program or erase) is in progress. * 3: Automatic sleep mode enables the low power mode when addresses remain stable for 150 ns. * 4: Applicable for only VCC applying. 37 MBM29LV320TE/BE80/90/10 ■ AC CHARACTERISTICS • Read Only Operations Characteristics Symbol Parameter Value JEDEC Standard Condition 80* 90* Min Max Min Read Cycle Time tAVAV tRC 80 90 Address to Output Delay tAVQV tACC CE = VIL OE = VIL 80 Chip Enable to Output Delay tELQV tCE OE = VIL 80 Output Enable to Output Delay tGLQV tOE Chip Enable to Output High-Z tEHQZ tDF Output Enable to Output High-Z tGHQZ tDF Output Hold Time From Addresses, CE or OE, Whichever Occurs First tAXQX RESET Pin Low to Read Mode CE to BYTE Switching Low or High 10* Max Min Max 100 ns 90 100 ns 90 100 ns 30 35 35 ns 25 30 30 ns 25 30 30 ns tOH 0 0 0 ns tREADY 20 20 20 µs tELFL tELFH 5 5 5 ns * : Test Conditions : Output Load : 1 TTL gate and 30 pF (MBM29LV320TE80, MBM29LV320BE80) 100 pF (MBM29LV320TE90/10, MBM29LV320BE90/10) Input rise and fall times : 5 ns Input pulse levels : 0.0 V or 3.0 V Timing measurement reference level Input : 1.5 V Output : 1.5 V 3.3 V IN3064 or Equivalent 2.7 kΩ Device Under Test 6.2 kΩ CL Diodes = IN3064 or Equivalent Notes : CL = 30 pF including jig capacitance (MBM29LV320TE80, MBM29LV320BE80) CL = 100 pF including jig capacitance (MBM29LV320TE90/10, MBM29LV320BE90/10) Test Conditions 38 Unit MBM29LV320TE/BE80/90/10 • Write/Erase/Program Operations Symbol Parameter JEDEC Value 80 (Note) Standard 90 (Note) 10 (Note) Min Typ Max Min Typ Max Min Unit Typ Max Write Cycle Time tAVAV tWC 80 90 100 ns Address Setup Time tAVWL tAS 0 0 0 ns Address Hold Time tWLAX tAH 45 45 45 ns Data Setup Time tDVWH tDS 30 35 35 ns Data Hold Time tWHDX tDH 0 0 0 ns 0 0 0 ns tOEH 10 10 10 ns Read Recover Time Before Write tGHWL tGHWL 0 0 0 ns Read Recover Time Before Write (OE High to CE Low) tGHEL tGHEL 0 0 0 ns CE Setup Time tELWL tCS 0 0 0 ns WE Setup Time tWLEL tWS 0 0 0 ns CE Hold Time tWHEH tCH 0 0 0 ns WE Hold Time tEHWH tWH 0 0 0 ns Write Pulse Width tWLWH tWP 35 35 35 ns CE Pulse Width tELEH tCP 35 35 35 ns Write Pulse Width High tWHWL tWPH 25 30 30 ns CE Pulse Width High tEHEL tCPH 25 30 30 ns tWHWH1 tWHWH1 8 8 8 µs 16 16 16 µs tWHWH2 tWHWH2 1 1 1 s tVCS 50 50 50 µs tVIDR 500 500 500 ns Rise Time to VACC * tVACCR 500 500 500 ns Voltage Transition Time *2 tVLHT µs 100 100 µs Output Enable Hold Time Read Toggle and Data Polling Byte Programming Operation Word Sector Erase Operation *1 VCC Setup Time 2 Rise Time to VID * 3 4 4 tWPP 2 tOESP 4 4 4 µs 2 CE Setup Time to WE Active * tCSP 4 4 4 µs Recover Time From RY/BY tRB 0 0 0 ns RESET Pulse Width tRP 500 500 500 ns RESET High Level Period Before Read tRH 200 200 200 ns Write Pulse Width *2 OE Setup Time to WE Active * 100 4 (Continued) 39 MBM29LV320TE/BE80/90/10 (Continued) Symbol Parameter JEDEC Value 80 (Note) Standard 10 (Note) Unit Min Typ Max Min Typ Max Min Typ Max BYTE Switching Low to Output High-Z tFLQZ 30 30 30 ns BYTE Switching High to Output Active tFHQV 80 90 100 ns Program/Erase Valid to RY/BY Delay tBUSY 90 90 90 ns Delay Time from Embedded Output Enable tEOE 80 90 100 ns Erase Time-out Time tTOW 50 50 50 µs Erase Suspend Transition Time tSPD 20 20 20 µs *1 : This does not include the preprogramming time. *2 : This timing is for Sector Group Protection operation. *3 : This timing is limited for Accelerated Program operation only. 40 90 (Note) MBM29LV320TE/BE80/90/10 ■ ERASE AND PROGRAMMING PERFORMANCE Limits Parameter Unit Min Typ Max Sector Erase Time 1 10 s Word Programming Time 16 360 µs Byte Programming Time 8 300 µs Chip Programming Time 100 s 100,000 cycle Program/Erase Cycle Comments Excludes programming time prior to erasure Excludes system-level overhead Excludes system-level overhead ■ TSOP (I) PIN CAPACITANCE Parameter Symbol Condition Value Typ Max Unit Input Capacitance CIN VIN = 0 6.0 7.5 pF Output Capacitance COUT VOUT = 0 8.5 12.0 pF Control Pin Capacitance CIN2 VIN = 0 8.0 10.0 pF WP/ACC Pin Capacitance CIN3 VIN = 0 15.0 20.0 pF Note : Test conditions TA = + 25 °C, f = 1.0 MHz ■ FBGA PIN CAPACITANCE Parameter Symbol Condition Value Typ Max Unit Input Capacitance CIN VIN = 0 6.0 7.5 pF Output Capacitance COUT VOUT = 0 8.5 12.0 pF Control Pin Capacitance CIN2 VIN = 0 8.0 10.0 pF WP/ACC Pin Capacitance CIN3 VIN = 0 15.0 20.0 pF Note : Test conditions TA = + 25 °C, f = 1.0 MHz 41 MBM29LV320TE/BE80/90/10 ■ TIMING DIAGRAM • Key to Switching Waveforms WAVEFORM INPUTS OUTPUTS Must Be Steady Will Be Steady May Change from H to L Will Change from H to L May Change from L to H Will Change from L to H "H" or "L" Any Change Permitted Changing State Unknown Does Not Apply Center Line is HighImpedance "Off" State 1. Read Operation Timing Diagram tRC Address Address Stable tACC CE tOE tDF OE tOEH WE tOH tCE High-Z Outputs 42 Output Valid High-Z MBM29LV320TE/BE80/90/10 2. Hardware Reset/Read Operation Timing Diagram tRC Address Address Stable tACC CE tRH tRP tRH tCE RESET tOH High-Z Outputs Output Valid 3. Alternate WE Controlled Program Operation Timing Diagram 3rd Bus Cycle Data Polling 555h Address tWC PA tAS PA tRC tAH CE tCS tCH tCE OE tGHWL tWP tOE tWPH tWHWH1 WE tOH tDS tDH Data A0h PD DQ7 DOUT DOUT Notes : • PA is address of the memory location to be programmed. • PD is data to be programmed at byte address. • DQ7 is the output of the complement of the data written to the device. • DOUT is the output of the data written to the device. • Figure indicates last two bus cycles out of four bus cycle sequence. • These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.) 43 MBM29LV320TE/BE80/90/10 4. Alternate CE Controlled Program Operation Timing Diagram 3rd Bus Cycle Data Polling 555h Address tWC PA tAS PA tAH WE tWS tWH OE tGHEL tCP tCPH tWHWH1 CE tDS Data A0h tDH PD DQ7 DOUT Notes : • PA is address of the memory location to be programmed. • PD is data to be programmed at byte address. • DQ7 is the output of the complement of the data written to the device. • DOUT is the output of the data written to the device. • Figure indicates last two bus cycles out of four bus cycle sequence. • These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.) 44 MBM29LV320TE/BE80/90/10 5. Chip/Sector Erase Operation Timing Diagram 555h Address tWC 2AAh tAS 555h 555h 2AAh SA* tAH CE tCS tCH OE tGHWL tWP tWPH tDS tDH WE AAh 10h for Chip Erase 55h 80h AAh 55h 30h Data tVCS VCC * : SA is the sector address for Sector Erase. Addresses = 555h (Word), AAAh (Byte) for Chip Erase. Note : These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.) 45 MBM29LV320TE/BE80/90/10 6. Data Polling during Embedded Algorithm Operation Timing Diagram CE tCH tDF tOE OE tOEH WE tCE * Data DQ7 DQ7 = Valid Data DQ7 High-Z tWHWH1 or 2 DQ6 to DQ0 DQ6 to DQ0 = Output Flag Data DQ6 to DQ0 Valid Data High-Z tEOE tBUSY RY/BY * : DQ7 = Valid Data (The device has completed the Embedded operation) . 7. Toggle Bit I during Embedded Algorithm Operation Timing Diagram CE tOEH WE OE tDH DQ6 Data (DQ0 to DQ7) * DQ6 = Toggle DQ6 = Toggle DQ6 = Stop Toggling tOE * : DQ6 = Stops toggling. (The device has completed the Embedded operation.) 46 DQ0 to DQ7 Data Valid MBM29LV320TE/BE80/90/10 8. DQ2 vs. DQ6 Enter Embedded Erasing WE Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Read Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete DQ6 DQ2 * Toggle DQ2 and DQ6 with OE or CE * : DQ2 is read from the erase-suspended sector. 9. RY/BY Timing Diagram during Program/Erase Operations CE Rising edge of the last write pulse WE Entire programming or erase operations RY/BY tBUSY 10. RESET, RY/BY Timing Diagram WE RESET tRP tRB RY/BY tREADY 47 MBM29LV320TE/BE80/90/10 11. Word Mode Configuration Timing Diagram CE tCE BYTE Data Output DQ14 to DQ0 Data Output (DQ14 to DQ0) (DQ7 to DQ0) tELFH tFHQV A-1 DQ15/A-1 DQ15 12. Byte Mode Configuration Timing Diagram CE BYTE DQ14 to DQ0 tELFL Data Output Data Output (DQ14 to DQ0) (DQ7 to DQ0) tACC DQ15/A-1 A-1 DQ15 tFLQZ 13. BYTE Timing Diagram for Write Operations Falling edge of last write signal CE or WE Input Valid BYTE tSET (tAS) 48 tHOLD (tAH) MBM29LV320TE/BE80/90/10 14. Sector Group Protection Timing Diagram A20, A19, A18 A17, A16, A15 A14, A13, A12 SPAX SPAY A6, A0 A1 VID 3V A9 tVLHT VID 3V OE tVLHT tVLHT tVLHT tWPP WE tOESP tCSP CE 01h Data tVCS tOE VCC SPAX : Sector Group Address to be protected. SPAY : Next Sector Group Address to be protected. Note : A-1 is VIL on byte mode. 49 MBM29LV320TE/BE80/90/10 15. Temporary Sector Group Unprotection Timing Diagram VCC tVIDR tVCS tVLHT VID 3V RESET CE WE tVLHT Program or Erase Command Sequence RY/BY Unprotection period 50 tVLHT MBM29LV320TE/BE80/90/10 16. Extended Sector Group Protection Timing Diagram VCC tVCS RESET tVLHT tVIDR tWC Address tWC SPAX SPAX SPAY A 6, A 0 A1 CE OE TIME-OUT tWP WE Data 60h 60h 40h 01h 60h tOE SPAX : Sector Group Address to be protected SPAY : Next Sector Group Address to be protected TIME-OUT : Time-Out window = 250 µs (Min) 51 MBM29LV320TE/BE80/90/10 17. Accelerated Program Timing Diagram VCC tVACCR tVCS tVLHT VACC 3V WP/ACC CE WE tVLHT Program Command Sequence RY/BY Acceleration period 52 tVLHT MBM29LV320TE/BE80/90/10 ■ FLOW CHART 1. Embedded ProgramTM Algorithm EMBEDDED ALGORITHM Start Write Program Command Sequence (See Below) Data Polling No Increment Address No Verify Data ? Yes Embedded Program Algorithm in progress Last Address ? Yes Programming Completed Program Command Sequence (Address/Command): 555h/AAh 2AAh/55h 555h/A0h Program Address/Program Data Note : The sequence is applied for × 16 mode. The addresses differ from × 8 mode. 53 MBM29LV320TE/BE80/90/10 2. Embedded EraseTM Algorithm EMBEDDED ALGORITHM Start Write Erase Command Sequence (See Below) Data Polling No Data = FFh ? Yes Embedded Erase Algorithm in progress Erasure Completed Chip Erase Command Sequence (Address/Command): Individual Sector/Multiple Sector Erase Command Sequence (Address/Command): 555h/AAh 555h/AAh 2AAh/55h 2AAh/55h 555h/80h 555h/80h 555h/AAh 555h/AAh 2AAh/55h 2AAh/55h 555h/10h Sector Address /30h Sector Address /30h Sector Address /30h Note : The sequence is applied for × 16 mode. The addresses differ from × 8 mode. 54 Additional sector erase commands are optional. MBM29LV320TE/BE80/90/10 3. Data Polling Algorithm VA = Address for programming = Any of the sector addresses within the sector being erased during sector erase or multiple erases operation = Any of the sector addresses within the sector not being protected during sector erase or multiple sector erases operation Start Read Byte (DQ7 to DQ0) Addr. = VA DQ7 = Data? Yes No No DQ5 = 1? Yes Read Byte (DQ7 to DQ0) Addr. = VA DQ7 = Data? * No Fail Yes Pass * : DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. 55 MBM29LV320TE/BE80/90/10 4. Toggle Bit Algorithm Start Read DQ7 to DQ0 Addr. = "H" or "L" *1 Read DQ7 to DQ0 Addr. = "H" or "L" DQ6 = Toggle? No Yes No DQ5 = 1? Yes *1, *2 Read DQ7 to DQ0 Twice Addr. = "H" or "L" DQ6 = Toggle? No Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete *1 : Read toggle bit twice to determine whether or not it is toggling. *2 : Recheck toggle bit because it may stop toggling as DQ5 changes to “1”. 56 MBM29LV320TE/BE80/90/10 5. Sector Group Protection Algorithm Start Setup Sector Group Addr. A20, A19, A18, A17,A16, A15, A14, A13, A12 ( ) PLSCNT = 1 OE = VID, A9 = VID, CE = VIL, RESET = VIH A6 = A0 = VIL, A1 = VIH Activate WE Pulse Increment PLSCNT Time out 100 µs WE = VIH, CE = OE = VIL (A9 should remain VID) Read from Sector Group A1 = VIH * ( Addr.A6= =SPA, ) A0 = VIL No PLSCNT = 25? Yes Remove VID from A9 Write Reset Command No Data = 01h? Yes Protect Another Sector Group ? Yes No Device Failed Remove VID from A9 Write Reset Command Sector Group Protection Completed * : A-1 is V IL on byte mode. 57 MBM29LV320TE/BE80/90/10 6. Temporary Sector Group Unprotection Algorithm Start RESET = VID *1 Perform Erase or Program Operations RESET = VIH Temporary Sector Group Unprotection Completed *2 *1 : All protected sectors are unprotected. *2 : All previously protected sectors are protected once again. 58 MBM29LV320TE/BE80/90/10 7. Extended Sector Group Protection Algorithm Start RESET = VID Wait to 4 µs Device is Operating in Temporary Sector Group Unprotection Mode No Extended Sector Group Protection Entry? Yes To Setup Sector Group Protection Write XXXh/60h PLSCNT = 1 To Protect Sector Group Write 60h to Sector Address (A6 = A0 = VIL, A1 = VIH) Time out 250 µs To Verify Sector Group Protection Write 40h to Sector Address (A6 = A0 = VIL, A1 = VIH) Increment PLSCNT Read from Sector Group Address (A0 = VIL, A1 = VIH, A6 = VIL) No PLSCNT = 25? Yes Remove VID from RESET Write Reset Command Setup Next Sector Address No Data = 01h? Yes Yes Protection Other Sector Group ? No Remove VID from RESET Write Reset Command Device Failed Sector Group Protection Completed 59 MBM29LV320TE/BE80/90/10 8. Embedded ProgramTM Algorithm for Fast Mode FAST MODE ALGORITHM Start 555h/AAh Set Fast Mode 2AAh/55h 555h/20h XXXh/A0h Program Address/Program Data Data Polling In Fast Program Verify Data? No Yes Increment Address No Last Address ? Yes Programming Completed XXXXh/90h Reset Fast Mode XXXXh/F0h Notes : •The sequence is applied for × 16 mode. •The addresses differ from × 8 mode. 60 MBM29LV320TE/BE80/90/10 ■ ORDERING INFORMATION Standard Products Fujitsu standard products are available in several packages. The order number is formed by a combination of : MBM29LV320 T E 80 TN PACKAGE TYPE TN = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout TR = 48-Pin Thin Small Outline Package (TSOP) Reverse Pinout PBT = 63-Ball Fine pitch Ball Grid Array Package (FBGA) SPEED OPTION See Product Selector Guide DEVICE REVISION BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector DEVICE NUMBER/DESCRIPTION MBM29LV320 32Mega-bit (4 M × 8-Bit or 2 M × 16-Bit) CMOS Flash Memory 3.0 V-only Read, Program, and Erase Valid Combinations MBM29LV320TE/BE 80 90 10 Valid Combinations TN TR PBT Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Fujitsu sales office to confirm availability of specific valid combinations and to check on newly released combinations. 61 MBM29LV320TE/BE80/90/10 ■ PACKAGE DIMENSION 48-pin plastic TSOP (I) (FPT-48P-M19) * Resin Protrusion. (Each Side: 0.15 (.006) Max) LEAD No. 1 48 INDEX Details of "A" part 0.25(.010) 0~8˚ 0.60±0.15 (.024±.006) 24 25 20.00±0.20 (.787±.008) * 18.40±0.20 (.724±.008) "A" * 12.00±0.20 (.472±.008) 11.50REF (.453) +.004 .043 –.002 (Mounting height) 0.10±0.05 (.004±.002) (Stand off height) 0.50(.020) TYP 0.10(.004) +0.03 0.22±0.05 (.009±.002) 0.17 –0.08 +.001 .007 –.003 C +0.10 1.10 –0.05 2001 FUJITSU LIMITED F48029S-c-4-5 0.10(.004) M Dimensions in mm (inches) 48-pin plastic TSOP (I) (FPT-48P-M20) * Resin Protrusion. (Each Side: 0.15 (.006) Max) LEAD No. 1 48 Details of "A" part INDEX 0.15(.006) MAX 0.35(.014) MAX "A" 0.15(.006) 24 0.25(.010) 25 19.00±0.20 (.748±.008) 0.50±0.10 (.020±.004) 0.15±0.05 (.006±.002) 0.10(.004) 0.20±0.10 (.008±.004) 0.50(.020) TYP 0.10(.004) M 0.10±0.05 (.004±.002) (STAND OFF) +0.10 1.10 –0.05 * 18.40±0.20 (.724±.008) 20.00±0.20 (.787±.008) C 2000 FUJITSU LIMITED F48030S-3c-4 11.50(.453)REF * 12.00±0.20(.472±.008) +.004 .043 –.002 (Mounting height) Mounting height Dimensions in mm (inches) (Continued) 62 MBM29LV320TE/BE80/90/10 (Continued) 63-pin plastic FBGA (BGA-63P-M01) +0.15 11.00±0.10(.433±.004) 1.05 –0.10 (8.80(.346)) +.006 .041 –.004 (Mounting height) (7.20(.283)) 0.38±0.10 (.015±.004) (Stand off) (5.60(.220)) 0.80(.031)TYP 8 7 6 7.00±0.10 (.276±.004) 5 (4.00(.157)) (5.60(.220)) 4 3 2 1 M L K J H G F E D C B A INDEX AREA INDEX BALL 63-ø0.45±0.05 (63-ø0.18±.002) 0.08(.003) M 0.10(.004) C 2001 FUJITSU LIMITED B63001S-c-2-2 Dimensions in mm (inches) 63 MBM29LV320TE/BE80/90/10 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Marketing Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3353 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fme.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmal.fujitsu.com/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 F0202 FUJITSU LIMITED Printed in Japan All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.