HD74HC323 8-bit Universal Shift/Storage Register (with 3-state Outputs) Description This eight-bit universal register features multiplexed I/O ports to achieve full eight bit data handling in a single 20-pin package. HD74HC323 applications are as stacked or push-down registers, buffer storage, and accumulator registers. Two function-select inputs and two output control inputs can be used to choose the modes of operation listed in the function table. Synchronous parallel loading is accomplished by taking both function-select lines S0 and S1 high. This places the three-state outputs in a high-impedance state, which permits data that is applied on the I/O ports to be clocked into the register. Reading out of this register can be accomplished while the outputs are enabled in any mode. The clear function is synchronous, and a low level at the clear input clears the register on the next low-to-high transition of the clock. Features • • • • • High Speed Operation: tpd (Clock to Q) = 20 ns typ (CL = 50 pF) High Output Current: Fanout of 15 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) HD74HC323 Function Table Inputs Function Select Output Control Serial Inputs/Outputs Outputs Mode Clear S1 S0 G1† G2† Clear L X L L L X X L L L L L L L L L L L L X L L X X L L L L L L L L L L H L L L L X X X QA0 QB0 QC0 QD0 QE0 QF0 QG0 QH0 QA0 QH0 H X X L L L X X QA0 QB0 QC0 QD0 QE0 QF0 QG0 QH0 QA0 QH0 Shift H L H L L X H H QAn QBn QCn QDn QEn QFn QGn H QGn Right H L H L L X L L QAn QBn QCn QDn QEn QFn QGn L QGn Shift H H L L L H X QBn QCn QDn QEn QFn QGn QHn H QBn H Left H H L L L L X QBn QCn QDn QEn QFn QGn QHn L QBn L Load H H H X X X X a b c d e f g h a h Hold Clock SL SR A/QA B/QB C/QC D/QD E/QE F/QF G/Q G H/QH QA’ QH’ a ... h = the level of the steady-state input at A through H, respectively. These data are loaded into the flipflops while the flip-flop outputs are isolated from the input/output terminals. Pin Arrangement Output controls S0 1 G1 2 20 VCC S0 S1 19 S1 SL 18 17 QH' G 3 G/QC 4 G/QC QH E/QE 5 E/QE H/QH 16 H/QH C/QC 6 C/QC F/QF 15 F/QF A/QA 7 A/QA D/QD 14 D/QD QA' 8 QA B/QB 13 B/QB Clear 9 Clear SR CK 12 Clock 11 Shift right SR GND 10 (Top view) 2 Shift left SL G2 HD74HC323 Absolute Maximum Ratings Item Symbol Rating Unit Supply voltage range VCC –0.5 to +7.0 V Input voltage VIN –0.5 to VCC + 0.5 V Output voltage VOUT –0.5 to VCC + 0.5 V Output current I OUT ±35 mA DC current drain per VCC, GND I CC, I GND ±75 mA DC input diode current I IK ±20 mA DC output diode current I OK ±20 mA Power dissipation per package PT 500 mW Storage temperature Tstg –65 to +150 °C Logic Diagram QH' SL H/QH G/QG F/QF E/QE D/QD C/QC B/QB CK CK CK CK CK CK A/QA CK CK CK CK SR S0 S1 Clear Clock QA' G1 G2 3 HD74HC323 DC Characteristics Ta = –40 to +85°C Ta = 25°C Item Symbol VCC (V) Min Typ Max Min Max Unit Test Conditions Input voltage VIH 2.0 1.5 — — 1.5 — V 4.5 3.15 — — 3.15 — 6.0 4.2 — — 4.2 — 2.0 — — 0.5 — 0.5 4.5 — — 1.35 — 1.35 6.0 — — 1.8 — 1.8 2.0 1.9 2.0 — 1.9 — 4.5 4.4 4.5 — 4.4 — 6.0 5.9 6.0 — 5.9 — 4.5 4.18 — — 4.13 — 6.0 5.68 — — 5.63 — 4.5 4.18 — — 4.13 — 6.0 5.68 — — 5.63 — 2.0 — 0.0 0.1 — 0.1 4.5 — 0.0 0.1 — 0.1 6.0 — 0.0 0.1 — 0.1 4.5 — — 0.26 — 0.33 6.0 — — 0.26 — 0.33 4.5 — — 0.26 — 0.33 6.0 — — 0.26 — 0.33 VIL Output voltage VOH VOL V V Vin = VIH or VIL I OH = –20 µA QA to QH I OH = –6 mA I OH = –7.8 mA QA’, QH ’ I OH = –4 mA I OH = –5.2 mA V Vin = VIH or VIL I OL = 20 µA QA to QH I OH = 6 mA I OH = 7.8 mA QA’, QH ’ I OH = 4 mA I OH = 5.2 mA Off-state output current I OZ 6.0 — — ±0.5 — ±5.0 µA Vin = VIH or VIL, Vout = VCC or GND Input current Iin 6.0 — — ±0.1 — ±1.0 µA Vin = VCC or GND Quiescent supply current I CC 6.0 — — 4.0 40 µA Vin = VCC or GND, Iout = 0 µA 4 — HD74HC323 AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Ta = –40 to +85°C Ta = 25°C Item Symbol VCC (V) Min Typ Max Min Max Unit Maximum clock f max 2.0 — — 5 — 4 MHz 4.5 — — 27 — 21 6.0 — — 31 — 24 Propagation delay t PLH 2.0 — — 150 — 190 time 4.5 — 18 30 — 38 6.0 — — 26 — 33 2.0 — — 175 — 220 4.5 — 20 35 — 44 6.0 — — 30 — 37 frequency t PHL Output enable t ZH 2.0 — — 150 — 190 time t ZL 4.5 — 14 30 — 38 6.0 — — 26 — 33 Output disable t HZ 2.0 — — 150 — 190 time t LZ 4.5 — 15 30 — 38 6.0 — — 26 — 33 Output rise/fall t TLH 2.0 — — 75 — 95 time t THL 4.5 — 5 15 — 19 6.0 — — 13 — 16 2.0 — — 60 — 75 4.5 — 4 12 — 15 6.0 — — 10 — 13 — — 5 10 — 10 Input capacitance Cin Test Conditions ns Clock to QA’ or QH ’ ns Clock to Q ns ns ns QA’, QH ’ ns Q pF 5 Unit: mm 24.50 25.40 Max 6.30 11 1 7.00 Max 20 10 1.30 2.54 ± 0.25 0.48 ± 0.10 0.51 Min 1.27 Max 2.54 Min 5.08 Max 0.89 7.62 + 0.11 0.25 – 0.05 0° – 15° Hitachi Code JEDEC EIAJ Weight (reference value) DP-20N — Conforms 1.26 g Unit: mm 12.6 13 Max 11 1 10 1.27 *0.42 ± 0.08 0.40 ± 0.06 0.10 ± 0.10 0.80 Max *0.22 ± 0.05 0.20 ± 0.04 2.20 Max 5.5 20 0.20 7.80 +– 0.30 1.15 0° – 8° 0.70 ± 0.20 0.15 0.12 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-20DA — Conforms 0.31 g Unit: mm 12.8 13.2 Max 11 1 10 0.20 ± 0.10 0.935 Max 1.27 *0.42 ± 0.08 0.40 ± 0.06 *0.27 ± 0.05 0.25 ± 0.04 2.65 Max 7.50 20 0.25 10.40 +– 0.40 1.45 0° – 8° 0.57 0.70 +– 0.30 0.15 0.12 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-20DB Conforms — 0.52 g Unit: mm 6.50 6.80 Max 11 1 10 4.40 20 0.65 *0.22+0.08 –0.07 0.20 ± 0.06 1.0 0.13 M 6.40 ± 0.20 *Dimension including the plating thickness Base material dimension 0.07 +0.03 –0.04 0.10 *0.17 ± 0.05 0.15 ± 0.04 1.10 Max 0.65 Max 0° – 8° 0.50 ± 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) TTP-20DA — — 0.07 g Cautions 1. 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