HD74HC651/HD74HC652 Octal Bus Transceivers/Registers (with inverted 3-state outputs) Octal Bus Transceivers/Registers (with 3-state outputs) Description This device consists of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Enable GAB and GBA are provided to cotrol the transceiver functions. Select AB and Select BA control pins are provided to select whether real-time or stored data is transferred. A low input level selects real-time data, and a high selects stored data. The following examples demonstrate the four fundamental bus-management functions that can be performed with the HD74HC651 and HD74HC652. Data on the A or B data bus, or both, can be stored in the internal D flip-flops by low-to high transition at the appropriate clock pins (Clock AB or Clock BA) regardless of the select or enable control pins. When Select AB and Select BA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling Enable GAB and GBA. In this configuration each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines will remain at its last state. Features • • • • • High Speed Operation: tpd (Bus to Bus) = 16 ns typ (CL = 50 pF) High Output Current: Fanout of 15 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) HD74HC651/HD74HC652 Function Table Transfer Stored Data to A and/or B Clock AB X X L or H Select AB X L X H Enable GAB L H L H Clock BA X X Select BA L X X H Enable GBA L H H L Real-time transfer Bus B to Bus A 2 Bus B Bus A L or H Bus B Bus A Real-Time Transfer Real-Time Transfer Bus B to Bus A Bus A to Bus B Storage Real-time transfer Bus A to Bus B Bus B Bus A Bus B Bus A HD74HC651/HD74HC652 Transfer stored data to A and/or B Storage Pin Arrangement Clock AB 1 24 VCC Select AB 2 23 Clock BA Enable GAB 3 22 Select BA A1 4 21 Enable GBA A2 5 20 B1 A3 6 19 B2 A4 7 18 B3 A5 8 17 B4 A6 9 16 B5 A7 10 15 B6 A8 11 14 B7 GND 12 13 B8 (Top view) 3 HD74HC651/HD74HC652 Absolute Maximum Ratings Item Symbol Rating Unit Supply voltage range VCC –0.5 to +7.0 V Input voltage VIN –0.5 to VCC + 0.5 V Output voltage VOUT –0.5 to VCC + 0.5 V Output current I OUT ±35 mA DC current drain per VCC , GND I CC, I GND ±75 mA DC input diode current I IK ±20 mA DC output diode current I OK ±20 mA Power Dissipation per package PT 500 mW Storage temperature Tstg –65 to +150 °C Logic Diagram HD74HC651 x7 VCC Q CAB CAB A D VCC D 4 Q CAB CAB B CAB CBA SBA SAB GBA GAB HD74HC651/HD74HC652 HD74HC652 x7 VCC Q CAB CAB A D VCC D Q CAB CAB B CAB CBA SBA SAB GBA GAB 5 HD74HC651/HD74HC652 DC Characteristics Ta = –40 to +85°C Ta = 25°C Item Symbol VCC (V) Min Typ Max Min Max Unit Input voltage VIH 2.0 1.5 — — 1.5 — V 4.5 3.15 — — 3.15 — 6.0 4.2 — — 4.2 — 2.0 — — 0.5 — 0.5 4.5 — — 1.35 — 1.35 6.0 — — 1.8 — 1.8 2.0 1.9 2.0 — 1.9 — 4.5 4.4 4.5 — 4.4 — 6.0 5.9 6.0 — 5.9 — 4.5 4.18 — — 4.13 — I OH = –6 mA 6.0 5.68 — — 5.63 — I OH = –7.8 mA 2.0 — 0.0 0.1 — 0.1 4.5 — 0.0 0.1 — 0.1 6.0 — 0.0 0.1 — 0.1 4.5 — — 0.26 — 0.33 I OL = 6 mA 6.0 — — 0.26 — 0.33 I OL = 7.8 mA VIL Output voltage VOH VOL Test Conditions V V V Vin = VIH or VIL I OH = –20 µA Vin = VIH or VIL I OL = 20 µA Off-state output current I OZ 6.0 — — ±0.5 — ±5.0 µA Vin = VIH or VIL, Vout = VCC or GND Input current Iin 6.0 — — ±0.1 — ±1.0 µA Vin = VCC or GND Quiescent supply current I CC 6.0 — — 4.0 40 µA Vin = VCC or GND, Iout = 0 µA 6 — HD74HC651/HD74HC652 AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Ta = –40 to +85°C Ta = 25°C VCC (V) Min Typ Max Min Max Unit Test Conditions Propagation delay t PLH 2.0 — — 170 — 215 ns Clock to Bus time 4.5 — 19 34 — 43 6.0 — — 29 — 37 2.0 — — 135 — 170 ns Bus to Bus 4.5 — 16 27 — 34 6.0 — — 23 — 29 2.0 — — 190 — 240 ns Select to Bus 4.5 — 18 38 — 48 6.0 — — 32 — 41 Item Symbol t PHL Output enable t ZL 2.0 — — 150 — 190 time t ZH 4.5 — 14 30 — 38 6.0 — — 26 — 33 Output disable t LZ 2.0 — — 150 — 190 time t HZ 4.5 — 18 30 — 38 6.0 — — 26 — 33 2.0 80 — — 100 — 4.5 16 7 — 20 — 6.0 14 — — 17 — 2.0 100 — — 125 — 4.5 20 4 — 25 — 6.0 17 — — 21 — 2.0 5 — — 5 — 4.5 5 –1 — 5 — 6.0 5 — — 5 — Pulse width Setup time Hold time tw t su th Output rise/fall t TLH 2.0 — — 60 — 75 time t THL 4.5 — 4 12 — 15 6.0 — — 10 — 13 — — 5 10 — 10 Input capacitance Cin ns ns ns ns ns ns pF 7 Unit: mm 13 13.4 15.0 Max 24 31.6 32.5 Max 12 1.2 15.24 0.48 ± 0.10 0.51 Min 2.54 ± 0.25 5.70 Max 2.13 Max 2.54 Min 1 + 0.11 0.25 – 0.05 0° – 15° Hitachi Code JEDEC EIAJ Weight (reference value) DP-24 Conforms Conforms 3.1 g Cautions 1. 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