LINER LTC6915IDE

LTC6915
Zero Drift, Precision
Instrumentation Amplifier with
Digitally Programmable Gain
U
FEATURES
■
■
■
■
■
■
■
■
■
■
DESCRIPTIO
The LTC®6915 is a precision programmable gain instrumentation amplifier. The gain can be programmed to 0, 1,
2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, or 4096
through a parallel or serial interface. The CMRR is typically
125dB with a dual 5V supply with any programmed gain.
The offset is below 10µV with a temperature drift of less
than 50nV/°C.
14 Levels of Programmable Gain
125dB CMRR Independent of Gain
Gain Accuracy 0.1% (Typ)
Maximum Offset Voltage of 10µV
Maximum Offset Voltage Drift: 50nV/°C
Rail-to-Rail Input and Output
Parallel or Serial (SPI) Interface for Gain Setting
Supply Operation: 2.7V to ±5.5V
Typical Noise: 2.5µVP-P (0.01Hz to 10Hz)
16-Lead SSOP and 12-Lead DFN Packages
The LTC6915 uses charge balanced sampled data techniques to convert a differential input voltage into a single
ended signal that is in turn amplified by a zero-drift
operational amplifier.
U
APPLICATIO S
■
■
■
■
■
The differential inputs operate from rail-to-rail and the
single-ended output swings from rail-to-rail. The LTC6915
can be used in single power supply applications as low as
2.7V, or with dual ±5V supplies. The LTC6915 is available
in a 16-lead SSOP package and a 12-lead DFN surface
mount package.
Thermocouple Amplifiers
Electronic Scales
Medical Instrumentation
Strain Gauge Amplifier
High Resolution Data Acquisition
, LTC and LT are registered trademarks of Linear Technology Corporation.
U
TYPICAL APPLICATIO
Differential Bridge Amplifier with Gain Programmed through the Serial Interface
LTC6915 SSOP PACKAGE
3 IN +
+
OUT 15
3V
2 IN
_
CS
CH
–
SENSE 14
CF
R < 10k
RESISTOR
ARRAY
REF 13
11 PARALLEL_SERIAL
MUX
µP
TO OTHER
DEVICES
6 CS(D0)
7 DIN(D1)
8 CLK(D2)
9 DOUT(D3)
4-BIT
LATCH
HOLD_THRU 5
V+
16
3V
0.1µF
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
8-BIT
SHIFT-REGISTER
SHDN
DGND
V
1
10
– 4
6915 TA01
6915f
1
LTC6915
W W
U
W
ABSOLUTE
AXI U RATI GS
(Note 1)
Total Supply Voltage (V + to V –) ............................... 11V
Input Current ...................................................... ±10mA
|VIN+ – VREF| ....................................................... 5.5V
|VIN– – VREF| ....................................................... 5.5V
|V+ – VDGND| ....................................................... 5.5V
|VDGND – V –| ....................................................... 5.5V
Digital Input Voltage ......................................... V – to V +
Operating Temperature Range
LTC6915C .............................................–0°C to 70°C
LTC6915I .............................................–40°C to 85°C
LTC6915H .........................................–40°C to 125°C
Junction Temperature
(GN Package) ................................................... 150°C
(DFN Package).................................................. 125°C
Storage Temperature
(GN Package) ....................................–65°C to 150°C
(DFN Package)...................................–65°C to 125°C
Lead Temperature (Soldering 10 sec)................... 300°C
U
W
U
PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
TOP VIEW
IN–
1
12 V +
IN+
2
11 OUT
V–
3
10 REF
CS(D0)
4
9
PARALLEL_SERIAL
8
DGND
7
DOUT(D3)
DIN(D1)
CLK(D2)
5
6
DE12 PACKAGE
12-LEAD (4mm × 3mm) PLASTIC DFN
UNDERSIDE METAL CONNECTED TO V–
TJMAX = 125°C, θJA = 160°C/W
ORDER PART
NUMBER
TOP VIEW
SHDN 1
LTC6915CDE
LTC6915IDE
IN – 2
15 OUT
IN + 3
14 SENSE
V– 4
HOLD_THRU 5
DFN PART
MARKING
16
V+
13 REF
12 NC
CS(D0) 6
11 PARALLEL_SERIAL
DIN(D1) 7
10 DGND
CLK(D2) 8
9
6915
6915I
LTC6915CGN
LTC6915IGN
LTC6915HGN
GN PART
MARKING
DOUT(D3)
GN PACKAGE
16-LEAD NARROW PLASTIC SSOP
6915
6915I
6915H
TJMAX = 150°C, θJA = 135°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
SYMBOL
V+ = 3V, V –
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
0
0.075
%
= 0V, VREF = 200 mV
Gain Error (Note 2)
AV = 1 (RL =10k)
●
–0.075
Gain Error (Note 2)
AV = 2 to 32 (RL = 10k)
●
–0.5
0
0.5
%
Gain Error (Note 2)
AV = 64 to 1024 (RL = 10k)
●
–0.6
–0.1
0.6
%
Gain Error (Note 2)
AV = 2048, 4096 (RL = 10k)
●
–1
–0.2
1.0
%
Gain Nonlinearity
AV = 1
●
3
15
ppm
Input Offset Voltage (Note 3)
VCM = 200mV
–3
±10
µV
Average Input Offset Drift (Note 3)
TA = –40°C to 85°C
TA = 85°C to 125°C
●
●
±50
±100
nV/°C
nV/°C
IB
Average Input Bias Current (Note 4)
VCM = 1.2V
●
5
10
nA
IOS
Average Input Offset Current (Note 4)
VCM = 1.2V
●
1.5
3
nA
VOS
6915f
2
LTC6915
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V+ = 3V, V – = 0V, VREF = 200 mV
CMRR
Common Mode Rejection Ratio
AV = 1024, VCM = 0V to 3V, LTC6915C
AV = 1024, VCM = 0.1V to 2.9V, LTC6915I
AV = 1024, VCM = 0V to 3V, LTC6915I
AV = 1024, VCM = 0.1V to 2.9V, LTC6915H
AV = 1024, VCM = 0V to 2.97V, LTC6915H
●
●
●
●
●
100
100
95
100
85
119
119
119
dB
dB
dB
dB
dB
PSRR
Power Supply Rejection Ratio (Note 5)
VS = 2.7V to 6V
●
110
116
dB
Output Voltage Swing High
(Referenced to V–)
Sourcing 200µA
Sourcing 2mA
●
●
2.95
2.75
2.98
2.87
V
V
Output Voltage Swing Low
(Referenced to V–)
Sinking 200µA
Sinking 2mA
●
●
18
130
50
300
mV
mV
Supply Current, Parallel Mode
No Load at OUT, VCM = 200mV
●
0.88
1.3
mA
Supply Current, Serial Mode (Note 6)
No Load at OUT, Capacitive Load at
DOUT (CL) = 15pF, Continuous CLK
Frequency = 4MHz, CS= LOW,
Gain Control Code = 0001
●
1.1
1.65
mA
Supply Current Shutdown
VSHDN = 2.7V (Hardware Shutdown)
VSHDN = 1V, Gain Control Code = 0000
(Software Shutdown )
●
●
1
125
4
180
µA
µA
SHDN Input High
●
SHDN Input Low
●
2.7
1
V
V
SHDN and HOLD_THRU Input Current (Note 2)
●
5
µA
Internal Op Amp Gain Bandwidth
200
kHz
Slew Rate
0.2
V/µs
–0.5
3
kHz
Internal Sampling Frequency
V+ = 5V, V– = 0V, VREF = 200mV
VOS
Gain Error (Note 2)
AV = 1 (RL = 10k)
●
–0.075
0
0.075
%
Gain Error (Note 2)
AV = 2 to 32 (RL= 10k)
●
–0.5
0
0.5
%
Gain Error (Note 2)
AV = 64 to 1024 (RL = 10k)
●
–0.6
–0.1
0.6
%
Gain Error (Note 2)
AV = 2048, 4096 (RL = 10k)
●
–1
–0.2
1
%
Gain Nonlinearity
AV = 1
●
3
15
ppm
Input Offset Voltage (Note 3)
VCM = 200mV
Average Input Offset Drift (Note 3)
TA = –40°C to 85°C
TA = 85°C to 125°C
●
–3
±10
µV
±50
±100
nV/°C
nV/°C
Average Input Bias Current (Note 4)
VCM = 1.2V
●
5
10
nA
IOS
Average Input Offset Current (Note 4)
VCM = 1.2V
●
1.5
3
nA
CMRR
Common Mode Rejection Ratio
AV = 1024, VCM = 0V to 5V, LTC6915C
AV = 1024, VCM = 0.1V to 4.9V, LTC6915I
AV = 1024, VCM = 0V to 5V, LTC6915I
AV = 1024, VCM = 0.1V to 4.9V, LTC6915H
AV = 1024, VCM = 0V to 4.97V, LTC6915H
●
●
●
●
●
PSRR
Power Supply Rejection Ratio (Note 5)
VS = 2.7V to 6V
●
Output Voltage Swing High
Sourcing 200µA
Sourcing 2mA
●
●
Output Voltage Swing Low
Sinking 200µA
Sinking 2mA
●
●
105
105
95
100
85
125
125
125
dB
dB
dB
dB
dB
110
116
dB
4.95
4.80
4.99
4.93
V
V
17
120
50
300
mV
mV
6915f
3
LTC6915
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
SYMBOL
V+
PARAMETER
= 5V, V – = 0V, V
CONDITIONS
MIN
VOS
MAX
UNITS
REF = 200mV
Supply Current, Parallel Mode
No Load at OUT, VCM = 200mV
●
0.95
1.48
mA
Supply Current, Serial Mode (Note 6)
No Load at OUT, Capacitive Load at
DOUT (CL) = 15pF, Continuous CLK
Frequency = 4MHz, CS = LOW,
Gain Control Code = 0001
●
1.4
2
mA
Supply Current, Shutdown
VSHDN = 4.5V (Hardware Shutdown)
VSHDN = 1V, Gain Control Code = 0000
(Software Shutdown)
●
●
2
135
10
200
µA
µA
1
V
SHDN Input High
●
SHDN Input Low
●
SHDN and HOLD_THRU Input Current (Note 2)
●
4.5
V
5
µA
Internal Op Amp Gain Bandwidth
200
kHz
Slew Rate
0.2
V/µs
3
kHz
Internal Sampling Frequency
V + = 5V, V–
TYP
= –5V, VREF = 0V
Gain Error (Note 2)
AV = 1 (RL = 10k)
●
–0.075
0
0.075
%
Gain Error (Note 2)
AV = 2 to 32 (RL = 10k)
●
Gain Error (Note 2)
AV = 64 to 1024 (RL = 10k)
●
–0.5
0
0.5
%
–0.6
–0.1
0.6
%
Gain Error (Note 2)
AV = 2048, 4096 (RL = 10k)
●
Gain Nonlinearity
AV = 1
●
–1
–0.2
1
%
3
15
ppm
±20
nV
nV/°C
nV/°C
VCM = 0mV
Average Input Offset Drift (Note 3)
TA = –40°C to 85°C
TA = 85°C to 125°C
●
●
Average Input Bias Current (Note 4)
VCM = 1V
●
4
10
nA
Average Input Offset Current (Note 4)
VCM = 1V
●
1.5
3
nA
CMRR
Common Mode Rejection Ratio
AV = 1024, VCM = –5V to 5V, LTC6915C
AV = 1024, VCM = –4.9V to 4.9V, LTC6915I
AV = 1024, VCM = –5V to 5V, LTC6915I
AV = 1024, VCM = –4.9V to 4.9V, LTC6915H
AV = 1024, VCM = –5V to 4.97V, LTC6915H
●
●
●
●
●
PSRR
Power Supply Rejection Ratio (Note 5)
VS = 2.7V to 11V
●
Output Voltage Swing High
Sourcing 200µA
Sourcing 2mA
●
●
Output Voltage Swing Low
Sinking 200µA
Sinking 2mA
●
●
–4.98
–4.90
–4.92
–4.70
mV
mV
Supply Current, Parallel Mode
No Load, VCM = 200mV
●
1.1
1.6
mA
Supply Current, Serial Mode (Note 6)
No Load at OUT, Capacitive Load at
DOUT (CL) = 15pF, Continuous CLK
Frequency = 4MHz, CS = LOW,
Gain Control Code = 0001
●
1.73
2.48
mA
Supply Current, Shutdown
VSHDN = 4V (Hardware Shutdown)
VSHDN = 1V, Gain Control Code = 0000
(Software Shutdown )
●
●
160
25
240
µA
µA
IOS
5
±50
±100
Input Offset Voltage (Note 3)
SHDN Input High
●
SHDN Input Low
●
105
105
100
100
90
123
123
123
dB
dB
dB
dB
dB
110
116
dB
4.97
4.90
4.99
4.96
V
V
4
V
1
V
6915f
4
LTC6915
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V + = 5V, V– = –5V, VREF = 0V
SHDN and HOLD_THRU Input Current (Note 2)
5
●
µA
Internal Op Amp Gain Bandwidth
200
kHz
Slew Rate
0.2
V/µs
3
kHz
Internal Sampling Frequency
Digital I/O, All Digital I/O Voltage Referenced to DGND
VIH
Digital Input High Voltage
●
VIL
Digital Input Low Voltage
●
2.0
V
0.8
V+ – 0.3
V
VOH
Digital Output High Voltage
Sourcing 500µA
●
VOL
Digital Output Low Voltage
Sinking 500µA
●
0.3
V
Digital Input Leakage
V+ = 5V, V– = –5V, V
●
±2
µA
Timing, V + = 2.7V to 4.5V, V –
IN = 0V to 5V
V
= 0V (Note 7)
t1
DIN Valid to CLK Setup
●
t2
DIN Valid to CLK Hold
●
0
ns
t3
CLK Low
●
100
ns
t4
CLK High
●
100
ns
t5
CS/LD Pulse Width
●
60
ns
t6
LSB CLK to CS/LD
●
60
ns
t7
CS/LD Low to CLK
●
30
t8
DOUT Output Delay
t9
CLK Low to CS/LD Low
CL = 15pF
60
ns
ns
125
●
ns
●
0
ns
Timing, V+ = 4.5V to 5.5V, V – = 0V (Note 7)
t1
DIN Valid to CLK Setup
●
30
ns
t2
DIN Valid to CLK Hold
●
0
ns
t3
CLK Low
●
50
ns
t4
CLK High
●
50
ns
t5
CS/LD Pulse Width
●
40
ns
t6
LSB CLK to CS/LD
●
40
ns
t7
CS/LD Low to CLK
●
20
ns
t8
DOUT Output Delay
t9
CLK Low to CS/LD Low
CL = 15pF
85
●
ns
●
0
ns
Timing, Dual ±4.5V to ±5.5V Supplies (Note 7)
t1
DIN Valid to CLK Setup
●
30
ns
t2
DIN Valid to CLK Hold
●
0
ns
t3
CLK High
●
50
ns
t4
CLK Low
●
50
ns
t5
CS/LD Pulse Width
●
40
ns
t6
LSB CLK to CS/LD
●
40
ns
t7
CS/LD Low to CLK
●
20
ns
t8
DOUT Output Delay
t9
CLK Low to CS/LD Low
CL = 15pF
85
●
●
0
ns
ns
6915f
5
LTC6915
ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: These parameters are tested at ±5V supply; at 3V and 5V supplies
they are guaranteed by design.
Note 3: These parameters are guaranteed by design. Thermocouple effects
preclude measurement of these voltage levels in high speed automatic test
systems. VOS is measured to a limit set by test equipment capability.
Note 4: If the total source resistance is less than 10k, no DC errors result
from the input bias current or mismatch of the input bias currents or the
mismatch of the resistances connected to IN – and IN+.
Note 5: The PSRR measurement accuracy depends on the proximity of the
power supply bypass capacitor to the device under test. Because of this,
the PSRR is 100% tested to relaxed limits at final test. However, their
values are guaranteed by design to meet the data sheet limits.
Note 6: Supply current is dependent on the clock frequency. A higher
clock frequency results in higher supply current.
Note 7: Guaranteed by design, not subject to test.
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Input Offset Voltage vs Input
Common Mode
–4
–6
AV = 4096
–8
AV = 256
–10
AV = 16
–12
AV = 1
–2
–8
AV = 256
–10
–12
AV = 16
–14
–16
–16
–18
2.5
1.0
1.5
2.0
0.5
INPUT COMMON MODE VOLTAGE (V)
AV = 4096
–6
6915 G01
5
0
TA = 125°C
–5
TA = 85°C
TA = 25°C
–15
–20
TA = 70°C
–6
AV = 256
AV = 16
–8
–10
–14
AV = 1
–5 –4 –3 –2 –1 0 1 2 3 4
INPUT COMMON MODE VOLTAGE (V)
2.5
1.0
1.5
2.0
0.5
INPUT COMMON MODE VOLTAGE (V)
15
10
5
TA = 125°C
0
–5
TA = 85°C
TA = 25°C
–10
TA = 70°C
6915 G04
–20
0
10
5
VS = ±5V
VREF = 0V
AV = 16
TA = –50°C
TA = 25°C
TA = 125°C
0
–5
–10
TA = 85°C
TA = 70°C
–15
–20
TA = –50°C
3.0
5
6915 G03
20
–15
TA = –50°C
0
AV = 4096
–4
Input Offset Voltage vs Input
Common Mode
VS = 5V
VREF = 0.2V
AV = 16
15
INPUT OFFSET VOLTAGE (µV)
INPUT OFFSET VOLTAGE (µV)
20
10
–10
0
–2
Input Offset Voltage vs Input
Common Mode
VS = 3V
VREF = 0.2V
AV = 16
15
2
6915 G02
Input Offset Voltage vs Input
Common Mode
20
4
–12
AV = 1
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
INPUT COMMON MODE VOLTAGE (V)
3.0
VS = ±5V
VREF = 0V
TA = 25°C
6
–4
–14
0
8
VS = 5V
VREF = 0.2V
TA = 25°C
0
INPUT OFFSET VOLTAGE (µV)
INPUT OFFSET VOLTAGE (µV)
–2
2
Input Offset Voltage vs Input
Common Mode
INPUT OFFSET VOLTAGE (µV)
VS = 3V
VREF = 0.2V
TA = 25°C
INPUT OFFSET VOLTAGE (µV)
0
Input Offset Voltage vs Input
Common Mode
2
3
1
4
INPUT COMMON MODE VOLTAGE (V)
5
6915 G05
–25
–5
3
–3
1
–1
INPUT COMMON MODE VOLTAGE (V)
5
6915 G06
6915f
6
LTC6915
U W
TYPICAL PERFOR A CE CHARACTERISTICS
20
RS = 15k
–20
RS = 20k
–30 VS = 3V
RS
VREF = 0.2V
+
R+ = R– = RS
CIN
–40 CIN < 100pF
–
AV = 16
RS
TA = 25°C
–50
2.5
0
1.0
1.5
2.0
0.5
INPUT COMMON MODE VOLTAGE (V)
10
RS = 10k
RS = 15k
0
RS = 5k
RS
–10
+
CIN
–20
3.0
1
3
4
2
INPUT COMMON MODE VOLTAGE (V)
Error Due to Input RS Mismatch vs
Input Common Mode
Error Due to Input RS Mismatch vs
Input Common Mode
ADDITIONAL OFFSET (µV)
R+ = 15k, R– = 0k
–20
R+
–40
+
CIN
R
0
R+ = 0k, R– = 15k
0
+
–
R = 15k, R = 0k
–10
R+
–20
+
–
–30
R
–40
3.0
Offset Voltage vs Temperature
VS = ±5V
VREF = 0V
20 CIN < 100pF
AV = 16
TA = 25°C
10
5
R+ = 0k, R– = 20k
R+ = 0k, R– = 15k
0
–10
R+
–20
CIN
R+ = 15k, R– = 0k
R+ = 20k, R– = 0k
+
–
R–
VOS vs REF (Pin 13)
+
20
VIN = VIN = REF
AV = 16
TA = 25°C
10
5
–5 –4 –3 –2 –1 0 1 2 3 4
INPUT COMMON MODE VOLTAGE (V)
6915 G12
VOS vs REF (Pin 13)
2
–
VIN+ = VIN– = REF
AV = 16
TA = 25°C
10
–3
VS = ±5V
VS = 5V
VS = 3V
VOS (µV)
0
5
VOS (µV)
INPUT OFFSET VOLTAGE (µV)
–3
1
3
–1
INPUT COMMON MODE VOLTAGE (V)
6915 G11
15
–8
VS = 5V
VS = 3V
–13
–5
–10
–50
–5
–30
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
INPUT COMMON MODE VOLTAGE (V)
6915 G10
0
–
RS
R+ = 20k, R– = 0k
–
2.5
1.0
1.5
2.0
0.5
INPUT COMMON MODE VOLTAGE (V)
+
Error Due to Input RS Mismatch vs
Input Common Mode
R+ = 0k, R– = 20k
10
R+ = 20k, R– = 0k
–
RS
–10
30
VS = 5V
30 VREF = 0.2V
CIN < 100pF
20 AV = 16
TA = 25°C
CIN
–
–60
RS = 5k
6915 G09
40
0
RS = 15k
0
–20
5
6915 G08
VS = 3V
= 0.2V
V
60 REF
CIN < 100pF
R+ = 0k, R– = 20k
A = 16
40 V
TA = 25°C
R+ = 0k, R– = 15k
20
RS = 10k
CIN
6915 G07
80
10
RS = 20k
–
RS
0
VS = ±5V
VREF = 0V
R+ = R– = RS
CIN < 100pF
AV = 16
TA = 25°C
RS = 20k
ADDITIONAL OFFSET (µV)
ADDITIONAL OFFSET (µV)
RS = 10k
–10
ADDITIONAL OFFSET (µV)
RS = 5k
0
ADDITIONAL OFFSET (µV)
20
VS = 5V
VREF = 0.2V
R+ = R– = RS
CIN < 100pF
AV = 16
TA = 25°C
ADDITIONAL OFFSET (µV)
10
–80
Error Due to Input RS vs Input
Common Mode
Error Due to Input RS vs Input
Common Mode
Error Due to Input RS vs Input
Common Mode
VS = 10V
–10
–20
–30
–25
50
25
0
75
TEMPERATURE (°C)
100
125
6915 G13
–18
0
0.5
1.0
1.5
2.0
2.5
VREF (V)
3.0
3.5
4.0
6915 G14
–40
0
1
2
3
4
5 6
VREF (V)
7
8
9
10
6915 G15
6915f
7
LTC6915
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Gain Nonlinearity at Gain = 1
(Gain Nonlinearity Decreases for
Gain > 1)
Supply Current vs Supply Voltage
VS = ±2.5V
4 VCM = VREF = 0V
R = 10k
3 AL = 1
V
2 TA = 25°C
–1
–2
120
TA = 85°C
1.05
TA = 125°C
0.95
TA = 0°C
0.90
0.80
–4
0.75
+
1.8
0.70
2.4
70
2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5 11.5
SUPPLY VOLTAGE (V)
200
VS = 5V
150
VS = 3V
100
50
10
100
1000
FREQUENCY (Hz)
3
VS = 3V
TA = 25°C
2
1
0
–1
–2
–3
1
10000
0
2
4
6
TIME (s)
5
4
OUTPUT VOLTAGE SWING (V)
VS = 3V, SOURCING
2.0
1.5
0.5
0
0.01
VS = 3V, SINKING
VS = 5V, SINKING
1
0.1
OUTPUT CURRENT (mA)
–1
–2
VS = ±5V
TA = 25°C
6915 G22
2
4
6
TIME (s)
8
SOURCING
7
2
1
0
–1
–2
6
VS = 5V
dVOUT = 1V
G ≤ 100
TA = 25°C
5
4
3
2
–3
–5
0.01
10
8
Low Gain Settling Time vs
Settling Accuracy
3
–4
10
0
6915 G21
SETTLING TIME (ms)
VS = 5V, SOURCING
2.5
1.0
0
Output Voltage Swing vs
Output Current
3.5
3.0
1
6915 G20
Output Voltage Swing vs
Output Current
4.0
VS = 5V
TA = 25°C
2
–3
10
8
6915 G19
TA = 25°C
1000
Input Referred Noise in
10Hz Bandwidth
INPUT REFFERED NOISE VOLTAGE (µV)
INPUT REFFERED NOISE VOLTAGE (µV)
INPUT REFERRED NOISE DENSITY (nV/√Hz)
VS = ±5V
10
100
FREQUENCY (Hz)
1
6915 G18
3
250
R+ = 0k, R– = 10k
6915 G17
Input Referred Noise in
10Hz Bandwidth
AV = 16
TA = 25°C
–
R–
Input Voltage Noise Density
vs Frequency
OUTPUT VOLTAGE SWING (V)
R+
TA = –50°C
6915 G16
4.5
R+ = 10k, R– = 0k
80
–5
–2.4 –1.8 –1.2 –0.6 0
0.6 1.2
OUTPUT VOLTAGE (V)
5.0
R+ = R– = 10k
100
90
0.85
–3
R+ = R– = 1k
110
1.00
CMRR (db)
0
0
VS = 3V, 5V, ±5V
VIN = 1VP-P
1.10
1
300
CMRR vs Frequency
130
1.15
SUPPLY CURRENT (mA)
GAIN NONLINEARITY (ppm)
5
1
SINKING
1
0.1
OUTPUT CURRENT (mA)
10
6915 G23
0
0.0001
0.01
0.001
SETTLING ACCURACY (%)
0.1
6915 G24
6915f
8
LTC6915
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Internal Clock Frequency vs
Supply Voltage
Settling Time vs Gain
35
20
15
10
3.30
TA = 125°C
3.25
TA = 85°C
3.20
3.15
5
0
ADDITIONAL GAIN ERROR (%)
25
0.1
3.35
CLOCK FREQUENCY (kHz)
SETTLING TIME (ms)
3.40
VS = 5V
dVOUT = 1V
0.1% ACCURACY
TA = 25°C
30
Additional Gain Error vs Load
Resistance
10
100
GAIN (V/V)
1000
10000
3.10
2.5
4.5
6.5
8.5
SUPPLY VOLTAGE (V)
6915 G25
U
U
U
PI FU CTIO S
AV = 16
–0.1
AV = 256
–0.2
–0.3
AV = 4096
TA = –55°C
TA = 25°C
1
0
10.5
6915 G26
–0.4
0
2
6
8
4
LOAD RESISTANCE RL (k)
10
6915 G27
(DFN/GN Packages)
IN– (Pin 1/Pin 2): Inverting Analog Input.
SHDN (Pin 1 GN Package Only): Shutdown Pin. The IC is
shut down when SHDN is tied to V +. An internal current
source pulls this pin to V – when floating.
IN+ (Pin 2/Pin 3): Noninverting Analog Input.
V– (Pin 3/Pin 4): Negative Supply.
CS(D0) (Pin 4/Pin 6): TTL Level Input. When in serial
control mode, this pin is the chip select input (active low);
in parallel control mode, this pin is the LSB of the parallel
gain control code.
DIN(D1) (Pin 5/Pin 7): TTL Level Input. When in serial
control mode, this pin is the serial input data; in parallel
mode, this pin is the second LSB of the parallel gain
control code.
HOLD_THRU (Pin 5 GN Package Only): TTL Level Input
for Parallel Control Mode. When HOLD_THRU is high, the
parallel data is latched in an internal D-latch.
CLK(D2) (Pin 6/Pin 8): TTL Level Input. When in serial
control mode, this pin is the clock of the serial interface; in
parallel mode, this pin is the third LSB of the parallel gain
control code.
DOUT(D3) (Pin 7/Pin 9): TTL Level Input. When in serial
control mode, this pin is the output of the serial data; in
parallel mode, this pin is the MSB of the 4-bit parallel gain
control code. In parallel mode operation, if the data in to
DOUT (Pin 9) is from a voltage source greater than V+ (Pin
12), then connect a resistor between the voltage source
and DOUT to limit the current into Pin 9 to 5mA or less.
DGND (Pin 8/Pin 10): Digital Ground.
PARALLEL_SERIAL (Pin 9/Pin 11): Interface Selection
Input. When tied to V+, the interface is in parallel mode, i.e.,
the PGA gain is defined by the parallel codes (D3 ~ D0), i.e.,
CS(D0), DATA(D1), CLK(D2), and D OUT(D3). When
PARALLEL_SERIAL pin is tied to V –, the PGA gain is set
by the serial interface.
REF (Pin 10/Pin 13): Voltage Reference for PGA output.
OUT (Pin 11/Pin 15): Amplifier Output. The typical current
sourcing/sinking of the OUT pin is 1mA. For minimum gain
error, the load resistance should be 1k or greater (refer to
the Output Voltage Swing vs Output Current and Gain
Error vs Load Resistance in the Typical Performance
Characteristics section).
V+ (Pin 12/Pin 16): Positive Supply.
SENSE (Pin 14 GN Package Only): Sense Pin. When the
PGA drives a low resistance load and the interconnect
resistance between the OUT pin and the load is not
negligible, tying the SENSE pin as close as possible to the
load can improve the gain accuracy.
6915f
9
LTC6915
W
BLOCK DIAGRA S
(GN Package Only)
IN +
3
+
15
CS
IN –
CH
2
–
14
CF
OUT
SENSE
GAIN
CONTROL
RESISTOR
ARRAY
13
PARALLEL_SERIAL
11
CS(D0)
DIN(D1)
CLK(D2)
DOUT(D3)
5
4-BIT
LATCH
MUX
1
6
7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
8-BIT
SHIFT-REGISTER
8
16
10
4
9
REF
HOLD_THRU
SHDN
V+
DGND
V–
6915 BD01
(DFN Package Only)
IN +
2
+
11
CS
IN –
1
CH
OUT
–
CF
GAIN
CONTROL
RESISTOR
ARRAY
10
PARALLEL_SERIAL
9
MUX
CS(D0)
DIN(D1)
CLK(D2)
DOUT(D3)
4
5
6
REF
4-BIT
LATCH
DGND
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
8-BIT
SHIFT-REGISTER
12
8
3
7
V+
DGND
V–
6915 BD02
6915f
10
LTC6915
WU
W
TI I G DIAGRA
Timing Diagram of the Serial Interface
t4
t1
t2
t6
t3
t7
CLK
t9
D3
DIN
D2
D1
D0
D7 • • • • D4
D3
t5
CS/LD
t8
DOUT
D4
D3
D2
PREVIOUS BYTE
D1
D0
D7 • • • • D4
CURRENT BYTE
D3
6915 TD
U
OPERATIO
Theory of Operation (Refer to Block Diagrams)
The LTC6915 uses an internal capacitor (CS) to sample a
differential input signal riding on a DC common mode
voltage (the sampling rate is 3kHz and the input switch-on
resistance is 1k to 2k, depending on the power supply
voltage). This capacitor’s charge is transferred to a second
internal hold capacitor (CH) translating the common mode
voltage of the input differential signal to that of REF pin.
The resulting signal is amplified by a zero-drift op amp in
the noninverting configuration. Gain control within the
amplifier occurs by switching resistors from a matched
resistor array. The LTC6915 has 14 levels of gain, controlled by the parallel or serial interface. A feedback
capacitor CF helps to reduce the switching noise. Due to
the input sampling, an LTC6915 may produce aliasing
errors for input signals greater than 1.5kHz (one half the
3kHz sampling frequency). However, if the input signal is
bandlimited to less than 1.5kHz then an LTC6915 is useful
as instrumentation or as a differential to single-ended AC
amplifier with programmable gain.
Parallel Interface
As shown in Figure 1, connecting PARALLEL_SERIAL to
V+ allows the gain control code to be set through the
parallel lines (D3, D2, D1, D0). When HOLD_THRU is low
(referenced to DGND) or floating, the parallel gain control
bits (D3 ~ D0) directly control the PGA gain. When
HOLD_THRU is high, the parallel gain control bits are read
into and held by a 4-bit latch. Any change at D3 ~ D0 will
not affect the PGA gain when HOLD_THRU is high. Note
that the DFN12 package does not have the HOLD_THRU
pin. Instead, it is tied to DGND internally. The DOUT(D3) pin
is bidirectional (output in serial mode, input in parallel
mode). In parallel mode, the voltage at DOUT(D3) cannot
exceed V+; otherwise, large currents can be injected to V+
through the parasitic diode (see Figure 2). Connecting a
10k resistor at the DOUT(D3) pin if parallel mode is selected
(see Figure 1) is recommended for current limiting.
Serial Interface
Connecting PARALLEL_SERIAL to V – allows the gain
control code to be set through the serial interface. When
CS is low, the serial data on DIN is shifted into an 8-bit shiftregister on the rising edge of the clock, with the MSB
transferred first (see Figure 3). Serial data on DOUT is
shifted out on the clock’s falling edge. A high CS will load
the 4 LSBs of the shift-register into a 4-bit D-latch, which
are the gain control bits. The clock is disabled internally
when CS is pulled high. Note: CLK must be low before CS
is pulled low to avoid an extra internal clock pulse.
6915f
11
LTC6915
U
OPERATIO
DOUT is always active in serial mode (never tri-stated). This
simplifies the daisy chaining of the multiple devices. DOUT
cannot be “wire-or” to other SPI outputs. In addition, DOUT
does not return to zero at the end of transmission, i.e.
when CS is pulled high.
A LTC6915 may be daisy-chained with other LTC6915s or
other devices having serial interfaces by connecting the
DOUT to the DIN of the next chip while CLK and CS remain
common to all chips in the daisy chain. The serial data is
clocked to all the chips then the CS signal is pulled
high to update all of them simultaneously. Figure 4
shows an example of two LTC6915s in a daisy chained SPI
configuration.
5V
1
2
VIN
LTC6915
V+
SHDN
IN –
OUT
3
IN+
SENSE
4
V–
REF
5
6
7
8
HOLD_THRU
NC
CS(D0)
P/S
DIN(D1)
DGND
CLK(D2) DOUT(D3)
5V
LTC6915
1
16
0.1µF
2
15
VOUT
14
3
VIN
13
4
12
5
11
10
µP
9
V+
SHDN
D0
6
D1
7
D2
8
IN–
OUT
IN+
SENSE
V–
REF
HOLD_THRU
NC
CS(D0)
P/S
DIN(D1)
DGND
CLK(D2) DOUT(D3)
16
0.1µF
15
VOUT
14
13
12
11
10
10k
9
D3
PARALLEL GAIN CONTROL CODE = 1010
VOUT = 29 VIN = 512VIN
GAIN IS SET BY MICROPROCESSOR. A 10k RESISTOR
ON DOUT(D3) PROTECT THE DEVICE WHEN VD3 > V +
6915 F01
Figure 1. PGA in the Parallel Control Mode
V+
4-BIT GAIN
CONTROL CODE
4-BIT
LATCH
CS
DOUT(D3)
DGND
(INTERNAL
NODE)
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
8-BIT
SHIFT-REGISTER
DIN
V–
DOUT
6915 F01
CLK
(D3)
6915 F02
Figure 2. Bidirectional Nature of DOUT/D3 Pin
Figure 3. Diagram of Serial Interface
(MSB First Out)
6915f
12
LTC6915
U
OPERATIO
1
0.1µF 2
VIN
3
4
–5V
0.1µF
5
CS
6
DIN
7
CLK
8
µP
LTC6915
SHDN #1
IN–
V+
OUT
IN+
SENSE
V–
REF
HOLD_THRU
NC
CS(D0)
P/S
DIN(D1)
DGND
CLK(D2) DOUT(D3)
16
15
1
0.1µF
0.1µF 2
VOUT
14
VIN
13
–5V
0.1µF
12
11
IN –
V+
OUT
3
IN+
SENSE
4
V–
REF
5
6
–5V
LTC6915
SHDN #2
10
7
9
8
HOLD_THRU
NC
CS(D0)
P/S
DIN(D1)
DGND
CLK(D2) DOUT(D3)
16
15
0.1µF
VOUT
14
13
12
11
–5V
10
9
DOUT
CLK
DIN
D15
D11
D10
D9
D8
D7
D3
D2
D1
D0
GAIN CODE FOR #1
GAIN CODE FOR #2
CS/LD
6915 F04
Figure 4. 2 PGAs in a Daisy Chain
The amplifier’s gain is set as follows:
D3, D2, D1, D0
Gain
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101~
1111
0
1
2
4
8
16
32
64
128
256
512
1024
2048
4096
Input Voltage Range
±5 Volt Operation
The input common mode voltage range of the LTC6915 is
rail-to-rail. However, the following equation limits the size
of the differential input voltage:
When using the LTC6915 with supplies over 5.5V, care
must be taken to limit the maximum difference between
any of the input pins (IN+ or IN– ) and the REF pin to 5.5V,
i.e.,
V – ≤ (VIN+ – VIN –) + VREF ≤ V+ – 1.3
Where VIN+ and VIN– are the voltage of the differential input
pins, V+ and V – are the positive and negative supply
voltages respectively and VREF is the voltage of REF pin. In
addition, VIN+ and VIN– must not exceed the power supply
voltages, i.e.,
V – < VIN+ < V+ and V – < VIN– < V+
|VIN + – VREF| < 5.5 and |VIN– – VREF| < 5.5
If not, the device will be damaged. For example, if rail-torail input operation is desired when the supplies are at ±5V,
the REF pin should be 0, ±0.5V. As a second example, if the
V+ pin is 10V, and the V – and REF pins are at 0, the inputs
should not exceed 5.5V.
6915f
13
LTC6915
U
OPERATIO
Settling Time
The sampling rate is 3kHz and the input sampling period
during which CS is charged to the input differential voltage,
VIN, is approximately 150µs. First assume that on each
input sampling period, CS is charged fully to VIN . Since CS
= CH (= 1000pF), a change in the input will settle to N bits
of accuracy at the op amp noninverting input after N clock
cycles or 333µs(N). The settling time at the OUT pin is also
affected by the internal op amp. Since the gain bandwidth
of the internal op amp is typically 200kHz, the settling time
is dominated by the switched-capacitor front end for gains
below 100 (see the Low Gain Settling Time vs Settling
Accuracy and the Settling Time vs Gain graphs in the
Typical Performance Characteristics section). In addition,
the worst case settling time after a device-enable (active
low on Pin 1 of a GN package) is equal to the settling due
to the gain plus the input settling time (333µs • N). For
example, if an LTC6915 is enabled with a logic high on
Pin 1 then, the maximum settling time to 10 bits of
accuracy (0.1%) and a gain equal to 100 is 8.33ms
([333µs • 1024] + 5ms).
Input Current
Whenever the differential input VIN changes, CH must be
charged up to the new input voltage via CS. This results in
an input charging current during each input sampling
period. Eventually, CH and CS will reach VIN and ideally, the
input current would go to zero for DC inputs.
In reality, there are additional parasitic capacitors which
disturb the charge on CS every cycle even if VIN is a DC
voltage. For example, the parasitic bottom plate capacitor
on CS must be charged from the voltage on the REF pin to
the voltage on the IN– pin every cycle. The resulting input
charging current decays exponentially during each input
sampling period with a time constant equal to RSCS. If the
voltage disturbance due to these currents settles before
the end of the sampling period, there will be no errors due
to source resistance or the source resistance mismatch
between IN+ and IN–. With RS less than 10k, no DC errors
occur due to input current mismatch.
In the Typical Performance Characteristics section of this
data sheet, there are curves showing the additional error
from non-zero source resistance in the inputs. If there
are no large capacitors across the inputs, the amplifier is
less sensitive to source resistance and source resistance
mismatch. When large capacitors are placed across the
inputs, the input charging currents are placed across the
inputs. The input charging currents described above result in larger DC errors, especially with source resistor
mismatches.
Power Supply Bypassing
In a dual supply operation, connect a 0.1µF bypass capacitor from each power supply pin (V+ and V–) to an analog
round plance surrounding an LTC6915. The bypass
capacitor trace to the supply pins must be less than
0.2 inches (an X7R or X5R capacitor type is recommended). In single supply operation, connect the V– pin to
the analog ground plane and bypass the V+ pin.
Shutdown Modes
The IC has two shutdown modes, hardware shutdown and
software shutdown. When SHDN is tied to V+, the IC is in
hardware shutdown mode. During this shutdown mode,
the gain setting digital interface (serial or parallel) and the
main op amp are both disabled, thus the PGA dissipates
very small supply current (see the Electrical Characteristic
table). When SHDN is floating, an internal current source
will pull it down to V –. The digital interface is turned on to
read the gain setting codes. The IC is in normal amplification mode as long as the gain control code is other than
0000. If the gain control code is 0000, the IC operates in
software shutdown mode, i.e., the main op amp is turned
off so that the PGA dissipates less power. The DFN
package does not have hardware shutdown.
Setting the Voltage at the REF Pin
The current coming out of the REF pin may affect the
reference voltage at the REF pin (VREF). If VREF is set by a
resistive divider then the VREF voltage is a function of the
VOUT voltage (see Figure 5). In order to minimize the VREF
variations, the total resistance of R1 plus R2 should be
much less than 32k (5k or less) or use a voltage reference
to set VREF.
LTC6915
+
OUT
V+
VOUT
–
R1
V
– VREF
IREF = OUT
32k
R = 32k
VREF
0.1µF
REF
V+ V
V– 
VREF = 
+ OUT +
 • (R1 R2 32k)
 R1 32k R2 
R2
V–
6915 F05
Figure 5
6915f
14
LTC6915
U
TYPICAL APPLICATIO
Multiplexing Two LTC6915’s
5V
5V
0.1µF
0.1µF
SHDN
V+
LTC6915
#1
IN–
OUT
Send a gain code of 0000 to one IC to set its output to a high
impedance state and send a gain code other than 0000 to
the second IC to set it for normal amplification. If both
devices are ON, the 200Ω resistors protect the outputs.
The sense pin connection maintains gain accuracy for
loads 1k or greater.
VIN1
VIN2
IN+
V
–5V
0.1µF
SENSE
–
REF
HOLD_THRU
DATA
µP
SELECT
(TTL
LEVELS) CLOCK
SHDN
V+
LTC6915
200Ω
#2
IN–
OUT
200Ω
–5V
0.1µF
NC
–5V
IN+
V
SENSE
–
VOUT
REF
NC
HOLD_THRU
CS
PAR_SER
CS
PAR_SER
DIN
DGND
DIN
DGND
CLK
DOUT
CLK
DOUT
–5V
6915 F06
Figure 6. A 2:1 Multiplexing Two LTC6915’s
with Daisy Chained Gain Control
U
PACKAGE DESCRIPTIO
DE/UE Package
12-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1695)
4.00 ±0.10
(2 SIDES)
7
0.58 ±0.05
3.40 ±0.05
1.70 ±0.05
2.24 ±0.05 (2 SIDES)
3.00 ±0.10
(2 SIDES)
1.70 ± 0.10
(2 SIDES)
PIN 1
NOTCH
PACKAGE
OUTLINE
(UE12/DE12) DFN 0802
6
0.25 ± 0.05
0.75 ±0.05
0.200 REF
3.30 ±0.05
(2 SIDES)
0.38 ± 0.10
12
R = 0.20
TYP
PIN 1
TOP MARK
0.25 ± 0.05
R = 0.115
TYP
0.50
BSC
3.30 ±0.10
(2 SIDES)
0.00 – 0.05
1
0.50
BSC
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING PROPOSED TO BE A VARIATION OF VERSION
(WGED) IN JEDEC PACKAGE OUTLINE M0-229
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
4. EXPOSED PAD SHALL BE SOLDER PLATED
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
16 15 14 13 12 11 10 9
.254 MIN
.009
(0.229)
REF
.150 – .165
.229 – .244
(5.817 – 6.198)
.0165 ± .0015
.150 – .157**
(3.810 – 3.988)
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
.0250 TYP
RECOMMENDED SOLDER PAD LAYOUT
1
.015 ± .004
× 45°
(0.38 ± 0.10)
.007 – .0098
(0.178 – 0.249)
.053 – .068
(1.351 – 1.727)
2 3
4
5 6
7
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
8
.004 – .0098
(0.102 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.008 – .012
(0.203 – 0.305)
.0250
(0.635)
BSC
GN16 (SSOP) 0502
6915f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC6915
U
TYPICAL APPLICATIO
V+
V+
9
X1
4MHz 10
C5
0.1µF
20
VDD
PIC16LF73
RC5/SDO
OSC1/
RC4/SDI/SDA
CLKIN
RC3/SCK/SCL
OSC2/
CLKOUT RC2/CCP1
RC1/T1OSI/CCP2
V+
1
BRIDGE
SENSOR
10k ZETEK
ZXM61P02F
R < 10K
16 MOSI
15 MISO
13 CS1
LTC6915
IN –
3
IN+
SENSE
V–
REF
5
12 CS2
V+
SHDN
2
4
14 SCLK
6
28
RB7
MCLR/
7
RAS/AN4/SS
VPP
6
RA4/T0CLK1
VSS
VSS
8
1
7
8
OUT
HOLD_THRU
NC
CS(D0)
PAR_SER
DIN(D1)
DGND
CLK(D2)
DOUT(D3)
C1
0.1µF
16
C2
0.1µF
15
1
14
VCC
13
2
REF+
12
SDO
LTC2431
3
REF –
4
IN+
CS
5
IN –
FO
SCK
11
10
1.25V
9
8
9
7
10
GND
19
6
0V
10k
MEASURE
STANDBY
V+
V+
CONTROL SIGNAL
4
C3
0.1µF
VIN
GND1
1
V+
VOUT
6
C3
1µF
LT1790-1.25
GND2
2
6915 F07
Figure 7. Bridge Amplifier with Programmable Gain and Analog to Digital Conversion.
(Standby Current Less than 100µA)
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1043
Dual Precision Instrumentation Switched-Capacitor
Building Block
Rail-to-Rail Input, 120dB CMRR
LTC1100
Precision Zero-Drift Instrumentation Amplifier
Fixed Gains of 10 or 100, 10µV Offset, 50pA Input Bias Current
LTC1101
Precision, Micropower, Single Supply
Instrumentation Amplifier
Fixed Gain of 10 or 100, IS < 105µA
LTC1167
Single Resistor Gain Programmable,
Precision Instrumentation Amplifier
Single Gains Set Resistor, G = 1 to 10,000
Low Noise: 7.5nV/√Hz
LTC1168
Low Power Single Resistor Gain Programmable,
Precision Instrumentation Amplifiers
IS = 530µA
LTC1789-1
Single Supply, Rail-to-Rail Output,
Micropower Instrumentation Amplifier
IS = 80µA Max
LTC2050
Zero-Drift Operational Amplifier
SOT-23 Package
LTC2051
Dual Zero-Drift Operational Amplifier
MS8 Package
LTC2052
Quad Zero-Drift Operational Amplifier
GN16 Package
LTC2053
Rail-to-Rail Input and Output, Zero-Drift Instrumentation
Amplifier with Resistor-Programmable Gain
MS8 Package, 10µV Max VOS, 50nV/°C Max Drift
LTC6800
Rail-to-Rail Input and Output, Instrumentation Amplifier
with Resistor-Programmable Gain
MS8 Package, 100µV Max VOS, 250nV/°C Max Drift
6915f
16
Linear Technology Corporation
LT/TP 0204 1K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507 ● www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2003