5-WIDE 5, 4, 4, 4, 2 OA/OAI GATE DESCRIPTION FEATURES ■ Max. propagation delay of 800ps ■ IEE min. of –55mA ■ Extended supply voltage option: VEE = –4.2V to –5.5V ■ Voltage and temperature compensation for improved noise immunity ■ Internal 75KΩ input pull-down resistors The SY100S318 is an ultra-fast 5-wide 5, 4, 4, 4, 2 OR/ AND gate with both true and complementary outputs, designed for use in high-performance ECL systems. The inputs on this device have 75KΩ pull-down resistors. D2a D1a 11 10 9 8 7 6 5 D2b D3b VEE VEES D4b 12 13 14 15 16 17 18 D1c D2c Top View PLCC J28-1 4 3 2 1 28 27 26 O O VCCA VCC VCC D2e D1e D2b D3b 1 24 23 22 21 20 19 18 D1b 2 3 17 16 D5a D4a 15 14 D3a D2a D4d 6 13 7 8 9 10 11 12 D1a O O O 4 5 VCCA Top View Flatpack F24-1 D1e D1b D2b D3b D4b D3c D4c D1d D2d D3d D2e VCC D1a D2a D3a D4a D5a D1c D4b VEE D2c D2d D3d D4d 19 20 21 22 23 24 25 BLOCK DIAGRAM D1c D2c D3c D4c D3a 70% faster than Fairchild 40% lower power than Fairchild Function and pinout compatible with Fairchild F100K Available in 24-pin CERPACK and 28-pin PLCC packages D5a D4a VEES D1b PIN CONFIGURATIONS D3c D4c D1d VEES ■ ■ ■ ■ SY100S318 O D1d D2d D3d D4d PIN NAMES Pin D1e D2e Function Dna – Dne Data Inputs (n = 1...5) O–O Data Outputs VEES VEE Substrate VCCA VCCO for ECL Outputs Rev.: G 1 Amendment: /0 Issue Date: July, 1999 SY100S318 Micrel LOGIC EQUATION O = (D1a + D2a + D3a + D4a + D5a) (D1b + D2b + D3b + D4b) (D1c + D2c + D3c + D4c) (D1d + D2d + D3d + D4d) (D1e + D2e) DC ELECTRICAL CHARACTERISTICS VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND Symbol Parameter IIH Input HIGH Current, All Inputs IEE Power Supply Current Min. Typ. Max. Unit Condition — — 200 µA VIN = VIH (Max.) –55 –41 –25 mA Inputs Open AC ELECTRICAL CHARACTERISTICS CERPACK VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND TA = 0°C Symbol Parameter TA = +25°C TA = +85°C Min. Max. Min. Max. Min. Max. Unit tPLH tPHL Propagation Delay Data to Output 300 900 300 900 300 900 ps tTLH tTHL Transition Time 20% to 80%, 80% to 20% 200 900 200 900 200 900 ps Condition PLCC VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND TA = 0°C Symbol Parameter TA = +25°C TA = +85°C Min. Max. Min. Max. Min. Max. Unit tPLH tPHL Propagation Delay Data to Output 300 800 300 800 300 800 ps tTLH tTHL Transition Time 20% to 80%, 80% to 20% 200 900 200 900 200 900 ps 2 Condition SY100S318 Micrel TIMING DIAGRAM 0.7 ± 0.1 ns 0.7 ± 0.1 ns INPUT –0.95V 80% 50% 20% –1.69V TRUE tPHL tPLH 50% tPLH OUTPUT tPHL 80% 50% 20% COMPLEMENT tTLH tTHL Propagation Delay and Transition Times NOTE: VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND PRODUCT ORDERING CODE Ordering Code Package Type Operating Range SY100S318FC F24-1 Commercial SY100S318JC J28-1 Commercial SY100S318JCTR J28-1 Commercial 3 SY100S318 Micrel 24 LEAD CERPACK (F24-1) Rev. 03 4 SY100S318 Micrel 28 LEAD PLCC (J28-1) Rev. 03 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. © 2000 Micrel Incorporated 5