8-BIT SHIFT REGISTER FEATURES D7 Q7 Q6 PIN CONFIGURATIONS P6 P7 VEES 11 10 9 8 7 6 5 P4 CP VEE VEES S0 PIN NAMES Parallel Inputs Q0 — Q7 Data Outputs P2 P1 VEE Substrate P0 D0 Q0 VCCO for ECL Outputs Q1 1 24 23 22 21 20 19 18 P5 2 3 17 16 P6 P7 15 14 D7 Q7 13 7 8 9 10 11 12 Q8 Top View Flatpack F24-1 4 5 6 Q2 VCCA 19 20 21 22 23 24 25 CP P0 — P7 Q3 Q2 Rev.: G 1 P4 Serial Inputs 18 Q4 Q5 D0 — D7 VCC VCC 28 27 26 S1 S0 VEE Select Inputs Top View PLCC J28-1 P3 S0 — S1 Q4 VCCA 14 15 16 17 Q3 VCC VCCA Clock Pulse Input Q5 3 2 1 Q1 CP VEES S1 P3 Function 4 13 D0 Q0 Label 12 VEES ■ ■ ■ ■ The SY100S341 offer eight D-type, edge-triggered flipflops with both individual inputs for parallel operation as well as serial inputs for bidirectional shifting, and are designed for use in high-performance ECL systems. Data is clocked into the flip-flops on the rising edge of the clock. The mode of operation is selected by two Select inputs (S0, S1) which determine if the device performs a shift, hold or parallel entry function, as described in the Truth Table. The inputs on these devices have 75KΩ pull-down resistors. Max. shift frequency of 600MHz Max. Clock to Q delay of 1200ps IEE min. of –150mA Industry standard 100K ECL levels Extended supply voltage option: VEE = –4.2V to –5.5V Voltage and temperature compensation for improved noise immunity Internal 75KΩ input pull-down resistors 70% faster than Fairchild 300K at lower power Function and pinout compatible with Fairchild F100K Available in 24-pin CERPACK and 28-pin PLCC packages P5 ■ DESCRIPTION P2 P1 P0 ■ ■ ■ ■ ■ SY100S341 Amendment: /0 Issue Date: July, 1999 SY100S341 Micrel BLOCK DIAGRAM D7 Q7 D Q C P7 Q6 Q D C P6 Q1 Q D C P1 PARALLEL LOAD Q0 SHIFT LEFT Q D SHIFT RIGHT HOLD C P0 DECODE S0 S1 D0 CP 2 SY100S341 Micrel TRUTH TABLE Inputs Function Outputs D7 D0 S1 S0 CP Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Load Register X X L L u P7 P6 P5 P4 P3 P2 P1 P0 Shift Left Shift Left X X L H L L H H u u Q6 Q6 Q5 Q5 Q4 Q4 Q3 Q3 Q2 Q2 Q1 Q1 Q0 Q0 L H Shift Right Shift Right L H X X H H L L u u L H Q7 Q7 Q6 Q6 Q5 Q5 Q4 Q4 Q3 Q3 Q2 Q2 Q1 Q1 Hold Hold Hold X X X X X X H X X H X X X H L No Change NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care u = LOW-to-HIGH Transition DC ELECTRICAL CHARACTERISTICS VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND Symbol Parameter IIH Input HIGH Current, All Inputs IEE Power Supply Current Min. Typ. Max. Unit Condition — — 200 µA VIN = VIH (Max.) –150 –102 –71 mA Inputs Open AC ELECTRICAL CHARACTERISTICS CERPACK VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND TA = 0°C Symbol Parameter TA = +25°C TA = +85°C Min. Max. Min. Max. Min. Max. Unit fshift Shift Frequency 600 — 600 — 600 — MHz tPLH tPHL Propagation Delay CP to Output 450 1200 450 1200 450 1200 ps tTLH tTHL Transition Time 20% to 80%, 80% to 20% 300 900 300 900 300 900 ps tS Set-up Time Dn, Pn Sn 300 600 — — 300 600 — — 300 600 — — Hold Time Dn, Pn Sn 300 0 — — 300 0 — — 300 0 — — — 600 — 600 — 600 tH tpw (H) Pulse Width HIGH, CP ps ps 3 ps Condition SY100S341 Micrel AC ELECTRICAL CHARACTERISTICS PLCC VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND TA = 0°C Symbol Parameter TA = +25°C TA = +85°C Min. Max. Min. Max. Min. Max. Unit fshift Shift Frequency 600 — 600 — 600 — MHz tPLH tPHL Propagation Delay CP to Output 450 1200 450 1200 450 1200 ps tTLH tTHL Transition Time 20% to 80%, 80% to 20% 300 900 300 900 300 900 ps tS Set-up Time Dn, Pn Sn 300 600 — — 300 600 — — 300 600 — — Hold Time Dn, Pn Sn 300 0 — — 300 0 — — 300 0 — — — 600 — 600 — 600 tH tpw (H) ps ps Pulse Width HIGH, CP TIMING DIAGRAMS 0.7 ± 0.1 ns 0.7 ± 0.1 ns –0.95V 80% 50% 20% CLOCK –1.69V tpw (H) 1/fshift –0.95V PARALLEL –1.69V tPLH tPHL OUTPUT tTLH tTHL Propagation Delay and Transition Times 4 ps Condition SY100S341 Micrel TIMING DIAGRAMS –0.95V Pn, Sn, Dn 50% –1.69V tH tS –0.95V CLOCK 50% –1.69V Set-up and Hold Times NOTES: 1. VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND. 2. tS is the minimum time before the transition of the clock that information must be present at the data input. 3. tH is the minimum time after the transition of the clock that information must remain unchanged at the data input. PRODUCT ORDERING CODE Ordering Code 5 Package Type Operating Range SY100S341FC F24-1 Commercial SY100S341JC J28-1 Commercial SY100S341JCTR J28-1 Commercial SY100S341 Micrel 24 LEAD CERPACK (F24-1) Rev. 03 6 SY100S341 Micrel 28 LEAD PLCC (J28-1) Rev. 03 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. © 2000 Micrel Incorporated 7