QUINT EXCLUSIVE OR/NOR GATE FEATURES SY100S307 DESCRIPTION ■ Max. propagation delay of 1000ps ■ IEE min. of –58mA ■ Extended supply voltage option: VEE = –4.2V to –5.5V ■ Voltage and temperature compensation for improved noise immunity ■ Internal 75KΩ input pull-down resistors ■ 50% faster than Fairchild 300K at lower power ■ Function and pinout compatible with Fairchild F100K ■ Available in 24-pin CERPACK and 28-pin PLCC packages The SY100S307 is an ultra-fast quint exclusive-OR/ NOR gate designed for use in high-performance ECL systems. A function output that is the wire-OR result of the exclusive-OR outputs is also available. The inputs on the device have 75KΩ pull-down resistors. Ob Ob Oa D1a Oa VEES D2a PIN CONFIGURATIONS 11 10 9 8 7 6 5 D1b D2b VEE VEES 12 13 14 15 16 17 D1c D2c D2d BLOCK DIAGRAM Top View PLCC J28-1 18 4 3 2 1 28 27 Oc 26 Od Oc VCCA VCC VCC F Oa D1b Ob D2b Ob D1c Oc D2c Oc D1d Od D2d Od D1e Oe D2e Oe 1 2 D2e 3 Oe 4 Oe 5 6 24 23 22 21 20 19 18 17 Top View 16 Flatpack 15 F24-1 14 13 7 8 9 10 11 12 Od Od D1b D2d D2c D1c VEE D2b Od D1d D1e D2a D1a Oa Oa Ob Ob Oc Oc D2a VCC VCCA Oa F D1a Oe Oe F D1e D2e VEES D1d 19 20 21 22 23 24 25 PIN NAMES Pin Function Dna – Dne Data Inputs (n-1...5) E Enable Input Oa – Oe Data Outputs Oa – Oe Complementary Data Outputs VEES VEE Substrate VCCA VCCO for ECL Outputs Rev.: G 1 Amendment: /0 Issue Date: July, 1999 SY100S307 Micrel LOGIC EQUATION F = (D1a ⊕ D2a) + (D1b ⊕ D2b) + (D1c ⊕ D2c) + (D1d ⊕ D2d) + (D1e ⊕ D2e). DC ELECTRICAL CHARACTERISTICS VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND Symbol IIH IEE Parameter Min. Typ. Max. — — — — 200 250 –58 –40 –27 Input HIGH Current D2a — D2e D2a — D2e Power Supply Current Unit Condition µA VIN = VIH (Max.) mA Inputs Open AC ELECTRICAL CHARACTERISTICS CERPACK VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND TA = 0°C Symbol Parameter TA = +25°C TA = +85°C Min. Max. Min. Max. Min. Max. Unit tPLH tPH2 Propagation Delay D2a — D2e to O, O 200 1100 200 1150 200 1100 ps tPLH tPHL Propagation Delay D1a — D1e to O, O 200 1000 200 950 200 1000 ps tPLH tPHL Propagation Delay Data to F 300 1525 300 1525 300 1525 ps tTLH tTHL Transition Time 20% to 80%, 80% to 20% 300 900 300 900 300 900 ps Condition PLCC VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND TA = 0°C Symbol Parameter TA = +25°C TA = +85°C Min. Max. Min. Max. Min. Max. Unit tPLH tPH2 Propagation Delay D2a — D2e to O, O 300 1000 300 1000 300 1000 ps tPLH tPHL Propagation Delay D1a — D1e to O, O 300 900 300 900 300 930 ps tPLH tPHL Propagation Delay Data to F 300 1425 300 1425 300 1425 ps tTLH tTHL Transition Time 3 20% to 80%, 80% to 20% 00 900 300 900 300 900 ps 2 Condition SY100S307 Micrel TIMING DIAGRAM 0.7 ± 0.1 ns 0.7 ± 0.1 ns –0.95V INPUT 80% 50% 20% –1.69V TRUE tPHL tPLH 50% tPLH OUTPUT tPHL 80% 50% 20% COMPLEMENT tTLH tTHL Propagation Delay and Transition Times NOTE: VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND PRODUCT ORDERING CODE Ordering Code Package Type Operating Range SY100S307FC F24-1 Commercial SY100S307JC J28-1 Commercial SY100S307JCTR J28-1 Commercial 3 SY100S307 Micrel 24 LEAD CERPACK (F24-1) Rev. 03 4 SY100S307 Micrel 28 LEAD PLCC (J28-1) Rev. 03 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. © 2000 Micrel Incorporated 5