9-BIT SHIFT REGISTER FEATURES SY10E142 SY100E142 DESCRIPTION ■ 700MHz min. shift frequency ■ Extended 100E VEE range of –4.2V to –5.5V The SY10/100E142 are high-speed 9-bit shift registers designed for use in new, high-performance ECL systems. The E142 can accept serial or parallel data to be shifted out in one direction as both serial and parallel outputs. The nine inputs, D0-D8, accept parallel input data, while S-IN accepts serial input data. The SEL (Select) control pin serves to determine the mode of operation, either SHIFT or LOAD. The shift direction is from bit 0 to bit 8. The input data has to meet the set-up time before being clocked into the nine input registers on the rising edge of CLK1 or CLK2. Shifting is also performed on the rising edge of either CLK1 or CLK2. The MR (Master Reset) control signal asynchronously resets all nine registers to a logic LOW when a logic HIGH is applied to MR. The E142 is designed for applications such as diagnostic scan registers, parallel-to-serial conversions and is also suitable for byte-wide parity. ■ ■ ■ ■ 9 bits wide for byte-parity applications Asynchronous Master Reset Dual clocks Fully compatible with industry standard 10KH, 100K ECL levels ■ Internal 75KΩ input pulldown resistors ■ Fully compatible with Motorola MC10E/100E142 ■ Available in 28-pin PLCC package BLOCK DIAGRAM S-IN 1 D0 0 D Q Q0 D Q Q1 D Q Q2 PIN CONFIGURATION 1 0 D3 D Q D5 VCCO Q8 17 15 Q6 VCC Q5 Q5 D Q Q6 28 16 PLCC TOP VIEW J28-1 1 14 VCCO D0 3 13 Q4 D1 4 12 Q3 2 5 0 1 D7 Q4 Q7 27 0 1 D6 D Q 18 CLK1 CLK2 VEE S-IN 0 1 D5 Q3 0 1 D4 D Q 26 6 7 8 9 10 11 Q0 Q1 Q2 1 25 24 23 22 21 20 19 MR D4 VCCO D2 SEL 1 D8 D7 D6 0 D2 D3 D1 PIN NAMES D Q Q7 Pin 0 Function D0-D8 Parallel Data Inputs S-IN Serial Data Input SEL Mode Select Input CLK1, CLK2 Clock Inputs CLK1 MR Master Reset CLK2 Q0-Q8 Data Outputs VCCO VCC to Output 1 D8 D Q Q8 0 SEL MR Rev.: C 1 Amendment: /1 Issue Date: February, 1998 SY10E142 SY100E142 Micrel TRUTH TABLE SEL MODE L LOAD H SHIFT DC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0°C Symbol Parameter TA = +25°C Min. Typ. Max. Min. Typ. IIH Input HIGH Current IEE Power Supply Current 10E 100E TA = +85°C Max. Min. Typ. Max. Unit Condition µA — mA — Max. Unit Condition MHz — ps — ps — ps — — — 150 — — 150 — — 150 — — 120 120 145 145 — — 120 120 145 145 — — 120 138 145 165 AC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0°C Symbol Parameter TA = +25°C Min. Typ. Max. Min. Typ. TA = +85°C Max. Min. Typ. fSHIFT Max. Shift Frequency 700 900 — 700 900 — 700 900 — tPLH tPHL Propagation Delay to Output CLK MR 600 600 800 800 1000 1000 600 600 800 800 1000 1000 600 600 800 800 1000 1000 tS Set-up Time D SEL 50 300 –100 150 — — 50 300 –100 150 — — 50 300 –100 150 — — Hold Time D SEL 300 75 100 –150 — — 300 75 100 –150 — — 300 75 100 –150 — — tRR Reset Recovery Time 900 700 — 900 700 — 900 700 — ps — tPW Minimum Pulse Width CLK, MR 400 — — 400 — — 400 — — ps — tskew Within-Device Skew — 75 — — 75 — — 75 — ps 1 tr tf Rise/Fall Time 20% to 80% 300 525 800 300 525 800 300 525 800 ps — tH NOTE: 1. Within-device skew is defined as identical transitions on similar paths through a device. PRODUCT ORDERING CODE Ordering Code Package Type Operating Range SY10E142JC J28-1 Commercial SY10E142JCTR J28-1 Commercial SY100E142JC J28-1 Commercial SY100E142JCTR J28-1 Commercial 2 SY10E142 SY100E142 Micrel 28 LEAD PLCC (J28-1) Rev. 03 3 SY10E142 SY100E142 Micrel MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. © 2000 Micrel Incorporated 4