6-BIT 2:1 MUX-LATCH FEATURES DESCRIPTION ■ ■ ■ ■ ■ ■ ■ The SY10/100E155 offer six 2:1 multiplexers followed by latches with single-ended outputs, designed for use in new, high-performance ECL systems. The two external latch-enable signals (LEN1 and LEN2) are gated through a logical OR operation before use as control for the six latches. When both LEN1 and LEN 2 are at a logic LOW, the latches are transparent, thus presenting the data from the multiplexers at the output pins. If either LEN1 or LEN2 (or both) are at a logic HIGH, the outputs are latched. The multiplexer operation is controlled by the SEL (Select) signal which selects one of the two bits of input data at each mux to be passed through. The MR (Master Reset) signal operates asynchronously to take all outputs to a logic LOW. 750ps max. LEN to output Extended 100E VEE range of –4.2V to –5.5V 700ps max. D to output Single-ended outputs Asynchronous Master Reset Dual latch-enables Fully compatible with industry standard 10KH, 100K ECL levels ■ Internal 75KΩ input pulldown resistors ■ Fully compatible with Motorola MC10E/100E155 ■ Available in 28-pin PLCC package SEL Q Q0 E N R D4b D D4a D3b MUX D5a D0a D3a NC VCCO PIN CONFIGURATION BLOCK DIAGRAM D0b SY10E155 SY100E155 25 24 23 22 21 20 19 D2a MUX D2b SEL D3a SEL D4a MUX D4b SEL D5a SEL Q Q2 E NR 18 Q5 27 17 VEE 1 Q4 VCC Q3 MR SEL 2 D0b 4 28 5 Q Q3 D Q Q4 16 PLCC TOP VIEW J28-1 15 6 7 8 9 13 Q2 VCCO 12 Q1 14 3 E NR 10 11 PIN NAMES E NR D MUX D5b D D MUX D3b E NR 26 LEN1 LEN2 Q0 SEL Q1 D2b VCCO D1b Q D1b D2a D MUX D0b D1a D1a D5b Q Pin Q5 E NR SEL LEN1 LEN2 MR Function D0a–D5a Input Data a D0b–D5b Input Data b SEL Data Select Input LEN1, LEN2 Latch Enables MR Master Reset Q0–Q5 Outputs VCCO VCC to Output Rev.: C 1 Amendment: /1 Issue Date: February, 1998 SY10E155 SY100E155 Micrel TRUTH TABLES SEL Data LEN1 LEN2 Latch H a L L Transparent L b H X Latched X H Latched DC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0°C Symbol Parameter Min. IIH Input HIGH Current IEE Power Supply Current 10E 100E TA = +25°C Typ. Max. Min. Typ. TA = +85°C Max. Min. Typ. Max. Unit Condition µA — mA — Unit Condition ps — ps — ps — — — 150 — — 150 — — 150 — — 85 85 102 102 — — 85 85 102 102 — — 85 98 102 117 AC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0°C Symbol Parameter TA = +25°C TA = +85°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. tPLH tPHL Propagation Delay to Output D SEL LEN MR 325 475 350 450 500 675 500 600 700 925 750 850 325 475 350 450 500 675 500 600 700 925 750 850 325 475 350 450 500 675 500 600 700 925 750 850 tS Set-up Time D SEL 300 500 100 250 — — 300 500 100 250 — — 300 500 100 250 — — Hold Time D SEL 300 0 –100 –250 — — 300 0 –100 –250 — — 300 0 –100 –250 — — tRR Reset Recovery Time 800 650 — 800 650 — 800 650 — ps — tPW Minimum Pulse Width, MR 400 — — 400 — — 400 — — ps — tskew Within-Device Skew — 75 — — 75 — — 75 — ps 1 tr tf Rise/Fall Time 20% to 80% 300 450 800 300 450 800 300 450 800 ps — tH NOTE: 1. Within-device skew is defined as identical transitions on similar paths through a device. PRODUCT ORDERING CODE Ordering Code Package Type Operating Range SY10E155JC J28-1 Commercial SY10E155JCTR J28-1 Commercial SY100E155JC J28-1 Commercial SY100E155JCTR J28-1 Commercial 2 SY10E155 SY100E155 Micrel 28 LEAD PLCC (J28-1) Rev. 03 3 SY10E155 SY100E155 Micrel MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. © 2000 Micrel Incorporated 4