MITSUBISHI ICS (TV) M64894FP/GP SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR DESCRIPTION PIN CONFIGURATION (TOP VIEW) The M64894 is a semiconductor integrated circuit consisting of PLL frequency synthesizer for TV/VCR using I 2C BUS control. It contains the prescaler with operating up to 1.3GHz, 4 band drivers PRESCALER INPUT and tuning Amplifier for direct tuning. Built-in 4 band drivers. • • • • • • • • • 4 integrated PNP band drivers (Io=40mA,Vsat=0.2V typ@Vcc1 to 13.2V) Built-in high-withstanding voltage tuning Amplifier Low power dissipation (Icc=20mA, Vcc=5V) Built-in prescaler with input amplifier (Fmax=1.3GHz) I2C bus control (Read and write mode) X’tal 4MHz is used to realize 3 type of tuning steps (Division ratio 1/512, 1/640, 1/1024) Built-in 5-level A/D converter Programmable chip address 16-pin small SOP/SSOP package 14 SDA 13 SCL CLOCK INPUT 12 ADC A/D INPUT 11 VCC3 SUPPLY VOLTAGE 3 TUNING OUTPUT 1 16 Xin GND GND 2 15 ADS SUPPLY VOLTAGE 1 SUPPLY VOLTAGE 2 VCC1 3 VCC2 4 BS4 5 BS3 6 BS2 7 10 Vtu BS1 8 9 BAND SWITCHING OUTPUTS M64894FP/GP FEATURES CRYSTAL OSCILLATOR CHIP ADDRESS INPUT DATA INPUT fin Vin FILTER INPUT Outline 16P2S-A (FP) 16P2Z-A (GP) APPLICATION TV, VCR tuners FUNCTION RECOMMENDED OPERATING CONDITION Supply voltage range..............................................V CC1=4.5 to 5.5V VCC2=VCC1 to 13.2V VCC3=28 to 35V Rated supply voltage...........................................................V CC1=5V VCC2=12V VCC3=33V 1 • • • • • • • • • 2-modulus prescaler (1/32 and 1/33) Built-in 4MHz crystal oscillator and reference divider Programmable divider (10-bit M counter, 5-bit S counter) Tri-state phase comparator Lock detector Band switch driver Op. Amp for direct tuning I2C bus receiver 5-level A/D converter MITSUBISHI ICS (TV) M64894FP/GP SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR BLOCK DIAGRAM CRYSTAL CHIP ADDRESS OSCILLATOR INPUT DATA INPUT CLOCK INPUT A/D INPUT SUPPLY VOLTAGE 3 TUNING OUTPUT FILTER INPUT X in ADS SDA SCL ADC VCC3 Vtu Vin 16 15 14 13 12 11 10 9 OSC 5-LEVEL A/D C I C RECEIVER 2 DIVIDER 10 10-BIT M COUNTER LOCK DETECTOR AMP PHASE COMPARATOR CHARGE PUMP 1/32,1/33 5 5-BIT S COUNTER 4 P.O RESET 1/8 BAND DRIVER BIAS AMP 1 2 3 4 5 6 7 8 f in GND VCC1 VCC2 BS4 BS3 BS2 BS1 SUPPLY VOLTAGE 1 SUPPLY VOLTAGE 2 PRESCALER INPUT BAND SWITCHING OUTPUTS 2 MITSUBISHI ICS (TV) M64894FP/GP SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR DESCRIPTION OF PIN Pin No. 1 2 3 4 5 6 7 8 Symbol fin GND VCC1 VCC2 BS4 BS3 BS2 BS1 Pin name Prescaler input GND Input for the VCO frequency. Ground to 0V. Power supply voltage 1 Power supply voltage 2 Power supply voltage terminal. 5.0V ±0.5V Power supply for band switching, Vcc 1 to 13.2V Band switching outputs PNP open collector method is used. When the band switching data is "H", the output is ON. When it is "L", the output is OFF. 9 Vin Filter input (Charge pump output) 10 11 Vtu VCC3 Tuning output Power supply voltage 3 12 ADC/ftest AD converter input/ Test port 13 SCL Clock input 14 SDA Data input 15 ADS 16 Xin Address switching input This is connected to the crystal oscillator Function This is the output terminal for the LPF input and charge pump output. When the phase of the programmable divider output (f 1/N) is ahead compared to the reference frequency (fref), the "source" current state becomes active. If it is behind, the "sink" current becomes active. If the phases are the same, the high impedance state becomes active. This supplies the tuning voltage. Power supply voltage for tuning voltage 28 to 35V A/D conversion of the input voltage. In control byte data input, the programmabule freq. Divider output and reference freq. output is selected by the test mode. Data is read into the shift register when the clock signal falls. Input for band SW and programmable freq. divider set up. In lead mode, itoutputs lock detector output and power down flagand a state of 5 level A/D converter. Chip address sets it up with the input condition of terminal. 4.0MHz crystal oscillator is connected. ABSOLUTE MAXIMUM RATINGS (Ta=-20°C to +75°C, unless otherwise noted) Symbol VCC1 VCC2 VCC3 VI VO Parameter Supply voltage 1 Supply voltage 2 Supply voltage 3 Input voltage Conditions Pin3 Pin4 Pin11 Not to exceed VCC1 fREF output IBSON Output voltage Voltage applied when the band output is OFF Band output current tBSON ON the time when the band output is ON Pd Topr Tstg Power dissipation Operating temperature Storage temperature VBSOFF Per 1 band output circuit 50mA per 1 band output circuit 3circuit are pn at same time Ta=+75°C Ratings 6.0 14.4 36.0 6.0 Unit V V V V 6.0 V 14.4 V 50.0 mA 10 sec 450 (470) -20 to +75 -40 to +125 mW °C °C Ratings 4.5 to 5.5 VCC1 to 13.2 28 to 35 4.0 80 to 1,300 Unit V V V MHz MHz 0 to 40 mA RECOMMENDED OPERATING CONDITIONS (Ta=-20°C to +75°C, unless otherwise noted) 3 Symbol VCC1 VCC2 VCC3 fopr1 fopr2 Parameter Supply voltage 1 Supply voltage 2 Supply voltage 3 Operating frequency (1) Operating frequency (2) IBDL Band output current 5 to 8 Conditions Pin3 Pin4 Pin11 Crystal oscillation circuit Normally 1 circuit is on. 2 circuits on at the same time is max. It is prohibited to have 3 or more circuits turned on at the same time. MITSUBISHI ICS (TV) M64894FP/GP SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR ELECTRICAL CHARACTERISTICS (Ta=-20°C to +75°C, Vcc1=5.0V, Vcc2=12V, Vcc3=33V, unless otherwise noted) Symbol Parameter Test pin VIH “H” input voltage 13 to 14 VIL IIH IIL VOL VLO VBS IOLK1 VTOH VTOL IOH IOL ICPLK ICC1 ICC2A “L” input voltage “H” input current “L” input current 13 to 14 13 to 14 13, 14 ICC2B ICC2C ICC3 Input pin Test conditions Min. 3.0 Limits Typ. Max. VCC1+0.3 − − − − − − 11.6 − 32.5 − − − − − − − -4/-14 − − 11.8 − − 0.2 ±270 ±70 − 20 1.5 10 -10/30 0.4 10 − -10 − 0.4 ±370 ±110 ±50 30 Unit V V µA µA µA µA V µA V V µA µA nA mA “L” output current Leak current Supply current 1 9 9 3 VCC1=5.5V, Vi=4.0V VCC1=5.5V, Vi=0.4V VCC1=5.5V, Io=3mA VCC1=5.5V, Vo=5.5V VCC2=12V, Io=-40mA VCC2=12V band SW is OFF VCC3=33V VCC3=33V VCC1=5.0V, Vo=2.5V VCC1=5.0V, Vo=2.5V VCC1=5.5V, Vo=2.5V VCC1=5.5V 4 circuits: OFF 1 circuits: ON, Output: OPEN Output current 40mA Supply current 3 4 VCC2=12V − − 0.3 mA 4 VCC2=12V − 6.0 8.0 mA 4 11 VCC2=12V Io=-40mA VCC3=33V Output ON − − 46.0 3.0 48.0 4.0 mA mA SDA output Band SW Tuning output “H” output voltage “L” output voltage Output voltage Leak current 14 14 5 to 8 5 to 8 Output voltage “H” Output voltage “L” “H” output current 10 10 9 Charge pump Supply current 2 Note. Typical values are measured at VCC1=5.0V, VCC2=12V, VCC3=33V, Ta=+25°C. SWITCHING CHARACTERISTICS (Ta=-20°C to +75°C, VCC1=5.0V, VCC2=12V, VCC3=33V, unless otherwise noted) Symbol fopr Parameter Prescaler operating frequency Test pin 1 Vin Operating input voltage 1 tSCL Clock pulse frequency Bus free time Data hold time SCL low hold time SCL high hold time Set up time Data hold time Data set up time Rise time Fall time Set up time 13 14 13 13 13 13, 14 13, 14 13, 14 13, 14 13, 14 13, 14 tBUF tHDSTA tLOW tHIGH tSUSTA tHDDAT tSUDAT tr tf tSUSTO Test conditions Min. Limits Typ. Max. Unit VCC1=4.5 to 5.5V Vin=Vinmin to Vinmax 80 to 100MHz 100 to 200MHz VCC1=4.5 200 to 800MHz to 5.5V 800 to 1000MHz 1000 to 1300MHz 80 − 1300 MHz -24 -27 -30 -27 -18 − − − − − 4 4 4 4 4 dBm VCC1=4.5 to 5.5V VCC1=4.5 to 5.5V VCC1=4.5 to 5.5V VCC1=4.5 to 5.5V VCC1=4.5 to 5.5V VCC1=4.5 to 5.5V VCC1=4.5 to 5.5V VCC1=4.5 to 5.5V VCC1=4.5 to 5.5V VCC1=4.5 to 5.5V VCC1=4.5 to 5.5V 0 4.7 4 4.7 4 4.7 0 250 − − 4 − − − − − − − − − − − 100 − − − − − − − 1000 300 − kHz µs µs µs µs µs s ns ns ns µs 4 MITSUBISHI ICS (TV) M64894FP/GP SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR METHOD OF SETTING DATA The input information to consit of 2 or data of 4bytes to lead to Chip The information of 5 bytes necessary for circuit operation is chip Address is received in I Cbus receiver. It shows a definition of bus address and control data, bandS.W. data of 2 bytes and divider byte protocol admitted in the following. of 2 bytes. After the chip address input, 2 or data of 4 bytes are 2 1_STA CA CB BB STO received. 2_STA CA D1 D2 STO Function bit is contained the first and the third data byte to 3_STA CA CB BB D1 D2 STO distinguish between divider data and control data, band data, and 4_STA CA D1 D2 CB BB STO "0" goes ahead of divider data, and "1" goes ahead of control data, bandS.W. data. STA : Start condition STO : Stop condition CA : Chip address CB : Control data byte BB : BandS.W. data byte D1 : Divider data byte D2 : Divider data byte SDA SCL S STA 1-7 8 9 ADDRESS CA 0 ACK 1-7 8 9 DATA 1-7 ACK 8 9 DATA P ACK STO Write mode format Byte Address Byte Devider Byte1 Devider Byte2 Control Byte1 Band SW Byte MSB 1 0 N7 1 X 1 N14 N6 CP X 0 N13 N5 T2 X 0 N12 N4 T1 X 0 N11 N3 T0 BS4 MA1 N10 N2 RSa BS3 MA0 N9 N1 RSb BS2 0 N8 N0 OS BS1 LSB A A A A A MSB 1 POR 1 FL 0 X 0 X 0 X MA1 A2 MA0 A1 1 A0 LSB A A Read mode format Byte Address Byte Status Byte1 5 MITSUBISHI ICS (TV) M64894FP/GP SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR DATA CORDING EXAMPLE Write mode format example Byte Address Byte MSB 1 1 0 0 0 1 1 0 LSB 1 Devider Byte1 Devider Byte2 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 Control Byte1 1 1 0 0 0 0 1 0 1 Band SW Byte 0 0 0 0 1 0 0 0 1 0 1 1 0 1 1 1 1 0 1 1 1 1 1 1 LSB 1 1 1 Condotion in data setting ADS input V CC1 Dividing ratio N=16544 C.P. current 270µA fREF division ratio 1/1024 BS4 output ON fVCO=N×8×fREF=16544×8×(4MHz/1024)=517MHz Read mode format example Byte Address Byte Status Byte1 input Status Byte1 output MSB 1 1 0 1 1 1 0 1 1 TEST MODE DATA SET UP METHOD RSa 1 0 X : Random, 0 or 1. normal "0" MA1 ,MA0 : Programmabule Address Bit Address input voltage 0 to 0.1∗VCC1 MA1 MA0 0 0 1 1 0 1 0 1 Always valid 0.4∗VCC1 to 0.6*VCC1 0.9∗VCC1 to VCC1 Dividing ratio N=N14(2 ⋅⋅⋅ +N0(20=1) Therefore, the range of division N is 1,024 to 32,768 Example) fvco=fREF×8×N =31.25×N (kHz) CP: Setting up the charge pump current of the phase comparator Charge pump current 70µA 270µA Mode Test Normal T2, T1, T0 : Setting up for the test mode T2 T1 T0 0 0 X 0 1 X 1 1 0 1 1 1 1 0 0 1 0 1 Charge pump Normal operation High impedance Sink Source High impedance High impedance Division ratio 1/512 1/1024 1/640 OS 0 1 Tuning voltage output ON OFF Mode Normal Test POR : Power on reset flag. “1” output at reset FL : Lock detecter flag. “1” output at locked, “0” output at unlocked A2, A1, A0: 5level A/D converter output data =3.90625×8×N CP 0 1 RSb 1 1 0 OS : Set up the tuning amplifier N14 to N0 : How to set dividing ratio of the programable the divider 14=16384)+ FL “1”output at locked ADC input at open RSa, RSb : Set up for the reference frequency division ratio Test Mode Bit Set Up X Condotion in divise Pin 12 condition ADC input ADC input ADC input ADC input fREF output f1/N output ADC input voltage 0.6∗VCC1 to VCC1 0.45∗VCC1 to 0.6∗VCC1 0.3∗VCC1 to 0.45∗VCC1 0.15∗VCC1 to 0.3∗VCC1 0 to 0.15∗VCC1 A2 1 0 0 0 0 A1 0 1 1 0 0 A0 0 1 0 1 0 The voltage accuracy allowance range: ±0.03∗VCC1 (V) POWER ON RESET OPERATION Mode (Initial state the power is turned ON) Normal operation BS4 to BS1 : OFF Test mode Test mode Test mode Test mode Test mode Charge pump : High impedance Tuning amplifier : OFF Charge pump current : 270µA Frequency division ratio : 1/1024 6 MITSUBISHI ICS (TV) M64894FP/GP SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR TIMING DIAGRAM START condition SDA tBUF tLOW tr tHDSTA tf SCL tHDSTA tHDDAT tHIGH STOP condition 16 4MHz 7 tSUSTA START condition CRYSTAL OSCILLATOR CONNECTION DIAGRAM 18pF tSUDAT Crystal oscillator characteristics Actual resistance: less than 300Ω Load capacitance : 20pF tSUSTO STOP condition MITSUBISHI ICS (TV) M64894FP/GP SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR APPLICATION EXAMPLE BUILT-IN PLL TUNER +5V Vcc1 to 12V UHF VHF 1000p - 15 10µ 3 5 18 SW Vcc2 M64894FP/GP +B ADS 4 47k BS4 11 BS4 5 47k BS3 12 IF BS3 IF 6 1 TEST 47k BS2 13 BS2 M5493X series 3 DATA 7 47k BS1 14 14 BS1 8 1000p fIN 17 MCU 4 CLK GND 16 13 Lo 1 AGC 0.1µ 10 VT 9 56k 56k AFT PD 20 LD/f1/N ADC XOUT GND 6 7 8 16 2.2n 10 9 XIN 18p AGC 1.5n 1000pF 15 2 EN 12 4-BAND TUNER 100p ∗ 11 4MHz +33V Note) Filter constant is for reference. ∗ Add a capacitor to stabilize the circuit. BT Units Resistance : Ω Capacitance : F 8