MITSUBISHI
MITSUBISHI
〈DIGITAL
〈DIGITAL
ASSP〉
ASSP〉
M66256FP
M66256FP
5120 × 8-BIT LINE MEMORY (FIFO)
5120 × 8-BIT LINE MEMORY (FIFO)
DESCRIPTION
The M66256FP is a high-speed line memory with a FIFO
(First In First Out) structure of 5120-word × 8-bit configuration
which uses high-performance silicon gate CMOS process
technology.
It has separate clock, enable and reset signals for write and
read, and is most suitable as a buffer memory between devices with different data processing throughput.
DATA OUTPUT
Q0 ← 1
24 ← D0
Q1 ← 2
23 ← D1
Q2 ← 3
22 ← D2
Q3 ← 4
21 ← D3
RE → 5
20 ← WE
READ ENABLE INPUT
READ RESET INPUT RRES→ 6
GND
7
READ CLOCK INPUT RCK → 8
DATA OUTPUT
APPLICATION
Digital photocopiers, high-speed facsimile, laser beam printers.
M66256FP
FEATURES
• Memory configuration ........................................................
............................. 5120 words × 8-bits (dynamic memory)
• High-speed cycle ............................................. 25ns (Min.)
• High-speed access ......................................... 18ns (Max.)
• Output hold ........................................................ 3ns (Min.)
• Fully independent, asynchronous write and read operations
• Variable length delay bit
• Output .................................................................... 3 states
PIN CONFIGURATION (TOP VIEW)
DATA INPUT
WRITE ENABLE INPUT
19 ← WRES WRITE RESET INPUT
VCC
18
17 ← WCK WRITE CLOCK INPUT
Q4 ← 9
16 ← D4
Q5 ← 10
15 ← D5
Q6 ← 11
14 ← D6
Q7 ← 12
13 ← D7
DATA INPUT
Outline 24P2U-A
VCC 18
13 14 15 16 21 22 23 24
1 2 3 4 9 10 11 12
INPUT BUFFER
OUTPUT BUFFER
MEMORY ARRAY OF
5120-WORD × 8-BIT
CONFIGURATION
READ CONTROL CIRCUIT
WRITE
CLOCK INPUT WCK 17
DATA OUTPUT
Q0 ~ Q7
READ ADDRESS COUNTER
WRITE
RESET INPUT WRES 19
DATA INPUT
D0 ~ D7
WRITE ADDRESS COUNTER
WRITE
ENABLE INPUT WE 20
WRITE CONTROL CIRCUIT
BLOCK DIAGRAM
5 RE
READ
ENABLE INPUT
READ
6 RRES RESET INPUT
READ
8 RCK CLOCK INPUT
7 GND
1
MITSUBISHI 〈DIGITAL ASSP〉
M66256FP
5120 × 8-BIT LINE MEMORY (FIFO)
FUNCTION
When write enable input WE is “L”, the contents of data inputs
D0 to D7 are written into memory in synchronization with rise
edge of write clock input WCK. At this time, the write address
counter is also incremented simultaneously.
The write function given below are also performed in synchronization with rise edge of WCK.
When WE is “H”, a write operation to memory is inhibited and
the write address counter is stopped.
When write reset input WRES is “L”, the write address counter
is initialized.
When read enable input RE is “L”, the contents of memory are
output to data outputs Q0 to Q7 in synchronization with rise
edge of read clock input RCK. At this time, the read address
counter is also incremented simultaneously.
The read functions given below are also performed in synchronization with rise edge of RCK.
When RE is “H”, a read operation from memory is inhibited
and the read address counter is stopped. The outputs are in
the high impedance state.
When read reset input RRES is “L”, the read address counter
is initialized.
ABSOLUTE MAXIMUM RATINGS (Ta = 0 ~ 70°C, unless otherwise noted)
Symbol
VCC
VI
VO
Pd
Tstg
Parameter
Supply voltage
Input voltage
Output voltage
Maximum power dissipation
Storage temperature
Conditions
Ratings
–0.5 ~ +7.0
–0.5 ~ VCC + 0.5
–0.5 ~ VCC + 0.5
440
–65 ~ 150
A value based on GND pin
Ta = 25°C
Unit
V
V
V
mW
°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
GND
Topr
Parameter
Min.
4.5
Supply voltage
Supply voltage
Operating ambient temperature
Limits
Typ.
5
0
Unit
Max.
5.5
0
V
V
°C
70
ELECTRICAL CHARACTERISTICS (Ta = 0 ~ 70°C, VCC = 5V ± 10%, GND = 0V)
Symbol
VIH
VIL
VOH
VOL
Parameter
“H” input voltage
“L” input voltage
“H” output voltage
“L” output voltage
Test conditions
IOH = –4mA
IOL = 4mA
WE, WRES, WCK, RE,
RRES, RCK,
D0 ~ D7
WE, WRES, WCK, RE,
RRES, RCK,
D0 ~ D7
VI = VCC
IIL
“L” input current
VI = GND
IOZH
IOZL
Off state “H” output current
Off state “L” output current
Operating mean current dissipation
Input capacitance
Off state output capacitance
VO = VCC
VO = GND
VI = VCC, GND, Output open
tWCK, tRCK = 25ns
f = 1MHz
f = 1MHz
2
Max.
Unit
0.55
V
V
V
V
1.0
mA
–1.0
mA
5.0
–5.0
mA
mA
80
mA
10
15
pF
pF
VCC–0.8
“H” input current
CI
CO
Limits
Typ.
0.8
IIH
ICC
Min.
2.0
MITSUBISHI 〈DIGITAL ASSP〉
M66256FP
5120 × 8-BIT LINE MEMORY (FIFO)
SWITCHING CHARACTERISTICS (Ta = 0 ~ 70°C, VCC = 5V ± 10%, GND = 0V)
Symbol
tAC
tOH
tOEN
tODIS
Parameter
Access time
Output hold time
Output enable time
Output disable time
Min.
Limits
Typ.
3
3
3
Max.
18
18
18
Unit
ns
ns
ns
ns
TIMING CONDITIONS (Ta = 0 ~ 70°C, VCC = 5V ± 10%, GND = 0V, unless otherwise noted)
Symbol
tWCK
tWCKH
tWCKL
tRCK
tRCKH
tRCKL
tDS
tDH
tRESS
tRESH
tNRESS
tNRESH
tWES
tWEH
tNWES
tNWEH
tRES
tREH
tNRES
tNREH
tr, tf
tH
Parameter
Write clock (WCK) cycle
Write clock (WCK) “H” pulse width
Write clock (WCK) “L” pulse width
Read clock (RCK) cycle
Read clock (RCK) “H” pulse width
Read clock (RCK) “L” pulse width
Input data setup time to WCK
Input data hold time to WCK
Reset setup time to WCK or RCK
Reset hold time to WCK or RCK
Reset nonselect setup time to WCK or RCK
Reset nonselect hold time to WCK or RCK
WE setup time to WCK
WE hold time to WCK
WE nonselect setup time to WCK
WE nonselect hold time to WCK
RE setup time to RCK
RE hold time to RCK
RE nonselect setup time to RCK
RE nonselect hold time to RCK
Input pulse rise/fall time
Data hold time (Note 1)
Min.
25
11
11
25
11
11
7
3
7
3
7
3
7
3
7
3
7
3
7
3
Limits
Typ.
Max.
20
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Notes 1: For 1-line access, the following should be satisfied:
WE “H” level period ≤ 20ms – 5120 tWCK – WRES “L” level period
RE “H” level period ≤ 20ms – 5120 tRCK – RRES “L” level period
2: Perform reset operation after turning on power supply.
3
MITSUBISHI 〈DIGITAL ASSP〉
M66256FP
5120 × 8-BIT LINE MEMORY (FIFO)
TEST CIRCUIT
VCC
RL=1kΩ
Qn
SW1
CL=30pF : tAC, tOH
Qn
SW2
CL=5pF : tOEN, tODIS
RL=1kΩ
Input pulse level
:
Input pulse rise/fall time :
Decision voltage input :
Decision voltage output :
0 ~ 3V
3ns
1.3V
1.3V (However, tODIS(LZ) is 10% of output amplitude and tODIS(HZ) is 90% of
that for decision).
The load capacitance CL includes the floating capacitance of connection and the input capacitance of
probe.
Parameter
tODIS(LZ)
tODIS(HZ)
tOEN(ZL)
tOEN(ZH)
SW1
Closed
Open
Closed
Open
SW2
Open
Closed
Open
Closed
tODIS/tOEN TEST CONDITION
3V
RCK
1.3V
1.3V
GND
3V
RE
GND
tOEN(ZH)
tODIS(HZ)
1.3V
tODIS(LZ)
Qn
4
VOH
90%
Qn
tOEN(ZL)
1.3V
10%
VOL
MITSUBISHI 〈DIGITAL ASSP〉
M66256FP
5120 × 8-BIT LINE MEMORY (FIFO)
OPERATING TIMING
• Write cycle
Cycle n
Cycle n+1
Cycle n+2
tWCK
tWCKH tWCKL
Disable cycle
Cycle n+3
Cycle n+4
WCK
tWEH
tNWES
tNWEH
tWES
WE
tDS tDH
tDS tDH
(n)
Dn
( n+1)
(n+2)
(n+3)
(n+4)
WRES = “H”
• Write reset cycle
Cycle n–1
Cycle n
Reset cycle
tWCK
tNRESH tRESS
Cycle 0
Cycle 1
Cycle 2
WCK
tRESH
tNRESS
WRES
Dn
tDS tDH
tDS tDH
(n–1)
(n)
(0)
(1)
(2)
WE = “L”
5
MITSUBISHI 〈DIGITAL ASSP〉
M66256FP
5120 × 8-BIT LINE MEMORY (FIFO)
• Matters that needs attention when WCK stops
n cycle
n+1 cycle
n cycle
Disable cycle
WCK
tNWES
tWCK
WE
Dn
tDS tDH
tDS tDH
(n)
(n)
Period for writing data (n)
into memory
Period for writing data (n)
into memory
WRES = “H”
Input data of n cycle is read at the rising edge after WCK of n cycle and writing operation starts in the WCK low-level period of
n+1 cycle. The writing operation is complete at the falling edge after n+1 cycle.
To stop reading write data at n cycle, enter WCK before the rising edge after n+1 cycle.
When the cycle next to n cycle is a disable cycle, WCK for a cycle requires to be entered after the disable cycle as well.
6
MITSUBISHI 〈DIGITAL ASSP〉
M66256FP
5120 × 8-BIT LINE MEMORY (FIFO)
• Read cycle
Cycle n
Cycle n+1
Cycle n+2
Disable cycle
Cycle n+3
Cycle n+4
RCK
tRCK
tRCKH
tRCKL
tREH
tNRES
tNREH
tRES
tAC
RE
tODIS
tOEN
HIGH-Z
(n)
Qn
(n+1)
(n+2)
(n+3)
(n+4)
tOH
RRES = “H”
• Read reset cycle
Cycle n–1
Cycle n
tRCK
tNRESH tRESS
Reset cycle
Cycle 0
Cycle 1
Cycle 2
RCK
tRESH tNRESS
RRES
tAC
Qn
(n–1)
(n)
(0)
(0)
(0)
(1)
(2)
tOH
RE = “L”
7
MITSUBISHI 〈DIGITAL ASSP〉
M66256FP
5120 × 8-BIT LINE MEMORY (FIFO)
VARIABLE LENGTH DELAY BITS
• 1-line (5120 bits) delay
A write input data is written into memory at the second rise edge of WCK in the cycle, and a read output data is output from
memory at the first rise edge of RCK in the cycle, so that 1-line delay can be made easily.
Cycle 0
Cycle 1
Cycle 2
Cycle 5118 Cycle 5119
Cycle 5120 Cycle 5121 Cycle 5122
(0')
(1')
(2')
WCK
RCK
tRESS tRESH
WRES
RRES
tDS tDH
(1)
(0)
Dn
tDS tDH
(2)
(5117)
(5118)
(5119)
5120 cycles
(0')
tAC
(1')
(2')
(3')
(1)
(2)
(3)
tOH
(0)
Qn
WE, RE = “L”
• N-bit delay bit
(Making a reset at a cycle corresponding to delay length)
Cycle 0
Cycle 1
Cycle 2
Cycle n–2
Cycle n–1
Cycle n
(0')
Cycle n+1 Cycle n+2
(1')
(2')
Cycle n+3
(3')
WCK
RCK
tRESS tRESH
tRESS tRESH
WRES
RRES
tDS tDH
Dn
(0)
tDS tDH
(1)
(2)
m cycles
Qn
(n–3)
(n–2)
(n–1)
(0')
tAC
(1')
(2')
(3')
(1)
(2)
(3)
tOH
(0)
WE, RE = “L”
m≥3
8
MITSUBISHI 〈DIGITAL ASSP〉
M66256FP
5120 × 8-BIT LINE MEMORY (FIFO)
• N-bit delay
2
_____
_____
(Sliding WRES and RRES at a cycle corresponding to delay length)
Cycle 0
Cycle 1
Cycle 2
Cycle n–2
Cycle n–1
Cycle n
Cycle n+1 Cycle n+2
Cycle n+3
WCK
RCK
tRESS tRESH
WRES
tRESS tRESH
RRES
tDS tDH
tDS tDH
(0)
Dn
(1)
(2)
(n–2)
(n–1)
(n)
(n+2)
(n+3)
(1)
(2)
(3)
tOH
tAC
m cycles
(n+1)
(0)
Qn
WE, RE = "L"
m≥3
• N-bit delay __
3
(Disabling RE at a cycle corresponding to delay length)
Cycle 0
Cycle 1
Cycle 2
Cycle n–1
Cycle n
Cycle n+1 Cycle n+2
Cycle n+3
WCK
RCK
tRESS tRESH
WRES
RRES
tNREH tRES
RE
tDS tDH
(0)
Dn
tDS tDH
(1)
(2)
m cycles
(n–2)
(n–1)
(n)
tAC
(n+1)
(n+2)
(n+3)
(1)
(2)
(3)
tOH
HIGH-Z
Qn
(0)
WE = “L”
m≥3
9
MITSUBISHI 〈DIGITAL ASSP〉
M66256FP
5120 × 8-BIT LINE MEMORY (FIFO)
• Shortest read of data “n” written in cycle n
Cycle n–1 on read side should be started after end of cycle n+1 on write side
When the start of cycle n–1 on read side is earlier than the end of cycle n+1 on write side, output Q n of cycle n becomes invalid.
In the figure shown below, the read of cycle n–1 is invalid.
Cycle n
Cycle n+1
Cycle n+2
Cycle n+3
WCK
(n)
Dn
(n+1)
Cycle n–2
(n+2)
Cycle n–1
(n+3)
Cycle n
RCK
Qn
invalid
(n)
• Longest read of data “n” written in cycle n: 1-line delay
Cycle n <1>* on read side should be started when cycle n <2>* on write is started
Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1>* and the start of writing side n cycle <2>* overlap each other.
Cycle n <1>*
Cycle 0 <2>*
Cycle n <2>*
WCK
Dn
(n–1)<1>*
(n)<1>*
Cycle n <0>*
(00) <2>*
(n–1)<2>*
Cycle 0 <1>*
(n)<2>*
Cycle n <1>*
RCK
Qn
(n–1)<0>*
(n)<0>*
(0)<1>*
(n–1)<1>*
(n)<1>*
<0>*, <1>* and <2>* indicates a line value.
10
MITSUBISHI 〈DIGITAL ASSP〉
M66256FP
5120 × 8-BIT LINE MEMORY (FIFO)
APPLICATION EXAMPLE
Laplacian Filter Circuit for Correction of Resolution in the Secondary Scanning Direction.
N
Line n image data
M66256
~
~
B
Line (n+1)
image data
Q0
D9
Q9
Adder
N+K {2N–(A+B)}
D0
×2
Subtractor
2N–(A+B)
1-line
delay
Corrected
image data
×K
M66256
Q0
~
~
D9
Q9
Secondary scanning
direction
1-line
delay
A
Line (n–1)
image data
Adder
A+B
D0
Primary scanning
direction
A
Line (n–1)
N
Line n
B
Line (n+1)
N' = N+K { (N–A)+(N–B)}
= N+K { 2N–(A+B)}
K : Laplacean coefficient
11