MITSUBISHI <DIGITAL ASSP>
M66281FP
5120 x 8-BIT x 2 LINE MEMORY
When write reset input WRESB is set to "L", the write address
counter of memory only for 1 line delay data is initialized.
When read enable input REB is set to "L", the contents of memory
only for 1 line delay data are output to data outputs Q00 to Q07
and the contents of memory only for 2 line delay data are output to
Q10 to Q17 in synchronization with a rising edge of read clock
input RCK to perform reading operation.
When this is the case, the read address counters of memory only
for 1 line delay data and memory only for 2 line delay data are
incremented simultaneously.
In addition, data of Q00 to Q07 is written into memory only for 2
line delay data in synchronization with a rising edge of RCK. When
this is the case, the write address counter of memory only for 2 line
delay data is then incremented.
When REB is set to "H", operation for reading data from memory
only for 1 line delay and from memory only for 2 line delay data is
inhibited and the read address counter of each memory stops.
Outputs Q00 to Q07 and Q10 to Q17 are placed in a high
impedance state. In addition, the write address counter of memory
only for 2 line delay data then stops.
When read reset input RRESB is set to "L", the read address
counters of memory only for 1 line delay data as well as the write
address counter and read address counter of memory only for 2
line delay data are then initialized.
DESCRIPTION
The M66281FP is high speed line memory that uses high
performance silicon gate CMOS process technology and adopts the
FIFO (First In First Out) structure consisting of 5120 words x 8 bits
x 2.
Since memory is available to simultaneously output 1 line delay and
2 line delay data, the M66281FP is optimal for the compensation of
data of multiple lines.
FEATURES
•
•
•
•
•
•
•
•
•
•
Memory configuration 5120 words x 8 bits x 2 (dynamic memory)
High speed cycle
25 ns (Min.)
High speed access
18 ns (Max.)
Output hold
3 ns (Min.)
Reading and writing operations can be completely carried out
independently and asynchronously.
Variable length delay bit
Input/output
TTL direct connection allowable
Output
3 states
Q00 – Q07
1 line delay
Q10 – Q17
2 line delay
APPLICATION
• Digital copying machine, laser beam printer, high speed facsimile,
etc.
FUNCTION
When write enable input WEB is set to "L", the contents of data
inputs D0 to D7 are written into memory only for 1 line delay data in
synchronization with a rising edge of write clock input WCK to
perform writing operation. When this is the case, the write address
counter of memory only for 1 line delay data is incremented
simultaneously.
When WEB is set to "H", the writing operation is inhibited and the
write address counter of memory only for 1 line delay data stops.
25 NC
26 NC
27 D4
28 D3
29 D2
30 D1
31 D0
32 VCC
33 GND
34 WCK
35 WRESB
36 WEB
37 NC
38 NC
PIN CONFIGURATION (TOP VIEW)
24 NC
NC 39
RCK 40
23 D5
RRESB 41
22 D6
REB 42
21 D7
20 GND
GND 43
M66281FP
VCC 44
19 VCC
Q00 45
18 Q17
Q01 46
17 Q16
Q02 47
16 Q15
15 NC
Outline 48P6S-A(QFP)
NC 14
Q14 13
Q13 12
Q12 11
Q11 10
Q10 9
VCC 8
GND 7
Q07 6
Q06 5
Q05 4
Q04 3
Q03 2
NC 1
NC 48
NC : No connection
1
2
WEB 36
Write clock input
30
27
Input buffer
28
21
45 46 47 2
3
Memory Array
5120 words x 8 bits x 2
Memory only for 1 line delay data
Memory only for 2 line delay data
22
4
6
9 10 11 12 13 16 17 18
Output buffer
5
7
GND
Read clock input
Read reset input
41 RRESB
40 RCK
Read enable input
42 REB
43 GND
23
Data outputs
Q10 to Q17
VCC 44
Write control circuit
33 GND
Write address counter
VCC 32
29
Data outputs
Q0 to Q7
Read address counter
20 GND
8
31
Data inputs
D0 to D7
Read control circuit
VCC 19
VCC
WCK 34
Write reset input WRESB 35
Write enable input
BLOCK DIAGRAM
MITSUBISHI <DIGITAL ASSP>
M66281FP
5120 x 8-BIT x 2 LINE MEMORY
MITSUBISHI <DIGITAL ASSP>
M66281FP
5120 x 8-BIT x 2 LINE MEMORY
ABSOLUTE MAXIMUM RATINGS (Ta=0 – 70 °C unless otherwise noted)
Symbol
Vcc
VI
VO
Pd
Tstg
Parameter
Supply voltage
Input voltage
Output voltage
Power dispersion
Storage temperature
Conditions
Value based on the GND pin
Note
Ratings
Unit
-0.3 – +4.6
-0.3 – VCC+0.3
-0.3 – VCC+0.3
540
-55 – 150
V
V
V
mW
°C
Note : Ta=0 – 63˚C. Ta > 63˚C are derated at -9mW/˚C
RECOMMENDED OPERATING CONDITIONS
Symbol
Vcc
GND
Topr
Parameter
Supply voltage
Supply voltage
Operating temperature
Min.
2.7
Limits
Typ.
3.15
0
0
Max.
3.6
Unit
V
V
°C
70
ELECTRICAL CHARACTERISTICS (Ta=0 – 70 °C, Vcc=2.7 – 3.6V, GND=0V unless otherwise noted)
Symbol
VIH
VIL
VOH
VOL
Parameter
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
Conditions
Min.
2.0
Limits
Typ.
Max.
0.4
V
V
V
V
1.0
µA
-1.0
µA
5.0
-5.0
µA
µA
150
mA
10
15
pF
pF
0.8
IOH = -4mA
IOL = 4mA
VCC-0.4
IIH
High-level input current
VI = VCC
WEB, WRESB, WCK,
REB, RRESB, RCK,
D0 – D7
IIL
Low-level input current
VI = GND
WEB, WRESB, WCK,
REB, RRESB, RCK,
D0 – D7
IOZH
IOZL
Off-state high-level output current
Off-state low-level output current
VO = VCC
VO = GND
ICC
Average supply current during operation
CI
CO
Input capacitance
Off-time output capacitance
VI = VCC, GND, output open
tWCK, tRCK = 25ns
f = 1MHz
f = 1MHz
Unit
3
MITSUBISHI <DIGITAL ASSP>
M66281FP
5120 x 8-BIT x 2 LINE MEMORY
SWITCHING CHARACTERISTICS (Ta=0 – 70 °C, Vcc=2.7 – 3.6V, GND=0V unless otherwise noted)
Parameter
Symbol
tAC
tOH
tOEN
tODIS
Access time
Output hold time
Output enable time
Output disable time
Min.
Limits
Typ.
3
3
3
Max.
18
18
18
Unit
ns
ns
ns
ns
TIMING REQUIREMENTS (Ta=0 – 70 °C, Vcc=2.7 – 3.6V, GND=0V unless otherwise noted)
Symbol
tWCK
tWCKH
tWCKL
tRCK
tRCKH
tRCKL
tDS
tDH
tRESS
tRESH
tNRESS
tNRESH
tWES
tWEH
tNWES
tNWEH
tRES
tREH
tNRES
tNREH
t r, t f
tH
Parameter
Write clock (WCK) cycle
Write clock (WCK) "H" pulse width
Write clock (WCK) "L" pulse width
Read clock (RCK) cycle
Read clock (RCK) "H" pulse width
Read clock (RCK) "L" pulse width
Input data set up time for WCK
Input data hold time for WCK
Reset set up time for WCK/RCK
Reset hold time for WCK/RCK
Reset non-selection set up time for WCK/RCK
Reset non-selection hold time for WCK/RCK
WEB set up time for WCK
WEB hold time for WCK
WEB non-selection set up time for WCK
WEB non-selection hold time for WCK
REB set up time for RCK
REB hold time for RCK
REB non-selection set up time for RCK
REB non-selection hold time for RCK
Input pulse up/down time
Data hold time (Note 1)
Note 1: For 1 line access, the following conditions must be satisfied:
WEB high-level period ≤ 20 ms - 5120 • tWCK - WRESB low-level period
REB high-level period ≤ 20 ms - 5120 • tRCK - RRESB low-level period
2: Perform reset operation after turning on power supply.
4
Min.
25
11
11
25
11
11
7
3
7
3
7
3
7
3
7
3
7
3
7
3
Limits
Typ.
Max.
20
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
MITSUBISHI <DIGITAL ASSP>
M66281FP
5120 x 8-BIT x 2 LINE MEMORY
SWITCHING CHARACTERISTICS MEASUREMENT CIRCUIT
VCC
RL=1KΩ
SW1
Qn
Qn
SW2
CL = 30pF : tAC, tOH
CL = 5pF : tOEN, tODIS
RL=1KΩ
Input pulse level
Input pulse up/down time
Judging voltage Input
Output
: 0 – 3V
: 3 ns
: 1.3V
: 1.3V(However, tODIS(LZ) is judged with 10% of the
output amplitude, while tODIS(HZ) is judged with
90% of the output amplitude.)
Load capacitance CL includes the floating capacity of connected lines and input
capacitance of probe.
Item
SW1
SW2
tODIS(LZ)
Close
Open
tODIS(HZ)
Open
Close
tOEN(ZL)
Close
Open
tOEN(ZH)
Open
Close
tODIS and tOEN measurement condition
3V
RCK
1.3V
1.3V
GND
3V
REB
GND
tOEN(ZH)
tODIS(HZ)
VOH
90%
Qn
1.3V
tOEN(ZL)
tODIS(LZ)
Qn
1.3V
10%
VOL
5
MITSUBISHI <DIGITAL ASSP>
M66281FP
5120 x 8-BIT x 2 LINE MEMORY
OPERATION TIMING
• Write cycle
n cycle
n+1 cycle
n+2 cycle
Disable cycle
n+3 cycle
n+4 cycle
WCK
tWCK
tWCKH tWCKL
tWEH
tNWES
tNWEH
tWES
WEB
tDS tDH
(n)
Dn
(n+1)
(n+2)
(n+3)
(n+4)
WRESB = "H"
• Write reset cycle
n cycle
n-1 cycle
Reset cycle
0 cycle
1 cycle
2 cycle
WCK
tWCK
tNRESH tRESS
tRESH tNRESS
WRESB
tDS tDH
Dn
(n-1)
(n)
(0)
(1)
WEB = "L"
6
(2)
MITSUBISHI <DIGITAL ASSP>
M66281FP
5120 x 8-BIT x 2 LINE MEMORY
• Matters that needs attetion when WCK stops
n+1 cycle
n cycle
n cycle
Disable cycle
WCK
tWCK
tNWES
WEB
Dn
tDS tDH
tDS tDH
(n)
(n)
Period for writing data
(n) into memory
Period for writing data
(n) into memory
WRESB = "H"
Input data of n cycle is read at the rising edge after WCK of n cycle and writing operation starts in the WCK low-level period of n+1
cycle. The writing operation is complete at the falling edge after n+1 cycle.
To stop reading write data at n cycle, enter WCK before the rising edge after n+1 cycle.
When the cycle next to n cycle is a disable cycle, WCK for a cycle requires to be entered after the disable cycle as well.
7
MITSUBISHI <DIGITAL ASSP>
M66281FP
5120 x 8-BIT x 2 LINE MEMORY
• Read cycle
n+1 cycle
n cycle
n+2 cycle
n+3 cycle
Disable cycle
n+4 cycle
RCK
tRCK
tRCKH
tRCKL
tREH
tNREH
tNRES
tRES
tAC
REB
tOEN
tODIS
Q0n
(n)
(Q1n)
(n+1)
(n+2)
HIGH-Z
(n+3)
(n+4)
tOH
RRESB = "H"
• Read reset cycle
n-1 cycle
n cycle
Reset cycle
tRCK
tNRESH tRESS
0 cycle
1 cycle
2 cycle
RCK
tRESH tNRESS
RRESB
tAC
Q0n
(Q1n)
(n-1)
(n)
(0)
(0)
(0)
(1)
tOH
REB = "L"
8
(2)
MITSUBISHI <DIGITAL ASSP>
M66281FP
5120 x 8-BIT x 2 LINE MEMORY
• Notes on reading of written data in read disable
When writing operation is performed at n cycle and n+1 cycle on the writing side in the read disable period after n-1 cycle on
the reading side, output at n cycle and n+1 cycle after read enable is invalid. For output at n+2 cycle and after, however, data
written in the read disable period is to be output.
n-1 cycle
n cycle
n+1 cycle
n+2 cycle
n+3 cycle
n+4 cycle
n+5 cycle
n+6 cycle
n+7 cycle
WCK
tDS tDH
Dn
(n-1)
(n)
(n+1)
(n+2)
Disable cycle
n-1 cycle
(n+3)
(n+4)
(n+5)
n cycle
n+1 cycle
(n+6)
(n+7)
n+2 cycle
RCK
REB
tAC
tODIS
HIGH-Z
Q0n
(Q1n)
tOEN
(n-1)
invalid
invalid
(n+2)
WEB = "L"
WRESB = "H"
RRESB = "H"
9
MITSUBISHI <DIGITAL ASSP>
M66281FP
5120 x 8-BIT x 2 LINE MEMORY
VARIABLE LENGTH DELAY BIT
• 1 line (5120 bits) delay
Input data can be written at the rising edge of WCK after write cycle and output data is read at the rising edge of RCK before read
cycle to easily make 1 line delay.
0 cycle
1 cycle
2 cycle
5118 cycle 5119 cycle
5120 cycle 5121 cycle 5122 cycle
(0')
(1')
(2')
WCK
RCK
tRESS tRESH
WRESB
RRESB
tDS tDH
Dn
tDS tDH
(0)
(1)
(2)
(5117)
(5118)
(0')
(5119)
5120 cycle
tAC
(1')
(2')
(3')
(1)
(2)
(3)
tOH
Q0n
(0)
(Q1n)
WEB, REB = "L"
• n-bit delay bit
(Reset at cycles according to the delay length)
0 cycle
1 cycle
n-2 cycle
2 cycle
n-1 cycle
n cycle
(0')
n+1 cycle
(1')
n+2 cycle
(2')
n+3 cycle
(3')
WCK
RCK
tRESS tRESH
tRESS tRESH
WRESB
RRESB
tDS tDH
Dn
(0)
tDS tDH
(1)
(2)
m cycle
(n-3)
(n-2)
(n-1)
(0')
tAC
(1')
(2')
(3')
(1)
(2)
(3)
tOH
Q0n
(Q1n)
(0)
WEB, REB = "L"
m≥3
10
MITSUBISHI <DIGITAL ASSP>
M66281FP
5120 x 8-BIT x 2 LINE MEMORY
• n-bit delay 2
(Slides input timings of WRESB and RRESB at cycles according to the delay length.)
0 cycle
1 cycle
2 cycle
n-2 cycle
n-1 cycle
n cycle
n+1 cycle
n+2 cycle
n+3 cycle
WCK
RCK
tRESS tRESH
WRESB
tRESS tRESH
RRESB
tDS tDH
Dn
tDS tDH
(0)
(1)
(2)
(n-2)
(n-1)
m cycle
(n)
tAC
(n+1)
(n+2)
(n+3)
(1)
(2)
(3)
tOH
Q0n
(Q1n)
(0)
WEB, REB = "L"
m≥3
• n-bit delay 3
(Slides address by disabling REB in the period according to the delay length.)
0 cycle
1 cycle
2 cycle
n-1 cycle
n cycle
n+1 cycle
n+2 cycle
n+3 cycle
WCK
RCK
tRESS tRESH
WRESB
RRESB
tNREH tRES
REB
tDS tDH
tDS tDH
Dn
(0)
(1)
(2)
m cycle
Q0n
(Q1n)
HIGH-Z
(n-2)
(n-1)
(n)
tAC
(n+1)
(n+2)
(n+3)
(1)
(2)
(3)
tOH
invalid
WEB = "L"
m≥3
11
MITSUBISHI <DIGITAL ASSP>
M66281FP
5120 x 8-BIT x 2 LINE MEMORY
• Reading shortest n-cycle write data "n"
(Reading side n-2 cycle ends after the end of writing side n+1 cycle.)
When the reading side n-2 cycle ends before the end of the writing side n+1 cycle, output Qn of n cycle is made invalid.
In the following diagram, end of reading side n-2 cycle and end of writing side n+1 cycle overlap each other. This example can read n cycle
data in the shortest time. When this is the case, reading operation at n-1 cycle is invalid.
n cycle
n+1 cycle
n+2 cycle
n+3 cycle
WCK
Dn
(n)
(n+1)
n-2 cycle
(n+2)
n-1 cycle
(n+3)
n cycle
RCK
Q0n
(n)
invalid
(Q1n)
• Reading longest n-cycle write data "n": 1 line delay
(When writing side n-cycle <2> starts, reading side n cycle <1> then starts.)
Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1> and the start of writing side n cycle <2>* overlap each
other.
n cycle <1>*
n cycle <2>*
0 cycle <2>*
WCK
Dn
(n-1)<1>*
(n)<1>*
n cycle <0>*
(0)<2>*
(n-1)<2>*
0 cycle <1>*
(n)<2>*
n cycle <1>*
RCK
Q0n
(Q1n)
(n-1)<0>*
(n)<0>*
(0)<1>*
(n-1)<1>*
(n)<1>*
<0>*, <1>* and <2>* indicate value of lines.
12
MITSUBISHI <DIGITAL ASSP>
M66281FP
5120 x 8-BIT x 2 LINE MEMORY
APPLICATION EXAMPLE
Sub Scan Resolution Compensation Circuit with Laplacean Filter
N
n line image data
M66281
–
–
D7
Q07
B
(n+1) line
image data
X2
Subtracter
Adder
1 line
delay
N+K {2N-(A+B)}
Q00
2N-(A+B)
D0
Compensated
image data
XK
Q10
A+B
2 line
delay
A
(n-1) line
image data
Adder
–
Q17
Sub scan direction
Main scan direction
(n-1) line
A
N
B
n line
(n+1) line
N'=N+K { (N-A) + (N-B) }
=N+K { (2N - (A+B) }
K: Laplacean coefficient
13