MITSUBISHI MITSUBISHI SEMICONDUCTOR SEMICONDUCTOR <Dual-In-Line <Dual-In-Line Package Package Intelligent Intelligent Power Power Module> Module> PS21312 PS21312 TRANSFER-MOLD TRANSFER-MOLD TYPE TYPE INSULATED INSULATED TYPE TYPE PS21312 INTEGRATED POWER FUNCTIONS 3rd generation IGBT inverter bridge for 3 phase DC-to-AC power conversion. INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS • For upper-leg IGBTS : Drive circuit, High voltage isolated high-speed level shifting, Control circuit under-voltage (UV) protection. Note : Bootstrap supply scheme can be applied. • For lower-leg IGBTS : Drive circuit, Control circuit under-voltage protection (UV), Short-circuit protection (SC). • Fault signaling : Corresponding to a SC fault (Low-side IGBT) or a UV fault (Low-side IGBT). • Input interface : 5V line CMOS/TTL compatible, Schmitt Trigger receiver circuit. APPLICATION AC200V three-phase inverter drive for small power motor control. Fig. 1 PACKAGE OUTLINES (3.556) DUMMY PIN 12 10 11 987 A 654 321 Type name , Lot No. (0.5) 15 13 14 (8) P DE (φ2 ) .3 (φ3 TH 2) (17.4) 29 30 (8) (17.4) (0.75) (30.5) 28 27 26 25 24 23 22 21 20 19 18 16 17 (1.5) (0.5) (1.778 × 26) (1.778) (6.25) (6.25) (6.25) 34 33 (7.62) 32 31 (4MIN) (7.62 × 4) (41) (42) (49) (0.5) 35 1 2 3 4 5 PCB 6 (1) PATTERN 7 8 (1.9) SLIT 9 (1.8MIN) 10 (PCB LAYOUT) 11 Detail A *Note2 12 13 (5) 14 15 16 17 18 19 20 21 22 23 HEAT SINK SIDE 24 (35 °) 25 26 27 28 29 30 31 32 33 (1.25) 34 (2.5) 35 (0.5) TERMINAL (0.5) (1.2) (1) (10.5) (6.5) (1) TERMINAL CODE (1.656) (3.556) HEAT SINK SIDE VUFS (UPG) VUFB VP1 (COM) UP VVFS (VPG) VVFB VP1 (COM) VP VWFS (WPG) VWFB VP1 (COM) WP (UNG) VNO(NC) UN VN WN FO CFO CIN VNC VN1 (WNG) (VNG) P U V W N *Note1:(***) = Dummy Pin. *Note 2: In order to increase the surface distance between terminals, cut a slit, etc. on the PCB surface when mounting a module. * Note: The values used in the above figure are tentative. Aug. 1999 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module> PS21312 TRANSFER-MOLD TYPE INSULATED TYPE Fig. 2 INTERNAL FUNCTIONS BLOCK DIAGRAM (TYPICAL APPLICATION EXAMPLE) CBW– CBW+ CBU+ CBV+ CBV– CBU– High-side input (PWM) (5V line) Note 1,2) C3 : Tight tolerance, temp-compensated electrolytic type (Note : The capacitance value depends on the PWM control scheme used in the applied system). C4 : 0.22~2µF R-category ceramic capacitor for noise filtering. Bootstrap circuit C4 C3 Input signal Input signal Input signal coditioning coditioning coditioning For detailed description of the boot-strap circuit construction, please contact Mitsubishi Electric Level shifter Level shifter Level shifter Protection circuit (UV) Protection circuit (UV) (Note 6) Protection circuit (UV) DIP-IPM Drive circuit Drive circuit Drive circuit Inrush current limiter circuit P AC input H-side IGBTS (Note 4) C Fig. 3 U V W M AC line output Z N1 VNC Z : Surge absorber C : AC filter (Ceramic capacitor 2.2~6.5nF) (Protection against common-mode noise) N L-side IGBTS CIN Drive circuit SC protection Fo logic Input signal conditioning Control supply Under-Voltage protection FO CFO Low-side input (PWM) (5V line) (Note 1, 2) FO output (5V line) (Note 3, 5) Note1: 2: 3: 4: 5: 6: VD VNC (15V line) To prevent the input signals oscillation, an RC coupling at each input is recommended. (see also Fig. 6) By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU terminals without any opto-coupler or transformer isolation is possible. (see also Fig. 6) This output is open collector type. The signal line should be pulled up to the positive side of the 5V power supply with approximately 5.1kΩ resistance. (see also Fig. 6) The wiring between the power DC link capacitor and the P/N1 terminals should be as short as possible to protect the DIP-IPM against catastrophic high surge voltages. For extra precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to these P and N1 DC power input terminals. Fo output pulse width should be decided by connecting external capacitor between CFO and VNC terminals. (Example : CFO=22nF tFO=1.8ms (Typ.)) High voltage diodes (600V or more) should be used in the bootstrap circuit. Fig. 3 EXTERNAL PART OF THE DIP-IPM PROTECTION CIRCUIT DIP-IPM Short Circuit Protective Function (SC) : SC protection is achieved by sensing the L-side DC-Bus current (through the external shunt resistor) after allowing a suitable filtering time (defined by the RC circuit). When the sensed shunt voltage exceeds the SC trip-level, all the L-side IGBTs are turned OFF and a fault signal (Fo) is output. Since the SC fault may be repetitive, it is recommended to stop the system when the Fo signal is received and check the fault. Drive circuit P IC (A) H-side IGBTS SC Protection Trip Level U V W L-side IGBTS External protection circuit N1 Shunt Resistor A N VNC C R Drive circuit CIN B C Collector current waveform Protection circuit Note1: In the recommended external protection circuit, please select the RC time constant in the range 1.5~2.0µs. 2: To prevent erroneous protection operation, the wiring of A, B, C should be as short as possible. 0 2 tw (µs) Aug. 1999 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module> PS21312 TRANSFER-MOLD TYPE INSULATED TYPE MAXIMUM RATINGS (Tj = 25°C, unless otherwise noted) INVERTER PART Symbol VCC VCC(surge) VCES ±IC ±ICP PC Tj Parameter Condition Applied between P-N Supply voltage Supply voltage (surge) Collector-emitter voltage Each IGBT collector current Each IGBT collector current (peak) Collector dissipation Junction temperature Ratings Applied between P-N TC = 25°C TC = 25°C, instantaneous value (pulse) TC = 25°C, per 1 chip (Note 1) 450 500 600 5 10 20 –20~+150 Unit V V V A A W °C Note 1 : The maximum junction temperature rating of the power chips integrated within the DIP-IPM is 150°C (@ T f ≤ 100°C). However, to ensure safe operation of the DIP-IPM, the average junction temperature should be limited to T j(ave) ≤ 125°C (@ Tf ≤ 100°C). CONTROL (PROTECTION) PART Symbol VD Parameter Control supply voltage Condition Applied between VP1-VNC , VN1 -VNC VDB Control supply voltage VCIN Input voltage VFO Fault output supply voltage Fault output current Current sensing input voltage Applied between VUFB-VUFS, VVFB-VVFS , VWFB-VWFS Applied between UP, VP, WP-VNC, UN, VN, W N-VNC Applied between F O-VNC Sink current at F O terminal Applied between CIN-V NC IFO VSC Ratings 20 Unit V 20 V –0.5~+5.5 V –0.5~VD+0.5 15 –0.5~VD+0.5 V mA V Ratings Unit 400 V –20~+100 –40~+125 °C °C 1500 Vrms TOTAL SYSTEM Symbol Parameter VCC(PROT) Self protection supply voltage limit (short-circuit protection capability) Heat-fin operation temperature Tf Tstg Storage temperature Viso Isolation voltage Condition VD = 13.5~16.5V, Inverter part Tj = 125°C, non-repetitive, less than 2 µs (Note 2) 60Hz, Sinusoidal, AC 1 minute, connection pins to heat-sink plate Note 2 : Tf MEASUREMENT POINT Al Board Specifications: Dimensions 100 × 100 × 10mm, finishing: 12s, warp: –50~100µm Control Terminals FWDi Chip 18mm IGBT/FWDi Chip 16mm Al Board Groove IGBT Chip Temp. measurement point (inside the Al board) N W V U P Temp. measurement point (inside the Al board) Power Terminals 100~200µm of evenly applied Silicon-Grease Aug. 1999 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module> PS21312 TRANSFER-MOLD TYPE INSULATED TYPE THERMAL RESISTANCE Symbol Rth(j-f)Q Rth(j-f)F Parameter Junction-to-heat sink thermal resistance Limits Condition Inverter IGBT part (per 1/6 module) Inverter FWDi part (per 1/6 module) Min. Typ. Max. — — — — 6.0 6.5 Unit °C/W ELECTRICAL CHARACTERISTICS (Tj = 25°C, unless otherwise noted) INVERTER PART Symbol Condition Parameter VCE(sat) Collector-emitter saturation voltage VEC ton trr tc(on) toff tc(off) FWDi forward voltage ICES Collector-emitter cut-off current Min. — — — 0.1 — — — — — — IC = 5A, Tj = 25°C VD = VDB = 15V VCIN = 0V IC = 5A, Tj = 125°C Tj = 25°C, –IC = 5A, VCIN = 5V VCC = 300V, VD = 15V IC = 5A, Tj = 125°C Switching times Inductive load (upper-lower arm) VCIN = 5 ↔ 0V VCE = VCES Tj = 25°C Tj = 125°C Limits Typ. Unit 2.1 2.2 1.7 0.6 0.1 0.2 1.1 0.35 — — Max. 2.9 3.2 2.9 1.1 — 0.6 2.2 1.25 1.0 10 Min. 13.5 13.5 — — — — 4.9 — 0.8 — Limits Typ. 15.0 15.0 4.25 0.50 4.95 0.50 — 0.8 1.2 15 Max. 16.5 16.5 8.50 1.00 9.70 1.00 — 1.2 1.8 — V V mA mA mA mA V V V kHz 3.0 — — µs 0.45 10.0 10.5 10.3 10.8 1.0 0.8 2.5 0.8 2.5 0.5 — — — 0.55 12.0 12.5 12.5 — 1.8 1.4 3.0 1.4 3.0 13.0 — 2.0 4.0 2.0 4.0 V V V V V ms V V µs mA CONTROL (PROTECTION) PART Symbol VD VDB ID Control supply voltage Control supply voltage Circuit current VFOH VFOL VFOsat fPWM tdead VSC(ref) UVDBt UVDBr UVDt UVDr tFO Vth(on) Vth(off) Vth(on) Vth(off) Condition Parameter Fault output voltage PWM input frequency Allowable deadtime Short-circuit trip level Applied between VP1-VNC, VN1-VNC Applied between VUFB-VUFS, VVFB-VVFS , VWFB-VWFS VD = 15V, VCIN = 5V Total of VP1-VNC, VN1-VNC VDB = 15V, VCIN = 5V VUFB-VUFS, VVFB -VVFS, VWFB-VWFS VD = 15V, VCIN = 0V VP1-VNC , VN1 -VNC VDB = 15V, VCIN = 0V VUFB-VUFS, VVFB -VVFS, VWFB-VWFS VSC = 0V, FO circuit : 10kΩ to 5V pull-up VSC = 1V, FO circuit : 10kΩ to 5V pull-up VSC = 1V, IFO = 15mA Tj ≤ 125°C, Tf ≤ 100°C Relates to corresponding input signal for blocking arm shoot-through. (Tf ≤ 100°C) (Note 3) Tj = 25°C, VD = 15V Supply circuit under-voltage protection Tj ≤ 125°C Fault output pulse width ON threshold voltage OFF threshold voltage ON threshold voltage OFF threshold voltage CFO = 22nF H-side L-side Trip level Reset level Trip level Reset level (Note 4) Applied between: UP, VP, WP-VNC Applied between: UN, VN, W N-VNC Unit V V Note 3 : Short-circuit protection operates only at the low-arms. Please select the value of the external shunt resistor such that the SC trip level is less than 8.5A 4 : Fault signal is outputted when the low-arm short-circuit or control supply under-voltage protective functions operate. The fault output pulse-width tFO depends on the capacitance value of CFO according to the following approximate equation. : CFO = (12.2 ✕ 10-6) ✕ tFO [F] Aug. 1999 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module> PS21312 TRANSFER-MOLD TYPE INSULATED TYPE MECHANICAL CHARACTERISTICS AND RATINGS Parameter Condition Mounting torque Mounting screw : M3 Weight Heat-sink flatness Recommended 8kg·cm Recommended 0.78N·m (Note 5) Min. — — — –50 Limits Typ. 8 0.78 20 — Max. — — — 100 Min. Limits Typ. Max. Unit kg·cm N·m g µm RECOMMENDED OPERATION CONDITIONS Symbol Parameter Condition VCC VD VDB ∆VD, ∆VDB tdead fPWM VCIN(ON) VCIN(OFF) Supply voltage Control supply voltage Control supply voltage Control supply variation Arm shoot-through blocking time PWM input frequency Input ON voltage Input OFF voltage Applied between P-N Applied between VP1-VNC, VN1 -VNC Applied between VUFB-VUFS, VVFB -VVFS, VWFB-VWFS For each input signal Tj ≤ 125°C, Tf ≤ 100°C Applied between UP, VP, WP-VNC Applied between U N, VN, W N-VNC 0 13.5 13.5 –1 3 — 300 15.0 15.0 — — 15 0~0.65 4.0~5.5 400 16.5 16.5 1.0 — — Unit V V V V/µs µs kHz V V Note 5: DIP-IPM +– Measurement Range 3mm Heat-sink – + Heat-sink Aug. 1999 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module> PS21312 TRANSFER-MOLD TYPE INSULATED TYPE VUFB VCC VB VUFS VP1 IN HO HVIC 1 UP COM VS VVFS VCC VB VVFB VP1 IN HO HVIC 2 VP COM VS VWFB VCC VB VWFS VP1 IN HO HVIC 3 WP COM LVIC UOUT VOUT WOUT VS VN1 VCC UN UN WN VN WN VN Fo Fo VNO CIN P U V W N VNO(NC) DIP-IPM CIN CFO CFO GND VNC Fig. 4 THE DIP-IPM INTERNAL CIRCUIT * Note: The IGBTs gates and the HVICs COM terminals are connected to the dummy pins (not shown in Figure 4). Aug. 1999 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module> PS21312 TRANSFER-MOLD TYPE INSULATED TYPE Fig. 5 TIMING CHARTS OF THE DIP-IPM PROTECTIVE FUNCTIONS [A] Short-Circuit Protection (Lower-arms only) (For the external shunt resistance and CR connection, please refer to Fig. 3.) a1. Normal operation : IGBT ON and carrying current. a2. Short-circuit current detection (SC trigger). a3. IGBT gate interrupt. a4. IGBT turns OFF. a5. FO timer operation starts : The pulse width of the F O signal is set by the external capacitor CFO. a6. Input “H” : IGBT OFF state. a7. Input “L” : IGBT ON state, but during the F O active signal the IGBT doesn’t turn ON. a8. IGBT OFF state. Lower-arms control input a6 Protection circuit state a7 SET Internal IGBT gate RESET a3 a2 SC a4 a1 Output current Ic(A) a8 SC reference voltage Sense voltage of the shunt resistance CR circuit time constant DELAY (*Note) Fault output Fo a5 Note : The CR time constant safe guards against erroneous SC fault signals resulting from di/dt generated voltages when the IGBT turns ON. The optimum setting for the CR circuit time constant is 1.5~2.0µs. [B] Under-Voltage Protection (N-side, UVD) a1. Normal operation : IGBT ON and carrying current. a2. Under-voltage trip (UVDt). a3. IGBT OFF inspite of control input condition. a4. FO timer operation starts : The pulse width of the F O signal is set by the external capacitor CFO. a5. Under-voltage reset (UVDr). a6. Normal operation : IGBT ON and carrying current. Control input Protection circuit state Control supply voltage VD RESET SET UVDr UVDt a5 a2 a1 a3 a6 Output current Ic(A) Fault output Fo (N-side only) a4 Aug. 1999 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module> PS21312 TRANSFER-MOLD TYPE INSULATED TYPE [C] Under-Voltage Protection (P-side, UVDB) a1. Control supply voltage rises : After the voltage level reachs UVDBr, the circuits start to operate when the next input is applied. a2. Normal operation : IGBT ON and carrying current. a3. Under-voltage trip (UVDBt). a4. IGBT OFF inspite of control input condition (there is no FO signal output). a5. Under-voltage reset (UVDBr). a6. Normal operation : IGBT ON and carrying current. Control input Protection circuit state RESET SET RESET UVDBr Control supply voltage VDB a1 UVDBt a2 a5 a3 a4 a6 Output current Ic(A) High-level (no fault output) Fault output Fo Fig. 6 RECOMMENDED CPU I/O INTERFACE CIRCUIT 5V line 4.7kΩ DIP-IPM 5.1kΩ UP,VP,WP,UN,VN,WN Fo CPU 1nF 1nF VNC(Logic) Note : RC coupling at each input (parts shown dotted) may change depending on the PWM control scheme used in the application and on the wiring impedance of the application’s printed circuit board. Aug. 1999 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module> PS21312 TRANSFER-MOLD TYPE INSULATED TYPE Fig. 7 TYPICAL DIP-IPM APPLICATION CIRCUIT EXAMPLE For detailed description of the bootstrap circuit construction, please contact Mitsubishi Electric 5V line C1: Tight tolerance temp - compensated electrolytic type; C2,C3: 0.22~2 µ F R -category ceramic capacitor for noise filtering (Note : The capacitance value depends on the PWM control used in the applied system.) C2 VUFB C1 VUFS DIP-IPM P VP1 C3 UP VCC VB IN HO COM VS VCC VB IN HO COM VS VCC VB IN HO C2 U VVFB C1 VVFS VP1 C3 VP C2 V M VWF C1 C P U VWFS VP1 C3 WP U N I T COM W VS UOUT C3 VN1 VCC 5V line VOUT UN VN WN Fo UN VN WOUT If this wiring is too long, it might cause SC malfunction. WN Fo VNO CIN VNC GND N CFO C 15V line CFO CIN C4(CFO ) A The long wiring of GND might generate noise on input signals and cause IGBT drive malfunction. B C5 R1 Shunt resistance If this wiring is too long, the SC level fluctuation might be large and cause SC malfunction. N1 Note 1 : To prevent the input signals oscillation, an RC coupling at each input is recommended, and the wiring of each input should be as short as possible. (Less than 2cm) 2 : By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU terminals without any opto-coupler or transformer isolation is possible. 3 : FO output is open collector type. This signal line should be pulled up to the positive side of the 5V power supply with approximately 5.1kΩ resistance. 4 : FO output pulse width should be decided by connecting an external capacitor between CFO and VNC terminals (C FO). (Example : CFO = 22 nF → tFO = 1.8 ms (typ.)) 5 : Each input signal line should be pulled up to the positive side of the 5V power supply with approximately 4.7kΩ resistance (other RC coupling circuits at each input may be needed depending on the PWM control scheme used and on the wiring impedances of the system’s printed circuit board). Approximately a 0.22~2µF by-pass capacitor should be used across each power supply connection terminals. 6 : To prevent errors of the protection function, the wiring of A, B, C should be as short as possible. 7 : In the recommended protection circuit, please select the R1C5 time constant in the range of 1.5~2µs. 8 : Each capacitor should be put as nearby the terminals of the DIP-IPM as possible. 9 : To prevent surge destruction, the wiring between the smoothing capacitor and the P&N1 terminals should be as short as possible. Approximately a 0.1~0.22µF snubber capacitor between the P&N1 terminals is recommended. Aug. 1999