SEMICONDUCTOR TECHNICAL DATA The MC14508B dual 4–bit latch is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. The part consists of two identical, independent 4–bit latches with separate Strobe (ST) and Master Reset (MR) controls. Separate Disable inputs force the outputs to a high impedance state and allow the devices to be used in time sharing bus line applications. These complementary MOS latches find primary use in buffer storage, holding register, or general digital logic functions where low power dissipation and/or high noise immunity is desired. L SUFFIX CERAMIC CASE 623 P SUFFIX PLASTIC CASE 709 • 3–State Output • Supply Voltage Range = 3.0 Vdc to 18 Vdc • Capable–of Driving Two Low–power TTL Loads or One Low–power Schottky TTL Load over the Rated Temperature Range ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS* (Voltages Referenced to VSS) Symbol VDD Vin, Vout Iin, Iout PD Tstg Parameter DC Supply Voltage Value Unit – 0.5 to + 18.0 V Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V Input or Output Current (DC or Transient), per Pin ± 10 mA 500 mW – 65 to + 150 _C Power Dissipation, per Package† Storage Temperature Disable 0 D3 0 D2 0 D1 0 D0 0 Q3 0 Q2 0 Q1 0 Q0 0 0 1 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 X X X X 1 X X X 0 1 X X X X X X X X Latched 0 0 0 0 High Impedance CIRCUIT DIAGRAM Plastic Ceramic SOIC 1 2 3 4 6 8 10 MR ST DIS D0 D1 D2 D3 Q0 5 Q1 7 Q2 9 Q3 11 13 14 15 16 18 20 22 MR ST DIS D0 D1 D2 D3 Q0 17 Q1 19 Q2 21 Q3 23 VDD = PIN 24 VSS = PIN 12 X = Don’t Care DIS MC14XXXBCP MC14XXXBCL MC14XXXBDW BLOCK DIAGRAM TRUTH TABLE ST 1 ORDERING INFORMATION TA = – 55° to 125°C for all packages. TL Lead Temperature (8–Second Soldering) 260 _C * Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C MR 0 DW SUFFIX SOIC CASE 751E VDD MR ST Qn Dn (TO OTHER THREE LATCHES) VSS REV 3 1/94 MC14508B Motorola, Inc. 1995 344 MOTOROLA CMOS LOGIC DATA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Output Voltage Vin = VDD or 0 Symbol – 55_C 25_C 125_C VDD Vdc Min Max Min Typ # Max Min Max Unit “0” Level VOL 5.0 10 15 — — — 0.05 0.05 0.05 — — — 0 0 0 0.05 0.05 0.05 — — — 0.05 0.05 0.05 Vdc “1” Level VOH 5.0 10 15 4.95 9.95 14.95 — — — 4.95 9.95 14.95 5.0 10 15 — — — 4.95 9.95 14.95 — — — Vdc 5.0 10 15 — — — 1.5 3.0 4.0 — — — 2.25 4.50 6.75 1.5 3.0 4.0 — — — 1.5 3.0 4.0 5.0 10 15 3.5 7.0 11 — — — 3.5 7.0 11 2.75 5.50 8.25 — — — 3.5 7.0 11 — — — 5.0 5.0 10 15 – 3.0 – 0.64 – 1.6 – 4.2 — — — — – 2.4 – 0.51 – 1.3 – 3.4 – 4.2 – 0.88 – 2.25 – 8.8 — — — — – 1.7 – 0.36 – 0.9 – 2.4 — — — — IOL 5.0 10 15 0.64 1.6 4.2 — — — 0.51 1.3 3.4 0.88 2.25 8.8 — — — 0.36 0.9 2.4 — — — mAdc Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc Input Capacitance (Vin = 0) Cin — — — — 5.0 7.5 — — pF Quiescent Current (Per Package) IDD 5.0 10 15 — — — 5.0 10 20 — — — 0.005 0.010 0.015 5.0 10 20 — — — 150 300 600 µAdc Total Supply Current**† (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) IT 5.0 10 15 Three–State Leakage Current ITL 15 Vin = 0 or VDD Input Voltage “0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) VIL “1” Level VIH (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) Vdc Vdc IOH Source (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Sink mAdc IT = (1.46 µA/kHz) f + IDD IT = (2.91 µA/kHz) f + IDD IT = (4.37 µA/kHz) f + IDD — ± 0.1 — ± 0.0001 ± 0.1 µAdc — ± 3.0 µAdc #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. ** The formulas given are for the typical characteristics only at 25_C. ā †To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.008. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. MOTOROLA CMOS LOGIC DATA MC14508B 345 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C) All Types Characteristic Symbol VDD Min Typ # Max 5.0 10 15 — — — 100 50 40 200 100 80 5.0 10 15 — — — 220 90 60 440 180 120 tWH(R) 5.0 10 15 200 100 70 100 50 35 — — — ns trem 5.0 10 15 30 25 20 – 15 0 0 — — — ns tWH(S) 5.0 10 15 140 70 40 70 35 20 — — — ns Setup Time Data to Strobe tsu 5.0 10 15 50 20 10 25 10 5.0 — — — ns Hold Time Strobe to Data th 5.0 10 15 50 35 35 20 10 10 — — — ns 5.0 10 15 — — — 55 35 30 170 100 70 Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns tTLH, tTHL Propagation Delay Time, Dn or MR to Q tPLH, tPHL = (1.7 ns/pF) CL + 135 ns tPLH, tPHL = (0.66 ns/pF) CL + 57 ns tPLH, tPHL = (0.5 ns/pF) CL + 35 ns tPLH, tPHL Master Reset Pulse Width Master Reset Removal Time Strobe Pulse Width Unit ns ns ns 3–State Propagation Delay Time Output “1” to High Impedance tPHZ Output “0” to High Impedance tPLZ 5.0 10 15 — — — 75 40 35 170 100 70 High Impedance to “1” Level tPZH 5.0 10 15 — — — 80 35 30 170 100 70 High Impedance to “0” Level tPZL 5.0 10 15 — — — 105 50 35 210 100 70 * The formulas given are for the typical characteristics only at 25_C. #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. PIN ASSIGNMENT MC14508B 346 MRA 1 24 VDD STA 2 23 Q3B DISA 3 22 D3B D0A 4 21 Q2B Q0A 5 20 D2B D1A 6 19 Q1B Q1A 7 18 D1B D2A 8 17 Q0B Q2A 9 16 D0B D3A 10 15 DISB Q3A 11 14 STB VSS 12 13 MRB MOTOROLA CMOS LOGIC DATA tWH(S) STROBE INPUT 50% 50% tsu tWH(R) th Dn INPUT MASTER RESET INPUT 50% tPLH Qn OUTPUT tPHL 10% VSS VOH Qn OUTPUT 90% 50% tTLH VDD 50% VOL tTHL Figure 1. AC Waveforms VDD MR ST DISABLE D0 D1 D2 D3 PULSE GENERATOR VDD ST3 VDD Q0 ST1 Q1 Q2 1.0 k Test ST1 ST2 ST3 ST4 tPHZ tPLZ tPZL tPZH Open Close Close Open Close Open Open Close Close Open Open Close Open Close Close Open Q3 1.0 k ST4 VSS CL ST2 20 ns 20 ns DISABLE VDD 90% 50% 10% tPLZ tPZL 90% 10% Q3 OUTPUT tPHZ VSS VOH ≈ 2.5 V @ VDD = 5 V, 10 V, AND 15 V ≈ 2 V @ VDD = 5 V ≈ 6 V @ VDD = 10 V ≈ 10 V @ VDD = 15 V VOL tPZH 90% 10% Figure 2. 3–State AC Test Circuit and Waveforms MOTOROLA CMOS LOGIC DATA MC14508B 347 IOD 3–STATE MODE OF OPERATION The MC14508B can be used in bussed systems as shown. The output terminals of N 4–bit latches can be directly wired to a bus line, and to one of the 4–bit latches selected. The selected latch controls the logic state of the bus line and the remaining (N–1) 4–bit latches are disabled into a high impedance “off” state. The number of latches, N, which may be connected to a bus line is determined from the output drive current, IOD, the 3–state or disabled output leakage current, ITL, and the load current, IL, required to drive the bus line (including fanout to other device inputs) and can be calculated by the following: IOD – IL N= +1 ITL SELECTED AS 1/2 DRIVING DEVICE MC14508B IOD ITL 1/2 DISABLED MC14508B ITL N must be calculated for both high and low logic states of the bus line. ITL 1/2 DISABLED MC14508B ITL IL IL BUS LINES TYPICAL 3–STATE APPLICATIONS EXAMPLE 1 RESET CLOCK MC14015B SERIAL DATA 4–BIT SHIFT REGISTER 4–BIT SHIFT REGISTER MC QUAD LATCH 14508B (3–STATE) QUAD LATCH (3–STATE) STROBE DISABLE DISABLE 4–LINE DATA BUS EXAMPLE 2 DATA BUS 3–STATE 4–BIT LATCH 3–STATE 4–BIT LATCH MC 14508B MC 14508B 4–LINE DATA BUS 4–LINE DATA BUS MC14519B A B 3–STATE 4–BIT LATCH MC14508B 348 3–STATE 4–BIT LATCH MOTOROLA CMOS LOGIC DATA OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 623–05 ISSUE M 24 NOTES: 1. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 2. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION (WHEN FORMED PARALLEL). 13 B 1 12 DIM A B C D F G J K L M N A F SEATING PLANE C L N D G INCHES MIN MAX 1.230 1.290 0.500 0.610 0.160 0.220 0.016 0.020 0.050 0.060 0.100 BSC 0.008 0.012 0.125 0.160 0.600 BSC 0_ 15_ 0.020 0.050 J M K MILLIMETERS MIN MAX 31.24 32.77 12.70 15.49 4.06 5.59 0.41 0.51 1.27 1.52 2.54 BSC 0.20 0.30 3.18 4.06 15.24 BSC 0_ 15 _ 0.51 1.27 P SUFFIX PLASTIC DIP PACKAGE CASE 709–02 ISSUE C 24 NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 13 B 1 12 A L C N K H F G D MOTOROLA CMOS LOGIC DATA SEATING PLANE M J DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 31.37 32.13 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.03 0.20 0.38 2.92 3.43 15.24 BSC 0_ 15_ 0.51 1.02 INCHES MIN MAX 1.235 1.265 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.080 0.008 0.015 0.115 0.135 0.600 BSC 0_ 15_ 0.020 0.040 MC14508B 349 OUTLINE DIMENSIONS DW SUFFIX PLASTIC SOIC PACKAGE CASE 751E–04 ISSUE E –A– 24 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. 13 –B– 12X P 0.010 (0.25) 1 M B M 12 24X D J 0.010 (0.25) M T A S B S F R C –T– SEATING PLANE M 22X K G X 45 _ DIM A B C D F G J K M P R MILLIMETERS MIN MAX 15.25 15.54 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 BSC 0.23 0.32 0.13 0.29 0_ 8_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.601 0.612 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0_ 8_ 0.395 0.415 0.010 0.029 Motorola reserves the right to make changes without further notice to any products herein. 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How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315 MFAX: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 MC14508B 350 ◊ *MC14508B/D* MOTOROLA CMOS LOGIC DATA MC14508B/D