SEMICONDUCTOR TECHNICAL DATA ! ! ! High–Performance Silicon–Gate CMOS J SUFFIX CERAMIC PACKAGE CASE 732–03 20 1 The MC54/74HC244A is identical in pinout to the LS244. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This octal noninverting buffer/line driver/line receiver is designed to be used with 3–state memory address drivers, clock drivers, and other bus–oriented systems. The device has noninverting outputs and two active–low output enables. The HC244A is similar in function to the HC240A and HC241A. N SUFFIX PLASTIC PACKAGE CASE 738–03 20 1 DW SUFFIX SOIC PACKAGE CASE 751D–04 20 1 • • • • • • Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 µA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A • Chip Complexity: 136 FETs or 34 Equivalent Gates 1 SD SUFFIX SSOP PACKAGE CASE 940C–03 1 DT SUFFIX TSSOP PACKAGE CASE 948E–02 20 20 ORDERING INFORMATION MC54HCXXXAJ Ceramic MC74HCXXXAN Plastic MC74HCXXXADW SOIC MC74HCXXXASD SSOP MC74HCXXXADT TSSOP LOGIC DIAGRAM A1 A2 A3 A4 DATA INPUTS B1 B2 B3 B4 2 18 4 16 6 14 8 12 11 9 13 7 15 5 17 3 PIN ASSIGNMENT YA1 YA2 YA3 YA4 NONINVERTING OUTPUTS ENABLE A 1 20 VCC A1 2 19 ENABLE B YB4 3 18 YA1 A2 4 17 B4 YB3 5 16 YA2 A3 6 15 B3 YB2 7 14 YA3 YB2 A4 8 13 B2 YB1 9 12 YA4 YB3 GND 10 11 B1 YB1 YB4 FUNCTION TABLE OUTPUT ENABLES 1 ENABLE A 19 ENABLE B PIN 20 = VCC PIN 10 = GND Inputs Outputs Enable A, Enable B A, B YA, YB L L H L H X L H Z Z = high impedance 10/95 Motorola, Inc. 1995 1 REV 6 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MC54/74HC244A MAXIMUM RATINGS* Symbol VCC Parameter DC Supply Voltage (Referenced to GND) Value Unit – 0.5 to + 7.0 V V Vin DC Input Voltage (Referenced to GND) – 1.5 to VCC + 1.5 Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V DC Input Current, per Pin ± 20 mA Iout DC Output Current, per Pin ± 35 mA ICC DC Supply Current, VCC and GND Pins ± 75 mA PD Power Dissipation in Still Air, Plastic or Ceramic DIP† SOIC Package† SSOP or TSSOP Package† 750 500 450 mW Tstg Storage Temperature – 65 to + 150 _C Iin TL This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. v v _C Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC, SSOP or TSSOP Package) (Ceramic DIP) 260 300 * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. †Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C Ceramic DIP: – 10 mW/_C from 100_ to 125_C SOIC Package: – 7 mW/_C from 65_ to 125_C SSOP or TSSOP Package: – 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ v ÎÎÎÎ v ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ v ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ v ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ v ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ v ÎÎÎÎ v ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ v ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ v ÎÎÎÎ v ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter DC Supply Voltage (Referenced to GND) Min Max Unit 2.0 6.0 V 0 VCC V – 55 + 125 _C 0 0 0 1000 500 400 ns DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Symbol Parameter Test Conditions VCC V – 55 to 25_C 85_C 125_C Unit VIH Minimum High–Level Input Voltage Vout = VCC – 0.1 V |Iout| 20 µA 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V VIL Maximum Low–Level Input Voltage Vout = 0.1 V |Iout| 20 µA 2.0 4.5 6.0 0.5 1.35 1.8 0.5 1.35 1.8 0.5 1.35 1.8 V Minimum High–Level Output Voltage Vin = VIH |Iout| 20 µA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 4.5 6.0 3.98 5.48 3.84 5.34 3.70 5.20 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 4.5 6.0 0.26 0.26 0.33 0.33 0.40 0.40 6.0 ± 0.1 ± 1.0 ± 1.0 VOH Vin = VIH VOL Maximum Low–Level Output Voltage MOTOROLA Maximum Input Leakage Current 6.0 mA 7.8 mA Vin = VIL |Iout| 20 µA Vin = VIL Iin |Iout| |Iout| |Iout| |Iout| Vin = VCC or GND 2 6.0 mA 7.8 mA V µA High–Speed CMOS Logic Data DL129 — Rev 6 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ v ÎÎÎÎ v ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ v v ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MC54/74HC244A DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Symbol Parameter Test Conditions VCC V – 55 to 25_C 85_C 125_C Unit IOZ Maximum Three–State Leakage Current Output in High–Impedance State Vin = VIL or VIH Vout = VCC or GND 6.0 ± 0.5 ± 5.0 ± 10 µA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0 µA 6.0 4 40 160 µA NOTE: Information on typical parametric values and high frequency or heavy load considerations can be found in Chapter 2 of the Motorola High– Speed CMOS Data Book (DL129/D). AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Guaranteed Limit Symbol Parameter VCC V – 55 to 25_C 85_C 125_C Unit tPLH, tPHL Maximum Propagation Delay, A to YA or B to YB (Figures 1 and 3) 2.0 4.5 6.0 96 18 15 115 23 20 135 27 23 ns tPLZ, tPHZ Maximum Propagation Delay, Output Enable to YA or YB (Figures 2 and 4) 2.0 4.5 6.0 110 22 19 140 28 24 165 33 28 ns tPZL, tPZH Maximum Propagation Delay, Output Enable to YA or YB (Figures 2 and 4) 2.0 4.5 6.0 110 22 19 140 28 24 165 33 28 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 3) 2.0 4.5 6.0 60 12 10 75 15 13 90 18 15 ns Maximum Input Capacitance — 10 10 10 pF Maximum Three–State Output Capacitance (Output in High–Impedance State) — 15 15 15 pF Cin Cout NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High– Speed CMOS Data Book (DL129/D). Typical @ 25°C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Buffer)* pF 34 * Used to determine the no–load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). SWITCHING WAVEFORMS tr tf DATA INPUT A OR B tPLH VCC VCC 90% 50% 10% ENABLE A OR B GND tPHL OUTPUT Y OUTPUT Y Figure 1. High–Speed CMOS Logic Data DL129 — Rev 6 tPLZ HIGH IMPEDANCE 50% tPZH tTHL tTLH GND tPZL 90% 50% 10% OUTPUT YA OR YB 50% tPHZ 50% 10% VOL 90% VOH HIGH IMPEDANCE Figure 2. 3 MOTOROLA MC54/74HC244A TEST CIRCUITS TEST POINT TEST POINT OUTPUT DEVICE UNDER TEST OUTPUT DEVICE UNDER TEST CL* * Includes all probe and jig capacitance CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. 1 kΩ CL* * Includes all probe and jig capacitance Figure 3. Test Circuit Figure 4. Test Circuit PIN DESCRIPTIONS to these pins, the outputs are enabled and the devices function as noninverting buffers. When a high level is applied, the outputs assume the high impedance state. INPUTS A1, A2, A3, A4, B1, B2, B3, B4 (Pins 2, 4, 6, 8, 11, 13, 15, 17) Data input pins. Data on these pins appear in noninverted form on the corresponding Y outputs, when the outputs are enabled. OUTPUTS YA1, YA2, YA3, YA4, YB1, YB2, YB3, YB4 (Pins 18, 16, 14, 12, 9, 7, 5, 3) CONTROLS Device outputs. Depending upon the state of the output– enable pins, these outputs are either noninverting outputs or high–impedance outputs. Enable A, Enable B (Pins 1, 19) Output enables (active–low). When a low level is applied LOGIC DETAIL TO THREE OTHER A OR B INVERTERS ONE OF 8 INVERTERS VCC DATA INPUT A OR B YA OR YB ENABLE A OR ENABLE B MOTOROLA 4 High–Speed CMOS Logic Data DL129 — Rev 6 MC54/74HC244A OUTLINE DIMENSIONS 20 11 1 10 J SUFFIX CERAMIC PACKAGE CASE 732–03 ISSUE E NOTES: 1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE POSITION AT SEATING PLANE, AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSIONS A AND B INCLUDE MENISCUS. B A L C F DIM A B C D F G H J K L M N N H G D J K M MILLIMETERS MIN MAX 23.88 25.15 6.60 7.49 3.81 5.08 0.38 0.56 1.40 1.65 2.54 BSC 0.51 1.27 0.20 0.30 3.18 4.06 7.62 BSC 0_ 15 _ 0.25 1.02 INCHES MIN MAX 0.940 0.990 0.260 0.295 0.150 0.200 0.015 0.022 0.055 0.065 0.100 BSC 0.020 0.050 0.008 0.012 0.125 0.160 0.300 BSC 0_ 15_ 0.010 0.040 SEATING PLANE N SUFFIX PLASTIC PACKAGE CASE 738–03 ISSUE E –A– 20 11 1 10 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. B L C –T– DIM A B C D E F G J K L M N K SEATING PLANE M N E G F J D 0.25 (0.010) M T A 11 –B– 10X P 0.010 (0.25) 1 M B M 10 20X D 0.010 (0.25) M T A B S J S F R X 45 _ C –T– 18X G High–Speed CMOS Logic Data DL129 — Rev 6 K SEATING PLANE M T B M M DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D–04 ISSUE E –A– 20 20 PL 0.25 (0.010) 20 PL INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029 M 5 MOTOROLA MC54/74HC244A OUTLINE DIMENSIONS SD SUFFIX PLASTIC SSOP PACKAGE CASE 940C–03 ISSUE B K REF 0.12 (0.005) 20X 20 L/2 T U M S V 0.25 (0.010) S N M 11 N B L F ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ ÇÇÇ ÉÉÉ ÇÇÇ ÉÉÉ DETAIL E PIN 1 IDENT 1 10 K –U– A –V– 0.20 (0.008) J T U M J1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF K DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR INTRUSION SHALL NOT REDUCE DIMENSION K BY MORE THAN 0.07 (0.002) AT LEAST MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–. K1 S DIM A B C D F G H J J1 K K1 L M SECTION N–N 0.076 (0.003) –T– SEATING PLANE –W– C D G DETAIL E H 20X 0.15 (0.006) T U DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948E–02 ISSUE A K REF 0.10 (0.004) S M T U S V ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ S K K1 2X L/2 20 11 J J1 B –U– L PIN 1 IDENT SECTION N–N 1 10 0.25 (0.010) N 0.15 (0.006) T U S N F DETAIL E –W– C D G H DETAIL E 0.100 (0.004) –T– SEATING INCHES MIN MAX 0.278 0.288 0.205 0.212 0.068 0.078 0.002 0.008 0.024 0.037 0.026 BSC 0.023 0.030 0.003 0.008 0.003 0.006 0.010 0.015 0.010 0.013 0.301 0.311 0_ 8_ NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–. M A –V– MILLIMETERS MIN MAX 7.07 7.33 5.20 5.38 1.73 1.99 0.05 0.21 0.63 0.95 0.65 BSC 0.59 0.75 0.09 0.20 0.09 0.16 0.25 0.38 0.25 0.33 7.65 7.90 0_ 8_ DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 ––– 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 ––– 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ PLANE MOTOROLA 6 High–Speed CMOS Logic Data DL129 — Rev 6 MC54/74HC244A Motorola reserves the right to make changes without further notice to any products herein. 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Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315 MFAX: [email protected] –TOUCHTONE (602) 244–6609 INTERNET: http://Design–NET.com HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 High–Speed CMOS Logic Data DL129 — Rev 6 ◊ CODELINE 7 *MC54/74HC244A/D* MC54/74HC244A/D MOTOROLA