SN54/74LS190 SN54/74LS191 PRESETTABLE BCD/DECADE UP/DOWN COUNTERS PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS The SN54 / 74LS190 is a synchronous UP/ DOWN BCD Decade (8421) Counter and the SN54/ 74LS191 is a synchronous UP / DOWN Modulo-16 Binary Counter. State changes of the counters are synchronous with the LOW-to-HIGH transition of the Clock Pulse input. An asynchronous Parallel Load (PL) input overrides counting and loads the data present on the Pn inputs into the flip-flops, which makes it possible to use the circuits as programmable counters. A Count Enable (CE) input serves as the carry / borrow input in multi-stage counters. An Up / Down Count Control (U/D) input determines whether a circuit counts up or down. A Terminal Count (TC) output and a Ripple Clock (RC) output provide overflow/underflow indication and make possible a variety of methods for generating carry / borrow signals in multistage counter applications. • • • • • • • • PRESETTABLE BCD/ DECADE UP/ DOWN COUNTERS PRESETTABLE 4-BIT BINARY UP/ DOWN COUNTERS LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 620-09 16 1 Low Power . . . 90 mW Typical Dissipation High Speed . . . 25 MHz Typical Count Frequency Synchronous Counting Asynchronous Parallel Load Individual Preset Inputs Count Enable and Up/ Down Control Inputs Cascadable Input Clamp Diodes Limit High Speed Termination Effects N SUFFIX PLASTIC CASE 648-08 16 1 D SUFFIX SOIC CASE 751B-03 16 CONNECTION DIAGRAM DIP (TOP VIEW) 1 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. PIN NAMES CE CP U/D PL Pn Qn RC TC Count Enable (Active LOW) Input Clock Pulse (Active HIGH going edge) Input Up/Down Count Control Input Parallel Load Control (Active LOW) Input Parallel Data Inputs Flip-Flop Outputs (Note b) Ripple Clock Output (Note b) Terminal Count Output (Note b) Ceramic Plastic SOIC LOGIC SYMBOL LOADING (Note a) HIGH LOW 1.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 10 U.L. 10 U.L. 0.7 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L. 5 (2.5) U.L. 5 (2.5) U.L. NOTES: a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) b. Temperature Ranges. FAST AND LS TTL DATA 5-341 SN54/74LS190 • SN54/74LS191 STATE DIAGRAMS LS190 # " % " # " LS191 ⋅ ⋅ ⋅ ⋅ # " ⋅ ⋅ ⋅ ⋅ # % ⋅ ⋅ # ⋅ ⋅ ⋅ ⋅ # #" # #" % LS190 LS191 LOGIC DIAGRAMS # !" !" !" !" ! FAST AND LS TTL DATA 5-342 DECADE COUNTER LS190 $ # " SN54/74LS190 • SN54/74LS191 LOGIC DIAGRAMS (continued) ! BINARY COUNTER LS191 5-343 FAST AND LS TTL DATA SN54/74LS190 • SN54/74LS191 FUNCTIONAL DESCRIPTION The LS190 is a synchronous Up / Down BCD Decade Counter and the LS191 is a synchronous Up / Down 4-Bit Binary Counter. The operating modes of the LS190 decade counter and the LS191 binary counter are identical, with the only difference being the count sequences as noted in the state diagrams. Each circuit contains four master / slave flip-flops, with internal gating and steering logic to provide individual preset, count-up and count-down operations. Each circuit has an asynchronous parallel load capability permitting the counter to be preset to any desired number. When the Parallel Load (PL) input is LOW, information present on the Parallel Data inputs (P0 – P3) is loaded into the counter and appears on the Q outputs. This operation overrides the counting functions, as indicated in the Mode Select Table. A HIGH signal on the CE input inhibits counting. When CE is LOW, internal state change are initiated synchronously by the LOW-to-HIGH transition of the clock input. The direction of counting is determined by the U/D input signal, as indicated in the Mode Select Table. When counting is to be enabled, the CE signal can be made LOW when the clock is in either state. However, when counting is to be inhibited, the LOW-to-HIGH CE transition must occur only while the clock is HIGH. Similarly, the U / D signal should only be changed when either CE or the clock is HIGH. Two types of outputs are provided as overflow/underflow indicators. The Terminal Count (TC) output is normally LOW and goes HIGH when a circuit reaches zero in the count-down mode or reaches maximum (9 for the LS190, 15 for the LS191) in the count-up mode. The TC output will then remain HIGH until a state change occurs, whether by counting or presetting or until U / D is changed. The TC output should not be used as a clock signal because it is subject to decoding spikes. The TC signal is also used internally to enable the Ripple Clock (RC) output. The RC output is normally HIGH. When CE is LOW and TC is HIGH, the RC output will go LOW when the clock next goes LOW and will stay LOW until the clock goes HIGH again. This feature simplifies the design of multi-stage counters, as indicated in Figures a and b. In Figure a, each RC output is used as the clock input for the next higher stage. This configuration is particularly advantageous when the clock source has a limited drive capability, since it drives only the first stage. To prevent counting in all stages it is only necessary to inhibit the first stage, since a HIGH signal on CE inhibits the RC output pulse, as indicated in the RC Truth Table. A disadvantage of this configuration, in some applications, is the timing skew between state changes in the first and last stages. This represents the cumulative delay of the clock as it ripples through the preceding stages. A method of causing state changes to occur simultaneously in all stages is shown in Figure b. All clock inputs are driven in parallel and the RC outputs propagate the carry / borrow signals in ripple fashion. In this configuration the LOW state duration of the clock must be long enough to allow the negative-going edge of the carry / borrow signal to ripple through to the last stop before the clock goes HIGH. There is no such restriction on the HIGH state duration of the clock, since the RC output of any package goes HIGH shortly after its CP input goes HIGH. The configuration shown in Figure c avoids ripple delays and their associated restrictions. The CE input signal for a given stage is formed by combining the TC signals from all the preceding stages. Note that in order to inhibit counting an enable signal must be included in each carry gate. The simple inhibit scheme of Figures a and b doesn’t apply, because the TC output of a given stage is not affected by its own CE. MODE SELECT TABLE RC TRUTH TABLE INPUTS INPUTS CE TC* CP RC OUTPUT L H X H X L X X H H MODE PL CE U/D H H L H L L X H L H X X CP X X Count Up Count Down Preset (Asyn.) No Change (Hold) * TC is generated internally L = LOW Voltage Level H = HIGH Voltage Level X = Don’t Care = LOW-to-HIGH Clock Transition = LOW Pulse FAST AND LS TTL DATA 5-344 SN54/74LS190 • SN54/74LS191 GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 74 4.5 4.75 5.0 5.0 5.5 5.25 V TA Operating Ambient Temperature Range 54 74 – 55 0 25 25 125 70 °C IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 74 4.0 8.0 mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IIH Min Parameter Typ 54 0.7 74 0.8 – 0.65 IOS Short Circuit Current (Note 1) ICC Power Supply Current – 1.5 Test Conditions V Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input LOW Voltage for All Inputs V VCC = MIN, IIN = – 18 mA 54 2.5 3.5 V 74 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table VCC = VCC MIN, VIN = VIL or VIH per Truth Table 54, 74 0.25 0.4 V IOL = 4.0 mA 74 0.35 0.5 V IOL = 8.0 mA 20 60 µA VCC = MAX, VIN = 2.7 V mA VCC = MAX, VIN = 7.0 V – 0.4 – 1.2 mA VCC = MAX, VIN = 0.4 V – 100 mA VCC = MAX 35 mA VCC = MAX Other Inputs CE Input LOW Current Other Inputs CE Unit 2.0 Input HIGH Current Other Inputs CE IIL Max 0.1 0.3 – 20 Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 5-345 SN54/74LS190 • SN54/74LS191 AC CHARACTERISTICS (TA = 25°C) Limits Symbol Parameter Min Typ 20 25 Max Unit fMAX Maximum Clock Frequency tPLH tPHL Propagation Delay, PL to Output Q 22 33 33 50 ns tPLH tPHL Data to Output Q 20 27 32 40 ns tPLH tPHL Clock to RC 13 16 20 24 ns tPLH tPHL Clock to Output Q 16 24 24 36 ns tPLH tPHL Clock to TC 28 37 42 52 ns tPLH tPHL U / D to RC 30 30 45 45 ns tPLH tPHL U / D to TC 21 22 33 33 ns tPLH tPHL CE to RC 21 22 33 33 ns Max Unit Test Conditions MHz VCC = 5.0 V CL = 15 pF AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol Parameter Min Typ tW CP Pulse Width 25 ns tW PL Pulse Width 35 ns ts Data Setup Time 20 ns th Data Hold Time 5.0 ns trec Recovery Time 40 ns Test Conditions VCC = 5.0 V DEFINITIONS OF TERMS SETUP TIME (ts) is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW-to-HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) is defined as the minimum time following the clock transition from LOW-to-HIGH that the logic level must be maintained at the input in order to ensure continued recogni- tion. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOWto-HIGH and still be recognized. RECOVERY TIME (trec) is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW-to-HIGH in order to recognize and transfer HIGH data to the Q outputs. FAST AND LS TTL DATA 5-346 SN54/74LS190 • SN54/74LS191 DIRECTION CONTROL U/D RC U/D RC U/D ENABLE CE CE CE CLOCK CP CP CP RC Figure a. n-Stage Counter Using Ripple Clock DIRECTION CONTROL U/D ENABLE RC U/D RC U/D CE CE CE CP CP CP RC CLOCK Figure b. Synchronous n-Stage Counter Using Ripple Carry / Borrow DIRECTION CONTROL ENABLE U/D U/D U/D CE CE CE CP TC CP TC CP TC CLOCK Figure c. Synchronous n-Stage Counter with Parallel Gated Carry / Borrow FAST AND LS TTL DATA 5-347 SN54/74LS190 • SN54/74LS191 AC WAVEFORMS % % % Figure 2 ! % % % ! % Figure 1 ! % % % ! NOTE: PL = LOW Figure 3 Figure 4 ! % % %$ %# % %$ ! * The shaded areas indicate when the input is permitted * to change for predictable output performance Figure 5 % % % % Figure 6 %$ %$ % ' "! & Figure 7 Figure 8 FAST AND LS TTL DATA 5-348 % Case 751B-03 D Suffix 16-Pin Plastic SO-16 -A- "! ! " " ! " # 1 %# ) ! !" $ !" 8 C -T- D M K " ! #! J F ! Case 648-08 N Suffix 16-Pin Plastic R X 45° G " ! ) #! P ! " " 9 -B- ! 16 & ! ! ° ° ° ° ( ( ( ( "! ! " " ! ! ' " " ! ' ! " # & -A- 16 9 1 8 ! ! $ ! B # ) " ! " # ) !" $ !" ) F L C S -T- K H G M J D " Case 620-09 J Suffix 16-Pin Ceramic Dual In-Line -A- ! ! ! ! ° ° ° ° "! ! " 16 " ) " L K M N J G D " $ " $ ! " " ! ! FAST AND LS TTL DATA 5-349 & # ) !" $ !" ) -T $ " " C F & 8 E ! ! ! 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