MC100EP210S 2.5V1:5 Dual Differential LVDS Compatible Clock Driver The MC100EP210S is a low skew 1–to–5 dual differential driver, designed with LVDS clock distribution in mind. The LVDS or LVPECL input signals are differential and the signal is fanned out to five identical differential LVDS outputs. The EP210S specifically guarantees low output–to–output skew. Optimal design, layout, and processing minimize skew within a device and from device to device. Two internal 50 resistors are provided across the inputs. For LVDS inputs, VTA and VTB pins should be unconnected. For LVPECL inputs, VTA and VTB pins should be connected to the VTT (VCC–2.0 V) supply. Designers can take advantage of the EP210S performance to distribute low skew LVDS clocks across the backplane or the board. Special considerations are required for differential inputs under No Signal conditions to prevent instability. • • • • • • • • http://onsemi.com MARKING DIAGRAM* MC100 EP210S LQFP–32 FA SUFFIX CASE 873A AWLYYWW 32 1 A WL YY WW 20 ps Typical Output–to–Output Skew 85 ps Typical Device–to–Device Skew = Assembly Location = Wafer Lot = Year = Work Week 550 ps Typical Propagation Delay The 100 Series Contains Temperature Compensation *For additional information, refer to Application Note AND8002/D Maximum Frequency > 1 GHz Typical Operating Range: VCC = 2.375 V to 2.625 V with VEE = 0 V Internal 50 Input Termination Resistors LVDS Input/Output Compatible ORDERING INFORMATION Semiconductor Components Industries, LLC, 2002 May, 2002 – Rev. 5 1 Device Package Shipping MC100EP210SFA LQFP–32 250 Units/Tray MC100EP210SFAR2 LQFP–32 2000 Tape & Reel Publication Order Number: MC100EP210S/D MC100EP210S Qa3 Qa3 Qa4 Qa4 Qb0 Qb0 Qb1 Qb1 24 23 22 21 20 19 18 17 VCC 25 16 VCC Qa2 26 15 Qb2 Qa2 27 14 Qb2 Qa1 28 13 Qb3 Qa1 29 Qb3 VTA 50 Ω Termination Resistors MC100EP210S PIN DESCRIPTION 12 Qa0 31 10 Qb4 VCC 32 9 VCC 1 2 VEE VTA 3 4 5 6 7 8 VTB CLKb Qb4 CLKb 11 CLKa 30 CLKa Qa0 VEE PIN FUNCTION CLKn, CLKn LVDS, LVPECL CLK Inputs Qn0:4, Qn0:4 LVDS Outputs VTB 50 Ω Termination Resistors VCC Positive Supply VEE Ground Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. 32–Lead LQFP Pinout (Top View) VTA 50 VTB Qa0 Qa0 50 50 Qb0 Qb0 50 Qa1 CLKa Qa1 CLKa Qa2 Qb1 CLKb Qb1 CLKb Qb2 Qa2 Qb2 Qa3 Qb3 Qa3 Qb3 Qa4 Qb4 Qa4 Qb4 Figure 2. Logic Diagram ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor N/A Internal Input Pullup Resistor N/A ESD Protection Human Body Model Machine Model Charged Device Model Moisture Sensitivity (Note 1) > 2 kV > 100 V > 2 kV Level 2 Flammability Rating Oxygen Index UL–94 code V–0 A 1/8″ 28 to 34 Transistor Count 461 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, refer to Application Note AND8003/D. http://onsemi.com 2 MC100EP210S MAXIMUM RATINGS (Note 2) Parameter Symbol Condition 1 Condition 2 Rating Units 6 V –6 V VCC Power Supply VEE = 0 V VEE Power Supply (GND) VCC = 2.5 V VI LVDS LVPECL Input Voltage LVDS, VEE = 0 V Iout Output Current Continuous Surge TA Operating Temperature Range Tstg Storage Temperature Range –65 to +150 °C θJA Thermal Resistance (Junction–to–Ambient) 0 LFPM 500 LFPM 32 LQFP 32 LQFP 80 55 °C/W °C/W θJC Thermal Resistance (Junction–to–Case) std bd 32 LQFP 12 to 17 °C/W Tsol Wave Solder < 2 to 3 sec @ 248°C 265 °C VI ≤ VCC 6 V 50 100 mA mA –40 to +85 °C 2. Maximum Ratings are those values beyond which device damage may occur. DC CHARACTERISTICS VCC = 2.5 V, VEE = 0 V (Note 3) –40°C Symbol Characteristic Min 25°C Typ Max 150 200 Min 85°C Typ Max 150 200 Min Typ Max Unit 150 200 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 4) 1250 1400 1550 1250 1400 1550 1250 1400 1550 mV VOL Output LOW Voltage (Note 4) 800 950 1100 800 950 1100 800 950 1100 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 5) 1.2 2.5 1.2 2.5 1.2 2.5 V RT Internal Termination Resistor 43 57 43 57 43 57 IIH Input HIGH Current 150 µA IIL Input LOW Current 50 150 CLK CLK 150 0.5 –150 0.5 –150 µA 0.5 –150 NOTE: 100EP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 3. Input and output parameters vary 1:1 with VCC. 4. All loading with 100 Ω across LVDS differential outputs. 5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. AC CHARACTERISTICS VCC = 2.375 to 2.625 V, VEE = 0 V (Note 6) –40°C Symbol fmaxLVDS/ LVPECL Characteristic Min Maximum Frequency (See Figure 3. Fmax/JITTER) tPLH tPHL Propagation Delay tskew Typ 25°C Max 425 Typ Max Min >1 525 625 Within–Device Skew (Note 7) Device–to–Device Skew (Note 8) Duty Cycle Skew (Note 9) 20 85 80 tJITTER Cycle–to–Cycle Jitter (See Figure 3. Fmax/JITTER) VPP Minimum Input Swing tr/tf Output Rise/Fall Time (20%–80%) 6. 7. 8. 9. Min >1 85°C 450 Typ Max >1 550 650 25 160 100 20 85 80 .2 <1 150 800 1200 50 130 200 475 Unit GHz 575 675 ps 25 160 100 20 85 80 35 160 100 ps .2 <1 .2 <1 ps 150 800 1200 150 800 1200 mV 75 150 225 80 160 230 ps Measured with 400 mV source, 50% duty cycle clock source. All loading with 100 Ω across differential outputs. Skew is measured between outputs under identical transitions of similar paths through a device. Device–to–Device skew for identical transitions at identical VCC levels. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output. http://onsemi.com 3 MC100EP210S 450 9 Simulated 8 350 7 300 6 250 5 200 4 150 3 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ 100 ÉÉ ÉÉ ÉÉ 2 (JITTER) 50 1 0 0 200 400 600 800 1000 1200 1400 FREQUENCY (MHz) Figure 3. Fmax/Jitter Q Driver Device D Recceiver Device 100 Ω D Q Figure 4. Typical Termination for Output Driver and Device Evaluation http://onsemi.com 4 JITTEROUT ps (RMS) VOUTpp (mV) 400 MC100EP210S PACKAGE DIMENSIONS A 32 –T–, –U–, –Z– LQFP FA SUFFIX 32–LEAD PLASTIC PACKAGE CASE 873A–02 ISSUE A 4X A1 0.20 (0.008) AB T-U Z 25 1 –U– –T– B V AE P B1 DETAIL Y 17 8 AE DETAIL Y 9 4X –Z– 9 V1 0.20 (0.008) AC T-U Z S1 S DETAIL AD G –AB– 0.10 (0.004) AC AC T-U Z –AC– BASE METAL ÉÉ ÉÉ ÉÉ ÉÉ F 8X M R J M N D 0.20 (0.008) SEATING PLANE SECTION AE–AE W K X DETAIL AD Q GAUGE PLANE H 0.250 (0.010) C E http://onsemi.com 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12 REF 0.090 0.160 0.400 BSC 1 5 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12 REF 0.004 0.006 0.016 BSC 1 5 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF MC100EP210S Notes http://onsemi.com 6 MC100EP210S Notes http://onsemi.com 7 MC100EP210S ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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