SDRAM 64Mb H-die (x32) CMOS SDRAM 64Mb H-die (x32) SDRAM Specification Revision 1.4 August 2004 *Samsung Electronics reserves the right to change products or specification without notice. -1- Rev. 1.4 August 2004 SDRAM 64Mb H-die (x32) CMOS SDRAM Revision History Revision 0.0 (June, 2003) - Target spec First release. Revision 0.1 (July, 2003) - Delete speed 4.5ns. Revision 0.2 (September, 2003) - Preliminary spec release. Revision 1.0 (November, 2003) - Final spec release. Revision 1.1 (December, 2003) - Corrected typo. Revision 1.2 (December, 2003) - Modified load cap 50pF -> 30pF & Typo. Revision 1.3 (February, 2004) - Corrected typo. Revision 1.4 (August, 2004) - Corrected typo. -2- Rev. 1.4 August 2004 SDRAM 64Mb H-die (x32) CMOS SDRAM 512K x 32Bit x 4 Banks SDRAM FEATURES • JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed address • Four banks operation • MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock. • Burst read single-bit write operation • DQM for masking • Auto & self refresh • 64ms refresh period(4K Cycle) GENERAL DESCRIPTION The K4S643232H is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. Ordering Information Part No. Orgainization K4S643232H-TC/L70 Max Freq. Interface Package LVTTL 86pin TSOP(II) 143MHz(CL=3) K4S643232H-TC/L60 2Mb x 32 166MHz(CL=3) K4S643232H-TC/L55 183MHz(CL=3) K4S643232H-TC/L50 200MHz(CL=3) Organization Row Address Column Address 2Mx32 A0~A10 A0-A7 Row & Column address configuration -3- Rev. 1.4 August 2004 SDRAM 64Mb H-die (x32) CMOS SDRAM Package Physical Dimension 0~8°C #43 10.16 0.400 0.125+0.075 -0.035 0.005+0.003 -0.001 22.62 MAX 0.891 22.22 0.875 0.10 MAX 0.004 ( 0.61 ) 0.024 +0.07 ± 0.10 0.21 0.008 ± 0.004 0.20 -0.03 0.0079 +0.003 -0.001 0.45~0.75 0.018~0.030 #1 ± 0.05 ± 0.002 1.00 0.039 ± 0.10 ± 0.004 ( 0.50 ) 0.020 #44 11.76±0.20 0.463±0.008 #86 0.25 TYP 0.010 1.20 MAX 0.047 0.05 MIN 0.002 0.50 0.0197 86Pin TSOP(II) Package Dimension -4- Rev. 1.4 August 2004 SDRAM 64Mb H-die (x32) CMOS SDRAM FUNCTIONAL BLOCK DIAGRAM I/O Control Data Input Register LWE LDQM Bank Select 512K x 32 512K x 32 Output Buffer 512K x 32 Sense AMP Row Decoder ADD Row Buffer Refresh Counter DQi Column Decoder Col. Buffer LCBR LRAS Address Register CLK 512K x 32 Latency & Burst Length LCKE Programming Register LRAS LCBR LCAS LWE LWCBR LDQM Timing Register CLK CKE CS RAS CAS WE -5- DQM Rev. 1.4 August 2004 SDRAM 64Mb H-die (x32) CMOS SDRAM PIN CONFIGURATION (Top view) VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 N.C VDD DQM0 WE CAS RAS CS N.C BA0 BA1 A10/AP A0 A1 A2 DQM2 VDD N.C DQ16 VSSQ DQ17 DQ18 VDDQ DQ19 DQ20 VSSQ DQ21 DQ22 VDDQ DQ23 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 -6- VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 N.C VSS DQM1 N.C N.C CLK CKE A9 A8 A7 A6 A5 A4 A3 DQM3 VSS N.C DQ31 VDDQ DQ30 DQ29 VSSQ DQ28 DQ27 VDDQ DQ26 DQ25 VSSQ DQ24 VSS 86Pin TSOP (II) (400mil x 875mil) (0.5 mm Pin pitch) Rev. 1.4 August 2004 SDRAM 64Mb H-die (x32) CMOS SDRAM PIN FUNCTION DESCRIPTION Pin Name Input Function CLK System clock Active on the positive going edge to sample all inputs. CS Chip select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM. CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disables input buffers for power down mode. A0 ~ A10 Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA10, Column address : CA0 ~ CA7 BA0,1 Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. WE Write enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. DQM0 ~ 3 Data input/output mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. DQ0 ~ 31 Data input/output Data inputs/outputs are multiplexed on the same pins. VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic. VDDQ/VSSQ Data output power/ground Isolated power supply and ground for the output buffers to provide improved noise immunity. NC No Connection This pin is recommended to be left No connection on the device. -7- Rev. 1.4 August 2004 SDRAM 64Mb H-die (x32) CMOS SDRAM ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V TSTG -55 ~ +150 °C Power dissipation PD 1 W Short circuit current IOS 50 mA Storage temperature Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C) Parameter Symbol Min Typ Max Unit VDD, VDDQ 3.0 3.3 3.6 V Input logic high voltage VIH 2.0 3.0 VDDQ+0.3 V 1 Input logic low voltage VIL -0.3 0 0.8 V 2 Output logic high voltage VOH 2.4 - - V IOH = -2mA Output logic low voltage VOL - - 0.4 V IOL = 2mA ILI -10 - 10 uA 3 Supply voltage Input leakage current Note Notes : 1. VIH (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ, Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV) Pin Symbol Min Max Unit CCLK - 4 pF CIN - 4.5 pF Address CADD - 4.5 pF DQ0 ~ DQ31 COUT - 6.5 pF Clock RAS, CAS, WE, CS, CKE, DQM -8- Rev. 1.4 August 2004 SDRAM 64Mb H-die (x32) CMOS SDRAM DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70°C Parameter Operating Current (One Bank Active) Symbol ICC1 Test Condition CAS Latency Burst Length =1 tRC ≥ tRC(min), tCC ≥ tCC(min), Io = 0mA 3 Speed 50 55 60 70 140 140 130 130 2 CKE ≤ VIL(max), tCC = 10ns 2 ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞ 2 ICC2N CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 30ns 12 ICC2NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 7 ICC3P CKE ≤ VIL(max), tCC = 10ns 4 ICC3PS CKE ≤ VIL(max), tCC = ∞ 4 ICC3N CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 30ns 40 ICC3NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 35 Operating Current (Burst Mode) ICC4 Io = 0 mA, Page Burst All bank Activated, tCCD = tCCD(min) Refresh Current ICC5 Precharge Standby Current in non power-down mode Active Standby Current in power-down mode Active Standby Current in non power-down mode (One Bank Active) Self Refresh Current ICC6 Note mA 2 110 ICC2P Precharge Standby Current in power-down mode Unit mA mA mA mA 3 CKE ≤ 0.2V 160 2 3 tRC ≥ tRC(min) 170 150 140 mA 2 mA 3 120 150 150 140 120 2 120 C 2 mA 4 L 450 uA 5 Notes : 1. Unless otherwise notes, Input level is CMOS(VIH/VIL=VDDQ/VSSQ) in LVTTL. 2. Measured with outputs open. 3. Refresh period is 64ms. 4. K4S643232H-TC 5. K4S643232H-TL -9- Rev. 1.4 August 2004 SDRAM 64Mb H-die (x32) CMOS SDRAM AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C) Parameter Value Unit 2.4/0.4 V 1.4 V tr/tf = 1/1 ns 1.4 V AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition See Fig. 2 3.3V Vtt = 1.4V 1200Ω 50Ω VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output Output Z0 = 50Ω 30pF 870Ω 30pF (Fig. 1) DC output load circuit (Fig. 2) AC output load circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Symbol CAS CLK cycle time CAS 50 Min 55 Max 5 Min Min 5.5 1000 tCC 60 Max 10 70 Max 6 1000 Min Note 1000 ns 1 7 1000 10 Unit Max 10 10 Row active to row active delay tRRD(min) CLK 1 RAS to CAS delay tRCD(min) 3 2 3 2 3 2 3 2 CLK 1 Row precharge time tRP(min) 3 2 3 2 3 2 3 2 CLK 1 tRAS(min) 8 5 7 5 7 5 7 5 CLK 1 Row active time 2 100 tRAS(max) us Row cycle time tRC(min) CLK 1 Last data in to row precharge tRDL(min) 2 CLK 2 Last data in to new col.address delay tCDL(min) 1 CLK 2 Last data in to burst stop tBDL(min) 1 CLK 2 Col. address to col. address delay tCCD(min) 1 CLK 3 Mode Register Set cycle time tMRS(min) 2 CLK Number of valid output data 11 7 10 7 10 CAS Latency=3 2 CAS Latency=2 1 7 10 7 ea 4 Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. Refer to the following ns-unit based AC table. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. - 10 Rev. 1.4 August 2004 SDRAM 64Mb H-die (x32) CMOS SDRAM AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter 50 Symbol Min CLK cycle time CAS Latency=3 tCC CAS Latency=2 CLK to valid output delay CAS Latency=3 CAS Latency=3 CLK low pulse width CAS Latency=3 Input setup time tSAC tOH CLK high pulse width tCH CAS Latency=2 tCL CAS Latency=2 CAS Latency=3 Max 1000 Min 5.5 10 CAS Latency=2 Output data hold time 5 55 tSS CAS Latency=2 60 Max 1000 10 Min 6 70 Max 1000 10 Min 7 Unit Note ns 1 ns 1, 2 ns 2 ns 3 ns 3 ns 3 Max 1000 10 - 4.5 - 5.0 - 5.5 - 5.5 - 6 - 6 - 6 - 6 2 - 2 - 2 - 2 - 2 - 2 - 2.5 - 3 - 3 - 3 - 3 - 3 - 2 - 2 - 2.5 - 3 - 3 - 3 - 3 - 3 - 1.5 - 1.5 - 1.5 - 1.75 - 2.5 - 2.5 - 2.5 - 2.5 - Input hold time tSH 1 - 1 - 1 - 1 - ns 3 CLK to output in Low-Z tSLZ 1 - 1 - 1 - 1 - ns 2 - 4.5 - 5.0 - 5.5 - 5.5 ns - - 6 - 6 - 6 - 6 CLK to output in Hi-Z CAS latency=3 CAS latency=2 tSHZ Note : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf)=1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. - 11 Rev. 1.4 August 2004 SDRAM 64Mb H-die (x32) CMOS SDRAM SIMPLIFIED TRUTH TABLE Command Register Mode register set Auto refresh Refresh CKEn-1 CKEn CS RAS CAS WE DQM H X L L L L X OP code L L L H X X H Entry Self refresh Exit H BA0,1 L H L H H H H X X X X L H H X V Read & column address Auto precharge disable H X L H L H X V Write & column address Auto precharge disable Auto precharge enable X L H L L X H X L H H L X H X L L H L X H L Exit L H Entry H L Precharge power down mode Exit L Column address V L Column address H All banks Entry L DQM H No operation command H H H X X X L V V V X X X X H X X X L H H H H X X X L V V V X X H X X X L H H H 3 Row address H Auto precharge enable Clock suspend or active power down 3 3 L Bank selection 1,2 X X H Note 3 H Precharge A11, A9 ~ A 0 L Bank active & row addr. Burst Stop A10/AP X V L X H 4 4,5 4 4,5 6 X X X X X X X V X X X 7 (V=Valid, X=Don′t care, H=Logic high, L=Logic low) Notes :1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) - 12 Rev. 1.4 August 2004