SAMSUNG K4S1G0732B-TC75

SDRAM stacked 1Gb B-die (x8)
CMOS SDRAM
stacked 1Gb B-die SDRAM Specification
Revision 1.1
February 2004
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.1 February 2004
SDRAM stacked 1Gb B-die (x8)
CMOS SDRAM
Revision History
Revision 1.0 (August, 2003)
- First release.
Revision 1.1 (February, 2004)
-Corrected typo.
Rev. 1.1 February 2004
SDRAM stacked 1Gb B-die (x8)
CMOS SDRAM
32M x 8Bit x 4 Banks Synchronous DRAM
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (8K Cycle)
GENERAL DESCRIPTION
The K4S1G0732B is 1,073,741,824bits synchronous high data rate Dynamic RAM organized as 4 x 33,554,432 words by 8 bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system
clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable
latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
Ordering Information
Part No.
Orgainization
Max Freq.
Interface
Package
K4S1G0732B-TC75
st.128Mb x8
133MHz
LVTTL
54pin TSOP(II)
Organization
Row Address
Column Address
st.128Mx8
A0~A12
A0-A9, A11
Row & Column address configuration
Rev. 1.1 February 2004
SDRAM stacked 1Gb B-die (x8)
CMOS SDRAM
Package Physical Dimension
Unit : Millimeters
0~8°C
0.50
#27
10.16
#1
11.76±0.20
#28
0.40~0.60
0.25 TYP
#54
0.125+0.075
-0.035
22.53 MAX
22.22
± 0.10
2.54 MAX
0.10 MAX
0.05 MIN
0.71
0.25~0.40
0.80
54Pin TSOP2 Stack Package Dimension
FUNCTIONAL BLOCK DIAGRAM
CLK,CAS,RAS
/WE,DQM
/CS1,CKE1
64Mx8
64Mx8
/CS0,CKE0
DQ0 ~ DQ7
A0~A12,BA0,BA1
Rev. 1.1 February 2004
SDRAM stacked 1Gb B-die (x8)
CMOS SDRAM
PIN CONFIGURATION (Top view)
VDD
DQ0
VDDQ
N.C
DQ1
VSSQ
N.C
DQ2
VDDQ
N.C
DQ3
VSSQ
N.C
VDD
CS1
WE
CAS
RAS
CS0
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ7
VSSQ
N.C
DQ6
VDDQ
N.C
DQ5
VSSQ
N.C
DQ4
VDDQ
N.C
VSS
CKE1
DQM
CLK
CKE0
A12
A11
A9
A8
A7
A6
A5
A4
VSS
54Pin TSOP
(400mil x 875mil)
(0.8 mm Pin pitch)
PIN FUNCTION DESCRIPTION
Pin
CLK
Name
Input Function
System clock
Active on the positive going edge to sample all inputs.
CS0~1
Chip select
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE0~1
Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
A0 ~ A12
Address
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12, Column address : CA0 ~ CA9, CA11
BA0 ~ BA1
Bank select address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS
Column address strobe
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE
Write enable
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQM
Data input/output mask
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
DQ0 ~7
Data input/output
Data inputs/outputs are multiplexed on the same pins.
VDD/VSS
Power supply/ground
Power and ground for the input buffers and the core logic.
VDDQ/VSSQ
Data output power/ground
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
Rev. 1.1 February 2004
SDRAM stacked 1Gb B-die (x8)
CMOS SDRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
VIN, VOUT
-1.0 ~ 4.6
V
Voltage on VDD supply relative to Vss
VDD, VDDQ
-1.0 ~ 4.6
V
TSTG
-55 ~ +150
°C
Power dissipation
PD
2
W
Short circuit current
IOS
50
mA
Storage temperature
Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
Parameter
Symbol
Min
Typ
Max
Unit
VDD, VDDQ
3.0
3.3
3.6
V
Input logic high voltage
VIH
2.0
3.0
VDD+0.3
V
1
Input logic low voltage
VIL
-0.3
0
0.8
V
2
Output logic high voltage
VOH
2.4
-
-
V
IOH = -2mA
Output logic low voltage
VOL
-
-
0.4
V
IOL = 2mA
ILI
-10
-
10
uA
3
Supply voltage
Input leakage current
Note
Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
(VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)
CAPACITANCE
Pin
Clock
RAS, CAS, WE, DQM
Address
Symbol
Min
Max
Unit
CCLK
5.0
9.0
pF
CIN
5.0
10.0
pF
CADD
5.0
10.0
pF
CS#, CKE#
Ccs
2.5
6.5
pF
DQ0 ~ DQ7
COUT
8.0
14.0
pF
Note
Rev. 1.1 February 2004
SDRAM stacked 1Gb B-die (x8)
CMOS SDRAM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter
Symbol
Test Condition
Version
Unit
Note
mA
1
-75
Operating current
(One bank active)
Precharge standby current in
power-down mode
ICC1
ICC2P
ICC2PS
ICC2N
Precharge standby current in
non power-down mode
ICC2NS
Active standby current in
power-down mode
Active standby current in
non power-down mode
(One bank active)
ICC3P
ICC3PS
ICC3N
ICC3NS
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
110
CKE ≤ VIL(max), tCC = 10ns
4
CKE & CLK ≤ VIL(max), tCC = ∞
4
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
40
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
20
CKE ≤ VIL(max), tCC = 10ns
8
CKE & CLK ≤ VIL(max), tCC = ∞
8
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
50
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
35
mA
mA
mA
mA
Operating current
(Burst mode)
ICC4
IO = 0 mA
Page burst
4banks Activated
tCCD = 2CLKs
130
mA
1
Refresh current
ICC5
tRC ≥ tRC(min)
220
mA
2
Self refresh current
ICC6
CKE ≤ 0.2V
12
mA
3
Notes : 1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S1G0732B-TC75
4. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).
Rev. 1.1 February 2004
SDRAM stacked 1Gb B-die (x8)
CMOS SDRAM
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
Unit
2.4/0.4
V
1.4
V
tr/tf = 1/1
ns
1.4
V
See Fig. 2
3.3V
Vtt = 1.4V
1200Ω
50Ω
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
870Ω
Output
Z0 = 50Ω
50pF
50pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
Version
Unit
Note
-75
Row active to row active delay
tRRD(min)
15
ns
1
RAS to CAS delay
tRCD(min)
20
ns
1
Row precharge time
tRP(min)
20
ns
1
Row active time
tRAS(min)
45
ns
1
tRAS(max)
100
us
Row cycle time
tRC(min)
65
ns
1
Last data in to row precharge
tRDL(min)
2
CLK
2
Last data in to Active delay
tDAL(min)
2 CLK + 20 ns
-
Last data in to new col. address delay
tCDL(min)
1
CLK
2
Last data in to burst stop
tBDL(min)
1
CLK
2
Col. address to col. address delay
tCCD(min)
1
CLK
3
ea
4
Number of valid output data
Notes :
CAS latency=3
2
CAS latency=2
1
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Rev. 1.1 February 2004
SDRAM stacked 1Gb B-die (x8)
CMOS SDRAM
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
-75
Symbol
Min
CLK cycle time
CAS latency=3
7.5
tCC
CAS latency=2
CLK to valid
output delay
Output data
hold time
CAS latency=3
Note
1000
ns
1
ns
1,2
ns
2
10
5.4
tSAC
CAS latency=2
CAS latency=3
Unit
Max
6
3
tOH
CAS latency=2
3
CLK high pulse width
tCH
2.5
ns
3
CLK low pulse width
tCL
2.5
ns
3
Input setup time
tSS
1.5
ns
3
Input hold time
tSH
0.8
ns
3
CLK to output in Low-Z
tSLZ
1
ns
2
CLK to output
in Hi-Z
CAS latency=3
5.4
tSHZ
CAS latency=2
ns
5.4
Notes : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
DQ BUFFER OUTPUT DRIVE CHARACTERISTICS
Parameter
Symbol
Condition
Min
Output rise time
trh
Measure in linear
region : 1.2V ~ 1.8V
Output fall time
tfh
Output rise time
Output fall time
Typ
Max
Unit
Notes
1.37
4.37
Volts/ns
3
Measure in linear
region : 1.2V ~ 1.8V
1.30
3.8
Volts/ns
3
trh
Measure in linear
region : 1.2V ~ 1.8V
2.8
3.9
5.6
Volts/ns
1,2
tfh
Measure in linear
region : 1.2V ~ 1.8V
2.0
2.9
5.0
Volts/ns
1,2
Notes : 1. Rise time specification based on 0pF + 50 Ω to VSS, use these values to design to.
2. Fall time specification based on 0pF + 50 Ω to VDD, use these values to design to.
3. Measured into 50pF only, use these values to characterize to.
4. All measurements done with respect to VSS.
Rev. 1.1 February 2004
SDRAM stacked 1Gb B-die (x8)
CMOS SDRAM
IBIS SPECIFICATION
66MHz and 100/133MHz Pull-up
0
IOH Characteristics (Pull-up)
(V)
3.45
3.3
3.0
2.6
2.4
2.0
1.8
1.65
1.5
1.4
1.0
0.0
0.0
-21.1
-34.1
-58.7
-67.3
-73.0
-77.9
-80.8
-88.6
-93.0
100MHz
133Mhz
Max
I (mA)
-2.4
-27.3
-74.1
-129.2
-153.3
-197.0
-226.2
-248.0
-269.7
-284.3
-344.5
-502.4
0.5
1
1.5
2
2.5
3
3.5
0
66MHz
Min
-100
I (mA)
-200
-0.7
-7.5
-13.3
-27.5
-35.5
-41.1
-47.9
-52.4
-72.5
-93.0
mA
Voltage
100MHz
133MHz
Min
I (mA)
-300
-400
-500
-600
Voltage
IOH Min (100/133MHz)
IOH Min (66MHz)
IOH Max (66 and 100/133MHz)
66MHz and 100MHz Pull-down
IOL Characteristics (Pull-down)
(V)
0.0
0.4
0.65
0.85
1.0
1.4
1.5
1.65
1.8
1.95
3.0
3.45
100MHz
133MHz
Min
I (mA)
0.0
27.5
41.8
51.6
58.0
70.7
72.9
75.4
77.0
77.6
80.3
81.4
100MHz
133MHz
Max
I (mA)
0.0
70.2
107.5
133.8
151.2
187.7
194.4
202.5
208.6
212.0
219.6
222.6
250
66MHz
Min
I (mA)
0.0
17.7
26.9
33.3
37.6
46.6
48.0
49.5
50.7
51.5
54.2
54.9
200
150
mA
Voltage
100
50
0
0
0.5
1
1.5
2
2.5
3
3.5
Voltage
IOL Min (100MHz)
IOL Min (66MHz)
IOL Max (100MHz)
Rev. 1.1 February 2004
SDRAM stacked 1Gb B-die (x8)
CMOS SDRAM
Minimum VDD clamp current
(Referenced to VDD)
VDD Clamp @ CLK, CKE, CS, DQM & DQ
I (mA)
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.23
1.34
3.02
5.06
7.35
9.83
12.48
15.30
18.31
20
15
mA
VDD (V)
0.0
0.2
0.4
0.6
0.7
0.8
0.9
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
10
5
0
0
1
2
3
Voltage
I (mA)
Minimum VSS clamp current
VSS Clamp @ CLK, CKE, CS, DQM & DQ
I (mA)
-57.23
-45.77
-38.26
-31.22
-24.58
-18.37
-12.56
-7.57
-3.37
-1.75
-0.58
-0.05
0.0
0.0
0.0
0.0
-3
-2
-1
0
0
-10
-20
mA
VSS (V)
-2.6
-2.4
-2.2
-2.0
-1.8
-1.6
-1.4
-1.2
-1.0
-0.9
-0.8
-0.7
-0.6
-0.4
-0.2
0.0
-30
-40
-50
-60
Voltage
I (mA)
Rev. 1.1 February 2004
SDRAM stacked 1Gb B-die (x8)
CMOS SDRAM
SIMPLIFIED TRUTH TABLE
Command
Register
Mode register set
Auto refresh
Refresh
Entry
Self
refresh
(V=Valid, X=Don't care, H=Logic high, L=Logic low)
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
H
X
L
L
L
L
X
OP code
L
L
L
H
X
X
X
X
H
H
L
L
H
H
H
H
X
X
X
X
L
L
H
H
X
V
H
X
L
H
L
H
X
V
H
X
L
H
L
L
X
V
H
X
L
H
H
L
X
H
X
L
L
H
L
X
Entry
H
L
H
X
X
X
L
V
V
V
Exit
L
H
X
X
X
X
Entry
H
L
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
L
H
Bank active & row addr.
H
Read &
column address
Write &
column address
Exit
Auto precharge disable
Auto precharge enable
Auto precharge disable
Auto precharge enable
Burst stop
Precharge
Bank selection
All banks
Clock suspend or
active power down
Precharge power down mode
Exit
DQM
No operation command
BA0,1
L
H
H
H
X
X
H
X
X
X
L
H
H
H
X
A10/AP
A0 ~ A9
A11, A12
Note
1,2
3
3
3
3
Row address
L
Column
address
H
L
Column
address
H
X
V
L
X
H
4
4,5
4
4,5
6
X
X
X
X
X
X
V
X
X
X
7
Notes : 1. OP Code : Operand code
A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Rev. 1.1 February 2004