PRELIMINARY PRELIMINARY K6R1004C1C-C/C-L, K6R1004C1C-I/C-P CMOS SRAM Document Title 256Kx4 Bit (with OE) High-Speed CMOS Static RAM(5.0V Operating). Revision History Preliminary CCPCCCRCELIMINARY Rev. No. History Draft Data Rev. 0.0 Initial release with Preliminary. Aug. 5. 1998 Preliminary Rev. 1.0 Release to Final Data Sheet. 1.1. Delete Preliminary. Mar. 3. 1999 Final Rev. 2.0 Add 10ns & Low Power Ver. Apr. 24. 2000 Final Remark The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- Revision 2.0 April 2000 PRELIMINARY PRELIMINARY K6R1004C1C-C/C-L, K6R1004C1C-I/C-P CMOS SRAM 256K x 4 Bit (with OE) High-Speed CMOS Static RAM FEATURES GENERAL DESCRIPTION • Fast Access Time 10,12,15,20ns(Max.) • Low Power Dissipation Standby (TTL) : 30mA(Max.) (CMOS) : 5mA(Max.) 0.5mA(Max.) L-Ver. only Operating K6R1004C1C-10 : 75mA(Max.) K6R1004C1C-12 : 70mA(Max.) K6R1004C1C-15 : 68mA(Max.) K6R1004C1C-20 : 65mA(Max.) • Single 5.0V±10% Power Supply • TTL Compatible Inputs and Outputs • I/O Compatible with 3.3V Device • Fully Static Operation - No Clock or Refresh required • Three State Outputs • 2V Minimum Data Retention; L-ver. only • Center Power/Ground Pin Configuration • Standard Pin Configuration : The K6R1004C1C is a 1,048,576-bit high-speed Static Random Access Memory organized as 262,144 words by 4 bits. The K6R1004C1C uses 4 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAMSUNG′s advanced CMOS process and designed for highspeed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The K6R1004C1C is packaged in a 400 mil 32-pin plastic SOJ. Preliminary CCPCCCRCELIMINARY ORDERING INFORMATION K6R1004C1C-C10/C12/C15/C20 Commercial Temp. K6R1004C1C-I10/I12/I15/I20 Industrial Temp. PIN CONFIGURATION (Top View) FUNCTIONAL BLOCK DIAGRAM A0 A1 A2 A3 A4 A5 A6 A7 A8 I/O1 ~ I/O4 Row Select Clk Gen. Data Cont. Pre-Charge Circuit Memory Array 512 Rows 512x4 Columns I/O Circuit & Column Select N.C 1 32 A17 A0 2 31 A16 A1 3 30 A15 A2 4 29 A14 A3 5 28 A13 6 27 7 26 I/O4 Vcc 8 Vss 9 24 Vcc I/O2 10 23 I/O3 WE 11 22 A12 A4 12 21 A11 A5 13 20 A10 A6 14 19 A9 A7 15 18 A8 25 Vss SOJ 17 N.C N.C 16 CLK Gen. OE CS I/O1 PIN FUNCTION A9 A10 A11 A12 A13 A14 A15 A16 A17 Pin Name A0 - A17 CS WE OE WE Write Enable CS Chip Select OE Output Enable I/O1 ~ I/O 4 -2- Pin Function Address Inputs Data Inputs/Outputs VCC Power(+5.0V) VSS Ground N.C No Connection Revision 2.0 April 2000 PRELIMINARY PRELIMINARY K6R1004C1C-C/C-L, K6R1004C1C-I/C-P CMOS SRAM ABSOLUTE MAXIMUM RATINGS* Parameter Voltage on Any Pin Relative to V SS Symbol Rating Unit VIN, VOUT -0.5 to Vcc+0.5V V VCC -0.5 to 7.0 Preliminary CCPCCCRCELIMINARY Voltage on VCC Supply Relative to VSS Power Dissipation 1 W TSTG -65 to 150 °C Commercial TA 0 to 70 °C Industrial TA -40 to 85 °C Storage Temperature Operating Temperature V Pd * Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS(TA=0 to 70°C) Symbol Min Typ Max Unit Supply Voltage Parameter VCC 4.5 5.0 5.5 V Ground VSS 0 0 0 V Input High Voltage VIH 2.2 - VCC+0.5** V Input Low Voltage VIL -0.5* - 0.8 V * VIL(Min) = -2.0V a.c (Pulse Width ≤ 8ns) for I ≤ 20mA. ** V IH(Max) = VCC + 2.0V a.c (Pulse Width ≤ 8ns) for I ≤ 20mA. DC AND OPERATING CHARACTERISTICS(TA=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified) Min Max Unit Input Leakage Current Parameter ILI VIN=VSS to VCC -2 2 µA Output Leakage Current ILO CS=VIH or OE=VIH or WE=VIL VOUT=VSS to VCC -2 2 µA Operating Current ICC Min. Cycle, 100% Duty CS=VIL, VIN=VIH or VIL, IOUT=0mA 02ns - 75 mA 12ns - 70 15ns - 68 20ns - 65 Standby Current Output Low Voltage Level Output High Voltage Level Symbol Test Conditions ISB Min. Cycle, CS=VIH ISB1 f=0MHz, CS ≥VCC-0.2V, VIN≥VCC-0.2V or VIN≤0.2V VOL IOL=8mA VOH IOH=-4mA VOH1* - 30 Normal - 5 L-Ver. - 0.5 - 0.4 V 2.4 - V - 3.95 V IOH1=-0.1mA mA * VCC=5.0V±5%, Temp.=25°C. CAPACITANCE*(TA=25°C, f=1.0MHz) Symbol Test Conditions MIN Max Unit Input/Output Capacitance Item CI/O VI/O=0V - 8 pF Input Capacitance CIN VIN=0V - 6 pF * Capacitance is sampled and not 100% tested. -3- Revision 2.0 April 2000 PRELIMINARY PRELIMINARY K6R1004C1C-C/C-L, K6R1004C1C-I/C-P CMOS SRAM AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.) TEST CONDITIONS Parameter Value Preliminary CCPCCCRCELIMINARY 3ns Input Pulse Levels 0V to 3V Input Rise and Fall Times Input and Output timing Reference Levels 1.5V Output Loads See below Output Loads(B) for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ Output Loads(A) +5.0V RL = 50Ω DOUT VL = 1.5V 480Ω DOUT 30pF* ZO = 50Ω 255Ω 5pF* * Including Scope and Jig Capacitance * Capacitive Load consists of all components of the test environment. READ CYCLE* Parameter Read Cycle Time Symbol tRC K6R1004C1C-10 K6R1004C1C-12 K6R1004C1C-15 K6R1004C1C-20 Unit Min Max Min Max Min Max Min Max 10 - 12 - 15 - 20 - ns Address Access Time tAA - 10 - 12 - 15 - 20 ns Chip Select to Output tCO - 10 - 12 - 15 - 20 ns Output Enable to Valid Output tOE - 5 - 6 - 7 - 9 ns Chip Enable to Low-Z Output tLZ 3 - 3 - 3 - 3 - ns Output Enable to Low-Z Output tOLZ 0 - 0 - 0 - 0 - ns Chip Disable to High-Z Output tHZ 0 5 0 6 0 7 0 9 ns Output Disable to High-Z Output tOHZ 0 5 0 6 0 7 0 9 ns Output Hold from Address tOH 3 - 3 - 3 - 3 - ns Chip Selection to Power Up Time tPU 0 - 0 - 0 - 0 - ns Chip Selection to Power Down- tPD - 10 - 12 - 15 - 20 ns * The above parameters are also guaranteed at industrial temperature range. -4- Revision 2.0 April 2000 PRELIMINARY PRELIMINARY K6R1004C1C-C/C-L, K6R1004C1C-I/C-P CMOS SRAM WRITE CYCLE* Symbol Parameter K6R1004C1C-10 K6R1004C1C-12 Min Max Min 12 Max K6R1004C1C-15 Min Max K6R1004C1C-20 Min Max Unit - ns - 15Preliminary 20 CCPCCCRCELIMINARY 8 9 10 - ns - 0 - 0 - 0 - ns 7 - 8 - 9 - 10 - ns 7 - 8 - 9 - 10 - ns tWP1 10 - 12 - 15 - 20 - ns Write Recovery Time tWR 0 - 0 - 0 - 0 - ns Write to Output High-Z tWHZ 0 5 0 6 0 7 0 9 ns Data to Write Time Overlap tDW 5 - 6 - 7 - 8 - ns Data Hold from Write Time tDH 0 - 0 - 0 - 0 - ns End Write to Output Low-Z tOW 3 - 3 - 3 - 3 - ns Write Cycle Time tWC 10 - Chip Select to End of Write tCW 7 Address Set-up Time tAS 0 Address Valid to End of Write tAW Write Pulse Width(OE High) tWP Write Pulse Width(OE Low) * The above parameters are also guaranteed at industrial temperature range. TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL , WE=VIH) tRC Address tAA tOH Data Out Valid Data Previous Valid Data TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tAA tCO CS tHZ(3,4,5) tOHZ tOE OE tOH tOLZ tLZ(4,5) Data out Valid Data VCC ICC Current ISB tPU tPD 50% 50% -5- Revision 2.0 April 2000 PRELIMINARY PRELIMINARY K6R1004C1C-C/C-L, K6R1004C1C-I/C-P CMOS SRAM NOTES(READ CYCLE) 1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V OH or VOL levels. 4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device. 5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS=VIL. 7. Address valid prior to coincident with CS transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. Preliminary CCPCCCRCELIMINARY TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock) tWC Address tWR(5) tAW OE tCW(3) CS tWP(2) tAS(4) WE tDW Data in High-Z tDH Valid Data tOHZ(6) High-Z(8) Data out TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed) tWC Address tAW tWR(5) tCW(3) CS tAS(4) tWP1(2) WE tDW Data in High-Z tDH Valid Data tWHZ(6) tOW High-Z(8) Data out -6- (10) (9) Revision 2.0 April 2000 PRELIMINARY PRELIMINARY K6R1004C1C-C/C-L, K6R1004C1C-I/C-P CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(3) (CS=Controlled) tWC Address Preliminary CCPCCCRCELIMINARY tAW tWR(5) tCW(3) CS tWP(2) tAS(4) WE tDW High-Z Data in Valid Data tLZ High-Z tWHZ(6) High-Z(8) High-Z Data out tDH NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. 6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10.When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. FUNCTIONAL DESCRIPTION CS WE OE Mode I/O Pin Supply Current H X X* Not Select High-Z ISB, ISB1 L H H Output Disable High-Z ICC L H L Read DOUT ICC L L X Write DIN ICC * X means Don′t Care. -7- Revision 2.0 April 2000 PRELIMINARY PRELIMINARY K6R1004C1C-C/C-L, K6R1004C1C-I/C-P CMOS SRAM DATA RETENTION CHARACTERISTICS*(TA=0 to 70°C) Parameter Symbol Test Condition VCC for Data Retention VDR CS≥VCC-0.2V Data Retention Current IDR VCC=3.0V, CS≥VCC-0.2V VIN≥VCC-0.2V or VIN≤0.2V Data Retention Set-Up Time tSDR tRDR Typ. Max. 2.0 5.5 Preliminary CCPCCCRCELIMINARY 0.4 VCC=2.0V, CS≥VCC-0.2V VIN≥VCC-0.2V or VIN≤0.2V Recovery Time Min. See Data Retention Wave form(below) - - Unit V mA 0.3 0 - - ns 5 - - ms * The above parameters are also guaranteed at industrial temperature range. Data Retention Characteristic is for L-ver only. DATA RETENTION WAVE FORM CS controlled VCC tSDR Data Retention Mode tRDR 4.5V VIH VDR CS≥VCC - 0.2V CS GND -8- Revision 2.0 April 2000 PRELIMINARY PRELIMINARY K6R1004C1C-C/C-L, K6R1004C1C-I/C-P CMOS SRAM Units:millimeters/Inches PACKAGE DIMENSIONS 32-SOJ-400 Preliminary CCPCCCRCELIMINARY #17 10.16 0.400 #32 11.18 ±0.12 0.440 ±0.005 9.40 ±0.25 0.370 ±0.010 0.20 #1 #16 0.008 0.69 MIN 0.027 21.36 MAX 0.841 20.95 ±0.12 0.825 ±0.005 ( 1.30 ) 0.051 ( 1.30 ) 0.051 ( 0.95 ) 0.0375 +0.10 -0.05 +0.004 0.017 -0.002 0.43 1.27 0.050 +0.10 -0.05 +0.004 -0.002 0.71 0.028 -9- 3.76 MAX 0.148 0.10 MAX 0.004 +0.10 -0.05 +0.004 -0.002 Revision 2.0 April 2000